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coex.c
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coex.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#include "main.h"
#include "coex.h"
#include "fw.h"
#include "ps.h"
#include "debug.h"
#include "reg.h"
static u8 rtw_coex_next_rssi_state(struct rtw_dev *rtwdev, u8 pre_state,
u8 rssi, u8 rssi_thresh)
{
struct rtw_chip_info *chip = rtwdev->chip;
u8 tol = chip->rssi_tolerance;
u8 next_state;
if (pre_state == COEX_RSSI_STATE_LOW ||
pre_state == COEX_RSSI_STATE_STAY_LOW) {
if (rssi >= (rssi_thresh + tol))
next_state = COEX_RSSI_STATE_HIGH;
else
next_state = COEX_RSSI_STATE_STAY_LOW;
} else {
if (rssi < rssi_thresh)
next_state = COEX_RSSI_STATE_LOW;
else
next_state = COEX_RSSI_STATE_STAY_HIGH;
}
return next_state;
}
static void rtw_coex_limited_tx(struct rtw_dev *rtwdev,
bool tx_limit_en, bool ampdu_limit_en)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
bool wifi_under_b_mode = false;
if (!chip->scbd_support)
return;
/* force max tx retry limit = 8 */
if (coex_stat->wl_tx_limit_en == tx_limit_en &&
coex_stat->wl_ampdu_limit_en == ampdu_limit_en)
return;
if (!coex_stat->wl_tx_limit_en) {
coex_stat->darfrc = rtw_read32(rtwdev, REG_DARFRC);
coex_stat->darfrch = rtw_read32(rtwdev, REG_DARFRCH);
coex_stat->retry_limit = rtw_read16(rtwdev, REG_RETRY_LIMIT);
}
if (!coex_stat->wl_ampdu_limit_en)
coex_stat->ampdu_max_time =
rtw_read8(rtwdev, REG_AMPDU_MAX_TIME_V1);
coex_stat->wl_tx_limit_en = tx_limit_en;
coex_stat->wl_ampdu_limit_en = ampdu_limit_en;
if (tx_limit_en) {
/* set BT polluted packet on for tx rate adaptive,
* not including tx retry broken by PTA
*/
rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_GNT_BT_AWAKE);
/* set queue life time to avoid can't reach tx retry limit
* if tx is always broken by GNT_BT
*/
rtw_write8_set(rtwdev, REG_LIFETIME_EN, 0xf);
rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x0808);
/* auto rate fallback step within 8 retries */
if (wifi_under_b_mode) {
rtw_write32(rtwdev, REG_DARFRC, 0x1000000);
rtw_write32(rtwdev, REG_DARFRCH, 0x1010101);
} else {
rtw_write32(rtwdev, REG_DARFRC, 0x1000000);
rtw_write32(rtwdev, REG_DARFRCH, 0x4030201);
}
} else {
rtw_write8_clr(rtwdev, REG_TX_HANG_CTRL, BIT_EN_GNT_BT_AWAKE);
rtw_write8_clr(rtwdev, REG_LIFETIME_EN, 0xf);
rtw_write16(rtwdev, REG_RETRY_LIMIT, coex_stat->retry_limit);
rtw_write32(rtwdev, REG_DARFRC, coex_stat->darfrc);
rtw_write32(rtwdev, REG_DARFRCH, coex_stat->darfrch);
}
if (ampdu_limit_en)
rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, 0x20);
else
rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1,
coex_stat->ampdu_max_time);
}
static void rtw_coex_limited_wl(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_coex_stat *coex_stat = &coex->stat;
bool tx_limit = false;
bool tx_agg_ctrl = false;
if (coex->under_5g ||
coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
/* no need to limit tx */
} else {
tx_limit = true;
if (coex_stat->bt_hid_exist || coex_stat->bt_hfp_exist ||
coex_stat->bt_hid_pair_num > 0)
tx_agg_ctrl = true;
}
rtw_coex_limited_tx(rtwdev, tx_limit, tx_agg_ctrl);
}
static void rtw_coex_wl_ccklock_action(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
u8 para[6] = {0};
if (coex->stop_dm)
return;
para[0] = COEX_H2C69_WL_LEAKAP;
if (coex_stat->tdma_timer_base == 3 && coex_stat->wl_slot_extend) {
para[1] = PARA1_H2C69_DIS_5MS; /* disable 5ms extend */
rtw_fw_bt_wifi_control(rtwdev, para[0], ¶[1]);
coex_stat->wl_slot_extend = false;
coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
return;
}
if (coex_stat->wl_slot_extend && coex_stat->wl_force_lps_ctrl &&
!coex_stat->wl_cck_lock_ever) {
if (coex_stat->wl_fw_dbg_info[7] <= 5)
coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND]++;
else
coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
if (coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] == 7) {
para[1] = 0x1; /* disable 5ms extend */
rtw_fw_bt_wifi_control(rtwdev, para[0], ¶[1]);
coex_stat->wl_slot_extend = false;
coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
}
} else if (!coex_stat->wl_slot_extend && coex_stat->wl_cck_lock) {
para[1] = 0x0; /* enable 5ms extend */
rtw_fw_bt_wifi_control(rtwdev, para[0], ¶[1]);
coex_stat->wl_slot_extend = true;
}
}
static void rtw_coex_wl_ccklock_detect(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
/* TODO: wait for rx_rate_change_notify implement */
coex_stat->wl_cck_lock = false;
coex_stat->wl_cck_lock_pre = false;
coex_stat->wl_cck_lock_ever = false;
}
static void rtw_coex_wl_noisy_detect(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 cnt_cck;
/* wifi noisy environment identification */
cnt_cck = dm_info->cck_ok_cnt + dm_info->cck_err_cnt;
if (!coex_stat->wl_gl_busy) {
if (cnt_cck > 250) {
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] < 5)
coex_stat->cnt_wl[COEX_CNT_WL_NOISY2]++;
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] == 5) {
coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
}
} else if (cnt_cck < 100) {
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] < 5)
coex_stat->cnt_wl[COEX_CNT_WL_NOISY0]++;
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] == 5) {
coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
}
} else {
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] < 5)
coex_stat->cnt_wl[COEX_CNT_WL_NOISY1]++;
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] == 5) {
coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
}
}
if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] == 5)
coex_stat->wl_noisy_level = 2;
else if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] == 5)
coex_stat->wl_noisy_level = 1;
else
coex_stat->wl_noisy_level = 0;
}
}
static void rtw_coex_tdma_timer_base(struct rtw_dev *rtwdev, u8 type)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
u8 para[2] = {0};
if (coex_stat->tdma_timer_base == type)
return;
coex_stat->tdma_timer_base = type;
para[0] = COEX_H2C69_TDMA_SLOT;
if (type == 3) /* 4-slot */
para[1] = PARA1_H2C69_TDMA_4SLOT; /* 4-slot */
else /* 2-slot */
para[1] = PARA1_H2C69_TDMA_2SLOT;
rtw_fw_bt_wifi_control(rtwdev, para[0], ¶[1]);
/* no 5ms_wl_slot_extend for 4-slot mode */
if (coex_stat->tdma_timer_base == 3)
rtw_coex_wl_ccklock_action(rtwdev);
}
static void rtw_coex_set_wl_pri_mask(struct rtw_dev *rtwdev, u8 bitmap,
u8 data)
{
u32 addr;
addr = REG_BT_COEX_TABLE_H + (bitmap / 8);
bitmap = bitmap % 8;
rtw_write8_mask(rtwdev, addr, BIT(bitmap), data);
}
void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
u16 val = 0x2;
if (!chip->scbd_support)
return;
val |= coex_stat->score_board;
/* for 8822b, scbd[10] is CQDDR on
* for 8822c, scbd[10] is no fix 2M
*/
if (!chip->new_scbd10_def && (bitpos & COEX_SCBD_FIX2M)) {
if (set)
val &= ~COEX_SCBD_FIX2M;
else
val |= COEX_SCBD_FIX2M;
} else {
if (set)
val |= bitpos;
else
val &= ~bitpos;
}
if (val != coex_stat->score_board) {
coex_stat->score_board = val;
val |= BIT_BT_INT_EN;
rtw_write16(rtwdev, REG_WIFI_BT_INFO, val);
}
}
EXPORT_SYMBOL(rtw_coex_write_scbd);
static u16 rtw_coex_read_scbd(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
if (!chip->scbd_support)
return 0;
return (rtw_read16(rtwdev, REG_WIFI_BT_INFO)) & ~(BIT_BT_INT_EN);
}
static void rtw_coex_check_rfk(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
u8 cnt = 0;
u32 wait_cnt;
bool btk, wlk;
if (coex_rfe->wlg_at_btg && chip->scbd_support &&
coex_stat->bt_iqk_state != 0xff) {
wait_cnt = COEX_RFK_TIMEOUT / COEX_MIN_DELAY;
do {
/* BT RFK */
btk = !!(rtw_coex_read_scbd(rtwdev) & COEX_SCBD_BT_RFK);
/* WL RFK */
wlk = !!(rtw_read8(rtwdev, REG_ARFR4) & BIT_WL_RFK);
if (!btk && !wlk)
break;
mdelay(COEX_MIN_DELAY);
} while (++cnt < wait_cnt);
if (cnt >= wait_cnt)
coex_stat->bt_iqk_state = 0xff;
}
}
static void rtw_coex_query_bt_info(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
if (coex_stat->bt_disabled)
return;
rtw_fw_query_bt_info(rtwdev);
}
static void rtw_coex_monitor_bt_enable(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_coex_dm *coex_dm = &coex->dm;
bool bt_disabled = false;
u16 score_board;
if (chip->scbd_support) {
score_board = rtw_coex_read_scbd(rtwdev);
bt_disabled = !(score_board & COEX_SCBD_ONOFF);
}
if (coex_stat->bt_disabled != bt_disabled) {
rtw_dbg(rtwdev, RTW_DBG_COEX, "coex: BT state changed (%d) -> (%d)\n",
coex_stat->bt_disabled, bt_disabled);
coex_stat->bt_disabled = bt_disabled;
coex_stat->bt_ble_scan_type = 0;
coex_dm->cur_bt_lna_lvl = 0;
}
if (!coex_stat->bt_disabled) {
coex_stat->bt_reenable = true;
ieee80211_queue_delayed_work(rtwdev->hw,
&coex->bt_reenable_work, 15 * HZ);
} else {
coex_stat->bt_mailbox_reply = false;
coex_stat->bt_reenable = false;
}
}
static void rtw_coex_update_wl_link_info(struct rtw_dev *rtwdev, u8 reason)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_traffic_stats *stats = &rtwdev->stats;
bool is_5G = false;
bool scan = false, link = false;
int i;
u8 rssi_state;
u8 rssi_step;
u8 rssi;
scan = test_bit(RTW_FLAG_SCANNING, rtwdev->flags);
coex_stat->wl_connected = !!rtwdev->sta_cnt;
coex_stat->wl_gl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
if (stats->tx_throughput > stats->rx_throughput)
coex_stat->wl_tput_dir = COEX_WL_TPUT_TX;
else
coex_stat->wl_tput_dir = COEX_WL_TPUT_RX;
if (scan || link || reason == COEX_RSN_2GCONSTART ||
reason == COEX_RSN_2GSCANSTART || reason == COEX_RSN_2GSWITCHBAND)
coex_stat->wl_linkscan_proc = true;
else
coex_stat->wl_linkscan_proc = false;
rtw_coex_wl_noisy_detect(rtwdev);
for (i = 0; i < 4; i++) {
rssi_state = coex_dm->wl_rssi_state[i];
rssi_step = chip->wl_rssi_step[i];
rssi = rtwdev->dm_info.min_rssi;
rssi_state = rtw_coex_next_rssi_state(rtwdev, rssi_state,
rssi, rssi_step);
coex_dm->wl_rssi_state[i] = rssi_state;
}
switch (reason) {
case COEX_RSN_5GSCANSTART:
case COEX_RSN_5GSWITCHBAND:
case COEX_RSN_5GCONSTART:
is_5G = true;
break;
case COEX_RSN_2GSCANSTART:
case COEX_RSN_2GSWITCHBAND:
case COEX_RSN_2GCONSTART:
is_5G = false;
break;
default:
if (rtwdev->hal.current_band_type == RTW_BAND_5G)
is_5G = true;
else
is_5G = false;
break;
}
coex->under_5g = is_5G;
}
static inline u8 *get_payload_from_coex_resp(struct sk_buff *resp)
{
struct rtw_c2h_cmd *c2h;
u32 pkt_offset;
pkt_offset = *((u32 *)resp->cb);
c2h = (struct rtw_c2h_cmd *)(resp->data + pkt_offset);
return c2h->payload;
}
void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb)
{
struct rtw_coex *coex = &rtwdev->coex;
u8 *payload = get_payload_from_coex_resp(skb);
if (payload[0] != COEX_RESP_ACK_BY_WL_FW)
return;
skb_queue_tail(&coex->queue, skb);
wake_up(&coex->wait);
}
static struct sk_buff *rtw_coex_info_request(struct rtw_dev *rtwdev,
struct rtw_coex_info_req *req)
{
struct rtw_coex *coex = &rtwdev->coex;
struct sk_buff *skb_resp = NULL;
mutex_lock(&coex->mutex);
rtw_fw_query_bt_mp_info(rtwdev, req);
if (!wait_event_timeout(coex->wait, !skb_queue_empty(&coex->queue),
COEX_REQUEST_TIMEOUT)) {
rtw_err(rtwdev, "coex request time out\n");
goto out;
}
skb_resp = skb_dequeue(&coex->queue);
if (!skb_resp) {
rtw_err(rtwdev, "failed to get coex info response\n");
goto out;
}
out:
mutex_unlock(&coex->mutex);
return skb_resp;
}
static bool rtw_coex_get_bt_scan_type(struct rtw_dev *rtwdev, u8 *scan_type)
{
struct rtw_coex_info_req req = {0};
struct sk_buff *skb;
u8 *payload;
bool ret = false;
req.op_code = BT_MP_INFO_OP_SCAN_TYPE;
skb = rtw_coex_info_request(rtwdev, &req);
if (!skb)
goto out;
payload = get_payload_from_coex_resp(skb);
*scan_type = GET_COEX_RESP_BT_SCAN_TYPE(payload);
dev_kfree_skb_any(skb);
ret = true;
out:
return ret;
}
static bool rtw_coex_set_lna_constrain_level(struct rtw_dev *rtwdev,
u8 lna_constrain_level)
{
struct rtw_coex_info_req req = {0};
struct sk_buff *skb;
bool ret = false;
req.op_code = BT_MP_INFO_OP_LNA_CONSTRAINT;
req.para1 = lna_constrain_level;
skb = rtw_coex_info_request(rtwdev, &req);
if (!skb)
goto out;
dev_kfree_skb_any(skb);
ret = true;
out:
return ret;
}
static void rtw_coex_update_bt_link_info(struct rtw_dev *rtwdev)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_chip_info *chip = rtwdev->chip;
u8 i;
u8 rssi_state;
u8 rssi_step;
u8 rssi;
/* update wl/bt rssi by btinfo */
for (i = 0; i < COEX_RSSI_STEP; i++) {
rssi_state = coex_dm->bt_rssi_state[i];
rssi_step = chip->bt_rssi_step[i];
rssi = coex_stat->bt_rssi;
rssi_state = rtw_coex_next_rssi_state(rtwdev, rssi_state,
rssi, rssi_step);
coex_dm->bt_rssi_state[i] = rssi_state;
}
for (i = 0; i < COEX_RSSI_STEP; i++) {
rssi_state = coex_dm->wl_rssi_state[i];
rssi_step = chip->wl_rssi_step[i];
rssi = rtwdev->dm_info.min_rssi;
rssi_state = rtw_coex_next_rssi_state(rtwdev, rssi_state,
rssi, rssi_step);
coex_dm->wl_rssi_state[i] = rssi_state;
}
if (coex_stat->bt_ble_scan_en &&
coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE] % 3 == 0) {
u8 scan_type;
if (rtw_coex_get_bt_scan_type(rtwdev, &scan_type)) {
coex_stat->bt_ble_scan_type = scan_type;
if ((coex_stat->bt_ble_scan_type & 0x1) == 0x1)
coex_stat->bt_init_scan = true;
else
coex_stat->bt_init_scan = false;
}
}
coex_stat->bt_profile_num = 0;
/* set link exist status */
if (!(coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION)) {
coex_stat->bt_link_exist = false;
coex_stat->bt_pan_exist = false;
coex_stat->bt_a2dp_exist = false;
coex_stat->bt_hid_exist = false;
coex_stat->bt_hfp_exist = false;
} else {
/* connection exists */
coex_stat->bt_link_exist = true;
if (coex_stat->bt_info_lb2 & COEX_INFO_FTP) {
coex_stat->bt_pan_exist = true;
coex_stat->bt_profile_num++;
} else {
coex_stat->bt_pan_exist = false;
}
if (coex_stat->bt_info_lb2 & COEX_INFO_A2DP) {
coex_stat->bt_a2dp_exist = true;
coex_stat->bt_profile_num++;
} else {
coex_stat->bt_a2dp_exist = false;
}
if (coex_stat->bt_info_lb2 & COEX_INFO_HID) {
coex_stat->bt_hid_exist = true;
coex_stat->bt_profile_num++;
} else {
coex_stat->bt_hid_exist = false;
}
if (coex_stat->bt_info_lb2 & COEX_INFO_SCO_ESCO) {
coex_stat->bt_hfp_exist = true;
coex_stat->bt_profile_num++;
} else {
coex_stat->bt_hfp_exist = false;
}
}
if (coex_stat->bt_info_lb2 & COEX_INFO_INQ_PAGE) {
coex_dm->bt_status = COEX_BTSTATUS_INQ_PAGE;
} else if (!(coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION)) {
coex_dm->bt_status = COEX_BTSTATUS_NCON_IDLE;
} else if (coex_stat->bt_info_lb2 == COEX_INFO_CONNECTION) {
coex_dm->bt_status = COEX_BTSTATUS_CON_IDLE;
} else if ((coex_stat->bt_info_lb2 & COEX_INFO_SCO_ESCO) ||
(coex_stat->bt_info_lb2 & COEX_INFO_SCO_BUSY)) {
if (coex_stat->bt_info_lb2 & COEX_INFO_ACL_BUSY)
coex_dm->bt_status = COEX_BTSTATUS_ACL_SCO_BUSY;
else
coex_dm->bt_status = COEX_BTSTATUS_SCO_BUSY;
} else if (coex_stat->bt_info_lb2 & COEX_INFO_ACL_BUSY) {
coex_dm->bt_status = COEX_BTSTATUS_ACL_BUSY;
} else {
coex_dm->bt_status = COEX_BTSTATUS_MAX;
}
coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE]++;
rtw_dbg(rtwdev, RTW_DBG_COEX, "coex: bt status(%d)\n", coex_dm->bt_status);
}
static void rtw_coex_update_wl_ch_info(struct rtw_dev *rtwdev, u8 type)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_coex_dm *coex_dm = &rtwdev->coex.dm;
struct rtw_efuse *efuse = &rtwdev->efuse;
u8 link = 0;
u8 center_chan = 0;
u8 bw;
int i;
bw = rtwdev->hal.current_band_width;
if (type != COEX_MEDIA_DISCONNECT)
center_chan = rtwdev->hal.current_channel;
if (center_chan == 0 || (efuse->share_ant && center_chan <= 14)) {
link = 0;
} else if (center_chan <= 14) {
link = 0x1;
if (bw == RTW_CHANNEL_WIDTH_40)
bw = chip->bt_afh_span_bw40;
else
bw = chip->bt_afh_span_bw20;
} else if (chip->afh_5g_num > 1) {
for (i = 0; i < chip->afh_5g_num; i++) {
if (center_chan == chip->afh_5g[i].wl_5g_ch) {
link = 0x3;
center_chan = chip->afh_5g[i].bt_skip_ch;
bw = chip->afh_5g[i].bt_skip_span;
break;
}
}
}
coex_dm->wl_ch_info[0] = link;
coex_dm->wl_ch_info[1] = center_chan;
coex_dm->wl_ch_info[2] = bw;
rtw_fw_wl_ch_info(rtwdev, link, center_chan, bw);
}
static void rtw_coex_set_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
if (bt_pwr_dec_lvl == coex_dm->cur_bt_pwr_lvl)
return;
coex_dm->cur_bt_pwr_lvl = bt_pwr_dec_lvl;
rtw_fw_force_bt_tx_power(rtwdev, bt_pwr_dec_lvl);
}
static void rtw_coex_set_bt_rx_gain(struct rtw_dev *rtwdev, u8 bt_lna_lvl)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
if (bt_lna_lvl == coex_dm->cur_bt_lna_lvl)
return;
coex_dm->cur_bt_lna_lvl = bt_lna_lvl;
/* notify BT rx gain table changed */
if (bt_lna_lvl < 7) {
rtw_coex_set_lna_constrain_level(rtwdev, bt_lna_lvl);
rtw_coex_write_scbd(rtwdev, COEX_SCBD_RXGAIN, true);
} else {
rtw_coex_write_scbd(rtwdev, COEX_SCBD_RXGAIN, false);
}
}
static void rtw_coex_set_rf_para(struct rtw_dev *rtwdev,
struct coex_rf_para para)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
u8 offset = 0;
if (coex->freerun && coex_stat->wl_noisy_level <= 1)
offset = 3;
rtw_coex_set_wl_tx_power(rtwdev, para.wl_pwr_dec_lvl);
rtw_coex_set_bt_tx_power(rtwdev, para.bt_pwr_dec_lvl + offset);
rtw_coex_set_wl_rx_gain(rtwdev, para.wl_low_gain_en);
rtw_coex_set_bt_rx_gain(rtwdev, para.bt_lna_lvl);
}
u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr)
{
u32 val;
if (!ltecoex_read_reg(rtwdev, addr, &val)) {
rtw_err(rtwdev, "failed to read indirect register\n");
return 0;
}
return val;
}
EXPORT_SYMBOL(rtw_coex_read_indirect_reg);
void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr,
u32 mask, u32 val)
{
u32 shift = __ffs(mask);
u32 tmp;
tmp = rtw_coex_read_indirect_reg(rtwdev, addr);
tmp = (tmp & (~mask)) | ((val << shift) & mask);
if (!ltecoex_reg_write(rtwdev, addr, tmp))
rtw_err(rtwdev, "failed to write indirect register\n");
}
EXPORT_SYMBOL(rtw_coex_write_indirect_reg);
static void rtw_coex_coex_ctrl_owner(struct rtw_dev *rtwdev, bool wifi_control)
{
struct rtw_chip_info *chip = rtwdev->chip;
const struct rtw_hw_reg *btg_reg = chip->btg_reg;
if (wifi_control) {
rtw_write32_set(rtwdev, REG_SYS_SDIO_CTRL, BIT_LTE_MUX_CTRL_PATH);
if (btg_reg)
rtw_write8_set(rtwdev, btg_reg->addr, btg_reg->mask);
} else {
rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_LTE_MUX_CTRL_PATH);
if (btg_reg)
rtw_write8_clr(rtwdev, btg_reg->addr, btg_reg->mask);
}
}
static void rtw_coex_set_gnt_bt(struct rtw_dev *rtwdev, u8 state)
{
rtw_coex_write_indirect_reg(rtwdev, 0x38, 0xc000, state);
rtw_coex_write_indirect_reg(rtwdev, 0x38, 0x0c00, state);
}
static void rtw_coex_set_gnt_wl(struct rtw_dev *rtwdev, u8 state)
{
rtw_coex_write_indirect_reg(rtwdev, 0x38, 0x3000, state);
rtw_coex_write_indirect_reg(rtwdev, 0x38, 0x0300, state);
}
static void rtw_coex_set_table(struct rtw_dev *rtwdev, u32 table0, u32 table1)
{
#define DEF_BRK_TABLE_VAL 0xf0ffffff
rtw_write32(rtwdev, REG_BT_COEX_TABLE0, table0);
rtw_write32(rtwdev, REG_BT_COEX_TABLE1, table1);
rtw_write32(rtwdev, REG_BT_COEX_BRK_TABLE, DEF_BRK_TABLE_VAL);
}
static void rtw_coex_table(struct rtw_dev *rtwdev, u8 type)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_efuse *efuse = &rtwdev->efuse;
coex_dm->cur_table = type;
if (efuse->share_ant) {
if (type < chip->table_sant_num)
rtw_coex_set_table(rtwdev,
chip->table_sant[type].bt,
chip->table_sant[type].wl);
} else {
type = type - 100;
if (type < chip->table_nsant_num)
rtw_coex_set_table(rtwdev,
chip->table_nsant[type].bt,
chip->table_nsant[type].wl);
}
}
static void rtw_coex_ignore_wlan_act(struct rtw_dev *rtwdev, bool enable)
{
struct rtw_coex *coex = &rtwdev->coex;
if (coex->stop_dm)
return;
rtw_fw_bt_ignore_wlan_action(rtwdev, enable);
}
static void rtw_coex_power_save_state(struct rtw_dev *rtwdev, u8 ps_type,
u8 lps_val, u8 rpwm_val)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
u8 lps_mode = 0x0;
lps_mode = rtwdev->lps_conf.mode;
switch (ps_type) {
case COEX_PS_WIFI_NATIVE:
/* recover to original 32k low power setting */
coex_stat->wl_force_lps_ctrl = false;
rtw_leave_lps(rtwdev);
break;
case COEX_PS_LPS_OFF:
coex_stat->wl_force_lps_ctrl = true;
if (lps_mode)
rtw_fw_coex_tdma_type(rtwdev, 0x8, 0, 0, 0, 0);
rtw_leave_lps(rtwdev);
break;
default:
break;
}
}
static void rtw_coex_set_tdma(struct rtw_dev *rtwdev, u8 byte1, u8 byte2,
u8 byte3, u8 byte4, u8 byte5)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_chip_info *chip = rtwdev->chip;
u8 ps_type = COEX_PS_WIFI_NATIVE;
bool ap_enable = false;
if (ap_enable && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
byte1 &= ~BIT(4);
byte1 |= BIT(5);
byte5 |= BIT(5);
byte5 &= ~BIT(6);
ps_type = COEX_PS_WIFI_NATIVE;
rtw_coex_power_save_state(rtwdev, ps_type, 0x0, 0x0);
} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
if (chip->pstdma_type == COEX_PSTDMA_FORCE_LPSOFF)
ps_type = COEX_PS_LPS_OFF;
else
ps_type = COEX_PS_LPS_ON;
rtw_coex_power_save_state(rtwdev, ps_type, 0x50, 0x4);
} else {
ps_type = COEX_PS_WIFI_NATIVE;
rtw_coex_power_save_state(rtwdev, ps_type, 0x0, 0x0);
}
coex_dm->ps_tdma_para[0] = byte1;
coex_dm->ps_tdma_para[1] = byte2;
coex_dm->ps_tdma_para[2] = byte3;
coex_dm->ps_tdma_para[3] = byte4;
coex_dm->ps_tdma_para[4] = byte5;
rtw_fw_coex_tdma_type(rtwdev, byte1, byte2, byte3, byte4, byte5);
}
static void rtw_coex_tdma(struct rtw_dev *rtwdev, bool force, u32 tcase)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_dm *coex_dm = &coex->dm;
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_efuse *efuse = &rtwdev->efuse;
u8 n, type;
bool turn_on;
if (tcase & TDMA_4SLOT)/* 4-slot (50ms) mode */
rtw_coex_tdma_timer_base(rtwdev, 3);
else
rtw_coex_tdma_timer_base(rtwdev, 0);
type = (u8)(tcase & 0xff);
turn_on = (type == 0 || type == 100) ? false : true;
if (!force) {
if (turn_on == coex_dm->cur_ps_tdma_on &&
type == coex_dm->cur_ps_tdma) {
return;
}
}
if (turn_on) {
/* enable TBTT interrupt */
rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
rtw_coex_write_scbd(rtwdev, COEX_SCBD_TDMA, true);
} else {
rtw_coex_write_scbd(rtwdev, COEX_SCBD_TDMA, false);
}
if (efuse->share_ant) {
if (type < chip->tdma_sant_num)
rtw_coex_set_tdma(rtwdev,
chip->tdma_sant[type].para[0],
chip->tdma_sant[type].para[1],
chip->tdma_sant[type].para[2],
chip->tdma_sant[type].para[3],
chip->tdma_sant[type].para[4]);
} else {
n = type - 100;
if (n < chip->tdma_nsant_num)
rtw_coex_set_tdma(rtwdev,
chip->tdma_nsant[n].para[0],
chip->tdma_nsant[n].para[1],
chip->tdma_nsant[n].para[2],
chip->tdma_nsant[n].para[3],
chip->tdma_nsant[n].para[4]);
}
/* update pre state */
coex_dm->cur_ps_tdma_on = turn_on;
coex_dm->cur_ps_tdma = type;
rtw_dbg(rtwdev, RTW_DBG_COEX, "coex: coex tdma type (%d)\n", type);
}
static void rtw_coex_set_ant_path(struct rtw_dev *rtwdev, bool force, u8 phase)
{
struct rtw_coex *coex = &rtwdev->coex;
struct rtw_coex_stat *coex_stat = &coex->stat;
struct rtw_coex_dm *coex_dm = &coex->dm;
u8 ctrl_type = COEX_SWITCH_CTRL_MAX;
u8 pos_type = COEX_SWITCH_TO_MAX;
if (!force && coex_dm->cur_ant_pos_type == phase)
return;
coex_dm->cur_ant_pos_type = phase;
/* avoid switch coex_ctrl_owner during BT IQK */
rtw_coex_check_rfk(rtwdev);
switch (phase) {
case COEX_SET_ANT_POWERON:
/* set path control owner to BT at power-on */
if (coex_stat->bt_disabled)
rtw_coex_coex_ctrl_owner(rtwdev, true);
else
rtw_coex_coex_ctrl_owner(rtwdev, false);
ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
pos_type = COEX_SWITCH_TO_BT;
break;
case COEX_SET_ANT_INIT:
if (coex_stat->bt_disabled) {
/* set GNT_BT to SW low */
rtw_coex_set_gnt_bt(rtwdev, COEX_GNT_SET_SW_LOW);
/* set GNT_WL to SW high */
rtw_coex_set_gnt_wl(rtwdev, COEX_GNT_SET_SW_HIGH);
} else {
/* set GNT_BT to SW high */
rtw_coex_set_gnt_bt(rtwdev, COEX_GNT_SET_SW_HIGH);
/* set GNT_WL to SW low */
rtw_coex_set_gnt_wl(rtwdev, COEX_GNT_SET_SW_LOW);
}
/* set path control owner to wl at initial step */
rtw_coex_coex_ctrl_owner(rtwdev, true);
ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
pos_type = COEX_SWITCH_TO_BT;
break;
case COEX_SET_ANT_WONLY:
/* set GNT_BT to SW Low */
rtw_coex_set_gnt_bt(rtwdev, COEX_GNT_SET_SW_LOW);
/* Set GNT_WL to SW high */
rtw_coex_set_gnt_wl(rtwdev, COEX_GNT_SET_SW_HIGH);