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CHANGELOG.md

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Changes 3.0 to (unreleased):

  • Clean up examples to yield better Verilog output
  • Fewer stupid parentheses in Verilog output
  • Emit indexed part select Verilog syntax (+: or -:) when possible
  • Improved WARNING messages
  • Use ',' to separate sensitivity list in Verilog 2001 output
  • Support ** as exponentiation operator
  • Partial support for while and assert, contributed by jeinstei
  • Minor build system improvements, now might work on macOS

Changes 2.5 to 3.0 (Rodrigo A. Melo, February 2017):

  • Github-ization, including converting text to markdown
  • Better Verilog standard selection, and make 2001 the default
  • New --quiet option
  • Support scientific notation for floats
  • Use GHDL to test example VHDL input, corrected problems discovered
  • Yosys-compatible whitespace in <size>'<radix><number> notation output

Changes 2.4 to 2.5 (Larry Doolittle, September 2015)

Coding:

  • Use $(CC) in makefile
  • Trivial fix to yacc grammar, was causing FTBFS with recent bison
  • Eliminate a couple of unused variables

Changes 2.3 to 2.4 (Larry Doolittle, November 2010)

Grammar:

  • drop DOS-style returns at end of comments
  • allow FLOAT in expressions (maybe a mistake)
  • fixed regression in "others" handling since 2.1
  • don't crash with "others" in instantiation (Verilog result is still broken)

Grammar submitted by Shankar Giri:

  • Verilog 2001 module declaration (runtime selectable, use -g2001)
  • named generate block support for XST compatibility
  • support for array of vectors
  • some generic enhancements on architecture body

Coding:

  • CLI enhancement (added more switches)
  • factor out push_clkedge(), pull_clkedge()
  • fully const-correct
  • minor whitespace and coding style cleanup

Changes 2.2 to 2.3 (Larry Doolittle, May 2010)

Grammar:

  • add array type (not well tested)
  • add octal strings (O"777")
  • add one more "rem"
  • accept octal and hex strings as "when" values
  • accept constants, bit ranges, and "open" in port mappings
  • accept a single un-named generic map item
  • accept conv_integer function, treated as a no-op
  • accept ports with default values, but ignore default and give a warning
  • accept integer ranges, but ignore the range and give a warning

Coding:

  • list def.h properly in makefile
  • factor out new_vrange(), addnest(), setup_port()

Changes 1.2 to 2.2 (Larry Doolittle, February 2009)

Merge extensive changes from Mark Gonzales' version 2.0. Thanks, Mark!

Grammar:

  • add XNOR
  • add hex strings (X"f0f0")
  • remove UNIT reserved words, and actually emit timescale directive
  • case statements without "when others"
  • add a few more "rem"s to the grammar
  • add resize to the CONVFUNC_2 list
  • handle one-bit enumeration bit range correctly (no more [0])
  • some gratuitous changes in output whitespace

Coding:

  • clean up GENERIC pattern
  • debug and clean up slist routines and their usage
  • wrap malloc with xmalloc to exit if out of memory
  • update Free Software Foundation address

Changes 2.0 to 2.1 (Steve Haynal, unreleased?)

Presumably useful to Steve, but everything is too strange or scary for me (Larry Doolittle) to understand and incorporate. Sorry, Steve, maybe I'll get something from your work on my next iteration. People interested in the following features (incomplete list) should contact the developers directly:

  • lower-cased identifiers in translated Verilog
  • parses VHDL packages
  • parses many VHDL functions and macros
  • floating-point "after" construct parsed but ignored

Changes 1.0 to 2.0 (Mark Gonzales, June 2006)

Grammar:

  • FOR LOOP
  • FOR GENERATE and IF GENERATE
  • natural, integer, time types
  • based numbers (16#55aa#)
  • expressions can now include VHDL type conversion functions, mod operator, numbers
  • now can tolerate comments in the middle of expressions
  • expressions can now be used in subscripts and vector range definitions
  • width on (others => 'x') can now be an expression
  • uses always @(*) when creating some combinational always blocks
  • variable initialization support
  • constant can be initialized by an expression
  • GENERIC definitions for entity are now translated into Verilog parameter definitions, and GENERIC MAPs on instances are translated into Verilog in-line explicit parameter definitions.
  • allow entity declarations and architectures in separate files

Operation:

  • new -d option for trace parse - to debug grammar errors

Coding:

  • introduce slist data structure to build resulting Verilog

Changes 1.0 to 1.2 (Larry Doolittle, May 2005)

Grammar:

  • allow NATURAL as an expression terminal symbol
  • allow (name'event and exprc) as process sensitivity
  • allow IS syntactic sugar in COMPONENT declaration
  • add a bunch of "rem"s to the grammar
  • handle inout better
  • treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector"

Operation:

  • more complete handling of argc/argv
  • if error happened, return 1 from main and remove incorrect/incomplete output files
  • avoid insinuating that output Verilog is covered by GPL

Coding:

  • increase gcc warning level
  • add required #includes
  • remove spurious commas in bison token lists
  • drop worthless malloc() casts; see C-faq/q7.7
  • prototype yylex and yyerror
  • add braces around confusing if/else chain

Original 1.0 (Vincenzo Liguori, February 2001)