[dv] Verify data_rvalid_i hardening

[GregAC]

This PR: #1968 altered the handling of data_rvalid_i so that it will only cause a register write if a load is expected. Add a test that glitches data_rvalid_i when a load isn't in progress to verify this hardening.

[GregAC]

As this is a trivial feature that looks correct on inspection and is well tested under normal (i.e. no glitches) operation and isn't a critical countermeasure, but rather useful to have, this is assigned a low priority.