riscv_dret_test check fail

[Jiahua-Gong]

DV Bugs:
UVM_FATAL core_ibex_test_lib.sv(842) @ 8492700: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode

I think a dv bug, spike run asm code mret, (Machine mode -> User Mode && check mstatus == 2'b00).
RTL: return to the user mode,it's okay.
Testbench: should stay machine mode state. I think it's wrong.

[rswarbrick]

Hi there, and thanks for the message.

Could you give us a little more information about how to reproduce this? Maybe a seed for the test? I just ran make IBEX_CONFIG=opentitan SIMULATOR=vcs ISS=spike ITERATIONS=1 SEED=1 TEST=riscv_dret_test WAVES=0 COV=0 in the uvm/core_ibex directory and everything seemed to work.