Error in Simple system VCS+Verdi simulation, Failed to find the Verdi database

[tju-sun-lab]

Observed Behavior

I simulated the simple system example using VCS, following the guide in https://github.com/lowRISC/ibex/blob/master/examples/simple_system/README.md

I build the simulation with:
fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast --SRAMInitFile=./examples/sw/simple_system/hello_test/hello_test.vmem
It showed success.

Then I run the simulator as:
/build/lowrisc_ibex_ibex_simple_system_0/sim-vcs/lowrisc_ibex_ibex_simple_system_0 -gui &
Then I came across the error:

Error - Failed to find the Verdi database in ./build/lowrisc_ibex_ibex_simple_system_0/sim-vcs/lowrisc_ibex_ibex_simple_system_0.daidir. To solve the issue, generate the simulation database using VCS tools with the -kdb option.

If I don't use the DVE GUI,
./build/lowrisc_ibex_ibex_simple_system_0/sim-vcs/lowrisc_ibex_ibex_simple_system_0
It seems OK

Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06_Full64; Runtime version T-2022.06_Full64; Feb 19 23:21 2024
Initializing memory ibex_simple_system.u_ram.u_ram.gen_generic.u_impl_generic.unnamed$$_2.gen_meminit from file './examples/sw/simple_system/hello_test/hello_test.vmem'.
ibex_simple_system.u_top.u_ibex_tracer.unnamed$$_1.unnamed$$_2: Writing execution trace to trace_core_00000000.log
Terminating simulation by software request.
$finish called from file "../src/lowrisc_ibex_sim_shared_0/./rtl/sim/simulator_ctrl.sv", line 93.
$finish at simulation time 26276
V C S S i m u l a t i o n R e p o r t
Time: 26276
CPU Time: 0.270 seconds; Data structure size: 0.1Mb
Mon Feb 19 23:21:53 2024

So I would really appriciate it if you could help me solve this problem.

My Environment

EDA tool and version:

Synopsys VCS T-2022.06
Synopsys Verdi T-2022.06 for linux64 - May 29, 2022

Operating system:

Ubuntu Linux 20.04

Version of the Ibex source code:

5a8a1a9

[tju-sun-lab]

I modified the "ibex_simple_system.core" file and added a "-kdb" option, then the problem seems to be solved.
The sim section in the file will be

sim:
<<: *default_target
default_tool: verilator
tools:
vcs:
vcs_options:
- '-xlrm uniq_prior_final'
- '-debug_access+r'
- '-kdb'
verilator:
mode: cc
verilator_options:
# Disabling tracing reduces compile times but doesn't have a
# huge influence on runtime performance.
- '--trace'
- '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"
- "-Wwarn-IMPERFECTSCH"
# RAM primitives wider than 64bit (required for ECC) fail to build in
# Verilator without increasing the unroll count (see Verilator#1266)
- "--unroll-count 72"

[rswarbrick]

This looks like a sensible change to me. (And the VCS support in that file was written by me, back in 2020!)

Are you happy to open a PR with it?

[tju-sun-lab]

This looks like a sensible change to me. (And the VCS support in that file was written by me, back in 2020!)

Are you happy to open a PR with it?

Happy to that! I will open a pull request asap.