From 8c54914f97e98545a77f9948fb7ef8c069c3ccdd Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Thu, 16 Jan 2025 15:29:21 +0000 Subject: [PATCH] [prim,rtl] Remove ~under_rst from the expression for fifo_incr_wptr This term can only be necessary if wready_o is true. But wready_o is driven by the following continuous assignment: assign wready_o = ~full_o & ~under_rst; This commit doesn't add an assertion (to check the behaviour doesn't change) because the behaviour is internal to the module. Signed-off-by: Rupert Swarbrick --- hw/ip/prim/rtl/prim_fifo_sync.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ip/prim/rtl/prim_fifo_sync.sv b/hw/ip/prim/rtl/prim_fifo_sync.sv index 11910113e7e5a..24e00a5734043 100644 --- a/hw/ip/prim/rtl/prim_fifo_sync.sv +++ b/hw/ip/prim/rtl/prim_fifo_sync.sv @@ -176,7 +176,7 @@ module prim_fifo_sync #( .depth_o, .err_o ); - assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; + assign fifo_incr_wptr = wvalid_i & wready_o; assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; logic [Depth-1:0][Width-1:0] storage;