From c5165255bce45cf344de5150aa4cd1dd51be517f Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Tue, 29 Oct 2024 15:41:11 +0000
Subject: [PATCH 01/21] pinmux: changed spi signals to match common names

---
 data/top_config.toml               |  66 +++++------
 doc/ip/pinmux/README.md            |  50 ++++----
 rtl/system/pinmux.sv               | 180 ++++++++++++++---------------
 rtl/system/sonata_system.sv        |  22 ++--
 sw/cheri/common/platform-pinmux.hh |  16 +--
 5 files changed, 167 insertions(+), 167 deletions(-)

diff --git a/data/top_config.toml b/data/top_config.toml
index b763c8ad1..96b9c90fb 100644
--- a/data/top_config.toml
+++ b/data/top_config.toml
@@ -46,9 +46,9 @@ xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
 name = "spi"
 instances = 5
 ios = [
-  { name = "rx", type = "input", default = 0 },
-  { name = "tx", type = "output" },
-  { name = "sck", type = "output" },
+  { name = "cipo", type = "input", default = 0 },
+  { name = "copi", type = "output" },
+  { name = "sclk", type = "output" },
   { name = "cs", type = "output", length = 4 },
 ]
 memory_start = 0x80300000
@@ -99,15 +99,15 @@ block_ios = [{ block = "i2c", instance = 1, io = "sda" }]
 ## SPI Flash interface
 [[pins]]
 name = "appspi_d0"
-block_ios = [{ block = "spi", instance = 0, io = "tx" }]
+block_ios = [{ block = "spi", instance = 0, io = "copi" }]
 
 [[pins]]
 name = "appspi_d1"
-block_ios = [{ block = "spi", instance = 0, io = "rx" }]
+block_ios = [{ block = "spi", instance = 0, io = "cipo" }]
 
 [[pins]]
 name = "appspi_clk"
-block_ios = [{ block = "spi", instance = 0, io = "sck" }]
+block_ios = [{ block = "spi", instance = 0, io = "sclk" }]
 
 [[pins]]
 name = "appspi_cs"
@@ -116,13 +116,13 @@ block_ios = [{ block = "spi", instance = 0, io = "cs", io_index = 0 }]
 ## SPI LCD
 [[pins]]
 name = "lcd_copi"
-block_ios = [{ block = "spi", instance = 1, io = "tx" }]
+block_ios = [{ block = "spi", instance = 1, io = "copi" }]
 
 ## RX or CIPO is not connected
 
 [[pins]]
 name = "lcd_clk"
-block_ios = [{ block = "spi", instance = 1, io = "sck" }]
+block_ios = [{ block = "spi", instance = 1, io = "sclk" }]
 
 [[pins]]
 name = "lcd_cs"
@@ -131,15 +131,15 @@ block_ios = [{ block = "spi", instance = 1, io = "cs", io_index = 0 }]
 ## SPI Ethernet
 [[pins]]
 name = "ethmac_copi"
-block_ios = [{ block = "spi", instance = 2, io = "tx" }]
+block_ios = [{ block = "spi", instance = 2, io = "copi" }]
 
 [[pins]]
 name = "ethmac_cipo"
-block_ios = [{ block = "spi", instance = 2, io = "rx" }]
+block_ios = [{ block = "spi", instance = 2, io = "cipo" }]
 
 [[pins]]
 name = "ethmac_sclk"
-block_ios = [{ block = "spi", instance = 2, io = "sck" }]
+block_ios = [{ block = "spi", instance = 2, io = "sclk" }]
 
 [[pins]]
 name = "ethmac_cs"
@@ -203,21 +203,21 @@ block_ios = [
 [[pins]]
 name = "rph_g9_cipo"
 block_ios = [
-  {block = "spi", instance = 3, io = "rx"},
+  {block = "spi", instance = 3, io = "cipo"},
   {block = "gpio", instance = 0, io = "ios", io_index = 9},
 ]
 
 [[pins]]
 name = "rph_g10_copi"
 block_ios = [
-  {block = "spi", instance = 3, io = "tx"},
+  {block = "spi", instance = 3, io = "copi"},
   {block = "gpio", instance = 0, io = "ios", io_index = 10},
 ]
 
 [[pins]]
 name = "rph_g11_sclk"
 block_ios = [
-  {block = "spi", instance = 3, io = "sck"},
+  {block = "spi", instance = 3, io = "sclk"},
   {block = "gpio", instance = 0, io = "ios", io_index = 11},
 ]
 
@@ -267,21 +267,21 @@ block_ios = [
 [[pins]]
 name = "rph_g19_cipo"
 block_ios = [
-  {block = "spi", instance = 4, io = "rx"},
+  {block = "spi", instance = 4, io = "cipo"},
   {block = "gpio", instance = 0, io = "ios", io_index = 19},
 ]
 
 [[pins]]
 name = "rph_g20_copi"
 block_ios = [
-  {block = "spi", instance = 4, io = "tx"},
+  {block = "spi", instance = 4, io = "copi"},
   {block = "gpio", instance = 0, io = "ios", io_index = 20},
 ]
 
 [[pins]]
 name = "rph_g21_sclk"
 block_ios = [
-  {block = "spi", instance = 4, io = "sck"},
+  {block = "spi", instance = 4, io = "sclk"},
   {block = "gpio", instance = 0, io = "ios", io_index = 21},
 ]
 
@@ -362,21 +362,21 @@ block_ios = [
 [[pins]]
 name = "ah_tmpio11"
 block_ios = [
-  {block = "spi", instance = 3, io = "tx"},
+  {block = "spi", instance = 3, io = "copi"},
   {block = "gpio", instance = 1, io = "ios", io_index = 11},
 ]
 
 [[pins]]
 name = "ah_tmpio12"
 block_ios = [
-  {block = "spi", instance = 3, io = "rx"},
+  {block = "spi", instance = 3, io = "cipo"},
   {block = "gpio", instance = 1, io = "ios", io_index = 12},
 ]
 
 [[pins]]
 name = "ah_tmpio13"
 block_ios = [
-  {block = "spi", instance = 3, io = "sck"},
+  {block = "spi", instance = 3, io = "sclk"},
   {block = "gpio", instance = 1, io = "ios", io_index = 13},
 ]
 
@@ -388,15 +388,15 @@ block_ios = [{block = "spi", instance = 4, io = "cs", io_index = 3}]
 
 [[pins]]
 name = "mb2"
-block_ios = [{block = "spi", instance = 4, io = "sck"}]
+block_ios = [{block = "spi", instance = 4, io = "sclk"}]
 
 [[pins]]
 name = "mb3"
-block_ios = [{block = "spi", instance = 4, io = "rx"}]
+block_ios = [{block = "spi", instance = 4, io = "cipo"}]
 
 [[pins]]
 name = "mb4"
-block_ios = [{block = "spi", instance = 4, io = "tx"}]
+block_ios = [{block = "spi", instance = 4, io = "copi"}]
 
 [[pins]]
 name = "mb5"
@@ -425,13 +425,13 @@ name = "pmod0_1"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 0},
   {block = "spi", instance = 2, io = "cs", io_index = 0},
- ]
+]
 
 [[pins]]
 name = "pmod0_2"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 1},
-  {block = "spi", instance = 2, io = "tx"},
+  {block = "spi", instance = 2, io = "copi"},
   {block = "uart", instance = 2, io = "tx"},
 ]
 
@@ -440,7 +440,7 @@ name = "pmod0_3"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 2},
   {block = "i2c", instance = 0, io = "scl"},
-  {block = "spi", instance = 2, io = "rx"},
+  {block = "spi", instance = 2, io = "cipo"},
   {block = "uart", instance = 2, io = "rx"},
 ]
 
@@ -449,7 +449,7 @@ name = "pmod0_4"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 3},
   {block = "i2c", instance = 0, io = "sda"},
-  {block = "spi", instance = 2, io = "sck"},
+  {block = "spi", instance = 2, io = "sclk"},
 ]
 
 [[pins]]
@@ -479,7 +479,7 @@ block_ios = [
 name = "pmod1_2"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 1},
-  {block = "spi", instance = 3, io = "tx"},
+  {block = "spi", instance = 3, io = "copi"},
   {block = "uart", instance = 3, io = "tx"},
 ]
 
@@ -488,7 +488,7 @@ name = "pmod1_3"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 2},
   {block = "i2c", instance = 1, io = "scl"},
-  {block = "spi", instance = 3, io = "rx"},
+  {block = "spi", instance = 3, io = "cipo"},
   {block = "uart", instance = 3, io = "rx"},
 ]
 
@@ -497,7 +497,7 @@ name = "pmod1_4"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 3},
   {block = "i2c", instance = 1, io = "sda"},
-  {block = "spi", instance = 3, io = "sck"},
+  {block = "spi", instance = 3, io = "sclk"},
 ]
 
 [[pins]]
@@ -519,15 +519,15 @@ block_ios = [{block = "gpio", instance = 3, io = "ios", io_index = 7}]
 ## MicroSD card slot
 [[pins]]
 name = "microsd_clk"
-block_ios = [{block = "spi", instance = 3, io = "sck"}]
+block_ios = [{block = "spi", instance = 3, io = "sclk"}]
 
 [[pins]]
 name = "microsd_dat0"
-block_ios = [{block = "spi", instance = 3, io = "rx"}]
+block_ios = [{block = "spi", instance = 3, io = "cipo"}]
 
 [[pins]]
 name = "microsd_cmd"
-block_ios = [{block = "spi", instance = 3, io = "tx"}]
+block_ios = [{block = "spi", instance = 3, io = "copi"}]
 
 [[pins]]
 name = "microsd_dat3"
diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index 560c80f92..d500cc3ae 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -19,14 +19,14 @@ The default value for all of these selectors is `'b10`.
 | 0x004 | `sda0` | 0, `i2c[0].sda` |
 | 0x005 | `scl1` | 0, `i2c[1].scl` |
 | 0x006 | `sda1` | 0, `i2c[1].sda` |
-| 0x007 | `appspi_d0` | 0, `spi[0].tx` |
-| 0x008 | `appspi_clk` | 0, `spi[0].sck` |
+| 0x007 | `appspi_d0` | 0, `spi[0].copi` |
+| 0x008 | `appspi_clk` | 0, `spi[0].sclk` |
 | 0x009 | `appspi_cs` | 0, `spi[0].cs[0]` |
-| 0x00a | `lcd_copi` | 0, `spi[1].tx` |
-| 0x00b | `lcd_clk` | 0, `spi[1].sck` |
+| 0x00a | `lcd_copi` | 0, `spi[1].copi` |
+| 0x00b | `lcd_clk` | 0, `spi[1].sclk` |
 | 0x00c | `lcd_cs` | 0, `spi[1].cs[0]` |
-| 0x00d | `ethmac_copi` | 0, `spi[2].tx` |
-| 0x00e | `ethmac_sclk` | 0, `spi[2].sck` |
+| 0x00d | `ethmac_copi` | 0, `spi[2].copi` |
+| 0x00e | `ethmac_sclk` | 0, `spi[2].sclk` |
 | 0x00f | `ethmac_cs` | 0, `spi[2].cs[0]` |
 | 0x010 | `rph_g0` | 0, `i2c[0].sda`, `gpio[0].ios[0]` |
 | 0x011 | `rph_g1` | 0, `i2c[0].scl`, `gpio[0].ios[1]` |
@@ -38,8 +38,8 @@ The default value for all of these selectors is `'b10`.
 | 0x017 | `rph_g7_ce1` | 0, `spi[3].cs[1]`, `gpio[0].ios[7]` |
 | 0x018 | `rph_g8_ce0` | 0, `spi[3].cs[0]`, `gpio[0].ios[8]` |
 | 0x019 | `rph_g9_cipo` | 0, `gpio[0].ios[9]` |
-| 0x01a | `rph_g10_copi` | 0, `spi[3].tx`, `gpio[0].ios[10]` |
-| 0x01b | `rph_g11_sclk` | 0, `spi[3].sck`, `gpio[0].ios[11]` |
+| 0x01a | `rph_g10_copi` | 0, `spi[3].copi`, `gpio[0].ios[10]` |
+| 0x01b | `rph_g11_sclk` | 0, `spi[3].sclk`, `gpio[0].ios[11]` |
 | 0x01c | `rph_g12` | 0, `gpio[0].ios[12]` |
 | 0x01d | `rph_g13` | 0, `gpio[0].ios[13]` |
 | 0x01e | `rph_txd0` | 0, `uart[2].tx`, `gpio[0].ios[14]` |
@@ -48,8 +48,8 @@ The default value for all of these selectors is `'b10`.
 | 0x021 | `rph_g17` | 0, `spi[4].cs[1]`, `gpio[0].ios[17]` |
 | 0x022 | `rph_g18` | 0, `spi[4].cs[0]`, `gpio[0].ios[18]` |
 | 0x023 | `rph_g19_cipo` | 0, `gpio[0].ios[19]` |
-| 0x024 | `rph_g20_copi` | 0, `spi[4].tx`, `gpio[0].ios[20]` |
-| 0x025 | `rph_g21_sclk` | 0, `spi[4].sck`, `gpio[0].ios[21]` |
+| 0x024 | `rph_g20_copi` | 0, `spi[4].copi`, `gpio[0].ios[20]` |
+| 0x025 | `rph_g21_sclk` | 0, `spi[4].sclk`, `gpio[0].ios[21]` |
 | 0x026 | `rph_g22` | 0, `gpio[0].ios[22]` |
 | 0x027 | `rph_g23` | 0, `gpio[0].ios[23]` |
 | 0x028 | `rph_g24` | 0, `gpio[0].ios[24]` |
@@ -67,34 +67,34 @@ The default value for all of these selectors is `'b10`.
 | 0x034 | `ah_tmpio8` | 0, `gpio[1].ios[8]` |
 | 0x035 | `ah_tmpio9` | 0, `gpio[1].ios[9]` |
 | 0x036 | `ah_tmpio10` | 0, `spi[3].cs[2]`, `gpio[1].ios[10]` |
-| 0x037 | `ah_tmpio11` | 0, `spi[3].tx`, `gpio[1].ios[11]` |
+| 0x037 | `ah_tmpio11` | 0, `spi[3].copi`, `gpio[1].ios[11]` |
 | 0x038 | `ah_tmpio12` | 0, `gpio[1].ios[12]` |
-| 0x039 | `ah_tmpio13` | 0, `spi[3].sck`, `gpio[1].ios[13]` |
+| 0x039 | `ah_tmpio13` | 0, `spi[3].sclk`, `gpio[1].ios[13]` |
 | 0x03a | `mb1` | 0, `spi[4].cs[3]` |
-| 0x03b | `mb2` | 0, `spi[4].sck` |
-| 0x03c | `mb4` | 0, `spi[4].tx` |
+| 0x03b | `mb2` | 0, `spi[4].sclk` |
+| 0x03c | `mb4` | 0, `spi[4].copi` |
 | 0x03d | `mb5` | 0, `i2c[1].sda` |
 | 0x03e | `mb6` | 0, `i2c[1].scl` |
 | 0x03f | `mb7` | 0, `uart[3].tx` |
 | 0x040 | `mb10` | 0, `pwm_ios[0]` |
 | 0x041 | `pmod0_1` | 0, `gpio[2].ios[0]`, `spi[2].cs[0]` |
-| 0x042 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[2].tx`, `uart[2].tx` |
+| 0x042 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[2].copi`, `uart[2].tx` |
 | 0x043 | `pmod0_3` | 0, `gpio[2].ios[2]`, `i2c[0].scl` |
-| 0x044 | `pmod0_4` | 0, `gpio[2].ios[3]`, `i2c[0].sda`, `spi[2].sck` |
+| 0x044 | `pmod0_4` | 0, `gpio[2].ios[3]`, `i2c[0].sda`, `spi[2].sclk` |
 | 0x045 | `pmod0_5` | 0, `gpio[2].ios[4]` |
 | 0x046 | `pmod0_6` | 0, `gpio[2].ios[5]` |
 | 0x047 | `pmod0_7` | 0, `gpio[2].ios[6]` |
 | 0x048 | `pmod0_8` | 0, `gpio[2].ios[7]` |
 | 0x049 | `pmod1_1` | 0, `gpio[3].ios[0]`, `spi[3].cs[0]` |
-| 0x04a | `pmod1_2` | 0, `gpio[3].ios[1]`, `spi[3].tx`, `uart[3].tx` |
+| 0x04a | `pmod1_2` | 0, `gpio[3].ios[1]`, `spi[3].copi`, `uart[3].tx` |
 | 0x04b | `pmod1_3` | 0, `gpio[3].ios[2]`, `i2c[1].scl` |
-| 0x04c | `pmod1_4` | 0, `gpio[3].ios[3]`, `i2c[1].sda`, `spi[3].sck` |
+| 0x04c | `pmod1_4` | 0, `gpio[3].ios[3]`, `i2c[1].sda`, `spi[3].sclk` |
 | 0x04d | `pmod1_5` | 0, `gpio[3].ios[4]` |
 | 0x04e | `pmod1_6` | 0, `gpio[3].ios[5]` |
 | 0x04f | `pmod1_7` | 0, `gpio[3].ios[6]` |
 | 0x050 | `pmod1_8` | 0, `gpio[3].ios[7]` |
-| 0x051 | `microsd_clk` | 0, `spi[3].sck` |
-| 0x052 | `microsd_cmd` | 0, `spi[3].tx` |
+| 0x051 | `microsd_clk` | 0, `spi[3].sclk` |
+| 0x052 | `microsd_cmd` | 0, `spi[3].copi` |
 | 0x053 | `microsd_dat3` | 0, `spi[3].cs[3]` |
 
 Besides the output pin selectors, there are also selectors for which pin should drive block inputs:
@@ -234,11 +234,11 @@ Besides the output pin selectors, there are also selectors for which pin should
 | 0x882 | `uart[2].rx` | 1, `rph_rxd0`, `pmod0_3` |
 | 0x883 | `uart[3].rx` | 1, `ah_tmpio0`, `mb8`, `pmod1_3` |
 | 0x884 | `uart[4].rx` | 1, `rs232_rx` |
-| 0x885 | `spi[0].rx` | 0, `appspi_d1` |
-| 0x886 | `spi[1].rx` | 0, 0 |
-| 0x887 | `spi[2].rx` | 0, `ethmac_cipo`, `pmod0_3` |
-| 0x888 | `spi[3].rx` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod1_3`, `microsd_dat0` |
-| 0x889 | `spi[4].rx` | 0, `rph_g19_cipo`, `mb3` |
+| 0x885 | `spi[0].cipo` | 0, `appspi_d1` |
+| 0x886 | `spi[1].cipo` | 0, 0 |
+| 0x887 | `spi[2].cipo` | 0, `ethmac_cipo`, `pmod0_3` |
+| 0x888 | `spi[3].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod1_3`, `microsd_dat0` |
+| 0x889 | `spi[4].cipo` | 0, `rph_g19_cipo`, `mb3` |
 
 ## Regeneration
 
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index 24a1f2025..522f63a1c 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -35,11 +35,11 @@ module pinmux
   input  i2c_sda_en_i[I2C_NUM],
 
   // SPI IOs
-  output spi_rx_o[SPI_NUM],
-  input  spi_tx_i   [SPI_NUM],
-  input  spi_tx_en_i[SPI_NUM],
-  input  spi_sck_i   [SPI_NUM],
-  input  spi_sck_en_i[SPI_NUM],
+  output spi_cipo_o[SPI_NUM],
+  input  spi_copi_i   [SPI_NUM],
+  input  spi_copi_en_i[SPI_NUM],
+  input  spi_sclk_i   [SPI_NUM],
+  input  spi_sclk_en_i[SPI_NUM],
   input  [3:0] spi_cs_i   [SPI_NUM],
   input  [3:0] spi_cs_en_i[SPI_NUM],
 
@@ -468,7 +468,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[0]
+      spi_copi_i[0]
     }),
     .sel_i(appspi_d0_sel),
     .out_o(out_to_pins_o[OUT_PIN_APPSPI_D0])
@@ -482,7 +482,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[0]
+      spi_copi_en_i[0]
     }),
     .sel_i(appspi_d0_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_APPSPI_D0])
@@ -516,7 +516,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[0]
+      spi_sclk_i[0]
     }),
     .sel_i(appspi_clk_sel),
     .out_o(out_to_pins_o[OUT_PIN_APPSPI_CLK])
@@ -530,7 +530,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[0]
+      spi_sclk_en_i[0]
     }),
     .sel_i(appspi_clk_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_APPSPI_CLK])
@@ -612,7 +612,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[1]
+      spi_copi_i[1]
     }),
     .sel_i(lcd_copi_sel),
     .out_o(out_to_pins_o[OUT_PIN_LCD_COPI])
@@ -626,7 +626,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[1]
+      spi_copi_en_i[1]
     }),
     .sel_i(lcd_copi_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_LCD_COPI])
@@ -660,7 +660,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[1]
+      spi_sclk_i[1]
     }),
     .sel_i(lcd_clk_sel),
     .out_o(out_to_pins_o[OUT_PIN_LCD_CLK])
@@ -674,7 +674,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[1]
+      spi_sclk_en_i[1]
     }),
     .sel_i(lcd_clk_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_LCD_CLK])
@@ -756,7 +756,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[2]
+      spi_copi_i[2]
     }),
     .sel_i(ethmac_copi_sel),
     .out_o(out_to_pins_o[OUT_PIN_ETHMAC_COPI])
@@ -770,7 +770,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[2]
+      spi_copi_en_i[2]
     }),
     .sel_i(ethmac_copi_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_ETHMAC_COPI])
@@ -804,7 +804,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[2]
+      spi_sclk_i[2]
     }),
     .sel_i(ethmac_sclk_sel),
     .out_o(out_to_pins_o[OUT_PIN_ETHMAC_SCLK])
@@ -818,7 +818,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[2]
+      spi_sclk_en_i[2]
     }),
     .sel_i(ethmac_sclk_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_ETHMAC_SCLK])
@@ -1392,7 +1392,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[3],
+      spi_copi_i[3],
       gpio_ios_i[0][10]
     }),
     .sel_i(rph_g10_copi_sel),
@@ -1407,7 +1407,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[3],
+      spi_copi_en_i[3],
       gpio_ios_en_i[0][10]
     }),
     .sel_i(rph_g10_copi_sel),
@@ -1442,7 +1442,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[3],
+      spi_sclk_i[3],
       gpio_ios_i[0][11]
     }),
     .sel_i(rph_g11_sclk_sel),
@@ -1457,7 +1457,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[3],
+      spi_sclk_en_i[3],
       gpio_ios_en_i[0][11]
     }),
     .sel_i(rph_g11_sclk_sel),
@@ -1884,7 +1884,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[4],
+      spi_copi_i[4],
       gpio_ios_i[0][20]
     }),
     .sel_i(rph_g20_copi_sel),
@@ -1899,7 +1899,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[4],
+      spi_copi_en_i[4],
       gpio_ios_en_i[0][20]
     }),
     .sel_i(rph_g20_copi_sel),
@@ -1934,7 +1934,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[4],
+      spi_sclk_i[4],
       gpio_ios_i[0][21]
     }),
     .sel_i(rph_g21_sclk_sel),
@@ -1949,7 +1949,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[4],
+      spi_sclk_en_i[4],
       gpio_ios_en_i[0][21]
     }),
     .sel_i(rph_g21_sclk_sel),
@@ -2804,7 +2804,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[3],
+      spi_copi_i[3],
       gpio_ios_i[1][11]
     }),
     .sel_i(ah_tmpio11_sel),
@@ -2819,7 +2819,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[3],
+      spi_copi_en_i[3],
       gpio_ios_en_i[1][11]
     }),
     .sel_i(ah_tmpio11_sel),
@@ -2902,7 +2902,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[3],
+      spi_sclk_i[3],
       gpio_ios_i[1][13]
     }),
     .sel_i(ah_tmpio13_sel),
@@ -2917,7 +2917,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[3],
+      spi_sclk_en_i[3],
       gpio_ios_en_i[1][13]
     }),
     .sel_i(ah_tmpio13_sel),
@@ -3000,7 +3000,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[4]
+      spi_sclk_i[4]
     }),
     .sel_i(mb2_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB2])
@@ -3014,7 +3014,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[4]
+      spi_sclk_en_i[4]
     }),
     .sel_i(mb2_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB2])
@@ -3048,7 +3048,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[4]
+      spi_copi_i[4]
     }),
     .sel_i(mb4_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB4])
@@ -3062,7 +3062,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[4]
+      spi_copi_en_i[4]
     }),
     .sel_i(mb4_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB4])
@@ -3339,7 +3339,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][1],
-      spi_tx_i[2],
+      spi_copi_i[2],
       uart_tx_i[2]
     }),
     .sel_i(pmod0_2_sel),
@@ -3355,7 +3355,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][1],
-      spi_tx_en_i[2],
+      spi_copi_en_i[2],
       uart_tx_en_i[2]
     }),
     .sel_i(pmod0_2_sel),
@@ -3442,7 +3442,7 @@ module pinmux
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][3],
       i2c_sda_i[0],
-      spi_sck_i[2]
+      spi_sclk_i[2]
     }),
     .sel_i(pmod0_4_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_4])
@@ -3458,7 +3458,7 @@ module pinmux
       1'b0,
       gpio_ios_en_i[2][3],
       i2c_sda_en_i[0],
-      spi_sck_en_i[2]
+      spi_sclk_en_i[2]
     }),
     .sel_i(pmod0_4_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_4])
@@ -3735,7 +3735,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][1],
-      spi_tx_i[3],
+      spi_copi_i[3],
       uart_tx_i[3]
     }),
     .sel_i(pmod1_2_sel),
@@ -3751,7 +3751,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][1],
-      spi_tx_en_i[3],
+      spi_copi_en_i[3],
       uart_tx_en_i[3]
     }),
     .sel_i(pmod1_2_sel),
@@ -3838,7 +3838,7 @@ module pinmux
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][3],
       i2c_sda_i[1],
-      spi_sck_i[3]
+      spi_sclk_i[3]
     }),
     .sel_i(pmod1_4_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_4])
@@ -3854,7 +3854,7 @@ module pinmux
       1'b0,
       gpio_ios_en_i[3][3],
       i2c_sda_en_i[1],
-      spi_sck_en_i[3]
+      spi_sclk_en_i[3]
     }),
     .sel_i(pmod1_4_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_4])
@@ -4080,7 +4080,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sck_i[3]
+      spi_sclk_i[3]
     }),
     .sel_i(microsd_clk_sel),
     .out_o(out_to_pins_o[OUT_PIN_MICROSD_CLK])
@@ -4094,7 +4094,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sck_en_i[3]
+      spi_sclk_en_i[3]
     }),
     .sel_i(microsd_clk_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MICROSD_CLK])
@@ -4128,7 +4128,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_tx_i[3]
+      spi_copi_i[3]
     }),
     .sel_i(microsd_cmd_sel),
     .out_o(out_to_pins_o[OUT_PIN_MICROSD_CMD])
@@ -4142,7 +4142,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_tx_en_i[3]
+      spi_copi_en_i[3]
     }),
     .sel_i(microsd_cmd_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MICROSD_CMD])
@@ -8723,11 +8723,11 @@ module pinmux
     .out_o(uart_rx_o[4])
   );
 
-  logic [1:0] spi_rx_0_sel;
-  logic spi_rx_0_sel_addressed;
+  logic [1:0] spi_cipo_0_sel;
+  logic spi_cipo_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_rx_0_sel_addressed =
+  assign spi_cipo_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 132 &
     reg_be[1] == 1'b1;
@@ -8735,10 +8735,10 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_rx_0_sel <= 2'b10;
+      spi_cipo_0_sel <= 2'b10;
     end else begin
-      if (reg_we & spi_rx_0_sel_addressed) begin
-        spi_rx_0_sel <= reg_wdata[8+:2];
+      if (reg_we & spi_cipo_0_sel_addressed) begin
+        spi_cipo_0_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -8746,22 +8746,22 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) spi_rx_0_mux (
+  ) spi_cipo_0_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
       in_from_pins_i[IN_PIN_APPSPI_D1]
     }),
-    .sel_i(spi_rx_0_sel),
-    .out_o(spi_rx_o[0])
+    .sel_i(spi_cipo_0_sel),
+    .out_o(spi_cipo_o[0])
   );
 
-  logic [1:0] spi_rx_1_sel;
-  logic spi_rx_1_sel_addressed;
+  logic [1:0] spi_cipo_1_sel;
+  logic spi_cipo_1_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_rx_1_sel_addressed =
+  assign spi_cipo_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 132 &
     reg_be[2] == 1'b1;
@@ -8769,10 +8769,10 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_rx_1_sel <= 2'b10;
+      spi_cipo_1_sel <= 2'b10;
     end else begin
-      if (reg_we & spi_rx_1_sel_addressed) begin
-        spi_rx_1_sel <= reg_wdata[16+:2];
+      if (reg_we & spi_cipo_1_sel_addressed) begin
+        spi_cipo_1_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -8780,22 +8780,22 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) spi_rx_1_mux (
+  ) spi_cipo_1_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
       1'b0
     }),
-    .sel_i(spi_rx_1_sel),
-    .out_o(spi_rx_o[1])
+    .sel_i(spi_cipo_1_sel),
+    .out_o(spi_cipo_o[1])
   );
 
-  logic [2:0] spi_rx_2_sel;
-  logic spi_rx_2_sel_addressed;
+  logic [2:0] spi_cipo_2_sel;
+  logic spi_cipo_2_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_rx_2_sel_addressed =
+  assign spi_cipo_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 132 &
     reg_be[3] == 1'b1;
@@ -8803,10 +8803,10 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_rx_2_sel <= 3'b10;
+      spi_cipo_2_sel <= 3'b10;
     end else begin
-      if (reg_we & spi_rx_2_sel_addressed) begin
-        spi_rx_2_sel <= reg_wdata[24+:3];
+      if (reg_we & spi_cipo_2_sel_addressed) begin
+        spi_cipo_2_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -8814,7 +8814,7 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(3)
-  ) spi_rx_2_mux (
+  ) spi_cipo_2_mux (
     .clk_i,
     .rst_ni,
     .in_i({
@@ -8822,15 +8822,15 @@ module pinmux
       in_from_pins_i[IN_PIN_ETHMAC_CIPO],
       inout_from_pins_i[INOUT_PIN_PMOD0_3]
     }),
-    .sel_i(spi_rx_2_sel),
-    .out_o(spi_rx_o[2])
+    .sel_i(spi_cipo_2_sel),
+    .out_o(spi_cipo_o[2])
   );
 
-  logic [4:0] spi_rx_3_sel;
-  logic spi_rx_3_sel_addressed;
+  logic [4:0] spi_cipo_3_sel;
+  logic spi_cipo_3_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_rx_3_sel_addressed =
+  assign spi_cipo_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 136 &
     reg_be[0] == 1'b1;
@@ -8838,10 +8838,10 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_rx_3_sel <= 5'b10;
+      spi_cipo_3_sel <= 5'b10;
     end else begin
-      if (reg_we & spi_rx_3_sel_addressed) begin
-        spi_rx_3_sel <= reg_wdata[0+:5];
+      if (reg_we & spi_cipo_3_sel_addressed) begin
+        spi_cipo_3_sel <= reg_wdata[0+:5];
       end
     end
   end
@@ -8849,7 +8849,7 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(5)
-  ) spi_rx_3_mux (
+  ) spi_cipo_3_mux (
     .clk_i,
     .rst_ni,
     .in_i({
@@ -8859,15 +8859,15 @@ module pinmux
       inout_from_pins_i[INOUT_PIN_PMOD1_3],
       in_from_pins_i[IN_PIN_MICROSD_DAT0]
     }),
-    .sel_i(spi_rx_3_sel),
-    .out_o(spi_rx_o[3])
+    .sel_i(spi_cipo_3_sel),
+    .out_o(spi_cipo_o[3])
   );
 
-  logic [2:0] spi_rx_4_sel;
-  logic spi_rx_4_sel_addressed;
+  logic [2:0] spi_cipo_4_sel;
+  logic spi_cipo_4_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_rx_4_sel_addressed =
+  assign spi_cipo_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 136 &
     reg_be[1] == 1'b1;
@@ -8875,10 +8875,10 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_rx_4_sel <= 3'b10;
+      spi_cipo_4_sel <= 3'b10;
     end else begin
-      if (reg_we & spi_rx_4_sel_addressed) begin
-        spi_rx_4_sel <= reg_wdata[8+:3];
+      if (reg_we & spi_cipo_4_sel_addressed) begin
+        spi_cipo_4_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -8886,7 +8886,7 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(3)
-  ) spi_rx_4_mux (
+  ) spi_cipo_4_mux (
     .clk_i,
     .rst_ni,
     .in_i({
@@ -8894,8 +8894,8 @@ module pinmux
       inout_from_pins_i[INOUT_PIN_RPH_G19_CIPO],
       in_from_pins_i[IN_PIN_MB3]
     }),
-    .sel_i(spi_rx_4_sel),
-    .out_o(spi_rx_o[4])
+    .sel_i(spi_cipo_4_sel),
+    .out_o(spi_cipo_o[4])
   );
 
   // Combining inputs for combinable inouts
diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
index 74da92f46..671cff863 100644
--- a/rtl/system/sonata_system.sv
+++ b/rtl/system/sonata_system.sv
@@ -1039,9 +1039,9 @@ module sonata_system
   // - 2x Raspberry Pi HAT
   // - Arduino Shield
   // - mikroBUS Click
-  logic                    spi_sck[SPI_NUM];
-  logic                    spi_tx[SPI_NUM];
-  logic                    spi_rx[SPI_NUM];
+  logic                    spi_sclk[SPI_NUM];
+  logic                    spi_copi[SPI_NUM];
+  logic                    spi_cipo[SPI_NUM];
   logic [SPI_CS_WIDTH-1:0] spi_cs[SPI_NUM];
   for (genvar i = 0; i < SPI_NUM; i++) begin : gen_spi_hosts
     spi #(
@@ -1062,10 +1062,10 @@ module sonata_system
       .intr_complete_o     (spi_interrupts[i][4]),
 
       // SPI signals.
-      .spi_copi_o          (spi_tx [i]),
-      .spi_cipo_i          (spi_rx [i]),
+      .spi_copi_o          (spi_copi [i]),
+      .spi_cipo_i          (spi_cipo [i]),
       .spi_cs_o            (spi_cs [i]),
-      .spi_clk_o           (spi_sck[i])
+      .spi_clk_o           (spi_sclk[i])
     );
   end : gen_spi_hosts
 
@@ -1205,11 +1205,11 @@ module sonata_system
     .i2c_sda_i(i2c_sda_h2d),
     .i2c_sda_en_i(i2c_sda_en_h2d),
 
-    .spi_rx_o(spi_rx),
-    .spi_tx_i(spi_tx),
-    .spi_tx_en_i('{default: 'b1}),
-    .spi_sck_i(spi_sck),
-    .spi_sck_en_i('{default: 'b1}),
+    .spi_cipo_o(spi_cipo),
+    .spi_copi_i(spi_copi),
+    .spi_copi_en_i('{default: 'b1}),
+    .spi_sclk_i(spi_sclk),
+    .spi_sclk_en_i('{default: 'b1}),
     .spi_cs_i(spi_cs),
     .spi_cs_en_i('{default: '1}), // All continuously enabled.
 
diff --git a/sw/cheri/common/platform-pinmux.hh b/sw/cheri/common/platform-pinmux.hh
index 503c564e0..f63e5d73b 100644
--- a/sw/cheri/common/platform-pinmux.hh
+++ b/sw/cheri/common/platform-pinmux.hh
@@ -285,11 +285,11 @@ class SonataPinmux : private utils::NoCopyNoMove {
     uart_2_rx     = 0x882,
     uart_3_rx     = 0x883,
     uart_4_rx     = 0x884,
-    spi_0_rx      = 0x885,
-    spi_1_rx      = 0x886,
-    spi_2_rx      = 0x887,
-    spi_3_rx      = 0x888,
-    spi_4_rx      = 0x889,
+    spi_0_cipo    = 0x885,
+    spi_1_cipo    = 0x886,
+    spi_2_cipo    = 0x887,
+    spi_3_cipo    = 0x888,
+    spi_4_cipo    = 0x889,
   };
 
   /**
@@ -353,13 +353,13 @@ class SonataPinmux : private utils::NoCopyNoMove {
    */
   static constexpr uint8_t block_input_options(BlockInput block_input) {
     switch (block_input) {
-      case BlockInput::spi_3_rx:
+      case BlockInput::spi_3_cipo:
         return 5;
       case BlockInput::uart_3_rx:
         return 4;
       case BlockInput::uart_2_rx:
-      case BlockInput::spi_2_rx:
-      case BlockInput::spi_4_rx:
+      case BlockInput::spi_2_cipo:
+      case BlockInput::spi_4_cipo:
         return 3;
       default:
         return 2;

From c5d0f42da22fa37b2cc270bbb91c05b84950531a Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Wed, 30 Oct 2024 15:07:10 +0000
Subject: [PATCH 02/21] pinmux: changed pwm signal name

`ios` isn't very accurate as these are only outputs.
---
 data/top_config.toml        | 4 ++--
 doc/ip/pinmux/README.md     | 2 +-
 rtl/system/pinmux.sv        | 8 ++++----
 rtl/system/sonata_pkg.sv    | 2 +-
 rtl/system/sonata_system.sv | 8 ++++----
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/data/top_config.toml b/data/top_config.toml
index 96b9c90fb..10db5f47a 100644
--- a/data/top_config.toml
+++ b/data/top_config.toml
@@ -15,7 +15,7 @@ memory_size  = 0x00000040
 [[blocks]]
 name = "pwm"
 instances = 1
-ios = [{ name = "ios", type = "output", length = 6 }]
+ios = [{ name = "out", type = "output", length = 6 }]
 memory_start = 0x80001000
 memory_size  = 0x00001000
 xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
@@ -417,7 +417,7 @@ block_ios = [{block = "uart", instance = 3, io = "rx"}]
 
 [[pins]]
 name = "mb10"
-block_ios = [{block = "pwm", instance = 0, io = "ios", io_index = 0}]
+block_ios = [{block = "pwm", instance = 0, io = "out", io_index = 0}]
 
 ## PMODs
 [[pins]]
diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index d500cc3ae..e45e7bbeb 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -76,7 +76,7 @@ The default value for all of these selectors is `'b10`.
 | 0x03d | `mb5` | 0, `i2c[1].sda` |
 | 0x03e | `mb6` | 0, `i2c[1].scl` |
 | 0x03f | `mb7` | 0, `uart[3].tx` |
-| 0x040 | `mb10` | 0, `pwm_ios[0]` |
+| 0x040 | `mb10` | 0, `pwm_out[0]` |
 | 0x041 | `pmod0_1` | 0, `gpio[2].ios[0]`, `spi[2].cs[0]` |
 | 0x042 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[2].copi`, `uart[2].tx` |
 | 0x043 | `pmod0_3` | 0, `gpio[2].ios[2]`, `i2c[0].scl` |
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index 522f63a1c..eced6cab3 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -18,8 +18,8 @@ module pinmux
   input  [31:0] gpio_ios_en_i[GPIO_NUM],
 
   // PWM IOs
-  input  [5:0] pwm_ios_i   [PWM_NUM],
-  input  [5:0] pwm_ios_en_i[PWM_NUM],
+  input  [5:0] pwm_out_i   [PWM_NUM],
+  input  [5:0] pwm_out_en_i[PWM_NUM],
 
   // UART IOs
   output uart_rx_o[UART_NUM],
@@ -3240,7 +3240,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      pwm_ios_i[0][0]
+      pwm_out_i[0][0]
     }),
     .sel_i(mb10_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB10])
@@ -3254,7 +3254,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      pwm_ios_en_i[0][0]
+      pwm_out_en_i[0][0]
     }),
     .sel_i(mb10_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB10])
diff --git a/rtl/system/sonata_pkg.sv b/rtl/system/sonata_pkg.sv
index 0387b910f..f3187fcf0 100644
--- a/rtl/system/sonata_pkg.sv
+++ b/rtl/system/sonata_pkg.sv
@@ -15,7 +15,7 @@ package sonata_pkg;
 
   // Width of block IO arrays
   localparam int unsigned GPIO_IOS_WIDTH = 32;
-  localparam int unsigned PWM_IOS_WIDTH = 6;
+  localparam int unsigned PWM_OUT_WIDTH = 6;
   localparam int unsigned SPI_CS_WIDTH = 4;
 
   // Number of input, output, and inout pins
diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
index 671cff863..5f5d2135c 100644
--- a/rtl/system/sonata_system.sv
+++ b/rtl/system/sonata_system.sv
@@ -908,9 +908,9 @@ module sonata_system
   end : gen_i2c_hosts
 
   // Pulse width modulator.
-  logic [PWM_IOS_WIDTH-1:0] pwm_modulated;
+  logic [PWM_OUT_WIDTH-1:0] pwm_modulated;
   pwm_wrapper #(
-    .PwmWidth   ( PWM_IOS_WIDTH ),
+    .PwmWidth   ( PWM_OUT_WIDTH ),
     .PwmCtrSize ( PwmCtrSize )
   ) u_pwm (
     .clk_i           (clk_sys_i),
@@ -1191,8 +1191,8 @@ module sonata_system
     .clk_i(clk_sys_i),
     .rst_ni(rst_sys_ni),
 
-    .pwm_ios_i('{pwm_modulated}),
-    .pwm_ios_en_i('{'b1}),
+    .pwm_out_i('{pwm_modulated}),
+    .pwm_out_en_i('{'b1}),
 
     .uart_rx_o(uart_rx),
     .uart_tx_i(uart_tx),

From 96e6d7c0fa363dbf5c6751b19ffefc8004cf8960 Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Thu, 31 Oct 2024 19:08:41 +0000
Subject: [PATCH 03/21] pinmux: explicitly set sizes for combined output
 selectors

Verilator's lint complains about this being implicit when selecting a
value of 8. See future pinmapping commit.
---
 rtl/system/pinmux.sv        | 28 ++++++++++++++--------------
 rtl/templates/pinmux.sv.tpl |  2 +-
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index eced6cab3..3ba2ca019 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -8900,21 +8900,21 @@ module pinmux
 
   // Combining inputs for combinable inouts
   assign i2c_scl_o[0] =
-    (scl0_sel == 2 ? inout_from_pins_i[INOUT_PIN_SCL0] : 1'b1) &
-    (rph_g1_sel == 2 ? inout_from_pins_i[INOUT_PIN_RPH_G1] : 1'b1) &
-    (pmod0_3_sel == 4 ? inout_from_pins_i[INOUT_PIN_PMOD0_3] : 1'b1);
+    (scl0_sel == $bits(scl0_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SCL0] : 1'b1) &
+    (rph_g1_sel == $bits(rph_g1_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G1] : 1'b1) &
+    (pmod0_3_sel == $bits(pmod0_3_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD0_3] : 1'b1);
   assign i2c_sda_o[0] =
-    (sda0_sel == 2 ? inout_from_pins_i[INOUT_PIN_SDA0] : 1'b1) &
-    (rph_g0_sel == 2 ? inout_from_pins_i[INOUT_PIN_RPH_G0] : 1'b1) &
-    (pmod0_4_sel == 4 ? inout_from_pins_i[INOUT_PIN_PMOD0_4] : 1'b1);
+    (sda0_sel == $bits(sda0_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SDA0] : 1'b1) &
+    (rph_g0_sel == $bits(rph_g0_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G0] : 1'b1) &
+    (pmod0_4_sel == $bits(pmod0_4_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD0_4] : 1'b1);
   assign i2c_scl_o[1] =
-    (scl1_sel == 2 ? inout_from_pins_i[INOUT_PIN_SCL1] : 1'b1) &
-    (rph_g3_scl_sel == 2 ? inout_from_pins_i[INOUT_PIN_RPH_G3_SCL] : 1'b1) &
-    (mb6_sel == 2 ? inout_from_pins_i[INOUT_PIN_MB6] : 1'b1) &
-    (pmod1_3_sel == 4 ? inout_from_pins_i[INOUT_PIN_PMOD1_3] : 1'b1);
+    (scl1_sel == $bits(scl1_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SCL1] : 1'b1) &
+    (rph_g3_scl_sel == $bits(rph_g3_scl_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G3_SCL] : 1'b1) &
+    (mb6_sel == $bits(mb6_sel)'(2) ? inout_from_pins_i[INOUT_PIN_MB6] : 1'b1) &
+    (pmod1_3_sel == $bits(pmod1_3_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD1_3] : 1'b1);
   assign i2c_sda_o[1] =
-    (sda1_sel == 2 ? inout_from_pins_i[INOUT_PIN_SDA1] : 1'b1) &
-    (rph_g2_sda_sel == 2 ? inout_from_pins_i[INOUT_PIN_RPH_G2_SDA] : 1'b1) &
-    (mb5_sel == 2 ? inout_from_pins_i[INOUT_PIN_MB5] : 1'b1) &
-    (pmod1_4_sel == 4 ? inout_from_pins_i[INOUT_PIN_PMOD1_4] : 1'b1);
+    (sda1_sel == $bits(sda1_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SDA1] : 1'b1) &
+    (rph_g2_sda_sel == $bits(rph_g2_sda_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G2_SDA] : 1'b1) &
+    (mb5_sel == $bits(mb5_sel)'(2) ? inout_from_pins_i[INOUT_PIN_MB5] : 1'b1) &
+    (pmod1_4_sel == $bits(pmod1_4_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD1_4] : 1'b1);
 endmodule
diff --git a/rtl/templates/pinmux.sv.tpl b/rtl/templates/pinmux.sv.tpl
index 7ceeec48c..ebdcafec4 100644
--- a/rtl/templates/pinmux.sv.tpl
+++ b/rtl/templates/pinmux.sv.tpl
@@ -181,7 +181,7 @@ module pinmux
   % for block_io, default_value, operator, pins_and_select_values in combined_input_block_ios:
   assign ${block_io.uid.block}_${block_io.uid.io}_o[${block_io.uid.instance}] =
     % for idx, (pin, select_value) in enumerate(pins_and_select_values):
-    (${pin.name}_sel == ${select_value} ? ${pin.direction_prefix}from_pins_i[${pin.idx_param}] : ${default_value})${operator if idx < len(pins_and_select_values) - 1 else ';'}
+    (${pin.name}_sel == $bits(${pin.name}_sel)'(${select_value}) ? ${pin.direction_prefix}from_pins_i[${pin.idx_param}] : ${default_value})${operator if idx < len(pins_and_select_values) - 1 else ';'}
     % endfor
   % endfor
 endmodule

From bec0c197c008e22e52794cd2901b6ce9e03b81f9 Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Thu, 31 Oct 2024 19:12:00 +0000
Subject: [PATCH 04/21] pinmux: Added remaining devices to the headers and pmod

---
 data/top_config.toml               | 149 +++++---
 data/xbar_main_generated.hjson     |  28 --
 doc/ip/pinmux/README.md            |  88 +++--
 rtl/bus/sonata_xbar_main.sv        |   4 -
 rtl/bus/tl_main_pkg.sv             |  26 +-
 rtl/bus/xbar_main.sv               | 298 +++++++--------
 rtl/system/pinmux.sv               | 559 ++++++++++++++---------------
 rtl/system/sonata_pkg.sv           |   2 +-
 sw/cheri/common/platform-pinmux.hh |  45 ++-
 9 files changed, 586 insertions(+), 613 deletions(-)

diff --git a/data/top_config.toml b/data/top_config.toml
index 10db5f47a..13a787c9f 100644
--- a/data/top_config.toml
+++ b/data/top_config.toml
@@ -22,7 +22,7 @@ xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
 
 [[blocks]]
 name = "uart"
-instances = 5
+instances = 3
 ios = [
   { name = "rx", type = "input", default = 1 },
   { name = "tx", type = "output" },
@@ -73,11 +73,11 @@ block_ios = [{ block = "uart", instance = 1, io = "rx" }]
 
 [[pins]]
 name = "rs232_tx"
-block_ios = [{ block = "uart", instance = 4, io = "tx" }]
+block_ios = [{ block = "uart", instance = 2, io = "tx" }]
 
 [[pins]]
 name = "rs232_rx"
-block_ios = [{ block = "uart", instance = 4, io = "rx" }]
+block_ios = [{ block = "uart", instance = 2, io = "rx" }]
 
 ## QWIIC (Sparkfun) buses
 [[pins]]
@@ -189,100 +189,110 @@ block_ios = [{block = "gpio", instance = 0, io = "ios", io_index = 6}]
 [[pins]]
 name = "rph_g7_ce1"
 block_ios = [
-  {block = "spi", instance = 3, io = "cs", io_index = 1},
+  {block = "spi", instance = 2, io = "cs", io_index = 0},
   {block = "gpio", instance = 0, io = "ios", io_index = 7},
 ]
 
 [[pins]]
 name = "rph_g8_ce0"
 block_ios = [
-  {block = "spi", instance = 3, io = "cs", io_index = 0},
+  {block = "spi", instance = 2, io = "cs", io_index = 1},
   {block = "gpio", instance = 0, io = "ios", io_index = 8},
 ]
 
 [[pins]]
 name = "rph_g9_cipo"
 block_ios = [
-  {block = "spi", instance = 3, io = "cipo"},
+  {block = "spi", instance = 2, io = "cipo"},
   {block = "gpio", instance = 0, io = "ios", io_index = 9},
 ]
 
 [[pins]]
 name = "rph_g10_copi"
 block_ios = [
-  {block = "spi", instance = 3, io = "copi"},
+  {block = "spi", instance = 2, io = "copi"},
   {block = "gpio", instance = 0, io = "ios", io_index = 10},
 ]
 
 [[pins]]
 name = "rph_g11_sclk"
 block_ios = [
-  {block = "spi", instance = 3, io = "sclk"},
+  {block = "spi", instance = 2, io = "sclk"},
   {block = "gpio", instance = 0, io = "ios", io_index = 11},
 ]
 
 [[pins]]
 name = "rph_g12"
-block_ios = [{block = "gpio", instance = 0, io = "ios", io_index = 12}]
+block_ios = [
+  {block = "gpio", instance = 0, io = "ios", io_index = 12},
+  {block = "pwm", instance = 0, io = "out", io_index = 0},
+]
 
 [[pins]]
 name = "rph_g13"
-block_ios = [{block = "gpio", instance = 0, io = "ios", io_index = 13}]
+block_ios = [
+  {block = "gpio", instance = 0, io = "ios", io_index = 13},
+  {block = "pwm", instance = 0, io = "out", io_index = 1},
+]
 
 [[pins]]
 name = "rph_txd0"
 block_ios = [
-  {block = "uart", instance = 2, io = "tx"},
+  {block = "uart", instance = 1, io = "tx"},
   {block = "gpio", instance = 0, io = "ios", io_index = 14},
 ]
 
 [[pins]]
 name = "rph_rxd0"
 block_ios = [
-  {block = "uart", instance = 2, io = "rx"},
+  {block = "uart", instance = 1, io = "rx"},
   {block = "gpio", instance = 0, io = "ios", io_index = 15},
 ]
 
 [[pins]]
 name = "rph_g16_ce2"
 block_ios = [
-  {block = "spi", instance = 4, io = "cs", io_index = 2},
+  {block = "spi", instance = 3, io = "cs", io_index = 2},
   {block = "gpio", instance = 0, io = "ios", io_index = 16}
 ]
 
 [[pins]]
 name = "rph_g17"
 block_ios = [
-  {block = "spi", instance = 4, io = "cs", io_index = 1},
+  {block = "spi", instance = 3, io = "cs", io_index = 1},
   {block = "gpio", instance = 0, io = "ios", io_index = 17},
 ]
 
 [[pins]]
 name = "rph_g18"
 block_ios = [
-  {block = "spi", instance = 4, io = "cs", io_index = 0},
+  {block = "spi", instance = 3, io = "cs", io_index = 0},
   {block = "gpio", instance = 0, io = "ios", io_index = 18},
+  {block = "pwm", instance = 0, io = "out", io_index = 2},
 ]
 
 [[pins]]
 name = "rph_g19_cipo"
 block_ios = [
-  {block = "spi", instance = 4, io = "cipo"},
+  {block = "spi", instance = 3, io = "cipo"},
   {block = "gpio", instance = 0, io = "ios", io_index = 19},
+  {block = "pwm", instance = 0, io = "out", io_index = 3},
 ]
 
 [[pins]]
 name = "rph_g20_copi"
 block_ios = [
-  {block = "spi", instance = 4, io = "copi"},
+  {block = "spi", instance = 3, io = "copi"},
   {block = "gpio", instance = 0, io = "ios", io_index = 20},
+  {block = "pwm", instance = 0, io = "out", io_index = 4},
 ]
 
 [[pins]]
 name = "rph_g21_sclk"
 block_ios = [
-  {block = "spi", instance = 4, io = "sclk"},
+  {block = "spi", instance = 3, io = "sclk"},
   {block = "gpio", instance = 0, io = "ios", io_index = 21},
+  {block = "pwm", instance = 0, io = "out", io_index = 5},
 ]
 
 [[pins]]
@@ -312,13 +322,17 @@ block_ios = [{block = "gpio", instance = 0, io = "ios", io_index = 27}]
 ## Arduino Shield
 [[pins]]
 name = "ah_tmpio0"
-block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 0},
-             {block = "uart", instance = 3, io = "rx"}]
+block_ios = [
+  {block = "uart", instance = 1, io = "rx"},
+  {block = "gpio", instance = 1, io = "ios", io_index = 0},
+]
 
 [[pins]]
 name = "ah_tmpio1"
-block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 1},
-             {block = "uart", instance = 3, io = "tx"}]
+block_ios = [
+  {block = "uart", instance = 1, io = "tx"},
+  {block = "gpio", instance = 1, io = "ios", io_index = 1},
+]
 
 [[pins]]
 name = "ah_tmpio2"
@@ -326,7 +340,10 @@ block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 2}]
 
 [[pins]]
 name = "ah_tmpio3"
-block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 3}]
+block_ios = [
+  {block = "gpio", instance = 1, io = "ios", io_index = 3},
+  {block = "pwm", instance = 0, io = "out", io_index = 0},
+]
 
 [[pins]]
 name = "ah_tmpio4"
@@ -334,11 +351,17 @@ block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 4}]
 
 [[pins]]
 name = "ah_tmpio5"
-block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 5}]
+block_ios = [
+  {block = "gpio", instance = 1, io = "ios", io_index = 5},
+  {block = "pwm", instance = 0, io = "out", io_index = 1},
+]
 
 [[pins]]
 name = "ah_tmpio6"
-block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 6}]
+block_ios = [
+  {block = "gpio", instance = 1, io = "ios", io_index = 6}
+  {block = "pwm", instance = 0, io = "out", io_index = 2},
+]
 
 [[pins]]
 name = "ah_tmpio7"
@@ -350,33 +373,38 @@ block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 8}]
 
 [[pins]]
 name = "ah_tmpio9"
-block_ios = [{block = "gpio", instance = 1, io = "ios", io_index = 9}]
+block_ios = [
+  {block = "gpio", instance = 1, io = "ios", io_index = 9},
+  {block = "pwm", instance = 0, io = "out", io_index = 2},
+]
 
 [[pins]]
 name = "ah_tmpio10"
 block_ios = [
-  {block = "spi", instance = 3, io = "cs", io_index = 2},
+  {block = "spi", instance = 2, io = "cs", io_index = 3},
   {block = "gpio", instance = 1, io = "ios", io_index = 10},
+  {block = "pwm", instance = 0, io = "out", io_index = 4},
 ]
 
 [[pins]]
 name = "ah_tmpio11"
 block_ios = [
-  {block = "spi", instance = 3, io = "copi"},
+  {block = "spi", instance = 2, io = "copi"},
   {block = "gpio", instance = 1, io = "ios", io_index = 11},
+  {block = "pwm", instance = 0, io = "out", io_index = 5},
 ]
 
 [[pins]]
 name = "ah_tmpio12"
 block_ios = [
-  {block = "spi", instance = 3, io = "cipo"},
+  {block = "spi", instance = 2, io = "cipo"},
   {block = "gpio", instance = 1, io = "ios", io_index = 12},
 ]
 
 [[pins]]
 name = "ah_tmpio13"
 block_ios = [
-  {block = "spi", instance = 3, io = "sclk"},
+  {block = "spi", instance = 2, io = "sclk"},
   {block = "gpio", instance = 1, io = "ios", io_index = 13},
 ]
 
@@ -384,19 +412,19 @@ block_ios = [
 # mb0 is reset and already connected to a general purpose output.
 [[pins]]
 name = "mb1"
-block_ios = [{block = "spi", instance = 4, io = "cs", io_index = 3}]
+block_ios = [{block = "spi", instance = 3, io = "cs", io_index = 3}]
 
 [[pins]]
 name = "mb2"
-block_ios = [{block = "spi", instance = 4, io = "sclk"}]
+block_ios = [{block = "spi", instance = 3, io = "sclk"}]
 
 [[pins]]
 name = "mb3"
-block_ios = [{block = "spi", instance = 4, io = "cipo"}]
+block_ios = [{block = "spi", instance = 3, io = "cipo"}]
 
 [[pins]]
 name = "mb4"
-block_ios = [{block = "spi", instance = 4, io = "copi"}]
+block_ios = [{block = "spi", instance = 3, io = "copi"}]
 
 [[pins]]
 name = "mb5"
@@ -408,12 +436,11 @@ block_ios = [{block = "i2c", instance = 1, io = "scl"}]
 
 [[pins]]
 name = "mb7"
-block_ios = [{block = "uart", instance = 3, io = "tx"}]
+block_ios = [{block = "uart", instance = 1, io = "tx"}]
 
 [[pins]]
 name = "mb8"
-block_ios = [{block = "uart", instance = 3, io = "rx"}]
-# mb9 is interrupt and already connected to a general purpose input.
+block_ios = [{block = "uart", instance = 1, io = "rx"}]
 
 [[pins]]
 name = "mb10"
@@ -432,24 +459,25 @@ name = "pmod0_2"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 1},
   {block = "spi", instance = 2, io = "copi"},
-  {block = "uart", instance = 2, io = "tx"},
+  {block = "pwm", instance = 0, io = "out", io_index = 1},
+  {block = "uart", instance = 1, io = "tx"},
 ]
 
 [[pins]]
 name = "pmod0_3"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 2},
-  {block = "i2c", instance = 0, io = "scl"},
   {block = "spi", instance = 2, io = "cipo"},
-  {block = "uart", instance = 2, io = "rx"},
+  {block = "i2c", instance = 0, io = "scl"},
+  {block = "uart", instance = 1, io = "rx"},
 ]
 
 [[pins]]
 name = "pmod0_4"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 3},
-  {block = "i2c", instance = 0, io = "sda"},
   {block = "spi", instance = 2, io = "sclk"},
+  {block = "i2c", instance = 0, io = "sda"},
 ]
 
 [[pins]]
@@ -458,15 +486,24 @@ block_ios = [{block = "gpio", instance = 2, io = "ios", io_index = 4}]
 
 [[pins]]
 name = "pmod0_6"
-block_ios = [{block = "gpio", instance = 2, io = "ios", io_index = 5}]
+block_ios = [
+  {block = "gpio", instance = 2, io = "ios", io_index = 5},
+  {block = "pwm", instance = 0, io = "out", io_index = 2},
+]
 
 [[pins]]
 name = "pmod0_7"
-block_ios = [{block = "gpio", instance = 2, io = "ios", io_index = 6}]
+block_ios = [
+  {block = "gpio", instance = 2, io = "ios", io_index = 6},
+  {block = "spi", instance = 2, io = "cs", io_index = 1},
+]
 
 [[pins]]
 name = "pmod0_8"
-block_ios = [{block = "gpio", instance = 2, io = "ios", io_index = 7}]
+block_ios = [
+  {block = "gpio", instance = 2, io = "ios", io_index = 7},
+  {block = "spi", instance = 2, io = "cs", io_index = 2},
+]
 
 [[pins]]
 name = "pmod1_1"
@@ -480,24 +517,25 @@ name = "pmod1_2"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 1},
   {block = "spi", instance = 3, io = "copi"},
-  {block = "uart", instance = 3, io = "tx"},
+  {block = "pwm", instance = 0, io = "out", io_index = 3},
+  {block = "uart", instance = 2, io = "tx"},
 ]
 
 [[pins]]
 name = "pmod1_3"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 2},
-  {block = "i2c", instance = 1, io = "scl"},
   {block = "spi", instance = 3, io = "cipo"},
-  {block = "uart", instance = 3, io = "rx"},
+  {block = "i2c", instance = 1, io = "scl"},
+  {block = "uart", instance = 2, io = "rx"},
 ]
 
 [[pins]]
 name = "pmod1_4"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 3},
-  {block = "i2c", instance = 1, io = "sda"},
   {block = "spi", instance = 3, io = "sclk"},
+  {block = "i2c", instance = 1, io = "sda"},
 ]
 
 [[pins]]
@@ -506,15 +544,24 @@ block_ios = [{block = "gpio", instance = 3, io = "ios", io_index = 4}]
 
 [[pins]]
 name = "pmod1_6"
-block_ios = [{block = "gpio", instance = 3, io = "ios", io_index = 5}]
+block_ios = [
+  {block = "gpio", instance = 3, io = "ios", io_index = 5},
+  {block = "pwm", instance = 0, io = "out", io_index = 4},
+]
 
 [[pins]]
 name = "pmod1_7"
-block_ios = [{block = "gpio", instance = 3, io = "ios", io_index = 6}]
+block_ios = [
+  {block = "gpio", instance = 3, io = "ios", io_index = 6},
+  {block = "spi", instance = 3, io = "cs", io_index = 1},
+]
 
 [[pins]]
 name = "pmod1_8"
-block_ios = [{block = "gpio", instance = 3, io = "ios", io_index = 7}]
+block_ios = [
+  {block = "gpio", instance = 3, io = "ios", io_index = 7},
+  {block = "spi", instance = 3, io = "cs", io_index = 2},
+]
 
 ## MicroSD card slot
 [[pins]]
diff --git a/data/xbar_main_generated.hjson b/data/xbar_main_generated.hjson
index 120bbaba7..c9a8f18e5 100644
--- a/data/xbar_main_generated.hjson
+++ b/data/xbar_main_generated.hjson
@@ -195,32 +195,6 @@
       req_fifo_pass: false,
       rsp_fifo_pass: false,
     },
-    { name:  "uart3",
-      type:  "device",
-      clock: "clk_sys_i",
-      reset: "rst_sys_ni",
-      xbar:  false,
-      addr_range: [{
-        base_addr: "0x80103000",
-        size_byte: "0x1000",
-      }],
-      pipeline: true,
-      req_fifo_pass: false,
-      rsp_fifo_pass: false,
-    },
-    { name:  "uart4",
-      type:  "device",
-      clock: "clk_sys_i",
-      reset: "rst_sys_ni",
-      xbar:  false,
-      addr_range: [{
-        base_addr: "0x80104000",
-        size_byte: "0x1000",
-      }],
-      pipeline: true,
-      req_fifo_pass: false,
-      rsp_fifo_pass: false,
-    },
     { name:  "i2c0",
       type:  "device",
       clock: "clk_sys_i",
@@ -338,8 +312,6 @@
       "uart0",
       "uart1",
       "uart2",
-      "uart3",
-      "uart4",
       "i2c0",
       "i2c1",
       "spi0",
diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index e45e7bbeb..90f22a3cf 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -14,7 +14,7 @@ The default value for all of these selectors is `'b10`.
 |---------|------------|------------------------|
 | 0x000 | `ser0_tx` | 0, `uart[0].tx` |
 | 0x001 | `ser1_tx` | 0, `uart[1].tx` |
-| 0x002 | `rs232_tx` | 0, `uart[4].tx` |
+| 0x002 | `rs232_tx` | 0, `uart[2].tx` |
 | 0x003 | `scl0` | 0, `i2c[0].scl` |
 | 0x004 | `sda0` | 0, `i2c[0].sda` |
 | 0x005 | `scl1` | 0, `i2c[1].scl` |
@@ -35,21 +35,21 @@ The default value for all of these selectors is `'b10`.
 | 0x014 | `rph_g4` | 0, `gpio[0].ios[4]` |
 | 0x015 | `rph_g5` | 0, `gpio[0].ios[5]` |
 | 0x016 | `rph_g6` | 0, `gpio[0].ios[6]` |
-| 0x017 | `rph_g7_ce1` | 0, `spi[3].cs[1]`, `gpio[0].ios[7]` |
-| 0x018 | `rph_g8_ce0` | 0, `spi[3].cs[0]`, `gpio[0].ios[8]` |
+| 0x017 | `rph_g7_ce1` | 0, `spi[2].cs[0]`, `gpio[0].ios[7]` |
+| 0x018 | `rph_g8_ce0` | 0, `spi[2].cs[1]`, `gpio[0].ios[8]` |
 | 0x019 | `rph_g9_cipo` | 0, `gpio[0].ios[9]` |
-| 0x01a | `rph_g10_copi` | 0, `spi[3].copi`, `gpio[0].ios[10]` |
-| 0x01b | `rph_g11_sclk` | 0, `spi[3].sclk`, `gpio[0].ios[11]` |
-| 0x01c | `rph_g12` | 0, `gpio[0].ios[12]` |
-| 0x01d | `rph_g13` | 0, `gpio[0].ios[13]` |
-| 0x01e | `rph_txd0` | 0, `uart[2].tx`, `gpio[0].ios[14]` |
+| 0x01a | `rph_g10_copi` | 0, `spi[2].copi`, `gpio[0].ios[10]` |
+| 0x01b | `rph_g11_sclk` | 0, `spi[2].sclk`, `gpio[0].ios[11]` |
+| 0x01c | `rph_g12` | 0, `gpio[0].ios[12]`, `pwm_out[0]` |
+| 0x01d | `rph_g13` | 0, `gpio[0].ios[13]`, `pwm_out[1]` |
+| 0x01e | `rph_txd0` | 0, `uart[1].tx`, `gpio[0].ios[14]` |
 | 0x01f | `rph_rxd0` | 0, `gpio[0].ios[15]` |
-| 0x020 | `rph_g16_ce2` | 0, `spi[4].cs[2]`, `gpio[0].ios[16]` |
-| 0x021 | `rph_g17` | 0, `spi[4].cs[1]`, `gpio[0].ios[17]` |
-| 0x022 | `rph_g18` | 0, `spi[4].cs[0]`, `gpio[0].ios[18]` |
-| 0x023 | `rph_g19_cipo` | 0, `gpio[0].ios[19]` |
-| 0x024 | `rph_g20_copi` | 0, `spi[4].copi`, `gpio[0].ios[20]` |
-| 0x025 | `rph_g21_sclk` | 0, `spi[4].sclk`, `gpio[0].ios[21]` |
+| 0x020 | `rph_g16_ce2` | 0, `spi[3].cs[2]`, `gpio[0].ios[16]` |
+| 0x021 | `rph_g17` | 0, `spi[3].cs[1]`, `gpio[0].ios[17]` |
+| 0x022 | `rph_g18` | 0, `spi[3].cs[0]`, `gpio[0].ios[18]`, `pwm_out[2]` |
+| 0x023 | `rph_g19_cipo` | 0, `gpio[0].ios[19]`, `pwm_out[3]` |
+| 0x024 | `rph_g20_copi` | 0, `spi[3].copi`, `gpio[0].ios[20]`, `pwm_out[4]` |
+| 0x025 | `rph_g21_sclk` | 0, `spi[3].sclk`, `gpio[0].ios[21]`, `pwm_out[5]` |
 | 0x026 | `rph_g22` | 0, `gpio[0].ios[22]` |
 | 0x027 | `rph_g23` | 0, `gpio[0].ios[23]` |
 | 0x028 | `rph_g24` | 0, `gpio[0].ios[24]` |
@@ -57,42 +57,42 @@ The default value for all of these selectors is `'b10`.
 | 0x02a | `rph_g26` | 0, `gpio[0].ios[26]` |
 | 0x02b | `rph_g27` | 0, `gpio[0].ios[27]` |
 | 0x02c | `ah_tmpio0` | 0, `gpio[1].ios[0]` |
-| 0x02d | `ah_tmpio1` | 0, `gpio[1].ios[1]`, `uart[3].tx` |
+| 0x02d | `ah_tmpio1` | 0, `uart[1].tx`, `gpio[1].ios[1]` |
 | 0x02e | `ah_tmpio2` | 0, `gpio[1].ios[2]` |
-| 0x02f | `ah_tmpio3` | 0, `gpio[1].ios[3]` |
+| 0x02f | `ah_tmpio3` | 0, `gpio[1].ios[3]`, `pwm_out[0]` |
 | 0x030 | `ah_tmpio4` | 0, `gpio[1].ios[4]` |
-| 0x031 | `ah_tmpio5` | 0, `gpio[1].ios[5]` |
-| 0x032 | `ah_tmpio6` | 0, `gpio[1].ios[6]` |
+| 0x031 | `ah_tmpio5` | 0, `gpio[1].ios[5]`, `pwm_out[1]` |
+| 0x032 | `ah_tmpio6` | 0, `gpio[1].ios[6]`, `pwm_out[2]` |
 | 0x033 | `ah_tmpio7` | 0, `gpio[1].ios[7]` |
 | 0x034 | `ah_tmpio8` | 0, `gpio[1].ios[8]` |
-| 0x035 | `ah_tmpio9` | 0, `gpio[1].ios[9]` |
-| 0x036 | `ah_tmpio10` | 0, `spi[3].cs[2]`, `gpio[1].ios[10]` |
-| 0x037 | `ah_tmpio11` | 0, `spi[3].copi`, `gpio[1].ios[11]` |
+| 0x035 | `ah_tmpio9` | 0, `gpio[1].ios[9]`, `pwm_out[2]` |
+| 0x036 | `ah_tmpio10` | 0, `spi[2].cs[3]`, `gpio[1].ios[10]`, `pwm_out[4]` |
+| 0x037 | `ah_tmpio11` | 0, `spi[2].copi`, `gpio[1].ios[11]`, `pwm_out[5]` |
 | 0x038 | `ah_tmpio12` | 0, `gpio[1].ios[12]` |
-| 0x039 | `ah_tmpio13` | 0, `spi[3].sclk`, `gpio[1].ios[13]` |
-| 0x03a | `mb1` | 0, `spi[4].cs[3]` |
-| 0x03b | `mb2` | 0, `spi[4].sclk` |
-| 0x03c | `mb4` | 0, `spi[4].copi` |
+| 0x039 | `ah_tmpio13` | 0, `spi[2].sclk`, `gpio[1].ios[13]` |
+| 0x03a | `mb1` | 0, `spi[3].cs[3]` |
+| 0x03b | `mb2` | 0, `spi[3].sclk` |
+| 0x03c | `mb4` | 0, `spi[3].copi` |
 | 0x03d | `mb5` | 0, `i2c[1].sda` |
 | 0x03e | `mb6` | 0, `i2c[1].scl` |
-| 0x03f | `mb7` | 0, `uart[3].tx` |
+| 0x03f | `mb7` | 0, `uart[1].tx` |
 | 0x040 | `mb10` | 0, `pwm_out[0]` |
 | 0x041 | `pmod0_1` | 0, `gpio[2].ios[0]`, `spi[2].cs[0]` |
-| 0x042 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[2].copi`, `uart[2].tx` |
+| 0x042 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[2].copi`, `pwm_out[1]`, `uart[1].tx` |
 | 0x043 | `pmod0_3` | 0, `gpio[2].ios[2]`, `i2c[0].scl` |
-| 0x044 | `pmod0_4` | 0, `gpio[2].ios[3]`, `i2c[0].sda`, `spi[2].sclk` |
+| 0x044 | `pmod0_4` | 0, `gpio[2].ios[3]`, `spi[2].sclk`, `i2c[0].sda` |
 | 0x045 | `pmod0_5` | 0, `gpio[2].ios[4]` |
-| 0x046 | `pmod0_6` | 0, `gpio[2].ios[5]` |
-| 0x047 | `pmod0_7` | 0, `gpio[2].ios[6]` |
-| 0x048 | `pmod0_8` | 0, `gpio[2].ios[7]` |
+| 0x046 | `pmod0_6` | 0, `gpio[2].ios[5]`, `pwm_out[2]` |
+| 0x047 | `pmod0_7` | 0, `gpio[2].ios[6]`, `spi[2].cs[1]` |
+| 0x048 | `pmod0_8` | 0, `gpio[2].ios[7]`, `spi[2].cs[2]` |
 | 0x049 | `pmod1_1` | 0, `gpio[3].ios[0]`, `spi[3].cs[0]` |
-| 0x04a | `pmod1_2` | 0, `gpio[3].ios[1]`, `spi[3].copi`, `uart[3].tx` |
+| 0x04a | `pmod1_2` | 0, `gpio[3].ios[1]`, `spi[3].copi`, `pwm_out[3]`, `uart[2].tx` |
 | 0x04b | `pmod1_3` | 0, `gpio[3].ios[2]`, `i2c[1].scl` |
-| 0x04c | `pmod1_4` | 0, `gpio[3].ios[3]`, `i2c[1].sda`, `spi[3].sclk` |
+| 0x04c | `pmod1_4` | 0, `gpio[3].ios[3]`, `spi[3].sclk`, `i2c[1].sda` |
 | 0x04d | `pmod1_5` | 0, `gpio[3].ios[4]` |
-| 0x04e | `pmod1_6` | 0, `gpio[3].ios[5]` |
-| 0x04f | `pmod1_7` | 0, `gpio[3].ios[6]` |
-| 0x050 | `pmod1_8` | 0, `gpio[3].ios[7]` |
+| 0x04e | `pmod1_6` | 0, `gpio[3].ios[5]`, `pwm_out[4]` |
+| 0x04f | `pmod1_7` | 0, `gpio[3].ios[6]`, `spi[3].cs[1]` |
+| 0x050 | `pmod1_8` | 0, `gpio[3].ios[7]`, `spi[3].cs[2]` |
 | 0x051 | `microsd_clk` | 0, `spi[3].sclk` |
 | 0x052 | `microsd_cmd` | 0, `spi[3].copi` |
 | 0x053 | `microsd_dat3` | 0, `spi[3].cs[3]` |
@@ -230,15 +230,13 @@ Besides the output pin selectors, there are also selectors for which pin should
 | 0x87e | `gpio[3].ios[30]` | 0, 0 |
 | 0x87f | `gpio[3].ios[31]` | 0, 0 |
 | 0x880 | `uart[0].rx` | 1, `ser0_rx` |
-| 0x881 | `uart[1].rx` | 1, `ser1_rx` |
-| 0x882 | `uart[2].rx` | 1, `rph_rxd0`, `pmod0_3` |
-| 0x883 | `uart[3].rx` | 1, `ah_tmpio0`, `mb8`, `pmod1_3` |
-| 0x884 | `uart[4].rx` | 1, `rs232_rx` |
-| 0x885 | `spi[0].cipo` | 0, `appspi_d1` |
-| 0x886 | `spi[1].cipo` | 0, 0 |
-| 0x887 | `spi[2].cipo` | 0, `ethmac_cipo`, `pmod0_3` |
-| 0x888 | `spi[3].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod1_3`, `microsd_dat0` |
-| 0x889 | `spi[4].cipo` | 0, `rph_g19_cipo`, `mb3` |
+| 0x881 | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
+| 0x882 | `uart[2].rx` | 1, `rs232_rx`, `pmod1_3` |
+| 0x883 | `spi[0].cipo` | 0, `appspi_d1` |
+| 0x884 | `spi[1].cipo` | 0, 0 |
+| 0x885 | `spi[2].cipo` | 0, `ethmac_cipo`, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
+| 0x886 | `spi[3].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3`, `microsd_dat0` |
+| 0x887 | `spi[4].cipo` | 0, 0 |
 
 ## Regeneration
 
diff --git a/rtl/bus/sonata_xbar_main.sv b/rtl/bus/sonata_xbar_main.sv
index bdc964572..bf80371b2 100644
--- a/rtl/bus/sonata_xbar_main.sv
+++ b/rtl/bus/sonata_xbar_main.sv
@@ -97,10 +97,6 @@ module sonata_xbar_main
     .tl_uart1_i        (tl_uart_i[1]),
     .tl_uart2_o        (tl_uart_o[2]),
     .tl_uart2_i        (tl_uart_i[2]),
-    .tl_uart3_o        (tl_uart_o[3]),
-    .tl_uart3_i        (tl_uart_i[3]),
-    .tl_uart4_o        (tl_uart_o[4]),
-    .tl_uart4_i        (tl_uart_i[4]),
     .tl_i2c0_o        (tl_i2c_o[0]),
     .tl_i2c0_i        (tl_i2c_i[0]),
     .tl_i2c1_o        (tl_i2c_o[1]),
diff --git a/rtl/bus/tl_main_pkg.sv b/rtl/bus/tl_main_pkg.sv
index ca7d6c4f7..7f010decf 100644
--- a/rtl/bus/tl_main_pkg.sv
+++ b/rtl/bus/tl_main_pkg.sv
@@ -20,8 +20,6 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_SPACE_UART0       = 32'h 80100000;
   localparam logic [31:0] ADDR_SPACE_UART1       = 32'h 80101000;
   localparam logic [31:0] ADDR_SPACE_UART2       = 32'h 80102000;
-  localparam logic [31:0] ADDR_SPACE_UART3       = 32'h 80103000;
-  localparam logic [31:0] ADDR_SPACE_UART4       = 32'h 80104000;
   localparam logic [31:0] ADDR_SPACE_I2C0        = 32'h 80200000;
   localparam logic [31:0] ADDR_SPACE_I2C1        = 32'h 80201000;
   localparam logic [31:0] ADDR_SPACE_SPI0        = 32'h 80300000;
@@ -46,8 +44,6 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_MASK_UART0       = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_UART1       = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_UART2       = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_UART3       = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_UART4       = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_I2C0        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_I2C1        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_SPI0        = 32'h 00000fff;
@@ -59,7 +55,7 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_MASK_RV_PLIC     = 32'h 03ffffff;
 
   localparam int N_HOST   = 2;
-  localparam int N_DEVICE = 25;
+  localparam int N_DEVICE = 23;
 
   typedef enum int {
     TlSram = 0,
@@ -76,17 +72,15 @@ package tl_main_pkg;
     TlUart0 = 11,
     TlUart1 = 12,
     TlUart2 = 13,
-    TlUart3 = 14,
-    TlUart4 = 15,
-    TlI2C0 = 16,
-    TlI2C1 = 17,
-    TlSpi0 = 18,
-    TlSpi1 = 19,
-    TlSpi2 = 20,
-    TlSpi3 = 21,
-    TlSpi4 = 22,
-    TlUsbdev = 23,
-    TlRvPlic = 24
+    TlI2C0 = 14,
+    TlI2C1 = 15,
+    TlSpi0 = 16,
+    TlSpi1 = 17,
+    TlSpi2 = 18,
+    TlSpi3 = 19,
+    TlSpi4 = 20,
+    TlUsbdev = 21,
+    TlRvPlic = 22
   } tl_device_e;
 
   typedef enum int {
diff --git a/rtl/bus/xbar_main.sv b/rtl/bus/xbar_main.sv
index 927ff2c1e..b50cc690f 100644
--- a/rtl/bus/xbar_main.sv
+++ b/rtl/bus/xbar_main.sv
@@ -7,8 +7,8 @@
 //
 // Interconnect
 // ibex_lsu
-//   -> s1n_27
-//     -> sm1_28
+//   -> s1n_25
+//     -> sm1_26
 //       -> sram
 //     -> hyperram
 //     -> rev_tag
@@ -23,8 +23,6 @@
 //     -> uart0
 //     -> uart1
 //     -> uart2
-//     -> uart3
-//     -> uart4
 //     -> i2c0
 //     -> i2c1
 //     -> spi0
@@ -32,11 +30,11 @@
 //     -> spi2
 //     -> spi3
 //     -> spi4
-//     -> asf_29
+//     -> asf_27
 //       -> usbdev
 //     -> rv_plic
 // dbg_host
-//   -> sm1_28
+//   -> sm1_26
 //     -> sram
 
 module xbar_main (
@@ -80,10 +78,6 @@ module xbar_main (
   input  tlul_pkg::tl_d2h_t tl_uart1_i,
   output tlul_pkg::tl_h2d_t tl_uart2_o,
   input  tlul_pkg::tl_d2h_t tl_uart2_i,
-  output tlul_pkg::tl_h2d_t tl_uart3_o,
-  input  tlul_pkg::tl_d2h_t tl_uart3_i,
-  output tlul_pkg::tl_h2d_t tl_uart4_o,
-  input  tlul_pkg::tl_d2h_t tl_uart4_i,
   output tlul_pkg::tl_h2d_t tl_i2c0_o,
   input  tlul_pkg::tl_d2h_t tl_i2c0_i,
   output tlul_pkg::tl_h2d_t tl_i2c1_o,
@@ -114,219 +108,205 @@ module xbar_main (
   logic unused_scanmode;
   assign unused_scanmode = ^scanmode_i;
 
-  tl_h2d_t tl_s1n_27_us_h2d ;
-  tl_d2h_t tl_s1n_27_us_d2h ;
+  tl_h2d_t tl_s1n_25_us_h2d ;
+  tl_d2h_t tl_s1n_25_us_d2h ;
 
 
-  tl_h2d_t tl_s1n_27_ds_h2d [25];
-  tl_d2h_t tl_s1n_27_ds_d2h [25];
+  tl_h2d_t tl_s1n_25_ds_h2d [23];
+  tl_d2h_t tl_s1n_25_ds_d2h [23];
 
   // Create steering signal
-  logic [4:0] dev_sel_s1n_27;
+  logic [4:0] dev_sel_s1n_25;
 
 
-  tl_h2d_t tl_sm1_28_us_h2d [2];
-  tl_d2h_t tl_sm1_28_us_d2h [2];
+  tl_h2d_t tl_sm1_26_us_h2d [2];
+  tl_d2h_t tl_sm1_26_us_d2h [2];
 
-  tl_h2d_t tl_sm1_28_ds_h2d ;
-  tl_d2h_t tl_sm1_28_ds_d2h ;
+  tl_h2d_t tl_sm1_26_ds_h2d ;
+  tl_d2h_t tl_sm1_26_ds_d2h ;
 
-  tl_h2d_t tl_asf_29_us_h2d ;
-  tl_d2h_t tl_asf_29_us_d2h ;
-  tl_h2d_t tl_asf_29_ds_h2d ;
-  tl_d2h_t tl_asf_29_ds_d2h ;
+  tl_h2d_t tl_asf_27_us_h2d ;
+  tl_d2h_t tl_asf_27_us_d2h ;
+  tl_h2d_t tl_asf_27_ds_h2d ;
+  tl_d2h_t tl_asf_27_ds_d2h ;
 
 
 
-  assign tl_sm1_28_us_h2d[0] = tl_s1n_27_ds_h2d[0];
-  assign tl_s1n_27_ds_d2h[0] = tl_sm1_28_us_d2h[0];
+  assign tl_sm1_26_us_h2d[0] = tl_s1n_25_ds_h2d[0];
+  assign tl_s1n_25_ds_d2h[0] = tl_sm1_26_us_d2h[0];
 
-  assign tl_hyperram_o = tl_s1n_27_ds_h2d[1];
-  assign tl_s1n_27_ds_d2h[1] = tl_hyperram_i;
+  assign tl_hyperram_o = tl_s1n_25_ds_h2d[1];
+  assign tl_s1n_25_ds_d2h[1] = tl_hyperram_i;
 
-  assign tl_rev_tag_o = tl_s1n_27_ds_h2d[2];
-  assign tl_s1n_27_ds_d2h[2] = tl_rev_tag_i;
+  assign tl_rev_tag_o = tl_s1n_25_ds_h2d[2];
+  assign tl_s1n_25_ds_d2h[2] = tl_rev_tag_i;
 
-  assign tl_gpio_o = tl_s1n_27_ds_h2d[3];
-  assign tl_s1n_27_ds_d2h[3] = tl_gpio_i;
+  assign tl_gpio_o = tl_s1n_25_ds_h2d[3];
+  assign tl_s1n_25_ds_d2h[3] = tl_gpio_i;
 
-  assign tl_pinmux_o = tl_s1n_27_ds_h2d[4];
-  assign tl_s1n_27_ds_d2h[4] = tl_pinmux_i;
+  assign tl_pinmux_o = tl_s1n_25_ds_h2d[4];
+  assign tl_s1n_25_ds_d2h[4] = tl_pinmux_i;
 
-  assign tl_system_info_o = tl_s1n_27_ds_h2d[5];
-  assign tl_s1n_27_ds_d2h[5] = tl_system_info_i;
+  assign tl_system_info_o = tl_s1n_25_ds_h2d[5];
+  assign tl_s1n_25_ds_d2h[5] = tl_system_info_i;
 
-  assign tl_rgbled_ctrl_o = tl_s1n_27_ds_h2d[6];
-  assign tl_s1n_27_ds_d2h[6] = tl_rgbled_ctrl_i;
+  assign tl_rgbled_ctrl_o = tl_s1n_25_ds_h2d[6];
+  assign tl_s1n_25_ds_d2h[6] = tl_rgbled_ctrl_i;
 
-  assign tl_hw_rev_o = tl_s1n_27_ds_h2d[7];
-  assign tl_s1n_27_ds_d2h[7] = tl_hw_rev_i;
+  assign tl_hw_rev_o = tl_s1n_25_ds_h2d[7];
+  assign tl_s1n_25_ds_d2h[7] = tl_hw_rev_i;
 
-  assign tl_xadc_o = tl_s1n_27_ds_h2d[8];
-  assign tl_s1n_27_ds_d2h[8] = tl_xadc_i;
+  assign tl_xadc_o = tl_s1n_25_ds_h2d[8];
+  assign tl_s1n_25_ds_d2h[8] = tl_xadc_i;
 
-  assign tl_timer_o = tl_s1n_27_ds_h2d[9];
-  assign tl_s1n_27_ds_d2h[9] = tl_timer_i;
+  assign tl_timer_o = tl_s1n_25_ds_h2d[9];
+  assign tl_s1n_25_ds_d2h[9] = tl_timer_i;
 
-  assign tl_pwm0_o = tl_s1n_27_ds_h2d[10];
-  assign tl_s1n_27_ds_d2h[10] = tl_pwm0_i;
+  assign tl_pwm0_o = tl_s1n_25_ds_h2d[10];
+  assign tl_s1n_25_ds_d2h[10] = tl_pwm0_i;
 
-  assign tl_uart0_o = tl_s1n_27_ds_h2d[11];
-  assign tl_s1n_27_ds_d2h[11] = tl_uart0_i;
+  assign tl_uart0_o = tl_s1n_25_ds_h2d[11];
+  assign tl_s1n_25_ds_d2h[11] = tl_uart0_i;
 
-  assign tl_uart1_o = tl_s1n_27_ds_h2d[12];
-  assign tl_s1n_27_ds_d2h[12] = tl_uart1_i;
+  assign tl_uart1_o = tl_s1n_25_ds_h2d[12];
+  assign tl_s1n_25_ds_d2h[12] = tl_uart1_i;
 
-  assign tl_uart2_o = tl_s1n_27_ds_h2d[13];
-  assign tl_s1n_27_ds_d2h[13] = tl_uart2_i;
+  assign tl_uart2_o = tl_s1n_25_ds_h2d[13];
+  assign tl_s1n_25_ds_d2h[13] = tl_uart2_i;
 
-  assign tl_uart3_o = tl_s1n_27_ds_h2d[14];
-  assign tl_s1n_27_ds_d2h[14] = tl_uart3_i;
+  assign tl_i2c0_o = tl_s1n_25_ds_h2d[14];
+  assign tl_s1n_25_ds_d2h[14] = tl_i2c0_i;
 
-  assign tl_uart4_o = tl_s1n_27_ds_h2d[15];
-  assign tl_s1n_27_ds_d2h[15] = tl_uart4_i;
+  assign tl_i2c1_o = tl_s1n_25_ds_h2d[15];
+  assign tl_s1n_25_ds_d2h[15] = tl_i2c1_i;
 
-  assign tl_i2c0_o = tl_s1n_27_ds_h2d[16];
-  assign tl_s1n_27_ds_d2h[16] = tl_i2c0_i;
+  assign tl_spi0_o = tl_s1n_25_ds_h2d[16];
+  assign tl_s1n_25_ds_d2h[16] = tl_spi0_i;
 
-  assign tl_i2c1_o = tl_s1n_27_ds_h2d[17];
-  assign tl_s1n_27_ds_d2h[17] = tl_i2c1_i;
+  assign tl_spi1_o = tl_s1n_25_ds_h2d[17];
+  assign tl_s1n_25_ds_d2h[17] = tl_spi1_i;
 
-  assign tl_spi0_o = tl_s1n_27_ds_h2d[18];
-  assign tl_s1n_27_ds_d2h[18] = tl_spi0_i;
+  assign tl_spi2_o = tl_s1n_25_ds_h2d[18];
+  assign tl_s1n_25_ds_d2h[18] = tl_spi2_i;
 
-  assign tl_spi1_o = tl_s1n_27_ds_h2d[19];
-  assign tl_s1n_27_ds_d2h[19] = tl_spi1_i;
+  assign tl_spi3_o = tl_s1n_25_ds_h2d[19];
+  assign tl_s1n_25_ds_d2h[19] = tl_spi3_i;
 
-  assign tl_spi2_o = tl_s1n_27_ds_h2d[20];
-  assign tl_s1n_27_ds_d2h[20] = tl_spi2_i;
+  assign tl_spi4_o = tl_s1n_25_ds_h2d[20];
+  assign tl_s1n_25_ds_d2h[20] = tl_spi4_i;
 
-  assign tl_spi3_o = tl_s1n_27_ds_h2d[21];
-  assign tl_s1n_27_ds_d2h[21] = tl_spi3_i;
+  assign tl_asf_27_us_h2d = tl_s1n_25_ds_h2d[21];
+  assign tl_s1n_25_ds_d2h[21] = tl_asf_27_us_d2h;
 
-  assign tl_spi4_o = tl_s1n_27_ds_h2d[22];
-  assign tl_s1n_27_ds_d2h[22] = tl_spi4_i;
+  assign tl_rv_plic_o = tl_s1n_25_ds_h2d[22];
+  assign tl_s1n_25_ds_d2h[22] = tl_rv_plic_i;
 
-  assign tl_asf_29_us_h2d = tl_s1n_27_ds_h2d[23];
-  assign tl_s1n_27_ds_d2h[23] = tl_asf_29_us_d2h;
+  assign tl_sm1_26_us_h2d[1] = tl_dbg_host_i;
+  assign tl_dbg_host_o = tl_sm1_26_us_d2h[1];
 
-  assign tl_rv_plic_o = tl_s1n_27_ds_h2d[24];
-  assign tl_s1n_27_ds_d2h[24] = tl_rv_plic_i;
+  assign tl_s1n_25_us_h2d = tl_ibex_lsu_i;
+  assign tl_ibex_lsu_o = tl_s1n_25_us_d2h;
 
-  assign tl_sm1_28_us_h2d[1] = tl_dbg_host_i;
-  assign tl_dbg_host_o = tl_sm1_28_us_d2h[1];
+  assign tl_sram_o = tl_sm1_26_ds_h2d;
+  assign tl_sm1_26_ds_d2h = tl_sram_i;
 
-  assign tl_s1n_27_us_h2d = tl_ibex_lsu_i;
-  assign tl_ibex_lsu_o = tl_s1n_27_us_d2h;
-
-  assign tl_sram_o = tl_sm1_28_ds_h2d;
-  assign tl_sm1_28_ds_d2h = tl_sram_i;
-
-  assign tl_usbdev_o = tl_asf_29_ds_h2d;
-  assign tl_asf_29_ds_d2h = tl_usbdev_i;
+  assign tl_usbdev_o = tl_asf_27_ds_h2d;
+  assign tl_asf_27_ds_d2h = tl_usbdev_i;
 
   always_comb begin
     // default steering to generate error response if address is not within the range
-    dev_sel_s1n_27 = 5'd25;
-    if ((tl_s1n_27_us_h2d.a_address &
+    dev_sel_s1n_25 = 5'd23;
+    if ((tl_s1n_25_us_h2d.a_address &
          ~(ADDR_MASK_SRAM)) == ADDR_SPACE_SRAM) begin
-      dev_sel_s1n_27 = 5'd0;
+      dev_sel_s1n_25 = 5'd0;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_HYPERRAM)) == ADDR_SPACE_HYPERRAM) begin
-      dev_sel_s1n_27 = 5'd1;
+      dev_sel_s1n_25 = 5'd1;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_REV_TAG)) == ADDR_SPACE_REV_TAG) begin
-      dev_sel_s1n_27 = 5'd2;
+      dev_sel_s1n_25 = 5'd2;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
-      dev_sel_s1n_27 = 5'd3;
+      dev_sel_s1n_25 = 5'd3;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
-      dev_sel_s1n_27 = 5'd4;
+      dev_sel_s1n_25 = 5'd4;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_SYSTEM_INFO)) == ADDR_SPACE_SYSTEM_INFO) begin
-      dev_sel_s1n_27 = 5'd5;
+      dev_sel_s1n_25 = 5'd5;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_RGBLED_CTRL)) == ADDR_SPACE_RGBLED_CTRL) begin
-      dev_sel_s1n_27 = 5'd6;
+      dev_sel_s1n_25 = 5'd6;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_HW_REV)) == ADDR_SPACE_HW_REV) begin
-      dev_sel_s1n_27 = 5'd7;
+      dev_sel_s1n_25 = 5'd7;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_XADC)) == ADDR_SPACE_XADC) begin
-      dev_sel_s1n_27 = 5'd8;
+      dev_sel_s1n_25 = 5'd8;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_TIMER)) == ADDR_SPACE_TIMER) begin
-      dev_sel_s1n_27 = 5'd9;
+      dev_sel_s1n_25 = 5'd9;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_PWM0)) == ADDR_SPACE_PWM0) begin
-      dev_sel_s1n_27 = 5'd10;
+      dev_sel_s1n_25 = 5'd10;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
-      dev_sel_s1n_27 = 5'd11;
+      dev_sel_s1n_25 = 5'd11;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
-      dev_sel_s1n_27 = 5'd12;
+      dev_sel_s1n_25 = 5'd12;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
-      dev_sel_s1n_27 = 5'd13;
-
-    end else if ((tl_s1n_27_us_h2d.a_address &
-                  ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
-      dev_sel_s1n_27 = 5'd14;
-
-    end else if ((tl_s1n_27_us_h2d.a_address &
-                  ~(ADDR_MASK_UART4)) == ADDR_SPACE_UART4) begin
-      dev_sel_s1n_27 = 5'd15;
+      dev_sel_s1n_25 = 5'd13;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
-      dev_sel_s1n_27 = 5'd16;
+      dev_sel_s1n_25 = 5'd14;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
-      dev_sel_s1n_27 = 5'd17;
+      dev_sel_s1n_25 = 5'd15;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_SPI0)) == ADDR_SPACE_SPI0) begin
-      dev_sel_s1n_27 = 5'd18;
+      dev_sel_s1n_25 = 5'd16;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_SPI1)) == ADDR_SPACE_SPI1) begin
-      dev_sel_s1n_27 = 5'd19;
+      dev_sel_s1n_25 = 5'd17;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_SPI2)) == ADDR_SPACE_SPI2) begin
-      dev_sel_s1n_27 = 5'd20;
+      dev_sel_s1n_25 = 5'd18;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_SPI3)) == ADDR_SPACE_SPI3) begin
-      dev_sel_s1n_27 = 5'd21;
+      dev_sel_s1n_25 = 5'd19;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_SPI4)) == ADDR_SPACE_SPI4) begin
-      dev_sel_s1n_27 = 5'd22;
+      dev_sel_s1n_25 = 5'd20;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
-      dev_sel_s1n_27 = 5'd23;
+      dev_sel_s1n_25 = 5'd21;
 
-    end else if ((tl_s1n_27_us_h2d.a_address &
+    end else if ((tl_s1n_25_us_h2d.a_address &
                   ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
-      dev_sel_s1n_27 = 5'd24;
+      dev_sel_s1n_25 = 5'd22;
 end
   end
 
@@ -335,19 +315,19 @@ end
   tlul_socket_1n #(
     .HReqDepth (4'h0),
     .HRspDepth (4'h0),
-    .DReqPass  (25'hfc02a7),
-    .DRspPass  (25'hfc02a7),
-    .DReqDepth (100'h1000000111111110101011000),
-    .DRspDepth (100'h1000000111111110101011000),
-    .N         (25)
-  ) u_s1n_27 (
+    .DReqPass  (23'h3f02a7),
+    .DRspPass  (23'h3f02a7),
+    .DReqDepth (92'h10000001111110101011000),
+    .DRspDepth (92'h10000001111110101011000),
+    .N         (23)
+  ) u_s1n_25 (
     .clk_i        (clk_sys_i),
     .rst_ni       (rst_sys_ni),
-    .tl_h_i       (tl_s1n_27_us_h2d),
-    .tl_h_o       (tl_s1n_27_us_d2h),
-    .tl_d_o       (tl_s1n_27_ds_h2d),
-    .tl_d_i       (tl_s1n_27_ds_d2h),
-    .dev_select_i (dev_sel_s1n_27)
+    .tl_h_i       (tl_s1n_25_us_h2d),
+    .tl_h_o       (tl_s1n_25_us_d2h),
+    .tl_d_o       (tl_s1n_25_ds_h2d),
+    .tl_d_i       (tl_s1n_25_ds_d2h),
+    .dev_select_i (dev_sel_s1n_25)
   );
   tlul_socket_m1 #(
     .HReqPass  (2'h1),
@@ -356,26 +336,26 @@ end
     .DReqDepth (4'h0),
     .DRspDepth (4'h0),
     .M         (2)
-  ) u_sm1_28 (
+  ) u_sm1_26 (
     .clk_i        (clk_sys_i),
     .rst_ni       (rst_sys_ni),
-    .tl_h_i       (tl_sm1_28_us_h2d),
-    .tl_h_o       (tl_sm1_28_us_d2h),
-    .tl_d_o       (tl_sm1_28_ds_h2d),
-    .tl_d_i       (tl_sm1_28_ds_d2h)
+    .tl_h_i       (tl_sm1_26_us_h2d),
+    .tl_h_o       (tl_sm1_26_us_d2h),
+    .tl_d_o       (tl_sm1_26_ds_h2d),
+    .tl_d_i       (tl_sm1_26_ds_d2h)
   );
   tlul_fifo_async #(
     .ReqDepth        (1),
     .RspDepth        (1)
-  ) u_asf_29 (
+  ) u_asf_27 (
     .clk_h_i      (clk_sys_i),
     .rst_h_ni     (rst_sys_ni),
     .clk_d_i      (clk_usb_i),
     .rst_d_ni     (rst_usb_ni),
-    .tl_h_i       (tl_asf_29_us_h2d),
-    .tl_h_o       (tl_asf_29_us_d2h),
-    .tl_d_o       (tl_asf_29_ds_h2d),
-    .tl_d_i       (tl_asf_29_ds_d2h)
+    .tl_h_i       (tl_asf_27_us_h2d),
+    .tl_h_o       (tl_asf_27_us_d2h),
+    .tl_d_o       (tl_asf_27_ds_h2d),
+    .tl_d_i       (tl_asf_27_ds_d2h)
   );
 
 endmodule
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index 3ba2ca019..841d55ae8 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -228,7 +228,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      uart_tx_i[4]
+      uart_tx_i[2]
     }),
     .sel_i(rs232_tx_sel),
     .out_o(out_to_pins_o[OUT_PIN_RS232_TX])
@@ -242,7 +242,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      uart_tx_en_i[4]
+      uart_tx_en_i[2]
     }),
     .sel_i(rs232_tx_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_RS232_TX])
@@ -1244,7 +1244,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][1],
+      spi_cs_i[2][0],
       gpio_ios_i[0][7]
     }),
     .sel_i(rph_g7_ce1_sel),
@@ -1259,7 +1259,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][1],
+      spi_cs_en_i[2][0],
       gpio_ios_en_i[0][7]
     }),
     .sel_i(rph_g7_ce1_sel),
@@ -1294,7 +1294,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][0],
+      spi_cs_i[2][1],
       gpio_ios_i[0][8]
     }),
     .sel_i(rph_g8_ce0_sel),
@@ -1309,7 +1309,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][0],
+      spi_cs_en_i[2][1],
       gpio_ios_en_i[0][8]
     }),
     .sel_i(rph_g8_ce0_sel),
@@ -1392,7 +1392,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[3],
+      spi_copi_i[2],
       gpio_ios_i[0][10]
     }),
     .sel_i(rph_g10_copi_sel),
@@ -1407,7 +1407,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[3],
+      spi_copi_en_i[2],
       gpio_ios_en_i[0][10]
     }),
     .sel_i(rph_g10_copi_sel),
@@ -1442,7 +1442,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[3],
+      spi_sclk_i[2],
       gpio_ios_i[0][11]
     }),
     .sel_i(rph_g11_sclk_sel),
@@ -1457,14 +1457,14 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[3],
+      spi_sclk_en_i[2],
       gpio_ios_en_i[0][11]
     }),
     .sel_i(rph_g11_sclk_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G11_SCLK])
   );
 
-  logic [1:0] rph_g12_sel;
+  logic [2:0] rph_g12_sel;
   logic rph_g12_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -1476,23 +1476,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      rph_g12_sel <= 2'b10;
+      rph_g12_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g12_sel_addressed) begin
-        rph_g12_sel <= reg_wdata[0+:2];
+        rph_g12_sel <= reg_wdata[0+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) rph_g12_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[0][12]
+      gpio_ios_i[0][12],
+      pwm_out_i[0][0]
     }),
     .sel_i(rph_g12_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_RPH_G12])
@@ -1500,19 +1501,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) rph_g12_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[0][12]
+      gpio_ios_en_i[0][12],
+      pwm_out_en_i[0][0]
     }),
     .sel_i(rph_g12_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G12])
   );
 
-  logic [1:0] rph_g13_sel;
+  logic [2:0] rph_g13_sel;
   logic rph_g13_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -1524,23 +1526,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      rph_g13_sel <= 2'b10;
+      rph_g13_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g13_sel_addressed) begin
-        rph_g13_sel <= reg_wdata[8+:2];
+        rph_g13_sel <= reg_wdata[8+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) rph_g13_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[0][13]
+      gpio_ios_i[0][13],
+      pwm_out_i[0][1]
     }),
     .sel_i(rph_g13_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_RPH_G13])
@@ -1548,13 +1551,14 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) rph_g13_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[0][13]
+      gpio_ios_en_i[0][13],
+      pwm_out_en_i[0][1]
     }),
     .sel_i(rph_g13_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G13])
@@ -1588,7 +1592,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      uart_tx_i[2],
+      uart_tx_i[1],
       gpio_ios_i[0][14]
     }),
     .sel_i(rph_txd0_sel),
@@ -1603,7 +1607,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      uart_tx_en_i[2],
+      uart_tx_en_i[1],
       gpio_ios_en_i[0][14]
     }),
     .sel_i(rph_txd0_sel),
@@ -1686,7 +1690,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[4][2],
+      spi_cs_i[3][2],
       gpio_ios_i[0][16]
     }),
     .sel_i(rph_g16_ce2_sel),
@@ -1701,7 +1705,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[4][2],
+      spi_cs_en_i[3][2],
       gpio_ios_en_i[0][16]
     }),
     .sel_i(rph_g16_ce2_sel),
@@ -1736,7 +1740,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[4][1],
+      spi_cs_i[3][1],
       gpio_ios_i[0][17]
     }),
     .sel_i(rph_g17_sel),
@@ -1751,14 +1755,14 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[4][1],
+      spi_cs_en_i[3][1],
       gpio_ios_en_i[0][17]
     }),
     .sel_i(rph_g17_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G17])
   );
 
-  logic [2:0] rph_g18_sel;
+  logic [3:0] rph_g18_sel;
   logic rph_g18_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -1770,24 +1774,25 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      rph_g18_sel <= 3'b10;
+      rph_g18_sel <= 4'b10;
     end else begin
       if (reg_we & rph_g18_sel_addressed) begin
-        rph_g18_sel <= reg_wdata[16+:3];
+        rph_g18_sel <= reg_wdata[16+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) rph_g18_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[4][0],
-      gpio_ios_i[0][18]
+      spi_cs_i[3][0],
+      gpio_ios_i[0][18],
+      pwm_out_i[0][2]
     }),
     .sel_i(rph_g18_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_RPH_G18])
@@ -1795,20 +1800,21 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) rph_g18_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[4][0],
-      gpio_ios_en_i[0][18]
+      spi_cs_en_i[3][0],
+      gpio_ios_en_i[0][18],
+      pwm_out_en_i[0][2]
     }),
     .sel_i(rph_g18_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G18])
   );
 
-  logic [1:0] rph_g19_cipo_sel;
+  logic [2:0] rph_g19_cipo_sel;
   logic rph_g19_cipo_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -1820,23 +1826,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      rph_g19_cipo_sel <= 2'b10;
+      rph_g19_cipo_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g19_cipo_sel_addressed) begin
-        rph_g19_cipo_sel <= reg_wdata[24+:2];
+        rph_g19_cipo_sel <= reg_wdata[24+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) rph_g19_cipo_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[0][19]
+      gpio_ios_i[0][19],
+      pwm_out_i[0][3]
     }),
     .sel_i(rph_g19_cipo_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_RPH_G19_CIPO])
@@ -1844,19 +1851,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) rph_g19_cipo_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[0][19]
+      gpio_ios_en_i[0][19],
+      pwm_out_en_i[0][3]
     }),
     .sel_i(rph_g19_cipo_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G19_CIPO])
   );
 
-  logic [2:0] rph_g20_copi_sel;
+  logic [3:0] rph_g20_copi_sel;
   logic rph_g20_copi_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -1868,24 +1876,25 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      rph_g20_copi_sel <= 3'b10;
+      rph_g20_copi_sel <= 4'b10;
     end else begin
       if (reg_we & rph_g20_copi_sel_addressed) begin
-        rph_g20_copi_sel <= reg_wdata[0+:3];
+        rph_g20_copi_sel <= reg_wdata[0+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) rph_g20_copi_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[4],
-      gpio_ios_i[0][20]
+      spi_copi_i[3],
+      gpio_ios_i[0][20],
+      pwm_out_i[0][4]
     }),
     .sel_i(rph_g20_copi_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_RPH_G20_COPI])
@@ -1893,20 +1902,21 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) rph_g20_copi_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[4],
-      gpio_ios_en_i[0][20]
+      spi_copi_en_i[3],
+      gpio_ios_en_i[0][20],
+      pwm_out_en_i[0][4]
     }),
     .sel_i(rph_g20_copi_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G20_COPI])
   );
 
-  logic [2:0] rph_g21_sclk_sel;
+  logic [3:0] rph_g21_sclk_sel;
   logic rph_g21_sclk_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -1918,24 +1928,25 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      rph_g21_sclk_sel <= 3'b10;
+      rph_g21_sclk_sel <= 4'b10;
     end else begin
       if (reg_we & rph_g21_sclk_sel_addressed) begin
-        rph_g21_sclk_sel <= reg_wdata[8+:3];
+        rph_g21_sclk_sel <= reg_wdata[8+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) rph_g21_sclk_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[4],
-      gpio_ios_i[0][21]
+      spi_sclk_i[3],
+      gpio_ios_i[0][21],
+      pwm_out_i[0][5]
     }),
     .sel_i(rph_g21_sclk_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_RPH_G21_SCLK])
@@ -1943,14 +1954,15 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) rph_g21_sclk_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[4],
-      gpio_ios_en_i[0][21]
+      spi_sclk_en_i[3],
+      gpio_ios_en_i[0][21],
+      pwm_out_en_i[0][5]
     }),
     .sel_i(rph_g21_sclk_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_RPH_G21_SCLK])
@@ -2320,8 +2332,8 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[1][1],
-      uart_tx_i[3]
+      uart_tx_i[1],
+      gpio_ios_i[1][1]
     }),
     .sel_i(ah_tmpio1_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO1])
@@ -2335,8 +2347,8 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[1][1],
-      uart_tx_en_i[3]
+      uart_tx_en_i[1],
+      gpio_ios_en_i[1][1]
     }),
     .sel_i(ah_tmpio1_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO1])
@@ -2390,7 +2402,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO2])
   );
 
-  logic [1:0] ah_tmpio3_sel;
+  logic [2:0] ah_tmpio3_sel;
   logic ah_tmpio3_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -2402,23 +2414,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ah_tmpio3_sel <= 2'b10;
+      ah_tmpio3_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio3_sel_addressed) begin
-        ah_tmpio3_sel <= reg_wdata[24+:2];
+        ah_tmpio3_sel <= reg_wdata[24+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio3_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[1][3]
+      gpio_ios_i[1][3],
+      pwm_out_i[0][0]
     }),
     .sel_i(ah_tmpio3_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO3])
@@ -2426,13 +2439,14 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio3_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[1][3]
+      gpio_ios_en_i[1][3],
+      pwm_out_en_i[0][0]
     }),
     .sel_i(ah_tmpio3_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO3])
@@ -2486,7 +2500,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO4])
   );
 
-  logic [1:0] ah_tmpio5_sel;
+  logic [2:0] ah_tmpio5_sel;
   logic ah_tmpio5_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -2498,23 +2512,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ah_tmpio5_sel <= 2'b10;
+      ah_tmpio5_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio5_sel_addressed) begin
-        ah_tmpio5_sel <= reg_wdata[8+:2];
+        ah_tmpio5_sel <= reg_wdata[8+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio5_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[1][5]
+      gpio_ios_i[1][5],
+      pwm_out_i[0][1]
     }),
     .sel_i(ah_tmpio5_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO5])
@@ -2522,19 +2537,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio5_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[1][5]
+      gpio_ios_en_i[1][5],
+      pwm_out_en_i[0][1]
     }),
     .sel_i(ah_tmpio5_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO5])
   );
 
-  logic [1:0] ah_tmpio6_sel;
+  logic [2:0] ah_tmpio6_sel;
   logic ah_tmpio6_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -2546,23 +2562,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ah_tmpio6_sel <= 2'b10;
+      ah_tmpio6_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio6_sel_addressed) begin
-        ah_tmpio6_sel <= reg_wdata[16+:2];
+        ah_tmpio6_sel <= reg_wdata[16+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio6_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[1][6]
+      gpio_ios_i[1][6],
+      pwm_out_i[0][2]
     }),
     .sel_i(ah_tmpio6_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO6])
@@ -2570,13 +2587,14 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio6_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[1][6]
+      gpio_ios_en_i[1][6],
+      pwm_out_en_i[0][2]
     }),
     .sel_i(ah_tmpio6_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO6])
@@ -2678,7 +2696,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO8])
   );
 
-  logic [1:0] ah_tmpio9_sel;
+  logic [2:0] ah_tmpio9_sel;
   logic ah_tmpio9_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -2690,23 +2708,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ah_tmpio9_sel <= 2'b10;
+      ah_tmpio9_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio9_sel_addressed) begin
-        ah_tmpio9_sel <= reg_wdata[8+:2];
+        ah_tmpio9_sel <= reg_wdata[8+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio9_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[1][9]
+      gpio_ios_i[1][9],
+      pwm_out_i[0][2]
     }),
     .sel_i(ah_tmpio9_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO9])
@@ -2714,19 +2733,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ah_tmpio9_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[1][9]
+      gpio_ios_en_i[1][9],
+      pwm_out_en_i[0][2]
     }),
     .sel_i(ah_tmpio9_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO9])
   );
 
-  logic [2:0] ah_tmpio10_sel;
+  logic [3:0] ah_tmpio10_sel;
   logic ah_tmpio10_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -2738,24 +2758,25 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ah_tmpio10_sel <= 3'b10;
+      ah_tmpio10_sel <= 4'b10;
     end else begin
       if (reg_we & ah_tmpio10_sel_addressed) begin
-        ah_tmpio10_sel <= reg_wdata[16+:3];
+        ah_tmpio10_sel <= reg_wdata[16+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) ah_tmpio10_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][2],
-      gpio_ios_i[1][10]
+      spi_cs_i[2][3],
+      gpio_ios_i[1][10],
+      pwm_out_i[0][4]
     }),
     .sel_i(ah_tmpio10_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO10])
@@ -2763,20 +2784,21 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) ah_tmpio10_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][2],
-      gpio_ios_en_i[1][10]
+      spi_cs_en_i[2][3],
+      gpio_ios_en_i[1][10],
+      pwm_out_en_i[0][4]
     }),
     .sel_i(ah_tmpio10_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO10])
   );
 
-  logic [2:0] ah_tmpio11_sel;
+  logic [3:0] ah_tmpio11_sel;
   logic ah_tmpio11_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -2788,24 +2810,25 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ah_tmpio11_sel <= 3'b10;
+      ah_tmpio11_sel <= 4'b10;
     end else begin
       if (reg_we & ah_tmpio11_sel_addressed) begin
-        ah_tmpio11_sel <= reg_wdata[24+:3];
+        ah_tmpio11_sel <= reg_wdata[24+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) ah_tmpio11_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[3],
-      gpio_ios_i[1][11]
+      spi_copi_i[2],
+      gpio_ios_i[1][11],
+      pwm_out_i[0][5]
     }),
     .sel_i(ah_tmpio11_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_AH_TMPIO11])
@@ -2813,14 +2836,15 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) ah_tmpio11_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[3],
-      gpio_ios_en_i[1][11]
+      spi_copi_en_i[2],
+      gpio_ios_en_i[1][11],
+      pwm_out_en_i[0][5]
     }),
     .sel_i(ah_tmpio11_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_AH_TMPIO11])
@@ -2902,7 +2926,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[3],
+      spi_sclk_i[2],
       gpio_ios_i[1][13]
     }),
     .sel_i(ah_tmpio13_sel),
@@ -2917,7 +2941,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[3],
+      spi_sclk_en_i[2],
       gpio_ios_en_i[1][13]
     }),
     .sel_i(ah_tmpio13_sel),
@@ -2952,7 +2976,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[4][3]
+      spi_cs_i[3][3]
     }),
     .sel_i(mb1_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB1])
@@ -2966,7 +2990,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[4][3]
+      spi_cs_en_i[3][3]
     }),
     .sel_i(mb1_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB1])
@@ -3000,7 +3024,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[4]
+      spi_sclk_i[3]
     }),
     .sel_i(mb2_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB2])
@@ -3014,7 +3038,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[4]
+      spi_sclk_en_i[3]
     }),
     .sel_i(mb2_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB2])
@@ -3048,7 +3072,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[4]
+      spi_copi_i[3]
     }),
     .sel_i(mb4_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB4])
@@ -3062,7 +3086,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[4]
+      spi_copi_en_i[3]
     }),
     .sel_i(mb4_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB4])
@@ -3192,7 +3216,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      uart_tx_i[3]
+      uart_tx_i[1]
     }),
     .sel_i(mb7_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB7])
@@ -3206,7 +3230,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      uart_tx_en_i[3]
+      uart_tx_en_i[1]
     }),
     .sel_i(mb7_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB7])
@@ -3310,7 +3334,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_1])
   );
 
-  logic [3:0] pmod0_2_sel;
+  logic [4:0] pmod0_2_sel;
   logic pmod0_2_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3322,17 +3346,17 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod0_2_sel <= 4'b10;
+      pmod0_2_sel <= 5'b10;
     end else begin
       if (reg_we & pmod0_2_sel_addressed) begin
-        pmod0_2_sel <= reg_wdata[16+:4];
+        pmod0_2_sel <= reg_wdata[16+:5];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(4)
+    .Inputs(5)
   ) pmod0_2_mux (
     .clk_i,
     .rst_ni,
@@ -3340,7 +3364,8 @@ module pinmux
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][1],
       spi_copi_i[2],
-      uart_tx_i[2]
+      pwm_out_i[0][1],
+      uart_tx_i[1]
     }),
     .sel_i(pmod0_2_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_2])
@@ -3348,7 +3373,7 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(4)
+    .Inputs(5)
   ) pmod0_2_enable_mux (
     .clk_i,
     .rst_ni,
@@ -3356,7 +3381,8 @@ module pinmux
       1'b0,
       gpio_ios_en_i[2][1],
       spi_copi_en_i[2],
-      uart_tx_en_i[2]
+      pwm_out_en_i[0][1],
+      uart_tx_en_i[1]
     }),
     .sel_i(pmod0_2_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_2])
@@ -3441,8 +3467,8 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][3],
-      i2c_sda_i[0],
-      spi_sclk_i[2]
+      spi_sclk_i[2],
+      i2c_sda_i[0]
     }),
     .sel_i(pmod0_4_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_4])
@@ -3457,8 +3483,8 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][3],
-      i2c_sda_en_i[0],
-      spi_sclk_en_i[2]
+      spi_sclk_en_i[2],
+      i2c_sda_en_i[0]
     }),
     .sel_i(pmod0_4_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_4])
@@ -3512,7 +3538,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_5])
   );
 
-  logic [1:0] pmod0_6_sel;
+  logic [2:0] pmod0_6_sel;
   logic pmod0_6_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3524,23 +3550,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod0_6_sel <= 2'b10;
+      pmod0_6_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_6_sel_addressed) begin
-        pmod0_6_sel <= reg_wdata[16+:2];
+        pmod0_6_sel <= reg_wdata[16+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod0_6_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[2][5]
+      gpio_ios_i[2][5],
+      pwm_out_i[0][2]
     }),
     .sel_i(pmod0_6_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_6])
@@ -3548,19 +3575,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod0_6_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[2][5]
+      gpio_ios_en_i[2][5],
+      pwm_out_en_i[0][2]
     }),
     .sel_i(pmod0_6_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_6])
   );
 
-  logic [1:0] pmod0_7_sel;
+  logic [2:0] pmod0_7_sel;
   logic pmod0_7_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3572,23 +3600,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod0_7_sel <= 2'b10;
+      pmod0_7_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_7_sel_addressed) begin
-        pmod0_7_sel <= reg_wdata[24+:2];
+        pmod0_7_sel <= reg_wdata[24+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod0_7_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[2][6]
+      gpio_ios_i[2][6],
+      spi_cs_i[2][1]
     }),
     .sel_i(pmod0_7_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_7])
@@ -3596,19 +3625,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod0_7_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[2][6]
+      gpio_ios_en_i[2][6],
+      spi_cs_en_i[2][1]
     }),
     .sel_i(pmod0_7_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_7])
   );
 
-  logic [1:0] pmod0_8_sel;
+  logic [2:0] pmod0_8_sel;
   logic pmod0_8_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3620,23 +3650,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod0_8_sel <= 2'b10;
+      pmod0_8_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_8_sel_addressed) begin
-        pmod0_8_sel <= reg_wdata[0+:2];
+        pmod0_8_sel <= reg_wdata[0+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod0_8_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[2][7]
+      gpio_ios_i[2][7],
+      spi_cs_i[2][2]
     }),
     .sel_i(pmod0_8_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_8])
@@ -3644,13 +3675,14 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod0_8_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[2][7]
+      gpio_ios_en_i[2][7],
+      spi_cs_en_i[2][2]
     }),
     .sel_i(pmod0_8_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_8])
@@ -3706,7 +3738,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_1])
   );
 
-  logic [3:0] pmod1_2_sel;
+  logic [4:0] pmod1_2_sel;
   logic pmod1_2_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3718,17 +3750,17 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod1_2_sel <= 4'b10;
+      pmod1_2_sel <= 5'b10;
     end else begin
       if (reg_we & pmod1_2_sel_addressed) begin
-        pmod1_2_sel <= reg_wdata[16+:4];
+        pmod1_2_sel <= reg_wdata[16+:5];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(4)
+    .Inputs(5)
   ) pmod1_2_mux (
     .clk_i,
     .rst_ni,
@@ -3736,7 +3768,8 @@ module pinmux
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][1],
       spi_copi_i[3],
-      uart_tx_i[3]
+      pwm_out_i[0][3],
+      uart_tx_i[2]
     }),
     .sel_i(pmod1_2_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_2])
@@ -3744,7 +3777,7 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(4)
+    .Inputs(5)
   ) pmod1_2_enable_mux (
     .clk_i,
     .rst_ni,
@@ -3752,7 +3785,8 @@ module pinmux
       1'b0,
       gpio_ios_en_i[3][1],
       spi_copi_en_i[3],
-      uart_tx_en_i[3]
+      pwm_out_en_i[0][3],
+      uart_tx_en_i[2]
     }),
     .sel_i(pmod1_2_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_2])
@@ -3837,8 +3871,8 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][3],
-      i2c_sda_i[1],
-      spi_sclk_i[3]
+      spi_sclk_i[3],
+      i2c_sda_i[1]
     }),
     .sel_i(pmod1_4_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_4])
@@ -3853,8 +3887,8 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][3],
-      i2c_sda_en_i[1],
-      spi_sclk_en_i[3]
+      spi_sclk_en_i[3],
+      i2c_sda_en_i[1]
     }),
     .sel_i(pmod1_4_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_4])
@@ -3908,7 +3942,7 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_5])
   );
 
-  logic [1:0] pmod1_6_sel;
+  logic [2:0] pmod1_6_sel;
   logic pmod1_6_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3920,23 +3954,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod1_6_sel <= 2'b10;
+      pmod1_6_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_6_sel_addressed) begin
-        pmod1_6_sel <= reg_wdata[16+:2];
+        pmod1_6_sel <= reg_wdata[16+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod1_6_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[3][5]
+      gpio_ios_i[3][5],
+      pwm_out_i[0][4]
     }),
     .sel_i(pmod1_6_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_6])
@@ -3944,19 +3979,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod1_6_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[3][5]
+      gpio_ios_en_i[3][5],
+      pwm_out_en_i[0][4]
     }),
     .sel_i(pmod1_6_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_6])
   );
 
-  logic [1:0] pmod1_7_sel;
+  logic [2:0] pmod1_7_sel;
   logic pmod1_7_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -3968,23 +4004,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod1_7_sel <= 2'b10;
+      pmod1_7_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_7_sel_addressed) begin
-        pmod1_7_sel <= reg_wdata[24+:2];
+        pmod1_7_sel <= reg_wdata[24+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod1_7_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[3][6]
+      gpio_ios_i[3][6],
+      spi_cs_i[3][1]
     }),
     .sel_i(pmod1_7_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_7])
@@ -3992,19 +4029,20 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod1_7_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[3][6]
+      gpio_ios_en_i[3][6],
+      spi_cs_en_i[3][1]
     }),
     .sel_i(pmod1_7_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_7])
   );
 
-  logic [1:0] pmod1_8_sel;
+  logic [2:0] pmod1_8_sel;
   logic pmod1_8_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -4016,23 +4054,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      pmod1_8_sel <= 2'b10;
+      pmod1_8_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_8_sel_addressed) begin
-        pmod1_8_sel <= reg_wdata[0+:2];
+        pmod1_8_sel <= reg_wdata[0+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod1_8_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      gpio_ios_i[3][7]
+      gpio_ios_i[3][7],
+      spi_cs_i[3][2]
     }),
     .sel_i(pmod1_8_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_8])
@@ -4040,13 +4079,14 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) pmod1_8_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      gpio_ios_en_i[3][7]
+      gpio_ios_en_i[3][7],
+      spi_cs_en_i[3][2]
     }),
     .sel_i(pmod1_8_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_8])
@@ -8584,7 +8624,7 @@ module pinmux
     .out_o(uart_rx_o[0])
   );
 
-  logic [1:0] uart_rx_1_sel;
+  logic [5:0] uart_rx_1_sel;
   logic uart_rx_1_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
@@ -8596,23 +8636,27 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      uart_rx_1_sel <= 2'b10;
+      uart_rx_1_sel <= 6'b10;
     end else begin
       if (reg_we & uart_rx_1_sel_addressed) begin
-        uart_rx_1_sel <= reg_wdata[8+:2];
+        uart_rx_1_sel <= reg_wdata[8+:6];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(6)
   ) uart_rx_1_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b1,
-      in_from_pins_i[IN_PIN_SER1_RX]
+      in_from_pins_i[IN_PIN_SER1_RX],
+      inout_from_pins_i[INOUT_PIN_RPH_RXD0],
+      inout_from_pins_i[INOUT_PIN_AH_TMPIO0],
+      in_from_pins_i[IN_PIN_MB8],
+      inout_from_pins_i[INOUT_PIN_PMOD0_3]
     }),
     .sel_i(uart_rx_1_sel),
     .out_o(uart_rx_o[1])
@@ -8646,91 +8690,21 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b1,
-      inout_from_pins_i[INOUT_PIN_RPH_RXD0],
-      inout_from_pins_i[INOUT_PIN_PMOD0_3]
+      in_from_pins_i[IN_PIN_RS232_RX],
+      inout_from_pins_i[INOUT_PIN_PMOD1_3]
     }),
     .sel_i(uart_rx_2_sel),
     .out_o(uart_rx_o[2])
   );
 
-  logic [3:0] uart_rx_3_sel;
-  logic uart_rx_3_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign uart_rx_3_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 128 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      uart_rx_3_sel <= 4'b10;
-    end else begin
-      if (reg_we & uart_rx_3_sel_addressed) begin
-        uart_rx_3_sel <= reg_wdata[24+:4];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(4)
-  ) uart_rx_3_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b1,
-      inout_from_pins_i[INOUT_PIN_AH_TMPIO0],
-      in_from_pins_i[IN_PIN_MB8],
-      inout_from_pins_i[INOUT_PIN_PMOD1_3]
-    }),
-    .sel_i(uart_rx_3_sel),
-    .out_o(uart_rx_o[3])
-  );
-
-  logic [1:0] uart_rx_4_sel;
-  logic uart_rx_4_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign uart_rx_4_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      uart_rx_4_sel <= 2'b10;
-    end else begin
-      if (reg_we & uart_rx_4_sel_addressed) begin
-        uart_rx_4_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) uart_rx_4_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b1,
-      in_from_pins_i[IN_PIN_RS232_RX]
-    }),
-    .sel_i(uart_rx_4_sel),
-    .out_o(uart_rx_o[4])
-  );
-
   logic [1:0] spi_cipo_0_sel;
   logic spi_cipo_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 128 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8738,7 +8712,7 @@ module pinmux
       spi_cipo_0_sel <= 2'b10;
     end else begin
       if (reg_we & spi_cipo_0_sel_addressed) begin
-        spi_cipo_0_sel <= reg_wdata[8+:2];
+        spi_cipo_0_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -8764,7 +8738,7 @@ module pinmux
   assign spi_cipo_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[2] == 1'b1;
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8772,7 +8746,7 @@ module pinmux
       spi_cipo_1_sel <= 2'b10;
     end else begin
       if (reg_we & spi_cipo_1_sel_addressed) begin
-        spi_cipo_1_sel <= reg_wdata[16+:2];
+        spi_cipo_1_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -8791,35 +8765,37 @@ module pinmux
     .out_o(spi_cipo_o[1])
   );
 
-  logic [2:0] spi_cipo_2_sel;
+  logic [4:0] spi_cipo_2_sel;
   logic spi_cipo_2_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
     reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[3] == 1'b1;
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_2_sel <= 3'b10;
+      spi_cipo_2_sel <= 5'b10;
     end else begin
       if (reg_we & spi_cipo_2_sel_addressed) begin
-        spi_cipo_2_sel <= reg_wdata[24+:3];
+        spi_cipo_2_sel <= reg_wdata[8+:5];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(5)
   ) spi_cipo_2_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
       in_from_pins_i[IN_PIN_ETHMAC_CIPO],
+      inout_from_pins_i[INOUT_PIN_RPH_G9_CIPO],
+      inout_from_pins_i[INOUT_PIN_AH_TMPIO12],
       inout_from_pins_i[INOUT_PIN_PMOD0_3]
     }),
     .sel_i(spi_cipo_2_sel),
@@ -8832,8 +8808,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 136 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 132 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8841,7 +8817,7 @@ module pinmux
       spi_cipo_3_sel <= 5'b10;
     end else begin
       if (reg_we & spi_cipo_3_sel_addressed) begin
-        spi_cipo_3_sel <= reg_wdata[0+:5];
+        spi_cipo_3_sel <= reg_wdata[16+:5];
       end
     end
   end
@@ -8854,8 +8830,8 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      inout_from_pins_i[INOUT_PIN_RPH_G9_CIPO],
-      inout_from_pins_i[INOUT_PIN_AH_TMPIO12],
+      inout_from_pins_i[INOUT_PIN_RPH_G19_CIPO],
+      in_from_pins_i[IN_PIN_MB3],
       inout_from_pins_i[INOUT_PIN_PMOD1_3],
       in_from_pins_i[IN_PIN_MICROSD_DAT0]
     }),
@@ -8863,36 +8839,35 @@ module pinmux
     .out_o(spi_cipo_o[3])
   );
 
-  logic [2:0] spi_cipo_4_sel;
+  logic [1:0] spi_cipo_4_sel;
   logic spi_cipo_4_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 136 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 132 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_4_sel <= 3'b10;
+      spi_cipo_4_sel <= 2'b10;
     end else begin
       if (reg_we & spi_cipo_4_sel_addressed) begin
-        spi_cipo_4_sel <= reg_wdata[8+:3];
+        spi_cipo_4_sel <= reg_wdata[24+:2];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(2)
   ) spi_cipo_4_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      inout_from_pins_i[INOUT_PIN_RPH_G19_CIPO],
-      in_from_pins_i[IN_PIN_MB3]
+      1'b0
     }),
     .sel_i(spi_cipo_4_sel),
     .out_o(spi_cipo_o[4])
@@ -8902,19 +8877,19 @@ module pinmux
   assign i2c_scl_o[0] =
     (scl0_sel == $bits(scl0_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SCL0] : 1'b1) &
     (rph_g1_sel == $bits(rph_g1_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G1] : 1'b1) &
-    (pmod0_3_sel == $bits(pmod0_3_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD0_3] : 1'b1);
+    (pmod0_3_sel == $bits(pmod0_3_sel)'(8) ? inout_from_pins_i[INOUT_PIN_PMOD0_3] : 1'b1);
   assign i2c_sda_o[0] =
     (sda0_sel == $bits(sda0_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SDA0] : 1'b1) &
     (rph_g0_sel == $bits(rph_g0_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G0] : 1'b1) &
-    (pmod0_4_sel == $bits(pmod0_4_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD0_4] : 1'b1);
+    (pmod0_4_sel == $bits(pmod0_4_sel)'(8) ? inout_from_pins_i[INOUT_PIN_PMOD0_4] : 1'b1);
   assign i2c_scl_o[1] =
     (scl1_sel == $bits(scl1_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SCL1] : 1'b1) &
     (rph_g3_scl_sel == $bits(rph_g3_scl_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G3_SCL] : 1'b1) &
     (mb6_sel == $bits(mb6_sel)'(2) ? inout_from_pins_i[INOUT_PIN_MB6] : 1'b1) &
-    (pmod1_3_sel == $bits(pmod1_3_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD1_3] : 1'b1);
+    (pmod1_3_sel == $bits(pmod1_3_sel)'(8) ? inout_from_pins_i[INOUT_PIN_PMOD1_3] : 1'b1);
   assign i2c_sda_o[1] =
     (sda1_sel == $bits(sda1_sel)'(2) ? inout_from_pins_i[INOUT_PIN_SDA1] : 1'b1) &
     (rph_g2_sda_sel == $bits(rph_g2_sda_sel)'(2) ? inout_from_pins_i[INOUT_PIN_RPH_G2_SDA] : 1'b1) &
     (mb5_sel == $bits(mb5_sel)'(2) ? inout_from_pins_i[INOUT_PIN_MB5] : 1'b1) &
-    (pmod1_4_sel == $bits(pmod1_4_sel)'(4) ? inout_from_pins_i[INOUT_PIN_PMOD1_4] : 1'b1);
+    (pmod1_4_sel == $bits(pmod1_4_sel)'(8) ? inout_from_pins_i[INOUT_PIN_PMOD1_4] : 1'b1);
 endmodule
diff --git a/rtl/system/sonata_pkg.sv b/rtl/system/sonata_pkg.sv
index f3187fcf0..be9c5a1cd 100644
--- a/rtl/system/sonata_pkg.sv
+++ b/rtl/system/sonata_pkg.sv
@@ -9,7 +9,7 @@ package sonata_pkg;
   // Number of Instances
   localparam int unsigned GPIO_NUM = 4;
   localparam int unsigned PWM_NUM = 1;
-  localparam int unsigned UART_NUM = 5;
+  localparam int unsigned UART_NUM = 3;
   localparam int unsigned I2C_NUM = 2;
   localparam int unsigned SPI_NUM = 5;
 
diff --git a/sw/cheri/common/platform-pinmux.hh b/sw/cheri/common/platform-pinmux.hh
index f63e5d73b..f99ba0234 100644
--- a/sw/cheri/common/platform-pinmux.hh
+++ b/sw/cheri/common/platform-pinmux.hh
@@ -283,13 +283,11 @@ class SonataPinmux : private utils::NoCopyNoMove {
     uart_0_rx     = 0x880,
     uart_1_rx     = 0x881,
     uart_2_rx     = 0x882,
-    uart_3_rx     = 0x883,
-    uart_4_rx     = 0x884,
-    spi_0_cipo    = 0x885,
-    spi_1_cipo    = 0x886,
-    spi_2_cipo    = 0x887,
-    spi_3_cipo    = 0x888,
-    spi_4_cipo    = 0x889,
+    spi_0_cipo    = 0x883,
+    spi_1_cipo    = 0x884,
+    spi_2_cipo    = 0x885,
+    spi_3_cipo    = 0x886,
+    spi_4_cipo    = 0x887,
   };
 
   /**
@@ -307,8 +305,14 @@ class SonataPinmux : private utils::NoCopyNoMove {
   static constexpr uint8_t output_pin_options(OutputPin output_pin) {
     switch (output_pin) {
       case OutputPin::pmod0_2:
-      case OutputPin::pmod0_4:
       case OutputPin::pmod1_2:
+        return 5;
+      case OutputPin::rph_g18:
+      case OutputPin::rph_g20_copi:
+      case OutputPin::rph_g21_sclk:
+      case OutputPin::ah_tmpio10:
+      case OutputPin::ah_tmpio11:
+      case OutputPin::pmod0_4:
       case OutputPin::pmod1_4:
         return 4;
       case OutputPin::rph_g0:
@@ -319,20 +323,28 @@ class SonataPinmux : private utils::NoCopyNoMove {
       case OutputPin::rph_g8_ce0:
       case OutputPin::rph_g10_copi:
       case OutputPin::rph_g11_sclk:
+      case OutputPin::rph_g12:
+      case OutputPin::rph_g13:
       case OutputPin::rph_txd0:
       case OutputPin::rph_g16_ce2:
       case OutputPin::rph_g17:
-      case OutputPin::rph_g18:
-      case OutputPin::rph_g20_copi:
-      case OutputPin::rph_g21_sclk:
+      case OutputPin::rph_g19_cipo:
       case OutputPin::ah_tmpio1:
-      case OutputPin::ah_tmpio10:
-      case OutputPin::ah_tmpio11:
+      case OutputPin::ah_tmpio3:
+      case OutputPin::ah_tmpio5:
+      case OutputPin::ah_tmpio6:
+      case OutputPin::ah_tmpio9:
       case OutputPin::ah_tmpio13:
       case OutputPin::pmod0_1:
       case OutputPin::pmod0_3:
+      case OutputPin::pmod0_6:
+      case OutputPin::pmod0_7:
+      case OutputPin::pmod0_8:
       case OutputPin::pmod1_1:
       case OutputPin::pmod1_3:
+      case OutputPin::pmod1_6:
+      case OutputPin::pmod1_7:
+      case OutputPin::pmod1_8:
         return 3;
       default:
         return 2;
@@ -353,13 +365,12 @@ class SonataPinmux : private utils::NoCopyNoMove {
    */
   static constexpr uint8_t block_input_options(BlockInput block_input) {
     switch (block_input) {
+      case BlockInput::uart_1_rx:
+        return 6;
+      case BlockInput::spi_2_cipo:
       case BlockInput::spi_3_cipo:
         return 5;
-      case BlockInput::uart_3_rx:
-        return 4;
       case BlockInput::uart_2_rx:
-      case BlockInput::spi_2_cipo:
-      case BlockInput::spi_4_cipo:
         return 3;
       default:
         return 2;

From c2265d4a0bb4719e325b54a0d1808151b09e8a29 Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Fri, 1 Nov 2024 10:13:29 +0000
Subject: [PATCH 05/21] sonata_system: dedicated spi devices pulled out of
 pinmux

These pins are only used for spi so don't need to be pinmuxed.
---
 data/top_config.toml                  |  131 +--
 data/xbar_main.hjson                  |   22 +
 data/xbar_main_generated.hjson        |   57 +-
 doc/ip/pinmux/README.md               |  149 ++-
 dv/verilator/top_verilator.sv         |   47 +-
 rtl/bus/sonata_xbar_main.sv           |   14 +-
 rtl/bus/tl_main_pkg.sv                |   41 +-
 rtl/bus/xbar_main.sv                  |  300 +++----
 rtl/fpga/top_sonata.sv                |   49 +-
 rtl/system/pinmux.sv                  | 1198 ++++++-------------------
 rtl/system/sonata_pkg.sv              |   35 +-
 rtl/system/sonata_system.sv           |  105 ++-
 rtl/templates/sonata_xbar_main.sv.tpl |    8 +
 sw/cheri/common/platform-pinmux.hh    |  151 ++--
 14 files changed, 806 insertions(+), 1501 deletions(-)

diff --git a/data/top_config.toml b/data/top_config.toml
index 13a787c9f..d5bf82ccd 100644
--- a/data/top_config.toml
+++ b/data/top_config.toml
@@ -44,14 +44,14 @@ xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
 
 [[blocks]]
 name = "spi"
-instances = 5
+instances = 2
 ios = [
   { name = "cipo", type = "input", default = 0 },
   { name = "copi", type = "output" },
   { name = "sclk", type = "output" },
   { name = "cs", type = "output", length = 4 },
 ]
-memory_start = 0x80300000
+memory_start = 0x80302000
 memory_size  = 0x00001000
 
 # UARTS
@@ -96,54 +96,6 @@ block_ios = [{ block = "i2c", instance = 1, io = "scl" }]
 name = "sda1"
 block_ios = [{ block = "i2c", instance = 1, io = "sda" }]
 
-## SPI Flash interface
-[[pins]]
-name = "appspi_d0"
-block_ios = [{ block = "spi", instance = 0, io = "copi" }]
-
-[[pins]]
-name = "appspi_d1"
-block_ios = [{ block = "spi", instance = 0, io = "cipo" }]
-
-[[pins]]
-name = "appspi_clk"
-block_ios = [{ block = "spi", instance = 0, io = "sclk" }]
-
-[[pins]]
-name = "appspi_cs"
-block_ios = [{ block = "spi", instance = 0, io = "cs", io_index = 0 }]
-
-## SPI LCD
-[[pins]]
-name = "lcd_copi"
-block_ios = [{ block = "spi", instance = 1, io = "copi" }]
-
-## RX or CIPO is not connected
-
-[[pins]]
-name = "lcd_clk"
-block_ios = [{ block = "spi", instance = 1, io = "sclk" }]
-
-[[pins]]
-name = "lcd_cs"
-block_ios = [{ block = "spi", instance = 1, io = "cs", io_index = 0 }]
-
-## SPI Ethernet
-[[pins]]
-name = "ethmac_copi"
-block_ios = [{ block = "spi", instance = 2, io = "copi" }]
-
-[[pins]]
-name = "ethmac_cipo"
-block_ios = [{ block = "spi", instance = 2, io = "cipo" }]
-
-[[pins]]
-name = "ethmac_sclk"
-block_ios = [{ block = "spi", instance = 2, io = "sclk" }]
-
-[[pins]]
-name = "ethmac_cs"
-block_ios = [{ block = "spi", instance = 2, io = "cs", io_index = 0 }]
 
 ## Raspberry Pi HAT
 [[pins]]
@@ -189,35 +141,35 @@ block_ios = [{block = "gpio", instance = 0, io = "ios", io_index = 6}]
 [[pins]]
 name = "rph_g7_ce1"
 block_ios = [
-  {block = "spi", instance = 2, io = "cs", io_index = 0},
+  {block = "spi", instance = 0, io = "cs", io_index = 0},
   {block = "gpio", instance = 0, io = "ios", io_index = 7},
 ]
 
 [[pins]]
 name = "rph_g8_ce0"
 block_ios = [
-  {block = "spi", instance = 2, io = "cs", io_index = 1},
+  {block = "spi", instance = 0, io = "cs", io_index = 1},
   {block = "gpio", instance = 0, io = "ios", io_index = 8},
 ]
 
 [[pins]]
 name = "rph_g9_cipo"
 block_ios = [
-  {block = "spi", instance = 2, io = "cipo"},
+  {block = "spi", instance = 0, io = "cipo"},
   {block = "gpio", instance = 0, io = "ios", io_index = 9},
 ]
 
 [[pins]]
 name = "rph_g10_copi"
 block_ios = [
-  {block = "spi", instance = 2, io = "copi"},
+  {block = "spi", instance = 0, io = "copi"},
   {block = "gpio", instance = 0, io = "ios", io_index = 10},
 ]
 
 [[pins]]
 name = "rph_g11_sclk"
 block_ios = [
-  {block = "spi", instance = 2, io = "sclk"},
+  {block = "spi", instance = 0, io = "sclk"},
   {block = "gpio", instance = 0, io = "ios", io_index = 11},
 ]
 
@@ -252,21 +204,21 @@ block_ios = [
 [[pins]]
 name = "rph_g16_ce2"
 block_ios = [
-  {block = "spi", instance = 3, io = "cs", io_index = 2},
+  {block = "spi", instance = 1, io = "cs", io_index = 2},
   {block = "gpio", instance = 0, io = "ios", io_index = 16}
 ]
 
 [[pins]]
 name = "rph_g17"
 block_ios = [
-  {block = "spi", instance = 3, io = "cs", io_index = 1},
+  {block = "spi", instance = 1, io = "cs", io_index = 1},
   {block = "gpio", instance = 0, io = "ios", io_index = 17},
 ]
 
 [[pins]]
 name = "rph_g18"
 block_ios = [
-  {block = "spi", instance = 3, io = "cs", io_index = 0},
+  {block = "spi", instance = 1, io = "cs", io_index = 0},
   {block = "gpio", instance = 0, io = "ios", io_index = 18},
   {block = "pwm", instance = 0, io = "out", io_index = 2},
 ]
@@ -274,7 +226,7 @@ block_ios = [
 [[pins]]
 name = "rph_g19_cipo"
 block_ios = [
-  {block = "spi", instance = 3, io = "cipo"},
+  {block = "spi", instance = 1, io = "cipo"},
   {block = "gpio", instance = 0, io = "ios", io_index = 19},
   {block = "pwm", instance = 0, io = "out", io_index = 3},
 ]
@@ -282,7 +234,7 @@ block_ios = [
 [[pins]]
 name = "rph_g20_copi"
 block_ios = [
-  {block = "spi", instance = 3, io = "copi"},
+  {block = "spi", instance = 1, io = "copi"},
   {block = "gpio", instance = 0, io = "ios", io_index = 20},
   {block = "pwm", instance = 0, io = "out", io_index = 4},
 ]
@@ -290,7 +242,7 @@ block_ios = [
 [[pins]]
 name = "rph_g21_sclk"
 block_ios = [
-  {block = "spi", instance = 3, io = "sclk"},
+  {block = "spi", instance = 1, io = "sclk"},
   {block = "gpio", instance = 0, io = "ios", io_index = 21},
   {block = "pwm", instance = 0, io = "out", io_index = 5},
 ]
@@ -381,7 +333,7 @@ block_ios = [
 [[pins]]
 name = "ah_tmpio10"
 block_ios = [
-  {block = "spi", instance = 2, io = "cs", io_index = 3},
+  {block = "spi", instance = 0, io = "cs", io_index = 3},
   {block = "gpio", instance = 1, io = "ios", io_index = 10},
   {block = "pwm", instance = 0, io = "out", io_index = 4},
 ]
@@ -389,7 +341,7 @@ block_ios = [
 [[pins]]
 name = "ah_tmpio11"
 block_ios = [
-  {block = "spi", instance = 2, io = "copi"},
+  {block = "spi", instance = 0, io = "copi"},
   {block = "gpio", instance = 1, io = "ios", io_index = 11},
   {block = "pwm", instance = 0, io = "out", io_index = 5},
 ]
@@ -397,14 +349,14 @@ block_ios = [
 [[pins]]
 name = "ah_tmpio12"
 block_ios = [
-  {block = "spi", instance = 2, io = "cipo"},
+  {block = "spi", instance = 0, io = "cipo"},
   {block = "gpio", instance = 1, io = "ios", io_index = 12},
 ]
 
 [[pins]]
 name = "ah_tmpio13"
 block_ios = [
-  {block = "spi", instance = 2, io = "sclk"},
+  {block = "spi", instance = 0, io = "sclk"},
   {block = "gpio", instance = 1, io = "ios", io_index = 13},
 ]
 
@@ -412,19 +364,19 @@ block_ios = [
 # mb0 is reset and already connected to a general purpose output.
 [[pins]]
 name = "mb1"
-block_ios = [{block = "spi", instance = 3, io = "cs", io_index = 3}]
+block_ios = [{block = "spi", instance = 1, io = "cs", io_index = 3}]
 
 [[pins]]
 name = "mb2"
-block_ios = [{block = "spi", instance = 3, io = "sclk"}]
+block_ios = [{block = "spi", instance = 1, io = "sclk"}]
 
 [[pins]]
 name = "mb3"
-block_ios = [{block = "spi", instance = 3, io = "cipo"}]
+block_ios = [{block = "spi", instance = 1, io = "cipo"}]
 
 [[pins]]
 name = "mb4"
-block_ios = [{block = "spi", instance = 3, io = "copi"}]
+block_ios = [{block = "spi", instance = 1, io = "copi"}]
 
 [[pins]]
 name = "mb5"
@@ -451,14 +403,14 @@ block_ios = [{block = "pwm", instance = 0, io = "out", io_index = 0}]
 name = "pmod0_1"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 0},
-  {block = "spi", instance = 2, io = "cs", io_index = 0},
+  {block = "spi", instance = 0, io = "cs", io_index = 0},
 ]
 
 [[pins]]
 name = "pmod0_2"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 1},
-  {block = "spi", instance = 2, io = "copi"},
+  {block = "spi", instance = 0, io = "copi"},
   {block = "pwm", instance = 0, io = "out", io_index = 1},
   {block = "uart", instance = 1, io = "tx"},
 ]
@@ -467,7 +419,7 @@ block_ios = [
 name = "pmod0_3"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 2},
-  {block = "spi", instance = 2, io = "cipo"},
+  {block = "spi", instance = 0, io = "cipo"},
   {block = "i2c", instance = 0, io = "scl"},
   {block = "uart", instance = 1, io = "rx"},
 ]
@@ -476,7 +428,7 @@ block_ios = [
 name = "pmod0_4"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 3},
-  {block = "spi", instance = 2, io = "sclk"},
+  {block = "spi", instance = 0, io = "sclk"},
   {block = "i2c", instance = 0, io = "sda"},
 ]
 
@@ -495,28 +447,28 @@ block_ios = [
 name = "pmod0_7"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 6},
-  {block = "spi", instance = 2, io = "cs", io_index = 1},
+  {block = "spi", instance = 0, io = "cs", io_index = 1},
 ]
 
 [[pins]]
 name = "pmod0_8"
 block_ios = [
   {block = "gpio", instance = 2, io = "ios", io_index = 7},
-  {block = "spi", instance = 2, io = "cs", io_index = 2},
+  {block = "spi", instance = 0, io = "cs", io_index = 2},
 ]
 
 [[pins]]
 name = "pmod1_1"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 0},
-  {block = "spi", instance = 3, io = "cs", io_index = 0},
+  {block = "spi", instance = 1, io = "cs", io_index = 0},
 ]
 
 [[pins]]
 name = "pmod1_2"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 1},
-  {block = "spi", instance = 3, io = "copi"},
+  {block = "spi", instance = 1, io = "copi"},
   {block = "pwm", instance = 0, io = "out", io_index = 3},
   {block = "uart", instance = 2, io = "tx"},
 ]
@@ -525,7 +477,7 @@ block_ios = [
 name = "pmod1_3"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 2},
-  {block = "spi", instance = 3, io = "cipo"},
+  {block = "spi", instance = 1, io = "cipo"},
   {block = "i2c", instance = 1, io = "scl"},
   {block = "uart", instance = 2, io = "rx"},
 ]
@@ -534,7 +486,7 @@ block_ios = [
 name = "pmod1_4"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 3},
-  {block = "spi", instance = 3, io = "sclk"},
+  {block = "spi", instance = 1, io = "sclk"},
   {block = "i2c", instance = 1, io = "sda"},
 ]
 
@@ -553,29 +505,12 @@ block_ios = [
 name = "pmod1_7"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 6},
-  {block = "spi", instance = 3, io = "cs", io_index = 1},
+  {block = "spi", instance = 1, io = "cs", io_index = 1},
 ]
 
 [[pins]]
 name = "pmod1_8"
 block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 7},
-  {block = "spi", instance = 3, io = "cs", io_index = 2},
+  {block = "spi", instance = 1, io = "cs", io_index = 2},
 ]
-
-## MicroSD card slot
-[[pins]]
-name = "microsd_clk"
-block_ios = [{block = "spi", instance = 3, io = "sclk"}]
-
-[[pins]]
-name = "microsd_dat0"
-block_ios = [{block = "spi", instance = 3, io = "cipo"}]
-
-[[pins]]
-name = "microsd_cmd"
-block_ios = [{block = "spi", instance = 3, io = "copi"}]
-
-[[pins]]
-name = "microsd_dat3"
-block_ios = [{block = "spi", instance = 3, io = "cs", io_index = 3}]
diff --git a/data/xbar_main.hjson b/data/xbar_main.hjson
index e7088a61e..a9adaae85 100644
--- a/data/xbar_main.hjson
+++ b/data/xbar_main.hjson
@@ -143,6 +143,26 @@
         size_byte: "0x00010000",
       }],
     },
+    { name:  "spi_board",
+      type:  "device",
+      clock: "clk_sys_i",
+      reset: "rst_sys_ni",
+      xbar:  false,
+      addr_range: [{
+        base_addr: "0x80300000",
+        size_byte: "0x1000",
+      }],
+    },
+    { name:  "spi_lcd",
+      type:  "device",
+      clock: "clk_sys_i",
+      reset: "rst_sys_ni",
+      xbar:  false,
+      addr_range: [{
+        base_addr: "0x80301000",
+        size_byte: "0x1000",
+      }],
+    },
     % for block in config.blocks:
     % if not block.name == "gpio":
     % for i in range(block.instances):
@@ -199,6 +219,8 @@
       "hw_rev",
       "xadc",
       "timer",
+      "spi_board",
+      "spi_lcd",
       % for block in config.blocks:
       % if not block.name == "gpio":
       % for i in range(block.instances):
diff --git a/data/xbar_main_generated.hjson b/data/xbar_main_generated.hjson
index c9a8f18e5..2daff0486 100644
--- a/data/xbar_main_generated.hjson
+++ b/data/xbar_main_generated.hjson
@@ -143,6 +143,26 @@
         size_byte: "0x00010000",
       }],
     },
+    { name:  "spi_board",
+      type:  "device",
+      clock: "clk_sys_i",
+      reset: "rst_sys_ni",
+      xbar:  false,
+      addr_range: [{
+        base_addr: "0x80300000",
+        size_byte: "0x1000",
+      }],
+    },
+    { name:  "spi_lcd",
+      type:  "device",
+      clock: "clk_sys_i",
+      reset: "rst_sys_ni",
+      xbar:  false,
+      addr_range: [{
+        base_addr: "0x80301000",
+        size_byte: "0x1000",
+      }],
+    },
     { name:  "pwm0",
       type:  "device",
       clock: "clk_sys_i",
@@ -222,26 +242,6 @@
       rsp_fifo_pass: false,
     },
     { name:  "spi0",
-      type:  "device",
-      clock: "clk_sys_i",
-      reset: "rst_sys_ni",
-      xbar:  false,
-      addr_range: [{
-        base_addr: "0x80300000",
-        size_byte: "0x1000",
-      }],
-    },
-    { name:  "spi1",
-      type:  "device",
-      clock: "clk_sys_i",
-      reset: "rst_sys_ni",
-      xbar:  false,
-      addr_range: [{
-        base_addr: "0x80301000",
-        size_byte: "0x1000",
-      }],
-    },
-    { name:  "spi2",
       type:  "device",
       clock: "clk_sys_i",
       reset: "rst_sys_ni",
@@ -251,7 +251,7 @@
         size_byte: "0x1000",
       }],
     },
-    { name:  "spi3",
+    { name:  "spi1",
       type:  "device",
       clock: "clk_sys_i",
       reset: "rst_sys_ni",
@@ -261,16 +261,6 @@
         size_byte: "0x1000",
       }],
     },
-    { name:  "spi4",
-      type:  "device",
-      clock: "clk_sys_i",
-      reset: "rst_sys_ni",
-      xbar:  false,
-      addr_range: [{
-        base_addr: "0x80304000",
-        size_byte: "0x1000",
-      }],
-    },
     { name:  "usbdev", // USB device
       type:  "device",
       clock: "clk_usb_i",
@@ -308,6 +298,8 @@
       "hw_rev",
       "xadc",
       "timer",
+      "spi_board",
+      "spi_lcd",
       "pwm0",
       "uart0",
       "uart1",
@@ -316,9 +308,6 @@
       "i2c1",
       "spi0",
       "spi1",
-      "spi2",
-      "spi3",
-      "spi4",
       "usbdev",
       "rv_plic",
     ],
diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index 90f22a3cf..605b78628 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -19,83 +19,71 @@ The default value for all of these selectors is `'b10`.
 | 0x004 | `sda0` | 0, `i2c[0].sda` |
 | 0x005 | `scl1` | 0, `i2c[1].scl` |
 | 0x006 | `sda1` | 0, `i2c[1].sda` |
-| 0x007 | `appspi_d0` | 0, `spi[0].copi` |
-| 0x008 | `appspi_clk` | 0, `spi[0].sclk` |
-| 0x009 | `appspi_cs` | 0, `spi[0].cs[0]` |
-| 0x00a | `lcd_copi` | 0, `spi[1].copi` |
-| 0x00b | `lcd_clk` | 0, `spi[1].sclk` |
-| 0x00c | `lcd_cs` | 0, `spi[1].cs[0]` |
-| 0x00d | `ethmac_copi` | 0, `spi[2].copi` |
-| 0x00e | `ethmac_sclk` | 0, `spi[2].sclk` |
-| 0x00f | `ethmac_cs` | 0, `spi[2].cs[0]` |
-| 0x010 | `rph_g0` | 0, `i2c[0].sda`, `gpio[0].ios[0]` |
-| 0x011 | `rph_g1` | 0, `i2c[0].scl`, `gpio[0].ios[1]` |
-| 0x012 | `rph_g2_sda` | 0, `i2c[1].sda`, `gpio[0].ios[2]` |
-| 0x013 | `rph_g3_scl` | 0, `i2c[1].scl`, `gpio[0].ios[3]` |
-| 0x014 | `rph_g4` | 0, `gpio[0].ios[4]` |
-| 0x015 | `rph_g5` | 0, `gpio[0].ios[5]` |
-| 0x016 | `rph_g6` | 0, `gpio[0].ios[6]` |
-| 0x017 | `rph_g7_ce1` | 0, `spi[2].cs[0]`, `gpio[0].ios[7]` |
-| 0x018 | `rph_g8_ce0` | 0, `spi[2].cs[1]`, `gpio[0].ios[8]` |
-| 0x019 | `rph_g9_cipo` | 0, `gpio[0].ios[9]` |
-| 0x01a | `rph_g10_copi` | 0, `spi[2].copi`, `gpio[0].ios[10]` |
-| 0x01b | `rph_g11_sclk` | 0, `spi[2].sclk`, `gpio[0].ios[11]` |
-| 0x01c | `rph_g12` | 0, `gpio[0].ios[12]`, `pwm_out[0]` |
-| 0x01d | `rph_g13` | 0, `gpio[0].ios[13]`, `pwm_out[1]` |
-| 0x01e | `rph_txd0` | 0, `uart[1].tx`, `gpio[0].ios[14]` |
-| 0x01f | `rph_rxd0` | 0, `gpio[0].ios[15]` |
-| 0x020 | `rph_g16_ce2` | 0, `spi[3].cs[2]`, `gpio[0].ios[16]` |
-| 0x021 | `rph_g17` | 0, `spi[3].cs[1]`, `gpio[0].ios[17]` |
-| 0x022 | `rph_g18` | 0, `spi[3].cs[0]`, `gpio[0].ios[18]`, `pwm_out[2]` |
-| 0x023 | `rph_g19_cipo` | 0, `gpio[0].ios[19]`, `pwm_out[3]` |
-| 0x024 | `rph_g20_copi` | 0, `spi[3].copi`, `gpio[0].ios[20]`, `pwm_out[4]` |
-| 0x025 | `rph_g21_sclk` | 0, `spi[3].sclk`, `gpio[0].ios[21]`, `pwm_out[5]` |
-| 0x026 | `rph_g22` | 0, `gpio[0].ios[22]` |
-| 0x027 | `rph_g23` | 0, `gpio[0].ios[23]` |
-| 0x028 | `rph_g24` | 0, `gpio[0].ios[24]` |
-| 0x029 | `rph_g25` | 0, `gpio[0].ios[25]` |
-| 0x02a | `rph_g26` | 0, `gpio[0].ios[26]` |
-| 0x02b | `rph_g27` | 0, `gpio[0].ios[27]` |
-| 0x02c | `ah_tmpio0` | 0, `gpio[1].ios[0]` |
-| 0x02d | `ah_tmpio1` | 0, `uart[1].tx`, `gpio[1].ios[1]` |
-| 0x02e | `ah_tmpio2` | 0, `gpio[1].ios[2]` |
-| 0x02f | `ah_tmpio3` | 0, `gpio[1].ios[3]`, `pwm_out[0]` |
-| 0x030 | `ah_tmpio4` | 0, `gpio[1].ios[4]` |
-| 0x031 | `ah_tmpio5` | 0, `gpio[1].ios[5]`, `pwm_out[1]` |
-| 0x032 | `ah_tmpio6` | 0, `gpio[1].ios[6]`, `pwm_out[2]` |
-| 0x033 | `ah_tmpio7` | 0, `gpio[1].ios[7]` |
-| 0x034 | `ah_tmpio8` | 0, `gpio[1].ios[8]` |
-| 0x035 | `ah_tmpio9` | 0, `gpio[1].ios[9]`, `pwm_out[2]` |
-| 0x036 | `ah_tmpio10` | 0, `spi[2].cs[3]`, `gpio[1].ios[10]`, `pwm_out[4]` |
-| 0x037 | `ah_tmpio11` | 0, `spi[2].copi`, `gpio[1].ios[11]`, `pwm_out[5]` |
-| 0x038 | `ah_tmpio12` | 0, `gpio[1].ios[12]` |
-| 0x039 | `ah_tmpio13` | 0, `spi[2].sclk`, `gpio[1].ios[13]` |
-| 0x03a | `mb1` | 0, `spi[3].cs[3]` |
-| 0x03b | `mb2` | 0, `spi[3].sclk` |
-| 0x03c | `mb4` | 0, `spi[3].copi` |
-| 0x03d | `mb5` | 0, `i2c[1].sda` |
-| 0x03e | `mb6` | 0, `i2c[1].scl` |
-| 0x03f | `mb7` | 0, `uart[1].tx` |
-| 0x040 | `mb10` | 0, `pwm_out[0]` |
-| 0x041 | `pmod0_1` | 0, `gpio[2].ios[0]`, `spi[2].cs[0]` |
-| 0x042 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[2].copi`, `pwm_out[1]`, `uart[1].tx` |
-| 0x043 | `pmod0_3` | 0, `gpio[2].ios[2]`, `i2c[0].scl` |
-| 0x044 | `pmod0_4` | 0, `gpio[2].ios[3]`, `spi[2].sclk`, `i2c[0].sda` |
-| 0x045 | `pmod0_5` | 0, `gpio[2].ios[4]` |
-| 0x046 | `pmod0_6` | 0, `gpio[2].ios[5]`, `pwm_out[2]` |
-| 0x047 | `pmod0_7` | 0, `gpio[2].ios[6]`, `spi[2].cs[1]` |
-| 0x048 | `pmod0_8` | 0, `gpio[2].ios[7]`, `spi[2].cs[2]` |
-| 0x049 | `pmod1_1` | 0, `gpio[3].ios[0]`, `spi[3].cs[0]` |
-| 0x04a | `pmod1_2` | 0, `gpio[3].ios[1]`, `spi[3].copi`, `pwm_out[3]`, `uart[2].tx` |
-| 0x04b | `pmod1_3` | 0, `gpio[3].ios[2]`, `i2c[1].scl` |
-| 0x04c | `pmod1_4` | 0, `gpio[3].ios[3]`, `spi[3].sclk`, `i2c[1].sda` |
-| 0x04d | `pmod1_5` | 0, `gpio[3].ios[4]` |
-| 0x04e | `pmod1_6` | 0, `gpio[3].ios[5]`, `pwm_out[4]` |
-| 0x04f | `pmod1_7` | 0, `gpio[3].ios[6]`, `spi[3].cs[1]` |
-| 0x050 | `pmod1_8` | 0, `gpio[3].ios[7]`, `spi[3].cs[2]` |
-| 0x051 | `microsd_clk` | 0, `spi[3].sclk` |
-| 0x052 | `microsd_cmd` | 0, `spi[3].copi` |
-| 0x053 | `microsd_dat3` | 0, `spi[3].cs[3]` |
+| 0x007 | `rph_g0` | 0, `i2c[0].sda`, `gpio[0].ios[0]` |
+| 0x008 | `rph_g1` | 0, `i2c[0].scl`, `gpio[0].ios[1]` |
+| 0x009 | `rph_g2_sda` | 0, `i2c[1].sda`, `gpio[0].ios[2]` |
+| 0x00a | `rph_g3_scl` | 0, `i2c[1].scl`, `gpio[0].ios[3]` |
+| 0x00b | `rph_g4` | 0, `gpio[0].ios[4]` |
+| 0x00c | `rph_g5` | 0, `gpio[0].ios[5]` |
+| 0x00d | `rph_g6` | 0, `gpio[0].ios[6]` |
+| 0x00e | `rph_g7_ce1` | 0, `spi[0].cs[0]`, `gpio[0].ios[7]` |
+| 0x00f | `rph_g8_ce0` | 0, `spi[0].cs[1]`, `gpio[0].ios[8]` |
+| 0x010 | `rph_g9_cipo` | 0, `gpio[0].ios[9]` |
+| 0x011 | `rph_g10_copi` | 0, `spi[0].copi`, `gpio[0].ios[10]` |
+| 0x012 | `rph_g11_sclk` | 0, `spi[0].sclk`, `gpio[0].ios[11]` |
+| 0x013 | `rph_g12` | 0, `gpio[0].ios[12]`, `pwm_out[0]` |
+| 0x014 | `rph_g13` | 0, `gpio[0].ios[13]`, `pwm_out[1]` |
+| 0x015 | `rph_txd0` | 0, `uart[1].tx`, `gpio[0].ios[14]` |
+| 0x016 | `rph_rxd0` | 0, `gpio[0].ios[15]` |
+| 0x017 | `rph_g16_ce2` | 0, `spi[1].cs[2]`, `gpio[0].ios[16]` |
+| 0x018 | `rph_g17` | 0, `spi[1].cs[1]`, `gpio[0].ios[17]` |
+| 0x019 | `rph_g18` | 0, `spi[1].cs[0]`, `gpio[0].ios[18]`, `pwm_out[2]` |
+| 0x01a | `rph_g19_cipo` | 0, `gpio[0].ios[19]`, `pwm_out[3]` |
+| 0x01b | `rph_g20_copi` | 0, `spi[1].copi`, `gpio[0].ios[20]`, `pwm_out[4]` |
+| 0x01c | `rph_g21_sclk` | 0, `spi[1].sclk`, `gpio[0].ios[21]`, `pwm_out[5]` |
+| 0x01d | `rph_g22` | 0, `gpio[0].ios[22]` |
+| 0x01e | `rph_g23` | 0, `gpio[0].ios[23]` |
+| 0x01f | `rph_g24` | 0, `gpio[0].ios[24]` |
+| 0x020 | `rph_g25` | 0, `gpio[0].ios[25]` |
+| 0x021 | `rph_g26` | 0, `gpio[0].ios[26]` |
+| 0x022 | `rph_g27` | 0, `gpio[0].ios[27]` |
+| 0x023 | `ah_tmpio0` | 0, `gpio[1].ios[0]` |
+| 0x024 | `ah_tmpio1` | 0, `uart[1].tx`, `gpio[1].ios[1]` |
+| 0x025 | `ah_tmpio2` | 0, `gpio[1].ios[2]` |
+| 0x026 | `ah_tmpio3` | 0, `gpio[1].ios[3]`, `pwm_out[0]` |
+| 0x027 | `ah_tmpio4` | 0, `gpio[1].ios[4]` |
+| 0x028 | `ah_tmpio5` | 0, `gpio[1].ios[5]`, `pwm_out[1]` |
+| 0x029 | `ah_tmpio6` | 0, `gpio[1].ios[6]`, `pwm_out[2]` |
+| 0x02a | `ah_tmpio7` | 0, `gpio[1].ios[7]` |
+| 0x02b | `ah_tmpio8` | 0, `gpio[1].ios[8]` |
+| 0x02c | `ah_tmpio9` | 0, `gpio[1].ios[9]`, `pwm_out[2]` |
+| 0x02d | `ah_tmpio10` | 0, `spi[0].cs[3]`, `gpio[1].ios[10]`, `pwm_out[4]` |
+| 0x02e | `ah_tmpio11` | 0, `spi[0].copi`, `gpio[1].ios[11]`, `pwm_out[5]` |
+| 0x02f | `ah_tmpio12` | 0, `gpio[1].ios[12]` |
+| 0x030 | `ah_tmpio13` | 0, `spi[0].sclk`, `gpio[1].ios[13]` |
+| 0x031 | `mb1` | 0, `spi[1].cs[3]` |
+| 0x032 | `mb2` | 0, `spi[1].sclk` |
+| 0x033 | `mb4` | 0, `spi[1].copi` |
+| 0x034 | `mb5` | 0, `i2c[1].sda` |
+| 0x035 | `mb6` | 0, `i2c[1].scl` |
+| 0x036 | `mb7` | 0, `uart[1].tx` |
+| 0x037 | `mb10` | 0, `pwm_out[0]` |
+| 0x038 | `pmod0_1` | 0, `gpio[2].ios[0]`, `spi[0].cs[0]` |
+| 0x039 | `pmod0_2` | 0, `gpio[2].ios[1]`, `spi[0].copi`, `pwm_out[1]`, `uart[1].tx` |
+| 0x03a | `pmod0_3` | 0, `gpio[2].ios[2]`, `i2c[0].scl` |
+| 0x03b | `pmod0_4` | 0, `gpio[2].ios[3]`, `spi[0].sclk`, `i2c[0].sda` |
+| 0x03c | `pmod0_5` | 0, `gpio[2].ios[4]` |
+| 0x03d | `pmod0_6` | 0, `gpio[2].ios[5]`, `pwm_out[2]` |
+| 0x03e | `pmod0_7` | 0, `gpio[2].ios[6]`, `spi[0].cs[1]` |
+| 0x03f | `pmod0_8` | 0, `gpio[2].ios[7]`, `spi[0].cs[2]` |
+| 0x040 | `pmod1_1` | 0, `gpio[3].ios[0]`, `spi[1].cs[0]` |
+| 0x041 | `pmod1_2` | 0, `gpio[3].ios[1]`, `spi[1].copi`, `pwm_out[3]`, `uart[2].tx` |
+| 0x042 | `pmod1_3` | 0, `gpio[3].ios[2]`, `i2c[1].scl` |
+| 0x043 | `pmod1_4` | 0, `gpio[3].ios[3]`, `spi[1].sclk`, `i2c[1].sda` |
+| 0x044 | `pmod1_5` | 0, `gpio[3].ios[4]` |
+| 0x045 | `pmod1_6` | 0, `gpio[3].ios[5]`, `pwm_out[4]` |
+| 0x046 | `pmod1_7` | 0, `gpio[3].ios[6]`, `spi[1].cs[1]` |
+| 0x047 | `pmod1_8` | 0, `gpio[3].ios[7]`, `spi[1].cs[2]` |
 
 Besides the output pin selectors, there are also selectors for which pin should drive block inputs:
 
@@ -232,11 +220,8 @@ Besides the output pin selectors, there are also selectors for which pin should
 | 0x880 | `uart[0].rx` | 1, `ser0_rx` |
 | 0x881 | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
 | 0x882 | `uart[2].rx` | 1, `rs232_rx`, `pmod1_3` |
-| 0x883 | `spi[0].cipo` | 0, `appspi_d1` |
-| 0x884 | `spi[1].cipo` | 0, 0 |
-| 0x885 | `spi[2].cipo` | 0, `ethmac_cipo`, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
-| 0x886 | `spi[3].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3`, `microsd_dat0` |
-| 0x887 | `spi[4].cipo` | 0, 0 |
+| 0x883 | `spi[0].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
+| 0x884 | `spi[1].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3` |
 
 ## Regeneration
 
diff --git a/dv/verilator/top_verilator.sv b/dv/verilator/top_verilator.sv
index 4ec7aab87..2c4f98d9d 100644
--- a/dv/verilator/top_verilator.sv
+++ b/dv/verilator/top_verilator.sv
@@ -112,7 +112,7 @@ module top_verilator (input logic clk_i, rst_ni);
   wire lcd_backlight;
 
   // mikroBUS Click.
-  wire mb0, mb1;
+  wire mb1;
   // Arduino
   wire ah_tmpio10;
   // RPi header.
@@ -124,7 +124,7 @@ module top_verilator (input logic clk_i, rst_ni);
   // MicroSD card slot
   wire microsd_dat3;
   // None of these signals is used presently.
-  wire unused_io_ = ^{mb0, mb1, ah_tmpio10, rph_g18, rph_g17,
+  wire unused_io_ = ^{mb1, ah_tmpio10, rph_g18, rph_g17,
                       rph_g16_ce2, rph_g8_ce0, rph_g7_ce1, ethmac_rst, ethmac_cs,
                       usrLed, microsd_dat3};
 
@@ -179,10 +179,6 @@ module top_verilator (input logic clk_i, rst_ni);
 
   assign uart_sys_tx = out_to_pins[OUT_PIN_SER0_TX];
   assign uart_aux_tx = out_to_pins[OUT_PIN_SER1_TX];
-  assign appspi_d0   = out_to_pins[OUT_PIN_APPSPI_D0];
-  assign lcd_copi    = out_to_pins[OUT_PIN_LCD_COPI];
-  assign appspi_clk  = out_to_pins[OUT_PIN_APPSPI_CLK];
-  assign lcd_clk     = out_to_pins[OUT_PIN_LCD_CLK];
 
   // Output I2C traffic to the RPi HAT ID EEPROM.
   assign {scl_rpi0_o, scl_rpi0_oe} = {inout_to_pins[INOUT_PIN_RPH_G1],
@@ -198,7 +194,6 @@ module top_verilator (input logic clk_i, rst_ni);
   assign {scl1_o, scl1_oe} = {inout_to_pins[INOUT_PIN_SCL1], inout_to_pins_en[INOUT_PIN_SCL1]};
   assign {sda1_o, sda1_oe} = {inout_to_pins[INOUT_PIN_SDA1], inout_to_pins_en[INOUT_PIN_SDA1]};
 
-  assign in_from_pins[IN_PIN_APPSPI_D1] = appspi_d1;
   assign in_from_pins[IN_PIN_SER0_RX]   = uart_sys_rx;
   assign in_from_pins[IN_PIN_SER1_RX]   = uart_aux_rx;
 
@@ -220,26 +215,17 @@ module top_verilator (input logic clk_i, rst_ni);
   assign inout_from_pins[INOUT_PIN_MB6] = 1'b1;
 
   // CS outputs to SPI peripherals from controllers.
-  assign appspi_cs    = out_to_pins[OUT_PIN_APPSPI_CS];
-  assign lcd_cs       = out_to_pins[OUT_PIN_LCD_CS];
-  assign ethmac_cs    = out_to_pins[OUT_PIN_ETHMAC_CS];
   assign rph_g8_ce0   = inout_to_pins[INOUT_PIN_RPH_G8_CE0];
   assign rph_g7_ce1   = inout_to_pins[INOUT_PIN_RPH_G7_CE1];
   assign ah_tmpio10   = inout_to_pins[INOUT_PIN_AH_TMPIO10];
-  assign microsd_dat3 = out_to_pins[OUT_PIN_MICROSD_DAT3];
   assign rph_g18      = inout_to_pins[INOUT_PIN_RPH_G18];
   assign rph_g17      = inout_to_pins[INOUT_PIN_RPH_G17];
   assign rph_g16_ce2  = inout_to_pins[INOUT_PIN_RPH_G16_CE2];
   assign mb1          = out_to_pins[OUT_PIN_MB1];
 
   logic unused_out_pins = ^{out_to_pins[OUT_PIN_RS232_TX],
-                            out_to_pins[OUT_PIN_ETHMAC_COPI],
-                            out_to_pins[OUT_PIN_ETHMAC_SCLK],
-                            out_to_pins[OUT_PIN_MB2],
-                            out_to_pins[OUT_PIN_MICROSD_CMD],
-                            out_to_pins[OUT_PIN_MICROSD_CLK]};
-
-  logic [18:0] unused_gp_o;
+                            out_to_pins[OUT_PIN_MB2]};
+  logic [23:0] unused_gp_o;
 
   // Loopback functionality used to verify the operation of the pinmux and GPIO pins;
   // these signals are re-timed through a single register stage simply to prevent Verilator
@@ -264,9 +250,9 @@ module top_verilator (input logic clk_i, rst_ni);
   wire [4:0] nav_sw_n = '0;
   wire [7:0] user_sw_n = '0;
   wire [2:0] sel_sw_n = '0;
-  wire mb9 = 1'b1; // undriven, apt to float high.
   wire microsd_det = 1'b1; // pulled high to indicate the _absence_ of a microSD card.
 
+
   // Instantiating the Sonata System.
   sonata_system #(
     .CheriErrWidth   ( CheriErrWidth   ),
@@ -289,8 +275,7 @@ module top_verilator (input logic clk_i, rst_ni);
     .rst_hr_ni      (rst_hr_n),
 
     .gp_i           ({
-                      14'b0,
-                      mb9, // mikroBUS Click interrupt
+                      15'b0,
                       microsd_det, // MicroSD card insertion detection
                       sel_sw_n, // Software selection switches
                       nav_sw_n, // joystick
@@ -298,9 +283,6 @@ module top_verilator (input logic clk_i, rst_ni);
                     }),
     .gp_o           ({
                       unused_gp_o,
-                      mb0, // mikroBUS Click reset
-                      ethmac_rst, // Ethernet
-                      lcd_backlight, lcd_dc, lcd_rst, // LCD screen
                       usrLed // User LEDs (8 bits)
                      }),
 
@@ -311,6 +293,23 @@ module top_verilator (input logic clk_i, rst_ni);
     .ard_an_p_i     (0),
     .ard_an_n_i     (0),
 
+
+    // Non-pinmuxed spi devices
+    .lcd_copi_o              (lcd_copi),
+    .lcd_sclk_o              (lcd_clk),
+    .lcd_cs_o                (lcd_cs),
+    .lcd_dc_o                (lcd_dc),
+    .lcd_rst_o               (lcd_rst),
+    .lcd_backlight_o         (lcd_backlight),
+
+    .spi_board_copi_o        (appspi_d0),
+    .spi_board_cipo_i        (appspi_d1),
+    .spi_board_sclk_o        (appspi_clk),
+    .spi_board_flash_cs_o    (appspi_cs),
+    .spi_board_eth_cs_o      (ethmac_cs),
+    .spi_board_eth_rst_o     (ethmac_rst),
+    .spi_board_microsd_cs_o  (microsd_dat3),
+
     // SPI hosts
     .spi_eth_irq_ni(1'b1),
 
diff --git a/rtl/bus/sonata_xbar_main.sv b/rtl/bus/sonata_xbar_main.sv
index bf80371b2..caf23a5ff 100644
--- a/rtl/bus/sonata_xbar_main.sv
+++ b/rtl/bus/sonata_xbar_main.sv
@@ -41,6 +41,10 @@ module sonata_xbar_main
   input  tlul_pkg::tl_d2h_t tl_xadc_i,
   output tlul_pkg::tl_h2d_t tl_timer_o,
   input  tlul_pkg::tl_d2h_t tl_timer_i,
+  output tlul_pkg::tl_h2d_t tl_spi_board_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_board_i,
+  output tlul_pkg::tl_h2d_t tl_spi_lcd_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_lcd_i,
   output tlul_pkg::tl_h2d_t tl_pwm_o[PWM_NUM],
   input  tlul_pkg::tl_d2h_t tl_pwm_i[PWM_NUM],
   output tlul_pkg::tl_h2d_t tl_uart_o[UART_NUM],
@@ -89,6 +93,10 @@ module sonata_xbar_main
     .tl_xadc_i        (tl_xadc_i),
     .tl_timer_o       (tl_timer_o),
     .tl_timer_i       (tl_timer_i),
+    .tl_spi_board_i   (tl_spi_board_i),
+    .tl_spi_board_o   (tl_spi_board_o),
+    .tl_spi_lcd_i     (tl_spi_lcd_i),
+    .tl_spi_lcd_o     (tl_spi_lcd_o),
     .tl_pwm0_o        (tl_pwm_o[0]),
     .tl_pwm0_i        (tl_pwm_i[0]),
     .tl_uart0_o        (tl_uart_o[0]),
@@ -105,12 +113,6 @@ module sonata_xbar_main
     .tl_spi0_i        (tl_spi_i[0]),
     .tl_spi1_o        (tl_spi_o[1]),
     .tl_spi1_i        (tl_spi_i[1]),
-    .tl_spi2_o        (tl_spi_o[2]),
-    .tl_spi2_i        (tl_spi_i[2]),
-    .tl_spi3_o        (tl_spi_o[3]),
-    .tl_spi3_i        (tl_spi_i[3]),
-    .tl_spi4_o        (tl_spi_o[4]),
-    .tl_spi4_i        (tl_spi_i[4]),
     .tl_usbdev_o      (tl_usbdev_o),
     .tl_usbdev_i      (tl_usbdev_i),
     .tl_rv_plic_o     (tl_rv_plic_o),
diff --git a/rtl/bus/tl_main_pkg.sv b/rtl/bus/tl_main_pkg.sv
index 7f010decf..9c7caabd2 100644
--- a/rtl/bus/tl_main_pkg.sv
+++ b/rtl/bus/tl_main_pkg.sv
@@ -16,17 +16,16 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_SPACE_XADC        = 32'h 8000b000;
   localparam logic [31:0] ADDR_SPACE_SYSTEM_INFO = 32'h 8000c000;
   localparam logic [31:0] ADDR_SPACE_TIMER       = 32'h 80040000;
+  localparam logic [31:0] ADDR_SPACE_SPI_BOARD   = 32'h 80300000;
+  localparam logic [31:0] ADDR_SPACE_SPI_LCD     = 32'h 80301000;
   localparam logic [31:0] ADDR_SPACE_PWM0        = 32'h 80001000;
   localparam logic [31:0] ADDR_SPACE_UART0       = 32'h 80100000;
   localparam logic [31:0] ADDR_SPACE_UART1       = 32'h 80101000;
   localparam logic [31:0] ADDR_SPACE_UART2       = 32'h 80102000;
   localparam logic [31:0] ADDR_SPACE_I2C0        = 32'h 80200000;
   localparam logic [31:0] ADDR_SPACE_I2C1        = 32'h 80201000;
-  localparam logic [31:0] ADDR_SPACE_SPI0        = 32'h 80300000;
-  localparam logic [31:0] ADDR_SPACE_SPI1        = 32'h 80301000;
-  localparam logic [31:0] ADDR_SPACE_SPI2        = 32'h 80302000;
-  localparam logic [31:0] ADDR_SPACE_SPI3        = 32'h 80303000;
-  localparam logic [31:0] ADDR_SPACE_SPI4        = 32'h 80304000;
+  localparam logic [31:0] ADDR_SPACE_SPI0        = 32'h 80302000;
+  localparam logic [31:0] ADDR_SPACE_SPI1        = 32'h 80303000;
   localparam logic [31:0] ADDR_SPACE_USBDEV      = 32'h 80400000;
   localparam logic [31:0] ADDR_SPACE_RV_PLIC     = 32'h 88000000;
 
@@ -40,6 +39,8 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_MASK_XADC        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_SYSTEM_INFO = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_TIMER       = 32'h 0000ffff;
+  localparam logic [31:0] ADDR_MASK_SPI_BOARD   = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_SPI_LCD     = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_PWM0        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_UART0       = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_UART1       = 32'h 00000fff;
@@ -48,14 +49,11 @@ package tl_main_pkg;
   localparam logic [31:0] ADDR_MASK_I2C1        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_SPI0        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_SPI1        = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_SPI2        = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_SPI3        = 32'h 00000fff;
-  localparam logic [31:0] ADDR_MASK_SPI4        = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_USBDEV      = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_RV_PLIC     = 32'h 03ffffff;
 
   localparam int N_HOST   = 2;
-  localparam int N_DEVICE = 23;
+  localparam int N_DEVICE = 22;
 
   typedef enum int {
     TlSram = 0,
@@ -68,19 +66,18 @@ package tl_main_pkg;
     TlXadc = 7,
     TlSystemInfo = 8,
     TlTimer = 9,
-    TlPwm0 = 10,
-    TlUart0 = 11,
-    TlUart1 = 12,
-    TlUart2 = 13,
-    TlI2C0 = 14,
-    TlI2C1 = 15,
-    TlSpi0 = 16,
-    TlSpi1 = 17,
-    TlSpi2 = 18,
-    TlSpi3 = 19,
-    TlSpi4 = 20,
-    TlUsbdev = 21,
-    TlRvPlic = 22
+    TlSpiBoard = 10,
+    TlSpiLcd = 11,
+    TlPwm0 = 12,
+    TlUart0 = 13,
+    TlUart1 = 14,
+    TlUart2 = 15,
+    TlI2C0 = 16,
+    TlI2C1 = 17,
+    TlSpi0 = 18,
+    TlSpi1 = 19,
+    TlUsbdev = 20,
+    TlRvPlic = 21
   } tl_device_e;
 
   typedef enum int {
diff --git a/rtl/bus/xbar_main.sv b/rtl/bus/xbar_main.sv
index b50cc690f..9c508a92c 100644
--- a/rtl/bus/xbar_main.sv
+++ b/rtl/bus/xbar_main.sv
@@ -7,8 +7,8 @@
 //
 // Interconnect
 // ibex_lsu
-//   -> s1n_25
-//     -> sm1_26
+//   -> s1n_24
+//     -> sm1_25
 //       -> sram
 //     -> hyperram
 //     -> rev_tag
@@ -19,6 +19,8 @@
 //     -> hw_rev
 //     -> xadc
 //     -> timer
+//     -> spi_board
+//     -> spi_lcd
 //     -> pwm0
 //     -> uart0
 //     -> uart1
@@ -27,14 +29,11 @@
 //     -> i2c1
 //     -> spi0
 //     -> spi1
-//     -> spi2
-//     -> spi3
-//     -> spi4
-//     -> asf_27
+//     -> asf_26
 //       -> usbdev
 //     -> rv_plic
 // dbg_host
-//   -> sm1_26
+//   -> sm1_25
 //     -> sram
 
 module xbar_main (
@@ -70,6 +69,10 @@ module xbar_main (
   input  tlul_pkg::tl_d2h_t tl_system_info_i,
   output tlul_pkg::tl_h2d_t tl_timer_o,
   input  tlul_pkg::tl_d2h_t tl_timer_i,
+  output tlul_pkg::tl_h2d_t tl_spi_board_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_board_i,
+  output tlul_pkg::tl_h2d_t tl_spi_lcd_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_lcd_i,
   output tlul_pkg::tl_h2d_t tl_pwm0_o,
   input  tlul_pkg::tl_d2h_t tl_pwm0_i,
   output tlul_pkg::tl_h2d_t tl_uart0_o,
@@ -86,12 +89,6 @@ module xbar_main (
   input  tlul_pkg::tl_d2h_t tl_spi0_i,
   output tlul_pkg::tl_h2d_t tl_spi1_o,
   input  tlul_pkg::tl_d2h_t tl_spi1_i,
-  output tlul_pkg::tl_h2d_t tl_spi2_o,
-  input  tlul_pkg::tl_d2h_t tl_spi2_i,
-  output tlul_pkg::tl_h2d_t tl_spi3_o,
-  input  tlul_pkg::tl_d2h_t tl_spi3_i,
-  output tlul_pkg::tl_h2d_t tl_spi4_o,
-  input  tlul_pkg::tl_d2h_t tl_spi4_i,
   output tlul_pkg::tl_h2d_t tl_usbdev_o,
   input  tlul_pkg::tl_d2h_t tl_usbdev_i,
   output tlul_pkg::tl_h2d_t tl_rv_plic_o,
@@ -108,205 +105,198 @@ module xbar_main (
   logic unused_scanmode;
   assign unused_scanmode = ^scanmode_i;
 
-  tl_h2d_t tl_s1n_25_us_h2d ;
-  tl_d2h_t tl_s1n_25_us_d2h ;
+  tl_h2d_t tl_s1n_24_us_h2d ;
+  tl_d2h_t tl_s1n_24_us_d2h ;
 
 
-  tl_h2d_t tl_s1n_25_ds_h2d [23];
-  tl_d2h_t tl_s1n_25_ds_d2h [23];
+  tl_h2d_t tl_s1n_24_ds_h2d [22];
+  tl_d2h_t tl_s1n_24_ds_d2h [22];
 
   // Create steering signal
-  logic [4:0] dev_sel_s1n_25;
+  logic [4:0] dev_sel_s1n_24;
 
 
-  tl_h2d_t tl_sm1_26_us_h2d [2];
-  tl_d2h_t tl_sm1_26_us_d2h [2];
+  tl_h2d_t tl_sm1_25_us_h2d [2];
+  tl_d2h_t tl_sm1_25_us_d2h [2];
 
-  tl_h2d_t tl_sm1_26_ds_h2d ;
-  tl_d2h_t tl_sm1_26_ds_d2h ;
+  tl_h2d_t tl_sm1_25_ds_h2d ;
+  tl_d2h_t tl_sm1_25_ds_d2h ;
 
-  tl_h2d_t tl_asf_27_us_h2d ;
-  tl_d2h_t tl_asf_27_us_d2h ;
-  tl_h2d_t tl_asf_27_ds_h2d ;
-  tl_d2h_t tl_asf_27_ds_d2h ;
+  tl_h2d_t tl_asf_26_us_h2d ;
+  tl_d2h_t tl_asf_26_us_d2h ;
+  tl_h2d_t tl_asf_26_ds_h2d ;
+  tl_d2h_t tl_asf_26_ds_d2h ;
 
 
 
-  assign tl_sm1_26_us_h2d[0] = tl_s1n_25_ds_h2d[0];
-  assign tl_s1n_25_ds_d2h[0] = tl_sm1_26_us_d2h[0];
+  assign tl_sm1_25_us_h2d[0] = tl_s1n_24_ds_h2d[0];
+  assign tl_s1n_24_ds_d2h[0] = tl_sm1_25_us_d2h[0];
 
-  assign tl_hyperram_o = tl_s1n_25_ds_h2d[1];
-  assign tl_s1n_25_ds_d2h[1] = tl_hyperram_i;
+  assign tl_hyperram_o = tl_s1n_24_ds_h2d[1];
+  assign tl_s1n_24_ds_d2h[1] = tl_hyperram_i;
 
-  assign tl_rev_tag_o = tl_s1n_25_ds_h2d[2];
-  assign tl_s1n_25_ds_d2h[2] = tl_rev_tag_i;
+  assign tl_rev_tag_o = tl_s1n_24_ds_h2d[2];
+  assign tl_s1n_24_ds_d2h[2] = tl_rev_tag_i;
 
-  assign tl_gpio_o = tl_s1n_25_ds_h2d[3];
-  assign tl_s1n_25_ds_d2h[3] = tl_gpio_i;
+  assign tl_gpio_o = tl_s1n_24_ds_h2d[3];
+  assign tl_s1n_24_ds_d2h[3] = tl_gpio_i;
 
-  assign tl_pinmux_o = tl_s1n_25_ds_h2d[4];
-  assign tl_s1n_25_ds_d2h[4] = tl_pinmux_i;
+  assign tl_pinmux_o = tl_s1n_24_ds_h2d[4];
+  assign tl_s1n_24_ds_d2h[4] = tl_pinmux_i;
 
-  assign tl_system_info_o = tl_s1n_25_ds_h2d[5];
-  assign tl_s1n_25_ds_d2h[5] = tl_system_info_i;
+  assign tl_system_info_o = tl_s1n_24_ds_h2d[5];
+  assign tl_s1n_24_ds_d2h[5] = tl_system_info_i;
 
-  assign tl_rgbled_ctrl_o = tl_s1n_25_ds_h2d[6];
-  assign tl_s1n_25_ds_d2h[6] = tl_rgbled_ctrl_i;
+  assign tl_rgbled_ctrl_o = tl_s1n_24_ds_h2d[6];
+  assign tl_s1n_24_ds_d2h[6] = tl_rgbled_ctrl_i;
 
-  assign tl_hw_rev_o = tl_s1n_25_ds_h2d[7];
-  assign tl_s1n_25_ds_d2h[7] = tl_hw_rev_i;
+  assign tl_hw_rev_o = tl_s1n_24_ds_h2d[7];
+  assign tl_s1n_24_ds_d2h[7] = tl_hw_rev_i;
 
-  assign tl_xadc_o = tl_s1n_25_ds_h2d[8];
-  assign tl_s1n_25_ds_d2h[8] = tl_xadc_i;
+  assign tl_xadc_o = tl_s1n_24_ds_h2d[8];
+  assign tl_s1n_24_ds_d2h[8] = tl_xadc_i;
 
-  assign tl_timer_o = tl_s1n_25_ds_h2d[9];
-  assign tl_s1n_25_ds_d2h[9] = tl_timer_i;
+  assign tl_timer_o = tl_s1n_24_ds_h2d[9];
+  assign tl_s1n_24_ds_d2h[9] = tl_timer_i;
 
-  assign tl_pwm0_o = tl_s1n_25_ds_h2d[10];
-  assign tl_s1n_25_ds_d2h[10] = tl_pwm0_i;
+  assign tl_spi_board_o = tl_s1n_24_ds_h2d[10];
+  assign tl_s1n_24_ds_d2h[10] = tl_spi_board_i;
 
-  assign tl_uart0_o = tl_s1n_25_ds_h2d[11];
-  assign tl_s1n_25_ds_d2h[11] = tl_uart0_i;
+  assign tl_spi_lcd_o = tl_s1n_24_ds_h2d[11];
+  assign tl_s1n_24_ds_d2h[11] = tl_spi_lcd_i;
 
-  assign tl_uart1_o = tl_s1n_25_ds_h2d[12];
-  assign tl_s1n_25_ds_d2h[12] = tl_uart1_i;
+  assign tl_pwm0_o = tl_s1n_24_ds_h2d[12];
+  assign tl_s1n_24_ds_d2h[12] = tl_pwm0_i;
 
-  assign tl_uart2_o = tl_s1n_25_ds_h2d[13];
-  assign tl_s1n_25_ds_d2h[13] = tl_uart2_i;
+  assign tl_uart0_o = tl_s1n_24_ds_h2d[13];
+  assign tl_s1n_24_ds_d2h[13] = tl_uart0_i;
 
-  assign tl_i2c0_o = tl_s1n_25_ds_h2d[14];
-  assign tl_s1n_25_ds_d2h[14] = tl_i2c0_i;
+  assign tl_uart1_o = tl_s1n_24_ds_h2d[14];
+  assign tl_s1n_24_ds_d2h[14] = tl_uart1_i;
 
-  assign tl_i2c1_o = tl_s1n_25_ds_h2d[15];
-  assign tl_s1n_25_ds_d2h[15] = tl_i2c1_i;
+  assign tl_uart2_o = tl_s1n_24_ds_h2d[15];
+  assign tl_s1n_24_ds_d2h[15] = tl_uart2_i;
 
-  assign tl_spi0_o = tl_s1n_25_ds_h2d[16];
-  assign tl_s1n_25_ds_d2h[16] = tl_spi0_i;
+  assign tl_i2c0_o = tl_s1n_24_ds_h2d[16];
+  assign tl_s1n_24_ds_d2h[16] = tl_i2c0_i;
 
-  assign tl_spi1_o = tl_s1n_25_ds_h2d[17];
-  assign tl_s1n_25_ds_d2h[17] = tl_spi1_i;
+  assign tl_i2c1_o = tl_s1n_24_ds_h2d[17];
+  assign tl_s1n_24_ds_d2h[17] = tl_i2c1_i;
 
-  assign tl_spi2_o = tl_s1n_25_ds_h2d[18];
-  assign tl_s1n_25_ds_d2h[18] = tl_spi2_i;
+  assign tl_spi0_o = tl_s1n_24_ds_h2d[18];
+  assign tl_s1n_24_ds_d2h[18] = tl_spi0_i;
 
-  assign tl_spi3_o = tl_s1n_25_ds_h2d[19];
-  assign tl_s1n_25_ds_d2h[19] = tl_spi3_i;
+  assign tl_spi1_o = tl_s1n_24_ds_h2d[19];
+  assign tl_s1n_24_ds_d2h[19] = tl_spi1_i;
 
-  assign tl_spi4_o = tl_s1n_25_ds_h2d[20];
-  assign tl_s1n_25_ds_d2h[20] = tl_spi4_i;
+  assign tl_asf_26_us_h2d = tl_s1n_24_ds_h2d[20];
+  assign tl_s1n_24_ds_d2h[20] = tl_asf_26_us_d2h;
 
-  assign tl_asf_27_us_h2d = tl_s1n_25_ds_h2d[21];
-  assign tl_s1n_25_ds_d2h[21] = tl_asf_27_us_d2h;
+  assign tl_rv_plic_o = tl_s1n_24_ds_h2d[21];
+  assign tl_s1n_24_ds_d2h[21] = tl_rv_plic_i;
 
-  assign tl_rv_plic_o = tl_s1n_25_ds_h2d[22];
-  assign tl_s1n_25_ds_d2h[22] = tl_rv_plic_i;
+  assign tl_sm1_25_us_h2d[1] = tl_dbg_host_i;
+  assign tl_dbg_host_o = tl_sm1_25_us_d2h[1];
 
-  assign tl_sm1_26_us_h2d[1] = tl_dbg_host_i;
-  assign tl_dbg_host_o = tl_sm1_26_us_d2h[1];
+  assign tl_s1n_24_us_h2d = tl_ibex_lsu_i;
+  assign tl_ibex_lsu_o = tl_s1n_24_us_d2h;
 
-  assign tl_s1n_25_us_h2d = tl_ibex_lsu_i;
-  assign tl_ibex_lsu_o = tl_s1n_25_us_d2h;
+  assign tl_sram_o = tl_sm1_25_ds_h2d;
+  assign tl_sm1_25_ds_d2h = tl_sram_i;
 
-  assign tl_sram_o = tl_sm1_26_ds_h2d;
-  assign tl_sm1_26_ds_d2h = tl_sram_i;
-
-  assign tl_usbdev_o = tl_asf_27_ds_h2d;
-  assign tl_asf_27_ds_d2h = tl_usbdev_i;
+  assign tl_usbdev_o = tl_asf_26_ds_h2d;
+  assign tl_asf_26_ds_d2h = tl_usbdev_i;
 
   always_comb begin
     // default steering to generate error response if address is not within the range
-    dev_sel_s1n_25 = 5'd23;
-    if ((tl_s1n_25_us_h2d.a_address &
+    dev_sel_s1n_24 = 5'd22;
+    if ((tl_s1n_24_us_h2d.a_address &
          ~(ADDR_MASK_SRAM)) == ADDR_SPACE_SRAM) begin
-      dev_sel_s1n_25 = 5'd0;
+      dev_sel_s1n_24 = 5'd0;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_HYPERRAM)) == ADDR_SPACE_HYPERRAM) begin
-      dev_sel_s1n_25 = 5'd1;
+      dev_sel_s1n_24 = 5'd1;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_REV_TAG)) == ADDR_SPACE_REV_TAG) begin
-      dev_sel_s1n_25 = 5'd2;
+      dev_sel_s1n_24 = 5'd2;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
-      dev_sel_s1n_25 = 5'd3;
+      dev_sel_s1n_24 = 5'd3;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
-      dev_sel_s1n_25 = 5'd4;
+      dev_sel_s1n_24 = 5'd4;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_SYSTEM_INFO)) == ADDR_SPACE_SYSTEM_INFO) begin
-      dev_sel_s1n_25 = 5'd5;
+      dev_sel_s1n_24 = 5'd5;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_RGBLED_CTRL)) == ADDR_SPACE_RGBLED_CTRL) begin
-      dev_sel_s1n_25 = 5'd6;
+      dev_sel_s1n_24 = 5'd6;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_HW_REV)) == ADDR_SPACE_HW_REV) begin
-      dev_sel_s1n_25 = 5'd7;
+      dev_sel_s1n_24 = 5'd7;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_XADC)) == ADDR_SPACE_XADC) begin
-      dev_sel_s1n_25 = 5'd8;
+      dev_sel_s1n_24 = 5'd8;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_TIMER)) == ADDR_SPACE_TIMER) begin
-      dev_sel_s1n_25 = 5'd9;
+      dev_sel_s1n_24 = 5'd9;
+
+    end else if ((tl_s1n_24_us_h2d.a_address &
+                  ~(ADDR_MASK_SPI_BOARD)) == ADDR_SPACE_SPI_BOARD) begin
+      dev_sel_s1n_24 = 5'd10;
+
+    end else if ((tl_s1n_24_us_h2d.a_address &
+                  ~(ADDR_MASK_SPI_LCD)) == ADDR_SPACE_SPI_LCD) begin
+      dev_sel_s1n_24 = 5'd11;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_PWM0)) == ADDR_SPACE_PWM0) begin
-      dev_sel_s1n_25 = 5'd10;
+      dev_sel_s1n_24 = 5'd12;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
-      dev_sel_s1n_25 = 5'd11;
+      dev_sel_s1n_24 = 5'd13;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
-      dev_sel_s1n_25 = 5'd12;
+      dev_sel_s1n_24 = 5'd14;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
-      dev_sel_s1n_25 = 5'd13;
+      dev_sel_s1n_24 = 5'd15;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
-      dev_sel_s1n_25 = 5'd14;
+      dev_sel_s1n_24 = 5'd16;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
-      dev_sel_s1n_25 = 5'd15;
+      dev_sel_s1n_24 = 5'd17;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_SPI0)) == ADDR_SPACE_SPI0) begin
-      dev_sel_s1n_25 = 5'd16;
+      dev_sel_s1n_24 = 5'd18;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_SPI1)) == ADDR_SPACE_SPI1) begin
-      dev_sel_s1n_25 = 5'd17;
-
-    end else if ((tl_s1n_25_us_h2d.a_address &
-                  ~(ADDR_MASK_SPI2)) == ADDR_SPACE_SPI2) begin
-      dev_sel_s1n_25 = 5'd18;
-
-    end else if ((tl_s1n_25_us_h2d.a_address &
-                  ~(ADDR_MASK_SPI3)) == ADDR_SPACE_SPI3) begin
-      dev_sel_s1n_25 = 5'd19;
-
-    end else if ((tl_s1n_25_us_h2d.a_address &
-                  ~(ADDR_MASK_SPI4)) == ADDR_SPACE_SPI4) begin
-      dev_sel_s1n_25 = 5'd20;
+      dev_sel_s1n_24 = 5'd19;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
-      dev_sel_s1n_25 = 5'd21;
+      dev_sel_s1n_24 = 5'd20;
 
-    end else if ((tl_s1n_25_us_h2d.a_address &
+    end else if ((tl_s1n_24_us_h2d.a_address &
                   ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
-      dev_sel_s1n_25 = 5'd22;
+      dev_sel_s1n_24 = 5'd21;
 end
   end
 
@@ -315,19 +305,19 @@ end
   tlul_socket_1n #(
     .HReqDepth (4'h0),
     .HRspDepth (4'h0),
-    .DReqPass  (23'h3f02a7),
-    .DRspPass  (23'h3f02a7),
-    .DReqDepth (92'h10000001111110101011000),
-    .DRspDepth (92'h10000001111110101011000),
-    .N         (23)
-  ) u_s1n_25 (
+    .DReqPass  (22'h1c0ea7),
+    .DRspPass  (22'h1c0ea7),
+    .DReqDepth (88'h1000111111000101011000),
+    .DRspDepth (88'h1000111111000101011000),
+    .N         (22)
+  ) u_s1n_24 (
     .clk_i        (clk_sys_i),
     .rst_ni       (rst_sys_ni),
-    .tl_h_i       (tl_s1n_25_us_h2d),
-    .tl_h_o       (tl_s1n_25_us_d2h),
-    .tl_d_o       (tl_s1n_25_ds_h2d),
-    .tl_d_i       (tl_s1n_25_ds_d2h),
-    .dev_select_i (dev_sel_s1n_25)
+    .tl_h_i       (tl_s1n_24_us_h2d),
+    .tl_h_o       (tl_s1n_24_us_d2h),
+    .tl_d_o       (tl_s1n_24_ds_h2d),
+    .tl_d_i       (tl_s1n_24_ds_d2h),
+    .dev_select_i (dev_sel_s1n_24)
   );
   tlul_socket_m1 #(
     .HReqPass  (2'h1),
@@ -336,26 +326,26 @@ end
     .DReqDepth (4'h0),
     .DRspDepth (4'h0),
     .M         (2)
-  ) u_sm1_26 (
+  ) u_sm1_25 (
     .clk_i        (clk_sys_i),
     .rst_ni       (rst_sys_ni),
-    .tl_h_i       (tl_sm1_26_us_h2d),
-    .tl_h_o       (tl_sm1_26_us_d2h),
-    .tl_d_o       (tl_sm1_26_ds_h2d),
-    .tl_d_i       (tl_sm1_26_ds_d2h)
+    .tl_h_i       (tl_sm1_25_us_h2d),
+    .tl_h_o       (tl_sm1_25_us_d2h),
+    .tl_d_o       (tl_sm1_25_ds_h2d),
+    .tl_d_i       (tl_sm1_25_ds_d2h)
   );
   tlul_fifo_async #(
     .ReqDepth        (1),
     .RspDepth        (1)
-  ) u_asf_27 (
+  ) u_asf_26 (
     .clk_h_i      (clk_sys_i),
     .rst_h_ni     (rst_sys_ni),
     .clk_d_i      (clk_usb_i),
     .rst_d_ni     (rst_usb_ni),
-    .tl_h_i       (tl_asf_27_us_h2d),
-    .tl_h_o       (tl_asf_27_us_d2h),
-    .tl_d_o       (tl_asf_27_ds_h2d),
-    .tl_d_i       (tl_asf_27_ds_d2h)
+    .tl_h_i       (tl_asf_26_us_h2d),
+    .tl_h_o       (tl_asf_26_us_d2h),
+    .tl_d_o       (tl_asf_26_ds_h2d),
+    .tl_d_i       (tl_asf_26_ds_d2h)
   );
 
 endmodule
diff --git a/rtl/fpga/top_sonata.sv b/rtl/fpga/top_sonata.sv
index ac3bc356f..8fca22684 100644
--- a/rtl/fpga/top_sonata.sv
+++ b/rtl/fpga/top_sonata.sv
@@ -251,7 +251,17 @@ module top_sonata
   assign enable_cheri = 1'b1;
 
   logic rgbled_dout;
-  logic [18:0] unused_gp_o;
+  logic [23:0] unused_gp_o;
+
+  wire spi_board_copi;
+  wire spi_board_cipo;
+  wire spi_board_sclk;
+
+  assign spi_board_cipo = &{1'b1, appspi_d1, ethmac_cipo, microsd_dat0};
+
+  assign {appspi_d0,   appspi_clk}   = {spi_board_copi, spi_board_sclk};
+  assign {ethmac_copi, ethmac_sclk}  = {spi_board_copi, spi_board_sclk};
+  assign {microsd_cmd, microsd_clk}  = {spi_board_copi, spi_board_sclk};
 
   sonata_system #(
     .CheriErrWidth   (  9             ),
@@ -276,8 +286,7 @@ module top_sonata
 
     // GPIO
     .gp_i           ({
-                      14'b0,
-                      mb9, // mikroBUS Click interrupt
+                      15'b0,
                       microsd_det, // MicroSD card insertion detection
                       sel_sw_n, // Software selection switches
                       nav_sw_n, // joystick
@@ -285,9 +294,6 @@ module top_sonata
                     }),
     .gp_o           ({
                       unused_gp_o,
-                      mb0, // mikroBUS Click reset
-                      ethmac_rst, // Ethernet
-                      lcd_backlight, lcd_dc, lcd_rst, // LCD screen
                       usrLed // User LEDs (8 bits)
                     }),
     .gp_o_en        (),
@@ -297,6 +303,22 @@ module top_sonata
     .ard_an_p_i     (ard_an_p),
     .ard_an_n_i     (ard_an_n),
 
+    // Non-pinmuxed spi devices
+    .lcd_copi_o              (lcd_copi),
+    .lcd_sclk_o              (lcd_clk),
+    .lcd_cs_o                (lcd_cs),
+    .lcd_dc_o                (lcd_dc),
+    .lcd_rst_o               (lcd_rst),
+    .lcd_backlight_o         (lcd_backlight),
+
+    .spi_board_copi_o        (spi_board_copi),
+    .spi_board_cipo_i        (spi_board_cipo),
+    .spi_board_sclk_o        (spi_board_sclk),
+    .spi_board_flash_cs_o    (appspi_cs),
+    .spi_board_eth_cs_o      (ethmac_cs),
+    .spi_board_eth_rst_o     (ethmac_rst),
+    .spi_board_microsd_cs_o  (microsd_dat3),
+
     // Interrupt for Ethernet is out of band
     .spi_eth_irq_ni (ethmac_intr),
 
@@ -392,32 +414,17 @@ module top_sonata
   );
 
   // Input Pins
-  assign in_from_pins[IN_PIN_MICROSD_DAT0] = microsd_dat0;
   assign in_from_pins[IN_PIN_MB8         ] = mb8;
   assign in_from_pins[IN_PIN_MB3         ] = mb3;
-  assign in_from_pins[IN_PIN_ETHMAC_CIPO ] = ethmac_cipo;
-  assign in_from_pins[IN_PIN_APPSPI_D1   ] = appspi_d1;
   assign in_from_pins[IN_PIN_RS232_RX    ] = rs232_rx;
   assign in_from_pins[IN_PIN_SER1_RX     ] = ser1_rx;
   assign in_from_pins[IN_PIN_SER0_RX     ] = ser0_rx;
 
-  assign microsd_dat3 = out_to_pins[OUT_PIN_MICROSD_DAT3];
-  assign microsd_cmd  = out_to_pins[OUT_PIN_MICROSD_CMD ];
-  assign microsd_clk  = out_to_pins[OUT_PIN_MICROSD_CLK ];
   assign mb10         = out_to_pins[OUT_PIN_MB10        ];
   assign mb7          = out_to_pins[OUT_PIN_MB7         ];
   assign mb4          = out_to_pins[OUT_PIN_MB4         ];
   assign mb2          = out_to_pins[OUT_PIN_MB2         ];
   assign mb1          = out_to_pins[OUT_PIN_MB1         ];
-  assign ethmac_cs    = out_to_pins[OUT_PIN_ETHMAC_CS   ];
-  assign ethmac_sclk  = out_to_pins[OUT_PIN_ETHMAC_SCLK ];
-  assign ethmac_copi  = out_to_pins[OUT_PIN_ETHMAC_COPI ];
-  assign lcd_cs       = out_to_pins[OUT_PIN_LCD_CS      ];
-  assign lcd_clk      = out_to_pins[OUT_PIN_LCD_CLK     ];
-  assign lcd_copi     = out_to_pins[OUT_PIN_LCD_COPI    ];
-  assign appspi_cs    = out_to_pins[OUT_PIN_APPSPI_CS   ];
-  assign appspi_clk   = out_to_pins[OUT_PIN_APPSPI_CLK  ];
-  assign appspi_d0    = out_to_pins[OUT_PIN_APPSPI_D0   ];
   assign rs232_tx     = out_to_pins[OUT_PIN_RS232_TX    ];
   assign ser1_tx      = out_to_pins[OUT_PIN_SER1_TX     ];
   assign ser0_tx      = out_to_pins[OUT_PIN_SER0_TX     ];
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index 841d55ae8..1b1424250 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -440,446 +440,14 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_SDA1])
   );
 
-  logic [1:0] appspi_d0_sel;
-  logic appspi_d0_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign appspi_d0_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 4 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      appspi_d0_sel <= 2'b10;
-    end else begin
-      if (reg_we & appspi_d0_sel_addressed) begin
-        appspi_d0_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) appspi_d0_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[0]
-    }),
-    .sel_i(appspi_d0_sel),
-    .out_o(out_to_pins_o[OUT_PIN_APPSPI_D0])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) appspi_d0_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_copi_en_i[0]
-    }),
-    .sel_i(appspi_d0_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_APPSPI_D0])
-  );
-
-  logic [1:0] appspi_clk_sel;
-  logic appspi_clk_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign appspi_clk_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 8 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      appspi_clk_sel <= 2'b10;
-    end else begin
-      if (reg_we & appspi_clk_sel_addressed) begin
-        appspi_clk_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) appspi_clk_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[0]
-    }),
-    .sel_i(appspi_clk_sel),
-    .out_o(out_to_pins_o[OUT_PIN_APPSPI_CLK])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) appspi_clk_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_sclk_en_i[0]
-    }),
-    .sel_i(appspi_clk_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_APPSPI_CLK])
-  );
-
-  logic [1:0] appspi_cs_sel;
-  logic appspi_cs_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign appspi_cs_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 8 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      appspi_cs_sel <= 2'b10;
-    end else begin
-      if (reg_we & appspi_cs_sel_addressed) begin
-        appspi_cs_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) appspi_cs_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[0][0]
-    }),
-    .sel_i(appspi_cs_sel),
-    .out_o(out_to_pins_o[OUT_PIN_APPSPI_CS])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) appspi_cs_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_cs_en_i[0][0]
-    }),
-    .sel_i(appspi_cs_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_APPSPI_CS])
-  );
-
-  logic [1:0] lcd_copi_sel;
-  logic lcd_copi_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign lcd_copi_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 8 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      lcd_copi_sel <= 2'b10;
-    end else begin
-      if (reg_we & lcd_copi_sel_addressed) begin
-        lcd_copi_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) lcd_copi_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[1]
-    }),
-    .sel_i(lcd_copi_sel),
-    .out_o(out_to_pins_o[OUT_PIN_LCD_COPI])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) lcd_copi_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_copi_en_i[1]
-    }),
-    .sel_i(lcd_copi_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_LCD_COPI])
-  );
-
-  logic [1:0] lcd_clk_sel;
-  logic lcd_clk_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign lcd_clk_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 8 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      lcd_clk_sel <= 2'b10;
-    end else begin
-      if (reg_we & lcd_clk_sel_addressed) begin
-        lcd_clk_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) lcd_clk_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[1]
-    }),
-    .sel_i(lcd_clk_sel),
-    .out_o(out_to_pins_o[OUT_PIN_LCD_CLK])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) lcd_clk_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_sclk_en_i[1]
-    }),
-    .sel_i(lcd_clk_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_LCD_CLK])
-  );
-
-  logic [1:0] lcd_cs_sel;
-  logic lcd_cs_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign lcd_cs_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 12 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      lcd_cs_sel <= 2'b10;
-    end else begin
-      if (reg_we & lcd_cs_sel_addressed) begin
-        lcd_cs_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) lcd_cs_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[1][0]
-    }),
-    .sel_i(lcd_cs_sel),
-    .out_o(out_to_pins_o[OUT_PIN_LCD_CS])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) lcd_cs_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_cs_en_i[1][0]
-    }),
-    .sel_i(lcd_cs_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_LCD_CS])
-  );
-
-  logic [1:0] ethmac_copi_sel;
-  logic ethmac_copi_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign ethmac_copi_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 12 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ethmac_copi_sel <= 2'b10;
-    end else begin
-      if (reg_we & ethmac_copi_sel_addressed) begin
-        ethmac_copi_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) ethmac_copi_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[2]
-    }),
-    .sel_i(ethmac_copi_sel),
-    .out_o(out_to_pins_o[OUT_PIN_ETHMAC_COPI])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) ethmac_copi_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_copi_en_i[2]
-    }),
-    .sel_i(ethmac_copi_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_ETHMAC_COPI])
-  );
-
-  logic [1:0] ethmac_sclk_sel;
-  logic ethmac_sclk_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign ethmac_sclk_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 12 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ethmac_sclk_sel <= 2'b10;
-    end else begin
-      if (reg_we & ethmac_sclk_sel_addressed) begin
-        ethmac_sclk_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) ethmac_sclk_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[2]
-    }),
-    .sel_i(ethmac_sclk_sel),
-    .out_o(out_to_pins_o[OUT_PIN_ETHMAC_SCLK])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) ethmac_sclk_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_sclk_en_i[2]
-    }),
-    .sel_i(ethmac_sclk_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_ETHMAC_SCLK])
-  );
-
-  logic [1:0] ethmac_cs_sel;
-  logic ethmac_cs_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign ethmac_cs_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 12 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ethmac_cs_sel <= 2'b10;
-    end else begin
-      if (reg_we & ethmac_cs_sel_addressed) begin
-        ethmac_cs_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) ethmac_cs_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[2][0]
-    }),
-    .sel_i(ethmac_cs_sel),
-    .out_o(out_to_pins_o[OUT_PIN_ETHMAC_CS])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) ethmac_cs_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_cs_en_i[2][0]
-    }),
-    .sel_i(ethmac_cs_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_ETHMAC_CS])
-  );
-
   logic [2:0] rph_g0_sel;
   logic rph_g0_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 16 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 4 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -887,7 +455,7 @@ module pinmux
       rph_g0_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g0_sel_addressed) begin
-        rph_g0_sel <= reg_wdata[0+:3];
+        rph_g0_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -928,8 +496,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 16 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 8 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -937,7 +505,7 @@ module pinmux
       rph_g1_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g1_sel_addressed) begin
-        rph_g1_sel <= reg_wdata[8+:3];
+        rph_g1_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -978,8 +546,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g2_sda_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 16 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 8 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -987,7 +555,7 @@ module pinmux
       rph_g2_sda_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g2_sda_sel_addressed) begin
-        rph_g2_sda_sel <= reg_wdata[16+:3];
+        rph_g2_sda_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -1028,8 +596,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g3_scl_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 16 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 8 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1037,7 +605,7 @@ module pinmux
       rph_g3_scl_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g3_scl_sel_addressed) begin
-        rph_g3_scl_sel <= reg_wdata[24+:3];
+        rph_g3_scl_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -1078,8 +646,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 20 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 8 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1087,7 +655,7 @@ module pinmux
       rph_g4_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g4_sel_addressed) begin
-        rph_g4_sel <= reg_wdata[0+:2];
+        rph_g4_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -1126,8 +694,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 20 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 12 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1135,7 +703,7 @@ module pinmux
       rph_g5_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g5_sel_addressed) begin
-        rph_g5_sel <= reg_wdata[8+:2];
+        rph_g5_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -1174,8 +742,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 20 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 12 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1183,7 +751,7 @@ module pinmux
       rph_g6_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g6_sel_addressed) begin
-        rph_g6_sel <= reg_wdata[16+:2];
+        rph_g6_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -1222,8 +790,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g7_ce1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 20 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 12 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1231,7 +799,7 @@ module pinmux
       rph_g7_ce1_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g7_ce1_sel_addressed) begin
-        rph_g7_ce1_sel <= reg_wdata[24+:3];
+        rph_g7_ce1_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -1244,7 +812,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[2][0],
+      spi_cs_i[0][0],
       gpio_ios_i[0][7]
     }),
     .sel_i(rph_g7_ce1_sel),
@@ -1259,7 +827,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[2][0],
+      spi_cs_en_i[0][0],
       gpio_ios_en_i[0][7]
     }),
     .sel_i(rph_g7_ce1_sel),
@@ -1272,8 +840,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g8_ce0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 24 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 12 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1281,7 +849,7 @@ module pinmux
       rph_g8_ce0_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g8_ce0_sel_addressed) begin
-        rph_g8_ce0_sel <= reg_wdata[0+:3];
+        rph_g8_ce0_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -1294,7 +862,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[2][1],
+      spi_cs_i[0][1],
       gpio_ios_i[0][8]
     }),
     .sel_i(rph_g8_ce0_sel),
@@ -1309,7 +877,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[2][1],
+      spi_cs_en_i[0][1],
       gpio_ios_en_i[0][8]
     }),
     .sel_i(rph_g8_ce0_sel),
@@ -1322,8 +890,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g9_cipo_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 24 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 16 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1331,7 +899,7 @@ module pinmux
       rph_g9_cipo_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g9_cipo_sel_addressed) begin
-        rph_g9_cipo_sel <= reg_wdata[8+:2];
+        rph_g9_cipo_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -1370,8 +938,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g10_copi_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 24 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 16 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1379,7 +947,7 @@ module pinmux
       rph_g10_copi_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g10_copi_sel_addressed) begin
-        rph_g10_copi_sel <= reg_wdata[16+:3];
+        rph_g10_copi_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -1392,7 +960,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[2],
+      spi_copi_i[0],
       gpio_ios_i[0][10]
     }),
     .sel_i(rph_g10_copi_sel),
@@ -1407,7 +975,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[2],
+      spi_copi_en_i[0],
       gpio_ios_en_i[0][10]
     }),
     .sel_i(rph_g10_copi_sel),
@@ -1420,8 +988,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g11_sclk_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 24 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 16 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1429,7 +997,7 @@ module pinmux
       rph_g11_sclk_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g11_sclk_sel_addressed) begin
-        rph_g11_sclk_sel <= reg_wdata[24+:3];
+        rph_g11_sclk_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -1442,7 +1010,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[2],
+      spi_sclk_i[0],
       gpio_ios_i[0][11]
     }),
     .sel_i(rph_g11_sclk_sel),
@@ -1457,7 +1025,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[2],
+      spi_sclk_en_i[0],
       gpio_ios_en_i[0][11]
     }),
     .sel_i(rph_g11_sclk_sel),
@@ -1470,8 +1038,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g12_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 16 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1479,7 +1047,7 @@ module pinmux
       rph_g12_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g12_sel_addressed) begin
-        rph_g12_sel <= reg_wdata[0+:3];
+        rph_g12_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -1520,8 +1088,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g13_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 20 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1529,7 +1097,7 @@ module pinmux
       rph_g13_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g13_sel_addressed) begin
-        rph_g13_sel <= reg_wdata[8+:3];
+        rph_g13_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -1570,8 +1138,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_txd0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 20 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1579,7 +1147,7 @@ module pinmux
       rph_txd0_sel <= 3'b10;
     end else begin
       if (reg_we & rph_txd0_sel_addressed) begin
-        rph_txd0_sel <= reg_wdata[16+:3];
+        rph_txd0_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -1620,8 +1188,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_rxd0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 20 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1629,7 +1197,7 @@ module pinmux
       rph_rxd0_sel <= 2'b10;
     end else begin
       if (reg_we & rph_rxd0_sel_addressed) begin
-        rph_rxd0_sel <= reg_wdata[24+:2];
+        rph_rxd0_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -1668,8 +1236,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g16_ce2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 20 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1677,7 +1245,7 @@ module pinmux
       rph_g16_ce2_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g16_ce2_sel_addressed) begin
-        rph_g16_ce2_sel <= reg_wdata[0+:3];
+        rph_g16_ce2_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -1690,7 +1258,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][2],
+      spi_cs_i[1][2],
       gpio_ios_i[0][16]
     }),
     .sel_i(rph_g16_ce2_sel),
@@ -1705,7 +1273,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][2],
+      spi_cs_en_i[1][2],
       gpio_ios_en_i[0][16]
     }),
     .sel_i(rph_g16_ce2_sel),
@@ -1718,8 +1286,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g17_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 24 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1727,7 +1295,7 @@ module pinmux
       rph_g17_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g17_sel_addressed) begin
-        rph_g17_sel <= reg_wdata[8+:3];
+        rph_g17_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -1740,7 +1308,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][1],
+      spi_cs_i[1][1],
       gpio_ios_i[0][17]
     }),
     .sel_i(rph_g17_sel),
@@ -1755,7 +1323,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][1],
+      spi_cs_en_i[1][1],
       gpio_ios_en_i[0][17]
     }),
     .sel_i(rph_g17_sel),
@@ -1768,8 +1336,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g18_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 24 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1777,7 +1345,7 @@ module pinmux
       rph_g18_sel <= 4'b10;
     end else begin
       if (reg_we & rph_g18_sel_addressed) begin
-        rph_g18_sel <= reg_wdata[16+:4];
+        rph_g18_sel <= reg_wdata[8+:4];
       end
     end
   end
@@ -1790,7 +1358,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][0],
+      spi_cs_i[1][0],
       gpio_ios_i[0][18],
       pwm_out_i[0][2]
     }),
@@ -1806,7 +1374,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][0],
+      spi_cs_en_i[1][0],
       gpio_ios_en_i[0][18],
       pwm_out_en_i[0][2]
     }),
@@ -1820,8 +1388,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g19_cipo_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 24 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1829,7 +1397,7 @@ module pinmux
       rph_g19_cipo_sel <= 3'b10;
     end else begin
       if (reg_we & rph_g19_cipo_sel_addressed) begin
-        rph_g19_cipo_sel <= reg_wdata[24+:3];
+        rph_g19_cipo_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -1870,8 +1438,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g20_copi_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 24 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1879,7 +1447,7 @@ module pinmux
       rph_g20_copi_sel <= 4'b10;
     end else begin
       if (reg_we & rph_g20_copi_sel_addressed) begin
-        rph_g20_copi_sel <= reg_wdata[0+:4];
+        rph_g20_copi_sel <= reg_wdata[24+:4];
       end
     end
   end
@@ -1892,7 +1460,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[3],
+      spi_copi_i[1],
       gpio_ios_i[0][20],
       pwm_out_i[0][4]
     }),
@@ -1908,7 +1476,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[3],
+      spi_copi_en_i[1],
       gpio_ios_en_i[0][20],
       pwm_out_en_i[0][4]
     }),
@@ -1922,8 +1490,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g21_sclk_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 28 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1931,7 +1499,7 @@ module pinmux
       rph_g21_sclk_sel <= 4'b10;
     end else begin
       if (reg_we & rph_g21_sclk_sel_addressed) begin
-        rph_g21_sclk_sel <= reg_wdata[8+:4];
+        rph_g21_sclk_sel <= reg_wdata[0+:4];
       end
     end
   end
@@ -1944,7 +1512,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[3],
+      spi_sclk_i[1],
       gpio_ios_i[0][21],
       pwm_out_i[0][5]
     }),
@@ -1960,7 +1528,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[3],
+      spi_sclk_en_i[1],
       gpio_ios_en_i[0][21],
       pwm_out_en_i[0][5]
     }),
@@ -1974,8 +1542,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g22_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 28 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -1983,7 +1551,7 @@ module pinmux
       rph_g22_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g22_sel_addressed) begin
-        rph_g22_sel <= reg_wdata[16+:2];
+        rph_g22_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -2022,8 +1590,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g23_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 28 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2031,7 +1599,7 @@ module pinmux
       rph_g23_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g23_sel_addressed) begin
-        rph_g23_sel <= reg_wdata[24+:2];
+        rph_g23_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -2070,8 +1638,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g24_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 28 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2079,7 +1647,7 @@ module pinmux
       rph_g24_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g24_sel_addressed) begin
-        rph_g24_sel <= reg_wdata[0+:2];
+        rph_g24_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -2118,8 +1686,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g25_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2127,7 +1695,7 @@ module pinmux
       rph_g25_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g25_sel_addressed) begin
-        rph_g25_sel <= reg_wdata[8+:2];
+        rph_g25_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -2166,8 +1734,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g26_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2175,7 +1743,7 @@ module pinmux
       rph_g26_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g26_sel_addressed) begin
-        rph_g26_sel <= reg_wdata[16+:2];
+        rph_g26_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -2214,8 +1782,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign rph_g27_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2223,7 +1791,7 @@ module pinmux
       rph_g27_sel <= 2'b10;
     end else begin
       if (reg_we & rph_g27_sel_addressed) begin
-        rph_g27_sel <= reg_wdata[24+:2];
+        rph_g27_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -2262,8 +1830,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2271,7 +1839,7 @@ module pinmux
       ah_tmpio0_sel <= 2'b10;
     end else begin
       if (reg_we & ah_tmpio0_sel_addressed) begin
-        ah_tmpio0_sel <= reg_wdata[0+:2];
+        ah_tmpio0_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -2310,8 +1878,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2319,7 +1887,7 @@ module pinmux
       ah_tmpio1_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio1_sel_addressed) begin
-        ah_tmpio1_sel <= reg_wdata[8+:3];
+        ah_tmpio1_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -2360,8 +1928,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2369,7 +1937,7 @@ module pinmux
       ah_tmpio2_sel <= 2'b10;
     end else begin
       if (reg_we & ah_tmpio2_sel_addressed) begin
-        ah_tmpio2_sel <= reg_wdata[16+:2];
+        ah_tmpio2_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -2408,8 +1976,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2417,7 +1985,7 @@ module pinmux
       ah_tmpio3_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio3_sel_addressed) begin
-        ah_tmpio3_sel <= reg_wdata[24+:3];
+        ah_tmpio3_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -2458,8 +2026,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2467,7 +2035,7 @@ module pinmux
       ah_tmpio4_sel <= 2'b10;
     end else begin
       if (reg_we & ah_tmpio4_sel_addressed) begin
-        ah_tmpio4_sel <= reg_wdata[0+:2];
+        ah_tmpio4_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -2506,8 +2074,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2515,7 +2083,7 @@ module pinmux
       ah_tmpio5_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio5_sel_addressed) begin
-        ah_tmpio5_sel <= reg_wdata[8+:3];
+        ah_tmpio5_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -2556,8 +2124,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2565,7 +2133,7 @@ module pinmux
       ah_tmpio6_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio6_sel_addressed) begin
-        ah_tmpio6_sel <= reg_wdata[16+:3];
+        ah_tmpio6_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -2606,8 +2174,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2615,7 +2183,7 @@ module pinmux
       ah_tmpio7_sel <= 2'b10;
     end else begin
       if (reg_we & ah_tmpio7_sel_addressed) begin
-        ah_tmpio7_sel <= reg_wdata[24+:2];
+        ah_tmpio7_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -2654,8 +2222,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio8_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2663,7 +2231,7 @@ module pinmux
       ah_tmpio8_sel <= 2'b10;
     end else begin
       if (reg_we & ah_tmpio8_sel_addressed) begin
-        ah_tmpio8_sel <= reg_wdata[0+:2];
+        ah_tmpio8_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -2702,8 +2270,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio9_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2711,7 +2279,7 @@ module pinmux
       ah_tmpio9_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio9_sel_addressed) begin
-        ah_tmpio9_sel <= reg_wdata[8+:3];
+        ah_tmpio9_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -2752,8 +2320,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio10_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2761,7 +2329,7 @@ module pinmux
       ah_tmpio10_sel <= 4'b10;
     end else begin
       if (reg_we & ah_tmpio10_sel_addressed) begin
-        ah_tmpio10_sel <= reg_wdata[16+:4];
+        ah_tmpio10_sel <= reg_wdata[8+:4];
       end
     end
   end
@@ -2774,7 +2342,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[2][3],
+      spi_cs_i[0][3],
       gpio_ios_i[1][10],
       pwm_out_i[0][4]
     }),
@@ -2790,7 +2358,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[2][3],
+      spi_cs_en_i[0][3],
       gpio_ios_en_i[1][10],
       pwm_out_en_i[0][4]
     }),
@@ -2804,8 +2372,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio11_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2813,7 +2381,7 @@ module pinmux
       ah_tmpio11_sel <= 4'b10;
     end else begin
       if (reg_we & ah_tmpio11_sel_addressed) begin
-        ah_tmpio11_sel <= reg_wdata[24+:4];
+        ah_tmpio11_sel <= reg_wdata[16+:4];
       end
     end
   end
@@ -2826,7 +2394,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[2],
+      spi_copi_i[0],
       gpio_ios_i[1][11],
       pwm_out_i[0][5]
     }),
@@ -2842,7 +2410,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[2],
+      spi_copi_en_i[0],
       gpio_ios_en_i[1][11],
       pwm_out_en_i[0][5]
     }),
@@ -2856,8 +2424,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio12_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2865,7 +2433,7 @@ module pinmux
       ah_tmpio12_sel <= 2'b10;
     end else begin
       if (reg_we & ah_tmpio12_sel_addressed) begin
-        ah_tmpio12_sel <= reg_wdata[0+:2];
+        ah_tmpio12_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -2904,8 +2472,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign ah_tmpio13_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2913,7 +2481,7 @@ module pinmux
       ah_tmpio13_sel <= 3'b10;
     end else begin
       if (reg_we & ah_tmpio13_sel_addressed) begin
-        ah_tmpio13_sel <= reg_wdata[8+:3];
+        ah_tmpio13_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -2926,7 +2494,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[2],
+      spi_sclk_i[0],
       gpio_ios_i[1][13]
     }),
     .sel_i(ah_tmpio13_sel),
@@ -2941,7 +2509,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[2],
+      spi_sclk_en_i[0],
       gpio_ios_en_i[1][13]
     }),
     .sel_i(ah_tmpio13_sel),
@@ -2954,8 +2522,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -2963,7 +2531,7 @@ module pinmux
       mb1_sel <= 2'b10;
     end else begin
       if (reg_we & mb1_sel_addressed) begin
-        mb1_sel <= reg_wdata[16+:2];
+        mb1_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -2976,7 +2544,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][3]
+      spi_cs_i[1][3]
     }),
     .sel_i(mb1_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB1])
@@ -2990,7 +2558,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[3][3]
+      spi_cs_en_i[1][3]
     }),
     .sel_i(mb1_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB1])
@@ -3002,8 +2570,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3011,7 +2579,7 @@ module pinmux
       mb2_sel <= 2'b10;
     end else begin
       if (reg_we & mb2_sel_addressed) begin
-        mb2_sel <= reg_wdata[24+:2];
+        mb2_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -3024,7 +2592,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[3]
+      spi_sclk_i[1]
     }),
     .sel_i(mb2_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB2])
@@ -3038,7 +2606,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_sclk_en_i[3]
+      spi_sclk_en_i[1]
     }),
     .sel_i(mb2_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB2])
@@ -3050,8 +2618,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3059,7 +2627,7 @@ module pinmux
       mb4_sel <= 2'b10;
     end else begin
       if (reg_we & mb4_sel_addressed) begin
-        mb4_sel <= reg_wdata[0+:2];
+        mb4_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -3072,7 +2640,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[3]
+      spi_copi_i[1]
     }),
     .sel_i(mb4_sel),
     .out_o(out_to_pins_o[OUT_PIN_MB4])
@@ -3086,7 +2654,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_copi_en_i[3]
+      spi_copi_en_i[1]
     }),
     .sel_i(mb4_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_MB4])
@@ -3098,8 +2666,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3107,7 +2675,7 @@ module pinmux
       mb5_sel <= 2'b10;
     end else begin
       if (reg_we & mb5_sel_addressed) begin
-        mb5_sel <= reg_wdata[8+:2];
+        mb5_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -3146,8 +2714,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3155,7 +2723,7 @@ module pinmux
       mb6_sel <= 2'b10;
     end else begin
       if (reg_we & mb6_sel_addressed) begin
-        mb6_sel <= reg_wdata[16+:2];
+        mb6_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -3194,8 +2762,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3203,7 +2771,7 @@ module pinmux
       mb7_sel <= 2'b10;
     end else begin
       if (reg_we & mb7_sel_addressed) begin
-        mb7_sel <= reg_wdata[24+:2];
+        mb7_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -3242,8 +2810,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign mb10_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3251,7 +2819,7 @@ module pinmux
       mb10_sel <= 2'b10;
     end else begin
       if (reg_we & mb10_sel_addressed) begin
-        mb10_sel <= reg_wdata[0+:2];
+        mb10_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -3290,8 +2858,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3299,7 +2867,7 @@ module pinmux
       pmod0_1_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_1_sel_addressed) begin
-        pmod0_1_sel <= reg_wdata[8+:3];
+        pmod0_1_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -3313,7 +2881,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][0],
-      spi_cs_i[2][0]
+      spi_cs_i[0][0]
     }),
     .sel_i(pmod0_1_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_1])
@@ -3328,7 +2896,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][0],
-      spi_cs_en_i[2][0]
+      spi_cs_en_i[0][0]
     }),
     .sel_i(pmod0_1_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_1])
@@ -3340,8 +2908,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3349,7 +2917,7 @@ module pinmux
       pmod0_2_sel <= 5'b10;
     end else begin
       if (reg_we & pmod0_2_sel_addressed) begin
-        pmod0_2_sel <= reg_wdata[16+:5];
+        pmod0_2_sel <= reg_wdata[8+:5];
       end
     end
   end
@@ -3363,7 +2931,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][1],
-      spi_copi_i[2],
+      spi_copi_i[0],
       pwm_out_i[0][1],
       uart_tx_i[1]
     }),
@@ -3380,7 +2948,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][1],
-      spi_copi_en_i[2],
+      spi_copi_en_i[0],
       pwm_out_en_i[0][1],
       uart_tx_en_i[1]
     }),
@@ -3394,8 +2962,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3403,7 +2971,7 @@ module pinmux
       pmod0_3_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_3_sel_addressed) begin
-        pmod0_3_sel <= reg_wdata[24+:3];
+        pmod0_3_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -3444,8 +3012,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3453,7 +3021,7 @@ module pinmux
       pmod0_4_sel <= 4'b10;
     end else begin
       if (reg_we & pmod0_4_sel_addressed) begin
-        pmod0_4_sel <= reg_wdata[0+:4];
+        pmod0_4_sel <= reg_wdata[24+:4];
       end
     end
   end
@@ -3467,7 +3035,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][3],
-      spi_sclk_i[2],
+      spi_sclk_i[0],
       i2c_sda_i[0]
     }),
     .sel_i(pmod0_4_sel),
@@ -3483,7 +3051,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][3],
-      spi_sclk_en_i[2],
+      spi_sclk_en_i[0],
       i2c_sda_en_i[0]
     }),
     .sel_i(pmod0_4_sel),
@@ -3496,8 +3064,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3505,7 +3073,7 @@ module pinmux
       pmod0_5_sel <= 2'b10;
     end else begin
       if (reg_we & pmod0_5_sel_addressed) begin
-        pmod0_5_sel <= reg_wdata[8+:2];
+        pmod0_5_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -3544,8 +3112,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3553,7 +3121,7 @@ module pinmux
       pmod0_6_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_6_sel_addressed) begin
-        pmod0_6_sel <= reg_wdata[16+:3];
+        pmod0_6_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -3594,8 +3162,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3603,7 +3171,7 @@ module pinmux
       pmod0_7_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_7_sel_addressed) begin
-        pmod0_7_sel <= reg_wdata[24+:3];
+        pmod0_7_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -3617,7 +3185,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][6],
-      spi_cs_i[2][1]
+      spi_cs_i[0][1]
     }),
     .sel_i(pmod0_7_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_7])
@@ -3632,7 +3200,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][6],
-      spi_cs_en_i[2][1]
+      spi_cs_en_i[0][1]
     }),
     .sel_i(pmod0_7_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_7])
@@ -3644,8 +3212,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod0_8_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3653,7 +3221,7 @@ module pinmux
       pmod0_8_sel <= 3'b10;
     end else begin
       if (reg_we & pmod0_8_sel_addressed) begin
-        pmod0_8_sel <= reg_wdata[0+:3];
+        pmod0_8_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -3667,7 +3235,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[2][7],
-      spi_cs_i[2][2]
+      spi_cs_i[0][2]
     }),
     .sel_i(pmod0_8_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD0_8])
@@ -3682,7 +3250,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[2][7],
-      spi_cs_en_i[2][2]
+      spi_cs_en_i[0][2]
     }),
     .sel_i(pmod0_8_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD0_8])
@@ -3694,8 +3262,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3703,7 +3271,7 @@ module pinmux
       pmod1_1_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_1_sel_addressed) begin
-        pmod1_1_sel <= reg_wdata[8+:3];
+        pmod1_1_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -3717,7 +3285,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][0],
-      spi_cs_i[3][0]
+      spi_cs_i[1][0]
     }),
     .sel_i(pmod1_1_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_1])
@@ -3732,7 +3300,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][0],
-      spi_cs_en_i[3][0]
+      spi_cs_en_i[1][0]
     }),
     .sel_i(pmod1_1_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_1])
@@ -3744,8 +3312,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3753,7 +3321,7 @@ module pinmux
       pmod1_2_sel <= 5'b10;
     end else begin
       if (reg_we & pmod1_2_sel_addressed) begin
-        pmod1_2_sel <= reg_wdata[16+:5];
+        pmod1_2_sel <= reg_wdata[8+:5];
       end
     end
   end
@@ -3767,7 +3335,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][1],
-      spi_copi_i[3],
+      spi_copi_i[1],
       pwm_out_i[0][3],
       uart_tx_i[2]
     }),
@@ -3784,7 +3352,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][1],
-      spi_copi_en_i[3],
+      spi_copi_en_i[1],
       pwm_out_en_i[0][3],
       uart_tx_en_i[2]
     }),
@@ -3798,8 +3366,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3807,7 +3375,7 @@ module pinmux
       pmod1_3_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_3_sel_addressed) begin
-        pmod1_3_sel <= reg_wdata[24+:3];
+        pmod1_3_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -3848,8 +3416,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3857,7 +3425,7 @@ module pinmux
       pmod1_4_sel <= 4'b10;
     end else begin
       if (reg_we & pmod1_4_sel_addressed) begin
-        pmod1_4_sel <= reg_wdata[0+:4];
+        pmod1_4_sel <= reg_wdata[24+:4];
       end
     end
   end
@@ -3871,7 +3439,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][3],
-      spi_sclk_i[3],
+      spi_sclk_i[1],
       i2c_sda_i[1]
     }),
     .sel_i(pmod1_4_sel),
@@ -3887,7 +3455,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][3],
-      spi_sclk_en_i[3],
+      spi_sclk_en_i[1],
       i2c_sda_en_i[1]
     }),
     .sel_i(pmod1_4_sel),
@@ -3900,8 +3468,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 68 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3909,7 +3477,7 @@ module pinmux
       pmod1_5_sel <= 2'b10;
     end else begin
       if (reg_we & pmod1_5_sel_addressed) begin
-        pmod1_5_sel <= reg_wdata[8+:2];
+        pmod1_5_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -3948,8 +3516,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 68 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -3957,7 +3525,7 @@ module pinmux
       pmod1_6_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_6_sel_addressed) begin
-        pmod1_6_sel <= reg_wdata[16+:3];
+        pmod1_6_sel <= reg_wdata[8+:3];
       end
     end
   end
@@ -3998,8 +3566,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 68 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -4007,7 +3575,7 @@ module pinmux
       pmod1_7_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_7_sel_addressed) begin
-        pmod1_7_sel <= reg_wdata[24+:3];
+        pmod1_7_sel <= reg_wdata[16+:3];
       end
     end
   end
@@ -4021,7 +3589,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][6],
-      spi_cs_i[3][1]
+      spi_cs_i[1][1]
     }),
     .sel_i(pmod1_7_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_7])
@@ -4036,7 +3604,7 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][6],
-      spi_cs_en_i[3][1]
+      spi_cs_en_i[1][1]
     }),
     .sel_i(pmod1_7_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_7])
@@ -4048,8 +3616,8 @@ module pinmux
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
   assign pmod1_8_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 68 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -4057,7 +3625,7 @@ module pinmux
       pmod1_8_sel <= 3'b10;
     end else begin
       if (reg_we & pmod1_8_sel_addressed) begin
-        pmod1_8_sel <= reg_wdata[0+:3];
+        pmod1_8_sel <= reg_wdata[24+:3];
       end
     end
   end
@@ -4071,7 +3639,7 @@ module pinmux
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
       gpio_ios_i[3][7],
-      spi_cs_i[3][2]
+      spi_cs_i[1][2]
     }),
     .sel_i(pmod1_8_sel),
     .out_o(inout_to_pins_o[INOUT_PIN_PMOD1_8])
@@ -4086,156 +3654,12 @@ module pinmux
     .in_i({
       1'b0,
       gpio_ios_en_i[3][7],
-      spi_cs_en_i[3][2]
+      spi_cs_en_i[1][2]
     }),
     .sel_i(pmod1_8_sel),
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_8])
   );
 
-  logic [1:0] microsd_clk_sel;
-  logic microsd_clk_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign microsd_clk_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      microsd_clk_sel <= 2'b10;
-    end else begin
-      if (reg_we & microsd_clk_sel_addressed) begin
-        microsd_clk_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) microsd_clk_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_sclk_i[3]
-    }),
-    .sel_i(microsd_clk_sel),
-    .out_o(out_to_pins_o[OUT_PIN_MICROSD_CLK])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) microsd_clk_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_sclk_en_i[3]
-    }),
-    .sel_i(microsd_clk_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_MICROSD_CLK])
-  );
-
-  logic [1:0] microsd_cmd_sel;
-  logic microsd_cmd_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign microsd_cmd_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      microsd_cmd_sel <= 2'b10;
-    end else begin
-      if (reg_we & microsd_cmd_sel_addressed) begin
-        microsd_cmd_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) microsd_cmd_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_copi_i[3]
-    }),
-    .sel_i(microsd_cmd_sel),
-    .out_o(out_to_pins_o[OUT_PIN_MICROSD_CMD])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) microsd_cmd_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_copi_en_i[3]
-    }),
-    .sel_i(microsd_cmd_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_MICROSD_CMD])
-  );
-
-  logic [1:0] microsd_dat3_sel;
-  logic microsd_dat3_sel_addressed;
-
-  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
-  assign microsd_dat3_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b0 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      microsd_dat3_sel <= 2'b10;
-    end else begin
-      if (reg_we & microsd_dat3_sel_addressed) begin
-        microsd_dat3_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) microsd_dat3_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[3][3]
-    }),
-    .sel_i(microsd_dat3_sel),
-    .out_o(out_to_pins_o[OUT_PIN_MICROSD_DAT3])
-  );
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) microsd_dat3_enable_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      spi_cs_en_i[3][3]
-    }),
-    .sel_i(microsd_dat3_sel),
-    .out_o(out_to_pins_en_o[OUT_PIN_MICROSD_DAT3])
-  );
-
   // Inputs - Physical pin inputs are muxed to particular block IO
 
   logic [1:0] gpio_ios_0_0_sel;
@@ -8697,7 +8121,7 @@ module pinmux
     .out_o(uart_rx_o[2])
   );
 
-  logic [1:0] spi_cipo_0_sel;
+  logic [3:0] spi_cipo_0_sel;
   logic spi_cipo_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
@@ -8709,29 +8133,31 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_0_sel <= 2'b10;
+      spi_cipo_0_sel <= 4'b10;
     end else begin
       if (reg_we & spi_cipo_0_sel_addressed) begin
-        spi_cipo_0_sel <= reg_wdata[24+:2];
+        spi_cipo_0_sel <= reg_wdata[24+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(4)
   ) spi_cipo_0_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      in_from_pins_i[IN_PIN_APPSPI_D1]
+      inout_from_pins_i[INOUT_PIN_RPH_G9_CIPO],
+      inout_from_pins_i[INOUT_PIN_AH_TMPIO12],
+      inout_from_pins_i[INOUT_PIN_PMOD0_3]
     }),
     .sel_i(spi_cipo_0_sel),
     .out_o(spi_cipo_o[0])
   );
 
-  logic [1:0] spi_cipo_1_sel;
+  logic [3:0] spi_cipo_1_sel;
   logic spi_cipo_1_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
@@ -8743,134 +8169,28 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_1_sel <= 2'b10;
+      spi_cipo_1_sel <= 4'b10;
     end else begin
       if (reg_we & spi_cipo_1_sel_addressed) begin
-        spi_cipo_1_sel <= reg_wdata[0+:2];
+        spi_cipo_1_sel <= reg_wdata[0+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(4)
   ) spi_cipo_1_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(spi_cipo_1_sel),
-    .out_o(spi_cipo_o[1])
-  );
-
-  logic [4:0] spi_cipo_2_sel;
-  logic spi_cipo_2_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_cipo_2_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_2_sel <= 5'b10;
-    end else begin
-      if (reg_we & spi_cipo_2_sel_addressed) begin
-        spi_cipo_2_sel <= reg_wdata[8+:5];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(5)
-  ) spi_cipo_2_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      in_from_pins_i[IN_PIN_ETHMAC_CIPO],
-      inout_from_pins_i[INOUT_PIN_RPH_G9_CIPO],
-      inout_from_pins_i[INOUT_PIN_AH_TMPIO12],
-      inout_from_pins_i[INOUT_PIN_PMOD0_3]
-    }),
-    .sel_i(spi_cipo_2_sel),
-    .out_o(spi_cipo_o[2])
-  );
-
-  logic [4:0] spi_cipo_3_sel;
-  logic spi_cipo_3_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_cipo_3_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_3_sel <= 5'b10;
-    end else begin
-      if (reg_we & spi_cipo_3_sel_addressed) begin
-        spi_cipo_3_sel <= reg_wdata[16+:5];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(5)
-  ) spi_cipo_3_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
       inout_from_pins_i[INOUT_PIN_RPH_G19_CIPO],
       in_from_pins_i[IN_PIN_MB3],
-      inout_from_pins_i[INOUT_PIN_PMOD1_3],
-      in_from_pins_i[IN_PIN_MICROSD_DAT0]
-    }),
-    .sel_i(spi_cipo_3_sel),
-    .out_o(spi_cipo_o[3])
-  );
-
-  logic [1:0] spi_cipo_4_sel;
-  logic spi_cipo_4_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign spi_cipo_4_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      spi_cipo_4_sel <= 2'b10;
-    end else begin
-      if (reg_we & spi_cipo_4_sel_addressed) begin
-        spi_cipo_4_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) spi_cipo_4_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_3]
     }),
-    .sel_i(spi_cipo_4_sel),
-    .out_o(spi_cipo_o[4])
+    .sel_i(spi_cipo_1_sel),
+    .out_o(spi_cipo_o[1])
   );
 
   // Combining inputs for combinable inouts
diff --git a/rtl/system/sonata_pkg.sv b/rtl/system/sonata_pkg.sv
index be9c5a1cd..55e95ecf7 100644
--- a/rtl/system/sonata_pkg.sv
+++ b/rtl/system/sonata_pkg.sv
@@ -11,7 +11,7 @@ package sonata_pkg;
   localparam int unsigned PWM_NUM = 1;
   localparam int unsigned UART_NUM = 3;
   localparam int unsigned I2C_NUM = 2;
-  localparam int unsigned SPI_NUM = 5;
+  localparam int unsigned SPI_NUM = 2;
 
   // Width of block IO arrays
   localparam int unsigned GPIO_IOS_WIDTH = 32;
@@ -19,39 +19,24 @@ package sonata_pkg;
   localparam int unsigned SPI_CS_WIDTH = 4;
 
   // Number of input, output, and inout pins
-  localparam int unsigned IN_PIN_NUM = 8;
-  localparam int unsigned OUT_PIN_NUM = 20;
+  localparam int unsigned IN_PIN_NUM = 5;
+  localparam int unsigned OUT_PIN_NUM = 8;
   localparam int unsigned INOUT_PIN_NUM = 64;
 
   localparam int unsigned IN_PIN_SER0_RX = 0;
   localparam int unsigned IN_PIN_SER1_RX = 1;
   localparam int unsigned IN_PIN_RS232_RX = 2;
-  localparam int unsigned IN_PIN_APPSPI_D1 = 3;
-  localparam int unsigned IN_PIN_ETHMAC_CIPO = 4;
-  localparam int unsigned IN_PIN_MB3 = 5;
-  localparam int unsigned IN_PIN_MB8 = 6;
-  localparam int unsigned IN_PIN_MICROSD_DAT0 = 7;
+  localparam int unsigned IN_PIN_MB3 = 3;
+  localparam int unsigned IN_PIN_MB8 = 4;
 
   localparam int unsigned OUT_PIN_SER0_TX = 0;
   localparam int unsigned OUT_PIN_SER1_TX = 1;
   localparam int unsigned OUT_PIN_RS232_TX = 2;
-  localparam int unsigned OUT_PIN_APPSPI_D0 = 3;
-  localparam int unsigned OUT_PIN_APPSPI_CLK = 4;
-  localparam int unsigned OUT_PIN_APPSPI_CS = 5;
-  localparam int unsigned OUT_PIN_LCD_COPI = 6;
-  localparam int unsigned OUT_PIN_LCD_CLK = 7;
-  localparam int unsigned OUT_PIN_LCD_CS = 8;
-  localparam int unsigned OUT_PIN_ETHMAC_COPI = 9;
-  localparam int unsigned OUT_PIN_ETHMAC_SCLK = 10;
-  localparam int unsigned OUT_PIN_ETHMAC_CS = 11;
-  localparam int unsigned OUT_PIN_MB1 = 12;
-  localparam int unsigned OUT_PIN_MB2 = 13;
-  localparam int unsigned OUT_PIN_MB4 = 14;
-  localparam int unsigned OUT_PIN_MB7 = 15;
-  localparam int unsigned OUT_PIN_MB10 = 16;
-  localparam int unsigned OUT_PIN_MICROSD_CLK = 17;
-  localparam int unsigned OUT_PIN_MICROSD_CMD = 18;
-  localparam int unsigned OUT_PIN_MICROSD_DAT3 = 19;
+  localparam int unsigned OUT_PIN_MB1 = 3;
+  localparam int unsigned OUT_PIN_MB2 = 4;
+  localparam int unsigned OUT_PIN_MB4 = 5;
+  localparam int unsigned OUT_PIN_MB7 = 6;
+  localparam int unsigned OUT_PIN_MB10 = 7;
 
   localparam int unsigned INOUT_PIN_SCL0 = 0;
   localparam int unsigned INOUT_PIN_SDA0 = 1;
diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
index 5f5d2135c..d14d53a32 100644
--- a/rtl/system/sonata_system.sv
+++ b/rtl/system/sonata_system.sv
@@ -40,6 +40,22 @@ module sonata_system
   input  wire  [ArdAniWidth-1:0]   ard_an_p_i,
   input  wire  [ArdAniWidth-1:0]   ard_an_n_i,
 
+  // Non-pinmuxed spi devices
+  output logic                     lcd_copi_o,
+  output logic                     lcd_sclk_o,
+  output logic                     lcd_cs_o,
+  output logic                     lcd_dc_o,
+  output logic                     lcd_rst_o,
+  output logic                     lcd_backlight_o,
+
+  output logic                     spi_board_copi_o,
+  input  logic                     spi_board_cipo_i,
+  output logic                     spi_board_sclk_o,
+  output logic                     spi_board_flash_cs_o,
+  output logic                     spi_board_eth_cs_o,
+  output logic                     spi_board_eth_rst_o,
+  output logic                     spi_board_microsd_cs_o,
+
   input  logic                     spi_eth_irq_ni, // Interrupt from Ethernet MAC
 
   // User JTAG
@@ -141,7 +157,7 @@ module sonata_system
   logic external_irq;
 
   logic [I2cIrqs-1:0]    i2c_interrupts [I2C_NUM];
-  logic [SpiIrqs-1:0]    spi_interrupts [SPI_NUM];
+  logic [SpiIrqs-1:0]    spi_interrupts [SPI_NUM + 2];
   logic [UartIrqs-1:0]   uart_interrupts[UART_NUM];
   logic [UsbdevIrqs-1:0] usbdev_interrupts;
 
@@ -293,6 +309,10 @@ module sonata_system
   tlul_pkg::tl_d2h_t tl_uart_d2h[UART_NUM];
   tlul_pkg::tl_h2d_t tl_timer_h2d;
   tlul_pkg::tl_d2h_t tl_timer_d2h;
+  tlul_pkg::tl_h2d_t tl_spi_board_h2d;
+  tlul_pkg::tl_d2h_t tl_spi_board_d2h;
+  tlul_pkg::tl_h2d_t tl_spi_lcd_h2d;
+  tlul_pkg::tl_d2h_t tl_spi_lcd_d2h;
   tlul_pkg::tl_h2d_t tl_system_info_h2d;
   tlul_pkg::tl_d2h_t tl_system_info_d2h;
   tlul_pkg::tl_h2d_t tl_rgbled_ctrl_h2d;
@@ -351,6 +371,10 @@ module sonata_system
     .tl_xadc_i        (tl_xadc_d2h),
     .tl_timer_o       (tl_timer_h2d),
     .tl_timer_i       (tl_timer_d2h),
+    .tl_spi_board_o   (tl_spi_board_h2d),
+    .tl_spi_board_i   (tl_spi_board_d2h),
+    .tl_spi_lcd_o     (tl_spi_lcd_h2d),
+    .tl_spi_lcd_i     (tl_spi_lcd_d2h),
     .tl_uart_o        (tl_uart_h2d),
     .tl_uart_i        (tl_uart_d2h),
     .tl_i2c_o         (tl_i2c_h2d),
@@ -909,6 +933,9 @@ module sonata_system
 
   // Pulse width modulator.
   logic [PWM_OUT_WIDTH-1:0] pwm_modulated;
+
+  assign lcd_backlight_o = pwm_modulated[PWM_OUT_WIDTH-1];
+
   pwm_wrapper #(
     .PwmWidth   ( PWM_OUT_WIDTH ),
     .PwmCtrSize ( PwmCtrSize )
@@ -1032,17 +1059,71 @@ module sonata_system
     .intr_av_setup_empty_o        (usbdev_interrupts[17])
   );
 
-  // SPI controllers.
+
+  // Dedicated Spi Controllers
+  // - Flash memory, Ethernet & microSD
   // - LCD screen
-  // - Flash memory
-  // - Ethernet
-  // - 2x Raspberry Pi HAT
-  // - Arduino Shield
-  // - mikroBUS Click
+  spi #(
+    .CSWidth(4)
+  ) u_spi_board (
+    .clk_i               (clk_sys_i),
+    .rst_ni              (rst_sys_ni),
+
+    // TileLink interface.
+    .tl_i                (tl_spi_board_h2d),
+    .tl_o                (tl_spi_board_d2h),
+
+    // Interrupts currently disconnected.
+    .intr_rx_full_o      (spi_interrupts[0][0]),
+    .intr_rx_watermark_o (spi_interrupts[0][1]),
+    .intr_tx_empty_o     (spi_interrupts[0][2]),
+    .intr_tx_watermark_o (spi_interrupts[0][3]),
+    .intr_complete_o     (spi_interrupts[0][4]),
+
+    // SPI signals.
+    .spi_copi_o          (spi_board_copi_o),
+    .spi_cipo_i          (spi_board_cipo_i),
+    .spi_cs_o            ({
+      spi_board_microsd_cs_o,
+      spi_board_eth_rst_o,
+      spi_board_eth_cs_o,
+      spi_board_flash_cs_o
+    }),
+    .spi_clk_o           (spi_board_sclk_o)
+  );
+
+  spi #(
+    .CSWidth(3)
+  ) u_spi_lcd (
+    .clk_i               (clk_sys_i),
+    .rst_ni              (rst_sys_ni),
+
+    // TileLink interface.
+    .tl_i                (tl_spi_lcd_h2d),
+    .tl_o                (tl_spi_lcd_d2h),
+
+    // Interrupts currently disconnected.
+    .intr_rx_full_o      (spi_interrupts[1][0]),
+    .intr_rx_watermark_o (spi_interrupts[1][1]),
+    .intr_tx_empty_o     (spi_interrupts[1][2]),
+    .intr_tx_watermark_o (spi_interrupts[1][3]),
+    .intr_complete_o     (spi_interrupts[1][4]),
+
+    // SPI signals.
+    .spi_copi_o          (lcd_copi_o),
+    .spi_cipo_i          (),
+    .spi_cs_o            ({lcd_rst_o, lcd_dc_o, lcd_cs_o}),
+    .spi_clk_o           (lcd_sclk_o)
+  );
+
+
+  // Pinmuxed SPI controllers.
+  // - 2x Pinmuxed
   logic                    spi_sclk[SPI_NUM];
   logic                    spi_copi[SPI_NUM];
   logic                    spi_cipo[SPI_NUM];
   logic [SPI_CS_WIDTH-1:0] spi_cs[SPI_NUM];
+
   for (genvar i = 0; i < SPI_NUM; i++) begin : gen_spi_hosts
     spi #(
       .CSWidth(SPI_CS_WIDTH)
@@ -1055,11 +1136,11 @@ module sonata_system
       .tl_o                (tl_spi_d2h[i]),
 
       // Interrupts currently disconnected.
-      .intr_rx_full_o      (spi_interrupts[i][0]),
-      .intr_rx_watermark_o (spi_interrupts[i][1]),
-      .intr_tx_empty_o     (spi_interrupts[i][2]),
-      .intr_tx_watermark_o (spi_interrupts[i][3]),
-      .intr_complete_o     (spi_interrupts[i][4]),
+      .intr_rx_full_o      (spi_interrupts[i + 2][0]),
+      .intr_rx_watermark_o (spi_interrupts[i + 2][1]),
+      .intr_tx_empty_o     (spi_interrupts[i + 2][2]),
+      .intr_tx_watermark_o (spi_interrupts[i + 2][3]),
+      .intr_complete_o     (spi_interrupts[i + 2][4]),
 
       // SPI signals.
       .spi_copi_o          (spi_copi [i]),
diff --git a/rtl/templates/sonata_xbar_main.sv.tpl b/rtl/templates/sonata_xbar_main.sv.tpl
index 4a5262f30..a26372a2b 100644
--- a/rtl/templates/sonata_xbar_main.sv.tpl
+++ b/rtl/templates/sonata_xbar_main.sv.tpl
@@ -41,6 +41,10 @@ module sonata_xbar_main
   input  tlul_pkg::tl_d2h_t tl_xadc_i,
   output tlul_pkg::tl_h2d_t tl_timer_o,
   input  tlul_pkg::tl_d2h_t tl_timer_i,
+  output tlul_pkg::tl_h2d_t tl_spi_board_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_board_i,
+  output tlul_pkg::tl_h2d_t tl_spi_lcd_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_lcd_i,
   % for block in config.blocks:
   % if not block.name == "gpio":
   output tlul_pkg::tl_h2d_t tl_${block.name}_o[${block.name.upper()}_NUM],
@@ -87,6 +91,10 @@ module sonata_xbar_main
     .tl_xadc_i        (tl_xadc_i),
     .tl_timer_o       (tl_timer_o),
     .tl_timer_i       (tl_timer_i),
+    .tl_spi_board_i   (tl_spi_board_i),
+    .tl_spi_board_o   (tl_spi_board_o),
+    .tl_spi_lcd_i     (tl_spi_lcd_i),
+    .tl_spi_lcd_o     (tl_spi_lcd_o),
     % for block in config.blocks:
     % if not block.name == "gpio":
     % for i in range(block.instances):
diff --git a/sw/cheri/common/platform-pinmux.hh b/sw/cheri/common/platform-pinmux.hh
index f99ba0234..d3d128083 100644
--- a/sw/cheri/common/platform-pinmux.hh
+++ b/sw/cheri/common/platform-pinmux.hh
@@ -58,83 +58,71 @@ class SonataPinmux : private utils::NoCopyNoMove {
     sda0         = 0x004,
     scl1         = 0x005,
     sda1         = 0x006,
-    appspi_d0    = 0x007,
-    appspi_clk   = 0x008,
-    appspi_cs    = 0x009,
-    lcd_copi     = 0x00a,
-    lcd_clk      = 0x00b,
-    lcd_cs       = 0x00c,
-    ethmac_copi  = 0x00d,
-    ethmac_sclk  = 0x00e,
-    ethmac_cs    = 0x00f,
-    rph_g0       = 0x010,
-    rph_g1       = 0x011,
-    rph_g2_sda   = 0x012,
-    rph_g3_scl   = 0x013,
-    rph_g4       = 0x014,
-    rph_g5       = 0x015,
-    rph_g6       = 0x016,
-    rph_g7_ce1   = 0x017,
-    rph_g8_ce0   = 0x018,
-    rph_g9_cipo  = 0x019,
-    rph_g10_copi = 0x01a,
-    rph_g11_sclk = 0x01b,
-    rph_g12      = 0x01c,
-    rph_g13      = 0x01d,
-    rph_txd0     = 0x01e,
-    rph_rxd0     = 0x01f,
-    rph_g16_ce2  = 0x020,
-    rph_g17      = 0x021,
-    rph_g18      = 0x022,
-    rph_g19_cipo = 0x023,
-    rph_g20_copi = 0x024,
-    rph_g21_sclk = 0x025,
-    rph_g22      = 0x026,
-    rph_g23      = 0x027,
-    rph_g24      = 0x028,
-    rph_g25      = 0x029,
-    rph_g26      = 0x02a,
-    rph_g27      = 0x02b,
-    ah_tmpio0    = 0x02c,
-    ah_tmpio1    = 0x02d,
-    ah_tmpio2    = 0x02e,
-    ah_tmpio3    = 0x02f,
-    ah_tmpio4    = 0x030,
-    ah_tmpio5    = 0x031,
-    ah_tmpio6    = 0x032,
-    ah_tmpio7    = 0x033,
-    ah_tmpio8    = 0x034,
-    ah_tmpio9    = 0x035,
-    ah_tmpio10   = 0x036,
-    ah_tmpio11   = 0x037,
-    ah_tmpio12   = 0x038,
-    ah_tmpio13   = 0x039,
-    mb1          = 0x03a,
-    mb2          = 0x03b,
-    mb4          = 0x03c,
-    mb5          = 0x03d,
-    mb6          = 0x03e,
-    mb7          = 0x03f,
-    mb10         = 0x040,
-    pmod0_1      = 0x041,
-    pmod0_2      = 0x042,
-    pmod0_3      = 0x043,
-    pmod0_4      = 0x044,
-    pmod0_5      = 0x045,
-    pmod0_6      = 0x046,
-    pmod0_7      = 0x047,
-    pmod0_8      = 0x048,
-    pmod1_1      = 0x049,
-    pmod1_2      = 0x04a,
-    pmod1_3      = 0x04b,
-    pmod1_4      = 0x04c,
-    pmod1_5      = 0x04d,
-    pmod1_6      = 0x04e,
-    pmod1_7      = 0x04f,
-    pmod1_8      = 0x050,
-    microsd_clk  = 0x051,
-    microsd_cmd  = 0x052,
-    microsd_dat3 = 0x053,
+    rph_g0       = 0x007,
+    rph_g1       = 0x008,
+    rph_g2_sda   = 0x009,
+    rph_g3_scl   = 0x00a,
+    rph_g4       = 0x00b,
+    rph_g5       = 0x00c,
+    rph_g6       = 0x00d,
+    rph_g7_ce1   = 0x00e,
+    rph_g8_ce0   = 0x00f,
+    rph_g9_cipo  = 0x010,
+    rph_g10_copi = 0x011,
+    rph_g11_sclk = 0x012,
+    rph_g12      = 0x013,
+    rph_g13      = 0x014,
+    rph_txd0     = 0x015,
+    rph_rxd0     = 0x016,
+    rph_g16_ce2  = 0x017,
+    rph_g17      = 0x018,
+    rph_g18      = 0x019,
+    rph_g19_cipo = 0x01a,
+    rph_g20_copi = 0x01b,
+    rph_g21_sclk = 0x01c,
+    rph_g22      = 0x01d,
+    rph_g23      = 0x01e,
+    rph_g24      = 0x01f,
+    rph_g25      = 0x020,
+    rph_g26      = 0x021,
+    rph_g27      = 0x022,
+    ah_tmpio0    = 0x023,
+    ah_tmpio1    = 0x024,
+    ah_tmpio2    = 0x025,
+    ah_tmpio3    = 0x026,
+    ah_tmpio4    = 0x027,
+    ah_tmpio5    = 0x028,
+    ah_tmpio6    = 0x029,
+    ah_tmpio7    = 0x02a,
+    ah_tmpio8    = 0x02b,
+    ah_tmpio9    = 0x02c,
+    ah_tmpio10   = 0x02d,
+    ah_tmpio11   = 0x02e,
+    ah_tmpio12   = 0x02f,
+    ah_tmpio13   = 0x030,
+    mb1          = 0x031,
+    mb2          = 0x032,
+    mb4          = 0x033,
+    mb5          = 0x034,
+    mb6          = 0x035,
+    mb7          = 0x036,
+    mb10         = 0x037,
+    pmod0_1      = 0x038,
+    pmod0_2      = 0x039,
+    pmod0_3      = 0x03a,
+    pmod0_4      = 0x03b,
+    pmod0_5      = 0x03c,
+    pmod0_6      = 0x03d,
+    pmod0_7      = 0x03e,
+    pmod0_8      = 0x03f,
+    pmod1_1      = 0x040,
+    pmod1_2      = 0x041,
+    pmod1_3      = 0x042,
+    pmod1_4      = 0x043,
+    pmod1_5      = 0x044,
+    pmod1_6      = 0x045,
+    pmod1_7      = 0x046,
+    pmod1_8      = 0x047,
   };
 
   /**
@@ -285,9 +273,6 @@ class SonataPinmux : private utils::NoCopyNoMove {
     uart_2_rx     = 0x882,
     spi_0_cipo    = 0x883,
     spi_1_cipo    = 0x884,
-    spi_2_cipo    = 0x885,
-    spi_3_cipo    = 0x886,
-    spi_4_cipo    = 0x887,
   };
 
   /**
@@ -367,9 +352,9 @@ class SonataPinmux : private utils::NoCopyNoMove {
     switch (block_input) {
       case BlockInput::uart_1_rx:
         return 6;
-      case BlockInput::spi_2_cipo:
-      case BlockInput::spi_3_cipo:
-        return 5;
+      case BlockInput::spi_0_cipo:
+      case BlockInput::spi_1_cipo:
+        return 4;
       case BlockInput::uart_2_rx:
         return 3;
       default:

From f9f30c680908e9973aa0db3bb79cb3247532dae5 Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Fri, 1 Nov 2024 10:38:30 +0000
Subject: [PATCH 06/21] doc: updated pin mappings diagram to reflect spi
 changes

---
 doc/ip/pinmux/pin_mappings.dot |  126 ++--
 doc/ip/pinmux/pin_mappings.svg | 1064 ++++++++++++++++----------------
 2 files changed, 590 insertions(+), 600 deletions(-)

diff --git a/doc/ip/pinmux/pin_mappings.dot b/doc/ip/pinmux/pin_mappings.dot
index 6d1fb2245..b58ea6878 100644
--- a/doc/ip/pinmux/pin_mappings.dot
+++ b/doc/ip/pinmux/pin_mappings.dot
@@ -14,7 +14,7 @@ digraph {
     i2c_1 [label = "i2c_1|<sda>sda|<scl>scl"]
 
     // SPI for Flash, Ethernet & microSD
-    spi_0 [label = "spi_0\
+    spi_board [label = "spi_board\
       |<copi>copi\
       |<cipo>cipo\
       |<sclk>sclk\
@@ -25,18 +25,17 @@ digraph {
     "]
 
     // SPI for LCD
-    spi_1 [label = "spi_1\
+    spi_lcd [label = "spi_lcd\
       |<copi>copi\
       |<cipo>cipo\
       |<sclk>sclk\
       |<cs_0>cs_0\
       |<cs_1>cs_1\
       |<cs_2>cs_2\
-      |<cs_3>cs_3\
     "]
 
     // Pi Spi0, Pmod 0, Arduino Header
-    spi_2 [label = "spi_2\
+    spi_0 [label = "spi_0\
       |<copi>copi\
       |<cipo>cipo\
       |<sclk>sclk\
@@ -47,7 +46,7 @@ digraph {
     "]
 
     // Pi Spi1, Pmod 1, mikroBUS
-    spi_3 [label = "spi_3\
+    spi_1 [label = "spi_1\
       |<copi>copi\
       |<cipo>cipo\
       |<sclk>sclk\
@@ -377,65 +376,64 @@ digraph {
   // SPI
   edge [dir=forward color=dodgerblue];
 
-  spi_0:copi -> appspi:d0;
-  spi_0:cipo -> appspi:d1 [dir=back];
-  spi_0:sclk -> appspi:clk;
-  spi_0:cs_0 -> appspi:cs;
-
-  spi_0:copi -> ethmac:copi;
-  spi_0:cipo -> ethmac:cipo [dir=back];
-  spi_0:sclk -> ethmac:sclk;
-  spi_0:cs_1 -> ethmac:cs;
-  spi_0:cs_2 -> ethmac:rst;
-
-  spi_0:copi -> microsd:cmd;
-  spi_0:cipo -> microsd:dat0 [dir=back];
-  spi_0:sclk -> microsd:clk;
-  spi_0:cs_3 -> microsd:dat3;
-
-  spi_1:copi -> lcd:copi;
-  spi_1:sclk -> lcd:clk;
-  spi_1:cs_0 -> lcd:cs;
-  spi_1:cs_1 -> lcd:rst;
-  spi_1:cs_2 -> lcd:dc;
-  spi_1:cs_3 -> lcd:backlight;
-
-  spi_2:copi -> pmod0:2;
-  spi_2:cipo -> pmod0:3 [dir=back];
-  spi_2:sclk -> pmod0:4;
-  spi_2:cs_0 -> pmod0:1;
-  spi_2:cs_1 -> pmod0:7;
-  spi_2:cs_2 -> pmod0:8;
-
-  spi_2:copi -> rph:g10_spi0_copi;
-  spi_2:cipo -> rph:g9_spi0_cipo [dir=back];
-  spi_2:sclk -> rph:g11_spi0_sclk;
-  spi_2:cs_0 -> rph:g7_spi0_ce0;
-  spi_2:cs_1 -> rph:g8_spi0_ce1;
-
-  spi_2:copi -> ah:tmpio11;
-  spi_2:cipo -> ah:tmpio12 [dir=back];
-  spi_2:sclk -> ah:tmpio13;
-  spi_2:cs_3 -> ah:tmpio10;
-
-  spi_3:copi -> pmod1:2;
-  spi_3:cipo -> pmod1:3 [dir=back];
-  spi_3:sclk -> pmod1:4;
-  spi_3:cs_0 -> pmod1:1;
-  spi_3:cs_1 -> pmod1:7;
-  spi_3:cs_2 -> pmod1:8;
-
-  spi_3:copi -> rph:g20_spi1_copi;
-  spi_3:cipo -> rph:g19_spi1_cipo [dir=back];
-  spi_3:sclk -> rph:g21_spi1_sclk;
-  spi_3:cs_0 -> rph:g18_spi1_ce0;
-  spi_3:cs_1 -> rph:g17_spi1_ce1;
-  spi_3:cs_2 -> rph:g16_spi1_ce2;
-
-  spi_3:copi -> mb:4;
-  spi_3:cipo -> mb:3 [dir=back];
-  spi_3:sclk -> mb:2;
-  spi_3:cs_3 -> mb:1;
+  spi_board:copi -> appspi:d0;
+  spi_board:cipo -> appspi:d1 [dir=back];
+  spi_board:sclk -> appspi:clk;
+  spi_board:cs_0 -> appspi:cs;
+
+  spi_board:copi -> ethmac:copi;
+  spi_board:cipo -> ethmac:cipo [dir=back];
+  spi_board:sclk -> ethmac:sclk;
+  spi_board:cs_1 -> ethmac:cs;
+  spi_board:cs_2 -> ethmac:rst;
+
+  spi_board:copi -> microsd:cmd;
+  spi_board:cipo -> microsd:dat0 [dir=back];
+  spi_board:sclk -> microsd:clk;
+  spi_board:cs_3 -> microsd:dat3;
+
+  spi_lcd:copi -> lcd:copi;
+  spi_lcd:sclk -> lcd:clk;
+  spi_lcd:cs_0 -> lcd:cs;
+  spi_lcd:cs_1 -> lcd:dc;
+  spi_lcd:cs_2 -> lcd:rst;
+
+  spi_0:copi -> pmod0:2;
+  spi_0:cipo -> pmod0:3 [dir=back];
+  spi_0:sclk -> pmod0:4;
+  spi_0:cs_0 -> pmod0:1;
+  spi_0:cs_1 -> pmod0:7;
+  spi_0:cs_2 -> pmod0:8;
+
+  spi_0:copi -> rph:g10_spi0_copi;
+  spi_0:cipo -> rph:g9_spi0_cipo [dir=back];
+  spi_0:sclk -> rph:g11_spi0_sclk;
+  spi_0:cs_0 -> rph:g7_spi0_ce0;
+  spi_0:cs_1 -> rph:g8_spi0_ce1;
+
+  spi_0:copi -> ah:tmpio11;
+  spi_0:cipo -> ah:tmpio12 [dir=back];
+  spi_0:sclk -> ah:tmpio13;
+  spi_0:cs_3 -> ah:tmpio10;
+
+  spi_1:copi -> pmod1:2;
+  spi_1:cipo -> pmod1:3 [dir=back];
+  spi_1:sclk -> pmod1:4;
+  spi_1:cs_0 -> pmod1:1;
+  spi_1:cs_1 -> pmod1:7;
+  spi_1:cs_2 -> pmod1:8;
+
+  spi_1:copi -> rph:g20_spi1_copi;
+  spi_1:cipo -> rph:g19_spi1_cipo [dir=back];
+  spi_1:sclk -> rph:g21_spi1_sclk;
+  spi_1:cs_0 -> rph:g18_spi1_ce0;
+  spi_1:cs_1 -> rph:g17_spi1_ce1;
+  spi_1:cs_2 -> rph:g16_spi1_ce2;
+
+  spi_1:copi -> mb:4;
+  spi_1:cipo -> mb:3 [dir=back];
+  spi_1:sclk -> mb:2;
+  spi_1:cs_3 -> mb:1;
 
   // PWM
   edge [dir=forward color=hotpink];
diff --git a/doc/ip/pinmux/pin_mappings.svg b/doc/ip/pinmux/pin_mappings.svg
index 6158122ac..bdb24f02f 100644
--- a/doc/ip/pinmux/pin_mappings.svg
+++ b/doc/ip/pinmux/pin_mappings.svg
@@ -11,12 +11,12 @@
 <!-- uart_0 -->
 <g id="node1" class="node">
 <title>uart_0</title>
-<path fill="none" stroke="black" d="M32.25,-1689.12C32.25,-1689.12 70,-1689.12 70,-1689.12 76,-1689.12 82,-1695.12 82,-1701.12 82,-1701.12 82,-1752.88 82,-1752.88 82,-1758.88 76,-1764.88 70,-1764.88 70,-1764.88 32.25,-1764.88 32.25,-1764.88 26.25,-1764.88 20.25,-1758.88 20.25,-1752.88 20.25,-1752.88 20.25,-1701.12 20.25,-1701.12 20.25,-1695.12 26.25,-1689.12 32.25,-1689.12"/>
-<text text-anchor="middle" x="51.12" y="-1747.58" font-family="Times,serif" font-size="14.00">uart_0</text>
-<polyline fill="none" stroke="black" points="20.25,-1739.62 82,-1739.62"/>
-<text text-anchor="middle" x="51.12" y="-1722.33" font-family="Times,serif" font-size="14.00">tx</text>
-<polyline fill="none" stroke="black" points="20.25,-1714.38 82,-1714.38"/>
-<text text-anchor="middle" x="51.12" y="-1697.08" font-family="Times,serif" font-size="14.00">rx</text>
+<path fill="none" stroke="black" d="M32.25,-1680.12C32.25,-1680.12 70,-1680.12 70,-1680.12 76,-1680.12 82,-1686.12 82,-1692.12 82,-1692.12 82,-1743.88 82,-1743.88 82,-1749.88 76,-1755.88 70,-1755.88 70,-1755.88 32.25,-1755.88 32.25,-1755.88 26.25,-1755.88 20.25,-1749.88 20.25,-1743.88 20.25,-1743.88 20.25,-1692.12 20.25,-1692.12 20.25,-1686.12 26.25,-1680.12 32.25,-1680.12"/>
+<text text-anchor="middle" x="51.12" y="-1738.58" font-family="Times,serif" font-size="14.00">uart_0</text>
+<polyline fill="none" stroke="black" points="20.25,-1730.62 82,-1730.62"/>
+<text text-anchor="middle" x="51.12" y="-1713.33" font-family="Times,serif" font-size="14.00">tx</text>
+<polyline fill="none" stroke="black" points="20.25,-1705.38 82,-1705.38"/>
+<text text-anchor="middle" x="51.12" y="-1688.08" font-family="Times,serif" font-size="14.00">rx</text>
 </g>
 <!-- usb -->
 <g id="node18" class="node">
@@ -43,36 +43,36 @@
 <!-- uart_0&#45;&gt;usb -->
 <g id="edge1" class="edge">
 <title>uart_0:tx&#45;&gt;usb:ser0_tx</title>
-<path fill="none" stroke="purple" d="M83.12,-1727C465.58,-1727 559.07,-1634.87 935.74,-1633.03"/>
-<polygon fill="purple" stroke="purple" points="935.75,-1636.53 945.74,-1633 935.73,-1629.53 935.75,-1636.53"/>
+<path fill="none" stroke="purple" d="M83.12,-1718C465.17,-1718 559.46,-1634.69 935.75,-1633.03"/>
+<polygon fill="purple" stroke="purple" points="935.74,-1636.53 945.74,-1633 935.73,-1629.53 935.74,-1636.53"/>
 </g>
 <!-- uart_0&#45;&gt;usb -->
 <g id="edge2" class="edge">
 <title>uart_0:rx&#45;&gt;usb:ser0_rx</title>
-<path fill="none" stroke="purple" d="M94.36,-1701.97C471.35,-1700.13 564.61,-1606 947.25,-1606"/>
-<polygon fill="purple" stroke="purple" points="94.63,-1698.47 84.64,-1702 94.65,-1705.47 94.63,-1698.47"/>
+<path fill="none" stroke="purple" d="M94.63,-1692.97C471,-1691.27 565.12,-1606 947.25,-1606"/>
+<polygon fill="purple" stroke="purple" points="94.63,-1689.47 84.64,-1693 94.65,-1696.47 94.63,-1689.47"/>
 </g>
 <!-- uart_1 -->
 <g id="node2" class="node">
 <title>uart_1</title>
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-<text text-anchor="middle" x="51.12" y="-1096.08" font-family="Times,serif" font-size="14.00">rx</text>
+<path fill="none" stroke="black" d="M32.25,-1079.12C32.25,-1079.12 70,-1079.12 70,-1079.12 76,-1079.12 82,-1085.12 82,-1091.12 82,-1091.12 82,-1142.88 82,-1142.88 82,-1148.88 76,-1154.88 70,-1154.88 70,-1154.88 32.25,-1154.88 32.25,-1154.88 26.25,-1154.88 20.25,-1148.88 20.25,-1142.88 20.25,-1142.88 20.25,-1091.12 20.25,-1091.12 20.25,-1085.12 26.25,-1079.12 32.25,-1079.12"/>
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+<text text-anchor="middle" x="51.12" y="-1112.33" font-family="Times,serif" font-size="14.00">tx</text>
+<polyline fill="none" stroke="black" points="20.25,-1104.38 82,-1104.38"/>
+<text text-anchor="middle" x="51.12" y="-1087.08" font-family="Times,serif" font-size="14.00">rx</text>
 </g>
 <!-- uart_1&#45;&gt;usb -->
 <g id="edge3" class="edge">
 <title>uart_1:tx&#45;&gt;usb:ser1_tx</title>
-<path fill="none" stroke="purple" d="M83.12,-1126C512.74,-1126 513.84,-1570.09 935.92,-1577.9"/>
+<path fill="none" stroke="purple" d="M83.12,-1117C514.59,-1117 512.04,-1569.93 935.87,-1577.89"/>
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 <!-- uart_1&#45;&gt;usb -->
 <g id="edge4" class="edge">
 <title>uart_1:rx&#45;&gt;usb:ser1_rx</title>
-<path fill="none" stroke="purple" d="M94.44,-1101.1C516.14,-1108.88 518.04,-1551 947.25,-1551"/>
-<polygon fill="purple" stroke="purple" points="94.67,-1097.61 84.64,-1101.01 94.61,-1104.61 94.67,-1097.61"/>
+<path fill="none" stroke="purple" d="M94.49,-1092.11C517.93,-1100.03 516.2,-1551 947.25,-1551"/>
+<polygon fill="purple" stroke="purple" points="94.67,-1088.61 84.64,-1092.01 94.61,-1095.61 94.67,-1088.61"/>
 </g>
 <!-- rph -->
 <g id="node25" class="node">
@@ -195,14 +195,14 @@
 <!-- uart_1&#45;&gt;rph -->
 <g id="edge5" class="edge">
 <title>uart_1:tx&#45;&gt;rph:txd0</title>
-<path fill="none" stroke="purple" d="M83.12,-1126C630.33,-1126 283.1,-2102.51 818.08,-2115.86"/>
+<path fill="none" stroke="purple" d="M83.12,-1117C633.5,-1117 279.99,-2102.39 818.01,-2115.86"/>
 <polygon fill="purple" stroke="purple" points="817.69,-2119.36 827.74,-2115.98 817.78,-2112.36 817.69,-2119.36"/>
 </g>
 <!-- uart_1&#45;&gt;rph -->
 <g id="edge6" class="edge">
 <title>uart_1:rx&#45;&gt;rph:rxd0</title>
-<path fill="none" stroke="purple" d="M94.28,-1101.14C628.58,-1114.46 282.75,-2089 829.25,-2089"/>
-<polygon fill="purple" stroke="purple" points="94.68,-1097.64 84.64,-1101.02 94.59,-1104.64 94.68,-1097.64"/>
+<path fill="none" stroke="purple" d="M94.35,-1092.14C631.69,-1105.58 279.58,-2089 829.25,-2089"/>
+<polygon fill="purple" stroke="purple" points="94.68,-1088.64 84.64,-1092.02 94.59,-1095.64 94.68,-1088.64"/>
 </g>
 <!-- ah -->
 <g id="node26" class="node">
@@ -269,14 +269,14 @@
 <!-- uart_1&#45;&gt;ah -->
 <g id="edge7" class="edge">
 <title>uart_1:tx&#45;&gt;ah:tmpio1</title>
-<path fill="none" stroke="purple" d="M83.12,-1126C571.15,-1126 375.5,-354.2 852.85,-342.14"/>
+<path fill="none" stroke="purple" d="M83.12,-1117C568.35,-1117 378.24,-354.06 852.91,-342.14"/>
 <polygon fill="purple" stroke="purple" points="852.78,-345.64 862.74,-342.02 852.69,-338.64 852.78,-345.64"/>
 </g>
 <!-- uart_1&#45;&gt;ah -->
 <g id="edge8" class="edge">
 <title>uart_1:rx&#45;&gt;ah:tmpio0</title>
-<path fill="none" stroke="purple" d="M94.5,-1100.86C556.2,-1089.25 392.3,-369 864.25,-369"/>
-<polygon fill="purple" stroke="purple" points="94.59,-1097.36 84.64,-1100.98 94.68,-1104.36 94.59,-1097.36"/>
+<path fill="none" stroke="purple" d="M94.44,-1091.86C553.56,-1080.4 395.01,-369 864.25,-369"/>
+<polygon fill="purple" stroke="purple" points="94.59,-1088.36 84.64,-1091.98 94.68,-1095.36 94.59,-1088.36"/>
 </g>
 <!-- mb -->
 <g id="node27" class="node">
@@ -328,14 +328,14 @@
 <!-- uart_1&#45;&gt;mb -->
 <g id="edge11" class="edge">
 <title>uart_1:tx&#45;&gt;mb:7</title>
-<path fill="none" stroke="purple" d="M83.12,-1126C452,-1126 545.65,-1174 908.87,-1174.98"/>
+<path fill="none" stroke="purple" d="M83.12,-1117C452.25,-1117 545.4,-1173.82 908.87,-1174.98"/>
 <polygon fill="purple" stroke="purple" points="908.73,-1178.48 918.74,-1175 908.74,-1171.48 908.73,-1178.48"/>
 </g>
 <!-- uart_1&#45;&gt;mb -->
 <g id="edge12" class="edge">
 <title>uart_1:rx&#45;&gt;mb:8</title>
-<path fill="none" stroke="purple" d="M94.5,-1101.01C457.68,-1101.96 551.43,-1148 920.25,-1148"/>
-<polygon fill="purple" stroke="purple" points="94.64,-1097.52 84.64,-1101 94.63,-1104.52 94.64,-1097.52"/>
+<path fill="none" stroke="purple" d="M94.51,-1092.02C457.92,-1093.14 551.19,-1148 920.25,-1148"/>
+<polygon fill="purple" stroke="purple" points="94.64,-1088.52 84.64,-1092 94.63,-1095.52 94.64,-1088.52"/>
 </g>
 <!-- pmod0 -->
 <g id="node28" class="node">
@@ -379,36 +379,36 @@
 <!-- uart_1&#45;&gt;pmod0 -->
 <g id="edge9" class="edge">
 <title>uart_1:tx&#45;&gt;pmod0:2</title>
-<path fill="none" stroke="purple" d="M83.12,-1126C448.3,-1126 464.89,-779.39 822.74,-772.12"/>
-<polygon fill="purple" stroke="purple" points="822.77,-775.62 832.74,-772.02 822.7,-768.62 822.77,-775.62"/>
+<path fill="none" stroke="purple" d="M83.12,-1117C446.63,-1117 466.5,-779.21 822.8,-772.11"/>
+<polygon fill="purple" stroke="purple" points="822.77,-775.61 832.74,-772.01 822.7,-768.61 822.77,-775.61"/>
 </g>
 <!-- uart_1&#45;&gt;pmod0 -->
 <g id="edge10" class="edge">
 <title>uart_1:rx&#45;&gt;pmod0:3</title>
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-<polygon fill="purple" stroke="purple" points="94.6,-1097.39 84.64,-1100.98 94.67,-1104.39 94.6,-1097.39"/>
+<path fill="none" stroke="purple" d="M94.59,-1091.89C451.23,-1084.75 470.38,-745 834.25,-745"/>
+<polygon fill="purple" stroke="purple" points="94.6,-1088.39 84.64,-1091.98 94.67,-1095.39 94.6,-1088.39"/>
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 <g id="node3" class="node">
 <title>uart_2</title>
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-<text text-anchor="middle" x="51.12" y="-1652.58" font-family="Times,serif" font-size="14.00">uart_2</text>
-<polyline fill="none" stroke="black" points="20.25,-1644.62 82,-1644.62"/>
-<text text-anchor="middle" x="51.12" y="-1627.33" font-family="Times,serif" font-size="14.00">tx</text>
-<polyline fill="none" stroke="black" points="20.25,-1619.38 82,-1619.38"/>
-<text text-anchor="middle" x="51.12" y="-1602.08" font-family="Times,serif" font-size="14.00">rx</text>
+<path fill="none" stroke="black" d="M32.25,-1585.12C32.25,-1585.12 70,-1585.12 70,-1585.12 76,-1585.12 82,-1591.12 82,-1597.12 82,-1597.12 82,-1648.88 82,-1648.88 82,-1654.88 76,-1660.88 70,-1660.88 70,-1660.88 32.25,-1660.88 32.25,-1660.88 26.25,-1660.88 20.25,-1654.88 20.25,-1648.88 20.25,-1648.88 20.25,-1597.12 20.25,-1597.12 20.25,-1591.12 26.25,-1585.12 32.25,-1585.12"/>
+<text text-anchor="middle" x="51.12" y="-1643.58" font-family="Times,serif" font-size="14.00">uart_2</text>
+<polyline fill="none" stroke="black" points="20.25,-1635.62 82,-1635.62"/>
+<text text-anchor="middle" x="51.12" y="-1618.33" font-family="Times,serif" font-size="14.00">tx</text>
+<polyline fill="none" stroke="black" points="20.25,-1610.38 82,-1610.38"/>
+<text text-anchor="middle" x="51.12" y="-1593.08" font-family="Times,serif" font-size="14.00">rx</text>
 </g>
 <!-- uart_2&#45;&gt;usb -->
 <g id="edge13" class="edge">
 <title>uart_2:tx&#45;&gt;usb:ser1_tx</title>
-<path fill="none" stroke="purple" d="M83.12,-1632C464.08,-1632 560.52,-1579.08 935.78,-1578.02"/>
-<polygon fill="purple" stroke="purple" points="935.74,-1581.52 945.74,-1578 935.73,-1574.52 935.74,-1581.52"/>
+<path fill="none" stroke="purple" d="M83.12,-1623C463.85,-1623 560.74,-1578.9 935.79,-1578.01"/>
+<polygon fill="purple" stroke="purple" points="935.74,-1581.51 945.74,-1578 935.73,-1574.51 935.74,-1581.51"/>
 </g>
 <!-- uart_2&#45;&gt;usb -->
 <g id="edge14" class="edge">
 <title>uart_2:rx&#45;&gt;usb:ser1_rx</title>
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-<polygon fill="purple" stroke="purple" points="94.63,-1603.48 84.64,-1607 94.64,-1610.48 94.63,-1603.48"/>
+<path fill="none" stroke="purple" d="M94.59,-1597.99C469.68,-1597.06 566.48,-1551 947.25,-1551"/>
+<polygon fill="purple" stroke="purple" points="94.63,-1594.49 84.64,-1598 94.64,-1601.49 94.63,-1594.49"/>
 </g>
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 <g id="node19" class="node">
@@ -427,14 +427,14 @@
 <!-- uart_2&#45;&gt;rs232 -->
 <g id="edge15" class="edge">
 <title>uart_2:tx&#45;&gt;rs232:tx</title>
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-<polygon fill="purple" stroke="purple" points="942.73,-1716.48 952.74,-1713 942.74,-1709.48 942.73,-1716.48"/>
+<path fill="none" stroke="purple" d="M83.12,-1623C468.55,-1623 563.18,-1711.25 942.93,-1712.97"/>
+<polygon fill="purple" stroke="purple" points="942.73,-1716.47 952.74,-1713 942.74,-1709.47 942.73,-1716.47"/>
 </g>
 <!-- uart_2&#45;&gt;rs232 -->
 <g id="edge16" class="edge">
 <title>uart_2:rx&#45;&gt;rs232:rx</title>
-<path fill="none" stroke="purple" d="M94.43,-1607.02C473.7,-1608.52 569.33,-1685 954.25,-1685"/>
-<polygon fill="purple" stroke="purple" points="94.65,-1603.52 84.64,-1607 94.63,-1610.52 94.65,-1603.52"/>
+<path fill="none" stroke="purple" d="M94.44,-1598.02C474.06,-1599.69 568.96,-1685 954.25,-1685"/>
+<polygon fill="purple" stroke="purple" points="94.65,-1594.53 84.64,-1598 94.63,-1601.53 94.65,-1594.53"/>
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 <g id="node29" class="node">
@@ -478,24 +478,24 @@
 <!-- uart_2&#45;&gt;pmod1 -->
 <g id="edge17" class="edge">
 <title>uart_2:tx&#45;&gt;pmod1:2</title>
-<path fill="none" stroke="purple" d="M83.12,-1632C511.63,-1632 403.9,-1024.82 822.98,-1014.14"/>
-<polygon fill="purple" stroke="purple" points="822.78,-1017.65 832.74,-1014.02 822.69,-1010.65 822.78,-1017.65"/>
+<path fill="none" stroke="purple" d="M83.12,-1623C509.12,-1623 406.34,-1024.66 823.04,-1014.14"/>
+<polygon fill="purple" stroke="purple" points="822.78,-1017.64 832.74,-1014.02 822.69,-1010.64 822.78,-1017.64"/>
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 <!-- uart_2&#45;&gt;pmod1 -->
 <g id="edge18" class="edge">
 <title>uart_2:rx&#45;&gt;pmod1:3</title>
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-<polygon fill="purple" stroke="purple" points="94.59,-1603.35 84.64,-1606.98 94.68,-1610.35 94.59,-1603.35"/>
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+<polygon fill="purple" stroke="purple" points="94.59,-1594.36 84.64,-1597.98 94.68,-1601.36 94.59,-1594.36"/>
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 <g id="node4" class="node">
 <title>i2c_0</title>
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-<text text-anchor="middle" x="51.12" y="-1557.58" font-family="Times,serif" font-size="14.00">i2c_0</text>
-<polyline fill="none" stroke="black" points="24.12,-1549.62 78.12,-1549.62"/>
-<text text-anchor="middle" x="51.12" y="-1532.33" font-family="Times,serif" font-size="14.00">sda</text>
-<polyline fill="none" stroke="black" points="24.12,-1524.38 78.12,-1524.38"/>
-<text text-anchor="middle" x="51.12" y="-1507.08" font-family="Times,serif" font-size="14.00">scl</text>
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+<text text-anchor="middle" x="51.12" y="-1548.58" font-family="Times,serif" font-size="14.00">i2c_0</text>
+<polyline fill="none" stroke="black" points="24.12,-1540.62 78.12,-1540.62"/>
+<text text-anchor="middle" x="51.12" y="-1523.33" font-family="Times,serif" font-size="14.00">sda</text>
+<polyline fill="none" stroke="black" points="24.12,-1515.38 78.12,-1515.38"/>
+<text text-anchor="middle" x="51.12" y="-1498.08" font-family="Times,serif" font-size="14.00">scl</text>
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@@ -522,129 +522,129 @@
 <!-- i2c_0&#45;&gt;qwiic -->
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-<path fill="none" stroke="darkorange" d="M90.62,-1536.99C472.38,-1536.27 574.05,-1499.72 955.87,-1499.01"/>
-<polygon fill="darkorange" stroke="darkorange" points="90.64,-1533.49 80.64,-1537 90.64,-1540.49 90.64,-1533.49"/>
+<path fill="none" stroke="darkorange" d="M90.61,-1527.99C472.24,-1527.44 574.19,-1499.55 955.88,-1499.01"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.64,-1524.49 80.64,-1528 90.64,-1531.49 90.64,-1524.49"/>
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 <g id="edge20" class="edge">
 <title>i2c_0:scl&#45;&gt;qwiic:scl0</title>
-<path fill="none" stroke="darkorange" d="M90.62,-1511.99C472.42,-1511.23 574.01,-1472.76 955.87,-1472.01"/>
-<polygon fill="darkorange" stroke="darkorange" points="90.64,-1508.49 80.64,-1512 90.64,-1515.49 90.64,-1508.49"/>
+<path fill="none" stroke="darkorange" d="M90.61,-1502.99C472.27,-1502.4 574.16,-1472.59 955.87,-1472.01"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.64,-1499.49 80.64,-1503 90.64,-1506.49 90.64,-1499.49"/>
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-<path fill="none" stroke="darkorange" d="M90.48,-1537.14C611.53,-1550.42 296.84,-2481.67 817.97,-2494.86"/>
-<polygon fill="darkorange" stroke="darkorange" points="90.68,-1533.65 80.64,-1537.02 90.59,-1540.65 90.68,-1533.65"/>
-<polygon fill="darkorange" stroke="darkorange" points="817.69,-2498.36 827.74,-2494.98 817.78,-2491.36 817.69,-2498.36"/>
+<path fill="none" stroke="darkorange" d="M90.55,-1528.14C614.58,-1541.55 293.79,-2481.55 817.91,-2494.86"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.68,-1524.65 80.64,-1528.02 90.59,-1531.65 90.68,-1524.65"/>
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-<polygon fill="darkorange" stroke="darkorange" points="90.68,-1508.65 80.64,-1512.02 90.59,-1515.65 90.68,-1508.65"/>
-<polygon fill="darkorange" stroke="darkorange" points="817.69,-2471.36 827.74,-2467.98 817.78,-2464.36 817.69,-2471.36"/>
+<path fill="none" stroke="darkorange" d="M90.53,-1503.14C613.9,-1516.52 294.47,-2454.58 817.92,-2467.86"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.68,-1499.65 80.64,-1503.02 90.59,-1506.65 90.68,-1499.65"/>
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-<polygon fill="darkorange" stroke="darkorange" points="90.59,-1533.35 80.64,-1536.98 90.68,-1540.35 90.59,-1533.35"/>
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 <g id="edge24" class="edge">
 <title>i2c_0:scl&#45;&gt;pmod0:3</title>
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 <g id="node5" class="node">
 <title>i2c_1</title>
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+<text text-anchor="middle" x="51.12" y="-1403.08" font-family="Times,serif" font-size="14.00">scl</text>
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 <!-- i2c_1&#45;&gt;qwiic -->
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 <title>i2c_1:sda&#45;&gt;qwiic:sda1</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.64,-1438.5 80.64,-1442 90.64,-1445.5 90.64,-1438.5"/>
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 <!-- i2c_1&#45;&gt;qwiic -->
 <g id="edge26" class="edge">
 <title>i2c_1:scl&#45;&gt;qwiic:scl1</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.64,-1413.5 80.64,-1417 90.64,-1420.5 90.64,-1413.5"/>
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 <g id="edge29" class="edge">
 <title>i2c_1:sda&#45;&gt;rph:g2_sda</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.68,-1438.64 80.64,-1442.02 90.59,-1445.64 90.68,-1438.64"/>
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 <g id="edge30" class="edge">
 <title>i2c_1:scl&#45;&gt;rph:g3_scl</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.68,-1413.64 80.64,-1417.02 90.59,-1420.64 90.68,-1413.64"/>
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 <g id="edge27" class="edge">
 <title>i2c_1:sda&#45;&gt;mb:5</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.62,-1438.44 80.64,-1441.99 90.66,-1445.44 90.62,-1438.44"/>
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+<polygon fill="darkorange" stroke="darkorange" points="90.62,-1429.44 80.64,-1432.99 90.66,-1436.44 90.62,-1429.44"/>
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 <title>i2c_1:scl&#45;&gt;mb:6</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.62,-1413.44 80.64,-1416.99 90.66,-1420.44 90.62,-1413.44"/>
+<path fill="none" stroke="darkorange" d="M90.59,-1407.94C461.71,-1403.94 537.71,-1206.02 908.9,-1202.06"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.62,-1404.44 80.64,-1407.99 90.66,-1411.44 90.62,-1404.44"/>
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 <!-- i2c_1&#45;&gt;pmod1 -->
 <g id="edge31" class="edge">
 <title>i2c_1:sda&#45;&gt;pmod1:4</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.6,-1438.37 80.64,-1441.98 90.68,-1445.37 90.6,-1438.37"/>
-<polygon fill="darkorange" stroke="darkorange" points="822.78,-963.64 832.74,-960.02 822.7,-956.64 822.78,-963.64"/>
+<path fill="none" stroke="darkorange" d="M90.6,-1432.87C470.71,-1423.9 442.69,-969.02 822.88,-960.13"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.6,-1429.37 80.64,-1432.98 90.68,-1436.36 90.6,-1429.37"/>
+<polygon fill="darkorange" stroke="darkorange" points="822.78,-963.63 832.74,-960.02 822.7,-956.63 822.78,-963.63"/>
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 <!-- i2c_1&#45;&gt;pmod1 -->
 <g id="edge32" class="edge">
 <title>i2c_1:scl&#45;&gt;pmod1:3</title>
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-<polygon fill="darkorange" stroke="darkorange" points="90.6,-1413.37 80.64,-1416.98 90.68,-1420.37 90.6,-1413.37"/>
+<path fill="none" stroke="darkorange" d="M90.54,-1407.87C459.41,-1399.7 454,-995.22 822.94,-987.12"/>
+<polygon fill="darkorange" stroke="darkorange" points="90.6,-1404.37 80.64,-1407.98 90.68,-1411.37 90.6,-1404.37"/>
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 </g>
-<!-- spi_0 -->
+<!-- spi_board -->
 <g id="node6" class="node">
-<title>spi_0</title>
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-<polyline fill="none" stroke="black" points="24.12,-3017.75 78.12,-3017.75"/>
+<title>spi_board</title>
+<path fill="none" stroke="black" d="M20.62,-2841C20.62,-2841 81.62,-2841 81.62,-2841 87.62,-2841 93.62,-2847 93.62,-2853 93.62,-2853 93.62,-3031 93.62,-3031 93.62,-3037 87.62,-3043 81.62,-3043 81.62,-3043 20.62,-3043 20.62,-3043 14.62,-3043 8.62,-3037 8.62,-3031 8.62,-3031 8.62,-2853 8.62,-2853 8.62,-2847 14.62,-2841 20.62,-2841"/>
+<text text-anchor="middle" x="51.12" y="-3025.7" font-family="Times,serif" font-size="14.00">spi_board</text>
+<polyline fill="none" stroke="black" points="8.62,-3017.75 93.62,-3017.75"/>
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+<polyline fill="none" stroke="black" points="8.62,-2992.5 93.62,-2992.5"/>
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+<polyline fill="none" stroke="black" points="8.62,-2967.25 93.62,-2967.25"/>
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+<polyline fill="none" stroke="black" points="8.62,-2942 93.62,-2942"/>
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-<polyline fill="none" stroke="black" points="24.12,-2916.75 78.12,-2916.75"/>
+<polyline fill="none" stroke="black" points="8.62,-2916.75 93.62,-2916.75"/>
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-<polyline fill="none" stroke="black" points="24.12,-2891.5 78.12,-2891.5"/>
+<polyline fill="none" stroke="black" points="8.62,-2891.5 93.62,-2891.5"/>
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-<polyline fill="none" stroke="black" points="24.12,-2866.25 78.12,-2866.25"/>
+<polyline fill="none" stroke="black" points="8.62,-2866.25 93.62,-2866.25"/>
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 <text text-anchor="start" x="1043.25" y="-3053.7" font-family="Times,serif" font-size="14.00">cs</text>
 </g>
-<!-- spi_0&#45;&gt;appspi -->
+<!-- spi_board&#45;&gt;appspi -->
 <g id="edge33" class="edge">
-<title>spi_0:copi&#45;&gt;appspi:d0</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-3005C469.71,-3005 550.25,-3190.33 934.78,-3193.95"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="934.72,-3197.45 944.74,-3193.99 934.75,-3190.45 934.72,-3197.45"/>
+<title>spi_board:copi&#45;&gt;appspi:d0</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-3005C478.83,-3005 557.24,-3190.33 934.99,-3193.95"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="934.72,-3197.44 944.74,-3193.99 934.75,-3190.45 934.72,-3197.44"/>
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-<!-- spi_0&#45;&gt;appspi -->
+<!-- spi_board&#45;&gt;appspi -->
 <g id="edge34" class="edge">
-<title>spi_0:cipo&#45;&gt;appspi:d1</title>
-<path fill="none" stroke="dodgerblue" d="M90.59,-2980.05C474.94,-2983.63 555.85,-3167 946.25,-3167"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.65,-2976.55 80.64,-2980.01 90.62,-2983.55 90.65,-2976.55"/>
+<title>spi_board:cipo&#45;&gt;appspi:d1</title>
+<path fill="none" stroke="dodgerblue" d="M106.38,-2980.05C483.95,-2983.63 562.73,-3167 946.25,-3167"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="106.65,-2976.55 96.64,-2980.01 106.62,-2983.55 106.65,-2976.55"/>
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-<!-- spi_0&#45;&gt;appspi -->
+<!-- spi_board&#45;&gt;appspi -->
 <g id="edge35" class="edge">
-<title>spi_0:sclk&#45;&gt;appspi:clk</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-2955C465.02,-2955 554.81,-3082.47 934.92,-3084.96"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="934.73,-3088.46 944.74,-3085 934.75,-3081.46 934.73,-3088.46"/>
+<title>spi_board:sclk&#45;&gt;appspi:clk</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-2955C473.96,-2955 561.84,-3082.41 934.85,-3084.96"/>
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-<!-- spi_0&#45;&gt;appspi -->
+<!-- spi_board&#45;&gt;appspi -->
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-<title>spi_0:cs_0&#45;&gt;appspi:cs</title>
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-<polygon fill="dodgerblue" stroke="dodgerblue" points="934.73,-3061.46 944.74,-3058 934.75,-3054.46 934.73,-3061.46"/>
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+<path fill="none" stroke="dodgerblue" d="M95.12,-2929C473.89,-2929 561.9,-3055.43 934.85,-3057.96"/>
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@@ -723,34 +723,34 @@
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-<!-- spi_0&#45;&gt;ethmac -->
+<!-- spi_board&#45;&gt;ethmac -->
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-<title>spi_0:copi&#45;&gt;ethmac:copi</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-3005C451.32,-3005 547.24,-3005 913.77,-3005"/>
+<title>spi_board:copi&#45;&gt;ethmac:copi</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-3005C460.29,-3005 554.38,-3005 913.99,-3005"/>
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-<!-- spi_0&#45;&gt;ethmac -->
+<!-- spi_board&#45;&gt;ethmac -->
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-<title>spi_0:cipo&#45;&gt;ethmac:cipo</title>
-<path fill="none" stroke="dodgerblue" d="M90.6,-2980C457.14,-2979.96 553.05,-2978 925.25,-2978"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.64,-2976.5 80.64,-2980 90.64,-2983.5 90.64,-2976.5"/>
+<title>spi_board:cipo&#45;&gt;ethmac:cipo</title>
+<path fill="none" stroke="dodgerblue" d="M106.39,-2980C465.99,-2979.96 560.09,-2978 925.25,-2978"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="106.64,-2976.5 96.64,-2980 106.64,-2983.5 106.64,-2976.5"/>
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-<!-- spi_0&#45;&gt;ethmac -->
+<!-- spi_board&#45;&gt;ethmac -->
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-<title>spi_0:sclk&#45;&gt;ethmac:sclk</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-2955C451.33,-2955 547.23,-2951.08 913.77,-2951"/>
+<title>spi_board:sclk&#45;&gt;ethmac:sclk</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-2955C460.29,-2955 554.38,-2951.08 913.99,-2951"/>
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-<!-- spi_0&#45;&gt;ethmac -->
+<!-- spi_board&#45;&gt;ethmac -->
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-<title>spi_0:cs_1&#45;&gt;ethmac:cs</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-2904C451.43,-2904 547.14,-2923.59 913.77,-2923.99"/>
+<title>spi_board:cs_1&#45;&gt;ethmac:cs</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-2904C460.39,-2904 554.28,-2923.59 913.98,-2923.99"/>
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-<!-- spi_0&#45;&gt;ethmac -->
+<!-- spi_board&#45;&gt;ethmac -->
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-<title>spi_0:cs_2&#45;&gt;ethmac:rst</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-2879C451.41,-2879 547.16,-2896.63 913.77,-2896.99"/>
+<title>spi_board:cs_2&#45;&gt;ethmac:rst</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-2879C460.37,-2879 554.3,-2896.63 913.98,-2896.99"/>
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@@ -787,49 +787,47 @@
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-<!-- spi_0&#45;&gt;microsd -->
+<!-- spi_board&#45;&gt;microsd -->
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-<title>spi_0:copi&#45;&gt;microsd:cmd</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-3005C448.07,-3005 527.86,-2847.28 890.88,-2844.05"/>
+<title>spi_board:copi&#45;&gt;microsd:cmd</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-3005C457.07,-3005 534.84,-2847.36 890.83,-2844.05"/>
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-<!-- spi_0&#45;&gt;microsd -->
+<!-- spi_board&#45;&gt;microsd -->
 <g id="edge43" class="edge">
-<title>spi_0:cipo&#45;&gt;microsd:dat0</title>
-<path fill="none" stroke="dodgerblue" d="M90.58,-2979.94C456.09,-2976.12 530.65,-2790 902.25,-2790"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.62,-2976.44 80.64,-2979.99 90.66,-2983.44 90.62,-2976.44"/>
+<title>spi_board:cipo&#45;&gt;microsd:dat0</title>
+<path fill="none" stroke="dodgerblue" d="M106.63,-2979.94C465.16,-2976.03 537.59,-2790 902.25,-2790"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="106.62,-2976.44 96.64,-2979.99 106.66,-2983.44 106.62,-2976.44"/>
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-<!-- spi_0&#45;&gt;microsd -->
+<!-- spi_board&#45;&gt;microsd -->
 <g id="edge44" class="edge">
-<title>spi_0:sclk&#45;&gt;microsd:clk</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-2955C446.26,-2955 529.61,-2819.82 890.93,-2817.04"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="890.75,-2820.54 900.74,-2817.01 890.72,-2813.54 890.75,-2820.54"/>
+<title>spi_board:sclk&#45;&gt;microsd:clk</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-2955C455.23,-2955 536.63,-2819.88 890.88,-2817.05"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="890.75,-2820.55 900.74,-2817.01 890.72,-2813.55 890.75,-2820.55"/>
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-<!-- spi_0&#45;&gt;microsd -->
+<!-- spi_board&#45;&gt;microsd -->
 <g id="edge45" class="edge">
-<title>spi_0:cs_3&#45;&gt;microsd:dat3</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-2854C446.78,-2854 529.11,-2711.96 890.91,-2709.05"/>
+<title>spi_board:cs_3&#45;&gt;microsd:dat3</title>
+<path fill="none" stroke="dodgerblue" d="M95.12,-2854C455.76,-2854 536.11,-2712.03 890.87,-2709.05"/>
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-<!-- spi_1 -->
+<!-- spi_lcd -->
 <g id="node7" class="node">
-<title>spi_1</title>
-<path fill="none" stroke="black" d="M36.12,-287C36.12,-287 66.12,-287 66.12,-287 72.12,-287 78.12,-293 78.12,-299 78.12,-299 78.12,-477 78.12,-477 78.12,-483 72.12,-489 66.12,-489 66.12,-489 36.12,-489 36.12,-489 30.12,-489 24.12,-483 24.12,-477 24.12,-477 24.12,-299 24.12,-299 24.12,-293 30.12,-287 36.12,-287"/>
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-<polyline fill="none" stroke="black" points="24.12,-312.25 78.12,-312.25"/>
-<text text-anchor="middle" x="51.12" y="-294.95" font-family="Times,serif" font-size="14.00">cs_3</text>
+<title>spi_lcd</title>
+<path fill="none" stroke="black" d="M30.75,-302.62C30.75,-302.62 71.5,-302.62 71.5,-302.62 77.5,-302.62 83.5,-308.62 83.5,-314.62 83.5,-314.62 83.5,-467.38 83.5,-467.38 83.5,-473.38 77.5,-479.38 71.5,-479.38 71.5,-479.38 30.75,-479.38 30.75,-479.38 24.75,-479.38 18.75,-473.38 18.75,-467.38 18.75,-467.38 18.75,-314.62 18.75,-314.62 18.75,-308.62 24.75,-302.62 30.75,-302.62"/>
+<text text-anchor="middle" x="51.12" y="-462.07" font-family="Times,serif" font-size="14.00">spi_lcd</text>
+<polyline fill="none" stroke="black" points="18.75,-454.12 83.5,-454.12"/>
+<text text-anchor="middle" x="51.12" y="-436.82" font-family="Times,serif" font-size="14.00">copi</text>
+<polyline fill="none" stroke="black" points="18.75,-428.88 83.5,-428.88"/>
+<text text-anchor="middle" x="51.12" y="-411.57" font-family="Times,serif" font-size="14.00">cipo</text>
+<polyline fill="none" stroke="black" points="18.75,-403.62 83.5,-403.62"/>
+<text text-anchor="middle" x="51.12" y="-386.32" font-family="Times,serif" font-size="14.00">sclk</text>
+<polyline fill="none" stroke="black" points="18.75,-378.38 83.5,-378.38"/>
+<text text-anchor="middle" x="51.12" y="-361.07" font-family="Times,serif" font-size="14.00">cs_0</text>
+<polyline fill="none" stroke="black" points="18.75,-353.12 83.5,-353.12"/>
+<text text-anchor="middle" x="51.12" y="-335.82" font-family="Times,serif" font-size="14.00">cs_1</text>
+<polyline fill="none" stroke="black" points="18.75,-327.88 83.5,-327.88"/>
+<text text-anchor="middle" x="51.12" y="-310.57" font-family="Times,serif" font-size="14.00">cs_2</text>
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 </g>
-<!-- spi_1&#45;&gt;lcd -->
+<!-- spi_lcd&#45;&gt;lcd -->
 <g id="edge46" class="edge">
-<title>spi_1:copi&#45;&gt;lcd:copi</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-451C461.84,-451 553.97,-554.94 931.01,-556.97"/>
+<title>spi_lcd:copi&#45;&gt;lcd:copi</title>
+<path fill="none" stroke="dodgerblue" d="M84.12,-442C465.07,-442 555.65,-554.71 930.78,-556.97"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-560.47 940.74,-557 930.75,-553.47 930.73,-560.47"/>
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-<!-- spi_1&#45;&gt;lcd -->
+<!-- spi_lcd&#45;&gt;lcd -->
 <g id="edge47" class="edge">
-<title>spi_1:sclk&#45;&gt;lcd:clk</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-401C463.21,-401 552.64,-527.49 930.97,-529.96"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-533.46 940.74,-530 930.75,-526.46 930.73,-533.46"/>
+<title>spi_lcd:sclk&#45;&gt;lcd:clk</title>
+<path fill="none" stroke="dodgerblue" d="M84.12,-391C466.62,-391 554.15,-527.23 930.74,-529.96"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="930.72,-533.46 940.74,-529.99 930.75,-526.46 930.72,-533.46"/>
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-<!-- spi_1&#45;&gt;lcd -->
+<!-- spi_lcd&#45;&gt;lcd -->
 <g id="edge48" class="edge">
-<title>spi_1:cs_0&#45;&gt;lcd:cs</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-375C463.14,-375 552.71,-500.51 930.97,-502.96"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-506.46 940.74,-503 930.75,-499.46 930.73,-506.46"/>
+<title>spi_lcd:cs_0&#45;&gt;lcd:cs</title>
+<path fill="none" stroke="dodgerblue" d="M84.12,-366C466.48,-366 554.29,-500.27 930.74,-502.96"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="930.72,-506.46 940.74,-502.99 930.75,-499.46 930.72,-506.46"/>
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-<!-- spi_1&#45;&gt;lcd -->
+<!-- spi_lcd&#45;&gt;lcd -->
 <g id="edge49" class="edge">
-<title>spi_1:cs_1&#45;&gt;lcd:rst</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-350C462.95,-350 552.89,-472.57 930.98,-474.96"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-478.46 940.74,-475 930.75,-471.46 930.73,-478.46"/>
+<title>spi_lcd:cs_1&#45;&gt;lcd:dc</title>
+<path fill="none" stroke="dodgerblue" d="M84.12,-340C464.67,-340 556.03,-445.85 930.79,-447.97"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-451.47 940.74,-448 930.75,-444.47 930.73,-451.47"/>
 </g>
-<!-- spi_1&#45;&gt;lcd -->
+<!-- spi_lcd&#45;&gt;lcd -->
 <g id="edge50" class="edge">
-<title>spi_1:cs_2&#45;&gt;lcd:dc</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-325C462.83,-325 553.01,-445.61 930.98,-447.97"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-451.46 940.74,-448 930.75,-444.46 930.73,-451.46"/>
+<title>spi_lcd:cs_2&#45;&gt;lcd:rst</title>
+<path fill="none" stroke="dodgerblue" d="M84.12,-315C468.3,-315 552.65,-471.89 930.97,-474.95"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="930.72,-478.45 940.74,-474.99 930.75,-471.45 930.72,-478.45"/>
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-<!-- spi_1&#45;&gt;lcd -->
-<g id="edge51" class="edge">
-<title>spi_1:cs_3&#45;&gt;lcd:backlight</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-300C462.7,-300 553.13,-418.65 930.99,-420.97"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="930.73,-424.46 940.74,-421 930.75,-417.46 930.73,-424.46"/>
-</g>
-<!-- spi_2 -->
+<!-- spi_0 -->
 <g id="node8" class="node">
-<title>spi_2</title>
-<path fill="none" stroke="black" d="M36.12,-798C36.12,-798 66.12,-798 66.12,-798 72.12,-798 78.12,-804 78.12,-810 78.12,-810 78.12,-988 78.12,-988 78.12,-994 72.12,-1000 66.12,-1000 66.12,-1000 36.12,-1000 36.12,-1000 30.12,-1000 24.12,-994 24.12,-988 24.12,-988 24.12,-810 24.12,-810 24.12,-804 30.12,-798 36.12,-798"/>
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-<polyline fill="none" stroke="black" points="24.12,-974.75 78.12,-974.75"/>
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-<polyline fill="none" stroke="black" points="24.12,-949.5 78.12,-949.5"/>
-<text text-anchor="middle" x="51.12" y="-932.2" font-family="Times,serif" font-size="14.00">cipo</text>
-<polyline fill="none" stroke="black" points="24.12,-924.25 78.12,-924.25"/>
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-<polyline fill="none" stroke="black" points="24.12,-899 78.12,-899"/>
-<text text-anchor="middle" x="51.12" y="-881.7" font-family="Times,serif" font-size="14.00">cs_0</text>
-<polyline fill="none" stroke="black" points="24.12,-873.75 78.12,-873.75"/>
-<text text-anchor="middle" x="51.12" y="-856.45" font-family="Times,serif" font-size="14.00">cs_1</text>
-<polyline fill="none" stroke="black" points="24.12,-848.5 78.12,-848.5"/>
-<text text-anchor="middle" x="51.12" y="-831.2" font-family="Times,serif" font-size="14.00">cs_2</text>
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-<text text-anchor="middle" x="51.12" y="-805.95" font-family="Times,serif" font-size="14.00">cs_3</text>
-</g>
-<!-- spi_2&#45;&gt;rph -->
-<g id="edge58" class="edge">
-<title>spi_2:copi&#45;&gt;rph:g10_spi0_copi</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-962C728.17,-962 182.85,-2210.24 817.9,-2224.87"/>
+<title>spi_0</title>
+<path fill="none" stroke="black" d="M36.12,-789C36.12,-789 66.12,-789 66.12,-789 72.12,-789 78.12,-795 78.12,-801 78.12,-801 78.12,-979 78.12,-979 78.12,-985 72.12,-991 66.12,-991 66.12,-991 36.12,-991 36.12,-991 30.12,-991 24.12,-985 24.12,-979 24.12,-979 24.12,-801 24.12,-801 24.12,-795 30.12,-789 36.12,-789"/>
+<text text-anchor="middle" x="51.12" y="-973.7" font-family="Times,serif" font-size="14.00">spi_0</text>
+<polyline fill="none" stroke="black" points="24.12,-965.75 78.12,-965.75"/>
+<text text-anchor="middle" x="51.12" y="-948.45" font-family="Times,serif" font-size="14.00">copi</text>
+<polyline fill="none" stroke="black" points="24.12,-940.5 78.12,-940.5"/>
+<text text-anchor="middle" x="51.12" y="-923.2" font-family="Times,serif" font-size="14.00">cipo</text>
+<polyline fill="none" stroke="black" points="24.12,-915.25 78.12,-915.25"/>
+<text text-anchor="middle" x="51.12" y="-897.95" font-family="Times,serif" font-size="14.00">sclk</text>
+<polyline fill="none" stroke="black" points="24.12,-890 78.12,-890"/>
+<text text-anchor="middle" x="51.12" y="-872.7" font-family="Times,serif" font-size="14.00">cs_0</text>
+<polyline fill="none" stroke="black" points="24.12,-864.75 78.12,-864.75"/>
+<text text-anchor="middle" x="51.12" y="-847.45" font-family="Times,serif" font-size="14.00">cs_1</text>
+<polyline fill="none" stroke="black" points="24.12,-839.5 78.12,-839.5"/>
+<text text-anchor="middle" x="51.12" y="-822.2" font-family="Times,serif" font-size="14.00">cs_2</text>
+<polyline fill="none" stroke="black" points="24.12,-814.25 78.12,-814.25"/>
+<text text-anchor="middle" x="51.12" y="-796.95" font-family="Times,serif" font-size="14.00">cs_3</text>
+</g>
+<!-- spi_0&#45;&gt;rph -->
+<g id="edge57" class="edge">
+<title>spi_0:copi&#45;&gt;rph:g10_spi0_copi</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-953C731.59,-953 179.48,-2210.14 817.84,-2224.87"/>
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-<!-- spi_2&#45;&gt;rph -->
+<!-- spi_0&#45;&gt;rph -->
+<g id="edge58" class="edge">
+<title>spi_0:cipo&#45;&gt;rph:g9_spi0_cipo</title>
+<path fill="none" stroke="dodgerblue" d="M90.4,-928.12C748.72,-942.83 156.72,-2252 829.25,-2252"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="90.68,-924.63 80.64,-928.02 90.6,-931.63 90.68,-924.63"/>
+</g>
+<!-- spi_0&#45;&gt;rph -->
 <g id="edge59" class="edge">
-<title>spi_2:cipo&#45;&gt;rph:g9_spi0_cipo</title>
-<path fill="none" stroke="dodgerblue" d="M90.34,-937.12C745.32,-951.73 160.18,-2252 829.25,-2252"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.68,-933.63 80.64,-937.02 90.6,-940.63 90.68,-933.63"/>
+<title>spi_0:sclk&#45;&gt;rph:g11_spi0_sclk</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-903C740.53,-903 170.59,-2183.5 818.16,-2197.88"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.7,-2201.37 827.74,-2197.98 817.78,-2194.37 817.7,-2201.37"/>
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-<!-- spi_2&#45;&gt;rph -->
+<!-- spi_0&#45;&gt;rph -->
 <g id="edge60" class="edge">
-<title>spi_2:sclk&#45;&gt;rph:g11_spi0_sclk</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-912C736.93,-912 174.24,-2182.97 817.75,-2197.87"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.7,-2201.37 827.74,-2197.98 817.78,-2194.37 817.7,-2201.37"/>
+<title>spi_0:cs_0&#45;&gt;rph:g7_spi0_ce0</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-877C792.57,-877 119.27,-2290.69 817.81,-2305.88"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.7,-2309.38 827.74,-2305.98 817.77,-2302.38 817.7,-2309.38"/>
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-<!-- spi_2&#45;&gt;rph -->
+<!-- spi_0&#45;&gt;rph -->
 <g id="edge61" class="edge">
-<title>spi_2:cs_0&#45;&gt;rph:g7_spi0_ce0</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-886C789.05,-886 122.73,-2290.79 817.87,-2305.88"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.7,-2309.38 827.74,-2305.98 817.77,-2302.38 817.7,-2309.38"/>
+<title>spi_0:cs_1&#45;&gt;rph:g8_spi0_ce1</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-852C791.79,-852 120.04,-2263.71 817.83,-2278.88"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.7,-2282.38 827.74,-2278.98 817.77,-2275.38 817.7,-2282.38"/>
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-<!-- spi_2&#45;&gt;rph -->
+<!-- spi_0&#45;&gt;ah -->
 <g id="edge62" class="edge">
-<title>spi_2:cs_1&#45;&gt;rph:g8_spi0_ce1</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-861C788.27,-861 123.5,-2263.81 817.88,-2278.88"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.7,-2282.38 827.74,-2278.98 817.77,-2275.38 817.7,-2282.38"/>
+<title>spi_0:copi&#45;&gt;ah:tmpio11</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-953C600.09,-953 343.27,-83.87 852.84,-71.14"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="852.78,-74.64 862.74,-71.02 852.69,-67.64 852.78,-74.64"/>
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-<!-- spi_2&#45;&gt;ah -->
+<!-- spi_0&#45;&gt;ah -->
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-<title>spi_2:copi&#45;&gt;ah:tmpio11</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-962C603.06,-962 340.36,-84 852.78,-71.14"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="852.78,-74.64 862.74,-71.02 852.69,-67.64 852.78,-74.64"/>
+<title>spi_0:cipo&#45;&gt;ah:tmpio12</title>
+<path fill="none" stroke="dodgerblue" d="M90.54,-927.86C600.75,-915.1 342.62,-44 864.25,-44"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="90.59,-924.36 80.64,-927.98 90.68,-931.36 90.59,-924.36"/>
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-<!-- spi_2&#45;&gt;ah -->
+<!-- spi_0&#45;&gt;ah -->
 <g id="edge64" class="edge">
-<title>spi_2:cipo&#45;&gt;ah:tmpio12</title>
-<path fill="none" stroke="dodgerblue" d="M90.61,-936.86C603.66,-923.97 339.65,-44 864.25,-44"/>
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-<!-- spi_2&#45;&gt;ah -->
-<g id="edge65" class="edge">
-<title>spi_2:sclk&#45;&gt;ah:tmpio13</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-912C604.39,-912 339.07,-30.06 852.75,-17.14"/>
+<title>spi_0:sclk&#45;&gt;ah:tmpio13</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-903C601.41,-903 341.98,-29.93 852.82,-17.14"/>
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-<!-- spi_2&#45;&gt;ah -->
-<g id="edge66" class="edge">
-<title>spi_2:cs_3&#45;&gt;ah:tmpio10</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-811C546.69,-811 395.39,-109.44 852.98,-98.14"/>
+<!-- spi_0&#45;&gt;ah -->
+<g id="edge65" class="edge">
+<title>spi_0:cs_3&#45;&gt;ah:tmpio10</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-802C544.03,-802 397.98,-109.3 853.04,-98.14"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="852.78,-101.64 862.74,-98.02 852.69,-94.64 852.78,-101.64"/>
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-<!-- spi_2&#45;&gt;pmod0 -->
-<g id="edge52" class="edge">
-<title>spi_2:copi&#45;&gt;pmod0:2</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-962C421.48,-962 486.79,-776.06 823.19,-772.07"/>
+<!-- spi_0&#45;&gt;pmod0 -->
+<g id="edge51" class="edge">
+<title>spi_0:copi&#45;&gt;pmod0:2</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-953C420.54,-953 487.71,-775.87 823.22,-772.06"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="822.76,-775.57 832.74,-772.01 822.72,-768.57 822.76,-775.57"/>
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-<!-- spi_2&#45;&gt;pmod0 -->
-<g id="edge53" class="edge">
-<title>spi_2:cipo&#45;&gt;pmod0:3</title>
-<path fill="none" stroke="dodgerblue" d="M90.19,-936.93C426.79,-932.9 491.68,-745 834.25,-745"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.62,-933.43 80.64,-936.99 90.66,-940.43 90.62,-933.43"/>
+<!-- spi_0&#45;&gt;pmod0 -->
+<g id="edge52" class="edge">
+<title>spi_0:cipo&#45;&gt;pmod0:3</title>
+<path fill="none" stroke="dodgerblue" d="M90.16,-927.94C425.87,-924.09 492.63,-745 834.25,-745"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="90.62,-924.43 80.64,-927.99 90.66,-931.43 90.62,-924.43"/>
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-<!-- spi_2&#45;&gt;pmod0 -->
-<g id="edge54" class="edge">
-<title>spi_2:sclk&#45;&gt;pmod0:4</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-912C421.91,-912 486.37,-722.15 823.18,-718.07"/>
+<!-- spi_0&#45;&gt;pmod0 -->
+<g id="edge53" class="edge">
+<title>spi_0:sclk&#45;&gt;pmod0:4</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-903C420.95,-903 487.31,-721.95 823.21,-718.06"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="822.76,-721.57 832.74,-718.01 822.72,-714.57 822.76,-721.57"/>
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-<!-- spi_2&#45;&gt;pmod0 -->
-<g id="edge55" class="edge">
-<title>spi_2:cs_0&#45;&gt;pmod0:1</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-886C413.16,-886 494.6,-800.94 822.97,-799.03"/>
+<!-- spi_0&#45;&gt;pmod0 -->
+<g id="edge54" class="edge">
+<title>spi_0:cs_0&#45;&gt;pmod0:1</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-877C412.73,-877 495.02,-800.74 822.98,-799.03"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="822.75,-802.53 832.74,-799 822.73,-795.53 822.75,-802.53"/>
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-<!-- spi_2&#45;&gt;pmod0 -->
-<g id="edge56" class="edge">
-<title>spi_2:cs_1&#45;&gt;pmod0:7</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-861C425.47,-861 482.82,-640.92 822.81,-636.08"/>
+<!-- spi_0&#45;&gt;pmod0 -->
+<g id="edge55" class="edge">
+<title>spi_0:cs_1&#45;&gt;pmod0:7</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-852C424.36,-852 483.89,-640.72 822.85,-636.08"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="822.76,-639.58 832.74,-636.01 822.71,-632.58 822.76,-639.58"/>
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-<!-- spi_2&#45;&gt;pmod0 -->
-<g id="edge57" class="edge">
-<title>spi_2:cs_2&#45;&gt;pmod0:8</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-836C425.72,-836 482.58,-613.96 822.81,-609.08"/>
+<!-- spi_0&#45;&gt;pmod0 -->
+<g id="edge56" class="edge">
+<title>spi_0:cs_2&#45;&gt;pmod0:8</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-827C424.6,-827 483.66,-613.76 822.84,-609.08"/>
 <polygon fill="dodgerblue" stroke="dodgerblue" points="822.76,-612.58 832.74,-609.01 822.71,-605.58 822.76,-612.58"/>
 </g>
-<!-- spi_3 -->
+<!-- spi_1 -->
 <g id="node9" class="node">
-<title>spi_3</title>
-<path fill="none" stroke="black" d="M36.12,-1183C36.12,-1183 66.12,-1183 66.12,-1183 72.12,-1183 78.12,-1189 78.12,-1195 78.12,-1195 78.12,-1373 78.12,-1373 78.12,-1379 72.12,-1385 66.12,-1385 66.12,-1385 36.12,-1385 36.12,-1385 30.12,-1385 24.12,-1379 24.12,-1373 24.12,-1373 24.12,-1195 24.12,-1195 24.12,-1189 30.12,-1183 36.12,-1183"/>
-<text text-anchor="middle" x="51.12" y="-1367.7" font-family="Times,serif" font-size="14.00">spi_3</text>
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-<text text-anchor="middle" x="51.12" y="-1342.45" font-family="Times,serif" font-size="14.00">copi</text>
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-<text text-anchor="middle" x="51.12" y="-1317.2" font-family="Times,serif" font-size="14.00">cipo</text>
-<polyline fill="none" stroke="black" points="24.12,-1309.25 78.12,-1309.25"/>
-<text text-anchor="middle" x="51.12" y="-1291.95" font-family="Times,serif" font-size="14.00">sclk</text>
-<polyline fill="none" stroke="black" points="24.12,-1284 78.12,-1284"/>
-<text text-anchor="middle" x="51.12" y="-1266.7" font-family="Times,serif" font-size="14.00">cs_0</text>
-<polyline fill="none" stroke="black" points="24.12,-1258.75 78.12,-1258.75"/>
-<text text-anchor="middle" x="51.12" y="-1241.45" font-family="Times,serif" font-size="14.00">cs_1</text>
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-<text text-anchor="middle" x="51.12" y="-1216.2" font-family="Times,serif" font-size="14.00">cs_2</text>
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-<text text-anchor="middle" x="51.12" y="-1190.95" font-family="Times,serif" font-size="14.00">cs_3</text>
-</g>
-<!-- spi_3&#45;&gt;rph -->
-<g id="edge73" class="edge">
-<title>spi_3:copi&#45;&gt;rph:g20_spi1_copi</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1347C504.12,-1347 402.28,-1943.08 817.76,-1953.85"/>
+<title>spi_1</title>
+<path fill="none" stroke="black" d="M36.12,-1174C36.12,-1174 66.12,-1174 66.12,-1174 72.12,-1174 78.12,-1180 78.12,-1186 78.12,-1186 78.12,-1364 78.12,-1364 78.12,-1370 72.12,-1376 66.12,-1376 66.12,-1376 36.12,-1376 36.12,-1376 30.12,-1376 24.12,-1370 24.12,-1364 24.12,-1364 24.12,-1186 24.12,-1186 24.12,-1180 30.12,-1174 36.12,-1174"/>
+<text text-anchor="middle" x="51.12" y="-1358.7" font-family="Times,serif" font-size="14.00">spi_1</text>
+<polyline fill="none" stroke="black" points="24.12,-1350.75 78.12,-1350.75"/>
+<text text-anchor="middle" x="51.12" y="-1333.45" font-family="Times,serif" font-size="14.00">copi</text>
+<polyline fill="none" stroke="black" points="24.12,-1325.5 78.12,-1325.5"/>
+<text text-anchor="middle" x="51.12" y="-1308.2" font-family="Times,serif" font-size="14.00">cipo</text>
+<polyline fill="none" stroke="black" points="24.12,-1300.25 78.12,-1300.25"/>
+<text text-anchor="middle" x="51.12" y="-1282.95" font-family="Times,serif" font-size="14.00">sclk</text>
+<polyline fill="none" stroke="black" points="24.12,-1275 78.12,-1275"/>
+<text text-anchor="middle" x="51.12" y="-1257.7" font-family="Times,serif" font-size="14.00">cs_0</text>
+<polyline fill="none" stroke="black" points="24.12,-1249.75 78.12,-1249.75"/>
+<text text-anchor="middle" x="51.12" y="-1232.45" font-family="Times,serif" font-size="14.00">cs_1</text>
+<polyline fill="none" stroke="black" points="24.12,-1224.5 78.12,-1224.5"/>
+<text text-anchor="middle" x="51.12" y="-1207.2" font-family="Times,serif" font-size="14.00">cs_2</text>
+<polyline fill="none" stroke="black" points="24.12,-1199.25 78.12,-1199.25"/>
+<text text-anchor="middle" x="51.12" y="-1181.95" font-family="Times,serif" font-size="14.00">cs_3</text>
+</g>
+<!-- spi_1&#45;&gt;rph -->
+<g id="edge72" class="edge">
+<title>spi_1:copi&#45;&gt;rph:g20_spi1_copi</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1338C506.73,-1338 399.79,-1943.22 818,-1953.86"/>
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-<!-- spi_3&#45;&gt;rph -->
+<!-- spi_1&#45;&gt;rph -->
+<g id="edge73" class="edge">
+<title>spi_1:cipo&#45;&gt;rph:g19_spi1_cipo</title>
+<path fill="none" stroke="dodgerblue" d="M90.44,-1313.15C523.15,-1324.37 386.64,-1981 829.25,-1981"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="90.68,-1309.65 80.64,-1313.02 90.59,-1316.65 90.68,-1309.65"/>
+</g>
+<!-- spi_1&#45;&gt;rph -->
 <g id="edge74" class="edge">
-<title>spi_3:cipo&#45;&gt;rph:g19_spi1_cipo</title>
-<path fill="none" stroke="dodgerblue" d="M90.37,-1322.14C520.59,-1333.21 389.27,-1981 829.25,-1981"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.68,-1318.65 80.64,-1322.02 90.59,-1325.65 90.68,-1318.65"/>
+<title>spi_1:sclk&#45;&gt;rph:g21_spi1_sclk</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1288C513.23,-1288 393.46,-1915.82 817.83,-1926.85"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-1930.35 827.74,-1926.98 817.78,-1923.35 817.69,-1930.35"/>
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-<!-- spi_3&#45;&gt;rph -->
+<!-- spi_1&#45;&gt;rph -->
 <g id="edge75" class="edge">
-<title>spi_3:sclk&#45;&gt;rph:g21_spi1_sclk</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1297C510.67,-1297 395.96,-1915.97 817.9,-1926.85"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-1930.35 827.74,-1926.98 817.78,-1923.35 817.69,-1930.35"/>
+<title>spi_1:cs_0&#45;&gt;rph:g18_spi1_ce0</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1262C545.53,-1262 362.08,-1996.03 818.01,-2007.86"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-2011.35 827.74,-2007.98 817.78,-2004.35 817.69,-2011.35"/>
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-<!-- spi_3&#45;&gt;rph -->
+<!-- spi_1&#45;&gt;rph -->
 <g id="edge76" class="edge">
-<title>spi_3:cs_0&#45;&gt;rph:g18_spi1_ce0</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1271C542.62,-1271 364.89,-1995.82 817.75,-2007.85"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-2011.35 827.74,-2007.98 817.78,-2004.35 817.69,-2011.35"/>
+<title>spi_1:cs_1&#45;&gt;rph:g17_spi1_ce1</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1237C562.08,-1237 345.94,-2022.58 817.97,-2034.85"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-2038.35 827.74,-2034.98 817.78,-2031.35 817.69,-2038.35"/>
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-<!-- spi_3&#45;&gt;rph -->
+<!-- spi_1&#45;&gt;rph -->
 <g id="edge77" class="edge">
-<title>spi_3:cs_1&#45;&gt;rph:g17_spi1_ce1</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1246C559.2,-1246 348.75,-2022.72 818.04,-2034.86"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-2038.35 827.74,-2034.98 817.78,-2031.35 817.69,-2038.35"/>
+<title>spi_1:cs_2&#45;&gt;rph:g16_spi1_ce2</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1212C579.16,-1212 329.26,-2049.18 817.94,-2061.85"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-2065.35 827.74,-2061.98 817.78,-2058.35 817.69,-2065.35"/>
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-<!-- spi_3&#45;&gt;rph -->
+<!-- spi_1&#45;&gt;mb -->
 <g id="edge78" class="edge">
-<title>spi_3:cs_2&#45;&gt;rph:g16_spi1_ce2</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1221C576.19,-1221 332.16,-2049.32 818.01,-2061.86"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="817.69,-2065.35 827.74,-2061.98 817.78,-2058.35 817.69,-2065.35"/>
+<title>spi_1:copi&#45;&gt;mb:4</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1338C450.88,-1338 542.77,-1257.67 908.79,-1256.03"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="908.74,-1259.53 918.74,-1256 908.73,-1252.53 908.74,-1259.53"/>
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-<!-- spi_3&#45;&gt;mb -->
+<!-- spi_1&#45;&gt;mb -->
 <g id="edge79" class="edge">
-<title>spi_3:copi&#45;&gt;mb:4</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1347C451.28,-1347 542.38,-1257.86 908.77,-1256.03"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="908.75,-1259.53 918.74,-1256 908.73,-1252.53 908.75,-1259.53"/>
+<title>spi_1:cipo&#45;&gt;mb:3</title>
+<path fill="none" stroke="dodgerblue" d="M90.54,-1312.99C455.13,-1312.39 550.01,-1283 920.25,-1283"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="90.64,-1309.49 80.64,-1313 90.64,-1316.49 90.64,-1309.49"/>
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-<!-- spi_3&#45;&gt;mb -->
+<!-- spi_1&#45;&gt;mb -->
 <g id="edge80" class="edge">
-<title>spi_3:cipo&#45;&gt;mb:3</title>
-<path fill="none" stroke="dodgerblue" d="M90.55,-1321.99C455.29,-1321.2 549.85,-1283 920.25,-1283"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.63,-1318.49 80.64,-1322 90.64,-1325.49 90.63,-1318.49"/>
+<title>spi_1:sclk&#45;&gt;mb:2</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1288C449.25,-1288 544.35,-1309.55 908.83,-1309.99"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="908.73,-1313.49 918.74,-1310 908.74,-1306.49 908.73,-1313.49"/>
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-<!-- spi_3&#45;&gt;mb -->
+<!-- spi_1&#45;&gt;mb -->
 <g id="edge81" class="edge">
-<title>spi_3:sclk&#45;&gt;mb:2</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1297C449.17,-1297 544.43,-1309.73 908.84,-1310"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="908.74,-1313.5 918.74,-1310 908.74,-1306.5 908.74,-1313.5"/>
+<title>spi_1:cs_3&#45;&gt;mb:1</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1187C455.06,-1187 538.85,-1334.01 908.94,-1336.96"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="908.72,-1340.45 918.74,-1336.99 908.75,-1333.45 908.72,-1340.45"/>
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-<!-- spi_3&#45;&gt;mb -->
-<g id="edge82" class="edge">
-<title>spi_3:cs_3&#45;&gt;mb:1</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1196C454.38,-1196 539.51,-1334.19 908.96,-1336.96"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="908.72,-1340.46 918.74,-1336.99 908.75,-1333.46 908.72,-1340.46"/>
+<!-- spi_1&#45;&gt;pmod1 -->
+<g id="edge66" class="edge">
+<title>spi_1:copi&#45;&gt;pmod1:2</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1338C440.49,-1338 468.49,-1020.77 822.86,-1014.11"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-1017.61 832.74,-1014.01 822.7,-1010.61 822.77,-1017.61"/>
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-<!-- spi_3&#45;&gt;pmod1 -->
+<!-- spi_1&#45;&gt;pmod1 -->
 <g id="edge67" class="edge">
-<title>spi_3:copi&#45;&gt;pmod1:2</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1347C442.07,-1347 466.96,-1020.95 822.81,-1014.11"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-1017.61 832.74,-1014.01 822.7,-1010.61 822.77,-1017.61"/>
+<title>spi_1:cipo&#45;&gt;pmod1:3</title>
+<path fill="none" stroke="dodgerblue" d="M90.53,-1312.89C445.22,-1306.19 472.54,-987 834.25,-987"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="90.61,-1309.39 80.64,-1312.99 90.67,-1316.39 90.61,-1309.39"/>
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-<!-- spi_3&#45;&gt;pmod1 -->
+<!-- spi_1&#45;&gt;pmod1 -->
 <g id="edge68" class="edge">
-<title>spi_3:cipo&#45;&gt;pmod1:3</title>
-<path fill="none" stroke="dodgerblue" d="M90.57,-1321.89C446.76,-1315 470.95,-987 834.25,-987"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="90.6,-1318.39 80.64,-1321.99 90.67,-1325.39 90.6,-1318.39"/>
+<title>spi_1:sclk&#45;&gt;pmod1:4</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1288C441.19,-1288 467.82,-966.85 822.84,-960.11"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-963.61 832.74,-960.01 822.7,-956.61 822.77,-963.61"/>
 </g>
-<!-- spi_3&#45;&gt;pmod1 -->
+<!-- spi_1&#45;&gt;pmod1 -->
 <g id="edge69" class="edge">
-<title>spi_3:sclk&#45;&gt;pmod1:4</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1297C442.78,-1297 466.27,-967.04 822.79,-960.11"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-963.61 832.74,-960.01 822.7,-956.61 822.77,-963.61"/>
+<title>spi_1:cs_0&#45;&gt;pmod1:1</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1262C424.97,-1262 483.3,-1045.83 822.83,-1041.08"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="822.76,-1044.58 832.74,-1041.01 822.71,-1037.58 822.76,-1044.58"/>
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-<!-- spi_3&#45;&gt;pmod1 -->
+<!-- spi_1&#45;&gt;pmod1 -->
 <g id="edge70" class="edge">
-<title>spi_3:cs_0&#45;&gt;pmod1:1</title>
-<path fill="none" stroke="dodgerblue" d="M79.12,-1271C426.1,-1271 482.21,-1046.03 822.79,-1041.08"/>
-<polygon fill="dodgerblue" stroke="dodgerblue" points="822.76,-1044.58 832.74,-1041.01 822.71,-1037.58 822.76,-1044.58"/>
+<title>spi_1:cs_1&#45;&gt;pmod1:7</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1237C446.92,-1237 462.36,-885.32 822.93,-878.11"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-881.61 832.74,-878.02 822.7,-874.61 822.77,-881.61"/>
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-<!-- spi_3&#45;&gt;pmod1 -->
+<!-- spi_1&#45;&gt;pmod1 -->
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-<title>spi_3:cs_1&#45;&gt;pmod1:7</title>
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-<!-- spi_3&#45;&gt;pmod1 -->
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-<title>spi_3:cs_2&#45;&gt;pmod1:8</title>
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-<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-854.62 832.74,-851.02 822.7,-847.62 822.77,-854.62"/>
+<title>spi_1:cs_2&#45;&gt;pmod1:8</title>
+<path fill="none" stroke="dodgerblue" d="M79.12,-1212C447.3,-1212 461.99,-858.37 822.92,-851.11"/>
+<polygon fill="dodgerblue" stroke="dodgerblue" points="822.77,-854.61 832.74,-851.02 822.7,-847.62 822.77,-854.61"/>
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 <text text-anchor="start" x="984.5" y="-2542.7" font-family="Times,serif" font-size="14.00">gpi</text>
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-<g id="edge101" class="edge">
+<g id="edge100" class="edge">
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-<g id="edge102" class="edge">
+<g id="edge101" class="edge">
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 <!-- gpio_board&#45;&gt;usr -->
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+<g id="edge102" class="edge">
 <title>gpio_board:gpi_8&#45;12&#45;&gt;usr:navsw_0&#45;4</title>
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 <!-- gpio_board&#45;&gt;usr -->
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+<g id="edge103" class="edge">
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 <!-- gpio_board&#45;&gt;microsd -->
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+<g id="edge104" class="edge">
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+<g id="edge105" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g0</title>
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+<g id="edge106" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g1</title>
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 <!-- gpio_rph&#45;&gt;rph -->
-<g id="edge108" class="edge">
+<g id="edge107" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g2_sda</title>
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+<g id="edge108" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g3_scl</title>
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+<g id="edge109" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g4</title>
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+<g id="edge110" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g5</title>
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+<g id="edge111" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g6</title>
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+<g id="edge112" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g7_spi0_ce0</title>
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+<g id="edge113" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g8_spi0_ce1</title>
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+<g id="edge114" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g9_spi0_cipo</title>
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+<g id="edge115" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g10_spi0_copi</title>
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+<g id="edge116" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g11_spi0_sclk</title>
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+<g id="edge117" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g12</title>
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+<g id="edge118" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g13</title>
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 <!-- gpio_rph&#45;&gt;rph -->
-<g id="edge120" class="edge">
+<g id="edge119" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:txd0</title>
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 <!-- gpio_rph&#45;&gt;rph -->
-<g id="edge121" class="edge">
+<g id="edge120" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:rxd0</title>
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-<g id="edge122" class="edge">
+<g id="edge121" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g16_spi1_ce2</title>
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+<g id="edge122" class="edge">
 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g17_spi1_ce1</title>
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+<g id="edge123" class="edge">
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+<g id="edge124" class="edge">
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 <title>gpio_rph:gpio_0&#45;27&#45;&gt;rph:g20_spi1_copi</title>
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+<g id="edge126" class="edge">
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+<g id="edge127" class="edge">
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+<g id="edge128" class="edge">
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+<g id="edge129" class="edge">
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+<g id="edge130" class="edge">
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+<g id="edge131" class="edge">
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+<g id="edge132" class="edge">
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 <title>gpio_ah:gpio_0&#45;13&#45;&gt;ah:tmpio9</title>
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 <title>gpio_ah:gpio_0&#45;13&#45;&gt;ah:tmpio10</title>
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 <title>gpio_ah:gpio_0&#45;13&#45;&gt;ah:tmpio11</title>
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 <title>gpio_ah:gpio_0&#45;13&#45;&gt;ah:tmpio12</title>
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 <title>gpio_ah:gpio_0&#45;13&#45;&gt;ah:tmpio13</title>
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@@ -1505,66 +1497,66 @@
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 <title>gpio_pmod0</title>
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+<polyline fill="none" stroke="black" points="0,-524 102.25,-524"/>
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 <title>gpio_pmodc:gpio_0&#45;5&#45;&gt;pmodc:1</title>
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 <title>gpio_pmodc:gpio_0&#45;5&#45;&gt;pmodc:3</title>
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 <title>gpio_pmodc:gpio_0&#45;5&#45;&gt;pmodc:4</title>
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 <title>gpio_pmodc:gpio_0&#45;5&#45;&gt;pmodc:5</title>
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 <title>gpio_pmodc:gpio_0&#45;5&#45;&gt;pmodc:6</title>
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@@ -1649,194 +1641,194 @@
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 <g id="node16" class="node">
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 <!-- pwm&#45;&gt;rph -->
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+<path fill="none" stroke="hotpink" d="M79.12,-631C432.31,-631 476.31,-899.14 822.85,-904.91"/>
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From 248a8515f3e44ff266823d4e0e80f45b2623767c Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Fri, 1 Nov 2024 11:03:40 +0000
Subject: [PATCH 07/21] pinmux: removed block inputs with no input options.

This removes blocks that have no options from the register map
---
 doc/ip/pinmux/README.md            |  140 +-
 rtl/system/pinmux.sv               | 2790 ++--------------------------
 rtl/templates/pinmux.sv.tpl        |    3 -
 sw/cheri/common/platform-pinmux.hh |  140 +-
 util/top_gen/generator.py          |    3 +
 5 files changed, 278 insertions(+), 2798 deletions(-)

diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index 605b78628..b6ae95fe5 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -117,111 +117,41 @@ Besides the output pin selectors, there are also selectors for which pin should
 | 0x819 | `gpio[0].ios[25]` | 0, `rph_g25` |
 | 0x81a | `gpio[0].ios[26]` | 0, `rph_g26` |
 | 0x81b | `gpio[0].ios[27]` | 0, `rph_g27` |
-| 0x81c | `gpio[0].ios[28]` | 0, 0 |
-| 0x81d | `gpio[0].ios[29]` | 0, 0 |
-| 0x81e | `gpio[0].ios[30]` | 0, 0 |
-| 0x81f | `gpio[0].ios[31]` | 0, 0 |
-| 0x820 | `gpio[1].ios[0]` | 0, `ah_tmpio0` |
-| 0x821 | `gpio[1].ios[1]` | 0, `ah_tmpio1` |
-| 0x822 | `gpio[1].ios[2]` | 0, `ah_tmpio2` |
-| 0x823 | `gpio[1].ios[3]` | 0, `ah_tmpio3` |
-| 0x824 | `gpio[1].ios[4]` | 0, `ah_tmpio4` |
-| 0x825 | `gpio[1].ios[5]` | 0, `ah_tmpio5` |
-| 0x826 | `gpio[1].ios[6]` | 0, `ah_tmpio6` |
-| 0x827 | `gpio[1].ios[7]` | 0, `ah_tmpio7` |
-| 0x828 | `gpio[1].ios[8]` | 0, `ah_tmpio8` |
-| 0x829 | `gpio[1].ios[9]` | 0, `ah_tmpio9` |
-| 0x82a | `gpio[1].ios[10]` | 0, `ah_tmpio10` |
-| 0x82b | `gpio[1].ios[11]` | 0, `ah_tmpio11` |
-| 0x82c | `gpio[1].ios[12]` | 0, `ah_tmpio12` |
-| 0x82d | `gpio[1].ios[13]` | 0, `ah_tmpio13` |
-| 0x82e | `gpio[1].ios[14]` | 0, 0 |
-| 0x82f | `gpio[1].ios[15]` | 0, 0 |
-| 0x830 | `gpio[1].ios[16]` | 0, 0 |
-| 0x831 | `gpio[1].ios[17]` | 0, 0 |
-| 0x832 | `gpio[1].ios[18]` | 0, 0 |
-| 0x833 | `gpio[1].ios[19]` | 0, 0 |
-| 0x834 | `gpio[1].ios[20]` | 0, 0 |
-| 0x835 | `gpio[1].ios[21]` | 0, 0 |
-| 0x836 | `gpio[1].ios[22]` | 0, 0 |
-| 0x837 | `gpio[1].ios[23]` | 0, 0 |
-| 0x838 | `gpio[1].ios[24]` | 0, 0 |
-| 0x839 | `gpio[1].ios[25]` | 0, 0 |
-| 0x83a | `gpio[1].ios[26]` | 0, 0 |
-| 0x83b | `gpio[1].ios[27]` | 0, 0 |
-| 0x83c | `gpio[1].ios[28]` | 0, 0 |
-| 0x83d | `gpio[1].ios[29]` | 0, 0 |
-| 0x83e | `gpio[1].ios[30]` | 0, 0 |
-| 0x83f | `gpio[1].ios[31]` | 0, 0 |
-| 0x840 | `gpio[2].ios[0]` | 0, `pmod0_1` |
-| 0x841 | `gpio[2].ios[1]` | 0, `pmod0_2` |
-| 0x842 | `gpio[2].ios[2]` | 0, `pmod0_3` |
-| 0x843 | `gpio[2].ios[3]` | 0, `pmod0_4` |
-| 0x844 | `gpio[2].ios[4]` | 0, `pmod0_5` |
-| 0x845 | `gpio[2].ios[5]` | 0, `pmod0_6` |
-| 0x846 | `gpio[2].ios[6]` | 0, `pmod0_7` |
-| 0x847 | `gpio[2].ios[7]` | 0, `pmod0_8` |
-| 0x848 | `gpio[2].ios[8]` | 0, 0 |
-| 0x849 | `gpio[2].ios[9]` | 0, 0 |
-| 0x84a | `gpio[2].ios[10]` | 0, 0 |
-| 0x84b | `gpio[2].ios[11]` | 0, 0 |
-| 0x84c | `gpio[2].ios[12]` | 0, 0 |
-| 0x84d | `gpio[2].ios[13]` | 0, 0 |
-| 0x84e | `gpio[2].ios[14]` | 0, 0 |
-| 0x84f | `gpio[2].ios[15]` | 0, 0 |
-| 0x850 | `gpio[2].ios[16]` | 0, 0 |
-| 0x851 | `gpio[2].ios[17]` | 0, 0 |
-| 0x852 | `gpio[2].ios[18]` | 0, 0 |
-| 0x853 | `gpio[2].ios[19]` | 0, 0 |
-| 0x854 | `gpio[2].ios[20]` | 0, 0 |
-| 0x855 | `gpio[2].ios[21]` | 0, 0 |
-| 0x856 | `gpio[2].ios[22]` | 0, 0 |
-| 0x857 | `gpio[2].ios[23]` | 0, 0 |
-| 0x858 | `gpio[2].ios[24]` | 0, 0 |
-| 0x859 | `gpio[2].ios[25]` | 0, 0 |
-| 0x85a | `gpio[2].ios[26]` | 0, 0 |
-| 0x85b | `gpio[2].ios[27]` | 0, 0 |
-| 0x85c | `gpio[2].ios[28]` | 0, 0 |
-| 0x85d | `gpio[2].ios[29]` | 0, 0 |
-| 0x85e | `gpio[2].ios[30]` | 0, 0 |
-| 0x85f | `gpio[2].ios[31]` | 0, 0 |
-| 0x860 | `gpio[3].ios[0]` | 0, `pmod1_1` |
-| 0x861 | `gpio[3].ios[1]` | 0, `pmod1_2` |
-| 0x862 | `gpio[3].ios[2]` | 0, `pmod1_3` |
-| 0x863 | `gpio[3].ios[3]` | 0, `pmod1_4` |
-| 0x864 | `gpio[3].ios[4]` | 0, `pmod1_5` |
-| 0x865 | `gpio[3].ios[5]` | 0, `pmod1_6` |
-| 0x866 | `gpio[3].ios[6]` | 0, `pmod1_7` |
-| 0x867 | `gpio[3].ios[7]` | 0, `pmod1_8` |
-| 0x868 | `gpio[3].ios[8]` | 0, 0 |
-| 0x869 | `gpio[3].ios[9]` | 0, 0 |
-| 0x86a | `gpio[3].ios[10]` | 0, 0 |
-| 0x86b | `gpio[3].ios[11]` | 0, 0 |
-| 0x86c | `gpio[3].ios[12]` | 0, 0 |
-| 0x86d | `gpio[3].ios[13]` | 0, 0 |
-| 0x86e | `gpio[3].ios[14]` | 0, 0 |
-| 0x86f | `gpio[3].ios[15]` | 0, 0 |
-| 0x870 | `gpio[3].ios[16]` | 0, 0 |
-| 0x871 | `gpio[3].ios[17]` | 0, 0 |
-| 0x872 | `gpio[3].ios[18]` | 0, 0 |
-| 0x873 | `gpio[3].ios[19]` | 0, 0 |
-| 0x874 | `gpio[3].ios[20]` | 0, 0 |
-| 0x875 | `gpio[3].ios[21]` | 0, 0 |
-| 0x876 | `gpio[3].ios[22]` | 0, 0 |
-| 0x877 | `gpio[3].ios[23]` | 0, 0 |
-| 0x878 | `gpio[3].ios[24]` | 0, 0 |
-| 0x879 | `gpio[3].ios[25]` | 0, 0 |
-| 0x87a | `gpio[3].ios[26]` | 0, 0 |
-| 0x87b | `gpio[3].ios[27]` | 0, 0 |
-| 0x87c | `gpio[3].ios[28]` | 0, 0 |
-| 0x87d | `gpio[3].ios[29]` | 0, 0 |
-| 0x87e | `gpio[3].ios[30]` | 0, 0 |
-| 0x87f | `gpio[3].ios[31]` | 0, 0 |
-| 0x880 | `uart[0].rx` | 1, `ser0_rx` |
-| 0x881 | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
-| 0x882 | `uart[2].rx` | 1, `rs232_rx`, `pmod1_3` |
-| 0x883 | `spi[0].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
-| 0x884 | `spi[1].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3` |
+| 0x81c | `gpio[1].ios[0]` | 0, `ah_tmpio0` |
+| 0x81d | `gpio[1].ios[1]` | 0, `ah_tmpio1` |
+| 0x81e | `gpio[1].ios[2]` | 0, `ah_tmpio2` |
+| 0x81f | `gpio[1].ios[3]` | 0, `ah_tmpio3` |
+| 0x820 | `gpio[1].ios[4]` | 0, `ah_tmpio4` |
+| 0x821 | `gpio[1].ios[5]` | 0, `ah_tmpio5` |
+| 0x822 | `gpio[1].ios[6]` | 0, `ah_tmpio6` |
+| 0x823 | `gpio[1].ios[7]` | 0, `ah_tmpio7` |
+| 0x824 | `gpio[1].ios[8]` | 0, `ah_tmpio8` |
+| 0x825 | `gpio[1].ios[9]` | 0, `ah_tmpio9` |
+| 0x826 | `gpio[1].ios[10]` | 0, `ah_tmpio10` |
+| 0x827 | `gpio[1].ios[11]` | 0, `ah_tmpio11` |
+| 0x828 | `gpio[1].ios[12]` | 0, `ah_tmpio12` |
+| 0x829 | `gpio[1].ios[13]` | 0, `ah_tmpio13` |
+| 0x82a | `gpio[2].ios[0]` | 0, `pmod0_1` |
+| 0x82b | `gpio[2].ios[1]` | 0, `pmod0_2` |
+| 0x82c | `gpio[2].ios[2]` | 0, `pmod0_3` |
+| 0x82d | `gpio[2].ios[3]` | 0, `pmod0_4` |
+| 0x82e | `gpio[2].ios[4]` | 0, `pmod0_5` |
+| 0x82f | `gpio[2].ios[5]` | 0, `pmod0_6` |
+| 0x830 | `gpio[2].ios[6]` | 0, `pmod0_7` |
+| 0x831 | `gpio[2].ios[7]` | 0, `pmod0_8` |
+| 0x832 | `gpio[3].ios[0]` | 0, `pmod1_1` |
+| 0x833 | `gpio[3].ios[1]` | 0, `pmod1_2` |
+| 0x834 | `gpio[3].ios[2]` | 0, `pmod1_3` |
+| 0x835 | `gpio[3].ios[3]` | 0, `pmod1_4` |
+| 0x836 | `gpio[3].ios[4]` | 0, `pmod1_5` |
+| 0x837 | `gpio[3].ios[5]` | 0, `pmod1_6` |
+| 0x838 | `gpio[3].ios[6]` | 0, `pmod1_7` |
+| 0x839 | `gpio[3].ios[7]` | 0, `pmod1_8` |
+| 0x83a | `uart[0].rx` | 1, `ser0_rx` |
+| 0x83b | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
+| 0x83c | `uart[2].rx` | 1, `rs232_rx`, `pmod1_3` |
+| 0x83d | `spi[0].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
+| 0x83e | `spi[1].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3` |
 
 ## Regeneration
 
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index 1b1424250..c7d9be5b8 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -4614,149 +4614,13 @@ module pinmux
     .out_o(gpio_ios_o[0][27])
   );
 
-  logic [1:0] gpio_ios_0_28_sel;
-  logic gpio_ios_0_28_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_0_28_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_0_28_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_0_28_sel_addressed) begin
-        gpio_ios_0_28_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_0_28_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_0_28_sel),
-    .out_o(gpio_ios_o[0][28])
-  );
-
-  logic [1:0] gpio_ios_0_29_sel;
-  logic gpio_ios_0_29_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_0_29_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_0_29_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_0_29_sel_addressed) begin
-        gpio_ios_0_29_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_0_29_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_0_29_sel),
-    .out_o(gpio_ios_o[0][29])
-  );
-
-  logic [1:0] gpio_ios_0_30_sel;
-  logic gpio_ios_0_30_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_0_30_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_0_30_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_0_30_sel_addressed) begin
-        gpio_ios_0_30_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_0_30_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_0_30_sel),
-    .out_o(gpio_ios_o[0][30])
-  );
-
-  logic [1:0] gpio_ios_0_31_sel;
-  logic gpio_ios_0_31_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_0_31_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 28 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_0_31_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_0_31_sel_addressed) begin
-        gpio_ios_0_31_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_0_31_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_0_31_sel),
-    .out_o(gpio_ios_o[0][31])
-  );
-
   logic [1:0] gpio_ios_1_0_sel;
   logic gpio_ios_1_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_addr[RegAddrWidth-2:0] == 28 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4790,7 +4654,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_addr[RegAddrWidth-2:0] == 28 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4824,7 +4688,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_addr[RegAddrWidth-2:0] == 28 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4858,7 +4722,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 32 &
+    reg_addr[RegAddrWidth-2:0] == 28 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4892,7 +4756,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_addr[RegAddrWidth-2:0] == 32 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4926,7 +4790,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_addr[RegAddrWidth-2:0] == 32 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4960,7 +4824,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_addr[RegAddrWidth-2:0] == 32 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -4994,7 +4858,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 36 &
+    reg_addr[RegAddrWidth-2:0] == 32 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5028,7 +4892,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_8_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_addr[RegAddrWidth-2:0] == 36 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5062,7 +4926,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_9_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_addr[RegAddrWidth-2:0] == 36 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5096,7 +4960,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_10_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_addr[RegAddrWidth-2:0] == 36 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5130,7 +4994,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_11_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 40 &
+    reg_addr[RegAddrWidth-2:0] == 36 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5164,7 +5028,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_12_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_addr[RegAddrWidth-2:0] == 40 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5198,7 +5062,7 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign gpio_ios_1_13_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_addr[RegAddrWidth-2:0] == 40 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
@@ -5226,22 +5090,22 @@ module pinmux
     .out_o(gpio_ios_o[1][13])
   );
 
-  logic [1:0] gpio_ios_1_14_sel;
-  logic gpio_ios_1_14_sel_addressed;
+  logic [1:0] gpio_ios_2_0_sel;
+  logic gpio_ios_2_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_14_sel_addressed =
+  assign gpio_ios_2_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_addr[RegAddrWidth-2:0] == 40 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_14_sel <= 2'b10;
+      gpio_ios_2_0_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_14_sel_addressed) begin
-        gpio_ios_1_14_sel <= reg_wdata[16+:2];
+      if (reg_we & gpio_ios_2_0_sel_addressed) begin
+        gpio_ios_2_0_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -5249,33 +5113,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_14_mux (
+  ) gpio_ios_2_0_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_1]
     }),
-    .sel_i(gpio_ios_1_14_sel),
-    .out_o(gpio_ios_o[1][14])
+    .sel_i(gpio_ios_2_0_sel),
+    .out_o(gpio_ios_o[2][0])
   );
 
-  logic [1:0] gpio_ios_1_15_sel;
-  logic gpio_ios_1_15_sel_addressed;
+  logic [1:0] gpio_ios_2_1_sel;
+  logic gpio_ios_2_1_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_15_sel_addressed =
+  assign gpio_ios_2_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 44 &
+    reg_addr[RegAddrWidth-2:0] == 40 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_15_sel <= 2'b10;
+      gpio_ios_2_1_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_15_sel_addressed) begin
-        gpio_ios_1_15_sel <= reg_wdata[24+:2];
+      if (reg_we & gpio_ios_2_1_sel_addressed) begin
+        gpio_ios_2_1_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -5283,33 +5147,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_15_mux (
+  ) gpio_ios_2_1_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_2]
     }),
-    .sel_i(gpio_ios_1_15_sel),
-    .out_o(gpio_ios_o[1][15])
+    .sel_i(gpio_ios_2_1_sel),
+    .out_o(gpio_ios_o[2][1])
   );
 
-  logic [1:0] gpio_ios_1_16_sel;
-  logic gpio_ios_1_16_sel_addressed;
+  logic [1:0] gpio_ios_2_2_sel;
+  logic gpio_ios_2_2_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_16_sel_addressed =
+  assign gpio_ios_2_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_addr[RegAddrWidth-2:0] == 44 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_16_sel <= 2'b10;
+      gpio_ios_2_2_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_16_sel_addressed) begin
-        gpio_ios_1_16_sel <= reg_wdata[0+:2];
+      if (reg_we & gpio_ios_2_2_sel_addressed) begin
+        gpio_ios_2_2_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -5317,33 +5181,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_16_mux (
+  ) gpio_ios_2_2_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_3]
     }),
-    .sel_i(gpio_ios_1_16_sel),
-    .out_o(gpio_ios_o[1][16])
+    .sel_i(gpio_ios_2_2_sel),
+    .out_o(gpio_ios_o[2][2])
   );
 
-  logic [1:0] gpio_ios_1_17_sel;
-  logic gpio_ios_1_17_sel_addressed;
+  logic [1:0] gpio_ios_2_3_sel;
+  logic gpio_ios_2_3_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_17_sel_addressed =
+  assign gpio_ios_2_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_addr[RegAddrWidth-2:0] == 44 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_17_sel <= 2'b10;
+      gpio_ios_2_3_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_17_sel_addressed) begin
-        gpio_ios_1_17_sel <= reg_wdata[8+:2];
+      if (reg_we & gpio_ios_2_3_sel_addressed) begin
+        gpio_ios_2_3_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -5351,33 +5215,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_17_mux (
+  ) gpio_ios_2_3_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_4]
     }),
-    .sel_i(gpio_ios_1_17_sel),
-    .out_o(gpio_ios_o[1][17])
+    .sel_i(gpio_ios_2_3_sel),
+    .out_o(gpio_ios_o[2][3])
   );
 
-  logic [1:0] gpio_ios_1_18_sel;
-  logic gpio_ios_1_18_sel_addressed;
+  logic [1:0] gpio_ios_2_4_sel;
+  logic gpio_ios_2_4_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_18_sel_addressed =
+  assign gpio_ios_2_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_addr[RegAddrWidth-2:0] == 44 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_18_sel <= 2'b10;
+      gpio_ios_2_4_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_18_sel_addressed) begin
-        gpio_ios_1_18_sel <= reg_wdata[16+:2];
+      if (reg_we & gpio_ios_2_4_sel_addressed) begin
+        gpio_ios_2_4_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -5385,33 +5249,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_18_mux (
+  ) gpio_ios_2_4_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_5]
     }),
-    .sel_i(gpio_ios_1_18_sel),
-    .out_o(gpio_ios_o[1][18])
+    .sel_i(gpio_ios_2_4_sel),
+    .out_o(gpio_ios_o[2][4])
   );
 
-  logic [1:0] gpio_ios_1_19_sel;
-  logic gpio_ios_1_19_sel_addressed;
+  logic [1:0] gpio_ios_2_5_sel;
+  logic gpio_ios_2_5_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_19_sel_addressed =
+  assign gpio_ios_2_5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 48 &
+    reg_addr[RegAddrWidth-2:0] == 44 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_19_sel <= 2'b10;
+      gpio_ios_2_5_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_19_sel_addressed) begin
-        gpio_ios_1_19_sel <= reg_wdata[24+:2];
+      if (reg_we & gpio_ios_2_5_sel_addressed) begin
+        gpio_ios_2_5_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -5419,33 +5283,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_19_mux (
+  ) gpio_ios_2_5_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_6]
     }),
-    .sel_i(gpio_ios_1_19_sel),
-    .out_o(gpio_ios_o[1][19])
+    .sel_i(gpio_ios_2_5_sel),
+    .out_o(gpio_ios_o[2][5])
   );
 
-  logic [1:0] gpio_ios_1_20_sel;
-  logic gpio_ios_1_20_sel_addressed;
+  logic [1:0] gpio_ios_2_6_sel;
+  logic gpio_ios_2_6_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_20_sel_addressed =
+  assign gpio_ios_2_6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_addr[RegAddrWidth-2:0] == 48 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_20_sel <= 2'b10;
+      gpio_ios_2_6_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_20_sel_addressed) begin
-        gpio_ios_1_20_sel <= reg_wdata[0+:2];
+      if (reg_we & gpio_ios_2_6_sel_addressed) begin
+        gpio_ios_2_6_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -5453,33 +5317,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_20_mux (
+  ) gpio_ios_2_6_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_7]
     }),
-    .sel_i(gpio_ios_1_20_sel),
-    .out_o(gpio_ios_o[1][20])
+    .sel_i(gpio_ios_2_6_sel),
+    .out_o(gpio_ios_o[2][6])
   );
 
-  logic [1:0] gpio_ios_1_21_sel;
-  logic gpio_ios_1_21_sel_addressed;
+  logic [1:0] gpio_ios_2_7_sel;
+  logic gpio_ios_2_7_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_21_sel_addressed =
+  assign gpio_ios_2_7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_addr[RegAddrWidth-2:0] == 48 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_21_sel <= 2'b10;
+      gpio_ios_2_7_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_21_sel_addressed) begin
-        gpio_ios_1_21_sel <= reg_wdata[8+:2];
+      if (reg_we & gpio_ios_2_7_sel_addressed) begin
+        gpio_ios_2_7_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -5487,33 +5351,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_21_mux (
+  ) gpio_ios_2_7_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD0_8]
     }),
-    .sel_i(gpio_ios_1_21_sel),
-    .out_o(gpio_ios_o[1][21])
+    .sel_i(gpio_ios_2_7_sel),
+    .out_o(gpio_ios_o[2][7])
   );
 
-  logic [1:0] gpio_ios_1_22_sel;
-  logic gpio_ios_1_22_sel_addressed;
+  logic [1:0] gpio_ios_3_0_sel;
+  logic gpio_ios_3_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_22_sel_addressed =
+  assign gpio_ios_3_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_addr[RegAddrWidth-2:0] == 48 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_22_sel <= 2'b10;
+      gpio_ios_3_0_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_22_sel_addressed) begin
-        gpio_ios_1_22_sel <= reg_wdata[16+:2];
+      if (reg_we & gpio_ios_3_0_sel_addressed) begin
+        gpio_ios_3_0_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -5521,33 +5385,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_22_mux (
+  ) gpio_ios_3_0_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_1]
     }),
-    .sel_i(gpio_ios_1_22_sel),
-    .out_o(gpio_ios_o[1][22])
+    .sel_i(gpio_ios_3_0_sel),
+    .out_o(gpio_ios_o[3][0])
   );
 
-  logic [1:0] gpio_ios_1_23_sel;
-  logic gpio_ios_1_23_sel_addressed;
+  logic [1:0] gpio_ios_3_1_sel;
+  logic gpio_ios_3_1_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_23_sel_addressed =
+  assign gpio_ios_3_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 52 &
+    reg_addr[RegAddrWidth-2:0] == 48 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_23_sel <= 2'b10;
+      gpio_ios_3_1_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_23_sel_addressed) begin
-        gpio_ios_1_23_sel <= reg_wdata[24+:2];
+      if (reg_we & gpio_ios_3_1_sel_addressed) begin
+        gpio_ios_3_1_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -5555,33 +5419,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_23_mux (
+  ) gpio_ios_3_1_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_2]
     }),
-    .sel_i(gpio_ios_1_23_sel),
-    .out_o(gpio_ios_o[1][23])
+    .sel_i(gpio_ios_3_1_sel),
+    .out_o(gpio_ios_o[3][1])
   );
 
-  logic [1:0] gpio_ios_1_24_sel;
-  logic gpio_ios_1_24_sel_addressed;
+  logic [1:0] gpio_ios_3_2_sel;
+  logic gpio_ios_3_2_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_24_sel_addressed =
+  assign gpio_ios_3_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_addr[RegAddrWidth-2:0] == 52 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_24_sel <= 2'b10;
+      gpio_ios_3_2_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_24_sel_addressed) begin
-        gpio_ios_1_24_sel <= reg_wdata[0+:2];
+      if (reg_we & gpio_ios_3_2_sel_addressed) begin
+        gpio_ios_3_2_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -5589,33 +5453,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_24_mux (
+  ) gpio_ios_3_2_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_3]
     }),
-    .sel_i(gpio_ios_1_24_sel),
-    .out_o(gpio_ios_o[1][24])
+    .sel_i(gpio_ios_3_2_sel),
+    .out_o(gpio_ios_o[3][2])
   );
 
-  logic [1:0] gpio_ios_1_25_sel;
-  logic gpio_ios_1_25_sel_addressed;
+  logic [1:0] gpio_ios_3_3_sel;
+  logic gpio_ios_3_3_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_25_sel_addressed =
+  assign gpio_ios_3_3_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_addr[RegAddrWidth-2:0] == 52 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_25_sel <= 2'b10;
+      gpio_ios_3_3_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_1_25_sel_addressed) begin
-        gpio_ios_1_25_sel <= reg_wdata[8+:2];
+      if (reg_we & gpio_ios_3_3_sel_addressed) begin
+        gpio_ios_3_3_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -5623,2209 +5487,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_1_25_mux (
+  ) gpio_ios_3_3_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_4]
     }),
-    .sel_i(gpio_ios_1_25_sel),
-    .out_o(gpio_ios_o[1][25])
+    .sel_i(gpio_ios_3_3_sel),
+    .out_o(gpio_ios_o[3][3])
   );
 
-  logic [1:0] gpio_ios_1_26_sel;
-  logic gpio_ios_1_26_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_26_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_26_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_1_26_sel_addressed) begin
-        gpio_ios_1_26_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_1_26_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_1_26_sel),
-    .out_o(gpio_ios_o[1][26])
-  );
-
-  logic [1:0] gpio_ios_1_27_sel;
-  logic gpio_ios_1_27_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_27_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_27_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_1_27_sel_addressed) begin
-        gpio_ios_1_27_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_1_27_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_1_27_sel),
-    .out_o(gpio_ios_o[1][27])
-  );
-
-  logic [1:0] gpio_ios_1_28_sel;
-  logic gpio_ios_1_28_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_28_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_28_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_1_28_sel_addressed) begin
-        gpio_ios_1_28_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_1_28_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_1_28_sel),
-    .out_o(gpio_ios_o[1][28])
-  );
-
-  logic [1:0] gpio_ios_1_29_sel;
-  logic gpio_ios_1_29_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_29_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_29_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_1_29_sel_addressed) begin
-        gpio_ios_1_29_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_1_29_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_1_29_sel),
-    .out_o(gpio_ios_o[1][29])
-  );
-
-  logic [1:0] gpio_ios_1_30_sel;
-  logic gpio_ios_1_30_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_30_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_30_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_1_30_sel_addressed) begin
-        gpio_ios_1_30_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_1_30_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_1_30_sel),
-    .out_o(gpio_ios_o[1][30])
-  );
-
-  logic [1:0] gpio_ios_1_31_sel;
-  logic gpio_ios_1_31_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_1_31_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_1_31_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_1_31_sel_addressed) begin
-        gpio_ios_1_31_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_1_31_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_1_31_sel),
-    .out_o(gpio_ios_o[1][31])
-  );
-
-  logic [1:0] gpio_ios_2_0_sel;
-  logic gpio_ios_2_0_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_0_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_0_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_0_sel_addressed) begin
-        gpio_ios_2_0_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_0_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_1]
-    }),
-    .sel_i(gpio_ios_2_0_sel),
-    .out_o(gpio_ios_o[2][0])
-  );
-
-  logic [1:0] gpio_ios_2_1_sel;
-  logic gpio_ios_2_1_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_1_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_1_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_1_sel_addressed) begin
-        gpio_ios_2_1_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_1_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_2]
-    }),
-    .sel_i(gpio_ios_2_1_sel),
-    .out_o(gpio_ios_o[2][1])
-  );
-
-  logic [1:0] gpio_ios_2_2_sel;
-  logic gpio_ios_2_2_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_2_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_2_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_2_sel_addressed) begin
-        gpio_ios_2_2_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_2_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_3]
-    }),
-    .sel_i(gpio_ios_2_2_sel),
-    .out_o(gpio_ios_o[2][2])
-  );
-
-  logic [1:0] gpio_ios_2_3_sel;
-  logic gpio_ios_2_3_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_3_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 64 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_3_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_3_sel_addressed) begin
-        gpio_ios_2_3_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_3_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_4]
-    }),
-    .sel_i(gpio_ios_2_3_sel),
-    .out_o(gpio_ios_o[2][3])
-  );
-
-  logic [1:0] gpio_ios_2_4_sel;
-  logic gpio_ios_2_4_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_4_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_4_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_4_sel_addressed) begin
-        gpio_ios_2_4_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_4_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_5]
-    }),
-    .sel_i(gpio_ios_2_4_sel),
-    .out_o(gpio_ios_o[2][4])
-  );
-
-  logic [1:0] gpio_ios_2_5_sel;
-  logic gpio_ios_2_5_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_5_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_5_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_5_sel_addressed) begin
-        gpio_ios_2_5_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_5_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_6]
-    }),
-    .sel_i(gpio_ios_2_5_sel),
-    .out_o(gpio_ios_o[2][5])
-  );
-
-  logic [1:0] gpio_ios_2_6_sel;
-  logic gpio_ios_2_6_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_6_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_6_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_6_sel_addressed) begin
-        gpio_ios_2_6_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_6_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_7]
-    }),
-    .sel_i(gpio_ios_2_6_sel),
-    .out_o(gpio_ios_o[2][6])
-  );
-
-  logic [1:0] gpio_ios_2_7_sel;
-  logic gpio_ios_2_7_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_7_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 68 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_7_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_7_sel_addressed) begin
-        gpio_ios_2_7_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_7_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD0_8]
-    }),
-    .sel_i(gpio_ios_2_7_sel),
-    .out_o(gpio_ios_o[2][7])
-  );
-
-  logic [1:0] gpio_ios_2_8_sel;
-  logic gpio_ios_2_8_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_8_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_8_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_8_sel_addressed) begin
-        gpio_ios_2_8_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_8_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_8_sel),
-    .out_o(gpio_ios_o[2][8])
-  );
-
-  logic [1:0] gpio_ios_2_9_sel;
-  logic gpio_ios_2_9_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_9_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_9_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_9_sel_addressed) begin
-        gpio_ios_2_9_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_9_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_9_sel),
-    .out_o(gpio_ios_o[2][9])
-  );
-
-  logic [1:0] gpio_ios_2_10_sel;
-  logic gpio_ios_2_10_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_10_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_10_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_10_sel_addressed) begin
-        gpio_ios_2_10_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_10_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_10_sel),
-    .out_o(gpio_ios_o[2][10])
-  );
-
-  logic [1:0] gpio_ios_2_11_sel;
-  logic gpio_ios_2_11_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_11_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 72 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_11_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_11_sel_addressed) begin
-        gpio_ios_2_11_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_11_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_11_sel),
-    .out_o(gpio_ios_o[2][11])
-  );
-
-  logic [1:0] gpio_ios_2_12_sel;
-  logic gpio_ios_2_12_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_12_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_12_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_12_sel_addressed) begin
-        gpio_ios_2_12_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_12_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_12_sel),
-    .out_o(gpio_ios_o[2][12])
-  );
-
-  logic [1:0] gpio_ios_2_13_sel;
-  logic gpio_ios_2_13_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_13_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_13_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_13_sel_addressed) begin
-        gpio_ios_2_13_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_13_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_13_sel),
-    .out_o(gpio_ios_o[2][13])
-  );
-
-  logic [1:0] gpio_ios_2_14_sel;
-  logic gpio_ios_2_14_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_14_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_14_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_14_sel_addressed) begin
-        gpio_ios_2_14_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_14_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_14_sel),
-    .out_o(gpio_ios_o[2][14])
-  );
-
-  logic [1:0] gpio_ios_2_15_sel;
-  logic gpio_ios_2_15_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_15_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 76 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_15_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_15_sel_addressed) begin
-        gpio_ios_2_15_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_15_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_15_sel),
-    .out_o(gpio_ios_o[2][15])
-  );
-
-  logic [1:0] gpio_ios_2_16_sel;
-  logic gpio_ios_2_16_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_16_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_16_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_16_sel_addressed) begin
-        gpio_ios_2_16_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_16_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_16_sel),
-    .out_o(gpio_ios_o[2][16])
-  );
-
-  logic [1:0] gpio_ios_2_17_sel;
-  logic gpio_ios_2_17_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_17_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_17_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_17_sel_addressed) begin
-        gpio_ios_2_17_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_17_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_17_sel),
-    .out_o(gpio_ios_o[2][17])
-  );
-
-  logic [1:0] gpio_ios_2_18_sel;
-  logic gpio_ios_2_18_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_18_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_18_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_18_sel_addressed) begin
-        gpio_ios_2_18_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_18_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_18_sel),
-    .out_o(gpio_ios_o[2][18])
-  );
-
-  logic [1:0] gpio_ios_2_19_sel;
-  logic gpio_ios_2_19_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_19_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 80 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_19_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_19_sel_addressed) begin
-        gpio_ios_2_19_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_19_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_19_sel),
-    .out_o(gpio_ios_o[2][19])
-  );
-
-  logic [1:0] gpio_ios_2_20_sel;
-  logic gpio_ios_2_20_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_20_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 84 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_20_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_20_sel_addressed) begin
-        gpio_ios_2_20_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_20_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_20_sel),
-    .out_o(gpio_ios_o[2][20])
-  );
-
-  logic [1:0] gpio_ios_2_21_sel;
-  logic gpio_ios_2_21_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_21_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 84 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_21_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_21_sel_addressed) begin
-        gpio_ios_2_21_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_21_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_21_sel),
-    .out_o(gpio_ios_o[2][21])
-  );
-
-  logic [1:0] gpio_ios_2_22_sel;
-  logic gpio_ios_2_22_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_22_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 84 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_22_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_22_sel_addressed) begin
-        gpio_ios_2_22_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_22_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_22_sel),
-    .out_o(gpio_ios_o[2][22])
-  );
-
-  logic [1:0] gpio_ios_2_23_sel;
-  logic gpio_ios_2_23_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_23_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 84 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_23_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_23_sel_addressed) begin
-        gpio_ios_2_23_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_23_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_23_sel),
-    .out_o(gpio_ios_o[2][23])
-  );
-
-  logic [1:0] gpio_ios_2_24_sel;
-  logic gpio_ios_2_24_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_24_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 88 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_24_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_24_sel_addressed) begin
-        gpio_ios_2_24_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_24_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_24_sel),
-    .out_o(gpio_ios_o[2][24])
-  );
-
-  logic [1:0] gpio_ios_2_25_sel;
-  logic gpio_ios_2_25_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_25_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 88 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_25_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_25_sel_addressed) begin
-        gpio_ios_2_25_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_25_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_25_sel),
-    .out_o(gpio_ios_o[2][25])
-  );
-
-  logic [1:0] gpio_ios_2_26_sel;
-  logic gpio_ios_2_26_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_26_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 88 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_26_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_26_sel_addressed) begin
-        gpio_ios_2_26_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_26_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_26_sel),
-    .out_o(gpio_ios_o[2][26])
-  );
-
-  logic [1:0] gpio_ios_2_27_sel;
-  logic gpio_ios_2_27_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_27_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 88 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_27_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_27_sel_addressed) begin
-        gpio_ios_2_27_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_27_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_27_sel),
-    .out_o(gpio_ios_o[2][27])
-  );
-
-  logic [1:0] gpio_ios_2_28_sel;
-  logic gpio_ios_2_28_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_28_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 92 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_28_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_28_sel_addressed) begin
-        gpio_ios_2_28_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_28_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_28_sel),
-    .out_o(gpio_ios_o[2][28])
-  );
-
-  logic [1:0] gpio_ios_2_29_sel;
-  logic gpio_ios_2_29_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_29_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 92 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_29_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_29_sel_addressed) begin
-        gpio_ios_2_29_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_29_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_29_sel),
-    .out_o(gpio_ios_o[2][29])
-  );
-
-  logic [1:0] gpio_ios_2_30_sel;
-  logic gpio_ios_2_30_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_30_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 92 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_30_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_30_sel_addressed) begin
-        gpio_ios_2_30_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_30_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_30_sel),
-    .out_o(gpio_ios_o[2][30])
-  );
-
-  logic [1:0] gpio_ios_2_31_sel;
-  logic gpio_ios_2_31_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_2_31_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 92 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_2_31_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_2_31_sel_addressed) begin
-        gpio_ios_2_31_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_2_31_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_2_31_sel),
-    .out_o(gpio_ios_o[2][31])
-  );
-
-  logic [1:0] gpio_ios_3_0_sel;
-  logic gpio_ios_3_0_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_0_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 96 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_0_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_0_sel_addressed) begin
-        gpio_ios_3_0_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_0_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_1]
-    }),
-    .sel_i(gpio_ios_3_0_sel),
-    .out_o(gpio_ios_o[3][0])
-  );
-
-  logic [1:0] gpio_ios_3_1_sel;
-  logic gpio_ios_3_1_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_1_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 96 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_1_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_1_sel_addressed) begin
-        gpio_ios_3_1_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_1_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_2]
-    }),
-    .sel_i(gpio_ios_3_1_sel),
-    .out_o(gpio_ios_o[3][1])
-  );
-
-  logic [1:0] gpio_ios_3_2_sel;
-  logic gpio_ios_3_2_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_2_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 96 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_2_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_2_sel_addressed) begin
-        gpio_ios_3_2_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_2_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_3]
-    }),
-    .sel_i(gpio_ios_3_2_sel),
-    .out_o(gpio_ios_o[3][2])
-  );
-
-  logic [1:0] gpio_ios_3_3_sel;
-  logic gpio_ios_3_3_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_3_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 96 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_3_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_3_sel_addressed) begin
-        gpio_ios_3_3_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_3_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_4]
-    }),
-    .sel_i(gpio_ios_3_3_sel),
-    .out_o(gpio_ios_o[3][3])
-  );
-
-  logic [1:0] gpio_ios_3_4_sel;
-  logic gpio_ios_3_4_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_4_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 100 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_4_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_4_sel_addressed) begin
-        gpio_ios_3_4_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_4_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_5]
-    }),
-    .sel_i(gpio_ios_3_4_sel),
-    .out_o(gpio_ios_o[3][4])
-  );
-
-  logic [1:0] gpio_ios_3_5_sel;
-  logic gpio_ios_3_5_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_5_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 100 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_5_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_5_sel_addressed) begin
-        gpio_ios_3_5_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_5_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_6]
-    }),
-    .sel_i(gpio_ios_3_5_sel),
-    .out_o(gpio_ios_o[3][5])
-  );
-
-  logic [1:0] gpio_ios_3_6_sel;
-  logic gpio_ios_3_6_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_6_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 100 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_6_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_6_sel_addressed) begin
-        gpio_ios_3_6_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_6_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_7]
-    }),
-    .sel_i(gpio_ios_3_6_sel),
-    .out_o(gpio_ios_o[3][6])
-  );
-
-  logic [1:0] gpio_ios_3_7_sel;
-  logic gpio_ios_3_7_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_7_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 100 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_7_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_7_sel_addressed) begin
-        gpio_ios_3_7_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_7_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      inout_from_pins_i[INOUT_PIN_PMOD1_8]
-    }),
-    .sel_i(gpio_ios_3_7_sel),
-    .out_o(gpio_ios_o[3][7])
-  );
-
-  logic [1:0] gpio_ios_3_8_sel;
-  logic gpio_ios_3_8_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_8_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 104 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_8_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_8_sel_addressed) begin
-        gpio_ios_3_8_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_8_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_8_sel),
-    .out_o(gpio_ios_o[3][8])
-  );
-
-  logic [1:0] gpio_ios_3_9_sel;
-  logic gpio_ios_3_9_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_9_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 104 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_9_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_9_sel_addressed) begin
-        gpio_ios_3_9_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_9_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_9_sel),
-    .out_o(gpio_ios_o[3][9])
-  );
-
-  logic [1:0] gpio_ios_3_10_sel;
-  logic gpio_ios_3_10_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_10_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 104 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_10_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_10_sel_addressed) begin
-        gpio_ios_3_10_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_10_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_10_sel),
-    .out_o(gpio_ios_o[3][10])
-  );
-
-  logic [1:0] gpio_ios_3_11_sel;
-  logic gpio_ios_3_11_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_11_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 104 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_11_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_11_sel_addressed) begin
-        gpio_ios_3_11_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_11_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_11_sel),
-    .out_o(gpio_ios_o[3][11])
-  );
-
-  logic [1:0] gpio_ios_3_12_sel;
-  logic gpio_ios_3_12_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_12_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 108 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_12_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_12_sel_addressed) begin
-        gpio_ios_3_12_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_12_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_12_sel),
-    .out_o(gpio_ios_o[3][12])
-  );
-
-  logic [1:0] gpio_ios_3_13_sel;
-  logic gpio_ios_3_13_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_13_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 108 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_13_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_13_sel_addressed) begin
-        gpio_ios_3_13_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_13_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_13_sel),
-    .out_o(gpio_ios_o[3][13])
-  );
-
-  logic [1:0] gpio_ios_3_14_sel;
-  logic gpio_ios_3_14_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_14_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 108 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_14_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_14_sel_addressed) begin
-        gpio_ios_3_14_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_14_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_14_sel),
-    .out_o(gpio_ios_o[3][14])
-  );
-
-  logic [1:0] gpio_ios_3_15_sel;
-  logic gpio_ios_3_15_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_15_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 108 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_15_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_15_sel_addressed) begin
-        gpio_ios_3_15_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_15_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_15_sel),
-    .out_o(gpio_ios_o[3][15])
-  );
-
-  logic [1:0] gpio_ios_3_16_sel;
-  logic gpio_ios_3_16_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_16_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 112 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_16_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_16_sel_addressed) begin
-        gpio_ios_3_16_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_16_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_16_sel),
-    .out_o(gpio_ios_o[3][16])
-  );
-
-  logic [1:0] gpio_ios_3_17_sel;
-  logic gpio_ios_3_17_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_17_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 112 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_17_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_17_sel_addressed) begin
-        gpio_ios_3_17_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_17_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_17_sel),
-    .out_o(gpio_ios_o[3][17])
-  );
-
-  logic [1:0] gpio_ios_3_18_sel;
-  logic gpio_ios_3_18_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_18_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 112 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_18_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_18_sel_addressed) begin
-        gpio_ios_3_18_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_18_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_18_sel),
-    .out_o(gpio_ios_o[3][18])
-  );
-
-  logic [1:0] gpio_ios_3_19_sel;
-  logic gpio_ios_3_19_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_19_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 112 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_19_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_19_sel_addressed) begin
-        gpio_ios_3_19_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_19_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_19_sel),
-    .out_o(gpio_ios_o[3][19])
-  );
-
-  logic [1:0] gpio_ios_3_20_sel;
-  logic gpio_ios_3_20_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_20_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 116 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_20_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_20_sel_addressed) begin
-        gpio_ios_3_20_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_20_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_20_sel),
-    .out_o(gpio_ios_o[3][20])
-  );
-
-  logic [1:0] gpio_ios_3_21_sel;
-  logic gpio_ios_3_21_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_21_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 116 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_21_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_21_sel_addressed) begin
-        gpio_ios_3_21_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_21_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_21_sel),
-    .out_o(gpio_ios_o[3][21])
-  );
-
-  logic [1:0] gpio_ios_3_22_sel;
-  logic gpio_ios_3_22_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_22_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 116 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_22_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_22_sel_addressed) begin
-        gpio_ios_3_22_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_22_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_22_sel),
-    .out_o(gpio_ios_o[3][22])
-  );
-
-  logic [1:0] gpio_ios_3_23_sel;
-  logic gpio_ios_3_23_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_23_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 116 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_23_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_23_sel_addressed) begin
-        gpio_ios_3_23_sel <= reg_wdata[24+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_23_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_23_sel),
-    .out_o(gpio_ios_o[3][23])
-  );
-
-  logic [1:0] gpio_ios_3_24_sel;
-  logic gpio_ios_3_24_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_24_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 120 &
-    reg_be[0] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_24_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_24_sel_addressed) begin
-        gpio_ios_3_24_sel <= reg_wdata[0+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_24_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_24_sel),
-    .out_o(gpio_ios_o[3][24])
-  );
-
-  logic [1:0] gpio_ios_3_25_sel;
-  logic gpio_ios_3_25_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_25_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 120 &
-    reg_be[1] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_25_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_25_sel_addressed) begin
-        gpio_ios_3_25_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_25_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_25_sel),
-    .out_o(gpio_ios_o[3][25])
-  );
-
-  logic [1:0] gpio_ios_3_26_sel;
-  logic gpio_ios_3_26_sel_addressed;
+  logic [1:0] gpio_ios_3_4_sel;
+  logic gpio_ios_3_4_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_26_sel_addressed =
+  assign gpio_ios_3_4_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 120 &
+    reg_addr[RegAddrWidth-2:0] == 52 &
     reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_26_sel <= 2'b10;
+      gpio_ios_3_4_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_3_26_sel_addressed) begin
-        gpio_ios_3_26_sel <= reg_wdata[16+:2];
+      if (reg_we & gpio_ios_3_4_sel_addressed) begin
+        gpio_ios_3_4_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -7833,33 +5521,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_3_26_mux (
+  ) gpio_ios_3_4_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_5]
     }),
-    .sel_i(gpio_ios_3_26_sel),
-    .out_o(gpio_ios_o[3][26])
+    .sel_i(gpio_ios_3_4_sel),
+    .out_o(gpio_ios_o[3][4])
   );
 
-  logic [1:0] gpio_ios_3_27_sel;
-  logic gpio_ios_3_27_sel_addressed;
+  logic [1:0] gpio_ios_3_5_sel;
+  logic gpio_ios_3_5_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_27_sel_addressed =
+  assign gpio_ios_3_5_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 120 &
+    reg_addr[RegAddrWidth-2:0] == 52 &
     reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_27_sel <= 2'b10;
+      gpio_ios_3_5_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_3_27_sel_addressed) begin
-        gpio_ios_3_27_sel <= reg_wdata[24+:2];
+      if (reg_we & gpio_ios_3_5_sel_addressed) begin
+        gpio_ios_3_5_sel <= reg_wdata[24+:2];
       end
     end
   end
@@ -7867,33 +5555,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_3_27_mux (
+  ) gpio_ios_3_5_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_6]
     }),
-    .sel_i(gpio_ios_3_27_sel),
-    .out_o(gpio_ios_o[3][27])
+    .sel_i(gpio_ios_3_5_sel),
+    .out_o(gpio_ios_o[3][5])
   );
 
-  logic [1:0] gpio_ios_3_28_sel;
-  logic gpio_ios_3_28_sel_addressed;
+  logic [1:0] gpio_ios_3_6_sel;
+  logic gpio_ios_3_6_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_28_sel_addressed =
+  assign gpio_ios_3_6_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 124 &
+    reg_addr[RegAddrWidth-2:0] == 56 &
     reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_28_sel <= 2'b10;
+      gpio_ios_3_6_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_3_28_sel_addressed) begin
-        gpio_ios_3_28_sel <= reg_wdata[0+:2];
+      if (reg_we & gpio_ios_3_6_sel_addressed) begin
+        gpio_ios_3_6_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -7901,101 +5589,33 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_3_28_mux (
+  ) gpio_ios_3_6_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_7]
     }),
-    .sel_i(gpio_ios_3_28_sel),
-    .out_o(gpio_ios_o[3][28])
+    .sel_i(gpio_ios_3_6_sel),
+    .out_o(gpio_ios_o[3][6])
   );
 
-  logic [1:0] gpio_ios_3_29_sel;
-  logic gpio_ios_3_29_sel_addressed;
+  logic [1:0] gpio_ios_3_7_sel;
+  logic gpio_ios_3_7_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_29_sel_addressed =
+  assign gpio_ios_3_7_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 124 &
+    reg_addr[RegAddrWidth-2:0] == 56 &
     reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_29_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_29_sel_addressed) begin
-        gpio_ios_3_29_sel <= reg_wdata[8+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_29_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_29_sel),
-    .out_o(gpio_ios_o[3][29])
-  );
-
-  logic [1:0] gpio_ios_3_30_sel;
-  logic gpio_ios_3_30_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_30_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 124 &
-    reg_be[2] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_30_sel <= 2'b10;
-    end else begin
-      if (reg_we & gpio_ios_3_30_sel_addressed) begin
-        gpio_ios_3_30_sel <= reg_wdata[16+:2];
-      end
-    end
-  end
-
-  prim_onehot_mux #(
-    .Width(1),
-    .Inputs(2)
-  ) gpio_ios_3_30_mux (
-    .clk_i,
-    .rst_ni,
-    .in_i({
-      1'b0,
-      1'b0
-    }),
-    .sel_i(gpio_ios_3_30_sel),
-    .out_o(gpio_ios_o[3][30])
-  );
-
-  logic [1:0] gpio_ios_3_31_sel;
-  logic gpio_ios_3_31_sel_addressed;
-
-  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
-  assign gpio_ios_3_31_sel_addressed =
-    reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 124 &
-    reg_be[3] == 1'b1;
-
-  always @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      gpio_ios_3_31_sel <= 2'b10;
+      gpio_ios_3_7_sel <= 2'b10;
     end else begin
-      if (reg_we & gpio_ios_3_31_sel_addressed) begin
-        gpio_ios_3_31_sel <= reg_wdata[24+:2];
+      if (reg_we & gpio_ios_3_7_sel_addressed) begin
+        gpio_ios_3_7_sel <= reg_wdata[8+:2];
       end
     end
   end
@@ -8003,15 +5623,15 @@ module pinmux
   prim_onehot_mux #(
     .Width(1),
     .Inputs(2)
-  ) gpio_ios_3_31_mux (
+  ) gpio_ios_3_7_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      1'b0
+      inout_from_pins_i[INOUT_PIN_PMOD1_8]
     }),
-    .sel_i(gpio_ios_3_31_sel),
-    .out_o(gpio_ios_o[3][31])
+    .sel_i(gpio_ios_3_7_sel),
+    .out_o(gpio_ios_o[3][7])
   );
 
   logic [1:0] uart_rx_0_sel;
@@ -8020,8 +5640,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign uart_rx_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 128 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8029,7 +5649,7 @@ module pinmux
       uart_rx_0_sel <= 2'b10;
     end else begin
       if (reg_we & uart_rx_0_sel_addressed) begin
-        uart_rx_0_sel <= reg_wdata[0+:2];
+        uart_rx_0_sel <= reg_wdata[16+:2];
       end
     end
   end
@@ -8054,8 +5674,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign uart_rx_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 128 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8063,7 +5683,7 @@ module pinmux
       uart_rx_1_sel <= 6'b10;
     end else begin
       if (reg_we & uart_rx_1_sel_addressed) begin
-        uart_rx_1_sel <= reg_wdata[8+:6];
+        uart_rx_1_sel <= reg_wdata[24+:6];
       end
     end
   end
@@ -8092,8 +5712,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign uart_rx_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 128 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8101,7 +5721,7 @@ module pinmux
       uart_rx_2_sel <= 3'b10;
     end else begin
       if (reg_we & uart_rx_2_sel_addressed) begin
-        uart_rx_2_sel <= reg_wdata[16+:3];
+        uart_rx_2_sel <= reg_wdata[0+:3];
       end
     end
   end
@@ -8127,8 +5747,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 128 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8136,7 +5756,7 @@ module pinmux
       spi_cipo_0_sel <= 4'b10;
     end else begin
       if (reg_we & spi_cipo_0_sel_addressed) begin
-        spi_cipo_0_sel <= reg_wdata[24+:4];
+        spi_cipo_0_sel <= reg_wdata[8+:4];
       end
     end
   end
@@ -8163,8 +5783,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 132 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -8172,7 +5792,7 @@ module pinmux
       spi_cipo_1_sel <= 4'b10;
     end else begin
       if (reg_we & spi_cipo_1_sel_addressed) begin
-        spi_cipo_1_sel <= reg_wdata[0+:4];
+        spi_cipo_1_sel <= reg_wdata[16+:4];
       end
     end
   end
diff --git a/rtl/templates/pinmux.sv.tpl b/rtl/templates/pinmux.sv.tpl
index ebdcafec4..08dfe9bf1 100644
--- a/rtl/templates/pinmux.sv.tpl
+++ b/rtl/templates/pinmux.sv.tpl
@@ -168,9 +168,6 @@ module pinmux
       % for idx, pin in enumerate(possible_pins):
       ${pin.direction_prefix}from_pins_i[${pin.idx_param}]${',' if idx < len(possible_pins)-1 else ''}
       % endfor
-      % if len(possible_pins) == 0:
-      1'b${block_io.default_value}
-      % endif
     }),
     .sel_i(${block_io.name}_sel),
     .out_o(${block_io.uid.block}_${block_io.uid.io}_o[${block_io.uid.instance}]${block_io.io_idx_str})
diff --git a/sw/cheri/common/platform-pinmux.hh b/sw/cheri/common/platform-pinmux.hh
index d3d128083..c197fc871 100644
--- a/sw/cheri/common/platform-pinmux.hh
+++ b/sw/cheri/common/platform-pinmux.hh
@@ -168,111 +168,41 @@ class SonataPinmux : private utils::NoCopyNoMove {
     gpio_0_ios_25 = 0x819,
     gpio_0_ios_26 = 0x81a,
     gpio_0_ios_27 = 0x81b,
-    gpio_0_ios_28 = 0x81c,
-    gpio_0_ios_29 = 0x81d,
-    gpio_0_ios_30 = 0x81e,
-    gpio_0_ios_31 = 0x81f,
-    gpio_1_ios_0  = 0x820,
-    gpio_1_ios_1  = 0x821,
-    gpio_1_ios_2  = 0x822,
-    gpio_1_ios_3  = 0x823,
-    gpio_1_ios_4  = 0x824,
-    gpio_1_ios_5  = 0x825,
-    gpio_1_ios_6  = 0x826,
-    gpio_1_ios_7  = 0x827,
-    gpio_1_ios_8  = 0x828,
-    gpio_1_ios_9  = 0x829,
-    gpio_1_ios_10 = 0x82a,
-    gpio_1_ios_11 = 0x82b,
-    gpio_1_ios_12 = 0x82c,
-    gpio_1_ios_13 = 0x82d,
-    gpio_1_ios_14 = 0x82e,
-    gpio_1_ios_15 = 0x82f,
-    gpio_1_ios_16 = 0x830,
-    gpio_1_ios_17 = 0x831,
-    gpio_1_ios_18 = 0x832,
-    gpio_1_ios_19 = 0x833,
-    gpio_1_ios_20 = 0x834,
-    gpio_1_ios_21 = 0x835,
-    gpio_1_ios_22 = 0x836,
-    gpio_1_ios_23 = 0x837,
-    gpio_1_ios_24 = 0x838,
-    gpio_1_ios_25 = 0x839,
-    gpio_1_ios_26 = 0x83a,
-    gpio_1_ios_27 = 0x83b,
-    gpio_1_ios_28 = 0x83c,
-    gpio_1_ios_29 = 0x83d,
-    gpio_1_ios_30 = 0x83e,
-    gpio_1_ios_31 = 0x83f,
-    gpio_2_ios_0  = 0x840,
-    gpio_2_ios_1  = 0x841,
-    gpio_2_ios_2  = 0x842,
-    gpio_2_ios_3  = 0x843,
-    gpio_2_ios_4  = 0x844,
-    gpio_2_ios_5  = 0x845,
-    gpio_2_ios_6  = 0x846,
-    gpio_2_ios_7  = 0x847,
-    gpio_2_ios_8  = 0x848,
-    gpio_2_ios_9  = 0x849,
-    gpio_2_ios_10 = 0x84a,
-    gpio_2_ios_11 = 0x84b,
-    gpio_2_ios_12 = 0x84c,
-    gpio_2_ios_13 = 0x84d,
-    gpio_2_ios_14 = 0x84e,
-    gpio_2_ios_15 = 0x84f,
-    gpio_2_ios_16 = 0x850,
-    gpio_2_ios_17 = 0x851,
-    gpio_2_ios_18 = 0x852,
-    gpio_2_ios_19 = 0x853,
-    gpio_2_ios_20 = 0x854,
-    gpio_2_ios_21 = 0x855,
-    gpio_2_ios_22 = 0x856,
-    gpio_2_ios_23 = 0x857,
-    gpio_2_ios_24 = 0x858,
-    gpio_2_ios_25 = 0x859,
-    gpio_2_ios_26 = 0x85a,
-    gpio_2_ios_27 = 0x85b,
-    gpio_2_ios_28 = 0x85c,
-    gpio_2_ios_29 = 0x85d,
-    gpio_2_ios_30 = 0x85e,
-    gpio_2_ios_31 = 0x85f,
-    gpio_3_ios_0  = 0x860,
-    gpio_3_ios_1  = 0x861,
-    gpio_3_ios_2  = 0x862,
-    gpio_3_ios_3  = 0x863,
-    gpio_3_ios_4  = 0x864,
-    gpio_3_ios_5  = 0x865,
-    gpio_3_ios_6  = 0x866,
-    gpio_3_ios_7  = 0x867,
-    gpio_3_ios_8  = 0x868,
-    gpio_3_ios_9  = 0x869,
-    gpio_3_ios_10 = 0x86a,
-    gpio_3_ios_11 = 0x86b,
-    gpio_3_ios_12 = 0x86c,
-    gpio_3_ios_13 = 0x86d,
-    gpio_3_ios_14 = 0x86e,
-    gpio_3_ios_15 = 0x86f,
-    gpio_3_ios_16 = 0x870,
-    gpio_3_ios_17 = 0x871,
-    gpio_3_ios_18 = 0x872,
-    gpio_3_ios_19 = 0x873,
-    gpio_3_ios_20 = 0x874,
-    gpio_3_ios_21 = 0x875,
-    gpio_3_ios_22 = 0x876,
-    gpio_3_ios_23 = 0x877,
-    gpio_3_ios_24 = 0x878,
-    gpio_3_ios_25 = 0x879,
-    gpio_3_ios_26 = 0x87a,
-    gpio_3_ios_27 = 0x87b,
-    gpio_3_ios_28 = 0x87c,
-    gpio_3_ios_29 = 0x87d,
-    gpio_3_ios_30 = 0x87e,
-    gpio_3_ios_31 = 0x87f,
-    uart_0_rx     = 0x880,
-    uart_1_rx     = 0x881,
-    uart_2_rx     = 0x882,
-    spi_0_cipo    = 0x883,
-    spi_1_cipo    = 0x884,
+    gpio_1_ios_0  = 0x81c,
+    gpio_1_ios_1  = 0x81d,
+    gpio_1_ios_2  = 0x81e,
+    gpio_1_ios_3  = 0x81f,
+    gpio_1_ios_4  = 0x820,
+    gpio_1_ios_5  = 0x821,
+    gpio_1_ios_6  = 0x822,
+    gpio_1_ios_7  = 0x823,
+    gpio_1_ios_8  = 0x824,
+    gpio_1_ios_9  = 0x825,
+    gpio_1_ios_10 = 0x826,
+    gpio_1_ios_11 = 0x827,
+    gpio_1_ios_12 = 0x828,
+    gpio_1_ios_13 = 0x829,
+    gpio_2_ios_0  = 0x82a,
+    gpio_2_ios_1  = 0x82b,
+    gpio_2_ios_2  = 0x82c,
+    gpio_2_ios_3  = 0x82d,
+    gpio_2_ios_4  = 0x82e,
+    gpio_2_ios_5  = 0x82f,
+    gpio_2_ios_6  = 0x830,
+    gpio_2_ios_7  = 0x831,
+    gpio_3_ios_0  = 0x832,
+    gpio_3_ios_1  = 0x833,
+    gpio_3_ios_2  = 0x834,
+    gpio_3_ios_3  = 0x835,
+    gpio_3_ios_4  = 0x836,
+    gpio_3_ios_5  = 0x837,
+    gpio_3_ios_6  = 0x838,
+    gpio_3_ios_7  = 0x839,
+    uart_0_rx     = 0x83a,
+    uart_1_rx     = 0x83b,
+    uart_2_rx     = 0x83c,
+    spi_0_cipo    = 0x83d,
+    spi_1_cipo    = 0x83e,
   };
 
   /**
diff --git a/util/top_gen/generator.py b/util/top_gen/generator.py
index c4c224580..bbbf82b07 100644
--- a/util/top_gen/generator.py
+++ b/util/top_gen/generator.py
@@ -231,6 +231,9 @@ def output_block_ios_iter(
 
         possible_pins = block_io_to_pins[block_io.uid]
 
+        if len(possible_pins) == 0:
+            continue
+
         yield OutputBlockIo(
             block_io,
             possible_pins,

From c27d4cddaa0f9465c1929602bc5c19b31e4469ea Mon Sep 17 00:00:00 2001
From: Marno van der Maas <mvdmaas+git@lowrisc.org>
Date: Fri, 1 Nov 2024 11:46:15 +0000
Subject: [PATCH 08/21] Pinmapping uart and spi fixup

---
 data/top_config.toml               | 14 +++++++++----
 doc/ip/pinmux/README.md            |  8 ++++----
 rtl/system/pinmux.sv               | 33 ++++++++++++++++--------------
 sw/cheri/common/platform-pinmux.hh |  4 ++--
 4 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/data/top_config.toml b/data/top_config.toml
index d5bf82ccd..f62c4294c 100644
--- a/data/top_config.toml
+++ b/data/top_config.toml
@@ -65,11 +65,17 @@ block_ios = [{ block = "uart", instance = 0, io = "rx" }]
 
 [[pins]]
 name = "ser1_tx"
-block_ios = [{ block = "uart", instance = 1, io = "tx" }]
+block_ios = [
+  { block = "uart", instance = 1, io = "tx" },
+  { block = "uart", instance = 2, io = "tx" },
+]
 
 [[pins]]
 name = "ser1_rx"
-block_ios = [{ block = "uart", instance = 1, io = "rx" }]
+block_ios = [
+  { block = "uart", instance = 1, io = "rx" },
+  { block = "uart", instance = 2, io = "rx" },
+]
 
 [[pins]]
 name = "rs232_tx"
@@ -141,14 +147,14 @@ block_ios = [{block = "gpio", instance = 0, io = "ios", io_index = 6}]
 [[pins]]
 name = "rph_g7_ce1"
 block_ios = [
-  {block = "spi", instance = 0, io = "cs", io_index = 0},
+  {block = "spi", instance = 0, io = "cs", io_index = 1},
   {block = "gpio", instance = 0, io = "ios", io_index = 7},
 ]
 
 [[pins]]
 name = "rph_g8_ce0"
 block_ios = [
-  {block = "spi", instance = 0, io = "cs", io_index = 1},
+  {block = "spi", instance = 0, io = "cs", io_index = 0},
   {block = "gpio", instance = 0, io = "ios", io_index = 8},
 ]
 
diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index b6ae95fe5..1fb58427f 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -13,7 +13,7 @@ The default value for all of these selectors is `'b10`.
 | Address | Pin output | Possible block outputs |
 |---------|------------|------------------------|
 | 0x000 | `ser0_tx` | 0, `uart[0].tx` |
-| 0x001 | `ser1_tx` | 0, `uart[1].tx` |
+| 0x001 | `ser1_tx` | 0, `uart[1].tx`, `uart[2].tx` |
 | 0x002 | `rs232_tx` | 0, `uart[2].tx` |
 | 0x003 | `scl0` | 0, `i2c[0].scl` |
 | 0x004 | `sda0` | 0, `i2c[0].sda` |
@@ -26,8 +26,8 @@ The default value for all of these selectors is `'b10`.
 | 0x00b | `rph_g4` | 0, `gpio[0].ios[4]` |
 | 0x00c | `rph_g5` | 0, `gpio[0].ios[5]` |
 | 0x00d | `rph_g6` | 0, `gpio[0].ios[6]` |
-| 0x00e | `rph_g7_ce1` | 0, `spi[0].cs[0]`, `gpio[0].ios[7]` |
-| 0x00f | `rph_g8_ce0` | 0, `spi[0].cs[1]`, `gpio[0].ios[8]` |
+| 0x00e | `rph_g7_ce1` | 0, `spi[0].cs[1]`, `gpio[0].ios[7]` |
+| 0x00f | `rph_g8_ce0` | 0, `spi[0].cs[0]`, `gpio[0].ios[8]` |
 | 0x010 | `rph_g9_cipo` | 0, `gpio[0].ios[9]` |
 | 0x011 | `rph_g10_copi` | 0, `spi[0].copi`, `gpio[0].ios[10]` |
 | 0x012 | `rph_g11_sclk` | 0, `spi[0].sclk`, `gpio[0].ios[11]` |
@@ -149,7 +149,7 @@ Besides the output pin selectors, there are also selectors for which pin should
 | 0x839 | `gpio[3].ios[7]` | 0, `pmod1_8` |
 | 0x83a | `uart[0].rx` | 1, `ser0_rx` |
 | 0x83b | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
-| 0x83c | `uart[2].rx` | 1, `rs232_rx`, `pmod1_3` |
+| 0x83c | `uart[2].rx` | 1, `ser1_rx`, `rs232_rx`, `pmod1_3` |
 | 0x83d | `spi[0].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
 | 0x83e | `spi[1].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3` |
 
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index c7d9be5b8..aeeacb26c 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -152,7 +152,7 @@ module pinmux
     .out_o(out_to_pins_en_o[OUT_PIN_SER0_TX])
   );
 
-  logic [1:0] ser1_tx_sel;
+  logic [2:0] ser1_tx_sel;
   logic ser1_tx_sel_addressed;
 
   // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
@@ -164,23 +164,24 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      ser1_tx_sel <= 2'b10;
+      ser1_tx_sel <= 3'b10;
     end else begin
       if (reg_we & ser1_tx_sel_addressed) begin
-        ser1_tx_sel <= reg_wdata[8+:2];
+        ser1_tx_sel <= reg_wdata[8+:3];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ser1_tx_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      uart_tx_i[1]
+      uart_tx_i[1],
+      uart_tx_i[2]
     }),
     .sel_i(ser1_tx_sel),
     .out_o(out_to_pins_o[OUT_PIN_SER1_TX])
@@ -188,13 +189,14 @@ module pinmux
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(2)
+    .Inputs(3)
   ) ser1_tx_enable_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b0,
-      uart_tx_en_i[1]
+      uart_tx_en_i[1],
+      uart_tx_en_i[2]
     }),
     .sel_i(ser1_tx_sel),
     .out_o(out_to_pins_en_o[OUT_PIN_SER1_TX])
@@ -812,7 +814,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[0][0],
+      spi_cs_i[0][1],
       gpio_ios_i[0][7]
     }),
     .sel_i(rph_g7_ce1_sel),
@@ -827,7 +829,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[0][0],
+      spi_cs_en_i[0][1],
       gpio_ios_en_i[0][7]
     }),
     .sel_i(rph_g7_ce1_sel),
@@ -862,7 +864,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0, // This is set to Z later when output enable is low.
-      spi_cs_i[0][1],
+      spi_cs_i[0][0],
       gpio_ios_i[0][8]
     }),
     .sel_i(rph_g8_ce0_sel),
@@ -877,7 +879,7 @@ module pinmux
     .rst_ni,
     .in_i({
       1'b0,
-      spi_cs_en_i[0][1],
+      spi_cs_en_i[0][0],
       gpio_ios_en_i[0][8]
     }),
     .sel_i(rph_g8_ce0_sel),
@@ -5706,7 +5708,7 @@ module pinmux
     .out_o(uart_rx_o[1])
   );
 
-  logic [2:0] uart_rx_2_sel;
+  logic [3:0] uart_rx_2_sel;
   logic uart_rx_2_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
@@ -5718,22 +5720,23 @@ module pinmux
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       // Select second input by default so that pins are connected to the first block that is specified in the configuration.
-      uart_rx_2_sel <= 3'b10;
+      uart_rx_2_sel <= 4'b10;
     end else begin
       if (reg_we & uart_rx_2_sel_addressed) begin
-        uart_rx_2_sel <= reg_wdata[0+:3];
+        uart_rx_2_sel <= reg_wdata[0+:4];
       end
     end
   end
 
   prim_onehot_mux #(
     .Width(1),
-    .Inputs(3)
+    .Inputs(4)
   ) uart_rx_2_mux (
     .clk_i,
     .rst_ni,
     .in_i({
       1'b1,
+      in_from_pins_i[IN_PIN_SER1_RX],
       in_from_pins_i[IN_PIN_RS232_RX],
       inout_from_pins_i[INOUT_PIN_PMOD1_3]
     }),
diff --git a/sw/cheri/common/platform-pinmux.hh b/sw/cheri/common/platform-pinmux.hh
index c197fc871..411af76bb 100644
--- a/sw/cheri/common/platform-pinmux.hh
+++ b/sw/cheri/common/platform-pinmux.hh
@@ -230,6 +230,7 @@ class SonataPinmux : private utils::NoCopyNoMove {
       case OutputPin::pmod0_4:
       case OutputPin::pmod1_4:
         return 4;
+      case OutputPin::ser1_tx:
       case OutputPin::rph_g0:
       case OutputPin::rph_g1:
       case OutputPin::rph_g2_sda:
@@ -282,11 +283,10 @@ class SonataPinmux : private utils::NoCopyNoMove {
     switch (block_input) {
       case BlockInput::uart_1_rx:
         return 6;
+      case BlockInput::uart_2_rx:
       case BlockInput::spi_0_cipo:
       case BlockInput::spi_1_cipo:
         return 4;
-      case BlockInput::uart_2_rx:
-        return 3;
       default:
         return 2;
     }

From cb76457cc1d0ce0ac91ed64a4d08e28cc50b3020 Mon Sep 17 00:00:00 2001
From: Hugo McNally <hugo.mcnally@gmail.com>
Date: Fri, 1 Nov 2024 11:45:15 +0000
Subject: [PATCH 09/21] top: added the pmodc gpio block and pins

---
 data/top_config.toml               |  27 +-
 doc/ip/pinmux/README.md            |  22 +-
 rtl/fpga/top_sonata.sv             |   2 +
 rtl/system/pinmux.sv               | 522 ++++++++++++++++++++++++++++-
 rtl/system/sonata_pkg.sv           |  10 +-
 sw/cheri/common/platform-pinmux.hh |  22 +-
 6 files changed, 577 insertions(+), 28 deletions(-)

diff --git a/data/top_config.toml b/data/top_config.toml
index f62c4294c..da3e0adea 100644
--- a/data/top_config.toml
+++ b/data/top_config.toml
@@ -1,6 +1,6 @@
 [[blocks]]
 name = "gpio"
-instances = 4 # RPi, Ard, Pmod0, Pmod1
+instances = 5 # RPi, Ard, Pmod0, Pmod1, PmodC
 ios = [
   {
     name = "ios",
@@ -520,3 +520,28 @@ block_ios = [
   {block = "gpio", instance = 3, io = "ios", io_index = 7},
   {block = "spi", instance = 1, io = "cs", io_index = 2},
 ]
+
+
+[[pins]]
+name = "pmodc_1"
+block_ios = [{block = "gpio", instance = 4, io = "ios", io_index = 0}]
+
+[[pins]]
+name = "pmodc_2"
+block_ios = [{block = "gpio", instance = 4, io = "ios", io_index = 1}]
+
+[[pins]]
+name = "pmodc_3"
+block_ios = [{block = "gpio", instance = 4, io = "ios", io_index = 2}]
+
+[[pins]]
+name = "pmodc_4"
+block_ios = [{block = "gpio", instance = 4, io = "ios", io_index = 3}]
+
+[[pins]]
+name = "pmodc_5"
+block_ios = [{block = "gpio", instance = 4, io = "ios", io_index = 4}]
+
+[[pins]]
+name = "pmodc_6"
+block_ios = [{block = "gpio", instance = 4, io = "ios", io_index = 5}]
diff --git a/doc/ip/pinmux/README.md b/doc/ip/pinmux/README.md
index 1fb58427f..700e06ad3 100644
--- a/doc/ip/pinmux/README.md
+++ b/doc/ip/pinmux/README.md
@@ -84,6 +84,12 @@ The default value for all of these selectors is `'b10`.
 | 0x045 | `pmod1_6` | 0, `gpio[3].ios[5]`, `pwm_out[4]` |
 | 0x046 | `pmod1_7` | 0, `gpio[3].ios[6]`, `spi[1].cs[1]` |
 | 0x047 | `pmod1_8` | 0, `gpio[3].ios[7]`, `spi[1].cs[2]` |
+| 0x048 | `pmodc_1` | 0, `gpio[4].ios[0]` |
+| 0x049 | `pmodc_2` | 0, `gpio[4].ios[1]` |
+| 0x04a | `pmodc_3` | 0, `gpio[4].ios[2]` |
+| 0x04b | `pmodc_4` | 0, `gpio[4].ios[3]` |
+| 0x04c | `pmodc_5` | 0, `gpio[4].ios[4]` |
+| 0x04d | `pmodc_6` | 0, `gpio[4].ios[5]` |
 
 Besides the output pin selectors, there are also selectors for which pin should drive block inputs:
 
@@ -147,11 +153,17 @@ Besides the output pin selectors, there are also selectors for which pin should
 | 0x837 | `gpio[3].ios[5]` | 0, `pmod1_6` |
 | 0x838 | `gpio[3].ios[6]` | 0, `pmod1_7` |
 | 0x839 | `gpio[3].ios[7]` | 0, `pmod1_8` |
-| 0x83a | `uart[0].rx` | 1, `ser0_rx` |
-| 0x83b | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
-| 0x83c | `uart[2].rx` | 1, `ser1_rx`, `rs232_rx`, `pmod1_3` |
-| 0x83d | `spi[0].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
-| 0x83e | `spi[1].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3` |
+| 0x83a | `gpio[4].ios[0]` | 0, `pmodc_1` |
+| 0x83b | `gpio[4].ios[1]` | 0, `pmodc_2` |
+| 0x83c | `gpio[4].ios[2]` | 0, `pmodc_3` |
+| 0x83d | `gpio[4].ios[3]` | 0, `pmodc_4` |
+| 0x83e | `gpio[4].ios[4]` | 0, `pmodc_5` |
+| 0x83f | `gpio[4].ios[5]` | 0, `pmodc_6` |
+| 0x840 | `uart[0].rx` | 1, `ser0_rx` |
+| 0x841 | `uart[1].rx` | 1, `ser1_rx`, `rph_rxd0`, `ah_tmpio0`, `mb8`, `pmod0_3` |
+| 0x842 | `uart[2].rx` | 1, `ser1_rx`, `rs232_rx`, `pmod1_3` |
+| 0x843 | `spi[0].cipo` | 0, `rph_g9_cipo`, `ah_tmpio12`, `pmod0_3` |
+| 0x844 | `spi[1].cipo` | 0, `rph_g19_cipo`, `mb3`, `pmod1_3` |
 
 ## Regeneration
 
diff --git a/rtl/fpga/top_sonata.sv b/rtl/fpga/top_sonata.sv
index 8fca22684..0ccf399a1 100644
--- a/rtl/fpga/top_sonata.sv
+++ b/rtl/fpga/top_sonata.sv
@@ -140,6 +140,7 @@ module top_sonata
   // PMODs
   inout  logic [7:0] pmod0,
   inout  logic [7:0] pmod1,
+  inout  logic [5:0] pmodc,
 
   // Status input from USB transceiver
   input  logic       usrusb_vbusdetect,
@@ -437,6 +438,7 @@ module top_sonata
     .inout_to_pins_en_i(inout_to_pins_en),
     .inout_from_pins_o (inout_from_pins ),
     .inout_pins_io({
+      pmodc,
       pmod1,
       pmod0,
       mb6,
diff --git a/rtl/system/pinmux.sv b/rtl/system/pinmux.sv
index aeeacb26c..512264b0a 100644
--- a/rtl/system/pinmux.sv
+++ b/rtl/system/pinmux.sv
@@ -3662,6 +3662,294 @@ module pinmux
     .out_o(inout_to_pins_en_o[INOUT_PIN_PMOD1_8])
   );
 
+  logic [1:0] pmodc_1_sel;
+  logic pmodc_1_sel_addressed;
+
+  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
+  assign pmodc_1_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b0 &
+    reg_addr[RegAddrWidth-2:0] == 72 &
+    reg_be[0] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      pmodc_1_sel <= 2'b10;
+    end else begin
+      if (reg_we & pmodc_1_sel_addressed) begin
+        pmodc_1_sel <= reg_wdata[0+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_1_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0, // This is set to Z later when output enable is low.
+      gpio_ios_i[4][0]
+    }),
+    .sel_i(pmodc_1_sel),
+    .out_o(inout_to_pins_o[INOUT_PIN_PMODC_1])
+  );
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_1_enable_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      gpio_ios_en_i[4][0]
+    }),
+    .sel_i(pmodc_1_sel),
+    .out_o(inout_to_pins_en_o[INOUT_PIN_PMODC_1])
+  );
+
+  logic [1:0] pmodc_2_sel;
+  logic pmodc_2_sel_addressed;
+
+  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
+  assign pmodc_2_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b0 &
+    reg_addr[RegAddrWidth-2:0] == 72 &
+    reg_be[1] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      pmodc_2_sel <= 2'b10;
+    end else begin
+      if (reg_we & pmodc_2_sel_addressed) begin
+        pmodc_2_sel <= reg_wdata[8+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_2_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0, // This is set to Z later when output enable is low.
+      gpio_ios_i[4][1]
+    }),
+    .sel_i(pmodc_2_sel),
+    .out_o(inout_to_pins_o[INOUT_PIN_PMODC_2])
+  );
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_2_enable_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      gpio_ios_en_i[4][1]
+    }),
+    .sel_i(pmodc_2_sel),
+    .out_o(inout_to_pins_en_o[INOUT_PIN_PMODC_2])
+  );
+
+  logic [1:0] pmodc_3_sel;
+  logic pmodc_3_sel_addressed;
+
+  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
+  assign pmodc_3_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b0 &
+    reg_addr[RegAddrWidth-2:0] == 72 &
+    reg_be[2] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      pmodc_3_sel <= 2'b10;
+    end else begin
+      if (reg_we & pmodc_3_sel_addressed) begin
+        pmodc_3_sel <= reg_wdata[16+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_3_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0, // This is set to Z later when output enable is low.
+      gpio_ios_i[4][2]
+    }),
+    .sel_i(pmodc_3_sel),
+    .out_o(inout_to_pins_o[INOUT_PIN_PMODC_3])
+  );
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_3_enable_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      gpio_ios_en_i[4][2]
+    }),
+    .sel_i(pmodc_3_sel),
+    .out_o(inout_to_pins_en_o[INOUT_PIN_PMODC_3])
+  );
+
+  logic [1:0] pmodc_4_sel;
+  logic pmodc_4_sel_addressed;
+
+  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
+  assign pmodc_4_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b0 &
+    reg_addr[RegAddrWidth-2:0] == 72 &
+    reg_be[3] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      pmodc_4_sel <= 2'b10;
+    end else begin
+      if (reg_we & pmodc_4_sel_addressed) begin
+        pmodc_4_sel <= reg_wdata[24+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_4_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0, // This is set to Z later when output enable is low.
+      gpio_ios_i[4][3]
+    }),
+    .sel_i(pmodc_4_sel),
+    .out_o(inout_to_pins_o[INOUT_PIN_PMODC_4])
+  );
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_4_enable_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      gpio_ios_en_i[4][3]
+    }),
+    .sel_i(pmodc_4_sel),
+    .out_o(inout_to_pins_en_o[INOUT_PIN_PMODC_4])
+  );
+
+  logic [1:0] pmodc_5_sel;
+  logic pmodc_5_sel_addressed;
+
+  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
+  assign pmodc_5_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b0 &
+    reg_addr[RegAddrWidth-2:0] == 76 &
+    reg_be[0] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      pmodc_5_sel <= 2'b10;
+    end else begin
+      if (reg_we & pmodc_5_sel_addressed) begin
+        pmodc_5_sel <= reg_wdata[0+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_5_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0, // This is set to Z later when output enable is low.
+      gpio_ios_i[4][4]
+    }),
+    .sel_i(pmodc_5_sel),
+    .out_o(inout_to_pins_o[INOUT_PIN_PMODC_5])
+  );
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_5_enable_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      gpio_ios_en_i[4][4]
+    }),
+    .sel_i(pmodc_5_sel),
+    .out_o(inout_to_pins_en_o[INOUT_PIN_PMODC_5])
+  );
+
+  logic [1:0] pmodc_6_sel;
+  logic pmodc_6_sel_addressed;
+
+  // Register addresses of 0x000 to 0x7ff are pin selectors, which are packed with 4 per 32-bit word.
+  assign pmodc_6_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b0 &
+    reg_addr[RegAddrWidth-2:0] == 76 &
+    reg_be[1] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      pmodc_6_sel <= 2'b10;
+    end else begin
+      if (reg_we & pmodc_6_sel_addressed) begin
+        pmodc_6_sel <= reg_wdata[8+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_6_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0, // This is set to Z later when output enable is low.
+      gpio_ios_i[4][5]
+    }),
+    .sel_i(pmodc_6_sel),
+    .out_o(inout_to_pins_o[INOUT_PIN_PMODC_6])
+  );
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) pmodc_6_enable_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      gpio_ios_en_i[4][5]
+    }),
+    .sel_i(pmodc_6_sel),
+    .out_o(inout_to_pins_en_o[INOUT_PIN_PMODC_6])
+  );
+
   // Inputs - Physical pin inputs are muxed to particular block IO
 
   logic [1:0] gpio_ios_0_0_sel;
@@ -5636,14 +5924,218 @@ module pinmux
     .out_o(gpio_ios_o[3][7])
   );
 
+  logic [1:0] gpio_ios_4_0_sel;
+  logic gpio_ios_4_0_sel_addressed;
+
+  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
+  assign gpio_ios_4_0_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b1 &
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[2] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      gpio_ios_4_0_sel <= 2'b10;
+    end else begin
+      if (reg_we & gpio_ios_4_0_sel_addressed) begin
+        gpio_ios_4_0_sel <= reg_wdata[16+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) gpio_ios_4_0_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      inout_from_pins_i[INOUT_PIN_PMODC_1]
+    }),
+    .sel_i(gpio_ios_4_0_sel),
+    .out_o(gpio_ios_o[4][0])
+  );
+
+  logic [1:0] gpio_ios_4_1_sel;
+  logic gpio_ios_4_1_sel_addressed;
+
+  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
+  assign gpio_ios_4_1_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b1 &
+    reg_addr[RegAddrWidth-2:0] == 56 &
+    reg_be[3] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      gpio_ios_4_1_sel <= 2'b10;
+    end else begin
+      if (reg_we & gpio_ios_4_1_sel_addressed) begin
+        gpio_ios_4_1_sel <= reg_wdata[24+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) gpio_ios_4_1_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      inout_from_pins_i[INOUT_PIN_PMODC_2]
+    }),
+    .sel_i(gpio_ios_4_1_sel),
+    .out_o(gpio_ios_o[4][1])
+  );
+
+  logic [1:0] gpio_ios_4_2_sel;
+  logic gpio_ios_4_2_sel_addressed;
+
+  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
+  assign gpio_ios_4_2_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b1 &
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[0] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      gpio_ios_4_2_sel <= 2'b10;
+    end else begin
+      if (reg_we & gpio_ios_4_2_sel_addressed) begin
+        gpio_ios_4_2_sel <= reg_wdata[0+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) gpio_ios_4_2_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      inout_from_pins_i[INOUT_PIN_PMODC_3]
+    }),
+    .sel_i(gpio_ios_4_2_sel),
+    .out_o(gpio_ios_o[4][2])
+  );
+
+  logic [1:0] gpio_ios_4_3_sel;
+  logic gpio_ios_4_3_sel_addressed;
+
+  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
+  assign gpio_ios_4_3_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b1 &
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[1] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      gpio_ios_4_3_sel <= 2'b10;
+    end else begin
+      if (reg_we & gpio_ios_4_3_sel_addressed) begin
+        gpio_ios_4_3_sel <= reg_wdata[8+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) gpio_ios_4_3_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      inout_from_pins_i[INOUT_PIN_PMODC_4]
+    }),
+    .sel_i(gpio_ios_4_3_sel),
+    .out_o(gpio_ios_o[4][3])
+  );
+
+  logic [1:0] gpio_ios_4_4_sel;
+  logic gpio_ios_4_4_sel_addressed;
+
+  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
+  assign gpio_ios_4_4_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b1 &
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[2] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      gpio_ios_4_4_sel <= 2'b10;
+    end else begin
+      if (reg_we & gpio_ios_4_4_sel_addressed) begin
+        gpio_ios_4_4_sel <= reg_wdata[16+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) gpio_ios_4_4_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      inout_from_pins_i[INOUT_PIN_PMODC_5]
+    }),
+    .sel_i(gpio_ios_4_4_sel),
+    .out_o(gpio_ios_o[4][4])
+  );
+
+  logic [1:0] gpio_ios_4_5_sel;
+  logic gpio_ios_4_5_sel_addressed;
+
+  // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
+  assign gpio_ios_4_5_sel_addressed =
+    reg_addr[RegAddrWidth-1] == 1'b1 &
+    reg_addr[RegAddrWidth-2:0] == 60 &
+    reg_be[3] == 1'b1;
+
+  always @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      // Select second input by default so that pins are connected to the first block that is specified in the configuration.
+      gpio_ios_4_5_sel <= 2'b10;
+    end else begin
+      if (reg_we & gpio_ios_4_5_sel_addressed) begin
+        gpio_ios_4_5_sel <= reg_wdata[24+:2];
+      end
+    end
+  end
+
+  prim_onehot_mux #(
+    .Width(1),
+    .Inputs(2)
+  ) gpio_ios_4_5_mux (
+    .clk_i,
+    .rst_ni,
+    .in_i({
+      1'b0,
+      inout_from_pins_i[INOUT_PIN_PMODC_6]
+    }),
+    .sel_i(gpio_ios_4_5_sel),
+    .out_o(gpio_ios_o[4][5])
+  );
+
   logic [1:0] uart_rx_0_sel;
   logic uart_rx_0_sel_addressed;
 
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign uart_rx_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -5651,7 +6143,7 @@ module pinmux
       uart_rx_0_sel <= 2'b10;
     end else begin
       if (reg_we & uart_rx_0_sel_addressed) begin
-        uart_rx_0_sel <= reg_wdata[16+:2];
+        uart_rx_0_sel <= reg_wdata[0+:2];
       end
     end
   end
@@ -5676,8 +6168,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign uart_rx_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 56 &
-    reg_be[3] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[1] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -5685,7 +6177,7 @@ module pinmux
       uart_rx_1_sel <= 6'b10;
     end else begin
       if (reg_we & uart_rx_1_sel_addressed) begin
-        uart_rx_1_sel <= reg_wdata[24+:6];
+        uart_rx_1_sel <= reg_wdata[8+:6];
       end
     end
   end
@@ -5714,8 +6206,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign uart_rx_2_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[0] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[2] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -5723,7 +6215,7 @@ module pinmux
       uart_rx_2_sel <= 4'b10;
     end else begin
       if (reg_we & uart_rx_2_sel_addressed) begin
-        uart_rx_2_sel <= reg_wdata[0+:4];
+        uart_rx_2_sel <= reg_wdata[16+:4];
       end
     end
   end
@@ -5750,8 +6242,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_0_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[1] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 64 &
+    reg_be[3] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -5759,7 +6251,7 @@ module pinmux
       spi_cipo_0_sel <= 4'b10;
     end else begin
       if (reg_we & spi_cipo_0_sel_addressed) begin
-        spi_cipo_0_sel <= reg_wdata[8+:4];
+        spi_cipo_0_sel <= reg_wdata[24+:4];
       end
     end
   end
@@ -5786,8 +6278,8 @@ module pinmux
   // Register addresses of 0x800 to 0xfff are block IO selectors, which are packed with 4 per 32-bit word.
   assign spi_cipo_1_sel_addressed =
     reg_addr[RegAddrWidth-1] == 1'b1 &
-    reg_addr[RegAddrWidth-2:0] == 60 &
-    reg_be[2] == 1'b1;
+    reg_addr[RegAddrWidth-2:0] == 68 &
+    reg_be[0] == 1'b1;
 
   always @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -5795,7 +6287,7 @@ module pinmux
       spi_cipo_1_sel <= 4'b10;
     end else begin
       if (reg_we & spi_cipo_1_sel_addressed) begin
-        spi_cipo_1_sel <= reg_wdata[16+:4];
+        spi_cipo_1_sel <= reg_wdata[0+:4];
       end
     end
   end
diff --git a/rtl/system/sonata_pkg.sv b/rtl/system/sonata_pkg.sv
index 55e95ecf7..0e7361317 100644
--- a/rtl/system/sonata_pkg.sv
+++ b/rtl/system/sonata_pkg.sv
@@ -7,7 +7,7 @@
 package sonata_pkg;
 
   // Number of Instances
-  localparam int unsigned GPIO_NUM = 4;
+  localparam int unsigned GPIO_NUM = 5;
   localparam int unsigned PWM_NUM = 1;
   localparam int unsigned UART_NUM = 3;
   localparam int unsigned I2C_NUM = 2;
@@ -21,7 +21,7 @@ package sonata_pkg;
   // Number of input, output, and inout pins
   localparam int unsigned IN_PIN_NUM = 5;
   localparam int unsigned OUT_PIN_NUM = 8;
-  localparam int unsigned INOUT_PIN_NUM = 64;
+  localparam int unsigned INOUT_PIN_NUM = 70;
 
   localparam int unsigned IN_PIN_SER0_RX = 0;
   localparam int unsigned IN_PIN_SER1_RX = 1;
@@ -102,6 +102,12 @@ package sonata_pkg;
   localparam int unsigned INOUT_PIN_PMOD1_6 = 61;
   localparam int unsigned INOUT_PIN_PMOD1_7 = 62;
   localparam int unsigned INOUT_PIN_PMOD1_8 = 63;
+  localparam int unsigned INOUT_PIN_PMODC_1 = 64;
+  localparam int unsigned INOUT_PIN_PMODC_2 = 65;
+  localparam int unsigned INOUT_PIN_PMODC_3 = 66;
+  localparam int unsigned INOUT_PIN_PMODC_4 = 67;
+  localparam int unsigned INOUT_PIN_PMODC_5 = 68;
+  localparam int unsigned INOUT_PIN_PMODC_6 = 69;
 
   typedef logic [   IN_PIN_NUM-1:0] sonata_in_pins_t;
   typedef logic [  OUT_PIN_NUM-1:0] sonata_out_pins_t;
diff --git a/sw/cheri/common/platform-pinmux.hh b/sw/cheri/common/platform-pinmux.hh
index 411af76bb..3f62aff90 100644
--- a/sw/cheri/common/platform-pinmux.hh
+++ b/sw/cheri/common/platform-pinmux.hh
@@ -123,6 +123,12 @@ class SonataPinmux : private utils::NoCopyNoMove {
     pmod1_6      = 0x045,
     pmod1_7      = 0x046,
     pmod1_8      = 0x047,
+    pmodc_1      = 0x048,
+    pmodc_2      = 0x049,
+    pmodc_3      = 0x04a,
+    pmodc_4      = 0x04b,
+    pmodc_5      = 0x04c,
+    pmodc_6      = 0x04d,
   };
 
   /**
@@ -198,11 +204,17 @@ class SonataPinmux : private utils::NoCopyNoMove {
     gpio_3_ios_5  = 0x837,
     gpio_3_ios_6  = 0x838,
     gpio_3_ios_7  = 0x839,
-    uart_0_rx     = 0x83a,
-    uart_1_rx     = 0x83b,
-    uart_2_rx     = 0x83c,
-    spi_0_cipo    = 0x83d,
-    spi_1_cipo    = 0x83e,
+    gpio_4_ios_0  = 0x83a,
+    gpio_4_ios_1  = 0x83b,
+    gpio_4_ios_2  = 0x83c,
+    gpio_4_ios_3  = 0x83d,
+    gpio_4_ios_4  = 0x83e,
+    gpio_4_ios_5  = 0x83f,
+    uart_0_rx     = 0x840,
+    uart_1_rx     = 0x841,
+    uart_2_rx     = 0x842,
+    spi_0_cipo    = 0x843,
+    spi_1_cipo    = 0x844,
   };
 
   /**

From e403668c6060b4788ead447da3b1ef6e16d1d27b Mon Sep 17 00:00:00 2001
From: Alex Jones <alex.jones@lowrisc.org>
Date: Fri, 1 Nov 2024 11:21:50 +0000
Subject: [PATCH 10/21] Update SW definitions of number of GPIO/UART/SPI

Updates the definitions of the number of GPIO, UART and SPI devices that
are available in the software definitions file for Sonata to match the
changed nubmer of devices in the new pin mapping configuration. This
commit aims to keep changes minimal to get tests passing - it does not
look at solving any other issues with e.g. outdated definitions for now.
---
 sw/cheri/common/sonata-devices.hh | 6 ++++++
 sw/common/defs.h                  | 6 +++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/sw/cheri/common/sonata-devices.hh b/sw/cheri/common/sonata-devices.hh
index 29f74809a..dd9983e80 100644
--- a/sw/cheri/common/sonata-devices.hh
+++ b/sw/cheri/common/sonata-devices.hh
@@ -54,6 +54,12 @@ typedef SonataPinmux *PinmuxPtr;
   return i2c;
 }
 
+/**
+ * Note: SPI 0 is `spi_board`, used for Ethernet/Flash/MicroSD.
+ *       SPI 1 is `spi_lcd`, used for the LCD.
+ *       SPI 2 is actually what is called SPI0, for general use.
+ *       SPI 3 is actually what is called SPI1, for general use.
+ */
 [[maybe_unused]] static SpiPtr spi_ptr(CapRoot root, uint32_t idx = 0) {
   CHERI::Capability<volatile SonataSpi> spi = root.cast<volatile SonataSpi>();
   assert(idx < SPI_NUM);
diff --git a/sw/common/defs.h b/sw/common/defs.h
index f1c83cd64..2c16bfde1 100644
--- a/sw/common/defs.h
+++ b/sw/common/defs.h
@@ -18,7 +18,7 @@
 #define SYSTEM_INFO_ADDRESS (0x8000'C000)
 #define SYSTEM_INFO_BOUNDS (0x0000'0020)
 
-#define GPIO_NUM 5
+#define GPIO_NUM 6
 #define GPIO_BOUNDS (0x0000'0010)
 #define GPIO_ADDRESS (0x8000'0000)
 #define GPIO_RANGE (0x0000'0040)
@@ -28,7 +28,7 @@
 #define PWM_BOUNDS (0x0000'0008)
 #define PWM_RANGE (0x0000'0008)
 
-#define UART_NUM 5
+#define UART_NUM 3
 #define UART_BOUNDS (0x0000'0034)
 #define UART_ADDRESS (0x8010'0000)
 #define UART_RANGE (0x0000'1000)
@@ -38,7 +38,7 @@
 #define I2C_ADDRESS (0x8020'0000)
 #define I2C_RANGE (0x0000'1000)
 
-#define SPI_NUM 5
+#define SPI_NUM 4
 #define SPI_BOUNDS (0x0000'002C)
 #define SPI_ADDRESS (0x8030'0000)
 #define SPI_RANGE (0x0000'1000)

From 97c673567700aa36fe1a002032656492b09a3e1d Mon Sep 17 00:00:00 2001
From: Alex Jones <alex.jones@lowrisc.org>
Date: Thu, 31 Oct 2024 15:18:20 +0000
Subject: [PATCH 11/21] Update manual pinmux checker for new pin mapping
 changes

Updates the manual `pinmux_checker` application along with the
`pinmux_all_blocks_check` that uses it to match the new pin mapping
changes under Pinmux for 1.0.

This involves changing the pinmux assignment for a couple of pins to
match the changed order in the pinmux config changes. It also involves
reducing the number of UARTs that can be used by the the pinmux checker
from 1-2 down from 1-4, since the overall number of UARTs has also been
reduced by recent harwdare changes, and thus these non-existent UART
devices should not be exposed.

It finally also changes the number of SPIs exposed to just SPI0 and
SPI1 which are now exposed via Pinmux, and makes the necessary changes
to pinmux checker to facilitate this.
---
 sw/cheri/checks/pinmux_all_blocks_check.cc | 30 ++++++++++------------
 sw/cheri/checks/pinmux_checker.cc          |  8 +++---
 sw/cheri/checks/pinmux_checker.hh          |  8 +++---
 3 files changed, 21 insertions(+), 25 deletions(-)

diff --git a/sw/cheri/checks/pinmux_all_blocks_check.cc b/sw/cheri/checks/pinmux_all_blocks_check.cc
index 58e478ad8..9c46efcf6 100644
--- a/sw/cheri/checks/pinmux_all_blocks_check.cc
+++ b/sw/cheri/checks/pinmux_all_blocks_check.cc
@@ -28,11 +28,9 @@ using namespace CHERI;
   // Initialise capabilities for UART0 (the console), and all other UARTS (1-4)
   UartPtr uart0 = uart_ptr(rwRoot, 0);
   uart0->init(BAUD_RATE);
-  UartPtr uarts[4] = {
+  UartPtr uarts[2] = {
       uart_ptr(rwRoot, 1),
       uart_ptr(rwRoot, 2),
-      uart_ptr(rwRoot, 3),
-      uart_ptr(rwRoot, 4),
   };
   for (UartPtr uart : uarts) {
     uart->init(BAUD_RATE);
@@ -44,8 +42,8 @@ using namespace CHERI;
 
   // Create capabilities for SPI3&4, I2C0&1, GPIO and Pinmux for use in Pinmux testing
   SpiPtr spis[2] = {
-      spi_ptr(rwRoot, 2),
-      spi_ptr(rwRoot, 3),
+      spi_ptr(rwRoot, 2),  // SPI0
+      spi_ptr(rwRoot, 3),  // SPI1
   };
   I2cPtr i2cs[2] = {i2c_ptr(root, 0), i2c_ptr(root, 1)};
 
@@ -85,14 +83,14 @@ using namespace CHERI;
   OutputPinAssignment pmod_test_gpio_off_pins[]    = {{SonataPinmux::OutputPin::pmod0_2, 0}};
   BlockInputAssignment pmod_test_gpio_off_inputs[] = {{SonataPinmux::BlockInput::gpio_2_ios_2, 0}};
 
-  OutputPinAssignment pmod_test_uart_on_pins[]     = {{SonataPinmux::OutputPin::pmod0_2, 3}};
-  BlockInputAssignment pmod_test_uart_on_inputs[]  = {{SonataPinmux::BlockInput::uart_2_rx, 2}};
+  OutputPinAssignment pmod_test_uart_on_pins[]     = {{SonataPinmux::OutputPin::pmod0_2, 4}};
+  BlockInputAssignment pmod_test_uart_on_inputs[]  = {{SonataPinmux::BlockInput::uart_1_rx, 5}};
   OutputPinAssignment pmod_test_uart_off_pins[]    = {{SonataPinmux::OutputPin::pmod0_2, 0}};
-  BlockInputAssignment pmod_test_uart_off_inputs[] = {{SonataPinmux::BlockInput::uart_2_rx, 0}};
+  BlockInputAssignment pmod_test_uart_off_inputs[] = {{SonataPinmux::BlockInput::uart_1_rx, 0}};
 
   OutputPinAssignment pmod_test_i2c_on_pins[2];
   pmod_test_i2c_on_pins[0] = {SonataPinmux::OutputPin::pmod0_3, 2};  // Mux to I2C SDA
-  pmod_test_i2c_on_pins[1] = {SonataPinmux::OutputPin::pmod0_4, 2};  // Mux to I2C SCL
+  pmod_test_i2c_on_pins[1] = {SonataPinmux::OutputPin::pmod0_4, 3};  // Mux to I2C SCL
   OutputPinAssignment pmod_test_i2c_off_pins[2];
   pmod_test_i2c_off_pins[0] = {SonataPinmux::OutputPin::pmod0_3, 0};
   pmod_test_i2c_off_pins[1] = {SonataPinmux::OutputPin::pmod0_4, 0};
@@ -100,13 +98,13 @@ using namespace CHERI;
   OutputPinAssignment pmod_test_spi_on_pins[3];
   pmod_test_spi_on_pins[0]                       = {SonataPinmux::OutputPin::pmod0_1, 2};  // Mux to SPI CS
   pmod_test_spi_on_pins[1]                       = {SonataPinmux::OutputPin::pmod0_2, 2};  // Mux to SPI COPI
-  pmod_test_spi_on_pins[2]                       = {SonataPinmux::OutputPin::pmod0_4, 3};  // Mux to SPI SCK
-  BlockInputAssignment pmod_test_spi_on_inputs[] = {{SonataPinmux::BlockInput::spi_2_rx, 2}};
+  pmod_test_spi_on_pins[2]                       = {SonataPinmux::OutputPin::pmod0_4, 2};  // Mux to SPI SCK
+  BlockInputAssignment pmod_test_spi_on_inputs[] = {{SonataPinmux::BlockInput::spi_0_cipo, 3}};
   OutputPinAssignment pmod_test_spi_off_pins[3];
   pmod_test_spi_off_pins[0]                       = {SonataPinmux::OutputPin::pmod0_1, 0};
   pmod_test_spi_off_pins[1]                       = {SonataPinmux::OutputPin::pmod0_2, 0};
   pmod_test_spi_off_pins[2]                       = {SonataPinmux::OutputPin::pmod0_4, 0};
-  BlockInputAssignment pmod_test_spi_off_inputs[] = {{SonataPinmux::BlockInput::spi_2_rx, 0}};
+  BlockInputAssignment pmod_test_spi_off_inputs[] = {{SonataPinmux::BlockInput::spi_0_cipo, 0}};
 
   // The pinmux testplan to execute. This testplan runs through testing GPIO, UART, I2C and SPI
   // all on the same PMOD pins, with users manually changing out the connected devices between
@@ -157,7 +155,7 @@ using namespace CHERI;
           .num_block_inputs = ARRAYSIZE(pmod_test_uart_on_inputs),
           .uart_data =
               {
-                  UartTest::UartNum::Uart2,
+                  UartTest::UartNum::Uart1,
                   UartTimeoutUsec,
                   UartTestBytes,
               },
@@ -173,7 +171,7 @@ using namespace CHERI;
           .num_block_inputs = ARRAYSIZE(pmod_test_uart_off_inputs),
           .uart_data =
               {
-                  UartTest::UartNum::Uart2,
+                  UartTest::UartNum::Uart1,
                   UartTimeoutUsec,
                   UartTestBytes,
               },
@@ -211,7 +209,7 @@ using namespace CHERI;
           .num_output_pins  = ARRAYSIZE(pmod_test_spi_on_pins),
           .block_inputs     = pmod_test_spi_on_inputs,
           .num_block_inputs = ARRAYSIZE(pmod_test_spi_on_inputs),
-          .spi_data         = {SpiTest::SpiNum::Spi2},
+          .spi_data         = {SpiTest::SpiNum::Spi0},
           .expected_result  = true,
       },
       {
@@ -222,7 +220,7 @@ using namespace CHERI;
           .num_output_pins  = ARRAYSIZE(pmod_test_spi_off_pins),
           .block_inputs     = pmod_test_spi_off_inputs,
           .num_block_inputs = ARRAYSIZE(pmod_test_spi_off_inputs),
-          .spi_data         = {SpiTest::SpiNum::Spi2},
+          .spi_data         = {SpiTest::SpiNum::Spi0},
           .expected_result  = false,
       },
   };
diff --git a/sw/cheri/checks/pinmux_checker.cc b/sw/cheri/checks/pinmux_checker.cc
index 59cc1adc9..1bc7d7e08 100644
--- a/sw/cheri/checks/pinmux_checker.cc
+++ b/sw/cheri/checks/pinmux_checker.cc
@@ -110,7 +110,7 @@ static bool spi_n25q256a_read_jedec_id(SpiPtr spi) {
 /**
  * Execute a UART send/receive test using the UART specified in the test.
  */
-static bool execute_uart_test(const Test &test, ds::xoroshiro::P32R8 &prng, UartPtr uarts[4]) {
+static bool execute_uart_test(const Test &test, ds::xoroshiro::P32R8 &prng, UartPtr uarts[2]) {
   UartPtr tested_uart = uarts[static_cast<uint8_t>(test.uart_data.uart)];
   bool result         = uart_send_receive_test(prng, tested_uart, test.uart_data.timeout, test.uart_data.test_length);
   return result == test.expected_result;
@@ -177,7 +177,7 @@ static inline bool joystick_moved(SonataGpioFull *gpio) {
  * capabilities to all possible devices that might be tested to be provided.
  *
  * @param console Should be UART0, and not in the `uarts` parameter.
- * @param uarts   Should point to UARTS1-4, which are not used as the console.
+ * @param uarts   Should point to UARTS1-2, which are not used as the console.
  * @param spi     Should point to SPI3 and 4, which are not in use by default.
  * @param i2cs    Should point to I2C0 and I2C1.
  *
@@ -185,7 +185,7 @@ static inline bool joystick_moved(SonataGpioFull *gpio) {
  * otherwise.
  */
 bool execute_test(const Test &test, uint32_t test_num, Log &log, ds::xoroshiro::P32R8 &prng, SonataGpioFull *gpio,
-                  UartPtr uarts[4], SpiPtr spis[2], I2cPtr i2cs[2], SonataPinmux *pinmux) {
+                  UartPtr uarts[2], SpiPtr spis[2], I2cPtr i2cs[2], SonataPinmux *pinmux) {
   // If manual intervention is required, print out the test instruction and wait
   // for the user to press the joystick to signal that they are ready.
   if (test.manual_required) {
@@ -298,7 +298,7 @@ bool ask_retry_last_test(Log &log, SonataGpioFull *gpio) {
  * otherwise. Will return true even if there were retries.
  */
 bool execute_testplan(Test *testplan, uint8_t NumTests, Log &log, ds::xoroshiro::P32R8 &prng, SonataGpioFull *gpio,
-                      UartPtr uarts[4], SpiPtr spis[2], I2cPtr i2cs[2], SonataPinmux *pinmux) {
+                      UartPtr uarts[2], SpiPtr spis[2], I2cPtr i2cs[2], SonataPinmux *pinmux) {
   log.println("");
   log.println("{}Starting check.", prefix);
   log.println("");
diff --git a/sw/cheri/checks/pinmux_checker.hh b/sw/cheri/checks/pinmux_checker.hh
index 47a7d5290..e96016a1c 100644
--- a/sw/cheri/checks/pinmux_checker.hh
+++ b/sw/cheri/checks/pinmux_checker.hh
@@ -43,8 +43,6 @@ struct UartTest {
     // Uart0 is used as a console and cannot be tested
     Uart1,
     Uart2,
-    Uart3,
-    Uart4,
     NumUarts,
   } uart;
   uint32_t timeout;
@@ -71,9 +69,9 @@ struct I2cTest {
 // The test-specific data required to carry out a SPI Pmod SF3 Read ID test
 struct SpiTest {
   enum class SpiNum : uint8_t {
-    // Spi0-1 are used for the Flash and LCD and so cannot be tested.
-    Spi2,
-    Spi3,
+    // The Flash and LCD have unused dedicated SPIs which cannot be tested.
+    Spi0,
+    Spi1,
     NumSpi,
   } spi;
 };

From 029c903f862899c87f14177076697a18423ada18 Mon Sep 17 00:00:00 2001
From: Alex Jones <alex.jones@lowrisc.org>
Date: Fri, 1 Nov 2024 13:41:48 +0000
Subject: [PATCH 12/21] Update pinmux tests for mapping changes & convert SPI
 test to use external flash

Updates the pinmux tests for the changes introduced with the new pinmux
mapping. This primarily involves just changing the pins / devices used
to the devices that are now mapped on those pins, and updating
documentation to reflect this.

Also resets all pinmux logic after muxing to ensure that if more tests
are added afterwards or if the tests are run multiple times, that errors
are not introduced by the pinmux tests changing state.

Since the Application flash pinmux pins are no longer available through
pinmux, this also involves converting the SPI Pinmux test to change to
instead test using an extrenal SPI PMOD SF3 conecting to PMOD1. This
repurposes the existing test logic used by the pinmux checker to reduce
the amonut of additional code.
---
 sw/cheri/checks/pinmux_checker.cc |  34 -----
 sw/cheri/common/block_tests.cc    |  34 +++++
 sw/cheri/common/block_tests.hh    |   1 +
 sw/cheri/tests/pinmux_tests.hh    | 241 ++++++++++++++++--------------
 4 files changed, 167 insertions(+), 143 deletions(-)

diff --git a/sw/cheri/checks/pinmux_checker.cc b/sw/cheri/checks/pinmux_checker.cc
index 1bc7d7e08..cf830ed9b 100644
--- a/sw/cheri/checks/pinmux_checker.cc
+++ b/sw/cheri/checks/pinmux_checker.cc
@@ -73,40 +73,6 @@ static bool i2c_read_pmod_colour_id_test(I2cPtr i2c, Log &log) {
          ((data[0] == ExpectedPmodColourDeviceIdRevA) || (data[0] == ExpectedPmodColourDeviceIdRevB));
 }
 
-/**
- * Tests that the given SPI block is working as expected, by writing and reading
- * some data via SPI to read the JEDEC/Manufacturer ID of a connected N25Q56A
- * flash memory device, and checking it against known values. This test expects
- * that the SPI pins corresponding to the given SPI block are connected to a
- * device with such memory, e.g. a PMOD SF3.
- *
- * Returns true if the test passed, or false if it failed.
- */
-static bool spi_n25q256a_read_jedec_id(SpiPtr spi) {
-  constexpr uint8_t CmdReadJEDECId     = 0x9f;
-  constexpr uint8_t ExpectedJedecId[3] = {0x20, 0xBA, 0x19};
-
-  // Configure the SPI to be MSB-first.
-  spi->wait_idle();
-  spi->init(false, false, true, 0);
-
-  // Read the JEDEC ID from the external flash
-  uint8_t jedec_id[3] = {0x12, 0x34, 0x56};  // (Dummy data)
-  spi->cs             = (spi->cs & ~1u);     // Set ¬CS High
-  spi->blocking_write(&CmdReadJEDECId, 1);
-  spi->blocking_read(jedec_id, 3);
-  spi->cs = (spi->cs | 1u);  // Set ¬CS Low
-
-  // Check that the retrieved ID matches our expected value
-  for (size_t index = 0; index < sizeof(jedec_id); index++) {
-    if (jedec_id[index] != ExpectedJedecId[index]) {
-      return false;
-    }
-  }
-
-  return true;
-}
-
 /**
  * Execute a UART send/receive test using the UART specified in the test.
  */
diff --git a/sw/cheri/common/block_tests.cc b/sw/cheri/common/block_tests.cc
index ef27f75ec..e3ca77108 100644
--- a/sw/cheri/common/block_tests.cc
+++ b/sw/cheri/common/block_tests.cc
@@ -167,6 +167,40 @@ bool gpio_write_read_test(SonataGpioFull *gpio, GpioPin output_pin, GpioPin inpu
   return true;
 }
 
+/**
+ * Tests that the given SPI block is working as expected, by writing and reading
+ * some data via SPI to read the JEDEC/Manufacturer ID of a connected N25Q56A
+ * flash memory device, and checking it against known values. This test expects
+ * that the SPI pins corresponding to the given SPI block are connected to a
+ * device with such memory, e.g. a PMOD SF3.
+ *
+ * Returns true if the test passed, or false if it failed.
+ */
+bool spi_n25q256a_read_jedec_id(SpiPtr spi) {
+  constexpr uint8_t CmdReadJEDECId     = 0x9f;
+  constexpr uint8_t ExpectedJedecId[3] = {0x20, 0xBA, 0x19};
+
+  // Configure the SPI to be MSB-first.
+  spi->wait_idle();
+  spi->init(false, false, true, 0);
+
+  // Read the JEDEC ID from the external flash
+  uint8_t jedec_id[3] = {0x12, 0x34, 0x56};  // (Dummy data)
+  spi->cs             = (spi->cs & ~1u);     // Set ¬CS High
+  spi->blocking_write(&CmdReadJEDECId, 1);
+  spi->blocking_read(jedec_id, 3);
+  spi->cs = (spi->cs | 1u);  // Set ¬CS Low
+
+  // Check that the retrieved ID matches our expected value
+  for (size_t index = 0; index < sizeof(jedec_id); index++) {
+    if (jedec_id[index] != ExpectedJedecId[index]) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
 /**
  * Resets an I2C controller to acknowledge and disable any Controller Halt
  * events. When the I2C device is disconnected from Pinmux and tested,
diff --git a/sw/cheri/common/block_tests.hh b/sw/cheri/common/block_tests.hh
index 55139e3bc..2db339ab3 100644
--- a/sw/cheri/common/block_tests.hh
+++ b/sw/cheri/common/block_tests.hh
@@ -43,5 +43,6 @@ bool get_gpio_input(SonataGpioFull *gpio, GpioPin pin);
 bool uart_send_receive_test(ds::xoroshiro::P32R8 &prng, UartPtr uart, uint32_t read_timeout_usec, uint32_t test_length);
 bool gpio_write_read_test(SonataGpioFull *gpio, GpioPin output_pin, GpioPin input_pin, uint32_t wait_usec,
                           uint32_t test_length);
+bool spi_n25q256a_read_jedec_id(SpiPtr spi);
 
 void reset_i2c_controller(I2cPtr i2c);
diff --git a/sw/cheri/tests/pinmux_tests.hh b/sw/cheri/tests/pinmux_tests.hh
index 26fc2640b..6ec4262ee 100644
--- a/sw/cheri/tests/pinmux_tests.hh
+++ b/sw/cheri/tests/pinmux_tests.hh
@@ -38,6 +38,15 @@ using namespace CHERI;
 #define PINMUX_CABLE_CONNECTIONS_AVAILABLE true
 #endif
 
+/**
+ * Configures whether a Digilent PMOD SF3 is attached to the PMOD1
+ * connector as is required for Pinmux SPI testing.
+ * Ths can be overriden via a compilation flag.
+ */
+#ifndef PINMUX_PMOD1_PMODSF3_AVAILABLE
+#define PINMUX_PMOD1_PMODSF3_AVAILABLE true
+#endif
+
 // Testing parameters
 static constexpr uint32_t UartTimeoutUsec = 24;  // with 921,600 bps, this is > 25 bit times.
 static constexpr uint32_t UartTestBytes   = 100;
@@ -45,140 +54,141 @@ static constexpr uint32_t GpioWaitUsec    = 20;  // short wire bridge between FG
 static constexpr uint32_t GpioTestLength  = 10;
 
 static constexpr uint8_t PmxToDisabled = 0;
+static constexpr uint8_t PmxToDefault  = 1;
 
 /**
- * Attempt to retrieve the JEDEC ID of the Spi Flash device on the Sonata board,
- * and compare it to the known (expected) JEDEC ID. This is separate from the
- * similar test in the SPI tests, as it skips the initialisation logic that
- * should not be repeated in the pinmux check.
- *
- * Returns the number of failures during the test.
- */
-static int spi_jedec_id_test(Capability<volatile SonataSpi> spi, SpiFlash spi_flash) {
-  int failures = 0;
-
-  // Configure the SPI to be MSB-first.
-  spi->wait_idle();
-  spi->init(false, false, true, 0);
-
-  // Read the JEDEC ID from Flash
-  uint8_t jedec_id[3] = {0};
-  spi_flash.read_jedec_id(jedec_id);
-
-  // Check that the retrieved ID matches our expected value
-  for (size_t index = 0; index < sizeof(jedec_id); index++) {
-    if (jedec_id[index] != ExpectedSpiFlashJedecId[index]) {
-      failures++;
-    }
-  }
-
-  return failures;
-}
-
-/**
- * Test pinmux by enabling and disabling the UART3 TX pin output and UART3 RX
+ * Test pinmux by enabling and disabling the UART1 TX pin output and UART1 RX
  * block input. Tests the UART itself by sending and receiving some data over
- * UART3; it is required that UART3 TX and RX are manually connected on Sonata
+ * UART1; it is required that UART1 TX and RX are manually connected on Sonata
  * for this test (mikroBus P7 RX & TX).
  *
- * Tests UART3 normally, then disables TX and checks the test fails, then
+ * Tests UART1 normally, then disables TX and checks the test fails, then
  * disables RX and checks the test fails, and then re-enables the pins and
  * repeats the test, checking that it succeeds.
  *
  * Returns the number of failures during the test.
  */
-static int pinmux_uart_test(SonataPinmux *pinmux, ds::xoroshiro::P32R8 &prng, UartPtr uart3) {
-  constexpr uint8_t PmxMikroBusUartTransmitToUartTx3 = 1;
-  constexpr uint8_t PmxUartReceive3ToMb8             = 2;
+static int pinmux_uart_test(SonataPinmux *pinmux, ds::xoroshiro::P32R8 &prng, UartPtr uart1) {
+  constexpr uint8_t PmxMikroBusUartTransmitToUartTx1 = 1;
+  constexpr uint8_t PmxUartReceive1ToMb8             = 4;
 
   int failures = 0;
 
-  // Mux UART3 over mikroBus P7 RX & TX via default.
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::mb7, PmxMikroBusUartTransmitToUartTx3);
-  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_3_rx, PmxUartReceive3ToMb8);
+  // Mux UART1 over mikroBus P7 RX & TX via default.
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::mb7, PmxMikroBusUartTransmitToUartTx1);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxUartReceive1ToMb8);
 
-  // Check that messages are sent and received via UART3
-  failures += !uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  // Check that messages are sent and received via UART1
+  failures += !uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
 
-  // Disable UART3 TX through pinmux, and check the test now fails (no TX sent)
+  // Disable UART1 TX through pinmux, and check the test now fails (no TX sent)
   failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::mb7, PmxToDisabled);
-  failures += uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  failures += uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
 
-  // Re-enable UART3 TX and disable UART3 RX through pinmux, and check that the test
+  // Re-enable UART1 TX and disable UART1 RX through pinmux, and check that the test
   // still fails (no RX received)
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::mb7, PmxMikroBusUartTransmitToUartTx3);
-  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_3_rx, PmxToDisabled);
-  failures += uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::mb7, PmxMikroBusUartTransmitToUartTx1);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxToDisabled);
+  failures += uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
+
+  // Re-enable UART1 RX and check the test now passes again
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxUartReceive1ToMb8);
+  failures += !uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
 
-  // Re-enable UART3 RX and check the test now passes again
-  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_3_rx, PmxUartReceive3ToMb8);
-  failures += !uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  // Reset muxed pins to not interfere with future tests
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::mb7, PmxToDefault);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxToDefault);
 
   return failures;
 }
 
+static void reset_spi_flash(SpiPtr spi) {
+  spi->cs = (spi->cs & ~1u);  // Enable CS
+  spi->blocking_write(&CmdEnableReset, 1);
+  spi->wait_idle();
+  spi->cs = (spi->cs | 1u);  // Disable CS
+
+  spi->cs = (spi->cs & ~1u);  // Enable CS
+  spi->blocking_write(&CmdReset, 1);
+  spi->wait_idle();
+  spi->cs = (spi->cs | 1u);  // Disable CS
+
+  // Need to wait at least 30us for the reset to complete.
+  wait_mcycle(2000);
+}
+
 /**
- * Test pinmux by enabling and disabling the SPI Flash pins. First reads the
- * Flash's JEDEC ID like normal, then disables the pins via pinmux and repeats
- * the JEDEC ID read, checking that it fails. Then re-enables the pins via
- * pinmux and repeats the JEDEC ID read, checking that it succeeds.
+ * Test pinmux by enabling and disabling the SPI1 pins, which are used to communicate with a connected
+ * PMOD SF3 Spi Flash (n25q256a) device. First reads the flash's JEDEC ID like normal, then disables
+ * the pins via pinmux and repeats the JEDEC ID read, checking that it fails. Then re-enables the pins
+ * via pinmux and repeats the JEDEC ID read, checking that it succeeds.
  * Returns the number of failures during the test.
  */
-static int pinmux_spi_flash_test(SonataPinmux *pinmux, Capability<volatile SonataSpi> spi, SpiFlash spi_flash) {
-  constexpr uint8_t PmxSpiFlashDataToSpiTx0   = 1;
-  constexpr uint8_t PmxSpiFlashClockToSpiClk0 = 1;
-  constexpr uint8_t PmxSpiFlashCsToSpiCs0     = 1;
+static int pinmux_spi_flash_test(SonataPinmux *pinmux, SpiPtr spi) {
+  constexpr uint8_t PmxPmod1Io1ToSpi1Cs   = 2;
+  constexpr uint8_t PmxPmod1Io2ToSpi1Copi = 2;
+  constexpr uint8_t PmxPmod1Io4ToSpi1Sclk = 2;
+  constexpr uint8_t PmxSpi1CipoToPmod1Io3 = 3;
 
   int failures = 0;
 
   // Ensure the SPI Flash pins are enabled using Pinmux
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_d0, PmxSpiFlashDataToSpiTx0);
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_clk, PmxSpiFlashClockToSpiClk0);
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_cs, PmxSpiFlashCsToSpiCs0);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_1, PmxPmod1Io1ToSpi1Cs);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::spi_1_cipo, PmxSpi1CipoToPmod1Io3);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_2, PmxPmod1Io2ToSpi1Copi);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_4, PmxPmod1Io4ToSpi1Sclk);
 
   // Configure the SPI to be MSB-first.
   spi->wait_idle();
   spi->init(false, false, true, 0);
-  spi_flash.reset();
+  reset_spi_flash(spi);
 
   // Run the normal SPI Flash JEDEC ID Test; it should pass.
-  failures += spi_jedec_id_test(spi, spi_flash);
+  failures += !spi_n25q256a_read_jedec_id(spi);
 
   // Disable the SPI Flash pins through pinmux
   spi->wait_idle();
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_cs, PmxToDisabled);
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_d0, PmxToDisabled);
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_clk, PmxToDisabled);
-  spi_flash.reset();
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_1, PmxToDisabled);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::spi_1_cipo, PmxToDisabled);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_2, PmxToDisabled);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_4, PmxToDisabled);
+  reset_spi_flash(spi);
 
   // Run the JEDEC ID Test again; we expect it to fail.
-  failures += (spi_jedec_id_test(spi, spi_flash) == 0);
+  failures += spi_n25q256a_read_jedec_id(spi);
 
   // Re-enable the SPI Flash pins through pinmux
   spi->wait_idle();
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_d0, PmxSpiFlashDataToSpiTx0);
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_clk, PmxSpiFlashClockToSpiClk0);
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_cs, PmxSpiFlashCsToSpiCs0);
-  spi_flash.reset();
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_1, PmxPmod1Io1ToSpi1Cs);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::spi_1_cipo, PmxSpi1CipoToPmod1Io3);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_2, PmxPmod1Io2ToSpi1Copi);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_4, PmxPmod1Io4ToSpi1Sclk);
+  reset_spi_flash(spi);
 
   // Run the JEDEC ID Test one more time; it should pass.
-  failures += spi_jedec_id_test(spi, spi_flash);
+  failures += !spi_n25q256a_read_jedec_id(spi);
 
   // Disable specifically the Chip Select through Pinmux.
   spi->wait_idle();
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_cs, PmxToDisabled);
-  spi_flash.reset();
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_1, PmxToDisabled);
+  reset_spi_flash(spi);
 
   // Run the JEDEC ID Test again; we expect it to fail.
-  failures += (spi_jedec_id_test(spi, spi_flash) == 0);
+  failures += spi_n25q256a_read_jedec_id(spi);
 
   // Re-enable the Chip Select through Pinmux.
   spi->wait_idle();
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::appspi_cs, PmxSpiFlashCsToSpiCs0);
-  spi_flash.reset();
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_1, PmxPmod1Io1ToSpi1Cs);
+  reset_spi_flash(spi);
 
   // Run the JEDEC ID Test again; it should pass.
-  failures += spi_jedec_id_test(spi, spi_flash);
+  failures += !spi_n25q256a_read_jedec_id(spi);
+
+  // Reset muxed pins to not interfere with future tests
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_1, PmxToDefault);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::spi_1_cipo, PmxToDefault);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_2, PmxToDefault);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::pmod1_4, PmxToDefault);
 
   return failures;
 }
@@ -237,6 +247,12 @@ static int pinmux_i2c_test(SonataPinmux *pinmux, I2cPtr i2c0, I2cPtr i2c1) {
   failures += i2c_rpi_hat_id_eeprom_test(i2c0);
   failures += i2c_rpi_hat_imu_whoami_test(i2c1);
 
+  // Reset muxed pins to not interfere with future tests
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::rph_g0, PmxToDefault);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::rph_g1, PmxToDefault);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::rph_g2_sda, PmxToDefault);
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::rph_g3_scl, PmxToDefault);
+
   return failures;
 }
 
@@ -279,6 +295,10 @@ static int pinmux_gpio_test(SonataPinmux *pinmux, SonataGpioFull *gpio) {
   failures += !pinmux->block_input_select(SonataPinmux::BlockInput::gpio_1_ios_9, PmxArduinoGpio9ToAhTmpio9);
   failures += !gpio_write_read_test(gpio, GpioPinOutput, GpioPinInput, GpioWaitUsec, GpioTestLength);
 
+  // Reset muxed pins to not interfere with future tests
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio8, PmxToDefault);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::gpio_1_ios_9, PmxToDefault);
+
   return failures;
 }
 
@@ -294,10 +314,10 @@ static int pinmux_gpio_test(SonataPinmux *pinmux, SonataGpioFull *gpio) {
  *
  * Returns the number of failures during the test.
  */
-static int pinmux_mux_test(SonataPinmux *pinmux, ds::xoroshiro::P32R8 &prng, UartPtr uart3, SonataGpioFull *gpio) {
-  constexpr uint8_t PmxArduinoD1ToUartTx3     = 2;
-  constexpr uint8_t PmxArduinoD1ToGpio_1_1    = 1;
-  constexpr uint8_t PmxUartReceive3ToAhTmpio0 = 1;
+static int pinmux_mux_test(SonataPinmux *pinmux, ds::xoroshiro::P32R8 &prng, UartPtr uart1, SonataGpioFull *gpio) {
+  constexpr uint8_t PmxArduinoD1ToUartTx1     = 1;
+  constexpr uint8_t PmxArduinoD1ToGpio_1_1    = 2;
+  constexpr uint8_t PmxUartReceive1ToAhTmpio0 = 3;
   constexpr uint8_t PmxArduinoGpio0ToAhTmpio0 = 1;
 
   constexpr GpioPin GpioPinInput  = {GpioInstance::ArduinoShield, 0};
@@ -309,30 +329,35 @@ static int pinmux_mux_test(SonataPinmux *pinmux, ds::xoroshiro::P32R8 &prng, Uar
   set_gpio_output_enable(gpio, GpioPinOutput, true);
   set_gpio_output_enable(gpio, GpioPinInput, false);
 
-  // Mux UART3 over Arduino Shield D0 (RX) & D1 (TX)
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio1, PmxArduinoD1ToUartTx3);
-  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_3_rx, PmxUartReceive3ToAhTmpio0);
+  // Mux UART1 over Arduino Shield D0 (RX) & D1 (TX)
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio1, PmxArduinoD1ToUartTx1);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxUartReceive1ToAhTmpio0);
 
-  // Test that UART3 works over the muxed Arduino Shield D0 & D1 pins,
+  // Test that UART1 works over the muxed Arduino Shield D0 & D1 pins,
   // and that GPIO does not work, as these pins are not muxed for GPIO.
-  failures += !uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  failures += !uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
   failures += gpio_write_read_test(gpio, GpioPinOutput, GpioPinInput, GpioWaitUsec, GpioTestLength);
 
   // Mux GPIO over Arduino Shield D0 (GPIO input) & D1 (GPIO output)
   failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio1, PmxArduinoD1ToGpio_1_1);
   failures += !pinmux->block_input_select(SonataPinmux::BlockInput::gpio_1_ios_0, PmxArduinoGpio0ToAhTmpio0);
 
-  // Test that UART3 no longer works (no longer muxed over D0 & D1),
+  // Test that UART1 no longer works (no longer muxed over D0 & D1),
   // and that our muxed GPIO now works.
-  failures += uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  failures += uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
   failures += !gpio_write_read_test(gpio, GpioPinOutput, GpioPinInput, GpioWaitUsec, GpioTestLength);
 
-  // Mux back to UART3 again, and test that UART again passes and GPIO fails.
-  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio1, PmxArduinoD1ToUartTx3);
-  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_3_rx, PmxUartReceive3ToAhTmpio0);
-  failures += !uart_send_receive_test(prng, uart3, UartTimeoutUsec, UartTestBytes);
+  // Mux back to UART1 again, and test that UART again passes and GPIO fails.
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio1, PmxArduinoD1ToUartTx1);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxUartReceive1ToAhTmpio0);
+  failures += !uart_send_receive_test(prng, uart1, UartTimeoutUsec, UartTestBytes);
   failures += gpio_write_read_test(gpio, GpioPinOutput, GpioPinInput, GpioWaitUsec, GpioTestLength);
 
+  // Reset muxed pins to not interfere with future tests
+  failures += !pinmux->output_pin_select(SonataPinmux::OutputPin::ah_tmpio1, PmxToDefault);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::uart_1_rx, PmxToDefault);
+  failures += !pinmux->block_input_select(SonataPinmux::BlockInput::gpio_1_ios_0, PmxToDefault);
+
   return failures;
 }
 
@@ -347,9 +372,12 @@ void pinmux_tests(CapRoot root, Log &log) {
   SonataPinmux Pinmux                 = SonataPinmux(pinmux);
 
   // Create bounded capabilities for other devices, to be used in testing.
-  Capability<volatile SonataSpi> spi = root.cast<volatile SonataSpi>();
-  spi.address()                      = SPI_ADDRESS;
-  spi.bounds()                       = SPI_BOUNDS;
+  SpiPtr spi = spi_ptr(root, 3);
+
+  UartPtr uart1 = uart_ptr(root, 1);
+
+  I2cPtr i2c0 = i2c_ptr(root, 0);
+  I2cPtr i2c1 = i2c_ptr(root, 1);
 
   // Create bounded capabilities for the full range of GPIO
   SonataGpioFull gpio_full;
@@ -369,13 +397,6 @@ void pinmux_tests(CapRoot root, Log &log) {
   gpio_full.pmod1.address()   = GPIO_ADDRESS + GPIO_RANGE * 4;
   gpio_full.pmod1.bounds()    = GPIO_BOUNDS;
 
-  SpiFlash spi_flash(spi);
-
-  UartPtr uart3 = uart_ptr(root, 3);
-
-  I2cPtr i2c0 = i2c_ptr(root, 0);
-  I2cPtr i2c1 = i2c_ptr(root, 1);
-
   // Initialise PRNG for use to create (pseudo-)random test data.
   ds::xoroshiro::P32R8 prng;
   prng.set_state(0xDEAD, 0xBEEF);
@@ -390,10 +411,12 @@ void pinmux_tests(CapRoot root, Log &log) {
     bool test_failed = false;
     int failures     = 0;
 
-    log.print("  Running SPI Flash Pinmux test... ");
-    failures = pinmux_spi_flash_test(&Pinmux, spi, spi_flash);
-    test_failed |= (failures > 0);
-    write_test_result(log, failures);
+    if (PINMUX_PMOD1_PMODSF3_AVAILABLE) {
+      log.print("  Running SPI Flash Pinmux test... ");
+      failures = pinmux_spi_flash_test(&Pinmux, spi);
+      test_failed |= (failures > 0);
+      write_test_result(log, failures);
+    }
 
     if (I2C_RPI_HAT_AVAILABLE) {
       log.print("  Running I2C Pinmux test... ");
@@ -409,12 +432,12 @@ void pinmux_tests(CapRoot root, Log &log) {
       write_test_result(log, failures);
 
       log.print("  Running UART Pinmux test... ");
-      failures = pinmux_uart_test(&Pinmux, prng, uart3);
+      failures = pinmux_uart_test(&Pinmux, prng, uart1);
       test_failed |= (failures > 0);
       write_test_result(log, failures);
 
       log.print("  Running Mux test... ");
-      failures = pinmux_mux_test(&Pinmux, prng, uart3, &gpio_full);
+      failures = pinmux_mux_test(&Pinmux, prng, uart1, &gpio_full);
       test_failed |= (failures > 0);
       write_test_result(log, failures);
     }

From 09ba3750a92d3316d709de4a0efbc82a2159dd1f Mon Sep 17 00:00:00 2001
From: Alex Jones <alex.jones@lowrisc.org>
Date: Fri, 1 Nov 2024 14:39:12 +0000
Subject: [PATCH 13/21] Attach Basic PMOD SF3 SPI DPI to PMOD1 in Verilator

Adds a basic PMOD SF3 DPI in Verilator, attached to the PMOD1 pins so
that the device can be used. This is modelled to be the same as the
existing Application Flash on Sonata, but with a different JEDEC ID that
it reports. Makes the Spi Flash take a JEDEC ID as a parameter to reduce
duplicated logic between these DPIs.

Disclaimer: I am not a hardware engineer, the hardware changes may
contain problems.
---
 dv/dpi/spidpi/spi_flash.cc    |  6 ++---
 dv/dpi/spidpi/spi_flash.hh    |  8 ++++--
 dv/dpi/spidpi/spidpi.cc       |  4 ++-
 dv/verilator/top_verilator.sv | 49 +++++++++++++++++++++++++++++++++++
 4 files changed, 61 insertions(+), 6 deletions(-)

diff --git a/dv/dpi/spidpi/spi_flash.cc b/dv/dpi/spidpi/spi_flash.cc
index 47003d1e1..4bd300096 100644
--- a/dv/dpi/spidpi/spi_flash.cc
+++ b/dv/dpi/spidpi/spi_flash.cc
@@ -43,9 +43,9 @@ void spi_flash::writeByte(uint8_t inByte, uint32_t oobIn) {
       case CmdEnableReset: cmdComplete = true; break;
       case CmdReset: reset(); cmdComplete = true; break;
       case CmdReadJEDECId:
-        rsp[0] = 0xef;
-        rsp[1] = 0x40;
-        rsp[2] = 0x19;
+        rsp[0] = static_cast<uint8_t>(jedec_id >> 16);
+        rsp[1] = static_cast<uint8_t>(jedec_id >> 8);
+        rsp[2] = static_cast<uint8_t>(jedec_id);
         rspLen = 3u;
         rspIdx = 0u;
         cmdComplete = true;
diff --git a/dv/dpi/spidpi/spi_flash.hh b/dv/dpi/spidpi/spi_flash.hh
index 32161f1db..68c22d56e 100644
--- a/dv/dpi/spidpi/spi_flash.hh
+++ b/dv/dpi/spidpi/spi_flash.hh
@@ -11,8 +11,9 @@ class spi_flash : public spidpi {
 public:
   spi_flash(unsigned dataW,      // Number of data lines.
             unsigned oobInW,     // Width of Out-Of-Band input data (bits).
-            unsigned oobOutW) :  // Width of Out-Of-Band output data (bits).
-            spidpi(dataW, oobInW, oobOutW) {
+            unsigned oobOutW,    // Width of Out-Of-Band output data (bits).
+            uint32_t jedec_id) : // The JEDEC ID of the flash device.
+            spidpi(dataW, oobInW, oobOutW), jedec_id(jedec_id) {
       reset();
    }
 
@@ -66,4 +67,7 @@ private:
   // Current offset within flash for programming/reading operation.
   uint32_t memOffset;
   uint8_t  mem[kFlashBytes];
+
+  // JEDEC ID of the flash device, written in the bottom 24 bytes.
+  uint32_t jedec_id;
 };
diff --git a/dv/dpi/spidpi/spidpi.cc b/dv/dpi/spidpi/spidpi.cc
index d005d1a67..f545dec98 100644
--- a/dv/dpi/spidpi/spidpi.cc
+++ b/dv/dpi/spidpi/spidpi.cc
@@ -88,9 +88,11 @@ void *spidpi_create(const char *id,      // Bus identification.
   assert(ndevices == 1u);
   // Attach the appropriate devices to this bus.
   if (!strcmp(id, "flash")) {
-    ctx = new spi_flash(dataW, oobInW, oobOutW);
+    ctx = new spi_flash(dataW, oobInW, oobOutW, 0xef4019);
   } else if (!strcmp(id, "lcd")) {
     ctx = new spi_lcd(dataW, oobInW, oobOutW);
+  } else if (!strcmp(id, "pmod_sf3")) {
+    ctx = new spi_flash(dataW, oobInW, oobOutW, 0x20ba19);
   } else {
     ctx = new spidpi(dataW, oobInW, oobOutW, true);
     ctx->logText("Warning: SPI bus '%s' not recognised", id);
diff --git a/dv/verilator/top_verilator.sv b/dv/verilator/top_verilator.sv
index 2c4f98d9d..4615723df 100644
--- a/dv/verilator/top_verilator.sv
+++ b/dv/verilator/top_verilator.sv
@@ -32,6 +32,10 @@ module top_verilator (input logic clk_i, rst_ni);
   logic scl1_o, scl1_oe;
   logic sda1_o, sda1_oe;
 
+  logic cs_pmod1_o, cs_pmod1_oe;
+  logic sck_pmod1_o, sck_pmod1_oe;
+  logic copi_pmod1_o, copi_pmod1_oe;
+
   // Output clocks and data to the I2C buses.
   wire scl_rpi0_out = scl_rpi0_oe ? scl_rpi0_o : 1'b1;
   wire sda_rpi0_out = sda_rpi0_oe ? sda_rpi0_o : 1'b1;
@@ -42,6 +46,21 @@ module top_verilator (input logic clk_i, rst_ni);
   wire scl1_out = scl1_oe ? scl1_o : 1'b1;
   wire sda1_out = sda1_oe ? sda1_o : 1'b1;
 
+  // Output for the SPI PMOD1 buses, used for PMOD SF3 DPI
+  wire cs_pmod1_out   = cs_pmod1_oe ? cs_pmod1_o : 1'b1;
+  wire sck_pmod1_out  = sck_pmod1_oe ? sck_pmod1_o : 1'b1;
+  wire copi_pmod1_out = copi_pmod1_oe ? copi_pmod1_o : 1'b1;
+
+  // Input from SPI PMOD1 bus
+  wire cipo_pmod1_i;
+
+  // SPI PMOD SF3 OOB
+  wire pmod1_spi_d2; // WP_N (write protect negated)
+  wire pmod1_spi_d3; // HOLD_N or RESET_N
+  // Tie to 1 as they're active low and we don't need either signal
+  assign pmod1_spi_d2 = 1'b1;
+  assign pmod1_spi_d3 = 1'b1;
+
   // Clocks and data from the I2C DPI models.
   wire scl_rpi0_dpi, sda_rpi0_dpi;
   wire scl_rpi1_dpi, sda_rpi1_dpi;
@@ -194,6 +213,14 @@ module top_verilator (input logic clk_i, rst_ni);
   assign {scl1_o, scl1_oe} = {inout_to_pins[INOUT_PIN_SCL1], inout_to_pins_en[INOUT_PIN_SCL1]};
   assign {sda1_o, sda1_oe} = {inout_to_pins[INOUT_PIN_SDA1], inout_to_pins_en[INOUT_PIN_SDA1]};
 
+  // Output SPI traffic to the PMOD SF3 on PMOD1
+  assign {cs_pmod1_o, cs_pmod1_oe} = {inout_to_pins[INOUT_PIN_PMOD1_1],
+                                   inout_to_pins_en[INOUT_PIN_PMOD1_1]};
+  assign {copi_pmod1_o, copi_pmod1_oe} = {inout_to_pins[INOUT_PIN_PMOD1_2],
+                                       inout_to_pins_en[INOUT_PIN_PMOD1_2]};
+  assign {sck_pmod1_o, sck_pmod1_oe} = {inout_to_pins[INOUT_PIN_PMOD1_4],
+                                     inout_to_pins_en[INOUT_PIN_PMOD1_4]};
+
   assign in_from_pins[IN_PIN_SER0_RX]   = uart_sys_rx;
   assign in_from_pins[IN_PIN_SER1_RX]   = uart_aux_rx;
 
@@ -213,6 +240,9 @@ module top_verilator (input logic clk_i, rst_ni);
   // There is no device model on the mikroBUS Click I2C bus.
   assign inout_from_pins[INOUT_PIN_MB5] = 1'b1;
   assign inout_from_pins[INOUT_PIN_MB6] = 1'b1;
+  // Input SPI traffic from PMOD SF3 on PMOD1
+  assign inout_from_pins[INOUT_PIN_PMOD1_3] = cipo_pmod1_i;
+
 
   // CS outputs to SPI peripherals from controllers.
   assign rph_g8_ce0   = inout_to_pins[INOUT_PIN_RPH_G8_CE0];
@@ -488,6 +518,25 @@ module top_verilator (input logic clk_i, rst_ni);
     .oob_out  ( )  // not used.
   );
 
+  // SPI connection to PMOD SF3 flash via PMOD1 pins
+  spidpi #(
+    .ID       ("pmod_sf3"),
+    .NDevices (1),
+    .DataW    (1),
+    .OOB_InW  (2),
+    .OOB_OutW (1)
+  ) u_spidpi_pmod_sf3 (
+    .rst_ni   (rst_ni),
+
+    .sck      (sck_pmod1_out),
+    .cs       (cs_pmod1_out),
+    .copi     (copi_pmod1_out),
+    .cipo     (cipo_pmod1_i),
+
+    .oob_in   ({pmod1_spi_d3, pmod1_spi_d2}),
+    .oob_out  ( )  // not used.
+  );
+
 
   export "DPI-C" function mhpmcounter_get;
 

From e523ec89d8cab3069aa8630cffd18f33f09d985b Mon Sep 17 00:00:00 2001
From: Alex Jones <alex.jones@lowrisc.org>
Date: Fri, 1 Nov 2024 15:38:33 +0000
Subject: [PATCH 14/21] Add PMODC pins to XDC file

Co-authored-by: Elliot Baptist <elliot.baptist@lowrisc.org>
---
 data/pins_sonata.xdc | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/data/pins_sonata.xdc b/data/pins_sonata.xdc
index fd23ccc34..619869bf2 100644
--- a/data/pins_sonata.xdc
+++ b/data/pins_sonata.xdc
@@ -93,6 +93,14 @@ set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [
 set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmod0[6]}]
 set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmod0[7]}]
 
+## PMODC (pins between PMOD0 and PMOD1 on shared connector)
+set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmodc[0]}] ;# PMODC_1 on schematic
+set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmodc[1]}] ;# PMODC_2
+set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmodc[2]}] ;# ...
+set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmodc[3]}]
+set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmodc[4]}]
+set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmodc[5]}]
+
 ## PMOD1
 set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmod1[0]}]
 set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 IO_BUFFER_TYPE NONE } [get_ports {pmod1[1]}]

From a23c6e5f8cc0b8a2b5ace9f7368a432bfc90794b Mon Sep 17 00:00:00 2001
From: Elliot Baptist <elliot.baptist@lowrisc.org>
Date: Thu, 31 Oct 2024 09:16:07 +0000
Subject: [PATCH 15/21] Increase optimisation level

---
 flow/vivado_hook_opt_design_pre.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/flow/vivado_hook_opt_design_pre.tcl b/flow/vivado_hook_opt_design_pre.tcl
index d77544e7e..57f61edcb 100644
--- a/flow/vivado_hook_opt_design_pre.tcl
+++ b/flow/vivado_hook_opt_design_pre.tcl
@@ -6,7 +6,7 @@
 # - Set `opt` to `0` for no extra optimisation (fusesoc Vivado default).
 # - Set `opt` to `1` for light & effective extra optimisation (general use).
 # - Set `opt` to `2` for heavy & chancy extra optimisation (pushing clk speed).
-set opt 1
+set opt 2
 
 if {$opt >= 1} {
   # Over-constrain clock used by the core during early implementation stages

From dd850880282427653548ed9738fa62a015198450 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Sun, 3 Nov 2024 18:44:22 +0000
Subject: [PATCH 16/21] [rtl] Add register stage to SPI internal loopback

Timing failures have been observed on this loopback path, it has minimal
logic levels but a very long delay, possibly due to I/O timing
constraints.

Adding the register stage cuts the internal path. With the register
stage the internal loopback cannot run at full speed, however as this is
for testing purposes only this is acceptable.
---
 rtl/ip/spi/rtl/spi.sv       | 8 +++++++-
 sw/cheri/tests/spi_tests.hh | 4 +++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/rtl/ip/spi/rtl/spi.sv b/rtl/ip/spi/rtl/spi.sv
index 7c6484dd9..a2c4d7186 100644
--- a/rtl/ip/spi/rtl/spi.sv
+++ b/rtl/ip/spi/rtl/spi.sv
@@ -187,7 +187,13 @@ module spi import spi_reg_pkg::*; #(
   // Internal loopback functionality allowing the input (CIPO) to be received directly from
   // the output (COPI) for testing.
   logic spi_cipo;
-  assign spi_cipo = reg2hw.control.int_loopback.q ? spi_copi_o : spi_cipo_i;
+  logic spi_copi_q;
+
+  always_ff @(posedge clk_i) begin
+    spi_copi_q <= spi_copi_o;
+  end
+
+  assign spi_cipo = reg2hw.control.int_loopback.q ? spi_copi_q : spi_cipo_i;
 
   spi_core u_spi_core (
     .clk_i,
diff --git a/sw/cheri/tests/spi_tests.hh b/sw/cheri/tests/spi_tests.hh
index 0a5ab7425..b639f13a2 100644
--- a/sw/cheri/tests/spi_tests.hh
+++ b/sw/cheri/tests/spi_tests.hh
@@ -417,7 +417,9 @@ int spi_irq_test(SpiPtr spi, ds::xoroshiro::P32R8 &prng, Log &log) {
  */
 int spi_loopback_test(SpiPtr spi, bool external, bool cpol, bool cpha, bool msb_first, ds::xoroshiro::P32R8 &prng,
                       Log &log) {
-  constexpr uint32_t kSpiSpeed = 0u;  // Let's go as fast as possible.
+  // Register stage in internal loopback means this is the fastest possible
+  // speed.
+  constexpr uint32_t kSpiSpeed = 1u;
   // Take a copy of the PRNG so that we can predict the read-side data.
   ds::xoroshiro::P32R8 read_prng = prng;
   size_t bytes_read              = 0u;

From c4ff9812729de277333ae34c7df8d9356a4e4a03 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Sun, 3 Nov 2024 14:54:36 +0000
Subject: [PATCH 17/21] [ci] Save bitstream utilization and timing reports as
 artifacts

---
 .github/workflows/ci.yml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index d12df16c2..c03bd75e6 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -86,6 +86,8 @@ jobs:
     runs-on: [ubuntu-22.04-fpga, sonata]
     env:
       BITSTREAM_PATH: build/lowrisc_sonata_system_0/synth-vivado/lowrisc_sonata_system_0.bit
+      TIMING_RPT: build/lowrisc_sonata_system_0/synth-vivado/lowrisc_sonata_system_0.runs/impl_1/top_sonata_timing_summary_routed.rpt
+      UTILIZATION_RPT: build/lowrisc_sonata_system_0/synth-vivado/lowrisc_sonata_system_0.runs/impl_1/top_sonata_utilization_placed.rpt
       GS_PATH: gs://lowrisc-ci-cache/lowRISC/sonata-system/bitstream
 
     steps:
@@ -129,6 +131,14 @@ jobs:
         module load xilinx/vivado
         nix run .#bitstream-build
 
+    - name: Upload implementation reports
+      uses: actions/upload-artifact@v4
+      with:
+        name: implementation-reports
+        path: |
+          ${{ env.TIMING_RPT }}
+          ${{ env.UTILIZATION_RPT }}
+
     # Only upload the bistream if this is not a pull-request and the build bistream step ran. 
     - name: Upload bitstream to the cache
       if: github.event_name != 'pull_request' && env.file_exists == 'false' 

From f0ff867ed38546c968449275741a6e14797d4d10 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Mon, 28 Oct 2024 11:43:19 +0000
Subject: [PATCH 18/21] [rtl] Increase outstanding requests in SRAM wrapper

Need a minimum of 2 (this is what is used in OpenTitan) to enable back
to back requests without stall cycles.
---
 rtl/system/sram.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/rtl/system/sram.sv b/rtl/system/sram.sv
index 76ec17cd7..5e83c03f6 100644
--- a/rtl/system/sram.sv
+++ b/rtl/system/sram.sv
@@ -59,7 +59,8 @@ module sram #(
   // TL-UL device adapters
   tlul_adapter_sram #(
     .SramAw           ( SramAw ),
-    .EnableRspIntgGen ( 0      )
+    .EnableRspIntgGen ( 0      ),
+    .Outstanding      ( 2      )
   ) sram_a_device_adapter (
     .clk_i,
     .rst_ni,
@@ -96,7 +97,8 @@ module sram #(
 
   tlul_adapter_sram #(
     .SramAw           ( SramAw ),
-    .EnableRspIntgGen ( 0      )
+    .EnableRspIntgGen ( 0      ),
+    .Outstanding      ( 2      )
   ) sram_b_device_adapter (
     .clk_i,
     .rst_ni,

From a2b4006a638eeb4e95948cd8815c5ef76f07d12f Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Mon, 28 Oct 2024 15:54:15 +0000
Subject: [PATCH 19/21] Update lowrisc_ibex to lowrisc/cheriot-ibex@ea2df9db

Update code from upstream repository
https://github.com/lowrisc/cheriot-ibex.git to revision
ea2df9db3bcea776f0dc72d6d89c31c73798ecd4

* Feed RV32M through ibexc_top_tracing/ibexc_top (Greg Chadwick)
* Switch to no bitmanip by default (Greg Chadwick)
* Feed RV32B through in ibexc_top (Greg Chadwick)

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
---
 vendor/lowrisc_ibex.lock.hjson               | 2 +-
 vendor/lowrisc_ibex/rtl/ibexc_top.sv         | 5 +++--
 vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv | 4 +++-
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/vendor/lowrisc_ibex.lock.hjson b/vendor/lowrisc_ibex.lock.hjson
index 2572a83f2..4289d933f 100644
--- a/vendor/lowrisc_ibex.lock.hjson
+++ b/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowrisc/cheriot-ibex.git
-    rev: adc4803d5d13cdf5a629b3f53fb4ce8d1ac38fe5
+    rev: ea2df9db3bcea776f0dc72d6d89c31c73798ecd4
   }
 }
diff --git a/vendor/lowrisc_ibex/rtl/ibexc_top.sv b/vendor/lowrisc_ibex/rtl/ibexc_top.sv
index e725f7fdb..bf3bdeb66 100644
--- a/vendor/lowrisc_ibex/rtl/ibexc_top.sv
+++ b/vendor/lowrisc_ibex/rtl/ibexc_top.sv
@@ -26,6 +26,7 @@ module ibexc_top import ibex_pkg::*; import cheri_pkg::*; #(
   parameter int unsigned MHPMCounterNum   = 0,
   parameter int unsigned MHPMCounterWidth = 40,
   parameter bit          RV32E            = 1'b0,
+  parameter rv32m_e      RV32M            = RV32MFast,
   parameter rv32b_e      RV32B            = RV32BNone,
   parameter bit          WritebackStage   = 1'b1,
   parameter bit          BranchPredictor  = 1'b0,
@@ -258,8 +259,8 @@ module ibexc_top import ibex_pkg::*; import cheri_pkg::*; #(
     .MHPMCounterNum   (MHPMCounterNum  ),
     .MHPMCounterWidth (MHPMCounterWidth),
     .RV32E            (RV32E),
-    .RV32M            (RV32MFast),
-    .RV32B            (RV32BNone),
+    .RV32M            (RV32M),
+    .RV32B            (RV32B),
     .BranchTargetALU  (1'b1),
     .ICache           (ICache),
     .ICacheECC        (1'b0),
diff --git a/vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv b/vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv
index f89489bc0..8c2d0083a 100644
--- a/vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv
+++ b/vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv
@@ -14,12 +14,13 @@ module ibexc_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
   parameter int unsigned DmHaltAddr       = 32'h1A110800,
   parameter int unsigned DmExceptionAddr  = 32'h1A110808,
   parameter bit          RV32E            = 1'b0,
+  parameter rv32m_e      RV32M            = RV32MFast,
+  parameter rv32b_e      RV32B            = RV32BNone,
   parameter bit          CheriTBRE        = 1'b1,
   parameter bit          CheriStkZ        = 1'b1,
   parameter bit          DbgTriggerEn     = 1'b1,
   parameter int unsigned DbgHwBreakNum    = 4,
   parameter int unsigned MHPMCounterNum   = 0,
-  parameter rv32b_e      RV32B            = RV32BFull,
   parameter int unsigned HeapBase         = 32'h2001_0000,
   parameter int unsigned TSMapBase        = 32'h2004_0000, // 4kB default
   parameter int unsigned TSMapSize        = 1024,          // in words
@@ -155,6 +156,7 @@ module ibexc_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
     .DbgTriggerEn     (DbgTriggerEn),
     .DbgHwBreakNum    (DbgHwBreakNum),
     .RV32E            (RV32E),
+    .RV32M            (RV32M),
     .RV32B            (RV32B),
     .WritebackStage   (1'b1),
     .BranchPredictor  (1'b0),

From 0f366cbdb2501a84cb8dc8ec6fdd388ce1e5a122 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Mon, 28 Oct 2024 15:55:08 +0000
Subject: [PATCH 20/21] [rtl] Explicitly set RV32B/RV32M for Ibex

This is effectively a no-op change. Before the latest Ibex was vendored
we had no bitmanip (the RV32BFull parameter was not fully passed
through) and RV32M was the fast multiplier.

Sadly the single cycle multiplier seems to be increasing timing
pressure. It does just meet timing but greatly increases synthesis
times. As it's implemented with in-built FPGA DSP blocks it shouldn't be
a big issue to use it so something to examine here but for now leave
things as they are.
---
 rtl/system/sonata_system.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
index d14d53a32..6a03e2905 100644
--- a/rtl/system/sonata_system.sv
+++ b/rtl/system/sonata_system.sv
@@ -757,7 +757,8 @@ module sonata_system
     .HeapBase        ( tl_main_pkg::ADDR_SPACE_SRAM            ),
     .TSMapBase       ( tl_main_pkg::ADDR_SPACE_REV_TAG         ),
     .TSMapSize       ( RevTagDepth                             ),
-    .RV32B           ( ibex_pkg::RV32BFull                     ),
+    .RV32M           ( ibex_pkg::RV32MFast                     ),
+    .RV32B           ( ibex_pkg::RV32BNone                     ),
     .ICache          ( 1'b1                                    )
   ) u_top_tracing (
     .clk_i                  (clk_sys_i),

From 8235bc73c7cba686cd820a22165339fd390583fe Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 30 Oct 2024 08:37:08 +0000
Subject: [PATCH 21/21] Switch to single cycle multiplier for Ibex

---
 rtl/system/sonata_system.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
index 6a03e2905..3ced235b9 100644
--- a/rtl/system/sonata_system.sv
+++ b/rtl/system/sonata_system.sv
@@ -757,7 +757,7 @@ module sonata_system
     .HeapBase        ( tl_main_pkg::ADDR_SPACE_SRAM            ),
     .TSMapBase       ( tl_main_pkg::ADDR_SPACE_REV_TAG         ),
     .TSMapSize       ( RevTagDepth                             ),
-    .RV32M           ( ibex_pkg::RV32MFast                     ),
+    .RV32M           ( ibex_pkg::RV32MSingleCycle              ),
     .RV32B           ( ibex_pkg::RV32BNone                     ),
     .ICache          ( 1'b1                                    )
   ) u_top_tracing (