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params.json
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params.json
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{
"name": "ICEPOLE",
"tagline": "High-speed, Hardware-oriented Authenticated Encryption",
"body": "### ICEPOLE\r\nICEPOLE is a high-speed hardware-oriented scheme, suitable for high-throughput network nodes or\r\ngenerally any environment where specialized hardware (such as FPGAs or ASICs) can be used to\r\nprovide high data processing rates. ICEPOLE-128 (the primary ICEPOLE variant) is very fast.\r\nOn the modern FPGA device Virtex 6, a basic iterative architecture of ICEPOLE reaches 41\r\nGbits/s, which is over 10 times faster than the equivalent implementation of AES-128-GCM. The\r\nthroughput-to-area ratio is also substantially better when compared to AES-128-GCM. We have\r\ncarefully examined the security of the algorithm through a range of cryptanalytic techniques and\r\nour findings indicate that ICEPOLE offers high security level.\r\n\r\n### Specification\r\n[Specification]()\r\n\r\n[CHES paper](https://eprint.iacr.org/2014/266.pdf)\r\n\r\n### Third party cryptanalysis\r\n[Paper 1]()\r\n\r\n[Paper 2]()\r\n\r\n[Paper 3]()\r\n\r\n### Hardware Performance\r\n\r\n\r\n| | Xilinx Virtex 6 | Altera Stratix IV |\r\n| |ICEPOLE-128| AES-128-GCM|ratio | ICEPOLE-128 | AES-128-GCM | ratio|\r\n|---------------------|:-------:|------:|------:|------:|------:|------:|\r\n| throughput (Gbit/s) | 41.364 | 3.539 | 11.7 | 38.779 | 3.612 | 10.7 |\r\n| area (Slices/ALUT) | 1501 | 940 |1.6 |4564 | 4025 | 1.13 |\r\n| throughput-to-area | 27.56 | 3.76 |7.3 |8.5 |0.9 |9.4 |\r\n\r\n \r\nThe comparison between ICEPOLE-128 and AES-128-GCM using an iterative architecture\r\n\r\n### Authors \r\n\r\nPaweł Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik\r\n\r\n### Contact\r\n",
"note": "Don't delete this file! It's used internally to help with page regeneration."
}