From 05ae2206cab37d98d6112af64866a190406d2ead Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20B=C4=83l=C4=83nic=C4=83?= Date: Sat, 11 Mar 2023 01:07:05 +0200 Subject: [PATCH] Add partial XHCI support This enables the first two DWC3 controllers in host mode (bottom USB-A and Type-C on the ROCK5B). SuperSpeed is disabled for now. Also switch to XhciDxe and EhciDxe from MdeModulePkg and disable OHCI. --- .../Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl | 2 + .../Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl | 54 +++ .../RockchipPlatformLib/RockchipPlatformLib.c | 12 +- .../Platform/Radxa/ROCK5B/ROCK5B.dsc | 9 +- .../Platform/Radxa/ROCK5B/ROCK5B.fdf | 8 +- .../Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c | 345 ++++++++++++++++++ .../Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h | 156 ++++++++ .../Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf | 52 +++ .../Include/Library/RockchipPlatformLib.h | 2 +- 9 files changed, 626 insertions(+), 14 deletions(-) create mode 100644 edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl create mode 100644 edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c create mode 100644 edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h create mode 100644 edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf diff --git a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl index df3691a59..2d9c93f88 100755 --- a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl +++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl @@ -107,5 +107,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2) // won't work on Windows, will trigger bugcheck by usbehci // include ("Usb2.asl") + + include ("Usb3.asl") } } diff --git a/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl new file mode 100644 index 000000000..1a1e3f585 --- /dev/null +++ b/edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl @@ -0,0 +1,54 @@ +/** @file +* DWC3 XHCI Controllers. +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "AcpiTables.h" + +Device (XHC0) { + Name (_HID, "PNP0D10") + Name (_UID, Zero) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfc000000, 0x400000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 } + }) + Return (RBUF) + } +} + +Device (XHC1) { + Name (_HID, "PNP0D10") + Name (_UID, One) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfc400000, 0x400000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 } + }) + Return (RBUF) + } +} + +// TODO: This requires set up of the Naneng Combo PIPE PHY2 +// USB2 DP / DM are connected to one of the EHCI controllers instead (EHC1 on ROCK 5B). +/* +Device (XHC2) { + Name (_HID, "PNP0D10") + Name (_UID, Two) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfcd00000, 0x400000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 } + }) + Return (RBUF) + } +}*/ diff --git a/edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c index c6517487a..b5da2dbe3 100644 --- a/edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c +++ b/edk2-platforms/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -209,6 +209,7 @@ void EFIAPI Usb2PhyResume (void) { + MmioWrite32(0xfd5d0008, 0x20000000); MmioWrite32(0xfd5d4008, 0x20000000); MmioWrite32(0xfd5d8008, 0x20000000); MmioWrite32(0xfd5dc008, 0x20000000); @@ -218,12 +219,13 @@ Usb2PhyResume (void) void EFIAPI -UdPhyU3PortDisable (void) +UsbDpPhyEnable (void) { - /* disable U3 port */ - MmioWrite32 (0xfd5ac01c, 0xf08d0089); - MmioWrite32 (0xfd5ac034, 0xf08d0089); - /* remove rx-termination */ + /* enable rx_lfps_en & usbdp_low_pwrn */ + MmioWrite32(0xfd5c8004, 0x60006000); + MmioWrite32(0xfd5cc004, 0x60006000); + + /* remove rx-termination, we don't support SS yet */ MmioWrite32 (0xfd5c800c, 0x00030001); MmioWrite32 (0xfd5cc00c, 0x00030001); } diff --git a/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc b/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc index 00807796c..a2eb7e1c4 100644 --- a/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc +++ b/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc @@ -453,25 +453,26 @@ # Platform/Radxa/ROCK5B/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + # # USB Ohci Controller # - Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf + #Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf # # USB Ehci Controller # - Silicon/Rockchip/Drivers/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf # # USB Dwc3 Controller # - Silicon/Rockchip/Drivers/UsbDwc3InitDxe/UsbDwc3.inf + Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf # # USB Xhci Controller # - Silicon/Rockchip/Drivers/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf # # USB Host Support diff --git a/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.fdf b/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.fdf index 70b8813be..8ad225427 100644 --- a/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.fdf +++ b/edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.fdf @@ -178,22 +178,22 @@ READ_LOCK_STATUS = TRUE # # USB Ehci Controller # - INF Silicon/Rockchip/Drivers/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf # # USB Ohci Controller # - INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf + #INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf # # USB Dwc3 Controller # - INF Silicon/Rockchip/Drivers/UsbDwc3InitDxe/UsbDwc3.inf + INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf # # USB Xhci Controller # - INF Silicon/Rockchip/Drivers/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf # # USB Host Support diff --git a/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c b/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c new file mode 100644 index 000000000..66d62f02b --- /dev/null +++ b/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c @@ -0,0 +1,345 @@ +/** @file + + Copyright 2017, 2020 NXP + Copyright 2021, Jared McNeill + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#include "UsbHcd.h" + +STATIC +VOID +XhciSetBeatBurstLength ( + IN UINTN UsbReg + ) +{ + DWC3 *Dwc3Reg; + + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET); + + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK, + USB3_ENABLE_BEAT_BURST); + + MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT); +} + +STATIC +VOID +Dwc3SetFladj ( + IN DWC3 *Dwc3Reg, + IN UINT32 Val + ) +{ + MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL | + GFLADJ_30MHZ (Val)); +} + +STATIC +VOID +Dwc3SetMode ( + IN DWC3 *Dwc3Reg, + IN UINT32 Mode + ) +{ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl, + ~(DWC3_GCTL_PRTCAPDIR (DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR (Mode)); +} + +/** + This function issues phy reset and core soft reset + + @param Dwc3Reg Pointer to DWC3 register. + +**/ +STATIC +VOID +Dwc3CoreSoftReset ( + IN DWC3 *Dwc3Reg + ) +{ + // + // Put core in reset before resetting PHY + // + MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET); + + // + // Assert USB2 PHY reset + // + MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + // + // Assert USB3 PHY reset + // + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); + + MemoryFence (); + + // + // Clear USB3 PHY reset + // + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST); + + // + // Clear USB2 PHY reset + // + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_PHYSOFTRST); + + MemoryFence (); + + // + // Take core out of reset, PHYs are stable now + // + MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET); +} + +/** + This function performs low-level initialization of DWC3 Core + + @param Dwc3Reg Pointer to DWC3 register. + +**/ +STATIC +EFI_STATUS +Dwc3CoreInit ( + IN DWC3 *Dwc3Reg + ) +{ + UINT32 Revision; + UINT32 Reg; + UINTN Dwc3Hwparams1; + + Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId); + // + // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision num + // + if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSYS_ID) { + DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n")); + return EFI_NOT_FOUND; + } + + Dwc3CoreSoftReset (Dwc3Reg); + + Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl); + Reg &= ~DWC3_GCTL_SCALEDOWN_MASK; + Reg &= ~DWC3_GCTL_DISSCRAMBLE; + + Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1); + + if (DWC3_GHWPARAMS1_EN_PWROPT (Dwc3Hwparams1) == + DWC3_GHWPARAMS1_EN_PWROPT_CLK) { + Reg &= ~DWC3_GCTL_DSBLCLKGTNG; + } else { + DEBUG ((DEBUG_WARN,"No power optimization available.\n")); + } + + if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) { + Reg |= DWC3_GCTL_U2RSTECN; + } + + MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +XhciCoreInit ( + IN UINTN UsbReg + ) +{ + EFI_STATUS Status; + DWC3 *Dwc3Reg; + + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET); + + Status = Dwc3CoreInit (Dwc3Reg); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%r) \n", + UsbReg, Status)); + + return Status; + } + + Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST); + + Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT); + + /* UTMI+ mode */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK, DWC3_GUSB2PHYCFG_USBTRDTIM(5)); + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], DWC3_GUSB2PHYCFG_PHYIF); + + /* snps,dis_enblslpm_quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_ENBLSLPM, 0); + /* snps,dis-u2-freeclk-exists-quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS, 0); + /* snps,dis_u2_susphy_quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_SUSPHY, 0); + /* snps,dis-del-phy-power-chg-quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_DEPOCHANGE, 0); + /* snps,dis-tx-ipgap-linecheck-quirk */ + MmioOr32 ((UINTN)&Dwc3Reg->GUctl1, DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS); + + /* Set max speed */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->DCfg, ~DCFG_SPEED_MASK, DCFG_SPEED_SS); + + return Status; +} + +EFIAPI +EFI_STATUS +InitializeXhciController ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS UsbReg = This->Resources->AddrRangeMin; + + DEBUG ((DEBUG_ERROR, "XHCI: Initialize DWC3 at 0x%lX\n", UsbReg)); + + Status = XhciCoreInit (UsbReg); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "XHCI: Controller init Failed for 0x%lX (0x%r)\n", + UsbReg, Status)); + return EFI_DEVICE_ERROR; + } + + // + // Change beat burst and outstanding pipelined transfers requests + // + XhciSetBeatBurstLength (UsbReg); + + return EFI_SUCCESS; +} + +/** + This function gets registered as a callback to perform USB controller intialization + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context. + +**/ +VOID +EFIAPI +UsbEndOfDxeCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINT32 NumUsb2Controller; + UINT32 NumUsb3Controller; + UINT32 XhciControllerAddr; + UINT32 EhciControllerAddr; + UINT32 OhciControllerAddr; + UINT32 Index; + + gBS->CloseEvent (Event); + + NumUsb3Controller = PcdGet32 (PcdNumDwc3Controller); + NumUsb2Controller = PcdGet32 (PcdNumEhciController); + + /* Enable USB PHYs */ + Usb2PhyResume(); + + UsbDpPhyEnable(); + + UsbPortPowerEnable (); + + /* Register USB3 controllers */ + for (Index = 0; Index < NumUsb3Controller; Index++) { + XhciControllerAddr = PcdGet32 (PcdDwc3BaseAddress) + + (Index * PcdGet32 (PcdDwc3Size)); + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeXhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + InitializeXhciController, + NULL, + 1, + XhciControllerAddr, PcdGet32 (PcdDwc3Size) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register XHCI device 0x%x, error 0x%r \n", + XhciControllerAddr, Status)); + } + } + + /* Register USB2 controllers */ + for (Index = 0; Index < NumUsb2Controller; Index++) { + EhciControllerAddr = PcdGet32 (PcdEhciBaseAddress) + + (Index * PcdGet32 (PcdEhciSize)); + OhciControllerAddr = EhciControllerAddr + 0x10000; + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeEhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + EhciControllerAddr, 0x10000 + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register EHCI device 0x%x, error 0x%r \n", + EhciControllerAddr, Status)); + } + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeOhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + OhciControllerAddr, 0x10000 + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register OHCI device 0x%x, error 0x%r \n", + OhciControllerAddr, Status)); + } + } +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +InitializeUsbHcd ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + UsbEndOfDxeCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + + return Status; +} diff --git a/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h b/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h new file mode 100644 index 000000000..24dc5ec53 --- /dev/null +++ b/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h @@ -0,0 +1,156 @@ +/** @file + + Copyright 2017, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef USB_HCD_H_ +#define USB_HCD_H_ + +#include + +/* Global constants */ +#define DWC3_GSNPSID_MASK 0xffff0000 +#define DWC3_SYNOPSYS_ID 0x55330000 +#define DWC3_RELEASE_MASK 0xffff +#define DWC3_REG_OFFSET 0xC100 +#define DWC3_RELEASE_190a 0x190a + +/* Global Configuration Register */ +#define DWC3_GCTL_U2RSTECN BIT16 +#define DWC3_GCTL_PRTCAPDIR(N) ((N) << 12) +#define DWC3_GCTL_PRTCAP_HOST 1 +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_CORESOFTRESET BIT11 +#define DWC3_GCTL_SCALEDOWN(N) ((N) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE BIT3 +#define DWC3_GCTL_DSBLCLKGTNG BIT0 + +/* Global HWPARAMS1 Register */ +#define DWC3_GHWPARAMS1_EN_PWROPT(N) (((N) & (3 << 24)) >> 24) +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 + +/* Global UCTL1 Register */ +#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT28 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT31 +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT30 +#define DWC3_GUSB2PHYCFG_USBTRDTIM(N) (((N) & 0xf) << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_SUSPHY BIT6 +#define DWC3_GUSB2PHYCFG_PHYIF BIT3 +#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT0 + +/* Global USB3 PIPE Control Register */ +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT31 +#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT18 + +/* Global Frame Length Adjustment Register */ +#define GFLADJ_30MHZ_REG_SEL BIT7 +#define GFLADJ_30MHZ(N) ((N) & 0x3f) +#define GFLADJ_30MHZ_DEFAULT 0x20 + +/* Default to the FSL XHCI defines */ +#define USB3_ENABLE_BEAT_BURST 0xF +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF +#define USB3_SET_BEAT_BURST_LIMIT 0xF00 + +/* DCFG Register */ +#define DCFG_SPEED_MASK (BIT2|BIT1|BIT0) +#define DCFG_SPEED_HS 0 +#define DCFG_SPEED_FS 1 +#define DCFG_SPEED_LS 2 +#define DCFG_SPEED_SS 4 +#define DCFG_SPEED_SS_PLUS 5 + +typedef struct { + UINT32 GEvntAdrLo; + UINT32 GEvntAdrHi; + UINT32 GEvntSiz; + UINT32 GEvntCount; +} G_EVENT_BUFFER; + +typedef struct { + UINT32 DDepCmdPar2; + UINT32 DDepCmdPar1; + UINT32 DDepCmdPar0; + UINT32 DDepCmd; +} D_PHYSICAL_EP; + +typedef struct { + UINT32 GSBusCfg0; + UINT32 GSBusCfg1; + UINT32 GTxThrCfg; + UINT32 GRxThrCfg; + UINT32 GCtl; + UINT32 Res1; + UINT32 GSts; + UINT32 GUctl1; + UINT32 GSnpsId; + UINT32 GGpio; + UINT32 GUid; + UINT32 GUctl; + UINT64 GBusErrAddr; + UINT64 GPrtbImap; + UINT32 GHwParams0; + UINT32 GHwParams1; + UINT32 GHwParams2; + UINT32 GHwParams3; + UINT32 GHwParams4; + UINT32 GHwParams5; + UINT32 GHwParams6; + UINT32 GHwParams7; + UINT32 GDbgFifoSpace; + UINT32 GDbgLtssm; + UINT32 GDbgLnmcc; + UINT32 GDbgBmu; + UINT32 GDbgLspMux; + UINT32 GDbgLsp; + UINT32 GDbgEpInfo0; + UINT32 GDbgEpInfo1; + UINT64 GPrtbImapHs; + UINT64 GPrtbImapFs; + UINT32 Res3[28]; + UINT32 GUsb2PhyCfg[16]; + UINT32 GUsb2I2cCtl[16]; + UINT32 GUsb2PhyAcc[16]; + UINT32 GUsb3PipeCtl[16]; + UINT32 GTxFifoSiz[32]; + UINT32 GRxFifoSiz[32]; + G_EVENT_BUFFER GEvntBuf[32]; + UINT32 GHwParams8; + UINT32 Res4[11]; + UINT32 GFLAdj; + UINT32 Res5[51]; + UINT32 DCfg; + UINT32 DCtl; + UINT32 DEvten; + UINT32 DSts; + UINT32 DGCmdPar; + UINT32 DGCmd; + UINT32 Res6[2]; + UINT32 DAlepena; + UINT32 Res7[55]; + D_PHYSICAL_EP DPhyEpCmd[32]; + UINT32 Res8[128]; + UINT32 OCfg; + UINT32 OCtl; + UINT32 OEvt; + UINT32 OEvtEn; + UINT32 OSts; + UINT32 Res9[3]; + UINT32 AdpCfg; + UINT32 AdpCtl; + UINT32 AdpEvt; + UINT32 AdpEvten; + UINT32 BcCfg; + UINT32 Res10; + UINT32 BcEvt; + UINT32 BcEvten; +} DWC3; + +#endif diff --git a/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf b/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf new file mode 100644 index 000000000..edc5dac9c --- /dev/null +++ b/edk2-platforms/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf @@ -0,0 +1,52 @@ +# UsbHcd.inf +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = UsbHcdDxe + FILE_GUID = 196e7c2a-37b2-4b85-8683-718588952449 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeUsbHcd + +[Sources.common] + UsbHcd.c + UsbHcd.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + RockchipPlatformLib + +[FixedPcd] + gRockchipTokenSpaceGuid.PcdOhciBaseAddress + gRockchipTokenSpaceGuid.PcdNumOhciController + gRockchipTokenSpaceGuid.PcdOhciSize + gRockchipTokenSpaceGuid.PcdEhciBaseAddress + gRockchipTokenSpaceGuid.PcdNumEhciController + gRockchipTokenSpaceGuid.PcdEhciSize + gRockchipTokenSpaceGuid.PcdDwc3BaseAddress + gRockchipTokenSpaceGuid.PcdNumDwc3Controller + gRockchipTokenSpaceGuid.PcdDwc3Size + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/edk2-platforms/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h b/edk2-platforms/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h index 68210a530..39cc28ca2 100644 --- a/edk2-platforms/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h +++ b/edk2-platforms/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h @@ -74,7 +74,7 @@ I2cGetBase ( void EFIAPI -UdPhyU3PortDisable (void); +UsbDpPhyEnable (void); void EFIAPI