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Run any RVV based Core for further RVV Understanding #71

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shahzaibk23 opened this issue Oct 20, 2023 · 1 comment
Open

Run any RVV based Core for further RVV Understanding #71

shahzaibk23 opened this issue Oct 20, 2023 · 1 comment
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rtl Implementation in Chisel Vector Implementation

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@shahzaibk23
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To Review any Open Source RVV Core for further researching and figuring things out.
@shahzaibk23 shahzaibk23 added rtl Implementation in Chisel Vector Implementation labels Oct 20, 2023
@latifbhatti
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I've researched another co-processor called Vicuna, which supports the vector extension built using the System Verilog language. I've created a .VCD file to visualize the output of elective (emul), (evl), and number field (nf) on GTK Wave.

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@shahzaibk23 @latifbhatti