diff --git a/.gitmodules b/.gitmodules index cf2203975f..477fa5145b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -40,3 +40,6 @@ [submodule "fpga/src/ariane-ethernet"] path = fpga/src/ariane-ethernet url = https://github.com/lowRISC/ariane-ethernet.git +[submodule "src/axi_riscv_atomics"] + path = src/axi_riscv_atomics + url = https://github.com/pulp-platform/axi_riscv_atomics.git diff --git a/.travis.yml b/.travis.yml index 0fc805e671..18d44591af 100644 --- a/.travis.yml +++ b/.travis.yml @@ -41,7 +41,7 @@ env: branches: only: - master - - ariane_next + - ariane-dev before_install: - export CXX=g++-7 CC=gcc-7 @@ -72,7 +72,7 @@ jobs: name: build gcc script: - ci/build-riscv-gcc.sh 1 - - rm -rf $RISCV/riscv-gnu-toolchain + - rm -rf $RISCV/riscv-gnu-toolchain - stage: compile2 name: build tools script: diff --git a/Makefile b/Makefile index e48eed47c7..26ca3eae27 100644 --- a/Makefile +++ b/Makefile @@ -90,6 +90,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ $(wildcard fpga/src/axi_slice/src/*.sv) \ $(wildcard src/plic/*.sv) \ $(wildcard src/axi_node/src/*.sv) \ + $(wildcard src/axi_riscv_atomics/src/*.sv) \ $(wildcard src/axi_mem_if/src/*.sv) \ $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \ $(wildcard src/debug/debug_rom/*.sv) \ diff --git a/fpga/src/ariane_xilinx.sv b/fpga/src/ariane_xilinx.sv index dd4988e7d1..7413c2647d 100644 --- a/fpga/src/ariane_xilinx.sv +++ b/fpga/src/ariane_xilinx.sv @@ -209,7 +209,8 @@ axi_node_wrap_with_slices #( ariane_soc::EthernetBase + ariane_soc::EthernetLength -1, ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1, ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1 - }) + }), + .valid_rule_i ('1) ); // --------------- @@ -446,51 +447,72 @@ logic s_axi_rlast; logic s_axi_rvalid; logic s_axi_rready; -assign master[ariane_soc::DRAM].r_user = '0; -assign master[ariane_soc::DRAM].b_user = '0; +AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) +) dram(); + +axi_riscv_atomics #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ), + .AXI_MAX_WRITE_TXNS ( 1 ), + .RISCV_WORD_WIDTH ( 64 ) +) i_axi_riscv_atomics ( + .clk_i ( clk ), + .rst_ni ( ndmreset_n ), + .slv ( master[ariane_soc::DRAM] ), + .mst ( dram ) +); + +assign dram.r_user = '0; +assign dram.b_user = '0; xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr ( - .s_axi_aclk ( clk ), - .s_axi_aresetn ( ndmreset_n ), - .s_axi_awid ( master[ariane_soc::DRAM].aw_id ), - .s_axi_awaddr ( master[ariane_soc::DRAM].aw_addr ), - .s_axi_awlen ( master[ariane_soc::DRAM].aw_len ), - .s_axi_awsize ( master[ariane_soc::DRAM].aw_size ), - .s_axi_awburst ( master[ariane_soc::DRAM].aw_burst ), - .s_axi_awlock ( master[ariane_soc::DRAM].aw_lock ), - .s_axi_awcache ( master[ariane_soc::DRAM].aw_cache ), - .s_axi_awprot ( master[ariane_soc::DRAM].aw_prot ), - .s_axi_awregion ( master[ariane_soc::DRAM].aw_region ), - .s_axi_awqos ( master[ariane_soc::DRAM].aw_qos ), - .s_axi_awvalid ( master[ariane_soc::DRAM].aw_valid ), - .s_axi_awready ( master[ariane_soc::DRAM].aw_ready ), - .s_axi_wdata ( master[ariane_soc::DRAM].w_data ), - .s_axi_wstrb ( master[ariane_soc::DRAM].w_strb ), - .s_axi_wlast ( master[ariane_soc::DRAM].w_last ), - .s_axi_wvalid ( master[ariane_soc::DRAM].w_valid ), - .s_axi_wready ( master[ariane_soc::DRAM].w_ready ), - .s_axi_bid ( master[ariane_soc::DRAM].b_id ), - .s_axi_bresp ( master[ariane_soc::DRAM].b_resp ), - .s_axi_bvalid ( master[ariane_soc::DRAM].b_valid ), - .s_axi_bready ( master[ariane_soc::DRAM].b_ready ), - .s_axi_arid ( master[ariane_soc::DRAM].ar_id ), - .s_axi_araddr ( master[ariane_soc::DRAM].ar_addr ), - .s_axi_arlen ( master[ariane_soc::DRAM].ar_len ), - .s_axi_arsize ( master[ariane_soc::DRAM].ar_size ), - .s_axi_arburst ( master[ariane_soc::DRAM].ar_burst ), - .s_axi_arlock ( master[ariane_soc::DRAM].ar_lock ), - .s_axi_arcache ( master[ariane_soc::DRAM].ar_cache ), - .s_axi_arprot ( master[ariane_soc::DRAM].ar_prot ), - .s_axi_arregion ( master[ariane_soc::DRAM].ar_region ), - .s_axi_arqos ( master[ariane_soc::DRAM].ar_qos ), - .s_axi_arvalid ( master[ariane_soc::DRAM].ar_valid ), - .s_axi_arready ( master[ariane_soc::DRAM].ar_ready ), - .s_axi_rid ( master[ariane_soc::DRAM].r_id ), - .s_axi_rdata ( master[ariane_soc::DRAM].r_data ), - .s_axi_rresp ( master[ariane_soc::DRAM].r_resp ), - .s_axi_rlast ( master[ariane_soc::DRAM].r_last ), - .s_axi_rvalid ( master[ariane_soc::DRAM].r_valid ), - .s_axi_rready ( master[ariane_soc::DRAM].r_ready ), + .s_axi_aclk ( clk ), + .s_axi_aresetn ( ndmreset_n ), + .s_axi_awid ( dram.aw_id ), + .s_axi_awaddr ( dram.aw_addr ), + .s_axi_awlen ( dram.aw_len ), + .s_axi_awsize ( dram.aw_size ), + .s_axi_awburst ( dram.aw_burst ), + .s_axi_awlock ( dram.aw_lock ), + .s_axi_awcache ( dram.aw_cache ), + .s_axi_awprot ( dram.aw_prot ), + .s_axi_awregion ( dram.aw_region ), + .s_axi_awqos ( dram.aw_qos ), + .s_axi_awvalid ( dram.aw_valid ), + .s_axi_awready ( dram.aw_ready ), + .s_axi_wdata ( dram.w_data ), + .s_axi_wstrb ( dram.w_strb ), + .s_axi_wlast ( dram.w_last ), + .s_axi_wvalid ( dram.w_valid ), + .s_axi_wready ( dram.w_ready ), + .s_axi_bid ( dram.b_id ), + .s_axi_bresp ( dram.b_resp ), + .s_axi_bvalid ( dram.b_valid ), + .s_axi_bready ( dram.b_ready ), + .s_axi_arid ( dram.ar_id ), + .s_axi_araddr ( dram.ar_addr ), + .s_axi_arlen ( dram.ar_len ), + .s_axi_arsize ( dram.ar_size ), + .s_axi_arburst ( dram.ar_burst ), + .s_axi_arlock ( dram.ar_lock ), + .s_axi_arcache ( dram.ar_cache ), + .s_axi_arprot ( dram.ar_prot ), + .s_axi_arregion ( dram.ar_region ), + .s_axi_arqos ( dram.ar_qos ), + .s_axi_arvalid ( dram.ar_valid ), + .s_axi_arready ( dram.ar_ready ), + .s_axi_rid ( dram.r_id ), + .s_axi_rdata ( dram.r_data ), + .s_axi_rresp ( dram.r_resp ), + .s_axi_rlast ( dram.r_last ), + .s_axi_rvalid ( dram.r_valid ), + .s_axi_rready ( dram.r_ready ), // to size converter .m_axi_aclk ( ddr_clock_out ), .m_axi_aresetn ( ndmreset_n ), @@ -548,7 +570,7 @@ xlnx_clk_gen i_xlnx_clk_gen ( fan_ctrl i_fan_ctrl ( .clk_i ( clk ), .rst_ni ( ndmreset_n ), - .pwm_setting_i ( sw[3:0] ), + .pwm_setting_i ( '1 ), .fan_pwm_o ( fan_pwm ) ); diff --git a/include/axi_intf.sv b/include/axi_intf.sv index 2df625fae1..1fa2344cba 100644 --- a/include/axi_intf.sv +++ b/include/axi_intf.sv @@ -31,6 +31,7 @@ interface AXI_BUS #( typedef logic [AXI_DATA_WIDTH-1:0] data_t; typedef logic [AXI_STRB_WIDTH-1:0] strb_t; typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [5:0] atop_t; id_t aw_id; addr_t aw_addr; @@ -41,6 +42,7 @@ interface AXI_BUS #( cache_t aw_cache; prot_t aw_prot; qos_t aw_qos; + atop_t aw_atop; region_t aw_region; user_t aw_user; logic aw_valid; @@ -82,7 +84,7 @@ interface AXI_BUS #( logic r_ready; modport Master ( - output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, input aw_ready, + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, input aw_ready, output w_data, w_strb, w_last, w_user, w_valid, input w_ready, input b_id, b_resp, b_user, b_valid, output b_ready, output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready, @@ -90,7 +92,7 @@ interface AXI_BUS #( ); modport Slave ( - input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, output aw_ready, + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, output aw_ready, input w_data, w_strb, w_last, w_user, w_valid, output w_ready, output b_id, b_resp, b_user, b_valid, input b_ready, input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready, @@ -99,7 +101,7 @@ interface AXI_BUS #( /// The interface as an output (issuing requests, initiator, master). modport out ( - output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, input aw_ready, + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, input aw_ready, output w_data, w_strb, w_last, w_user, w_valid, input w_ready, input b_id, b_resp, b_user, b_valid, output b_ready, output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready, @@ -108,7 +110,7 @@ interface AXI_BUS #( /// The interface as an input (accepting requests, target, slave). modport in ( - input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_valid, output aw_ready, + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_valid, output aw_ready, input w_data, w_strb, w_last, w_user, w_valid, output w_ready, output b_id, b_resp, b_user, b_valid, input b_ready, input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready, @@ -140,6 +142,7 @@ interface AXI_BUS_ASYNC logic [3:0] aw_cache; logic [2:0] aw_prot; logic [3:0] aw_qos; + logic [5:0] aw_atop; logic [3:0] aw_region; logic [AXI_USER_WIDTH-1:0] aw_user; logic [BUFFER_WIDTH-1:0] aw_writetoken; @@ -181,7 +184,7 @@ interface AXI_BUS_ASYNC logic [BUFFER_WIDTH-1:0] r_readpointer; modport Master ( - output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_writetoken, input aw_readpointer, + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_writetoken, input aw_readpointer, output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer, input b_id, b_resp, b_user, b_writetoken, output b_readpointer, output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer, @@ -189,7 +192,7 @@ interface AXI_BUS_ASYNC ); modport Slave ( - input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_user, aw_writetoken, output aw_readpointer, + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_atop, aw_region, aw_user, aw_writetoken, output aw_readpointer, input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer, output b_id, b_resp, b_user, b_writetoken, input b_readpointer, input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer, diff --git a/src/axi b/src/axi index d94d601e55..8140a2aa21 160000 --- a/src/axi +++ b/src/axi @@ -1 +1 @@ -Subproject commit d94d601e55213d770beceebfab7786adf7baf8ce +Subproject commit 8140a2aa21e991271741b9865f0b0beea4a73999 diff --git a/src/axi_node b/src/axi_node index 6338af6ee3..a29a69a543 160000 --- a/src/axi_node +++ b/src/axi_node @@ -1 +1 @@ -Subproject commit 6338af6ee3065c4de22b555a67f64755745b7129 +Subproject commit a29a69a543e96d0c9f79ea9c7df20580b3da5002 diff --git a/src/axi_riscv_atomics b/src/axi_riscv_atomics new file mode 160000 index 0000000000..90729df265 --- /dev/null +++ b/src/axi_riscv_atomics @@ -0,0 +1 @@ +Subproject commit 90729df26593ee7b6eb4f55eb2ad665b0f8d1356 diff --git a/src/util/axi_master_connect.sv b/src/util/axi_master_connect.sv index 72cf8c703f..7470f54807 100644 --- a/src/util/axi_master_connect.sv +++ b/src/util/axi_master_connect.sv @@ -26,6 +26,7 @@ module axi_master_connect ( assign master.aw_cache = axi_req_i.aw.cache; assign master.aw_prot = axi_req_i.aw.prot; assign master.aw_qos = axi_req_i.aw.qos; + assign master.aw_atop = axi_req_i.aw.atop; assign master.aw_region = axi_req_i.aw.region; assign master.aw_user = '0; assign master.aw_valid = axi_req_i.aw_valid; diff --git a/src/util/axi_slave_connect.sv b/src/util/axi_slave_connect.sv index 3c6f388e34..d8454ab9f2 100644 --- a/src/util/axi_slave_connect.sv +++ b/src/util/axi_slave_connect.sv @@ -17,7 +17,6 @@ module axi_slave_connect ( AXI_BUS.in slave ); - assign axi_req_o.aw.atop = '0; // not supported at the moment assign axi_req_o.aw.id = slave.aw_id; assign axi_req_o.aw.addr = slave.aw_addr; assign axi_req_o.aw.len = slave.aw_len; @@ -27,6 +26,7 @@ module axi_slave_connect ( assign axi_req_o.aw.cache = slave.aw_cache; assign axi_req_o.aw.prot = slave.aw_prot; assign axi_req_o.aw.qos = slave.aw_qos; + assign axi_req_o.aw.atop = slave.aw_atop; assign axi_req_o.aw.region = slave.aw_region; // assign = slave.aw_user; assign axi_req_o.aw_valid = slave.aw_valid; diff --git a/tb/ariane_testharness.sv b/tb/ariane_testharness.sv index 5ed6ccb7da..aadb035570 100644 --- a/tb/ariane_testharness.sv +++ b/tb/ariane_testharness.sv @@ -242,10 +242,9 @@ module ariane_testharness #( .rdata_o ( rom_rdata ) ); - // --------------- - // Memory - // --------------- - + // ------------------------------ + // Memory + Exclusive Access + // ------------------------------ AXI_BUS #( .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), @@ -260,138 +259,20 @@ module ariane_testharness #( logic [AXI_DATA_WIDTH-1:0] wdata; logic [AXI_DATA_WIDTH-1:0] rdata; - axi_pkg::aw_chan_t aw_chan_i; - axi_pkg::w_chan_t w_chan_i; - axi_pkg::b_chan_t b_chan_o; - axi_pkg::ar_chan_t ar_chan_i; - axi_pkg::r_chan_t r_chan_o; - axi_pkg::aw_chan_t aw_chan_o; - axi_pkg::w_chan_t w_chan_o; - axi_pkg::b_chan_t b_chan_i; - axi_pkg::ar_chan_t ar_chan_o; - axi_pkg::r_chan_t r_chan_i; - - axi_delayer #( - .aw_t ( axi_pkg::aw_chan_t ), - .w_t ( axi_pkg::w_chan_t ), - .b_t ( axi_pkg::b_chan_t ), - .ar_t ( axi_pkg::ar_chan_t ), - .r_t ( axi_pkg::r_chan_t ), - .StallRandomOutput ( StallRandomOutput ), - .StallRandomInput ( StallRandomInput ), - .FixedDelayInput ( 0 ), - .FixedDelayOutput ( 0 ) - ) i_axi_delayer ( - .clk_i ( clk_i ), - .rst_ni ( ndmreset_n ), - .aw_valid_i ( master[ariane_soc::DRAM].aw_valid ), - .aw_chan_i ( aw_chan_i ), - .aw_ready_o ( master[ariane_soc::DRAM].aw_ready ), - .w_valid_i ( master[ariane_soc::DRAM].w_valid ), - .w_chan_i ( w_chan_i ), - .w_ready_o ( master[ariane_soc::DRAM].w_ready ), - .b_valid_o ( master[ariane_soc::DRAM].b_valid ), - .b_chan_o ( b_chan_o ), - .b_ready_i ( master[ariane_soc::DRAM].b_ready ), - .ar_valid_i ( master[ariane_soc::DRAM].ar_valid ), - .ar_chan_i ( ar_chan_i ), - .ar_ready_o ( master[ariane_soc::DRAM].ar_ready ), - .r_valid_o ( master[ariane_soc::DRAM].r_valid ), - .r_chan_o ( r_chan_o ), - .r_ready_i ( master[ariane_soc::DRAM].r_ready ), - .aw_valid_o ( dram.aw_valid ), - .aw_chan_o ( aw_chan_o ), - .aw_ready_i ( dram.aw_ready ), - .w_valid_o ( dram.w_valid ), - .w_chan_o ( w_chan_o ), - .w_ready_i ( dram.w_ready ), - .b_valid_i ( dram.b_valid ), - .b_chan_i ( b_chan_i ), - .b_ready_o ( dram.b_ready ), - .ar_valid_o ( dram.ar_valid ), - .ar_chan_o ( ar_chan_o ), - .ar_ready_i ( dram.ar_ready ), - .r_valid_i ( dram.r_valid ), - .r_chan_i ( r_chan_i ), - .r_ready_o ( dram.r_ready ) + axi_riscv_atomics #( + .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_MAX_WRITE_TXNS ( 1 ), + .RISCV_WORD_WIDTH ( 64 ) + ) i_axi_riscv_atomics ( + .clk_i, + .rst_ni ( ndmreset_n ), + .slv ( master[ariane_soc::DRAM] ), + .mst ( dram ) ); - assign aw_chan_i.atop = '0; - assign aw_chan_i.id = master[ariane_soc::DRAM].aw_id; - assign aw_chan_i.addr = master[ariane_soc::DRAM].aw_addr; - assign aw_chan_i.len = master[ariane_soc::DRAM].aw_len; - assign aw_chan_i.size = master[ariane_soc::DRAM].aw_size; - assign aw_chan_i.burst = master[ariane_soc::DRAM].aw_burst; - assign aw_chan_i.lock = master[ariane_soc::DRAM].aw_lock; - assign aw_chan_i.cache = master[ariane_soc::DRAM].aw_cache; - assign aw_chan_i.prot = master[ariane_soc::DRAM].aw_prot; - assign aw_chan_i.qos = master[ariane_soc::DRAM].aw_qos; - assign aw_chan_i.region = master[ariane_soc::DRAM].aw_region; - - assign ar_chan_i.id = master[ariane_soc::DRAM].ar_id; - assign ar_chan_i.addr = master[ariane_soc::DRAM].ar_addr; - assign ar_chan_i.len = master[ariane_soc::DRAM].ar_len; - assign ar_chan_i.size = master[ariane_soc::DRAM].ar_size; - assign ar_chan_i.burst = master[ariane_soc::DRAM].ar_burst; - assign ar_chan_i.lock = master[ariane_soc::DRAM].ar_lock; - assign ar_chan_i.cache = master[ariane_soc::DRAM].ar_cache; - assign ar_chan_i.prot = master[ariane_soc::DRAM].ar_prot; - assign ar_chan_i.qos = master[ariane_soc::DRAM].ar_qos; - assign ar_chan_i.region = master[ariane_soc::DRAM].ar_region; - - assign w_chan_i.data = master[ariane_soc::DRAM].w_data; - assign w_chan_i.strb = master[ariane_soc::DRAM].w_strb; - assign w_chan_i.last = master[ariane_soc::DRAM].w_last; - - assign master[ariane_soc::DRAM].r_id = r_chan_o.id; - assign master[ariane_soc::DRAM].r_data = r_chan_o.data; - assign master[ariane_soc::DRAM].r_resp = r_chan_o.resp; - assign master[ariane_soc::DRAM].r_last = r_chan_o.last; - - assign master[ariane_soc::DRAM].b_id = b_chan_o.id; - assign master[ariane_soc::DRAM].b_resp = b_chan_o.resp; - - - assign dram.aw_id = aw_chan_o.id; - assign dram.aw_addr = aw_chan_o.addr; - assign dram.aw_len = aw_chan_o.len; - assign dram.aw_size = aw_chan_o.size; - assign dram.aw_burst = aw_chan_o.burst; - assign dram.aw_lock = aw_chan_o.lock; - assign dram.aw_cache = aw_chan_o.cache; - assign dram.aw_prot = aw_chan_o.prot; - assign dram.aw_qos = aw_chan_o.qos; - assign dram.aw_region = aw_chan_o.region; - assign dram.aw_user = master[ariane_soc::DRAM].aw_user; - - assign dram.ar_id = ar_chan_o.id; - assign dram.ar_addr = ar_chan_o.addr; - assign dram.ar_len = ar_chan_o.len; - assign dram.ar_size = ar_chan_o.size; - assign dram.ar_burst = ar_chan_o.burst; - assign dram.ar_lock = ar_chan_o.lock; - assign dram.ar_cache = ar_chan_o.cache; - assign dram.ar_prot = ar_chan_o.prot; - assign dram.ar_qos = ar_chan_o.qos; - assign dram.ar_region = ar_chan_o.region; - assign dram.ar_user = master[ariane_soc::DRAM].ar_user; - - assign dram.w_data = w_chan_o.data; - assign dram.w_strb = w_chan_o.strb; - assign dram.w_last = w_chan_o.last; - assign dram.w_user = master[ariane_soc::DRAM].w_user; - - assign r_chan_i.id = dram.r_id; - assign r_chan_i.data = dram.r_data; - assign r_chan_i.resp = dram.r_resp; - assign r_chan_i.last = dram.r_last; - assign master[ariane_soc::DRAM].r_user = dram.r_user; - - assign b_chan_i.id = dram.b_id; - assign b_chan_i.resp = dram.b_resp; - assign master[ariane_soc::DRAM].b_user = dram.b_user; - - axi2mem #( .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ), .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), @@ -462,7 +343,8 @@ module ariane_testharness #( ariane_soc::EthernetBase + ariane_soc::EthernetLength -1, ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1, ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1 - }) + }), + .valid_rule_i ('1) ); // ---------------