Spindle encoder

[ozzyrob]

Would it be possible to use:
https://github.com/scottalford75/Remora/tree/main/LinuxCNC/Components/PRUencoder
and use the following as a basis for verilog
https://github.com/scottalford75/Remora/tree/main/Firmware/FirmwareSource/Remora-OS5/modules/encoder

If you come up with something with some code I can test and have a go at modification.

[multigcs]

yes it is possible, i already got myself an encoder with z-pin. i will try it the next days, but i have to adapt the linuxncnc componente too

[ozzyrob]

Ahhh yes that as well, that would be great :)

[multigcs]

the FPGA part works already, i use one bit each in the din and dout byte.

if i set the dout bit the din bit also goes to 1
if now the index is reached the din bit changes back to 0 and the counter goes to 0

now i have to check how to connect the whole thing in the hal-component with the bidirectional index-enable signal/bit

[multigcs]

done :)
but have breaking changes, some pin names changed in hal:
rio.input.0 -> rio.din0
rio.output.1 -> rio.dout1

[ozzyrob]

Awesome, will give it a go this weekend.

[multigcs]

www.youtube.com/shorts/vhRBIgLiabI

[kzali]

Hi Oliver I see that you are using this encoder:
https://www.amazon.de/gp/product/B08PDLFKBM/ref=ppx_yo_dt_b_search_asin_title?ie=UTF8&th=1

Is it the 600hz one?

[multigcs]

exactly this one (600Hz)

[ozzyrob]

Awesome !

How does the hal goto together ?

BTW Love the setup you had for testing

[multigcs]

setp rio.PV.4-scale 600
net spindle-position rio.PV.4 => spindle.0.revs
net spindle-index-enable rio.PV.4-index-enable <=> spindle.0.index-enable

git branch g33

i renamed some hal pin names

[ozzyrob]

Thanks mate !