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Copy pathSOIC-8-N_to_DIP-8.sch
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SOIC-8-N_to_DIP-8.sch
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<text x="88.9" y="11.43" size="2.54" layer="94">REV:</text>
<text x="1.27" y="19.05" size="2.54" layer="94">TITLE:</text>
<text x="1.27" y="11.43" size="2.54" layer="94">Document Number:</text>
<text x="17.78" y="19.05" size="2.54" layer="94">>DRAWING_NAME</text>
</symbol>
<symbol name="CONNECTOR_4">
<pin name="1" x="-7.62" y="5.08" length="middle"/>
<pin name="2" x="-7.62" y="2.54" length="middle"/>
<pin name="3" x="-7.62" y="0" length="middle"/>
<pin name="4" x="-7.62" y="-2.54" length="middle"/>
<wire x1="-2.54" y1="7.62" x2="-2.54" y2="-5.08" width="0.254" layer="94"/>
<wire x1="-2.54" y1="-5.08" x2="5.08" y2="-5.08" width="0.254" layer="94"/>
<wire x1="5.08" y1="-5.08" x2="5.08" y2="7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="7.62" x2="-2.54" y2="7.62" width="0.254" layer="94"/>
<text x="-2.54" y="10.16" size="2.0828" layer="95">>NAME</text>
</symbol>
<symbol name="CONNECTOR_4_PINS_5-8">
<pin name="5" x="-7.62" y="2.54" length="middle"/>
<pin name="6" x="-7.62" y="0" length="middle"/>
<pin name="7" x="-7.62" y="-2.54" length="middle"/>
<pin name="8" x="-7.62" y="-5.08" length="middle"/>
<wire x1="-2.54" y1="5.08" x2="-2.54" y2="-7.62" width="0.254" layer="94"/>
<wire x1="-2.54" y1="-7.62" x2="5.08" y2="-7.62" width="0.254" layer="94"/>
<wire x1="5.08" y1="-7.62" x2="5.08" y2="5.08" width="0.254" layer="94"/>
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<text x="-2.54" y="7.62" size="2.0828" layer="95">>NAME</text>
</symbol>
</symbols>
<devicesets>
<deviceset name="DS9638CM" prefix="U">
<description>RS-422 Dual High Speed Differential Line Driver</description>
<gates>
<gate name="A" symbol="DS9638CM" x="0" y="0"/>
</gates>
<devices>
<device name="" package="SOIC127P62X175-8N">
<connects>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="INA" pad="2"/>
<connect gate="A" pin="INB" pad="3"/>
<connect gate="A" pin="OUTA" pad="8"/>
<connect gate="A" pin="OUTB" pad="6"/>
<connect gate="A" pin="OUT~A" pad="7"/>
<connect gate="A" pin="OUT~B" pad="5"/>
<connect gate="A" pin="VCC" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="AVAILABILITY" value="Good"/>
<attribute name="DESCRIPTION" value=" DIFF LINE DRIVER, RS422, SOIC-8; Device Type: Differential Line Driver; IC Interf "/>
<attribute name="MF" value="Texas Instruments"/>
<attribute name="MP" value="DS9638CM/NOPB"/>
<attribute name="PACKAGE" value="SOIC-8 Texas Instruments"/>
<attribute name="PRICE" value="1.08 USD"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LETTER_L" prefix="FRAME" uservalue="yes">
<description><b>FRAME</b><p>
LETTER landscape</description>
<gates>
<gate name="G$1" symbol="LETTER_L" x="0" y="0"/>
<gate name="G$2" symbol="DOCFIELD" x="147.32" y="0" addlevel="must"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="CONNECTOR_4" prefix="J">
<gates>
<gate name="G$1" symbol="CONNECTOR_4" x="0" y="-2.54"/>
</gates>
<devices>
<device name="-0.100_VERTICAL" package="68000-104HLF">
<connects>
<connect gate="G$1" pin="1" pad="1"/>
<connect gate="G$1" pin="2" pad="2"/>
<connect gate="G$1" pin="3" pad="3"/>
<connect gate="G$1" pin="4" pad="4"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="CONNECTOR_4_PINS_5-8" prefix="J">
<gates>
<gate name="G$1" symbol="CONNECTOR_4_PINS_5-8" x="0" y="0"/>
</gates>
<devices>
<device name="" package="68000-104HLF_PINS_5-8">
<connects>
<connect gate="G$1" pin="5" pad="5"/>
<connect gate="G$1" pin="6" pad="6"/>
<connect gate="G$1" pin="7" pad="7"/>
<connect gate="G$1" pin="8" pad="8"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</libraries>
<attributes>
</attributes>
<variantdefs>
</variantdefs>
<classes>
<class number="0" name="default" width="0" drill="0">
</class>
</classes>
<parts>
<part name="U1" library="SnapEDA" deviceset="DS9638CM" device=""/>
<part name="FRAME1" library="SnapEDA" deviceset="LETTER_L" device=""/>
<part name="J1" library="SnapEDA" deviceset="CONNECTOR_4" device="-0.100_VERTICAL"/>
<part name="J2" library="SnapEDA" deviceset="CONNECTOR_4_PINS_5-8" device=""/>
</parts>
<sheets>
<sheet>
<plain>
<text x="148.59" y="24.13" size="2.54" layer="88">SOIC-8-N
SOIC127P62X175-8N
TI DS9638CM</text>
</plain>
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<instance part="U1" gate="A" x="121.92" y="104.14"/>
<instance part="FRAME1" gate="G$1" x="0" y="0"/>
<instance part="FRAME1" gate="G$2" x="147.32" y="0"/>
<instance part="J1" gate="G$1" x="66.04" y="101.6" rot="MR0"/>
<instance part="J2" gate="G$1" x="182.88" y="101.6" rot="MR180"/>
</instances>
<busses>
</busses>
<nets>
<net name="1" class="0">
<segment>
<pinref part="J1" gate="G$1" pin="1"/>
<wire x1="73.66" y1="106.68" x2="83.82" y2="106.68" width="0.1524" layer="91"/>
<label x="83.82" y="106.68" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U1" gate="A" pin="VCC"/>
<wire x1="93.98" y1="106.68" x2="104.14" y2="106.68" width="0.1524" layer="91"/>
<label x="93.98" y="106.68" size="1.778" layer="95"/>
</segment>
</net>
<net name="2" class="0">
<segment>
<pinref part="J1" gate="G$1" pin="2"/>
<wire x1="83.82" y1="104.14" x2="73.66" y2="104.14" width="0.1524" layer="91"/>
<label x="83.82" y="104.14" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U1" gate="A" pin="INA"/>
<wire x1="93.98" y1="101.6" x2="104.14" y2="101.6" width="0.1524" layer="91"/>
<label x="93.98" y="101.6" size="1.778" layer="95"/>
</segment>
</net>
<net name="3" class="0">
<segment>
<pinref part="J1" gate="G$1" pin="3"/>
<wire x1="83.82" y1="101.6" x2="73.66" y2="101.6" width="0.1524" layer="91"/>
<label x="83.82" y="101.6" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U1" gate="A" pin="INB"/>
<wire x1="93.98" y1="99.06" x2="104.14" y2="99.06" width="0.1524" layer="91"/>
<label x="93.98" y="99.06" size="1.778" layer="95"/>
</segment>
</net>
<net name="4" class="0">
<segment>
<pinref part="J1" gate="G$1" pin="4"/>
<wire x1="83.82" y1="99.06" x2="73.66" y2="99.06" width="0.1524" layer="91"/>
<label x="83.82" y="99.06" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U1" gate="A" pin="GND"/>
<wire x1="93.98" y1="93.98" x2="104.14" y2="93.98" width="0.1524" layer="91"/>
<label x="93.98" y="93.98" size="1.778" layer="95"/>
</segment>
</net>
<net name="8" class="0">
<segment>
<pinref part="U1" gate="A" pin="OUTA"/>
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<label x="149.86" y="106.68" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J2" gate="G$1" pin="8"/>
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<label x="165.1" y="106.68" size="1.778" layer="95"/>
</segment>
</net>
<net name="7" class="0">
<segment>
<pinref part="U1" gate="A" pin="OUT~A"/>
<wire x1="149.86" y1="104.14" x2="139.7" y2="104.14" width="0.1524" layer="91"/>
<label x="149.86" y="104.14" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J2" gate="G$1" pin="7"/>
<wire x1="165.1" y1="104.14" x2="175.26" y2="104.14" width="0.1524" layer="91"/>
<label x="165.1" y="104.14" size="1.778" layer="95"/>
</segment>
</net>
<net name="6" class="0">
<segment>
<pinref part="U1" gate="A" pin="OUTB"/>
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<label x="149.86" y="99.06" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J2" gate="G$1" pin="6"/>
<wire x1="165.1" y1="101.6" x2="175.26" y2="101.6" width="0.1524" layer="91"/>
<label x="165.1" y="101.6" size="1.778" layer="95"/>
</segment>
</net>
<net name="5" class="0">
<segment>
<pinref part="U1" gate="A" pin="OUT~B"/>
<wire x1="149.86" y1="96.52" x2="139.7" y2="96.52" width="0.1524" layer="91"/>
<label x="149.86" y="96.52" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="J2" gate="G$1" pin="5"/>
<wire x1="165.1" y1="99.06" x2="175.26" y2="99.06" width="0.1524" layer="91"/>
<label x="165.1" y="99.06" size="1.778" layer="95"/>
</segment>
</net>
</nets>
</sheet>
</sheets>
<errors>
<approved hash="104,1,104.14,106.68,U1,VCC,1,,,"/>
<approved hash="113,1,124.356,92.606,FRAME1,,,,,"/>
</errors>
</schematic>
</drawing>
<compatibility>
<note version="6.3" minversion="6.2.2" severity="warning">
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.
</note>
</compatibility>
</eagle>