diff --git a/.github/workflows/Archived/Build_SKY_EEVB_Release.yaml b/.github/workflows/Archived/Build_SKY_EEVB_Release.yaml new file mode 100644 index 0000000000..53ce646496 --- /dev/null +++ b/.github/workflows/Archived/Build_SKY_EEVB_Release.yaml @@ -0,0 +1,11 @@ +name: Build SKY_EEVB_Release + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_Release: + name: Build SKY_EEVB_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_Release' diff --git a/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Debug.yaml b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Debug.yaml new file mode 100644 index 0000000000..0f8dfe4857 --- /dev/null +++ b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_EEVB_STD_SIF_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF_Debug: + name: Build SKY_EEVB_STD_SIF_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_STD_SIF_Debug' diff --git a/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Release.yaml new file mode 100644 index 0000000000..aeeba5475f --- /dev/null +++ b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -0,0 +1,11 @@ +name: Build SKY_EEVB_STD_SIF_Release + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF_Release: + name: Build SKY_EEVB_STD_SIF_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_STD_SIF_Release' diff --git a/.github/workflows/Archived/Build_SKY_EEVB_Watchdog_Debug.yaml b/.github/workflows/Archived/Build_SKY_EEVB_Watchdog_Debug.yaml new file mode 100644 index 0000000000..e5fd26016b --- /dev/null +++ b/.github/workflows/Archived/Build_SKY_EEVB_Watchdog_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_EEVB_Watchdog_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_Watchdog_Debug: + name: Build SKY_EEVB_Watchdog_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_Watchdog_Debug' diff --git a/.github/workflows/Archived/Build_Si5400_CEVB_Debug.yaml b/.github/workflows/Archived/Build_Si5400_CEVB_Debug.yaml new file mode 100644 index 0000000000..3069ccc16b --- /dev/null +++ b/.github/workflows/Archived/Build_Si5400_CEVB_Debug.yaml @@ -0,0 +1,11 @@ +name: Build Si5400_CEVB_Debug + +on: + workflow_dispatch + +jobs: + build_Si5400_CEVB_Debug: + name: Build Si5400_CEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5400_CEVB_Debug' diff --git a/.github/workflows/Archived/Build_Si5400_CEVB_Release.yaml b/.github/workflows/Archived/Build_Si5400_CEVB_Release.yaml new file mode 100644 index 0000000000..d4d9aafb53 --- /dev/null +++ b/.github/workflows/Archived/Build_Si5400_CEVB_Release.yaml @@ -0,0 +1,11 @@ +name: Build Si5400_CEVB_Release + +on: + workflow_dispatch + +jobs: + build_Si5400_CEVB_Release: + name: Build Si5400_CEVB_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5400_CEVB_Release' diff --git a/.github/workflows/Archived/Build_Si5575_CEVB_Debug.yaml b/.github/workflows/Archived/Build_Si5575_CEVB_Debug.yaml new file mode 100644 index 0000000000..ec53a8a115 --- /dev/null +++ b/.github/workflows/Archived/Build_Si5575_CEVB_Debug.yaml @@ -0,0 +1,11 @@ +name: Build Si5575_CEVB_Debug + +on: + workflow_dispatch + +jobs: + build_Si5575_CEVB_Debug: + name: Build Si5575_CEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5575_CEVB_Debug' diff --git a/.github/workflows/Archived/Build_Si5575_CEVB_Release.yaml b/.github/workflows/Archived/Build_Si5575_CEVB_Release.yaml new file mode 100644 index 0000000000..56e6cadf3b --- /dev/null +++ b/.github/workflows/Archived/Build_Si5575_CEVB_Release.yaml @@ -0,0 +1,11 @@ +name: Build Si5575_CEVB_Release + +on: + workflow_dispatch + +jobs: + build_Si5575_CEVB_Release: + name: Build Si5575_CEVB_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5575_CEVB_Release' diff --git a/.github/workflows/Archived/Makefile b/.github/workflows/Archived/Makefile new file mode 100644 index 0000000000..35a3b44c0d --- /dev/null +++ b/.github/workflows/Archived/Makefile @@ -0,0 +1,8 @@ +usage: + @echo "Use make branch or make main" + +branch: + perl make-sky-yamls.pl --branch + +main: + perl make-sky-yamls.pl --main diff --git a/.github/workflows/Archived/SKY-BUILDS.txt b/.github/workflows/Archived/SKY-BUILDS.txt new file mode 100644 index 0000000000..360ce44a9b --- /dev/null +++ b/.github/workflows/Archived/SKY-BUILDS.txt @@ -0,0 +1,9 @@ +# Format is: +# Target,Preset +SKY_EEVB,SKY_EEVB_Debug +Si5575_CEVB,Si5575_CEVB_Debug + +# No longer used +# SKY_EEVB,SKY_EEVB_Release +# SKY_EEVB,SKY_EEVB_STD_SIF_Release +# SKY_EEVB,SKY_EEVB_STD_SIF_Debug diff --git a/.github/workflows/Archived/make-sky-yamls.pl b/.github/workflows/Archived/make-sky-yamls.pl new file mode 100644 index 0000000000..f52cd24b60 --- /dev/null +++ b/.github/workflows/Archived/make-sky-yamls.pl @@ -0,0 +1,39 @@ +#!/usr/bin/perl + +use strict; +use File::Slurp; + +my $opt = shift; + +my $yaml_file; +if ($opt eq "--main") { + $yaml_file = "build_skyworks_evb.main.yml.template"; +} elsif ($opt eq "--branch") { + $yaml_file = "build_skyworks_evb.yml.template"; +} else { + die "bad usage\n"; +} + +my %presets_found; + +my $builds_file = "SKY-BUILDS.txt"; +my $buff = read_file($builds_file); +my @lines = split /\r\n|\n|\r/, $buff; + +foreach my $line (@lines) +{ + # warn $line; + next if ($line =~ /^\s*#/); + next if ($line =~ /^\s*$/); + my($target,$preset) = split(/,/,$line); + + # Don't allow a preset name to be used more than once + die "preset $preset is used more than one in $builds_file\n" if ($presets_found{$preset}); + $presets_found{$preset} = 1; + + print("$target/$preset ...\n"); + my $yaml = read_file($yaml_file); + $yaml =~ s/\@TARGET\@/$target/g; + $yaml =~ s/\@PRESET\@/$preset/g; + write_file("Build_$preset.yaml", $yaml); +} diff --git a/.github/workflows/Build_Field_Programmer_Debug.yaml b/.github/workflows/Build_Field_Programmer_Debug.yaml new file mode 100644 index 0000000000..fbf4ea368e --- /dev/null +++ b/.github/workflows/Build_Field_Programmer_Debug.yaml @@ -0,0 +1,11 @@ +name: Build FIELD_PROG_Debug + +on: + workflow_dispatch + +jobs: + build_FIELD_PROG_Debug: + name: Build FIELD_PROG_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'FIELD_PROG_Debug' diff --git a/.github/workflows/Build_SKY_CEVB1_Debug.yaml b/.github/workflows/Build_SKY_CEVB1_Debug.yaml new file mode 100644 index 0000000000..285e70da19 --- /dev/null +++ b/.github/workflows/Build_SKY_CEVB1_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_CEVB1_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_CEVB1_Debug: + name: Build SKY_CEVB1_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_CEVB1_Debug' diff --git a/.github/workflows/Build_SKY_CEVB1_Release.yaml b/.github/workflows/Build_SKY_CEVB1_Release.yaml new file mode 100644 index 0000000000..7efe3363b3 --- /dev/null +++ b/.github/workflows/Build_SKY_CEVB1_Release.yaml @@ -0,0 +1,11 @@ +name: Build SKY_CEVB1_Release + +on: + workflow_dispatch + +jobs: + build_SKY_CEVB1_Release: + name: Build SKY_CEVB1_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_CEVB1_Release' diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml new file mode 100644 index 0000000000..b26c649979 --- /dev/null +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_EEVB_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_Debug: + name: Build SKY_EEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_Debug' diff --git a/.github/workflows/Build_STB_Interposer_Debug.yaml b/.github/workflows/Build_STB_Interposer_Debug.yaml new file mode 100644 index 0000000000..62d4043d28 --- /dev/null +++ b/.github/workflows/Build_STB_Interposer_Debug.yaml @@ -0,0 +1,11 @@ +name: Build STB_Interposer_Debug + +on: + workflow_dispatch + +jobs: + build_STB_Interposer_Debug: + name: Build STB_Interposer_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'STB_Interposer_Debug' diff --git a/.github/workflows/build_skyworks_evb.main.yml.template b/.github/workflows/build_skyworks_evb.main.yml.template new file mode 100644 index 0000000000..929cad03b6 --- /dev/null +++ b/.github/workflows/build_skyworks_evb.main.yml.template @@ -0,0 +1,20 @@ +name: Build @PRESET@ + +on: + workflow_dispatch + +jobs: + build_@PRESET@: + runs-on: windows-latest + + steps: + + - name: PLEASE RUN FROM TARGET BRANCH + run: | + + "*****************************************************************" | Write-Host -ForegroundColor White + " ⚠️ Please run the action from the 'skyworks-evb' branch ⚠️ " | Write-Host -ForegroundColor White + "*****************************************************************" | Write-Host -ForegroundColor White + "" | Write-Host -ForegroundColor White -NoNewline + "You can do this by selecting the branch name in the drop-down " | Write-Host -ForegroundColor White + "that shows in the GitHub action runner under 'Use workflow from' " | Write-Host -ForegroundColor White diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template new file mode 100644 index 0000000000..4522c68e21 --- /dev/null +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -0,0 +1,11 @@ +name: Build @PRESET@ + +on: + workflow_dispatch + +jobs: + build_@PRESET@: + name: Build @PRESET@ + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: '@PRESET@' diff --git a/.github/workflows/merge-upstream-skyworks-evb.yml b/.github/workflows/merge-upstream-skyworks-evb.yml new file mode 100644 index 0000000000..d48dbbcd57 --- /dev/null +++ b/.github/workflows/merge-upstream-skyworks-evb.yml @@ -0,0 +1,37 @@ +name: Merge from upstream into skyworks-evb +on: + schedule: + # scheduled for 00:00 every day + - cron: '15 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + ref: skyworks-evb + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4.1 + with: + target_sync_branch: skyworks-evb + upstream_sync_branch: main + upstream_sync_repo: Skyworks-Timing-Software/nf-interpreter + target_repo_token: ${{ secrets.GITHUB_TOKEN }} + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml new file mode 100644 index 0000000000..5d9d245909 --- /dev/null +++ b/.github/workflows/merge-upstream.yml @@ -0,0 +1,37 @@ +name: Merge from upstream into main +on: + schedule: + # scheduled for 00:00 every day + - cron: '0 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + ref: main + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4.1 + with: + target_sync_branch: main + upstream_sync_branch: main + upstream_sync_repo: nanoframework/nf-interpreter + target_repo_token: ${{ secrets.GITHUB_TOKEN }} + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml new file mode 100644 index 0000000000..1a22ad8486 --- /dev/null +++ b/.github/workflows/skyworks_evb_build.yaml @@ -0,0 +1,126 @@ +name: Skyworks .NET nanoFramework target build +run-name: Workflow for Skyworks .NET nanoFramework target build + +on: + workflow_call: + inputs: + targetName: + required: true + type: string + +jobs: + build-skyworks-target: + name: Build Skyworks target + timeout-minutes: 15 + runs-on: windows-latest + + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '13.3.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ inputs.targetName }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ inputs.targetName }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build/build-info.txt" + + $metadata += "Target: ${{ inputs.targetName }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + + - uses: actions/upload-artifact@v4 + with: + name: '${{ inputs.targetName }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build/build-info.txt + + - name: Tag the build + if: ${{ github.event.pull_request.number == null }} + uses: actions/github-script@v7 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ inputs.targetName }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) diff --git a/.gitignore b/.gitignore index 9727ed1dc9..4fc8344f26 100644 --- a/.gitignore +++ b/.gitignore @@ -380,3 +380,4 @@ sdkconfig CMakeUserPresets.json config/user-tools-repos.json config/user-prefs.json +targets/AzureRTOS/SiliconLabs/Si5575_CEVB/.vscode/settings.json diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake new file mode 100644 index 0000000000..0e876fb4c3 --- /dev/null +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake @@ -0,0 +1,52 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Com.SkyworksInc.NanoFramework.Devices.I2c) + + +# set include directories +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Core) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/HAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.I2c) + +# source files +set(Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS + + # nano_sl_i2cspm.c + + com_sky_nf_dev_i2c_native.cpp + com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp + + target_com_sky_nf_dev_i2c_config.cpp +) + +foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS}) + + set(Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.I2c + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE}") + endif() + + list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_SOURCES ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Com.SkyworksInc.NanoFramework.Devices.I2c DEFAULT_MSG Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS Com.SkyworksInc.NanoFramework.Devices.I2c_SOURCES) diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake new file mode 100644 index 0000000000..c7ced8d93c --- /dev/null +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake @@ -0,0 +1,54 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Com.SkyworksInc.NanoFramework.Devices.Spi) + + +# set include directories +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Core) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/HAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.Spi) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/System.Device.Spi) + +# source files +set(Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS + + com_sky_nf_dev_spi_native.cpp + com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp + + target_com_sky_nf_dev_spi_config.cpp + cpu_spi.cpp +) + +foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS}) + + set(Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${CMAKE_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.Spi + ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Device.Spi + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE}") + endif() + + list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_SOURCES ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Com.SkyworksInc.NanoFramework.Devices.Spi DEFAULT_MSG Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS Com.SkyworksInc.NanoFramework.Devices.Spi_SOURCES) diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index bf697344d3..114eae5756 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -59,7 +59,8 @@ option(API_Hardware.GiantGecko "option for Hardware.Gia ################################### # add options for private APIs here - +option(API_Com.SkyworksInc.NanoFramework.Devices.I2c "option for Skyworks I2C API") +option(API_Com.SkyworksInc.NanoFramework.Devices.Spi "option for Skyworks SPI API") ################################### ################################################################# @@ -465,6 +466,18 @@ ParseInteropAssemblies() ################################## # add parsing of private APIs here +# Com.SkyworksInc.NanoFramework.Devices.I2c +if(API_Com.SkyworksInc.NanoFramework.Devices.I2c) + ##### API name here (doted name) + PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.I2c") +endif() + +# Com.SkyworksInc.NanoFramework.Devices.Spi +if(API_Com.SkyworksInc.NanoFramework.Devices.Spi) + ##### API name here (doted name) + PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.Spi") +endif() + ################################## # parse the declarations to have new lines and ';' diff --git a/CMake/binutils.common.cmake b/CMake/binutils.common.cmake index b19afaf76d..93a7ff642b 100644 --- a/CMake/binutils.common.cmake +++ b/CMake/binutils.common.cmake @@ -790,7 +790,7 @@ function(nf_add_mbedtls_library) FetchContent_GetProperties(mbedtls) if(NOT mbedtls_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(mbedtls) + FetchContent_MakeAvailable(mbedtls) endif() set(MBEDTLS_AS_SUBPROJECT TRUE) diff --git a/src/CLR/CorLib/corlib_native_System_Number.cpp b/src/CLR/CorLib/corlib_native_System_Number.cpp index 34a9939a03..5ceeedba30 100644 --- a/src/CLR/CorLib/corlib_native_System_Number.cpp +++ b/src/CLR/CorLib/corlib_native_System_Number.cpp @@ -196,30 +196,45 @@ int Library_corlib_native_System_Number::GetDotIndex(char *buffer, int bufferCon void Library_corlib_native_System_Number::RoundUpNumStr(char *buffer, int *bufferContentLength) { char *c = &buffer[*bufferContentLength - 1]; + for (;;) { if (*c != '.' && *c != '-') { *c += 1; + if (*c <= '9') + { break; + } + *c = '0'; } + if (c == buffer) { if (*c == '-') { - memmove(&buffer[2], &buffer[1], *bufferContentLength + 1); - buffer[1] = '1'; + if (*bufferContentLength > 1) + { + memmove(&buffer[2], &buffer[1], *bufferContentLength + 1); + buffer[1] = '1'; + } } else { - memmove(&buffer[1], buffer, *bufferContentLength + 1); - buffer[0] = '1'; + if (*bufferContentLength > 0) + { + memmove(&buffer[1], buffer, *bufferContentLength + 1); + buffer[0] = '1'; + } } + (*bufferContentLength)++; + break; } + c--; } } @@ -232,9 +247,12 @@ int Library_corlib_native_System_Number::ReplaceNegativeSign(char *buffer, int b { int negativeSignLength = GetStrLen(negativeSign); - memmove(&buffer[negativeSignLength], &buffer[1], bufferContentLength); - memcpy(buffer, negativeSign, negativeSignLength); - ret += negativeSignLength - 1; + if (bufferContentLength > 1) + { + memmove(&buffer[negativeSignLength], &buffer[1], bufferContentLength); + memcpy(buffer, negativeSign, negativeSignLength); + ret += negativeSignLength - 1; + } } return ret; @@ -248,13 +266,22 @@ int Library_corlib_native_System_Number::ReplaceDecimalSeparator( int ret = bufferContentLength; int dotIndex = GetDotIndex(buffer, bufferContentLength); + if (dotIndex != -1) { int decimalSeparatorLength = GetStrLen(decimalSeparator); - memmove(&buffer[dotIndex + decimalSeparatorLength], &buffer[dotIndex + 1], bufferContentLength); - memcpy(&buffer[dotIndex], decimalSeparator, decimalSeparatorLength); - ret += decimalSeparatorLength - 1; + if (bufferContentLength > dotIndex + 1) + { + memmove( + &buffer[dotIndex + decimalSeparatorLength], + &buffer[dotIndex + 1], + bufferContentLength - dotIndex - 1); + + memcpy(&buffer[dotIndex], decimalSeparator, decimalSeparatorLength); + + ret += decimalSeparatorLength - 1; + } } return ret; @@ -271,10 +298,12 @@ int Library_corlib_native_System_Number::InsertGroupSeparators( int significantDigitsStartAtIndex = 0; int significantDigitCount = bufferContentLength - 1; int dotIndex = GetDotIndex(buffer, bufferContentLength); + if (dotIndex != -1) { significantDigitCount = dotIndex - 1; } + if (buffer[0] == '-') { significantDigitCount--; @@ -289,27 +318,40 @@ int Library_corlib_native_System_Number::InsertGroupSeparators( { ret = bufferContentLength + plusLength; - int srcIdx = bufferContentLength; - int tgtIdx = ret; + int sourceIdx = bufferContentLength; + int targetIdx = ret; if (dotIndex != -1) { int fractionPostfixWithDotLength = bufferContentLength - dotIndex; - memmove(&buffer[dotIndex + plusLength], &buffer[dotIndex], fractionPostfixWithDotLength); - srcIdx -= fractionPostfixWithDotLength; - tgtIdx -= fractionPostfixWithDotLength; + + if (bufferContentLength > dotIndex) + { + memmove(&buffer[dotIndex + plusLength], &buffer[dotIndex], fractionPostfixWithDotLength); + + sourceIdx -= fractionPostfixWithDotLength; + targetIdx -= fractionPostfixWithDotLength; + } } for (;;) { - if ((srcIdx - significantDigitsStartAtIndex) <= groupSize) + if ((sourceIdx - significantDigitsStartAtIndex) <= groupSize) + { break; + } + + targetIdx -= groupSize; + sourceIdx -= groupSize; - tgtIdx -= groupSize; - srcIdx -= groupSize; - memmove(&buffer[tgtIdx], &buffer[srcIdx], groupSize); - tgtIdx -= groupSepLength; - memcpy(&buffer[tgtIdx], groupSep, groupSepLength); + if (bufferContentLength > sourceIdx) + { + memmove(&buffer[targetIdx], &buffer[sourceIdx], groupSize); + + targetIdx -= groupSepLength; + + memcpy(&buffer[targetIdx], groupSep, groupSepLength); + } } } diff --git a/src/CLR/Core/GarbageCollector_Compaction.cpp b/src/CLR/Core/GarbageCollector_Compaction.cpp index b7c681de08..cd16c5aa2a 100644 --- a/src/CLR/Core/GarbageCollector_Compaction.cpp +++ b/src/CLR/Core/GarbageCollector_Compaction.cpp @@ -256,13 +256,13 @@ void CLR_RT_GarbageCollector::Heap_Compact() freeRegion->Unlink(); -#ifdef _DEBUG +#ifdef DEBUG _ASSERTE(relocCurrent->m_destination >= (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode()); _ASSERTE(relocCurrent->m_destination < (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.LastNode()); _ASSERTE(relocCurrent->m_start >= (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode()); _ASSERTE(relocCurrent->m_start < (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.LastNode()); - _ASSERTE(moveBytes <= freeRegion_Size); + _ASSERTE(moveBytes <= (move * sizeof(CLR_RT_HeapBlock))); #endif diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index dd94e0594d..a5061b978a 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -727,12 +727,13 @@ void CLR_PRF_Profiler::TrackObjectCreation(CLR_RT_HeapBlock *ptr) else if (dt == DATATYPE_SZARRAY) { CLR_RT_HeapBlock_Array *array = (CLR_RT_HeapBlock_Array *)ptr; - CLR_RT_TypeDef_Index elementIdx = array->ReflectionDataConst().m_data.m_type; PackAndWriteBits(array->ReflectionDataConst().m_data.m_type); PackAndWriteBits(array->ReflectionDataConst().m_levels); #ifdef NANOCLR_TRACE_PROFILER_MESSAGES + CLR_RT_TypeDef_Index elementIdx = array->ReflectionDataConst().m_data.m_type; + #ifdef _WIN64 CLR_Debug::Printf( "\r\n Profiler info: ! (0x0x%" PRIx64 " | %d) DT: %d [%08x] %d bytes\r\n", diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp new file mode 100644 index 0000000000..45dd0ee516 --- /dev/null +++ b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp @@ -0,0 +1,34 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_i2c_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus::NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_I2c = +{ + "Com.SkyworksInc.NanoFramework.Devices.I2c", + 0x913E3D1E, + method_lookup, + { 100, 0, 0, 2 } +}; + +// clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h new file mode 100644 index 0000000000..d0e114bab7 --- /dev/null +++ b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h @@ -0,0 +1,47 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef _COM_SKY_NF_DEV_I2C_NATIVE_H_ +#define _COM_SKY_NF_DEV_I2C_NATIVE_H_ + +#include +#include +#include +#include + +typedef enum __nfpack I2cBusSpeed +{ + I2cBusSpeed_StandardMode = 0, + I2cBusSpeed_FastMode = 1, +} I2cBusSpeed; + +typedef enum __nfpack I2cTransferStatus +{ + I2cTransferStatus_UnknownError = 0, + I2cTransferStatus_ClockStretchTimeout = 1, + I2cTransferStatus_PartialTransfer = 2, + I2cTransferStatus_SlaveAddressNotAcknowledged = 3, +} I2cTransferStatus; + +struct Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus +{ + static const int FIELD_STATIC___busSpeed = 0; + + static const int FIELD___syncLock = 1; + static const int FIELD___buffer = 2; + + NANOCLR_NATIVE_DECLARE(NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte); + + //--// +}; + +struct Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cException +{ + static const int FIELD___bytesTransferred = 5; + static const int FIELD___status = 6; + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_I2c; + +#endif //_COM_SKY_NF_DEV_I2C_NATIVE_H_ diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp new file mode 100644 index 0000000000..047e91b910 --- /dev/null +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -0,0 +1,54 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_spi_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = +{ + "Com.SkyworksInc.NanoFramework.Devices.Spi", + 0x25E3D06E, + method_lookup, + { 100, 0, 0, 10 } +}; + +// clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h new file mode 100644 index 0000000000..bcf610a248 --- /dev/null +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -0,0 +1,80 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef _COM_SKY_NF_DEV_SPI_NATIVE_H_ +#define _COM_SKY_NF_DEV_SPI_NATIVE_H_ + +#include +#include +#include +#include + +// defined src\System.Device.Spi\sys_dev_spi_native.h +// typedef enum __nfpack DataFlow +// { +// DataFlow_MsbFirst = 0, +// DataFlow_LsbFirst = 1, +// } DataFlow; + +typedef enum __nfpack SpiError +{ + SpiError_Unknown = 0, + SpiError_Timeout = 1, + SpiError_Aborted = 2, +} SpiError; + +// defined src\System.Device.Spi\sys_dev_spi_native.h +typedef enum __nfpack SpiPhasePolarityMode +{ + SpiPhasePolarityMode_Mode0 = 0, + SpiPhasePolarityMode_Mode1 = 1, + SpiPhasePolarityMode_Mode2 = 2, + SpiPhasePolarityMode_Mode3 = 3, +} SpiPhasePolarityMode; + +// defined src\System.Device.Spi\sys_dev_spi_native.h +typedef enum __nfpack SpiWireMode +{ + SpiWireMode_FullDuplex = 0, + SpiWireMode_HalfDuplex = 1, + SpiWireMode_Simplex = 2, +} SpiWireMode; + +struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration +{ + static const int FIELD___clockFrequency = 1; + static const int FIELD___databitLength = 2; + static const int FIELD___spiPhasePolarityMode = 3; + static const int FIELD___dataFlow = 4; + static const int FIELD___spiWireMode = 5; + + //--// +}; + +struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus +{ + static const int FIELD_STATIC___busConnectionSettings = 0; + + static const int FIELD___syncLock = 1; + static const int FIELD___bufferSingleOperation = 2; + + NANOCLR_NATIVE_DECLARE( + NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); + NANOCLR_NATIVE_DECLARE(NativeReportBusSettingsChanged___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); + + //--// + + static HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack); + static HRESULT ThrowError(CLR_RT_StackFrame &stack, CLR_UINT32 errorCode); +}; + +struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiException +{ + static const int FIELD___errorCode = 5; + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi; + +#endif //_COM_SKY_NF_DEV_SPI_NATIVE_H_ diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h new file mode 100644 index 0000000000..5d568902fc --- /dev/null +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE SKYWORKS SPI IMPLEMENTATION IS NO USING CPU SPI // +/////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index ab39adbdc8..3bc42da5af 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -2,6 +2,10 @@ "version": 4, "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", + "SiliconLabs/SKY_EEVB/CMakePresets.json", + "SiliconLabs/SKY_CEVB1/CMakePresets.json", + "SiliconLabs/STB_Interposer/CMakePresets.json", + "SiliconLabs/FIELD_PROG/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/.vscode/settings.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/.vscode/settings.json new file mode 100644 index 0000000000..cad7657dfa --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cmake.configureOnOpen": false +} \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json new file mode 100644 index 0000000000..940675f6da --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json @@ -0,0 +1,85 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "FIELD_PROG_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "FIELD_PROG", + "TARGET_NAME": "FIELD_PROG_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_nanoFramework.System.IO.Hashing": "ON" + } + }, + { + "name": "FIELD_PROG_Release", + "inherits": [ + "FIELD_PROG_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "FIELD_PROG_Release", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "FIELD_PROG_Debug", + "displayName": "FIELD_PROG_Debug", + "configurePreset": "FIELD_PROG_Debug" + }, + { + "inherits": "base-user", + "name": "FIELD_PROG_Release", + "displayName": "FIELD_PROG_Release", + "configurePreset": "FIELD_PROG_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/README.md b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/README.md new file mode 100644 index 0000000000..d5e436cd75 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/README.md @@ -0,0 +1,28 @@ +# Skyworks Field Programmer EVB featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8263237766/Gecko+Field+Programmer + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC <- NOT USED, ADC is disabled + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/bspconfig.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c new file mode 100644 index 0000000000..e4792d9bb0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/launch.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c new file mode 100644 index 0000000000..c31008e084 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c @@ -0,0 +1,187 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure S2 switch for input + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // check if there is a request to remain on nanoBooter + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // do not load CLR, remain in nanoBooter + } + else + { + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..75f91c7370 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c new file mode 100644 index 0000000000..d2db3a36b0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c @@ -0,0 +1,187 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + UsbStackInit(); + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..a8b2041199 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + +////////////////// +// SPI1 (USART1)// +////////////////// + +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..e9226d5dfb --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// DUT SPI on USART1 +#define GECKO_USE_SPI1 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.h.in b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..c6b9aca497 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.cpp @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..115d8a0324 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b5d0ffb355 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6e7b275464 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.h new file mode 100644 index 0000000000..c81f83afe3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +/* + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h new file mode 100644 index 0000000000..77281d59a9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json new file mode 100644 index 0000000000..1aa84f401a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json @@ -0,0 +1,85 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_CEVB1_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "SKY_CEVB1", + "TARGET_NAME": "SKY_CEVB1_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_nanoFramework.System.IO.Hashing": "ON" + } + }, + { + "name": "SKY_CEVB1_Release", + "inherits": [ + "SKY_CEVB1_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_CEVB1_Release", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_CEVB1_Debug", + "displayName": "SKY_CEVB1_Debug", + "configurePreset": "SKY_CEVB1_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_CEVB1_Release", + "displayName": "SKY_CEVB1_Release", + "configurePreset": "SKY_CEVB1_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md new file mode 100644 index 0000000000..a6a28e8c83 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md @@ -0,0 +1,30 @@ +# Skyworks CEVB Scheme #1 featuring SiLabs EFM32 Giant Gecko GG11 + +This is used for Si5575 CEVB, Si5400 CEVB, and Si5500 8x8 CEVB as of Feb 2024. + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8175353962/Si5575+CEVB+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c new file mode 100644 index 0000000000..e4792d9bb0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c new file mode 100644 index 0000000000..e0a0dcde98 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c @@ -0,0 +1,186 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure S2 switch for input + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // check if there is a request to remain on nanoBooter + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // do not load CLR, remain in nanoBooter + } + else + { + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..75f91c7370 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c new file mode 100644 index 0000000000..54ca65223c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -0,0 +1,190 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..6c5b724749 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..bdfea3503d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..a2de5db33c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on SKY_CEVB1; CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..e203cd7428 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on SKY_CEVB1; CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b5d0ffb355 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6e7b275464 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h new file mode 100644 index 0000000000..c81f83afe3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +/* + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h new file mode 100644 index 0000000000..409945557b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json new file mode 100644 index 0000000000..f82c4f1465 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -0,0 +1,103 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_EEVB_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "SKY_EEVB", + "TARGET_NAME": "SKY_EEVB_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", + "NF_CLR_NO_IL_INLINE": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_nanoFramework.System.IO.Hashing": "ON" + } + }, + { + "name": "SKY_EEVB_Watchdog_Debug", + "inherits": [ + "SKY_EEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_EEVB_Watchdog_Debug", + "NF_FEATURE_WATCHDOG": "ON" + } + }, + { + "name": "SKY_EEVB_Release", + "inherits": [ + "SKY_EEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_EEVB_Release", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_EEVB_Debug", + "displayName": "SKY_EEVB_Debug", + "configurePreset": "SKY_EEVB_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_EEVB_Watchdog_Debug", + "displayName": "SKY_EEVB_Watchdog_Debug", + "configurePreset": "SKY_EEVB_Watchdog_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_EEVB_Release", + "displayName": "SKY_EEVB_Release", + "configurePreset": "SKY_EEVB_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/README.md new file mode 100644 index 0000000000..0262029c2d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/README.md @@ -0,0 +1,28 @@ +# Skyworks EEVB featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8050344361/EEVB+Controller+Board+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c new file mode 100644 index 0000000000..e4792d9bb0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c new file mode 100644 index 0000000000..e0a0dcde98 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c @@ -0,0 +1,186 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure S2 switch for input + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // check if there is a request to remain on nanoBooter + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // do not load CLR, remain in nanoBooter + } + else + { + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..75f91c7370 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c new file mode 100644 index 0000000000..54ca65223c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c @@ -0,0 +1,190 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..5adbeff229 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PF8 +// MOSI: PF6 +// MISO: PF7 +// CS: PF9 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4, 4) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..409945557b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..32147d6ec7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.cpp @@ -0,0 +1,46 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..0aece00b26 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 TRUE +#define GECKO_USE_ADC1 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b5d0ffb355 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..38074baf86 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.h new file mode 100644 index 0000000000..654d7141ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.h @@ -0,0 +1,5 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE +#define GECKO_USE_I2C2 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..09360b8d8e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.cpp @@ -0,0 +1,33 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI1 // +////////// + +// USART1 +// SPI1_SCK: PD2 +// SPI1_MOSI: PD0 +// SPI1_MISO: PD1 +// SPI1_CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SPI2_SCK: PF8 +// SPI2_MOSI: PF6 +// SPI2_MISO: PF7 +// SPI2_CS: PF9 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.h new file mode 100644 index 0000000000..1ff4bd6324 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 FALSE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE +#define GECKO_USE_SPI3 FALSE +#define GECKO_USE_SPI4 FALSE +#define GECKO_USE_SPI5 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..aebb9d511a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,33 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PC1 +// port for I2C0_SDA is: PC0 + +// GPIO alternate pin function is 4 for both pins (see Alternate Functionality mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortC, gpioPortC, 1, 0, 4, 4) + +////////// +// I2C2 // +////////// + +// Devices available in GG11 dev kit +// Modules | Description | +// Si7021 | Relative Humidity and Temperature Sensor | +// Si7210 | Hall-Effect Sensor | + +// pin configuration for I2C2 +// port for I2C2_SCL is: GPIOI_5 +// port for I2C2_SDA is: GPIOI_4 + +// GPIO alternate pin function is 7 for both pins (see Alternate Functionality mapping table in device datasheet) +I2C_CONFIG_PINS(2, gpioPortI, gpioPortI, 5, 4, 7, 7) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..8b7431bf9d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..51613d0c77 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,34 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI0 // +////////// + +// Note: on SL_STK3701A SPI0 is available at EXP connector + +// pin configuration for SPI0 (EMC encoded "port location") +// SPI0_SCK: PE12, location 0, EXP Header Pin 8 +// SPI0_MOSI: PE10, location 0, EXP Header Pin 4 +// SPI0_MISO: PE11, location 0, EXP Header Pin 6 +// SPI0_CS: PE13, location 0, EXP Header Pin 10 + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display + +// pin configuration for SPI1 (EMC encoded "port location") +// SPI1_SCK: PC15, location 3 +// SPI1_MOSI: PA14, location 6 +// SPI1_MISO: (not used for LCD) +// SPI1_CS: PC14, location 3 + +INIT_SPI_CONFIG(1, 3, 6, 0, 3) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..6dfccbd22e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h index 2c21c90446..6a71f5dc7e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h @@ -9,3 +9,5 @@ // enable USART0 #define GECKO_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h index 0e5a564e80..8945b4cb74 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h @@ -4,4 +4,4 @@ // #define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C2 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h index 6dfccbd22e..409945557b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h @@ -3,5 +3,5 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 TRUE #define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json new file mode 100644 index 0000000000..273958d9fb --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -0,0 +1,85 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "STB_Interposer_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "STB_Interposer", + "TARGET_NAME": "STB_Interposer_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_nanoFramework.System.IO.Hashing": "ON" + } + }, + { + "name": "STB_Interposer_Release", + "inherits": [ + "STB_Interposer_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "STB_Interposer", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "STB_Interposer_Debug", + "displayName": "STB_Interposer_Debug", + "configurePreset": "STB_Interposer_Debug" + }, + { + "inherits": "base-user", + "name": "STB_Interposer_Release", + "displayName": "STB_Interposer_Release", + "configurePreset": "STB_Interposer_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md b/targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md new file mode 100644 index 0000000000..60965af68c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md @@ -0,0 +1,28 @@ +# Skyworks STB Interposer featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/NAT/pages/8204484955/Interposer+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c new file mode 100644 index 0000000000..09982097e3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 66}, + + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c new file mode 100644 index 0000000000..e0a0dcde98 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c @@ -0,0 +1,186 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure S2 switch for input + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // check if there is a request to remain on nanoBooter + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // do not load CLR, remain in nanoBooter + } + else + { + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..d17abebca3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c new file mode 100644 index 0000000000..54ca65223c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c @@ -0,0 +1,190 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..6c5b724749 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..bdfea3503d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..ade2abefdb --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..ce46252b6d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b5d0ffb355 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..38074baf86 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h new file mode 100644 index 0000000000..79c0cadd23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h new file mode 100644 index 0000000000..742991d83c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 71e5e99c18..e5ef9d328c 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -301,37 +301,46 @@ static void events_handler(sl_power_manager_em_t from, sl_power_manager_em_t to) ((to == SL_POWER_MANAGER_EM1) || (to == SL_POWER_MANAGER_EM0))) { +#if HAL_USE_ONEWIRE == TRUE // Wake the USART Tx pin back up out = GPIO_PinOutGet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN, gpioModePushPull, out); +#endif // HAL_USE_ONEWIRE +#if HAL_WP_USE_SERIAL == TRUE // Wake the USART Tx pin back up out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); +#endif // HAL_WP_USE_SERIAL + } else if ( ((to == SL_POWER_MANAGER_EM2) || (to == SL_POWER_MANAGER_EM3)) && ((from == SL_POWER_MANAGER_EM1) || (from == SL_POWER_MANAGER_EM0))) { +#if HAL_USE_ONEWIRE == TRUE // Sleep the USART Tx pin on series 2 devices to save energy out = GPIO_PinOutGet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN, gpioModeDisabled, out); +#endif // HAL_USE_ONEWIRE +#if HAL_WP_USE_SERIAL == TRUE // Sleep the USART Tx pin on series 2 devices to save energy out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); +#endif // HAL_WP_USE_SERIAL + } #endif // _SILICON_LABS_32B_SERIES_2 - // Enable next byte detect to wake from sleep if (to < SL_POWER_MANAGER_EM2) { + // Only prepare for wakeup from EM1 or less, since USART doesn't run in EM2 - // Enable next byte detection to wakeup from sleep on next byte - context_onewire.context.set_next_byte_detect(sl_iostream_onewire_handle->context, true); - - // Enable next byte detection to wakeup from sleep on next byte - context_vcom.context.set_next_byte_detect(sl_iostream_vcom_handle->context, true); + if (sl_iostream_uart_vcom_handle->stream.context != NULL) + { + sl_iostream_uart_prepare_for_sleep(sl_iostream_uart_vcom_handle); + } } } #endif // SL_CATALOG_POWER_MANAGER_PRESENT diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 8f7215bd57..54d5cf0fc3 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -117,8 +117,8 @@ sl_status_t sli_usbd_vendor_winusb_init() if (deviceState > SL_USBD_DEVICE_STATE_INIT) { - // device is already initialized, stop USB core, **ONLY** if there isn't a debugger connected - if (!DebuggerIsConnected()) + // device is already initialized, stop USB core, **ONLY** if there isn't an active debug session + if (!DebugSessionIsActive()) { sl_usbd_core_stop_device(); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h index 0e763ef420..f5d4490a24 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -19,11 +19,11 @@ typedef enum __nfpack UsbEventType #define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" /// Length of GUID Property Name -#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) +#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof(DEVICEINTERFACE_GUID_PROP_NAME) // GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) -#define DEVICE_CLASS_GUID_PROPERTY L"{00000000-0000-0000-0000-000000000000}" -#define DEVICE_CLASS_GUID_PROPERTY_LEN sizeof(DEVICE_CLASS_GUID_PROPERTY) +#define DEVICE_CLASS_GUID_PROPERTY_PLACEHOLDER L"{00000000-0000-0000-0000-000000000000}" +#define DEVICE_CLASS_GUID_PROPERTY_LEN sizeof(DEVICE_CLASS_GUID_PROPERTY_PLACEHOLDER) /* class numbers assigned by the USB stack after init */ @@ -39,10 +39,11 @@ __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req /* init functions for all vendor instances */ #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -sl_status_t sli_usbd_vendor_winusb_init(void); + sl_status_t sli_usbd_vendor_winusb_init(void); #ifdef __cplusplus } diff --git a/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c b/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c index a9f03e98e2..ada17d331a 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c @@ -6,8 +6,9 @@ #include #include -//See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html -typedef enum { +// See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html +typedef enum +{ Reset = 1, NMI = 2, HardFault = 3, @@ -20,23 +21,27 @@ typedef enum { typedef void *regarm_t; // This structure represents the stack frame saved during an interrupt handler. -struct port_extctx { - regarm_t spsr_irq; - regarm_t lr_irq; - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_usr; +struct port_extctx +{ + regarm_t spsr_irq; + regarm_t lr_irq; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_usr; }; -void NMI_Handler(void) { - while(1); +void NMI_Handler(void) +{ + while (1) + ; } -// dev note: on all the following the variables need to be declared as volatile so they don't get optimized out by the linker -// dev note: the pragma below is to ignore the warning because the variables aren't actually being used despite needing to remain there for debug +// dev note: on all the following the variables need to be declared as volatile so they don't get optimized out by the +// linker dev note: the pragma below is to ignore the warning because the variables aren't actually being used despite +// needing to remain there for debug #ifdef __GNUC__ #pragma GCC diagnostic push @@ -46,46 +51,77 @@ void NMI_Handler(void) { // hard fault handler for Cortex-M3 & M4 -void HardFault_Handler(void) { +void HardFault_Handler(void) +{ - //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + // Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info struct port_extctx ctx; - //Get thread context. Contains main registers including PC and LR - memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + // Get thread context. Contains main registers including PC and LR + memcpy(&ctx, (void *)__get_PSP(), sizeof(struct port_extctx)); (void)ctx; - //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + // Interrupt status register: Which interrupt have we encountered, e.g. HardFault? volatile FaultType faultType = (FaultType)__get_IPSR(); // these are not available in all the STM32 series - //Flags about hardfault / busfault - //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference - volatile bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false); - volatile bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false); - volatile bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false); - volatile bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false); - volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false); + // Flags about hardfault / busfault + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + // Configurable Fault Status Register + volatile uint32_t _CFSR = SCB->CFSR; + + // IACCVIOL: Instruction access violation + volatile bool isFaultInstructionAccessViolation = ((_CFSR & (1 << 0)) ? true : false); + // DACCVIOL: Data access violation + volatile bool isFaultDataAccessViolation = ((_CFSR & (1 << 1)) ? true : false); + // MUNSTKERR: Unstacking error + volatile bool isFaultUnstackingError = ((_CFSR & (1 << 3)) ? true : false); + // MSTKERR: Stacking error + volatile bool isFaultStackingError = ((_CFSR & (1 << 4)) ? true : false); + // MMARVALID: MMAR is valid + volatile bool isMarkedMemoryAddressValid = ((_CFSR & (1 << 7)) ? true : false); + // IBUSERR: Instruction bus error + volatile bool isFaultInstructionBusError = ((_CFSR & (1 << 8)) ? true : false); + // PRECISERR: Precise data bus error + volatile bool isFaultPreciseDataBusError = ((_CFSR & (1 << 9)) ? true : false); + // IMPRECISERR: Imprecise data bus error + volatile bool isFaultImpreciseDataBusError = ((_CFSR & (1 << 10)) ? true : false); + // LSPERR: Lazy state preservation error + volatile bool isFaultLazyStatePreservationError = ((_CFSR & (1 << 13)) ? true : false); + // BFARVALID: BFAR is valid + volatile bool isFaultBusFaultAddressValid = ((_CFSR & (1 << 15)) ? true : false); + // UNDEFINSTR: Undefined instruction usage fault + volatile bool isUndefinedInstructionUsageFault = ((_CFSR & (1 << 16)) ? true : false); + // INVSTATE: Invalid state usage fault + volatile bool isInvalidStateUsageFault = ((_CFSR & (1 << 17)) ? true : false); + // INVPC: Invalid PC load usage fault + volatile bool isInvalidPcLoadUsageFault = ((_CFSR & (1 << 18)) ? true : false); + // NOCP: No coprocessor usage fault + volatile bool isNoCoprocessorUsageFault = ((_CFSR & (1 << 19)) ? true : false); + // UNALIGNED: Unaligned access usage fault + volatile bool isUnalignedAccessUsageFault = ((_CFSR & (1 << 24)) ? true : false); + // DIVBYZERO: Divide by zero usage fault + volatile bool isDivideByZeroUsageFault = ((_CFSR & (1 << 25)) ? true : false); // Hard Fault Status Register - volatile unsigned long _HFSR = (*((volatile unsigned long *)(0xE000ED2C))) ; + volatile unsigned long _HFSR = (*((volatile unsigned long *)(0xE000ED2C))); // Debug Fault Status Register - volatile unsigned long _DFSR = (*((volatile unsigned long *)(0xE000ED30))) ; + volatile unsigned long _DFSR = (*((volatile unsigned long *)(0xE000ED30))); // Auxiliary Fault Status Register - volatile unsigned long _AFSR = (*((volatile unsigned long *)(0xE000ED3C))) ; + volatile unsigned long _AFSR = (*((volatile unsigned long *)(0xE000ED3C))); // Read the Fault Address Registers. These may not contain valid values. // Check BFARVALID/MMARVALID to see if they are valid values - + // MemManage Fault Address Register - volatile unsigned long _MMAR = (*((volatile unsigned long *)(0xE000ED34))) ; - - //For HardFault/BusFault this is the address that was accessed causing the error + volatile unsigned long _MMAR = (*((volatile unsigned long *)(0xE000ED34))); + + // For HardFault/BusFault this is the address that was accessed causing the error volatile uint32_t faultAddress = SCB->BFAR; - + // forces a breakpoint causing the debugger to stop // if no debugger is attached this is ignored __asm volatile("BKPT #0\n"); @@ -96,31 +132,56 @@ void HardFault_Handler(void) { void BusFault_Handler(void) __attribute__((alias("HardFault_Handler"))); -void UsageFault_Handler(void) { +void UsageFault_Handler(void) +{ - //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info - //Get thread context. Contains main registers including PC and LR + // Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + // Get thread context. Contains main registers including PC and LR struct port_extctx ctx; - memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + memcpy(&ctx, (void *)__get_PSP(), sizeof(struct port_extctx)); (void)ctx; - //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + // Interrupt status register: Which interrupt have we encountered, e.g. HardFault? FaultType faultType = (FaultType)__get_IPSR(); (void)faultType; - // these are not available in all the STM32 series - #if defined(STM32L4XX_HAL_VERSION) - - //Flags about hardfault / busfault - //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference - volatile bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false); - volatile bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false); - volatile bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false); - volatile bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false); - volatile bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false); - volatile bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false); - - #endif + // Flags about hardfault / busfault + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + // Configurable Fault Status Register + volatile uint32_t _CFSR = SCB->CFSR; + + // IACCVIOL: Instruction access violation + volatile bool isFaultInstructionAccessViolation = ((_CFSR & (1 << 0)) ? true : false); + // DACCVIOL: Data access violation + volatile bool isFaultDataAccessViolation = ((_CFSR & (1 << 1)) ? true : false); + // MUNSTKERR: Unstacking error + volatile bool isFaultUnstackingError = ((_CFSR & (1 << 3)) ? true : false); + // MSTKERR: Stacking error + volatile bool isFaultStackingError = ((_CFSR & (1 << 4)) ? true : false); + // MMARVALID: MMAR is valid + volatile bool isMarkedMemoryAddressValid = ((_CFSR & (1 << 7)) ? true : false); + // IBUSERR: Instruction bus error + volatile bool isFaultInstructionBusError = ((_CFSR & (1 << 8)) ? true : false); + // PRECISERR: Precise data bus error + volatile bool isFaultPreciseDataBusError = ((_CFSR & (1 << 9)) ? true : false); + // IMPRECISERR: Imprecise data bus error + volatile bool isFaultImpreciseDataBusError = ((_CFSR & (1 << 10)) ? true : false); + // LSPERR: Lazy state preservation error + volatile bool isFaultLazyStatePreservationError = ((_CFSR & (1 << 13)) ? true : false); + // BFARVALID: BFAR is valid + volatile bool isFaultBusFaultAddressValid = ((_CFSR & (1 << 15)) ? true : false); + // UNDEFINSTR: Undefined instruction usage fault + volatile bool isUndefinedInstructionUsageFault = ((_CFSR & (1 << 16)) ? true : false); + // INVSTATE: Invalid state usage fault + volatile bool isInvalidStateUsageFault = ((_CFSR & (1 << 17)) ? true : false); + // INVPC: Invalid PC load usage fault + volatile bool isInvalidPcLoadUsageFault = ((_CFSR & (1 << 18)) ? true : false); + // NOCP: No coprocessor usage fault + volatile bool isNoCoprocessorUsageFault = ((_CFSR & (1 << 19)) ? true : false); + // UNALIGNED: Unaligned access usage fault + volatile bool isUnalignedAccessUsageFault = ((_CFSR & (1 << 24)) ? true : false); + // DIVBYZERO: Divide by zero usage fault + volatile bool isDivideByZeroUsageFault = ((_CFSR & (1 << 25)) ? true : false); // forces a breakpoint causing the debugger to stop // if no debugger is attached this is ignored @@ -130,33 +191,59 @@ void UsageFault_Handler(void) { NVIC_SystemReset(); } -void MemManage_Handler(void) { +void MemManage_Handler(void) +{ - //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info - //Get thread context. Contains main registers including PC and LR + // Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + // Get thread context. Contains main registers including PC and LR struct port_extctx ctx; - memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + memcpy(&ctx, (void *)__get_PSP(), sizeof(struct port_extctx)); (void)ctx; - //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + // Interrupt status register: Which interrupt have we encountered, e.g. HardFault? FaultType faultType = (FaultType)__get_IPSR(); (void)faultType; - // these are not available in all the STM32 series - #if defined(STM32L4XX_HAL_VERSION) - - //For HardFault/BusFault this is the address that was accessed causing the error + // For HardFault/BusFault this is the address that was accessed causing the error volatile uint32_t faultAddress = SCB->MMFAR; - //Flags about hardfault / busfault - //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference - volatile bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false); - volatile bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false); - volatile bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false); - volatile bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false); - volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false); - - #endif + // Flags about hardfault / busfault + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + // Configurable Fault Status Register + volatile uint32_t _CFSR = SCB->CFSR; + + // IACCVIOL: Instruction access violation + volatile bool isFaultInstructionAccessViolation = ((_CFSR & (1 << 0)) ? true : false); + // DACCVIOL: Data access violation + volatile bool isFaultDataAccessViolation = ((_CFSR & (1 << 1)) ? true : false); + // MUNSTKERR: Unstacking error + volatile bool isFaultUnstackingError = ((_CFSR & (1 << 3)) ? true : false); + // MSTKERR: Stacking error + volatile bool isFaultStackingError = ((_CFSR & (1 << 4)) ? true : false); + // MMARVALID: MMAR is valid + volatile bool isMarkedMemoryAddressValid = ((_CFSR & (1 << 7)) ? true : false); + // IBUSERR: Instruction bus error + volatile bool isFaultInstructionBusError = ((_CFSR & (1 << 8)) ? true : false); + // PRECISERR: Precise data bus error + volatile bool isFaultPreciseDataBusError = ((_CFSR & (1 << 9)) ? true : false); + // IMPRECISERR: Imprecise data bus error + volatile bool isFaultImpreciseDataBusError = ((_CFSR & (1 << 10)) ? true : false); + // LSPERR: Lazy state preservation error + volatile bool isFaultLazyStatePreservationError = ((_CFSR & (1 << 13)) ? true : false); + // BFARVALID: BFAR is valid + volatile bool isFaultBusFaultAddressValid = ((_CFSR & (1 << 15)) ? true : false); + // UNDEFINSTR: Undefined instruction usage fault + volatile bool isUndefinedInstructionUsageFault = ((_CFSR & (1 << 16)) ? true : false); + // INVSTATE: Invalid state usage fault + volatile bool isInvalidStateUsageFault = ((_CFSR & (1 << 17)) ? true : false); + // INVPC: Invalid PC load usage fault + volatile bool isInvalidPcLoadUsageFault = ((_CFSR & (1 << 18)) ? true : false); + // NOCP: No coprocessor usage fault + volatile bool isNoCoprocessorUsageFault = ((_CFSR & (1 << 19)) ? true : false); + // UNALIGNED: Unaligned access usage fault + volatile bool isUnalignedAccessUsageFault = ((_CFSR & (1 << 24)) ? true : false); + // DIVBYZERO: Divide by zero usage fault + volatile bool isDivideByZeroUsageFault = ((_CFSR & (1 << 25)) ? true : false); // forces a breakpoint causing the debugger to stop // if no debugger is attached this is ignored @@ -175,9 +262,9 @@ void MemManage_Handler(void) { // Call this to cause a hard fault by accessing a nonexistent memory address @ 0xCCCCCCCC. void HardFaultTest() { - volatile uint32_t*p; + volatile uint32_t *p; uint32_t n; - p = (uint32_t*)0xCCCCCCCC; + p = (uint32_t *)0xCCCCCCCC; n = *p; (void)n; } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp new file mode 100644 index 0000000000..5518292c18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -0,0 +1,684 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_i2c_native_target.h" + +typedef Library_corlib_native_System_SpanByte SpanByte; +typedef Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cException I2cException; + +//////////////////////////////////////////// +// declaration of the the I2C PAL structs // +//////////////////////////////////////////// +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +NF_PAL_I2C I2C0_PAL; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +NF_PAL_I2C I2C1_PAL; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +NF_PAL_I2C I2C2_PAL; +#endif + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +uint8_t I2C0_DeviceCounter = 0; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +uint8_t I2C1_DeviceCounter = 0; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +uint8_t I2C2_DeviceCounter = 0; +#endif + +// these values have adjust following characterization of Skyworks EVB rev2.0 +#define I2C_FREQ_STANDARD_SKYWORKS_EVB 110000 +#define I2C_FREQ_FAST_SKYWORKS_EVB 676000 + +// estimate the time required to perform the I2C transaction +bool IsLongRunningOperation( + uint16_t writeSize, + uint16_t readSize, + float byteTime, + uint32_t &estimatedDurationMiliseconds) +{ + // add an extra byte to account for the address + estimatedDurationMiliseconds = byteTime * (writeSize + readSize + 1); + + if (estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +// ThreadX I2C Working thread +static void I2CWorkingThread_entry(uint32_t arg) +{ + NF_PAL_I2C *palI2c = (NF_PAL_I2C *)arg; + I2C_TransferSeq_TypeDef i2cTransfer; + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + i2cTransfer.flags = I2C_FLAG_WRITE_READ; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = palI2c->ReadBuffer; + i2cTransfer.buf[1].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + i2cTransfer.flags = I2C_FLAG_WRITE; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + // this is a Read only transaction + i2cTransfer.flags = I2C_FLAG_READ; + i2cTransfer.buf[0].data = palI2c->ReadBuffer; + i2cTransfer.buf[0].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + } + + // fire event for I2C transaction complete + Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); + + // terminate this thread + tx_thread_terminate(palI2c->WorkingThread); +} + +HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2c) +{ + NANOCLR_HEADER(); + + I2CSPM_Init_TypeDef i2cInit = { + NULL, + 0, + 0, + 0, + 0, +#if defined(_SILICON_LABS_32B_SERIES_0) + 0, +#elif defined(_SILICON_LABS_32B_SERIES_1) + 0, + 0, +#endif + 0, + I2C_FREQ_STANDARD_MAX, + i2cClockHLRStandard, + }; + + // config GPIO pins used by the I2C peripheral + // init the PAL struct for this I2C bus and assign the respective driver + // all this occurs if not already done + // why do we need to check if this is already done? because several I2cDevice objects can be created associated to + // the same bus just using different addresses + switch (busIndex) + { + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 0: + if (I2C0_PAL.Configuration == NULL) + { + I2C0_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C0_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C0_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C0(); + + I2C0_PAL.Configuration->port = I2C0; + palI2c = &I2C0_PAL; + + // increase device counter + I2C0_DeviceCounter++; + } + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 1: + if (I2C1_PAL.Configuration == NULL) + { + I2C1_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C1_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C1_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C1(); + + I2C1_PAL.Configuration->port = I2C1; + palI2c = &I2C1_PAL; + + // increase device counter + I2C1_DeviceCounter++; + } + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 2: + if (I2C2_PAL.Configuration == NULL) + { + I2C2_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C2_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C2_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C2(); + + I2C2_PAL.Configuration->port = I2C2; + palI2c = &I2C2_PAL; + + // increase device counter + I2C2_DeviceCounter++; + } + + break; +#endif + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Get a general low-level I2C configuration, depending on user's managed parameters + if (busSpeed == I2cBusSpeed_StandardMode) + { + palI2c->Configuration->i2cMaxFreq = I2C_FREQ_STANDARD_SKYWORKS_EVB; + palI2c->Configuration->i2cClhr = i2cClockHLRStandard; + } + else + { + palI2c->Configuration->i2cMaxFreq = I2C_FREQ_FAST_SKYWORKS_EVB; + palI2c->Configuration->i2cClhr = i2cClockHLRAsymetric; + } + + I2CSPM_Init(palI2c->Configuration); + + // compute rough estimate on the time to tx/rx a byte (in milliseconds) + if (busSpeed == I2cBusSpeed_StandardMode) + { + // 100kbit/s: this is roughly 0.10ms per byte, give or take + palI2c->ByteTime = 0.1; + } + else + { + // 400kbit/s: this is roughly 0.02ms per byte, give or take + palI2c->ByteTime = 0.02; + } + + // clear pointer to working thread + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + + NANOCLR_NOCLEANUP(); +} + +HRESULT DisposeI2c(uint8_t busIndex, NF_PAL_I2C *&palI2c) +{ + NANOCLR_HEADER(); + + // get the driver for the I2C bus + // Gecko I2C bus index is 0 based + switch (busIndex) + { + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 0: + palI2c = &I2C0_PAL; + + // free memory + platform_free(I2C0_PAL.Configuration); + + // clears configuration + I2C0_PAL.Configuration = NULL; + + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 1: + // free memory + platform_free(I2C1_PAL.Configuration); + + // clears configuration + I2C1_PAL.Configuration = NULL; + + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 2: + // free memory + platform_free(I2C2_PAL.Configuration); + + // clears configuration + I2C2_PAL.Configuration = NULL; + + break; +#endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // stop working thread, if it's running + if (palI2c->WorkingThread != NULL) + { + // delete thread + tx_thread_delete(palI2c->WorkingThread); + + // free stack memory + platform_free(palI2c->WorkingThreadStack); + + // clear pointers + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + } + + NANOCLR_NOCLEANUP(); +} + +static HRESULT ThrowOnError(CLR_RT_StackFrame &stack, I2C_TransferReturn_TypeDef transactionResult, int bytesTransfered) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index i2cExceptionTypeDef; + CLR_RT_HeapBlock *hbObj; + + CLR_RT_HeapBlock &res = stack.m_owningThread->m_currentException; + + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("I2cException", "Com.SkyworksInc.NanoFramework.Devices.I2c", i2cExceptionTypeDef); + + if ((Library_corlib_native_System_Exception::CreateInstance(res, i2cExceptionTypeDef, CLR_E_FAIL, &stack)) == S_OK) + { + // dereference the exception object in order to reach its fields + hbObj = res.Dereference(); + + // figure out what was the error and set the status field + switch (transactionResult) + { + case i2cTransferNack: + hbObj[I2cException::FIELD___status].SetInteger( + (CLR_UINT32)I2cTransferStatus_SlaveAddressNotAcknowledged); + break; + + case i2cTransferBusErr: + case i2cTransferArbLost: + case i2cTransferUsageFault: + case i2cTransferSwFault: + hbObj[I2cException::FIELD___status].SetInteger((CLR_UINT32)I2cTransferStatus_ClockStretchTimeout); + break; + + default: + hbObj[I2cException::FIELD___status].SetInteger((CLR_UINT32)I2cTransferStatus_UnknownError); + + // set the bytes transferred field + hbObj[I2cException::FIELD___bytesTransferred].SetInteger(bytesTransfered); + } + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +static HRESULT NativeTransmit(uint8_t busIndex, NF_PAL_I2C *&palI2c, CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + { + bool isLongRunningOperation = false; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + CLR_RT_HeapBlock *writeSpanByte; + CLR_RT_HeapBlock *readSpanByte; + CLR_RT_HeapBlock_Array *writeBuffer = NULL; + CLR_RT_HeapBlock_Array *readBuffer = NULL; + int readOffset = 0; + int writeOffset = 0; + I2C_TransferSeq_TypeDef i2cTransfer; + I2C_TransferReturn_TypeDef transactionResult = i2cTransferInProgress; + + // get the driver for the I2C bus + switch (busIndex) + { + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 0: + palI2c = &I2C0_PAL; + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 1: + palI2c = &I2C1_PAL; + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 2: + palI2c = &I2C2_PAL; + break; +#endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // dereference the write and read SpanByte from the arguments + writeSpanByte = stack.Arg3().Dereference(); + + if (writeSpanByte != NULL) + { + // get buffer + writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (writeBuffer != NULL) + { + // Get the write offset, only the elements defined by the span must be written, not the whole array + writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as write size, only the elements defined by the span must be written + palI2c->WriteSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + } + } + + if (writeBuffer == NULL) + { + // nothing to write, have to zero this + palI2c->WriteSize = 0; + } + + readSpanByte = stack.Arg4().Dereference(); + + if (readSpanByte != NULL) + { + // get buffer + readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (readBuffer != NULL) + { + // Get the read offset, only the elements defined by the span must be read, not the whole array + readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as read size, only the elements defined by the span must be read + palI2c->ReadSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + } + } + + if (readBuffer == NULL) + { + // nothing to read, have to zero this + palI2c->ReadSize = 0; + } + + // check if this is a long running operation + isLongRunningOperation = IsLongRunningOperation( + palI2c->WriteSize, + palI2c->ReadSize, + palI2c->ByteTime, + (uint32_t &)estimatedDurationMiliseconds); + + if (isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in + // milliseconds this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer(*writeBuffer); + CLR_RT_ProtectFromGC gcReadBuffer(*readBuffer); + } + + // this is going to be used to check for the right event in case of simultaneous I2C transaction + if (!isLongRunningOperation || stack.m_customState == 1) + { + + // get slave address from connection settings field + i2cTransfer.addr = (uint16_t)stack.Arg2().NumericByRef().s4 << 1; + + if (writeBuffer != NULL) + { + // grab the pointer to the array by starting and the offset specified in the span + palI2c->WriteBuffer = (uint8_t *)writeBuffer->GetElement(writeOffset); + } + + if (readBuffer != NULL) + { + // grab the pointer to the array by starting and the offset specified in the span + palI2c->ReadBuffer = (uint8_t *)readBuffer->GetElement(readOffset); + } + } + + if (isLongRunningOperation) + { + // this is a long running operation and hasn't started yet + // perform I2C transaction using driver's ASYNC API which is launching a thread to perform it + if (stack.m_customState == 1) + { + // spawn working thread to perform the I2C transaction + + // 1. allocate memory for I2C thread + palI2c->WorkingThreadStack = (uint32_t *)platform_malloc(I2C_THREAD_STACK_SIZE); + + if (palI2c->WorkingThreadStack == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // 2. create thread + uint16_t status = tx_thread_create( + palI2c->WorkingThread, +#if !defined(BUILD_RTM) + (CHAR *)"I2C Thread", +#else + NULL, +#endif + I2CWorkingThread_entry, + (uint32_t)palI2c, + palI2c->WorkingThreadStack, + I2C_THREAD_STACK_SIZE, + I2C_THREAD_PRIORITY, + I2C_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + else + { + // this is NOT a long running operation + // perform I2C transaction + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + i2cTransfer.flags = I2C_FLAG_WRITE_READ; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = palI2c->ReadBuffer; + i2cTransfer.buf[1].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + i2cTransfer.flags = I2C_FLAG_WRITE; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + // this is a Read only transaction + i2cTransfer.flags = I2C_FLAG_READ; + i2cTransfer.buf[0].data = palI2c->ReadBuffer; + i2cTransfer.buf[0].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + if (palI2c->WorkingThread->tx_thread_state == TX_TERMINATED) + { + // I2C working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_I2cMaster, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + if (eventResult || !isLongRunningOperation) + { + // event occurred + // OR this is NOT a long running operation + + if (isLongRunningOperation) + { + // get transaction result from I2C struct + transactionResult = palI2c->TransactionResult; + + // delete thread + tx_thread_delete(palI2c->WorkingThread); + + // free stack memory + platform_free(palI2c->WorkingThreadStack); + + // clear pointers + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + } + + // get the result from the working thread execution + if (transactionResult != i2cTransferDone) + { + + NANOCLR_CHECK_HRESULT(ThrowOnError(stack, transactionResult, palI2c->WriteSize + palI2c->ReadSize)); + } + else + { + // successful transaction + // set the result field + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus:: + NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t busIndex; + I2cBusSpeed busSpeed; + NF_PAL_I2C *palI2c = NULL; + + CLR_IDX assemblyIdx; + CLR_RT_Assembly *thisAssembly = NULL; + CLR_RT_HeapBlock_Array *busSpeedCollection = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + busIndex = (uint8_t)stack.Arg1().NumericByRef().s4; + + // get ref to SpiBaseConfiguration from static _busConnectionSettings array... + // need to access it through the assembly + assemblyIdx = pThis->ObjectCls().Assembly(); + thisAssembly = g_CLR_RT_TypeSystem.m_assemblies[assemblyIdx - 1]; + busSpeedCollection = thisAssembly->GetStaticField(FIELD_STATIC___busSpeed)->DereferenceArray(); + // ...access it by index + busSpeed = (I2cBusSpeed) * ((I2cBusSpeed *)busSpeedCollection->GetElement(busIndex)); + + // init I2C bus + NANOCLR_CHECK_HRESULT(InitI2c(busIndex, busSpeed, palI2c)); + + // perform transfer + // dereference the write and read SpanByte from the arguments + NANOCLR_CHECK_HRESULT(NativeTransmit(busIndex, palI2c, stack)); + + // dispose I2C bus + NANOCLR_CHECK_HRESULT(DisposeI2c(busIndex, palI2c)); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h new file mode 100644 index 0000000000..22e67c93ac --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h @@ -0,0 +1,88 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef COM_SKY_NF_DEV_I2C_NATIVE_TARGET_H +#define COM_SKY_NF_DEV_I2C_NATIVE_TARGET_H + +#include +#include + +#include +#include +#include +#include + +// receiver thread +#define I2C_THREAD_STACK_SIZE 256 +#define I2C_THREAD_PRIORITY 5 + +// set missing defines +#ifndef GECKO_USE_I2C0 +#define GECKO_USE_I2C0 FALSE +#endif +#ifndef GECKO_USE_I2C1 +#define GECKO_USE_I2C1 FALSE +#endif +#ifndef GECKO_USE_I2C2 +#define GECKO_USE_I2C2 FALSE +#endif + +// struct representing the I2C +typedef struct NF_PAL_I2C +{ + I2CSPM_Init_TypeDef *Configuration; + TX_THREAD *WorkingThread; + uint32_t *WorkingThreadStack; + I2C_TransferReturn_TypeDef TransactionResult; + uint16_t Address; + float ByteTime; + + uint8_t *WriteBuffer; + uint8_t WriteSize; + + uint8_t *ReadBuffer; + uint8_t ReadSize; +} NF_PAL_I2C; + +//////////////////////////////////////////// +// declaration of the the I2C PAL structs // +//////////////////////////////////////////// +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +extern NF_PAL_I2C I2C0_PAL; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +extern NF_PAL_I2C I2C1_PAL; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +extern NF_PAL_I2C I2C2_PAL; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + +// the following macro defines a function that configures the GPIO pins for a Gecko I2C peripheral +// it gets called in the System_Device_I2c_I2cDevice::NativeInit function +// this is required because the I2C peripherals can use multiple GPIO configuration combinations +#define I2C_CONFIG_PINS(num, gpio_port_scl, gpio_port_sda, scl_pin, sda_pin, scl_port_location, sda_port_location) \ + void ConfigPins_I2C##num() \ + { \ + I2C##num##_PAL.Configuration->sclPort = gpio_port_scl; \ + I2C##num##_PAL.Configuration->sdaPort = gpio_port_sda; \ + I2C##num##_PAL.Configuration->sclPin = scl_pin; \ + I2C##num##_PAL.Configuration->sdaPin = sda_pin; \ + I2C##num##_PAL.Configuration->portLocationScl = scl_port_location; \ + I2C##num##_PAL.Configuration->portLocationSda = sda_port_location; \ + } + +#else +#error \ + "Only _SILICON_LABS_32B_SERIES_1 is supported at this time. To add support for other series declaration above has to be updated" +#endif + +////////////////////////////////////////////////////////////////////////////////////////////// +// when an I2C is defined the declarations below will have the real function/configuration // +// in the target folder @ target_windows_devices_i2c_config.cpp // +////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_I2C0(); +void ConfigPins_I2C1(); +void ConfigPins_I2C2(); + +#endif // COM_SKY_NF_DEV_I2C_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c new file mode 100644 index 0000000000..65a575de4d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c @@ -0,0 +1,158 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include +#include "em_cmu.h" +#include "em_gpio.h" +#include "sl_assert.h" +#include "sl_i2cspm.h" +#include "sl_udelay.h" + +#include + +/* transfer timeout (how many polls) */ +#ifndef I2CSPM_TRANSFER_TIMEOUT +#define I2CSPM_TRANSFER_TIMEOUT 300 +#endif + +/* SCL hold time (in initialization function) in microseconds */ +#ifndef SL_I2CSPM_SCL_HOLD_TIME_US +#define SL_I2CSPM_SCL_HOLD_TIME_US 100 +#endif + +/******************************************************************************* + * Initalize I2C peripheral + ******************************************************************************/ +void I2CSPM_Init(I2CSPM_Init_TypeDef *init) +{ + int i; + CMU_Clock_TypeDef i2cClock; + I2C_Init_TypeDef i2cInit; + + EFM_ASSERT(init != NULL); + +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + + /* Select I2C peripheral clock */ + if (false) + { +#if defined(I2C0) + } + else if (init->port == I2C0) + { + i2cClock = cmuClock_I2C0; +#endif +#if defined(I2C1) + } + else if (init->port == I2C1) + { + i2cClock = cmuClock_I2C1; +#endif +#if defined(I2C2) + } + else if (init->port == I2C2) + { + i2cClock = cmuClock_I2C2; +#endif + } + else + { + /* I2C clock is not defined */ + EFM_ASSERT(false); + return; + } + CMU_ClockEnable(i2cClock, true); + + /* Output value must be set to 1 to not drive lines low. Set + SCL first, to ensure it is high before changing SDA. */ + GPIO_PinModeSet(init->sclPort, init->sclPin, gpioModeWiredAndPullUp, 1); + GPIO_PinModeSet(init->sdaPort, init->sdaPin, gpioModeWiredAndPullUp, 1); + + /* In some situations, after a reset during an I2C transfer, the slave + device may be left in an unknown state. Send 9 clock pulses to + set slave in a defined state. */ + for (i = 0; i < 9; i++) + { + GPIO_PinOutClear(init->sclPort, init->sclPin); + sl_udelay_wait(SL_I2CSPM_SCL_HOLD_TIME_US); + GPIO_PinOutSet(init->sclPort, init->sclPin); + sl_udelay_wait(SL_I2CSPM_SCL_HOLD_TIME_US); + } + + /* Enable pins and set location */ +#if defined(_I2C_ROUTEPEN_MASK) + init->port->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN; + init->port->ROUTELOC0 = + (uint32_t)((init->portLocationSda << _I2C_ROUTELOC0_SDALOC_SHIFT) | (init->portLocationScl << _I2C_ROUTELOC0_SCLLOC_SHIFT)); +#elif defined(_I2C_ROUTE_MASK) + init->port->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (init->portLocation << _I2C_ROUTE_LOCATION_SHIFT); +#else +#if defined(I2C0) + if (init->port == I2C0) + { + GPIO->I2CROUTE[0].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[0].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[0].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#if defined(I2C1) + if (init->port == I2C1) + { + GPIO->I2CROUTE[1].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[1].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[1].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#if defined(I2C2) + if (init->port == I2C2) + { + GPIO->I2CROUTE[2].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[2].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[2].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#endif + + /* Set emlib init parameters */ + i2cInit.enable = true; + i2cInit.master = true; /* master mode only */ + i2cInit.freq = init->i2cMaxFreq; + i2cInit.refFreq = init->i2cRefFreq; + i2cInit.clhr = init->i2cClhr; + + I2C_Init(init->port, &i2cInit); +} + +/******************************************************************************* + * Perform I2C transfer + ******************************************************************************/ +I2C_TransferReturn_TypeDef I2CSPM_Transfer(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq) +{ + I2C_TransferReturn_TypeDef ret; + uint32_t timeout = I2CSPM_TRANSFER_TIMEOUT; + + // Do a polled transfer + ret = I2C_TransferInit(i2c, seq); + + while (ret == i2cTransferInProgress && timeout--) + { + + ret = I2C_Transfer(i2c); + + // allow other tasks to run + tx_thread_sleep(10); + } + + return ret; +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h new file mode 100644 index 0000000000..3c1ec28f52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// using this to "map" the include file with the standard name +#include "com_sky_nf_dev_i2c_native_target.h" diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp new file mode 100644 index 0000000000..cfc49d3039 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -0,0 +1,715 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_spi_native_target.h" + +extern NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex); +extern void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred); +extern bool CPU_SPI_Initialize_Extended( + uint8_t busIndex, + const SPI_DEVICE_CONFIGURATION &busConfiguration, + bool reconfigure); + +typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus Devices_Spi_SpiBus; +typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration + SpiBaseConfiguration; +typedef Library_corlib_native_System_SpanByte SpanByte; +typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiException SpiException; + +static HRESULT SPI_nWrite_nRead( + NF_PAL_SPI *palSpi, + SPI_DEVICE_CONFIGURATION &sdev, + SPI_WRITE_READ_SETTINGS &wrc, + uint8_t *writeBuffer, + int32_t writeSize, + uint8_t *readBuffer, + int32_t readSize); + +// Saved config for each available SPI bus +SPI_DEVICE_CONFIGURATION SpiConfigs[NUM_SPI_BUSES]; + +// flags for bus config changes pending +bool BusConfigChangesPending[NUM_SPI_BUSES]; + +void Com_Sky_Spi_Callback(int busIndex) +{ + (void)busIndex; + + // fire event for SPI transaction complete + Events_Set(SYSTEM_EVENT_FLAG_SPI_MASTER); +} + +void ConfigureAndInitSpiBus( + int8_t busIndex, + SPI_DEVICE_CONFIGURATION *&spiDeviceConfig, + const CLR_RT_HeapBlock *baseConfig) +{ + NF_PAL_SPI *palSpi = NULL; + + // CS is always active low + spiDeviceConfig->ChipSelectActiveState = false; + // CS is controled by the Gecko SDK driver + spiDeviceConfig->DeviceChipSelect = -1; + // always bus master + spiDeviceConfig->BusMode = SpiBusMode_master; + + // SPI bus index is 1 based, but the array is 0 based + spiDeviceConfig->Spi_Bus = busIndex + 1; + + // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode + // which is stored at _spiPhasePolarityMode + spiDeviceConfig->Spi_Mode = + (SpiMode)baseConfig[SpiBaseConfiguration::FIELD___spiPhasePolarityMode].NumericByRefConst().s4; + spiDeviceConfig->DataOrder16 = + (DataBitOrder)baseConfig[SpiBaseConfiguration::FIELD___dataFlow].NumericByRefConst().s4; + spiDeviceConfig->Clock_RateHz = baseConfig[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRefConst().s4; + spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; + // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode + // which is stored at _spiWireMode field + spiDeviceConfig->BusConfiguration = + (SpiBusConfiguration)baseConfig[SpiBaseConfiguration::FIELD___spiWireMode].NumericByRefConst().s4; + spiDeviceConfig->DataIs16bits = + baseConfig[SpiBaseConfiguration::FIELD___databitLength].NumericByRefConst().s4 == 16 ? true : false; + + // get PAL SPI + palSpi = GetNfPalfromBusIndex(busIndex); + + // store this here too + palSpi->BufferIs16bits = spiDeviceConfig->DataIs16bits; + + CPU_SPI_Initialize_Extended(busIndex, *spiDeviceConfig, true); + + // lower changes pending flag + BusConfigChangesPending[busIndex] = false; +} + +// duplicated from src\System.Device.Spi\sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp +// estimate the time required to perform the SPI transaction +// TODO doesn't take into account of full duplex or sequential ( assumes sequential at the moment ) +bool System_Device_IsLongRunningOperation( + uint32_t writeSize, + uint32_t readSize, + bool fullDuplex, + bool bufferIs16bits, + float byteTime, + uint32_t &estimatedDurationMiliseconds) +{ + if (bufferIs16bits) + { + // double the buffers size + writeSize = 2 * writeSize; + readSize = 2 * readSize; + } + + if (fullDuplex) + { + estimatedDurationMiliseconds = byteTime * MAX(writeSize, readSize); + } + else + { + estimatedDurationMiliseconds = byteTime * (writeSize + readSize); + } + + if (estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::ExecuteTransfer( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock *baseConfig = NULL; + CLR_RT_HeapBlock_Array *writeBuffer; + CLR_RT_HeapBlock_Array *readBuffer; + CLR_RT_HeapBlock *writeSpanByte; + CLR_RT_HeapBlock *readSpanByte; + uint8_t *writeData = NULL; + uint8_t *readData = NULL; + int16_t writeSize = 0; + int16_t readSize = 0; + int16_t readOffset = 0; + int16_t writeOffset = 0; + bool fullDuplex; + int32_t operationResult; + + bool isLongRunningOperation; + uint32_t estimatedDurationMiliseconds; + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + int8_t busIndex; + SPI_WRITE_READ_SETTINGS rws; + NF_PAL_SPI *palSpi = NULL; + SPI_DEVICE_CONFIGURATION *spiDeviceConfig = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + busIndex = (int8_t)stack.Arg1().NumericByRef().s4; + + // SPI bus index is 1 based, but the array is 0 based + busIndex--; + + spiDeviceConfig = &SpiConfigs[busIndex]; + + if (stack.m_customState == 0) + { + // check if this SPI has been initialized + palSpi = GetNfPalfromBusIndex(busIndex); + + if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex]) + { + // SPI bus not initialized or config changes pending + + // compose SPI_DEVICE_CONFIGURATION + // get SpiBaseConfiguration from argument + baseConfig = stack.Arg5().Dereference(); + + ConfigureAndInitSpiBus(busIndex, spiDeviceConfig, baseConfig); + } + + // dereference the write and read SpanByte from the arguments + writeSpanByte = stack.Arg2().Dereference(); + + if (writeSpanByte != NULL) + { + // get buffer + writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (writeBuffer != NULL) + { + // Get the write offset, only the elements defined by the span must be written, not the whole + // array + writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as write size, only the elements defined by the span must be written + writeSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + writeData = (unsigned char *)writeBuffer->GetElement(writeOffset); + } + } + + if (writeData == NULL) + { + // nothing to write, have to zero this + writeSize = 0; + } + + readSpanByte = stack.Arg3().Dereference(); + + if (readSpanByte != NULL) + { + // get buffer + readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (readBuffer != NULL) + { + // Get the read offset, only the elements defined by the span must be read, not the whole array + readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as read size, only the elements defined by the span must be read + readSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + readData = (unsigned char *)readBuffer->GetElement(readOffset); + } + } + + if (readData == NULL) + { + // nothing to read, have to zero this + readSize = 0; + } + + // assuming full duplex all the time + fullDuplex = true; + + // Set up read/write settings for SPI_Write_Read call + rws = {fullDuplex, 0, palSpi->BufferIs16bits, 0, palSpi->ChipSelect, false}; + + // Check to see if we should run async so as not to hold up other tasks + isLongRunningOperation = System_Device_IsLongRunningOperation( + writeSize, + readSize, + fullDuplex, + palSpi->BufferIs16bits, + spiDeviceConfig->ByteTime, + (uint32_t &)estimatedDurationMiliseconds); + + if (isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in + // milliseconds this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + + // Use twice the estimated Duration as timeout + estimatedDurationMiliseconds *= 2; + + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + // if m_customState == 0 then push timeout on to eval stack[0] then move to m_customState = 1 + // Return current timeout value + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // protect the buffers from GC so DMA can find them where they are supposed to be + if (writeData != NULL) + { + CLR_RT_ProtectFromGC gcWriteBuffer(*writeBuffer); + } + if (readData != NULL) + { + CLR_RT_ProtectFromGC gcReadBuffer(*readBuffer); + } + + // Set callback for async calls to nano spi + rws.callback = Com_Sky_Spi_Callback; + } + + // Start SPI transfer + // We can ask for async transfer by setting callback but it depends if underlying supports it + // return of CLR_E_BUSY means async started + operationResult = SPI_nWrite_nRead( + palSpi, + SpiConfigs[busIndex - 1], + rws, + (uint8_t *)writeData, + (int32_t)writeSize, + (uint8_t *)readData, + (int32_t)readSize); + + // Async transfer started, go to custom 2 state (wait completion) + if (operationResult == CLR_E_BUSY) + { + stack.m_customState = 2; + } + else if (operationResult != S_OK) + { + // Something went wrong with SPI transfer + NANOCLR_CHECK_HRESULT(ThrowError(stack, operationResult)); + } + } + + // Waiting for Async operation to complete + if (stack.m_customState == 2) + { + // Get timeout from eval stack we set up + stack.SetupTimeoutFromTicks(hbTimeout, timeout); + + while (eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Spi transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_SpiMaster, eventResult)); + + if (!eventResult) + { + // Timeout + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // null pointers and vars + pThis = NULL; + } + + NANOCLR_NOCLEANUP(); +} + +static HRESULT SPI_nWrite_nRead( + NF_PAL_SPI *palSpi, + SPI_DEVICE_CONFIGURATION &sdev, + SPI_WRITE_READ_SETTINGS &wrc, + uint8_t *writeBuffer, + int32_t writeSize, + uint8_t *readBuffer, + int32_t readSize) +{ + NANOCLR_HEADER(); + + bool busConfigIsHalfDuplex; + Ecode_t transferResult; + + // If callback then use async operation + bool sync = (wrc.callback == 0); + + // Save width of transfer + palSpi->BufferIs16bits = wrc.Bits16ReadWrite; + + // Callback sync / async + palSpi->Callback = wrc.callback; + + if (writeBuffer != NULL) + { + palSpi->WriteSize = writeSize; + } + + if (readBuffer != NULL) + { + palSpi->ReadSize = readSize; + } + + // === Setup the operation and init buffers === + palSpi->BusIndex = sdev.Spi_Bus; + + // adjust the bus index to match the PAL struct + NF_SpiDriver_SetFramelength(palSpi->Handle, wrc.Bits16ReadWrite ? 16 : 8); + + // set bus config flag + busConfigIsHalfDuplex = (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex); + + if (writeBuffer != NULL) + { + // set the pointer to the write buffer as BYTE + palSpi->WriteBuffer = (uint8_t *)writeBuffer; + } + + if (readBuffer != NULL) + { + // set DMA read buffer + if (palSpi->ReadSize > 0) + { + palSpi->ReadBuffer = (uint8_t *)readBuffer; + } + } + + if (sync) + { + // Sync operation + // perform SPI operation using driver's SYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (wrc.fullDuplex) + { + // Full duplex + // Uses the largest buffer size as transfer size + transferResult = NF_SpiDriver_MTransferB( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->ReadBuffer, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize); + } + else + { + // send operation + // TODO + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; + // } + transferResult = NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + + // bail out if the transmit operation failed + if (transferResult != ECODE_EMDRV_SPIDRV_OK) + { + NANOCLR_SET_AND_LEAVE(transferResult); + } + + // receive operation + // TODO + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + transferResult = NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // receive + // TODO + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + transferResult = NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + } + else + { + // send + // TODO + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; + } + transferResult = NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + } + } + + NANOCLR_SET_AND_LEAVE(transferResult); + } + else + { + // Start an Asyncronous SPI transfer + // perform SPI operation using driver's ASYNC API + // Completed on calling SPI Callback + + // this is a Async operation + // perform SPI operation using driver's ASYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (wrc.fullDuplex) + { + // Full duplex + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // Uses the largest buffer size as transfer size + NF_SpiDriver_MTransfer( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->ReadBuffer, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + SpiTransferCompleteCallback); + } + else + { + // flag that an Rx is required after the Tx operation completes + palSpi->SequentialTxRx = true; + + // start send operation + if (busConfigIsHalfDuplex) + { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; + } + + // receive operation will be started in the callback after the above completes + NF_SpiDriver_MTransmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start receive + NF_SpiDriver_MReceive( + palSpi->Handle, + palSpi->ReadBuffer, + palSpi->ReadSize, + SpiTransferCompleteCallback); + } + else + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start send + NF_SpiDriver_MTransmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); + } + } + + // Inform caller async operation started + NANOCLR_SET_AND_LEAVE(CLR_E_BUSY); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(ExecuteTransfer(stack)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeReportBusSettingsChanged___VOID__I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + int8_t busIndex; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // SPI bus index is 1 based, but the array is 0 based + busIndex = (int8_t)stack.Arg1().NumericByRef().s4 - 1; + + BusConfigChangesPending[busIndex] = true; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_SPI *palSpi = NULL; + int8_t busIndex; + uint32_t clockDivValue; + uint32_t refFreq; + uint32_t realClk; + CLR_RT_HeapBlock *baseConfig = NULL; + SPI_DEVICE_CONFIGURATION *spiDeviceConfig = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + // Gecko SPI bus index is 0 based + busIndex = (int8_t)stack.Arg1().NumericByRef().s4 - 1; + + spiDeviceConfig = &SpiConfigs[busIndex]; + + // get the PAL struct for the SPI bus + switch (busIndex) + { +#if GECKO_USE_SPI0 == TRUE + case 0: + palSpi = &SPI0_PAL; + + break; +#endif + +#if GECKO_USE_SPI1 == TRUE + case 1: + palSpi = &SPI1_PAL; + + break; +#endif + +#if GECKO_USE_SPI2 == TRUE + case 2: + palSpi = &SPI2_PAL; + + break; +#endif + +#if GECKO_USE_SPI3 == TRUE + case 3: + palSpi = &SPI3_PAL; + + break; +#endif + +#if GECKO_USE_SPI4 == TRUE + case 4: + palSpi = &SPI4_PAL; + break; +#endif + +#if GECKO_USE_SPI5 == TRUE + case 5: + palSpi = &SPI5_PAL; + + break; +#endif + + default: + // the requested SPI bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex]) + { + // the configuration has not been set yet, or there are pending changes + // compose SPI_DEVICE_CONFIGURATION + // get SpiBaseConfiguration from argument + baseConfig = stack.Arg2().Dereference(); + + ConfigureAndInitSpiBus(busIndex, spiDeviceConfig, baseConfig); + } + + // The divider field of the USART->CLKDIV register is of the following form: + // xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider + // The driver it's only setting the integral part of the divider, so we just need to + // rotate the value 5 + 3 bits to the right to get the actual divider value + + clockDivValue = palSpi->Handle->peripheral.usartPort->CLKDIV >> 8; +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (palSpi->Handle->peripheral.usartPort == USART2) + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } + else + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + + realClk = (refFreq - 1) / (2 * clockDivValue); + + stack.SetResult_I4(realClk); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::ThrowError( + CLR_RT_StackFrame &stack, + CLR_UINT32 errorCode) +{ + NANOCLR_HEADER(); + + SpiError spiErrorCode; + + CLR_RT_HeapBlock &res = stack.m_owningThread->m_currentException; + + if ((Library_corlib_native_System_Exception::CreateInstance( + res, + g_CLR_RT_WellKnownTypes.m_SocketException, + CLR_E_FAIL, + &stack)) == S_OK) + { + // Set the error code + if (errorCode == ECODE_EMDRV_SPIDRV_TIMEOUT) + { + spiErrorCode = SpiError_Timeout; + } + else if (errorCode == ECODE_EMDRV_SPIDRV_ABORTED) + { + spiErrorCode = SpiError_Aborted; + } + else + { + spiErrorCode = SpiError_Unknown; + } + + res.Dereference()[SpiException::FIELD___errorCode].SetInteger((CLR_UINT32)spiErrorCode); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h new file mode 100644 index 0000000000..bb2190fc6b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h @@ -0,0 +1,51 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef COM_SKY_NF_DEV_SPI_NATIVE_TARGET_H +#define COM_SKY_NF_DEV_SPI_NATIVE_TARGET_H + +#include +#include +#include + +#include +#include +#include <../System.Device.Spi/nf_gecko_spi_driver.h> +#include <../System.Device.Spi/sys_dev_spi_native_target.h> + +// all PAL declarations are coming from CPU SPI + +/////////////////////////////////////////////////// +// for Skyworks SPI CS is controlled by SPI driver +#define SPI_CS_CONTROL spidrvCsControlAuto +/////////////////////////////////////////////////// + +#if defined(_USART_ROUTELOC0_MASK) + +//////////////////////////////////////////////////////// +// INIT_SPI_CONFIG from System.Device.Spi redefined here +#if defined(INIT_SPI_CONFIG) +#undef INIT_SPI_CONFIG +#endif +//////////////////////////////////////////////////////// + +// the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral +// it gets called in the System_Device_SPi_SPiDevice::NativeInit function +// this is required because the SPI peripherals can use multiple GPIO configuration combinations +#define INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) \ + void InitSpiConfig##num(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex) \ + { \ + initSpiData.port = USART##num; \ + initSpiData.portLocationTx = mosi_port_location; \ + initSpiData.portLocationClk = sck_port_location; \ + initSpiData.portLocationCs = cs_port_location; \ + if (!isHalfDuplex) \ + { \ + initSpiData.portLocationRx = miso_port_location; \ + } \ + } + +#else +#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#endif + +#endif // SYS_DEV_SPI_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h new file mode 100644 index 0000000000..72756c9502 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// using this to "map" the include file with the standard name +#include "com_sky_nf_dev_spi_native_target.h" \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h new file mode 100644 index 0000000000..cc790a9b24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +//////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE // +//////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index f8e45eb333..76482f3d71 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -12,7 +12,7 @@ #include #include -#include +#include "nf_gecko_spi_driver.h" // set missing defines #if defined(USART0) @@ -117,6 +117,8 @@ extern NF_PAL_SPI SPI5_PAL; #if defined(_USART_ROUTELOC0_MASK) +#if !defined(INIT_SPI_CONFIG) + // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations @@ -132,6 +134,8 @@ extern NF_PAL_SPI SPI5_PAL; } \ } +#endif // INIT_SPI_CONFIG + #else #error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 7344734546..336ebc1007 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -188,8 +188,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ // cancel the async operation... sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - // ... return exception - NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + // clear RX counter + UsbStream_PAL.RxBytesReceived = 0; } } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index 5f6a5e0a37..bd0f8b73c7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -26,6 +26,7 @@ typedef Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost OneWireH extern "C" void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate); extern sl_iostream_t *sl_iostream_onewire_handle; +extern sl_iostream_uart_t *sl_iostream_uart_onewire_handle; // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; @@ -33,8 +34,7 @@ static oneWireState DriverState = ONEWIRE_UNINIT; void oneWireStop() { // stop UART - // TODO - // uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); + sl_iostream_uart_deinit(sl_iostream_uart_onewire_handle); // driver is stopped DriverState = ONEWIRE_STOP; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h index 56f110502a..46c79b58c5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -10,6 +10,8 @@ #include #include +#include + #include // set missing defines diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c index 9043c3db0f..4b2cfd6269 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c @@ -6,5 +6,41 @@ #include #include +#include +#include + +// need to declare these as extern instead of including the header files +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + // required for Azure RTOS TX_INTERRUPT_SAVE_AREA implementation at platform level unsigned int interrupt_save; + +// common code used to start USB stack and various components +void UsbStackInit() +{ + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all other threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} diff --git a/targets/ESP32/CMakeLists.txt b/targets/ESP32/CMakeLists.txt index 4e625c3f81..715ee4258e 100644 --- a/targets/ESP32/CMakeLists.txt +++ b/targets/ESP32/CMakeLists.txt @@ -94,7 +94,7 @@ endif() FetchContent_GetProperties(esp32_idf) if(NOT esp32_idf_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(esp32_idf) + FetchContent_MakeAvailable(esp32_idf) endif() # add IDF CMake dir to modules path diff --git a/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp b/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp index 7bcb6aabfb..2b7192c1e4 100644 --- a/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp +++ b/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp @@ -36,7 +36,7 @@ uint8_t WP_TransmitMessage(WP_Message *message) WireProtocolTransmitCallback(&data.front(), data.size()); } - return data.size(); + return true; } void WP_CheckAvailableIncomingData()