From 98c265c531627d62cd56de518ca25aa5e120228f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 1 Jun 2022 16:27:39 +0100 Subject: [PATCH 001/572] Add presets for Silabs EFM32GG11 --- CMakePresets.json | 36 ++++++++++++++++++++++++++++++++++ CMakeUserPresets.TEMPLATE.json | 22 ++++++++++++++++++++- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/CMakePresets.json b/CMakePresets.json index 385630a7cd..f89834d757 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -272,6 +272,42 @@ "API_nanoFramework.Graphics": "OFF" } }, + { + "name": "EFM32GG11_preset", + "inherits": [ + "general-preset", + "arm-gcc-cortex-preset" + ], + "hidden": true, + "cacheVariables": { + "RTOS": "AzureRTOS", + "TARGET_SERIES": "SILABS_GG_S1", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "SWO_OUTPUT": "OFF", + "NF_BUILD_RTM": "OFF", + "API_System.Math": "OFF", + "API_Hardware.Stm32": "OFF", + "API_System.Device.Gpio": "ON", + "API_System.Device.Spi": "OFF", + "API_System.Device.I2c": "OFF", + "API_System.Device.Pwm": "OFF", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "OFF", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "OFF", + "API_nanoFramework.System.Collections": "OFF", + "API_nanoFramework.System.Text": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF" + } + }, { "name": "ESP32_PSRAM_REV0_preset", "inherits": [ diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 687fcd8921..a70730c3e6 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -136,6 +136,21 @@ "NF_INTEROP_ASSEMBLIES": null } }, + { + "name": "EFM32GG11", + "inherits": [ + "user-local-tools", + "user-prefs", + "EFM32GG11_preset" + ], + "cacheVariables": { + "TARGET_BOARD": { + "type": "STRING", + "value": "${presetName}" + }, + "NF_INTEROP_ASSEMBLIES": null + } + }, { "name": "ESP32_PSRAM_REV0", "inherits": [ @@ -621,6 +636,11 @@ "displayName": "ST_B_L475E_IOT01A", "configurePreset": "ST_B_L475E_IOT01A" }, + { + "name": "EFM32GG11", + "displayName": "EFM32GG11", + "configurePreset": "EFM32GG11" + }, { "name": "ESP32_PSRAM_REV0", "displayName": "ESP32_PSRAM_REV0", @@ -812,4 +832,4 @@ "configurePreset": "TI_CC1352P1_LAUNCHXL" } ] -} +} \ No newline at end of file From d4ee8bfde241585300e0e6b8c5aff98f8beda153 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 1 Jun 2022 18:46:23 +0100 Subject: [PATCH 002/572] Initial work on adding Gecko SDK and EFM32GG11 target - Add CMakes for the new SDK. - Add config files for the new vendor. - Add new target. - Update existing CMakes to accommodate new vendor and SDK. --- .../AzureRTOS_EFM32GG1_GCC_options.cmake | 69 +++ CMake/Modules/Gecko_SDK.cmake | 87 +++ CMake/binutils.AzureRTOS.cmake | 5 - CMakePresets.json | 4 +- CMakeUserPresets.TEMPLATE.json | 2 +- targets/AzureRTOS/CMakeLists.txt | 17 + targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 90 ++++ .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 36 ++ .../SL_STK3701A/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 124 +++++ .../SL_STK3701A/common/Device_BlockStorage.c | 124 +++++ .../SiliconLabs/SL_STK3701A/launch.json | 115 ++++ .../SL_STK3701A/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 229 ++++++++ .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 147 ++++++ .../SL_STK3701A/nanoBooter/target_board.h.in | 18 + .../SL_STK3701A/nanoCLR/CMakeLists.txt | 11 + .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 229 ++++++++ .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 132 +++++ .../SL_STK3701A/nanoCLR/nanoHAL.cpp | 8 + .../SL_STK3701A/nanoCLR/target_board.h.in | 18 + .../SL_STK3701A/target_BlockStorage.c | 19 + .../SL_STK3701A/target_BlockStorage.h | 12 + .../SiliconLabs/SL_STK3701A/target_common.c | 30 ++ .../SL_STK3701A/target_common.h.in | 45 ++ .../SL_STK3701A/target_stdio_config.c | 15 + .../SL_STK3701A/target_stdio_config.h | 11 + .../SiliconLabs/SL_STK3701A/target_tx_user.h | 206 ++++++++ .../SiliconLabs/_common/CMakeLists.txt | 0 .../SiliconLabs/_include/CMakeLists.txt | 10 + .../SiliconLabs/_include/platformHAL.h | 11 + .../SiliconLabs/_include/targetHAL_Time.h | 13 + .../SiliconLabs/_include/targetPAL.h | 9 + .../SiliconLabs/_nanoBooter/CMakeLists.txt | 9 + .../WireProtocol_MonitorCommands.c | 73 +++ .../SiliconLabs/_nanoCLR/CMakeLists.txt | 38 ++ .../_nanoCLR/System.Device.Gpio/cpu_gpio.cpp | 498 ++++++++++++++++++ .../sys_dev_gpio_native_target.h | 13 + .../SiliconLabs/_nanoCLR/targetHAL.cpp | 286 ++++++++++ .../SiliconLabs/_nanoCLR/targetHAL_Power.c | 130 +++++ .../SiliconLabs/_nanoCLR/targetHAL_Time.cpp | 185 +++++++ .../SiliconLabs/_nanoCLR/target_platform.h.in | 33 ++ targets/AzureRTOS/_common/include/LaunchCLR.h | 2 + 43 files changed, 3125 insertions(+), 8 deletions(-) create mode 100644 CMake/Modules/AzureRTOS_EFM32GG1_GCC_options.cmake create mode 100644 CMake/Modules/Gecko_SDK.cmake create mode 100644 targets/AzureRTOS/SiliconLabs/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/_include/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/_include/platformHAL.h create mode 100644 targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h create mode 100644 targets/AzureRTOS/SiliconLabs/_include/targetPAL.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in diff --git a/CMake/Modules/AzureRTOS_EFM32GG1_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG1_GCC_options.cmake new file mode 100644 index 0000000000..b832f51c96 --- /dev/null +++ b/CMake/Modules/AzureRTOS_EFM32GG1_GCC_options.cmake @@ -0,0 +1,69 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") +set(CMAKE_C_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") +set(CMAKE_CXX_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs " CACHE INTERNAL "executable linker flags") + + +# TARGET parameter to set the target that's setting them for +# optional EXTRA_COMPILE_OPTIONS with compile options to be added +macro(nf_set_compile_options) + + # parse arguments + cmake_parse_arguments(NFSCO "" "TARGET" "EXTRA_COMPILE_OPTIONS" ${ARGN}) + + if(NOT NFSCO_TARGET OR "${NFSCO_TARGET}" STREQUAL "") + message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_compile_options()") + endif() + + # include any extra options coming from any extra args? + # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # enable: + # - FPU + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX) + +endmacro() + + +# TARGET parameter to set the target that's setting them for +# optional EXTRA_LINK_FLAGS with link flags to be added +macro(nf_set_link_options) + + # parse arguments + cmake_parse_arguments(NFSLO "" "TARGET;EXTRA_LINK_FLAGS" "" ${ARGN}) + + if(NOT NFSLO_TARGET OR "${NFSLO_TARGET}" STREQUAL "") + message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_link_options()") + endif() + + # request specs from newlib nano + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs --specs=nosys.specs") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # include libraries in build + nf_include_libraries_in_build(${NFSLO_TARGET}) + + # set extra linker flags + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${NFSLO__EXTRA_LINK_FLAGS} ") + + # set optimization flags + nf_set_optimization_options(${NFSLO_TARGET}) + +endmacro() diff --git a/CMake/Modules/Gecko_SDK.cmake b/CMake/Modules/Gecko_SDK.cmake new file mode 100644 index 0000000000..563ea3664a --- /dev/null +++ b/CMake/Modules/Gecko_SDK.cmake @@ -0,0 +1,87 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) + +# include the Gecko HAL and CMSIS for the appropriate series + +function(nf_set_silabs_target_series) + + # process target series, which is in the format "SILABS_xxxxx" + string(REPLACE "SILABS" "" TARGET_SERIES_SHORT "${TARGET_SERIES}") + + # store the series name for later use + set(TARGET_SERIES_SHORT ${TARGET_SERIES_SHORT} CACHE INTERNAL "Silabs series short name") + + if("${TARGET_SERIES}" STREQUAL "EFM32GG1") + # WHEN CHANGING THESE MAKE SURE TO UPDATE THE DEV CONTAINERS + # set(HAL_DRIVER_GIT_TAG v1.7.6) + # set(CMSIS_DEVICE_GIT_TAG v2.3.6) + else() + # series is NOT supported + message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") + endif() + +endfunction() + + +# check if cube package source was specified or if it's empty (default is empty) +macro(nf_process_gecko_sdk) + + FetchContent_GetProperties(gecko_sdk) + + # general files + + #series specific files + if("${TARGET_SERIES}" STREQUAL "EFM32GG1") + + set(GECKO_SDK_SRCS + + # RT + chcore.c + chcoreasm.S + ) + + endif() + +endmacro() + +# macro to be called from binutils to add Gecko SDK as a library +# optional EXTRA_INCLUDES with include paths to be added to the library +# optional EXTRA_COMPILE_DEFINITIONS with compiler definitions to be added to the library +macro(nf_add_gecko_sdk) + + # parse arguments + cmake_parse_arguments(NFGCKSDK "" "BUILD_TARGET" "EXTRA_INCLUDES;EXTRA_COMPILE_DEFINITIONS" ${ARGN}) + + if("${NFGCKSDK_BUILD_TARGET}" STREQUAL "${NANOBOOTER_PROJECT_NAME}") + set(CONFIG_FILES_PATH "${TARGET_BASE_LOCATION}/nanoBooter") + elseif("${NFGCKSDK_BUILD_TARGET}" STREQUAL "${NANOCLR_PROJECT_NAME}") + set(CONFIG_FILES_PATH "${TARGET_BASE_LOCATION}/nanoCLR") + endif() + + # add THESE has a library + set(LIB_NAME gecko_sdk) + + add_library( + ${LIB_NAME} STATIC + gecko_sdk_SOURCES + ) + + target_include_directories( + ${LIB_NAME} + PUBLIC + "gecko_sdk_INCLUDE_DIRS}" + ${NFGCKSDK_EXTRA_INCLUDES} + ) + + nf_set_compile_options(TARGET ${LIB_NAME} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS ${NFGCKSDK_EXTRA_COMPILE_DEFINITIONS} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + nf_set_link_options(TARGET ${LIB_NAME}) + + # add alias + add_library("nano::${LIB_NAME}" ALIAS ${LIB_NAME}) + +endmacro() diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index e8b6c8f2dc..2fe0070b4a 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -27,11 +27,6 @@ endfunction() # sets network connectivity options according to the NetX driver choosen in build options WIFI_DRIVER and ETHERNET_DRIVER macro(nf_set_network_connectivity_options) - # sanity check - if(NOT DEFINED ETHERNET_DRIVER AND NOT DEFINED WIFI_DRIVER) - message(FATAL_ERROR "\n\nSorry but you must define either ETHERNET_DRIVER or WIFI_DRIVER build option...\n\n") - endif() - ############################ if(DEFINED WIFI_DRIVER) diff --git a/CMakePresets.json b/CMakePresets.json index f89834d757..e17b3d3b66 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -273,7 +273,7 @@ } }, { - "name": "EFM32GG11_preset", + "name": "SL_STK3701A_preset", "inherits": [ "general-preset", "arm-gcc-cortex-preset" @@ -281,7 +281,7 @@ "hidden": true, "cacheVariables": { "RTOS": "AzureRTOS", - "TARGET_SERIES": "SILABS_GG_S1", + "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", "NF_FEATURE_DEBUGGER": "ON", "NF_FEATURE_RTC": "ON", diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index a70730c3e6..9d881fc97b 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -141,7 +141,7 @@ "inherits": [ "user-local-tools", "user-prefs", - "EFM32GG11_preset" + "SL_STK3701A_preset" ], "cacheVariables": { "TARGET_BOARD": { diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index 85675bd546..8739565215 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -360,6 +360,23 @@ elseif(EXISTS ${PROJECT_SOURCE_DIR}/targets/AzureRTOS/Maxim/${TARGET_BOARD}) set(TARGET_VENDOR Maxim) +# try to find SiliconLabs board in the targets folder +elseif(EXISTS ${PROJECT_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/${TARGET_BOARD}) + + # board found + message(STATUS "Support for target board '${TARGET_BOARD}' found") + + # Define base path for the class libraries + nf_set_base_path_for_libraries_modules(${PROJECT_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_nanoCLR) + + # set target base location + set(TARGET_BASE_LOCATION ${PROJECT_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/${TARGET_BOARD}) + + add_subdirectory(SiliconLabs) + + # add TARGET board directory + add_subdirectory(SiliconLabs/${TARGET_BOARD}) + else() # try to find STM board in the Community targets folder diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt new file mode 100644 index 0000000000..724639e32b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -0,0 +1,90 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(binutils.common) +include(Gecko_SDK) + +# Set target series +nf_set_silabs_target_series() + +# check if GECKO_SDK_SOURCE was specified or if it's empty (default is empty) +set(NO_GECKO_SDK_SOURCE TRUE) +if(GECKO_SDK_SOURCE) + if(NOT ${GECKO_SDK_SOURCE} STREQUAL "") + set(NO_GECKO_SDK_SOURCE FALSE) + endif() +endif() + +# Gecko SDK version +set(GECKO_SDK_VERSION_EMPTY TRUE) + +# check if build was requested with a specifc Gecko SDK version +if(DEFINED GECKO_SDK_VERSION) + if(NOT "${GECKO_SDK_VERSION}" STREQUAL "") + set(GECKO_SDK_VERSION_EMPTY FALSE) + endif() +endif() + +# check if build was requested with a specifc Gecko SDK version +if(GECKO_SDK_VERSION_EMPTY) + # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version + # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS + set(GECKO_SDK_VERSION "v4.0.2") +endif() + +if(NO_GECKO_SDK_SOURCE) + # no Gecko SDK source specified, download it from it's repo + message(STATUS "Gecko SDK is: ${GECKO_SDK_VERSION} from official repo") + + FetchContent_Declare( + gecko_sdk + GIT_REPOSITORY https://github.com/SiliconLabs/gecko_sdk.git + GIT_TAG ${GECKO_SDK_VERSION} + ) + +else() + # Gecko SDK source was specified + + # sanity check is source path exists + if(EXISTS ${GECKO_SDK_SOURCE}/) + if(CMAKE_HOST_SYSTEM_NAME STREQUAL Windows) + + message(STATUS "Gecko SDK is: ${GECKO_SDK_VERSION} (source from: ${GECKO_SDK_SOURCE})") + FetchContent_Declare( + gecko_sdk + SOURCE_DIR ${GECKO_SDK_SOURCE} + ) + + else() + message(STATUS "Gecko SDK is: ${GECKO_SDK_VERSION} (source from: ${GECKO_SDK_SOURCE})") + + FetchContent_Declare( + gecko_sdk + SOURCE_DIR ${GECKO_SDK_SOURCE} + ) + + endif() + else() + message(FATAL_ERROR "Couldn't find Gecko SDK source at ${GECKO_SDK_SOURCE}/") + endif() + +endif() + +FetchContent_GetProperties(gecko_sdk) +FetchContent_Populate(gecko_sdk) + +# including here the CMake files for the source files specific to the target series +include(AzureRTOS_${TARGET_SERIES}_sources) + +list(APPEND TARGET_AZURERTOS_COMMON_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/_include) + +# make vars global +set(TARGET_AZURERTOS_COMMON_INCLUDE_DIRS ${TARGET_AZURERTOS_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") + +# add platform dirs +add_subdirectory(_include) +add_subdirectory(_common) +add_subdirectory(_nanoBooter) +add_subdirectory(_nanoCLR) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt new file mode 100644 index 0000000000..6f0d4f04ca --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -0,0 +1,36 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +# set(STM32_DRIVER_TARGET_DEVICE STM32L475xx CACHE BOOL "Set STM32 target for HAL Driver") + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + # BOOTER_EXTRA_LINKMAP_PROPERTIES + # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x4000" + + # CLR_EXTRA_LINKMAP_PROPERTIES + # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x2000" +) + +# make vars global +set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..39d1668d73 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,124 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 08000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, + + // 08008000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 16, 237}, + + // 08077000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 509}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 080FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + // STM32L4 flash requires 64bits width programming + (BlockRegionAttribute_ProgramWidthIs64bits), + + // start address for block region + 0x08000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x800, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c new file mode 100644 index 0000000000..c52a00f600 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c @@ -0,0 +1,124 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 08000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, + + // 08008000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 16, 158}, + + // 0804F800 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 080FF800 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + // STM32L4 flash requires 64bits width programming + (BlockRegionAttribute_ProgramWidthIs64bits), + + // start address for block region + 0x08000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x800, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json new file mode 100644 index 0000000000..9bacbe281d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json @@ -0,0 +1,115 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "ST_B_L475E_IOT01A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "targetArchitecture": "ARM", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoBooter.hex\" " + }, + { + "text": "file /build/nanoBooter.elf" + }, + { + "text": "monitor reset halt" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": false + } + ], + "customLaunchSetupCommands": [ + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" + }, + { + "name": "ST_B_L475E_IOT01A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "targetArchitecture": "ARM", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoCLR.hex\" " + }, + { + "text": "file /build/nanoCLR.elf" + }, + { + "text": "monitor reset halt" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": false + } + ], + "customLaunchSetupCommands": [ + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..d547592f88 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,229 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c new file mode 100644 index 0000000000..f56cc17fab --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -0,0 +1,147 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#include +#include +#include +#include + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + // palTogglePad(GPIOB, GPIOB_LD2); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // starts the serial driver + // sdStart(&SERIAL_DRIVER, NULL); + +// #if (HAL_NF_USE_STM32_CRC == TRUE) +// // startup crc +// crcStart(NULL); +// #endif + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + //halInit(); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // // check if there is a request to remain on nanoBooter + // if (!IsToRemainInBooter()) + // { + // // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) + // { + // // check for valid CLR image + // // we are checking for a valid image at the deployment address, which is pointing to the CLR address + // if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + // { + // // there seems to be a valid CLR image + // // launch nanoCLR + // LaunchCLR((uint32_t)&__deployment_start__); + // } + // } + // } + + // Enter the ThreadX kernel + tx_kernel_enter(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..3eee9275ee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..d547592f88 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,229 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c new file mode 100644 index 0000000000..48e004773f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -0,0 +1,132 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// #include +// #include + +// #include + +// #include +// #include +// #include +// #include +// #include +// #include +// #include +// #include +// #include + +// extern TX_EVENT_FLAGS_GROUP wpUartEvent; +// extern CLR_SETTINGS clrSettings; + +// // byte pool configuration and definitions +// // need to be at least as big as the config sector +// #define DEFAULT_BYTE_POOL_SIZE 0x2000 +// TX_BYTE_POOL byte_pool_0; +// uint8_t __attribute__((section(".ram4"))) memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// // threads definitions and configurations + +// // receiver thread +// #define RECEIVER_THREAD_STACK_SIZE 2048 +// #define RECEIVER_THREAD_PRIORITY 5 + +// TX_THREAD receiverThread; +// uint32_t __attribute__((section(".ram4"))) receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +// extern void ReceiverThread_entry(uint32_t parameter); + +// // CLR thread +// #define CLR_THREAD_STACK_SIZE 4092 +// #define CLR_THREAD_PRIORITY 5 + +// TX_THREAD clrStartupThread; +// uint32_t __attribute__((section(".ram4"))) clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +// extern void ClrStartupThread_entry(uint32_t parameter); + +// void tx_application_define(void *first_unused_memory) +// { +// (void)first_unused_memory; +// uint16_t status; + +// // Create a byte memory pool from which to allocate the thread stacks. +// tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + +// // start watchdog +// Watchdog_Init(); + +// // turn LED2 off +// palClearPad(GPIOB, GPIOB_LD2); + +// #if (HAL_NF_USE_STM32_CRC == TRUE) +// // startup crc +// crcStart(NULL); +// #endif + +// // starts the serial driver +// sdStart(&SERIAL_DRIVER, NULL); + +// #if (TRACE_TO_STDIO == TRUE) +// StdioPort_Init(); +// #endif + +// // Create receiver thread +// status = tx_thread_create( +// &receiverThread, +// "Receiver Thread", +// ReceiverThread_entry, +// 0, +// receiverThreadStack, +// RECEIVER_THREAD_STACK_SIZE, +// RECEIVER_THREAD_PRIORITY, +// RECEIVER_THREAD_PRIORITY, +// TX_NO_TIME_SLICE, +// TX_AUTO_START); + +// if (status != TX_SUCCESS) +// { +// while (1) +// { +// } +// } + +// // CLR settings to launch CLR thread +// memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + +// clrSettings.MaxContextSwitches = 50; +// clrSettings.WaitForDebugger = false; +// clrSettings.EnterDebuggerLoopAfterExit = true; + +// // Create CLR startup thread +// status = tx_thread_create( +// &clrStartupThread, +// "CLR Thread", +// ClrStartupThread_entry, +// (uint32_t)&clrSettings, +// clrStartupThreadStack, +// CLR_THREAD_STACK_SIZE, +// CLR_THREAD_PRIORITY, +// CLR_THREAD_PRIORITY, +// TX_NO_TIME_SLICE, +// TX_AUTO_START); + +// if (status != TX_SUCCESS) +// { +// while (1) +// { +// } +// } +// } + +// // Application entry point. +// int main(void) +// { +// halInit(); + +// // init boot clipboard +// InitBootClipboard(); + +// // Enter the ThreadX kernel +// tx_kernel_enter(); +// } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c new file mode 100644 index 0000000000..e0e9fe93fc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// extern struct BlockStorageDevice Device_BlockStorage; +// extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +// extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +// void BlockStorage_AddDevices() +// { +// BlockStorageList_AddDevice( +// (BlockStorageDevice *)&Device_BlockStorage, +// &STM32Flash_BlockStorageInterface, +// &Device_BlockStorageConfig, +// false); +// } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c new file mode 100644 index 0000000000..0635f76a6c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c @@ -0,0 +1,30 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0,//ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use JTAG for updates +// TODO +// inline GET_TARGET_CAPABILITIES(TargetCapabilities_JtagUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(true); diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in new file mode 100644 index 0000000000..f62324c82a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in @@ -0,0 +1,45 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x10000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00008000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.c new file mode 100644 index 0000000000..457394d46b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.c @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// // pin configuration for stdio using UART4 +// // port for TX pin is: GPIOA +// // port for RX pin is: GPIOA +// // TX pin: is GPIOA_0 +// // RX pin: is GPIOA_1 +// // GPIO alternate pin function is 8 see alternate function mapping ST datasheet +// STDIO_UART_CONFIG_PINS(GPIOA, GPIOA, 0, 1, 8) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.h new file mode 100644 index 0000000000..d5df942106 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_stdio_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// Select which STM32 uart/serial port used. +// If you change STDIO_SERIAL_DRIVER here to another UARTn, also +// edit mcuconf.h to set #define STM32_SERIAL_USE_UARTn TRUE +// and edit GPIO pins defined in target_stdio_config.c +// #define STDIO_SERIAL_DRIVER SD4 diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/targets/AzureRTOS/SiliconLabs/_include/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_include/CMakeLists.txt new file mode 100644 index 0000000000..a04b9c88fb --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append include directory for target Azure RTOS +list(APPEND TARGET_AZURERTOS_COMMON_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) + +# make var global +set(TARGET_AZURERTOS_COMMON_INCLUDE_DIRS ${TARGET_AZURERTOS_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h b/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h new file mode 100644 index 0000000000..6b58caa8f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _PLATFORM_HAL_TIME_H_ +#define _PLATFORM_HAL_TIME_H_ + +#define WIRE_PROTOCOL_UART_BUFFER_SIZE 32 + +#endif //_PLATFORM_HAL_TIME_H_ diff --git a/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h b/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h new file mode 100644 index 0000000000..604aa20859 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_TIME_H_ +#define _TARGET_HAL_TIME_H_ + +#include + +#define HAL_Time_CurrentSysTicks tx_time_get + +#endif //_TARGET_HAL_TIME_H_ diff --git a/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h b/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h new file mode 100644 index 0000000000..1f7f186093 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGETPAL_H +#define TARGETPAL_H + +#endif // TARGETPAL_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..8367e19c36 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +list(APPEND TARGET_AZURERTOS_NANOBOOTER_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) + +# make var global +set(TARGET_AZURERTOS_NANOBOOTER_SOURCES ${TARGET_AZURERTOS_NANOBOOTER_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c b/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c new file mode 100644 index 0000000000..66eb37a9ef --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c @@ -0,0 +1,73 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// #include +// #include +// #include +// #include +// #include +// #include + +// int AccessMemory(uint32_t location, uint32_t lengthInBytes, uint8_t *buffer, int32_t mode, uint32_t *errorCode) +// { +// // reset error code +// *errorCode = AccessMemoryErrorCode_NoError; + +// switch (mode) +// { +// case AccessMemory_Write: +// // use FLASH driver to perform write operation +// // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h +// return STM32FlashDriver_Write(NULL, location, lengthInBytes, buffer, true); + +// case AccessMemory_Erase: +// // erase using FLASH driver +// // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h +// return STM32FlashDriver_EraseBlock(NULL, location); + +// case AccessMemory_Check: +// // compute CRC32 of the memory segment +// *(unsigned int *)buffer = SUPPORT_ComputeCRC((uint32_t *)location, lengthInBytes, 0); +// // done here +// return true; + +// case AccessMemory_Read: +// // use FLASH driver to perform read operation +// // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h +// STM32FlashDriver_Read(NULL, location, lengthInBytes, buffer); +// return true; + +// default: +// // default return is FALSE +// return false; +// } +// } + +// //////////////////////////////////////////////////// + +// int Monitor_Reboot(WP_Message *message) +// { +// Monitor_Reboot_Command *cmd = (Monitor_Reboot_Command *)message->m_payload; + +// WP_ReplyToCommand(message, true, false, NULL, 0); + +// if (cmd != NULL) +// { +// if (Monitor_Reboot_c_EnterProprietaryBooter == (cmd->m_flags & Monitor_Reboot_c_EnterProprietaryBooter)) +// { +// // request to load proprietary bootloader +// // OK to call directly as this will launch the bootloader only if the target has support for it +// LaunchProprietaryBootloader(); +// } +// else +// { +// // RESET CPU to load nanoCLR +// NVIC_SystemReset(); +// } +// } + +// return true; +// } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..b2f67531a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt @@ -0,0 +1,38 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# add header file with common target definitions +configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in + ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) + +# append target Azure RTOS nanoCLR source files +list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) +list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp) +list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c) + +# make var global +set(TARGET_AZURERTOS_NANOCLR_SOURCES ${TARGET_AZURERTOS_NANOCLR_SOURCES} CACHE INTERNAL "make global") + +# append target nanoCLR include directories +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Core) + +# append PAL include directory +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) + +# append Runtime.Native include directory +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Runtime.Native) + +# append nano API includes +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src) + +# append includes +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src) + +# make var global +set(TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS ${TARGET_AZURERTOS_NANOCLR_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp new file mode 100644 index 0000000000..789b2144e0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp @@ -0,0 +1,498 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "sys_dev_gpio_native_target.h" + +#define GPIO_MAX_PIN 256 +#define TOTAL_GPIO_PORTS ((GPIO_MAX_PIN + 15) / 16) + +// // Double linkedlist to hold the state of each Input pin +// struct gpio_input_state : public HAL_DblLinkedNode +// { +// // Pin number +// GPIO_PIN pinNumber; +// // debounce timer for this Pin +// TX_TIMER debounceTimer; +// // Ptr to user ISR or null +// GPIO_INTERRUPT_SERVICE_ROUTINE isrPtr; +// // debounce Millsecs, no debonce=0 +// uint32_t debounceMs; +// // Interrupt mode +// uint8_t mode; +// // Param to user isr call +// void *param; +// // Expected state for debounce handler +// bool expected; +// // True if waiting for debounce timer to complete +// bool waitingDebounce; +// }; + +// static HAL_DblLinkedList gpioInputList; // Double Linked list for GPIO input status +// static uint16_t pinReserved[TOTAL_GPIO_PORTS]; // reserved - 1 bit per pin + +// // this is an utility function to get a ChibiOS PAL IoLine from our "encoded" pin number +// static ioline_t GetIoLine(int16_t pinNumber) +// { +// stm32_gpio_t *port = GPIO_PORT(pinNumber); +// int16_t pad = pinNumber % 16; + +// return PAL_LINE(port, pad); +// } + +// bool IsValidGpioPin(GPIO_PIN pinNumber) +// { +// return (pinNumber <= GPIO_MAX_PIN); +// } + +// // Get pointer to gpio_input_state for GPIO pin +// // return NULL if not found +// gpio_input_state *GetGpioWithInterrupt(uint16_t gpioPin) +// { +// gpio_input_state *ptr = gpioInputList.FirstNode(); +// while (ptr->Next() != NULL) +// { +// if (GPIO_PIN(ptr->pinNumber) == gpioPin) +// { +// return ptr; +// } + +// ptr = ptr->Next(); +// } + +// return NULL; +// } + +// static void DebounceTimerCallback(uint32_t id) +// { +// gpio_input_state *pState = (gpio_input_state *)id; + +// // get current pin state +// bool actual = palReadLine(GetIoLine(pState->pinNumber)); + +// if (actual == pState->expected) +// { +// pState->isrPtr(pState->pinNumber, actual, pState->param); +// if (pState->mode == GPIO_INT_EDGE_BOTH) +// { +// // both edges +// // update expected state +// pState->expected ^= 1; +// } +// } + +// pState->waitingDebounce = false; +// } + +// void GpioEventCallback(void *arg) +// { +// NATIVE_INTERRUPT_START + +// TX_DISABLE + +// gpio_input_state *pGpio = (gpio_input_state *)arg; + +// if (pGpio != NULL) +// { +// // Ignore any pin changes during debounce +// if (!pGpio->waitingDebounce) +// { +// // check if there is a debounce time set +// if (pGpio->debounceMs > 0) +// { +// // Set flag we are waiting for debounce on this pin +// pGpio->waitingDebounce = true; + +// // setup timer +// tx_timer_deactivate(&pGpio->debounceTimer); +// tx_timer_change(&pGpio->debounceTimer, 0, pGpio->debounceMs / 10); +// tx_timer_activate(&pGpio->debounceTimer); +// } +// else +// { +// // get IoLine from pin number +// ioline_t ioLine = GetIoLine(pGpio->pinNumber); + +// TX_RESTORE + +// pGpio->isrPtr(pGpio->pinNumber, palReadLine(ioLine), pGpio->param); + +// TX_DISABLE +// } +// } +// } + +// TX_RESTORE + +// NATIVE_INTERRUPT_END +// } + +// // Get pointer to gpio_input_state for Gpio pin +// // return NULL if not found +// gpio_input_state *GetInputState(GPIO_PIN pinNumber) +// { +// gpio_input_state *ptr = gpioInputList.FirstNode(); + +// while (ptr->Next() != NULL) +// { +// if (ptr->pinNumber == pinNumber) +// { +// return ptr; +// } + +// ptr = ptr->Next(); +// } + +// return NULL; +// } + +// // Allocate a new gpio_input_state and add to end of list +// // if already exist then just return current ptr +// gpio_input_state *AllocateGpioInputState(GPIO_PIN pinNumber) +// { +// gpio_input_state *ptr = GetInputState(pinNumber); + +// if (ptr == NULL) +// { +// ptr = (gpio_input_state *)platform_malloc(sizeof(gpio_input_state)); + +// // sanity check +// if (ptr != NULL) +// { +// memset(ptr, 0, sizeof(gpio_input_state)); +// ptr->pinNumber = pinNumber; + +// tx_timer_create( +// &ptr->debounceTimer, +// (char *)"GPIO debounce timer", +// DebounceTimerCallback, +// 0, +// 0, +// 1, +// TX_NO_ACTIVATE); + +// gpioInputList.LinkAtBack(ptr); +// } +// } + +// return ptr; +// } + +// void UnlinkInputState(gpio_input_state *pState) +// { +// tx_timer_delete(&pState->debounceTimer); + +// // disable the EXT interrupt channel +// // it's OK to do always this, no matter if it's enabled or not +// palDisableLineEvent(GetIoLine(pState->pinNumber)); + +// pState->Unlink(); + +// platform_free(pState); +// } + +// // Delete gpio_input_state from List and tidy up ( Timer & ISR handler ) +// void DeleteInputState(GPIO_PIN pinNumber) +// { +// gpio_input_state *pState = GetInputState(pinNumber); + +// if (pState) +// { +// UnlinkInputState(pState); +// } +// } + +// bool CPU_GPIO_Initialize() +// { +// // Initialise Double linked list for input pin states +// gpioInputList.Initialize(); + +// // Make sure all pins are not reserved +// memset(pinReserved, 0, sizeof(pinReserved)); + +// return true; +// } + +// bool CPU_GPIO_Uninitialize() +// { +// NANOCLR_FOREACH_NODE(gpio_input_state, pGpio, gpioInputList) +// { +// UnlinkInputState(pGpio); +// } +// NANOCLR_FOREACH_NODE_END(); + +// return true; +// } + +// // Set/reset reserved state of pin +// bool CPU_GPIO_ReservePin(GPIO_PIN pinNumber, bool fReserve) +// { +// // Check if valid pin number +// if (!IsValidGpioPin(pinNumber)) +// { +// return false; +// } + +// int port = pinNumber >> 4, bit = 1 << (pinNumber & 0x0F); +// bool ret = true; +// GLOBAL_LOCK(); + +// if (fReserve) +// { +// if (pinReserved[port] & bit) +// { +// ret = false; // already reserved +// } +// else +// { +// pinReserved[port] |= bit; +// } +// } +// else +// { +// pinReserved[port] &= ~bit; +// } + +// GLOBAL_UNLOCK(); +// return ret; +// } + +// // Return if Pin is reserved +// bool CPU_GPIO_PinIsBusy(GPIO_PIN pinNumber) +// { +// // Check if valid pin number +// if (!IsValidGpioPin(pinNumber)) +// { +// return false; +// } + +// int port = pinNumber >> 4, sh = pinNumber & 0x0F; +// return (pinReserved[port] >> sh) & 1; +// } + +// // Return maximum number of pins +// int32_t CPU_GPIO_GetPinCount() +// { +// return GPIO_MAX_PIN; +// } + +// // Get current state of pin +// GpioPinValue CPU_GPIO_GetPinState(GPIO_PIN pin) +// { +// return (GpioPinValue)palReadLine(GetIoLine(pin)); +// } + +// // Set Pin state +// void CPU_GPIO_SetPinState(GPIO_PIN pin, GpioPinValue pinState) +// { +// palWriteLine(GetIoLine(pin), (int)pinState); +// } + +// void CPU_GPIO_TogglePinState(GPIO_PIN pinNumber) +// { +// palToggleLine(GetIoLine(pinNumber)); +// } + +// bool CPU_GPIO_EnableInputPin( +// GPIO_PIN pinNumber, +// uint32_t debounceTimeMilliseconds, +// GPIO_INTERRUPT_SERVICE_ROUTINE pinISR, +// void *isrParam, +// GPIO_INT_EDGE intEdge, +// PinMode driveMode) +// { +// gpio_input_state *pState; + +// // Check Input drive mode +// if (driveMode >= (int)PinMode_Output) +// { +// return false; +// } + +// // Set as Input GPIO_INT_EDGE intEdge, GPIO_RESISTOR ResistorState +// if (!CPU_GPIO_SetDriveMode(pinNumber, driveMode)) +// { +// return false; +// } + +// pState = AllocateGpioInputState(pinNumber); + +// // Link ISR ptr supplied and not already set up +// // CPU_GPIO_EnableInputPin could be called a 2nd time with changed parameters +// if (pinISR != NULL && (pState->isrPtr == NULL)) +// { +// // there are callbacks registered and... +// // the drive mode is input so need to setup the interrupt + +// // get IoLine from pin number +// ioline_t ioLine = GetIoLine(pinNumber); + +// palEnableLineEvent(ioLine, PAL_EVENT_MODE_BOTH_EDGES); +// palSetLineCallback(ioLine, GpioEventCallback, pState); + +// // store parameters & configs +// pState->isrPtr = pinISR; +// pState->mode = intEdge; +// pState->param = (void *)isrParam; +// pState->debounceMs = (uint32_t)(debounceTimeMilliseconds); + +// switch (intEdge) +// { +// case GPIO_INT_EDGE_LOW: +// case GPIO_INT_LEVEL_LOW: +// pState->expected = PAL_LOW; +// break; + +// case GPIO_INT_EDGE_HIGH: +// case GPIO_INT_LEVEL_HIGH: +// pState->expected = PAL_HIGH; +// break; + +// case GPIO_INT_EDGE_BOTH: +// pState->expected = !CPU_GPIO_GetPinState(pinNumber); // expected NOT current state +// break; + +// default: +// break; +// } +// } +// else if (pinISR == NULL && (pState->isrPtr != NULL)) +// { +// // there is no managed handler setup anymore + +// // disable the EXT interrupt channel +// // it's OK to do always this, no matter if it's enabled or not +// palDisableLineEvent(GetIoLine(pState->pinNumber)); + +// // clear parameters & configs +// pState->isrPtr = NULL; +// pState->mode = GPIO_INT_NONE; +// pState->param = NULL; +// pState->debounceMs = 0; +// } + +// return true; +// } + +// // Enable an output pin +// // +// // pinNumber - Gpio pin number +// // InitialState - Initial state of pin +// // driveMode - Drive mode and resistors +// // return - True if succesful, false invalid pin, pin not putput, invalid drive mode for ouptput +// // +// bool CPU_GPIO_EnableOutputPin(GPIO_PIN pinNumber, GpioPinValue InitialState, PinMode driveMode) +// { +// // check not an output drive mode +// if (driveMode < (int)PinMode_Output) +// { +// return false; +// } + +// // If this is currently an input pin then clean up +// DeleteInputState(pinNumber); + +// if (CPU_GPIO_SetDriveMode(pinNumber, driveMode) == false) +// { +// return false; +// } + +// CPU_GPIO_SetPinState(pinNumber, InitialState); + +// return true; +// } + +// void CPU_GPIO_DisablePin(GPIO_PIN pinNumber, PinMode driveMode, uint32_t alternateFunction) +// { +// DeleteInputState(pinNumber); + +// GLOBAL_LOCK(); + +// CPU_GPIO_SetDriveMode(pinNumber, driveMode); + +// // get IoLine from pin number +// ioline_t ioLine = GetIoLine(pinNumber); +// palSetLineMode(ioLine, PAL_MODE_ALTERNATE(alternateFunction)); + +// GLOBAL_UNLOCK(); + +// CPU_GPIO_ReservePin(pinNumber, false); +// } + +// // Validate pin and set drive mode +// // return true if ok +// bool CPU_GPIO_SetDriveMode(GPIO_PIN pinNumber, PinMode driveMode) +// { +// // get IoLine from pin number +// ioline_t ioLine = GetIoLine(pinNumber); + +// switch (driveMode) +// { +// case PinMode_Input: +// palSetLineMode(ioLine, PAL_MODE_INPUT); +// break; + +// case PinMode_InputPullDown: +// palSetLineMode(ioLine, PAL_MODE_INPUT_PULLDOWN); +// break; + +// case PinMode_InputPullUp: +// palSetLineMode(ioLine, PAL_MODE_INPUT_PULLUP); +// break; + +// case PinMode_Output: +// palSetLineMode(ioLine, PAL_MODE_OUTPUT_PUSHPULL); +// break; + +// case PinMode_OutputOpenDrain: +// palSetLineMode(ioLine, PAL_MODE_OUTPUT_OPENDRAIN); +// break; + +// default: +// // all other modes are NOT supported +// return false; +// } + +// return true; +// } + +// bool CPU_GPIO_DriveModeSupported(GPIO_PIN pinNumber, PinMode driveMode) +// { +// (void)pinNumber; + +// bool driveModeSupported = false; + +// // check if the requested drive mode is support by ChibiOS config +// if ((driveMode == PinMode_Input) || (driveMode == PinMode_InputPullDown) || (driveMode == PinMode_InputPullUp) || +// (driveMode == PinMode_Output) || (driveMode == PinMode_OutputOpenDrain)) +// { +// driveModeSupported = true; +// } + +// return driveModeSupported; +// } + +// uint32_t CPU_GPIO_GetPinDebounce(GPIO_PIN pinNumber) +// { +// gpio_input_state *ptr = GetInputState(pinNumber); + +// if (ptr) +// { +// return ptr->debounceMs; +// } + +// return 0; +// } + +// bool CPU_GPIO_SetPinDebounce(GPIO_PIN pinNumber, uint32_t debounceTimeMilliseconds) +// { +// gpio_input_state *ptr = GetInputState(pinNumber); +// if (ptr) +// { +// ptr->debounceMs = debounceTimeMilliseconds; +// return true; +// } +// return false; +// } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h new file mode 100644 index 0000000000..202ac24153 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_GPIO_NATIVE_TARGET_H +#define SYS_DEV_GPIO_NATIVE_TARGET_H + +#include +#include +// #include + +#endif // SYS_DEV_GPIO_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp new file mode 100644 index 0000000000..55024d32d5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -0,0 +1,286 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include +#include + +// #if (HAL_USE_CAN == TRUE) +// #include +// #endif +// #if (HAL_USE_I2C == TRUE) +// #include +// #endif +// #if (HAL_USE_SPI == TRUE) +// #include +// #endif +// #if (HAL_USE_UART == TRUE) +// #include +// #endif + +// global mutex protecting the internal state of the interpreter, including event flags +// mutex_t interpreterGlobalMutex; + +// because nanoHAL_Initialize/Uninitialize needs to be called in both C and C++ we need a proxy to allow it to be called +// in 'C' +extern "C" +{ + + void nanoHAL_Initialize_C() + { + nanoHAL_Initialize(); + } + + void nanoHAL_Uninitialize_C() + { + nanoHAL_Uninitialize(); + } +} + +void nanoHAL_Initialize() +{ + // initialize global mutex + // chMtxObjectInit(&interpreterGlobalMutex); + + HAL_CONTINUATION::InitializeList(); + HAL_COMPLETION ::InitializeList(); + + BlockStorageList_Initialize(); + + // initialize block storage devices + BlockStorage_AddDevices(); + + BlockStorageList_InitializeDevices(); + + // clear managed heap region + unsigned char *heapStart = NULL; + unsigned int heapSize = 0; + + ::HeapLocation(heapStart, heapSize); + memset(heapStart, 0, heapSize); + +#if (NANOCLR_GRAPHICS == TRUE) + g_GraphicsMemoryHeap.Initialize(); +#endif + + ConfigurationManager_Initialize(); + + Events_Initialize(); + + CPU_GPIO_Initialize(); + +// #if (HAL_USE_CAN == TRUE) + +// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) +// Can1_PAL.Driver = NULL; +// #endif +// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) +// Can2_PAL.Driver = NULL; +// #endif +// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) +// Can3_PAL.Driver = NULL; +// #endif + +// #endif + +// #if (HAL_USE_I2C == TRUE) + +// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) +// I2C1_PAL.Driver = NULL; +// #endif +// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) +// I2C2_PAL.Driver = NULL; +// #endif +// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) +// I2C3_PAL.Driver = NULL; +// #endif +// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) +// I2C4_PAL.Driver = NULL; +// #endif + +// #endif + +// #if (HAL_USE_SPI == TRUE) +// nanoSPI_Initialize(); +// #endif + +// #if (HAL_USE_UART == TRUE) + +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) +// Uart1_PAL.UartDriver = NULL; +// Uart1_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) +// Uart2_PAL.UartDriver = NULL; +// Uart2_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) +// Uart3_PAL.UartDriver = NULL; +// Uart3_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) +// Uart4_PAL.UartDriver = NULL; +// Uart4_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) +// Uart5_PAL.UartDriver = NULL; +// Uart5_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) +// Uart6_PAL.UartDriver = NULL; +// Uart6_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) +// Uart7_PAL.UartDriver = NULL; +// Uart7_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) +// Uart8_PAL.UartDriver = NULL; +// Uart8_PAL__.UartDriver = NULL; +// #endif + +// #endif + +#if (NANOCLR_GRAPHICS == TRUE) + DisplayInterfaceConfig config; // not used for DSI display + g_DisplayInterface.Initialize(config); + g_DisplayDriver.Initialize(); + + // g_TouchInterface.Initialize(); + // g_TouchDevice.Initialize(); + + // PalEvent_Initialize(); + // Gesture_Initialize(); + // Ink_Initialize(); +#endif + + // Initialise Network Stack + Network_Initialize(); +} + +void nanoHAL_Uninitialize() +{ + // release the global mutex, just in case it's locked somewhere + // chMtxUnlock(&interpreterGlobalMutex); + + // TODO check for s_rebootHandlers + // for(int i = 0; i< ARRAYSIZE(s_rebootHandlers); i++) + // { + // if(s_rebootHandlers[i] != NULL) + // { + // s_rebootHandlers[i](); + // } + // else + // { + // break; + // } + // } + + // TODO + SOCKETS_CloseConnections(); + +#if !defined(HAL_REDUCESIZE) + // TODO need to call this but it's preventing the debug session from starting + Network_Uninitialize(); +#endif + + BlockStorageList_UnInitializeDevices(); + + // need to be sure that: + // - all mutexes for drivers that use them are released + // - all drivers are stopped + +// #if (HAL_USE_SPI == TRUE) +// nanoSPI_Uninitialize(); +// #endif + +// #if (HAL_USE_CAN == TRUE) + +// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) +// canStop(&CAND1); +// #endif +// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) +// canStop(&CAND2); +// #endif +// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) +// canStop(&CAND3); +// #endif + +// #endif + +// #if (HAL_USE_I2C == TRUE) + +// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) +// i2cReleaseBus(&I2CD1); +// i2cStop(&I2CD1); +// #endif +// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) +// i2cReleaseBus(&I2CD2); +// i2cStop(&I2CD2); +// #endif +// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) +// i2cReleaseBus(&I2CD3); +// i2cStop(&I2CD3); +// #endif +// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) +// i2cReleaseBus(&I2CD4); +// i2cStop(&I2CD4); +// #endif + +// #endif + +// #if (HAL_USE_SPI == TRUE) +// nanoSPI_Uninitialize(); +// #endif + +// #if (HAL_USE_UART == TRUE) + +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) +// uartReleaseBus(&UARTD1); +// uartStop(&UARTD1); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) +// uartReleaseBus(&UARTD2); +// uartStop(&UARTD2); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) +// uartReleaseBus(&UARTD3); +// uartStop(&UARTD3); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) +// uartReleaseBus(&UARTD4); +// uartStop(&UARTD4); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) +// uartReleaseBus(&UARTD5); +// uartStop(&UARTD5); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) +// uartReleaseBus(&UARTD6); +// uartStop(&UARTD6); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) +// uartReleaseBus(&UARTD7); +// uartStop(&UARTD7); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) +// uartReleaseBus(&UARTD8); +// uartStop(&UARTD8); +// #endif + +// #endif + + CPU_GPIO_Uninitialize(); + + Events_Uninitialize(); + + HAL_CONTINUATION::Uninitialize(); + HAL_COMPLETION ::Uninitialize(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c new file mode 100644 index 0000000000..74e40f1035 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c @@ -0,0 +1,130 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +#ifdef HAL_RTC_MODULE_ENABLED +extern RTC_HandleTypeDef RtcHandle; +#endif + +// uint32_t WakeupReasonStore; + +inline void CPU_Reset() +{ + //NVIC_SystemReset(); +}; + +inline bool CPU_IsSoftRebootSupported() +{ + return true; +}; + +// CPU sleep is not currently implemented in this target +inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents) +{ + (void)level; + (void)wakeEvents; +}; + +void CPU_SetPowerMode(PowerLevel_type powerLevel) +{ + // default to false + //bool success = false; + + switch (powerLevel) + { + case PowerLevel__Off: + // stop watchdog + //wdgStop(&WDGD1); + + // gracefully shutdown everything + nanoHAL_Uninitialize_C(); + + //__disable_irq(); + +// ///////////////////////////////////////////////////////////////////////// +// // stop the idependent watchdog, for series where the option is available +// #if defined(STM32L4XX) + +// (void)success; +// // TODO FIXME this code needs to follow the same workflow as the STM32F7 +// CLEAR_BIT(FLASH->OPTR, FLASH_OPTR_IWDG_STDBY); +// #elif defined(STM32F7XX) + +// // only need to change this option bit if not already done +// if ((FLASH->OPTCR & FLASH_OPTCR_IWDG_STDBY)) +// { +// // developer notes: +// // follow workflow recommended @ 3.4.2 Option bytes programming (from programming manual) +// // Authorizes the Option Byte register programming +// FLASH->OPTKEYR = FLASH_OPT_KEY1; +// FLASH->OPTKEYR = FLASH_OPT_KEY2; + +// // wait 500ms for any flash operation to be completed +// success = FLASH_WaitForLastOperation(500); + +// if (success) +// { +// // write option value (clear the FLASH_OPTCR_IWDG_STDBY) +// CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_IWDG_STDBY); + +// // set the option start bit +// FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; + +// // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without +// // optimization +// __DSB(); + +// // wait 100ms for the flash operation to be completed +// success = FLASH_WaitForLastOperation(100); +// } + +// // Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access +// FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; +// } + +// (void)success; + +// #endif + +// ///////////////////////////////////////////////////// +// // set alarm interrupt enable +// // set power control register to: power down deep sleep +// ///////////////////////////////////////////////////// + +// // TODO +// //__HAL_RTC_ALARMA_ENABLE(&RtcHandle); +// //__HAL_RTC_ALARM_ENABLE_IT(&RtcHandle, RTC_IT_ALRA); + +// // TODO +// // need review here to use ST HAL HAL_PWREx_EnterSTOP2Mode + +// #if defined(STM32F7XX) + +// ////////////////////////////////////////////////////////////////////////////////////////////////////// +// // workaround recommended in section 2.2.2 at STM32F77xxx errata document (DM00257543 - ES0334 Rev 5) // +// PWR->CSR1 |= PWR_CSR1_EIWUP; +// ////////////////////////////////////////////////////////////////////////////////////////////////////// + +// SET_BIT(PWR->CR1, PWR_CR1_PDDS); + +// #endif + + // set SLEEPDEEP bit of Cortex SCR + //SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + // wait for interrupt, and the execution dies here + //__WFI(); + + break; + + default: + // all the other power modes are unsupported here + break; + } +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp new file mode 100644 index 0000000000..2289d35121 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp @@ -0,0 +1,185 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +#include + +// // Returns the current date time from the RTC +// uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +// { +// #if (HAL_USE_RTC == TRUE) + +// // use RTC to get date time +// SYSTEMTIME st; +// RTCDateTime _dateTime; + +// rtcGetTime(&RTCD1, &_dateTime); + +// st.wDay = (unsigned short)_dateTime.day; +// st.wMonth = (unsigned short)_dateTime.month; +// st.wYear = (unsigned short)(_dateTime.year + 1980); // ChibiOS is counting years since 1980 +// st.wDayOfWeek = (unsigned short)_dateTime.dayofweek; + +// // zero 'time' fields if date part only is required +// if (datePartOnly) +// { +// st.wMilliseconds = 0; +// st.wSecond = 0; +// st.wMinute = 0; +// st.wHour = 0; +// } +// else +// { +// // full date&time required, fill in 'time' fields too + +// st.wMilliseconds = (unsigned short)(_dateTime.millisecond % 1000); +// _dateTime.millisecond /= 1000; +// st.wSecond = (unsigned short)(_dateTime.millisecond % 60); +// _dateTime.millisecond /= 60; +// st.wMinute = (unsigned short)(_dateTime.millisecond % 60); +// _dateTime.millisecond /= 60; +// st.wHour = (unsigned short)(_dateTime.millisecond % 24); +// } + +// return HAL_Time_ConvertFromSystemTime(&st); + +// #else + +// if (datePartOnly) +// { +// SYSTEMTIME st; +// HAL_Time_ToSystemTime(HAL_Time_CurrentTime(), &st); + +// st.wHour = 0; +// st.wMinute = 0; +// st.wSecond = 0; +// st.wMilliseconds = 0; + +// return HAL_Time_ConvertFromSystemTime(&st); +// } +// else +// { +// return HAL_Time_CurrentTime(); +// } + +// #endif +// }; + +// void HAL_Time_SetUtcTime(uint64_t utcTime) +// { +// SYSTEMTIME systemTime; + +// HAL_Time_ToSystemTime(utcTime, &systemTime); + +// #if (HAL_USE_RTC == TRUE) + +// // set RTC +// RTCDateTime newTime; + +// newTime.year = systemTime.wYear - 1980; // ChibiOS time base is 1980-01-01 +// newTime.month = systemTime.wMonth; +// newTime.day = systemTime.wDay; +// newTime.dayofweek = systemTime.wDayOfWeek; +// newTime.millisecond = +// ((((uint32_t)systemTime.wHour * 3600) + ((uint32_t)systemTime.wMinute * 60) + (uint32_t)systemTime.wSecond) * +// 1000); + +// // set RTC time +// rtcSetTime(&RTCD1, &newTime); + +// #else + +// // TODO FIXME +// // need to add implementation when RTC is not being used +// // can't mess with the systicks because the scheduling can fail + +// #endif +// } + +bool HAL_Time_TimeSpanToStringEx(const int64_t &ticks, char *&buf, size_t &len) +{ + uint64_t ticksAbs; + uint64_t rest; + + if (ticks < 0) + { + ticksAbs = -ticks; + + CLR_SafeSprintf(buf, len, "-"); + } + else + { + ticksAbs = ticks; + } + + rest = ticksAbs % (1000 * TIME_CONVERSION__TICKUNITS); + ticksAbs = ticksAbs / (1000 * TIME_CONVERSION__TICKUNITS); // Convert to seconds. + + if (ticksAbs > TIME_CONVERSION__ONEDAY) // More than one day. + { + CLR_SafeSprintf(buf, len, "%d.", (int32_t)(ticksAbs / TIME_CONVERSION__ONEDAY)); + ticksAbs %= TIME_CONVERSION__ONEDAY; + } + + CLR_SafeSprintf(buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEHOUR)); + ticksAbs %= TIME_CONVERSION__ONEHOUR; + CLR_SafeSprintf(buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEMINUTE)); + ticksAbs %= TIME_CONVERSION__ONEMINUTE; + CLR_SafeSprintf(buf, len, "%02d", (int32_t)(ticksAbs / TIME_CONVERSION__ONESECOND)); + ticksAbs %= TIME_CONVERSION__ONESECOND; + + ticksAbs = (uint32_t)rest; + if (ticksAbs) + { + CLR_SafeSprintf(buf, len, ".%07d", (uint32_t)ticksAbs); + } + + return len != 0; +} + +bool DateTimeToString(const int64_t &time, char *&buf, size_t &len) +{ + SYSTEMTIME st; + + HAL_Time_ToSystemTime(time, &st); + + return CLR_SafeSprintf( + buf, + len, + "%4d/%02d/%02d %02d:%02d:%02d.%03d", + st.wYear, + st.wMonth, + st.wDay, + st.wHour, + st.wMinute, + st.wSecond, + st.wMilliseconds); +} + +char *DateTimeToString(const int64_t &time) +{ + static char rgBuffer[128]; + char *szBuffer = rgBuffer; + size_t iBuffer = ARRAYSIZE(rgBuffer); + + DateTimeToString(time, szBuffer, iBuffer); + + return rgBuffer; +} + +const char *HAL_Time_CurrentDateTimeToString() +{ + return DateTimeToString(HAL_Time_CurrentDateTime(false)); +} + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks) +{ + return ((ticks * (uint64_t)TX_TIMER_TICKS_PER_SECOND) / 1000); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in new file mode 100644 index 0000000000..86d7716d84 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -0,0 +1,33 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_PLATFORM_H +#define TARGET_PLATFORM_H + +#define NANOCLR_GRAPHICS @NANOCLR_GRAPHICS@ +#define NF_FEATURE_USE_SPIFFS @NF_FEATURE_USE_SPIFFS_OPTION@ +#define HAL_USE_RTC @HAL_USE_RTC_OPTION@ + +// // takes care of enabling the HAL subsystems required for API options +// #define HAL_USE_SPI @HAL_USE_SPI_OPTION@ +// #define HAL_USE_I2C @HAL_USE_I2C_OPTION@ +// #define HAL_USE_PWM @HAL_USE_PWM_OPTION@ +// #define HAL_USE_ADC @HAL_USE_ADC_OPTION@ +// #define HAL_USE_DAC @HAL_USE_DAC_OPTION@ +// #define HAL_USE_UART @HAL_USE_UART_OPTION@ +// #define HAL_USE_SDC @HAL_USE_SDC_OPTION@ +// #define HAL_USE_WDG @HAL_USE_WDG_OPTION@ +// #define HAL_USE_CAN @HAL_USE_CAN_OPTION@ +// #define HAL_NF_USE_STM32_CRC TRUE +// #define HAL_NF_USE_STM32_ONEWIRE @HAL_USE_STM32_ONEWIRE_OPTION@ +// #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSD_OPTION@ +// #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ + +#endif // TARGET_PLATFORM_H diff --git a/targets/AzureRTOS/_common/include/LaunchCLR.h b/targets/AzureRTOS/_common/include/LaunchCLR.h index a82dcb6f91..1c90bf5ae6 100644 --- a/targets/AzureRTOS/_common/include/LaunchCLR.h +++ b/targets/AzureRTOS/_common/include/LaunchCLR.h @@ -6,6 +6,8 @@ #ifndef LAUNCHCLR_H #define LAUNCHCLR_H +#include + void LaunchCLR(uint32_t address); bool CheckValidCLRImage(uint32_t address); From c0421aabe74d0f859b3973664ea25e8fa0eb91fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 1 Jun 2022 18:46:23 +0100 Subject: [PATCH 003/572] Initial work on adding Gecko SDK and EFM32GG11 target - Add CMakes for the new SDK. - Add config files for the new vendor. - Add new target. - Update existing CMakes to accommodate new vendor and SDK. --- .../AzureRTOS_SILABS_GG_S1_GCC_options.cmake | 69 ++++++ .../SiliconLabs/EFM32GG11/CMakeLists.txt | 36 +++ .../EFM32GG11/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 124 ++++++++++ .../EFM32GG11/common/Device_BlockStorage.c | 124 ++++++++++ .../SiliconLabs/EFM32GG11/launch.json | 115 +++++++++ .../EFM32GG11/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 229 ++++++++++++++++++ .../SiliconLabs/EFM32GG11/nanoBooter/main.c | 147 +++++++++++ .../EFM32GG11/nanoBooter/target_board.h.in | 18 ++ .../EFM32GG11/nanoCLR/CMakeLists.txt | 11 + .../EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 229 ++++++++++++++++++ .../SiliconLabs/EFM32GG11/nanoCLR/main.c | 132 ++++++++++ .../SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp | 8 + .../EFM32GG11/nanoCLR/target_board.h.in | 18 ++ .../EFM32GG11/target_BlockStorage.c | 19 ++ .../EFM32GG11/target_BlockStorage.h | 12 + .../SiliconLabs/EFM32GG11/target_common.c | 30 +++ .../SiliconLabs/EFM32GG11/target_common.h.in | 45 ++++ .../EFM32GG11/target_stdio_config.c | 15 ++ .../EFM32GG11/target_stdio_config.h | 11 + .../SiliconLabs/EFM32GG11/target_tx_user.h | 206 ++++++++++++++++ 22 files changed, 1618 insertions(+) create mode 100644 CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h diff --git a/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake b/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake new file mode 100644 index 0000000000..b832f51c96 --- /dev/null +++ b/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake @@ -0,0 +1,69 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") +set(CMAKE_C_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") +set(CMAKE_CXX_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs " CACHE INTERNAL "executable linker flags") + + +# TARGET parameter to set the target that's setting them for +# optional EXTRA_COMPILE_OPTIONS with compile options to be added +macro(nf_set_compile_options) + + # parse arguments + cmake_parse_arguments(NFSCO "" "TARGET" "EXTRA_COMPILE_OPTIONS" ${ARGN}) + + if(NOT NFSCO_TARGET OR "${NFSCO_TARGET}" STREQUAL "") + message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_compile_options()") + endif() + + # include any extra options coming from any extra args? + # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # enable: + # - FPU + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX) + +endmacro() + + +# TARGET parameter to set the target that's setting them for +# optional EXTRA_LINK_FLAGS with link flags to be added +macro(nf_set_link_options) + + # parse arguments + cmake_parse_arguments(NFSLO "" "TARGET;EXTRA_LINK_FLAGS" "" ${ARGN}) + + if(NOT NFSLO_TARGET OR "${NFSLO_TARGET}" STREQUAL "") + message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_link_options()") + endif() + + # request specs from newlib nano + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs --specs=nosys.specs") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # include libraries in build + nf_include_libraries_in_build(${NFSLO_TARGET}) + + # set extra linker flags + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${NFSLO__EXTRA_LINK_FLAGS} ") + + # set optimization flags + nf_set_optimization_options(${NFSLO_TARGET}) + +endmacro() diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt new file mode 100644 index 0000000000..6f0d4f04ca --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt @@ -0,0 +1,36 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +# set(STM32_DRIVER_TARGET_DEVICE STM32L475xx CACHE BOOL "Set STM32 target for HAL Driver") + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + # BOOTER_EXTRA_LINKMAP_PROPERTIES + # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x4000" + + # CLR_EXTRA_LINKMAP_PROPERTIES + # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x2000" +) + +# make vars global +set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..39d1668d73 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,124 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 08000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, + + // 08008000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 16, 237}, + + // 08077000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 509}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 080FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + // STM32L4 flash requires 64bits width programming + (BlockRegionAttribute_ProgramWidthIs64bits), + + // start address for block region + 0x08000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x800, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c new file mode 100644 index 0000000000..c52a00f600 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c @@ -0,0 +1,124 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 08000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, + + // 08008000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 16, 158}, + + // 0804F800 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 080FF800 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + // STM32L4 flash requires 64bits width programming + (BlockRegionAttribute_ProgramWidthIs64bits), + + // start address for block region + 0x08000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x800, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json b/targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json new file mode 100644 index 0000000000..9bacbe281d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json @@ -0,0 +1,115 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "ST_B_L475E_IOT01A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "targetArchitecture": "ARM", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoBooter.hex\" " + }, + { + "text": "file /build/nanoBooter.elf" + }, + { + "text": "monitor reset halt" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": false + } + ], + "customLaunchSetupCommands": [ + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" + }, + { + "name": "ST_B_L475E_IOT01A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "targetArchitecture": "ARM", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "setupCommands": [ + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + }, + { + "text": "monitor flash write_image erase \"/build/nanoCLR.hex\" " + }, + { + "text": "file /build/nanoCLR.elf" + }, + { + "text": "monitor reset halt" + }, + { + "text": "set output-radix 16", + "description": "set the default numeric base to 16", + "ignoreFailures": false + } + ], + "customLaunchSetupCommands": [ + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + } + ], + "logging": { + "moduleLoad": false, + "trace": false, + "engineLogging": false, + "programOutput": true, + "exceptions": true + }, + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..d547592f88 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,229 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c new file mode 100644 index 0000000000..f56cc17fab --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c @@ -0,0 +1,147 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#include +#include +#include +#include + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + // palTogglePad(GPIOB, GPIOB_LD2); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // starts the serial driver + // sdStart(&SERIAL_DRIVER, NULL); + +// #if (HAL_NF_USE_STM32_CRC == TRUE) +// // startup crc +// crcStart(NULL); +// #endif + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + //halInit(); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // // check if there is a request to remain on nanoBooter + // if (!IsToRemainInBooter()) + // { + // // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) + // { + // // check for valid CLR image + // // we are checking for a valid image at the deployment address, which is pointing to the CLR address + // if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + // { + // // there seems to be a valid CLR image + // // launch nanoCLR + // LaunchCLR((uint32_t)&__deployment_start__); + // } + // } + // } + + // Enter the ThreadX kernel + tx_kernel_enter(); +} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..3eee9275ee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..d547592f88 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,229 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c new file mode 100644 index 0000000000..48e004773f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c @@ -0,0 +1,132 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// #include +// #include + +// #include + +// #include +// #include +// #include +// #include +// #include +// #include +// #include +// #include +// #include + +// extern TX_EVENT_FLAGS_GROUP wpUartEvent; +// extern CLR_SETTINGS clrSettings; + +// // byte pool configuration and definitions +// // need to be at least as big as the config sector +// #define DEFAULT_BYTE_POOL_SIZE 0x2000 +// TX_BYTE_POOL byte_pool_0; +// uint8_t __attribute__((section(".ram4"))) memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// // threads definitions and configurations + +// // receiver thread +// #define RECEIVER_THREAD_STACK_SIZE 2048 +// #define RECEIVER_THREAD_PRIORITY 5 + +// TX_THREAD receiverThread; +// uint32_t __attribute__((section(".ram4"))) receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +// extern void ReceiverThread_entry(uint32_t parameter); + +// // CLR thread +// #define CLR_THREAD_STACK_SIZE 4092 +// #define CLR_THREAD_PRIORITY 5 + +// TX_THREAD clrStartupThread; +// uint32_t __attribute__((section(".ram4"))) clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +// extern void ClrStartupThread_entry(uint32_t parameter); + +// void tx_application_define(void *first_unused_memory) +// { +// (void)first_unused_memory; +// uint16_t status; + +// // Create a byte memory pool from which to allocate the thread stacks. +// tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + +// // start watchdog +// Watchdog_Init(); + +// // turn LED2 off +// palClearPad(GPIOB, GPIOB_LD2); + +// #if (HAL_NF_USE_STM32_CRC == TRUE) +// // startup crc +// crcStart(NULL); +// #endif + +// // starts the serial driver +// sdStart(&SERIAL_DRIVER, NULL); + +// #if (TRACE_TO_STDIO == TRUE) +// StdioPort_Init(); +// #endif + +// // Create receiver thread +// status = tx_thread_create( +// &receiverThread, +// "Receiver Thread", +// ReceiverThread_entry, +// 0, +// receiverThreadStack, +// RECEIVER_THREAD_STACK_SIZE, +// RECEIVER_THREAD_PRIORITY, +// RECEIVER_THREAD_PRIORITY, +// TX_NO_TIME_SLICE, +// TX_AUTO_START); + +// if (status != TX_SUCCESS) +// { +// while (1) +// { +// } +// } + +// // CLR settings to launch CLR thread +// memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + +// clrSettings.MaxContextSwitches = 50; +// clrSettings.WaitForDebugger = false; +// clrSettings.EnterDebuggerLoopAfterExit = true; + +// // Create CLR startup thread +// status = tx_thread_create( +// &clrStartupThread, +// "CLR Thread", +// ClrStartupThread_entry, +// (uint32_t)&clrSettings, +// clrStartupThreadStack, +// CLR_THREAD_STACK_SIZE, +// CLR_THREAD_PRIORITY, +// CLR_THREAD_PRIORITY, +// TX_NO_TIME_SLICE, +// TX_AUTO_START); + +// if (status != TX_SUCCESS) +// { +// while (1) +// { +// } +// } +// } + +// // Application entry point. +// int main(void) +// { +// halInit(); + +// // init boot clipboard +// InitBootClipboard(); + +// // Enter the ThreadX kernel +// tx_kernel_enter(); +// } diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c new file mode 100644 index 0000000000..e0e9fe93fc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// extern struct BlockStorageDevice Device_BlockStorage; +// extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +// extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +// void BlockStorage_AddDevices() +// { +// BlockStorageList_AddDevice( +// (BlockStorageDevice *)&Device_BlockStorage, +// &STM32Flash_BlockStorageInterface, +// &Device_BlockStorageConfig, +// false); +// } diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c new file mode 100644 index 0000000000..0635f76a6c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c @@ -0,0 +1,30 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0,//ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use JTAG for updates +// TODO +// inline GET_TARGET_CAPABILITIES(TargetCapabilities_JtagUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(true); diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in new file mode 100644 index 0000000000..f62324c82a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in @@ -0,0 +1,45 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x10000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00008000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c new file mode 100644 index 0000000000..457394d46b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// // pin configuration for stdio using UART4 +// // port for TX pin is: GPIOA +// // port for RX pin is: GPIOA +// // TX pin: is GPIOA_0 +// // RX pin: is GPIOA_1 +// // GPIO alternate pin function is 8 see alternate function mapping ST datasheet +// STDIO_UART_CONFIG_PINS(GPIOA, GPIOA, 0, 1, 8) diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h new file mode 100644 index 0000000000..d5df942106 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// Select which STM32 uart/serial port used. +// If you change STDIO_SERIAL_DRIVER here to another UARTn, also +// edit mcuconf.h to set #define STM32_SERIAL_USE_UARTn TRUE +// and edit GPIO pins defined in target_stdio_config.c +// #define STDIO_SERIAL_DRIVER SD4 diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif From 62791e06d13912f1b55b3e79173e69524a00d84c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 2 Jun 2022 10:16:52 +0100 Subject: [PATCH 004/572] More work on SL_STK3701A - Add TX low level init for target. - Work on CMake for SDK. - Remove old target folder. - Fix file name. --- ... => AzureRTOS_EFM32GG11_GCC_options.cmake} | 0 .../Modules/AzureRTOS_EFM32GG11_sources.cmake | 8 + CMake/Modules/Gecko_SDK.cmake | 49 +++- .../SiliconLabs/EFM32GG11/CMakeLists.txt | 36 --- .../EFM32GG11/common/CMakeLists.txt | 10 - .../common/Device_BlockStorage-DEBUG.c | 124 --------- .../EFM32GG11/common/Device_BlockStorage.c | 124 --------- .../SiliconLabs/EFM32GG11/launch.json | 115 --------- .../EFM32GG11/nanoBooter/CMakeLists.txt | 10 - .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 229 ----------------- .../SiliconLabs/EFM32GG11/nanoBooter/main.c | 147 ----------- .../EFM32GG11/nanoBooter/target_board.h.in | 18 -- .../EFM32GG11/nanoCLR/CMakeLists.txt | 11 - .../EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 229 ----------------- .../SiliconLabs/EFM32GG11/nanoCLR/main.c | 132 ---------- .../SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp | 8 - .../EFM32GG11/nanoCLR/target_board.h.in | 18 -- .../EFM32GG11/target_BlockStorage.c | 19 -- .../EFM32GG11/target_BlockStorage.h | 12 - .../SiliconLabs/EFM32GG11/target_common.c | 30 --- .../SiliconLabs/EFM32GG11/target_common.h.in | 45 ---- .../EFM32GG11/target_stdio_config.c | 15 -- .../EFM32GG11/target_stdio_config.h | 11 - .../SiliconLabs/EFM32GG11/target_tx_user.h | 206 --------------- .../common/tx_initialize_low_level.S | 239 ++++++++++++++++++ 25 files changed, 282 insertions(+), 1563 deletions(-) rename CMake/Modules/{AzureRTOS_EFM32GG1_GCC_options.cmake => AzureRTOS_EFM32GG11_GCC_options.cmake} (100%) create mode 100644 CMake/Modules/AzureRTOS_EFM32GG11_sources.cmake delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h delete mode 100644 targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S diff --git a/CMake/Modules/AzureRTOS_EFM32GG1_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake similarity index 100% rename from CMake/Modules/AzureRTOS_EFM32GG1_GCC_options.cmake rename to CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_sources.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_sources.cmake new file mode 100644 index 0000000000..c17262b642 --- /dev/null +++ b/CMake/Modules/AzureRTOS_EFM32GG11_sources.cmake @@ -0,0 +1,8 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +################################# +# This file is empty on purpose # +################################# diff --git a/CMake/Modules/Gecko_SDK.cmake b/CMake/Modules/Gecko_SDK.cmake index 563ea3664a..0f1f9feb88 100644 --- a/CMake/Modules/Gecko_SDK.cmake +++ b/CMake/Modules/Gecko_SDK.cmake @@ -9,13 +9,7 @@ include(FetchContent) function(nf_set_silabs_target_series) - # process target series, which is in the format "SILABS_xxxxx" - string(REPLACE "SILABS" "" TARGET_SERIES_SHORT "${TARGET_SERIES}") - - # store the series name for later use - set(TARGET_SERIES_SHORT ${TARGET_SERIES_SHORT} CACHE INTERNAL "Silabs series short name") - - if("${TARGET_SERIES}" STREQUAL "EFM32GG1") + if("${TARGET_SERIES}" STREQUAL "EFM32GG11") # WHEN CHANGING THESE MAKE SURE TO UPDATE THE DEV CONTAINERS # set(HAL_DRIVER_GIT_TAG v1.7.6) # set(CMSIS_DEVICE_GIT_TAG v2.3.6) @@ -28,21 +22,48 @@ endfunction() # check if cube package source was specified or if it's empty (default is empty) -macro(nf_process_gecko_sdk) +macro(nf_add_gecko_sdk) FetchContent_GetProperties(gecko_sdk) + # set include directories + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Include) + # general files #series specific files if("${TARGET_SERIES}" STREQUAL "EFM32GG1") - set(GECKO_SDK_SRCS - - # RT - chcore.c - chcoreasm.S - ) + set(GECKO_SDK_SRCS + system_efm32gg11b.c + startup_efm32gg11b.c + startup_efm32gg11b.S + ) + + foreach(SRC_FILE ${GECKO_SDK_SRCS}) + + set(GECKO_SDK_SRCS_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(GECKO_SDK_SRCS_SRC_FILE ${SRC_FILE} + PATHS + + ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source + ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source/GCC + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${GECKO_SDK_SRCS_SRC_FILE}") + endif() + + list(APPEND Gecko_SDK_SOURCES ${GECKO_SDK_SRCS_SRC_FILE}) + + endforeach() + + list(REMOVE_DUPLICATES GECKO_SDK_SRCS_INCLUDE_DIRS) + + include(FindPackageHandleStandardArgs) endif() diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt deleted file mode 100644 index 6f0d4f04ca..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/CMakeLists.txt +++ /dev/null @@ -1,36 +0,0 @@ - -include(FetchContent) -include(binutils.common) -include(binutils.AzureRTOS) -include(AzureRTOS_${TARGET_SERIES}_GCC_options) - -# Azure RTOS settings and inclusion of build system -set(THREADX_ARCH "cortex_m4" ) -set(THREADX_TOOLCHAIN "gnu" ) -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") -# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") -# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") - -# set(STM32_DRIVER_TARGET_DEVICE STM32L475xx CACHE BOOL "Set STM32 target for HAL Driver") - -add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) -# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) - -nf_setup_target_build( - HAS_NANOBOOTER - - BOOTER_LINKER_FILE - efm32gg11b_booter - - CLR_LINKER_FILE - efm32gg11b_CLR - - # BOOTER_EXTRA_LINKMAP_PROPERTIES - # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x4000" - - # CLR_EXTRA_LINKMAP_PROPERTIES - # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x2000" -) - -# make vars global -set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt deleted file mode 100644 index 8ea7907f60..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append common source files -list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) - -# make var global -set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c deleted file mode 100644 index 39d1668d73..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage-DEBUG.c +++ /dev/null @@ -1,124 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 08000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, - - // 08008000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 16, 237}, - - // 08077000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 509}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 080FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - // STM32L4 flash requires 64bits width programming - (BlockRegionAttribute_ProgramWidthIs64bits), - - // start address for block region - 0x08000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x800, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c deleted file mode 100644 index c52a00f600..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/common/Device_BlockStorage.c +++ /dev/null @@ -1,124 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 08000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, - - // 08008000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 16, 158}, - - // 0804F800 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 080FF800 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - // STM32L4 flash requires 64bits width programming - (BlockRegionAttribute_ProgramWidthIs64bits), - - // start address for block region - 0x08000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x800, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json b/targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json deleted file mode 100644 index 9bacbe281d..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/launch.json +++ /dev/null @@ -1,115 +0,0 @@ -{ - "version": "0.2.0", - "configurations": [ - { - "name": "ST_B_L475E_IOT01A nanoBooter", - "type": "cppdbg", - "request": "launch", - "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "targetArchitecture": "ARM", - "program": "${workspaceRoot}/build/nanoBooter.elf", - "setupCommands": [ - { - "text": "target extended-remote localhost:3333" - }, - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - }, - { - "text": "monitor flash write_image erase \"/build/nanoBooter.hex\" " - }, - { - "text": "file /build/nanoBooter.elf" - }, - { - "text": "monitor reset halt" - }, - { - "text": "set output-radix 16", - "description": "set the default numeric base to 16", - "ignoreFailures": false - } - ], - "customLaunchSetupCommands": [ - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - } - ], - "logging": { - "moduleLoad": false, - "trace": false, - "engineLogging": false, - "programOutput": true, - "exceptions": true - }, - "launchCompleteCommand": "exec-continue", - "debugServerPath": "/bin/openocd.exe", - "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", - "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", - "filterStderr": true, - "externalConsole": true, - "cwd": "${cwd}" - }, - { - "name": "ST_B_L475E_IOT01A nanoCLR", - "type": "cppdbg", - "request": "launch", - "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "targetArchitecture": "ARM", - "program": "${workspaceRoot}/build/nanoCLR.elf", - "setupCommands": [ - { - "text": "target extended-remote localhost:3333" - }, - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - }, - { - "text": "monitor flash write_image erase \"/build/nanoCLR.hex\" " - }, - { - "text": "file /build/nanoCLR.elf" - }, - { - "text": "monitor reset halt" - }, - { - "text": "set output-radix 16", - "description": "set the default numeric base to 16", - "ignoreFailures": false - } - ], - "customLaunchSetupCommands": [ - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - } - ], - "logging": { - "moduleLoad": false, - "trace": false, - "engineLogging": false, - "programOutput": true, - "exceptions": true - }, - "launchCompleteCommand": "exec-continue", - "debugServerPath": "/bin/openocd.exe", - "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", - "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", - "filterStderr": true, - "externalConsole": true, - "cwd": "${cwd}" - } - ] -} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt deleted file mode 100644 index 0b7c048e56..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoBooter source files -list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) - -# make var global -set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld deleted file mode 100644 index d547592f88..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c deleted file mode 100644 index f56cc17fab..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/main.c +++ /dev/null @@ -1,147 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -#include -#include -#include -#include - -// byte pool configuration and definitions -#define DEFAULT_BYTE_POOL_SIZE 4096 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// blink thread -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - // palTogglePad(GPIOB, GPIOB_LD2); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // starts the serial driver - // sdStart(&SERIAL_DRIVER, NULL); - -// #if (HAL_NF_USE_STM32_CRC == TRUE) -// // startup crc -// crcStart(NULL); -// #endif - - // initialize block storage list and devices - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - BlockStorageList_Initialize(); - BlockStorage_AddDevices(); - - // initialize configuration manager - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it here to have access to network configuration blocks - ConfigurationManager_Initialize(); - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // report successfull nanoBooter execution - ReportSuccessfullNanoBooter(); -} - -// Application entry point. -int main(void) -{ - //halInit(); - - // init boot clipboard - InitBootClipboard(); - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - - // // check if there is a request to remain on nanoBooter - // if (!IsToRemainInBooter()) - // { - // // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter - // if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) - // { - // // check for valid CLR image - // // we are checking for a valid image at the deployment address, which is pointing to the CLR address - // if (CheckValidCLRImage((uint32_t)&__deployment_start__)) - // { - // // there seems to be a valid CLR image - // // launch nanoCLR - // LaunchCLR((uint32_t)&__deployment_start__); - // } - // } - // } - - // Enter the ThreadX kernel - tx_kernel_enter(); -} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in deleted file mode 100644 index ec5e9be940..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoBooter/target_board.h.in +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOBOOTER_H_ -#define _TARGET_BOARD_NANOBOOTER_H_ - -#include - -#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" - -#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt deleted file mode 100644 index 3eee9275ee..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoCLR source files -list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) -list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) - -# make var global -set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld deleted file mode 100644 index d547592f88..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") -} diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c deleted file mode 100644 index 48e004773f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/main.c +++ /dev/null @@ -1,132 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// #include -// #include - -// #include - -// #include -// #include -// #include -// #include -// #include -// #include -// #include -// #include -// #include - -// extern TX_EVENT_FLAGS_GROUP wpUartEvent; -// extern CLR_SETTINGS clrSettings; - -// // byte pool configuration and definitions -// // need to be at least as big as the config sector -// #define DEFAULT_BYTE_POOL_SIZE 0x2000 -// TX_BYTE_POOL byte_pool_0; -// uint8_t __attribute__((section(".ram4"))) memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// // threads definitions and configurations - -// // receiver thread -// #define RECEIVER_THREAD_STACK_SIZE 2048 -// #define RECEIVER_THREAD_PRIORITY 5 - -// TX_THREAD receiverThread; -// uint32_t __attribute__((section(".ram4"))) receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -// extern void ReceiverThread_entry(uint32_t parameter); - -// // CLR thread -// #define CLR_THREAD_STACK_SIZE 4092 -// #define CLR_THREAD_PRIORITY 5 - -// TX_THREAD clrStartupThread; -// uint32_t __attribute__((section(".ram4"))) clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -// extern void ClrStartupThread_entry(uint32_t parameter); - -// void tx_application_define(void *first_unused_memory) -// { -// (void)first_unused_memory; -// uint16_t status; - -// // Create a byte memory pool from which to allocate the thread stacks. -// tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - -// // start watchdog -// Watchdog_Init(); - -// // turn LED2 off -// palClearPad(GPIOB, GPIOB_LD2); - -// #if (HAL_NF_USE_STM32_CRC == TRUE) -// // startup crc -// crcStart(NULL); -// #endif - -// // starts the serial driver -// sdStart(&SERIAL_DRIVER, NULL); - -// #if (TRACE_TO_STDIO == TRUE) -// StdioPort_Init(); -// #endif - -// // Create receiver thread -// status = tx_thread_create( -// &receiverThread, -// "Receiver Thread", -// ReceiverThread_entry, -// 0, -// receiverThreadStack, -// RECEIVER_THREAD_STACK_SIZE, -// RECEIVER_THREAD_PRIORITY, -// RECEIVER_THREAD_PRIORITY, -// TX_NO_TIME_SLICE, -// TX_AUTO_START); - -// if (status != TX_SUCCESS) -// { -// while (1) -// { -// } -// } - -// // CLR settings to launch CLR thread -// memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - -// clrSettings.MaxContextSwitches = 50; -// clrSettings.WaitForDebugger = false; -// clrSettings.EnterDebuggerLoopAfterExit = true; - -// // Create CLR startup thread -// status = tx_thread_create( -// &clrStartupThread, -// "CLR Thread", -// ClrStartupThread_entry, -// (uint32_t)&clrSettings, -// clrStartupThreadStack, -// CLR_THREAD_STACK_SIZE, -// CLR_THREAD_PRIORITY, -// CLR_THREAD_PRIORITY, -// TX_NO_TIME_SLICE, -// TX_AUTO_START); - -// if (status != TX_SUCCESS) -// { -// while (1) -// { -// } -// } -// } - -// // Application entry point. -// int main(void) -// { -// halInit(); - -// // init boot clipboard -// InitBootClipboard(); - -// // Enter the ThreadX kernel -// tx_kernel_enter(); -// } diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp deleted file mode 100644 index e754dd5f80..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/nanoHAL.cpp +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in deleted file mode 100644 index be11ba01ad..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/nanoCLR/target_board.h.in +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOCLR_H_ -#define _TARGET_BOARD_NANOCLR_H_ - -#include - -#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" - -#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c deleted file mode 100644 index e0e9fe93fc..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.c +++ /dev/null @@ -1,19 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -// extern struct BlockStorageDevice Device_BlockStorage; -// extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; -// extern IBlockStorageDevice STM32Flash_BlockStorageInterface; - -// void BlockStorage_AddDevices() -// { -// BlockStorageList_AddDevice( -// (BlockStorageDevice *)&Device_BlockStorage, -// &STM32Flash_BlockStorageInterface, -// &Device_BlockStorageConfig, -// false); -// } diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h deleted file mode 100644 index 0771bccc7b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_BlockStorage.h +++ /dev/null @@ -1,12 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef _TARGETPAL_BLOCKSTORAGE_H_ -#define _TARGETPAL_BLOCKSTORAGE_H_ 1 - -// this device has 1 block storage devices -#define TARGET_BLOCKSTORAGE_COUNT 1 - -#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c deleted file mode 100644 index 0635f76a6c..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.c +++ /dev/null @@ -1,30 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include -#include "target_board.h" -#include "target_common.h" -#include - -HAL_SYSTEM_CONFIG HalSystemConfig = -{ - { true }, // HAL_DRIVER_CONFIG_HEADER Header; - - 1, //ConvertCOM_DebugHandle(1), - 0,//ConvertCOM_DebugHandle(0), - 921600, - 0, // STDIO = COM2 or COM1 - - { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, - { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } -}; - -HAL_TARGET_CONFIGURATION g_TargetConfiguration; - -// this target can use JTAG for updates -// TODO -// inline GET_TARGET_CAPABILITIES(TargetCapabilities_JtagUpdate); -inline TARGET_HAS_PROPRIETARY_BOOTER(true); diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in deleted file mode 100644 index f62324c82a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_common.h.in +++ /dev/null @@ -1,45 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_COMMON_H_ -#define _TARGET_COMMON_H_ - -#include - -///////////////////////////////////////////////////////////////////////////////////////// -// The following addresses and sizes should be filled in according to the SoC data-sheet -// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR - -// RAM base address -#define RAM1_MEMORY_StartAddress ((uint32_t)0x10000000) -// RAM size -#define RAM1_MEMORY_Size ((uint32_t)0x00008000) - -// FLASH base address -#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) -// FLASH size -#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) - -///////////////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////// -#define TARGETNAMESTRING "@TARGET_NAME@" -#define PLATFORMNAMESTRING "GGECKO_S1" -////////////////////////////////////////////// - -///////////////////////////////////// -#define PLATFORM_HAS_RNG TRUE -///////////////////////////////////// - -///////////////////////////////////// -//#define EVENTS_HEART_BEAT -///////////////////////////////////// - -#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c deleted file mode 100644 index 457394d46b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.c +++ /dev/null @@ -1,15 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include - -// // pin configuration for stdio using UART4 -// // port for TX pin is: GPIOA -// // port for RX pin is: GPIOA -// // TX pin: is GPIOA_0 -// // RX pin: is GPIOA_1 -// // GPIO alternate pin function is 8 see alternate function mapping ST datasheet -// STDIO_UART_CONFIG_PINS(GPIOA, GPIOA, 0, 1, 8) diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h deleted file mode 100644 index d5df942106..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_stdio_config.h +++ /dev/null @@ -1,11 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -// Select which STM32 uart/serial port used. -// If you change STDIO_SERIAL_DRIVER here to another UARTn, also -// edit mcuconf.h to set #define STM32_SERIAL_USE_UARTn TRUE -// and edit GPIO pins defined in target_stdio_config.c -// #define STDIO_SERIAL_DRIVER SD4 diff --git a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h deleted file mode 100644 index 40c92111ed..0000000000 --- a/targets/AzureRTOS/SiliconLabs/EFM32GG11/target_tx_user.h +++ /dev/null @@ -1,206 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////// -// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file -// for nanoBooter and another for nanoCLR. -/////////////////////////////////////////////////////////////////////////////////////////// - -#ifndef TX_USER_H -#define TX_USER_H - -#define TX_TIMER_TICKS_PER_SECOND 1000 - -/* Define various build options for the ThreadX port. The application should either make changes - here by commenting or un-commenting the conditional compilation defined OR supply the defines - though the compiler's equivalent of the -D option. - - For maximum speed, the following should be defined: - - TX_MAX_PRIORITIES 32 - TX_DISABLE_PREEMPTION_THRESHOLD - TX_DISABLE_REDUNDANT_CLEARING - TX_DISABLE_NOTIFY_CALLBACKS - TX_NOT_INTERRUPTABLE - TX_TIMER_PROCESS_IN_ISR - TX_REACTIVATE_INLINE - TX_DISABLE_STACK_FILLING - TX_INLINE_THREAD_RESUME_SUSPEND - - For minimum size, the following should be defined: - - TX_MAX_PRIORITIES 32 - TX_DISABLE_PREEMPTION_THRESHOLD - TX_DISABLE_REDUNDANT_CLEARING - TX_DISABLE_NOTIFY_CALLBACKS - TX_NOT_INTERRUPTABLE - TX_TIMER_PROCESS_IN_ISR - - Of course, many of these defines reduce functionality and/or change the behavior of the - system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR - results in faster and smaller code, however, it increases the amount of processing in the ISR. - In addition, some services that are available in timers are not available from ISRs and will - therefore return an error if this option is used. This may or may not be desirable for a - given application. */ - -/* Override various options with default values already assigned in tx_port.h. Please also refer - to tx_port.h for descriptions on each of these options. */ - -/* -#define TX_MAX_PRIORITIES 32 -#define TX_MINIMUM_STACK ???? -#define TX_THREAD_USER_EXTENSION ???? -#define TX_TIMER_THREAD_STACK_SIZE ???? -#define TX_TIMER_THREAD_PRIORITY ???? -*/ - -/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls - should be processed within the a system timer thread or directly in the timer ISR. - By default, the timer thread is used. When the following is defined, the timer expiration - processing is done directly from the timer ISR, thereby eliminating the timer thread control - block, stack, and context switching to activate it. */ - -/* -#define TX_TIMER_PROCESS_IN_ISR -*/ - -/* Determine if in-line timer reactivation should be used within the timer expiration processing. - By default, this is disabled and a function call is used. When the following is defined, - reactivating is performed in-line resulting in faster timer processing but slightly larger - code size. */ - -#define TX_REACTIVATE_INLINE - -/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, - which places an 0xEF pattern in each byte of each thread's stack. This is used by - debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ - -/* -#define TX_DISABLE_STACK_FILLING -*/ - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -/* -#define TX_ENABLE_STACK_CHECKING -*/ - -/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is - enabled. If the application does not use preemption-threshold, it may be disabled to reduce - code size and improve performance. */ - -/* -#define TX_DISABLE_PREEMPTION_THRESHOLD -*/ - -/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears - the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary - clearing of ThreadX global variables. */ - -#define TX_DISABLE_REDUNDANT_CLEARING - -/* Determine if no timer processing is required. This option will help eliminate the timer - processing when not needed. The user will also have to comment out the call to - tx_timer_interrupt, which is typically made from assembly language in - tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR - must also be used. */ - -/* -#define TX_NO_TIMER -#ifndef TX_TIMER_PROCESS_IN_ISR -#define TX_TIMER_PROCESS_IN_ISR -#endif -*/ - -/* Determine if the notify callback option should be disabled. By default, notify callbacks are - enabled. If the application does not use notify callbacks, they may be disabled to reduce - code size and improve performance. */ - -#define TX_DISABLE_NOTIFY_CALLBACKS - -/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal - code in-line. This results in a larger image, but improves the performance of the thread - resume and suspend services. */ - -/* -#define TX_INLINE_THREAD_RESUME_SUSPEND -*/ - -/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code - size and less processing overhead, but increases the interrupt lockout time. */ - -/* -#define TX_NOT_INTERRUPTABLE -*/ - -/* Determine if the trace event logging code should be enabled. This causes slight increases in - code size and overhead, but provides the ability to generate system trace information which - is available for viewing in TraceX. */ - -/* -#define TX_ENABLE_EVENT_TRACE -*/ - -/* Determine if block pool performance gathering is required by the application. When the following is - defined, ThreadX gathers various block pool performance information. */ - -/* -#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if byte pool performance gathering is required by the application. When the following is - defined, ThreadX gathers various byte pool performance information. */ - -/* -#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if event flags performance gathering is required by the application. When the following is - defined, ThreadX gathers various event flags performance information. */ - -/* -#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if mutex performance gathering is required by the application. When the following is - defined, ThreadX gathers various mutex performance information. */ - -/* -#define TX_MUTEX_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if queue performance gathering is required by the application. When the following is - defined, ThreadX gathers various queue performance information. */ - -/* -#define TX_QUEUE_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if semaphore performance gathering is required by the application. When the following is - defined, ThreadX gathers various semaphore performance information. */ - -/* -#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if thread performance gathering is required by the application. When the following is - defined, ThreadX gathers various thread performance information. */ - -/* -#define TX_THREAD_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if timer performance gathering is required by the application. When the following is - defined, ThreadX gathers various timer performance information. */ - -/* -#define TX_TIMER_ENABLE_PERFORMANCE_INFO -*/ - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..ef21b2660d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler From 4711ccfa9a0154dd7ea2073955f4813466d41ad3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 2 Jun 2022 10:42:35 +0100 Subject: [PATCH 005/572] Rework inclusion of vendor and target folders --- targets/AzureRTOS/CMakeLists.txt | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index 8739565215..22ceff22b9 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -372,10 +372,7 @@ elseif(EXISTS ${PROJECT_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/${TARGET_BOARD # set target base location set(TARGET_BASE_LOCATION ${PROJECT_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/${TARGET_BOARD}) - add_subdirectory(SiliconLabs) - - # add TARGET board directory - add_subdirectory(SiliconLabs/${TARGET_BOARD}) + set(TARGET_VENDOR SiliconLabs) else() From b3a2311454a263408e361216a2edb13518ff24f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 2 Jun 2022 16:33:42 +0100 Subject: [PATCH 006/572] More work on integrating Gecko SDK in the build system --- .../AzureRTOS_EFM32GG11_GCC_options.cmake | 11 +- CMake/Modules/FindGecko_SDK.cmake | 211 +++++ CMake/Modules/Gecko_SDK.cmake | 102 --- CMake/binutils.AzureRTOS.cmake | 34 +- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 5 +- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 14 + .../autogen/sl_simple_led_instances.c | 63 ++ .../autogen/sl_simple_led_instances.h | 33 + .../SL_STK3701A/autogen/sl_uartdrv_init.c | 91 +++ .../autogen/sl_uartdrv_instances.h | 35 + .../common/tx_initialize_low_level.S | 2 +- .../config/sl_board_control_config.h | 82 ++ .../config/sl_iostream_usart_vcom_config.h | 112 +++ .../config/sl_simple_led_led0_config.h | 44 + .../config/sl_simple_led_led1_config.h | 44 + .../config/sl_uartdrv_usart_vcom_config.h | 107 +++ .../SL_STK3701A/config/uartdrv_config.h | 114 +++ .../SiliconLabs/SL_STK3701A/launch.json | 146 ++-- .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 8 + .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 66 +- .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 12 +- .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 28 +- .../SiliconLabs/_common/CMakeLists.txt | 38 + .../_common/WireProtocol_HAL_Interface.c | 76 ++ .../_common/autogen/RTE_Components.h | 16 + .../autogen/sl_board_default_init_stub.c | 13 + .../_common/autogen/sl_component_catalog.h | 17 + .../_common/autogen/sl_device_init_clocks.c | 26 + .../_common/autogen/sl_event_handler.c | 91 +++ .../_common/autogen/sl_event_handler.h | 22 + .../_common/autogen/sl_i2cspm_init.c | 42 + .../_common/autogen/sl_i2cspm_instances.h | 28 + .../_common/autogen/sl_iostream_handles.c | 27 + .../_common/autogen/sl_iostream_handles.h | 20 + .../autogen/sl_iostream_init_instances.h | 16 + .../sl_iostream_init_usart_instances.c | 208 +++++ .../sl_iostream_init_usart_instances.h | 34 + .../_common/config/dmadrv_config.h | 26 + .../_common/config/emlib_core_debug_config.h | 46 ++ .../SiliconLabs/_common/config/pin_config.h | 252 ++++++ .../config/sl_device_init_dcdc_config.h | 28 + .../config/sl_device_init_emu_config.h | 68 ++ .../config/sl_device_init_hfxo_config.h | 39 + .../config/sl_device_init_lfxo_config.h | 37 + .../_common/config/sl_i2cspm_sensor_config.h | 59 ++ .../_common/config/sl_memlcd_usart_config.h | 35 + .../_common/config/sl_memory_config.h | 28 + .../_common/config/sl_power_manager_config.h | 70 ++ .../_common/config/sl_sleeptimer_config.h | 72 ++ .../targetHAL_ConfigurationManager.cpp | 764 ++++++++++++++++++ .../_common/WireProtocol_ReceiverThread.c | 2 +- 51 files changed, 3333 insertions(+), 231 deletions(-) create mode 100644 CMake/Modules/FindGecko_SDK.cmake create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/RTE_Components.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_board_default_init_stub.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/dmadrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/emlib_core_debug_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_dcdc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_emu_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_i2cspm_sensor_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_memlcd_usart_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_power_manager_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_sleeptimer_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index b832f51c96..f0a5421a1d 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -9,11 +9,11 @@ # need to specify this for assembler set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") -set(CMAKE_C_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") -set(CMAKE_CXX_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") +set(CMAKE_C_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") +set(CMAKE_CXX_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") # need to specify linker flags here -set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs " CACHE INTERNAL "executable linker flags") +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs " CACHE INTERNAL "executable linker flags") # TARGET parameter to set the target that's setting them for @@ -29,11 +29,12 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX) + # - DEBUG_EFM from Gecko SDK + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DDEBUG_EFM=1) endmacro() diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake new file mode 100644 index 0000000000..20958def53 --- /dev/null +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -0,0 +1,211 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) + +# include the Gecko HAL and CMSIS for the appropriate series +FetchContent_GetProperties(gecko_sdk) + +# set include directories +list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/config) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) + +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/board/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/Include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/RTOS2/Include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/device_init/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/common/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emlib/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/gpiointerrupt/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/iostream/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/power_manager/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/system/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/sleeptimer/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/leddrv/inc) + +list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) + +# general files +set(gecko_sdk_srcs + sl_board_control_gpio.c + sl_board_init.c + + sl_memory.c + + em_acmp.c + em_adc.c + em_assert.c + em_cmu.c + em_core.c + em_cryotimer.c + em_csen.c + em_emu.c + em_ldma.c + em_gpio.c + em_i2c.c + em_lcd.c + em_leuart.c + em_lesense.c + em_prs.c + em_rmu.c + em_rtc.c + em_rtcc.c + em_system.c + em_timer.c + em_usart.c + em_vdac.c + + # emdrv + dmadrv.c + uartdrv.c + gpiointerrupt.c + + sl_device_init_dcdc_s1.c + sl_device_init_emu_s1.c + sl_device_init_hfxo_s1.c + sl_device_init_lfxo_s1.c + sl_device_init_nvic.c + sl_power_manager.c + sl_power_manager_hal_s0_s1.c + sl_sleeptimer.c + sl_sleeptimer_hal_rtc.c + sl_sleeptimer_hal_rtcc.c + + sl_slist.c + sl_system_init.c + sl_system_kernel.c + sl_system_process_action.c + + sl_udelay.c + sl_udelay_armv6m_gcc.S + sl_uartdrv_init.c + sl_iostream_usart.c + sl_iostream_uart.c + sl_iostream.c + + sl_device_init_clocks.c + sl_event_handler.c + sl_board_default_init_stub.c + sl_i2cspm_init.c + sl_i2cspm.c + sl_iostream_handles.c + sl_iostream_init_usart_instances.c + + sl_led.c + sl_simple_led.c + + # autogen at target level + sl_simple_led_instances.c + +) + +#series specific files +if("${TARGET_SERIES}" STREQUAL "EFM32GG11") + + list(APPEND gecko_sdk_srcs system_efm32gg11b.c) + list(APPEND gecko_sdk_srcs startup_efm32gg11b.c) + + foreach(src_file ${gecko_sdk_srcs}) + + set(gecko_sdk_src_file src_file-NOTFOUND) + + find_file(gecko_sdk_src_file ${src_file} + PATHS + + # common paths + ${gecko_sdk_SOURCE_DIR}/hardware/board/src + ${gecko_sdk_SOURCE_DIR}/platform/common/src + ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/src + ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/src + ${gecko_sdk_SOURCE_DIR}/platform/emdrv/gpiointerrupt/src + ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/src + ${gecko_sdk_SOURCE_DIR}/platform/emlib/src + ${gecko_sdk_SOURCE_DIR}/platform/service/device_init/src + ${gecko_sdk_SOURCE_DIR}/platform/service/iostream/src + ${gecko_sdk_SOURCE_DIR}/platform/service/power_manager/src + ${gecko_sdk_SOURCE_DIR}/platform/service/sleeptimer/src + ${gecko_sdk_SOURCE_DIR}/platform/service/system/src + ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/src + ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/src + ${gecko_sdk_SOURCE_DIR}/platform/driver/leddrv/src + + # device specific paths + ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen + + # target series specific + ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source + ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source/GCC + + ${TARGET_BASE_LOCATION}/autogen + ${TARGET_BASE_LOCATION}/config + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${src_file} >> ${gecko_sdk_src_file}") + endif() + + list(APPEND Gecko_SDK_SOURCES ${gecko_sdk_src_file}) + + endforeach() + + list(REMOVE_DUPLICATES Gecko_SDK_INCLUDE_DIRS) + +else() + # series is NOT supported + message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") +endif() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Gecko_SDK DEFAULT_MSG Gecko_SDK_INCLUDE_DIRS Gecko_SDK_SOURCES) + +# macro to be called from binutils to add Gecko SDK as a library +# optional EXTRA_INCLUDES with include paths to be added to the library +# optional EXTRA_COMPILE_DEFINITIONS with compiler definitions to be added to the library +macro(nf_add_gecko_sdk) + + # parse arguments + cmake_parse_arguments(NFGCKSDK "" "BUILD_TARGET" "EXTRA_INCLUDES;EXTRA_COMPILE_DEFINITIONS" ${ARGN}) + + if("${NFGCKSDK_BUILD_TARGET}" STREQUAL "${NANOBOOTER_PROJECT_NAME}") + set(CONFIG_FILES_PATH "${TARGET_BASE_LOCATION}/nanoBooter") + elseif("${NFGCKSDK_BUILD_TARGET}" STREQUAL "${NANOCLR_PROJECT_NAME}") + set(CONFIG_FILES_PATH "${TARGET_BASE_LOCATION}/nanoCLR") + endif() + + # add THESE has a library + set(LIB_NAME gecko_sdk_${NFGCKSDK_BUILD_TARGET}) + + add_library( + ${LIB_NAME} STATIC + ${Gecko_SDK_SOURCES} + ) + + target_include_directories( + ${LIB_NAME} PUBLIC + + ${Gecko_SDK_INCLUDE_DIRS} + ${NFGCKSDK_EXTRA_INCLUDES} + ) + + nf_set_compile_options(TARGET ${LIB_NAME} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS ${NFGCKSDK_EXTRA_COMPILE_DEFINITIONS} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + nf_set_link_options(TARGET ${LIB_NAME}) + + # add alias + add_library("nano::${LIB_NAME}" ALIAS ${LIB_NAME}) + +endmacro() diff --git a/CMake/Modules/Gecko_SDK.cmake b/CMake/Modules/Gecko_SDK.cmake index 0f1f9feb88..f8dd2a9cc1 100644 --- a/CMake/Modules/Gecko_SDK.cmake +++ b/CMake/Modules/Gecko_SDK.cmake @@ -4,105 +4,3 @@ # include(FetchContent) - -# include the Gecko HAL and CMSIS for the appropriate series - -function(nf_set_silabs_target_series) - - if("${TARGET_SERIES}" STREQUAL "EFM32GG11") - # WHEN CHANGING THESE MAKE SURE TO UPDATE THE DEV CONTAINERS - # set(HAL_DRIVER_GIT_TAG v1.7.6) - # set(CMSIS_DEVICE_GIT_TAG v2.3.6) - else() - # series is NOT supported - message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") - endif() - -endfunction() - - -# check if cube package source was specified or if it's empty (default is empty) -macro(nf_add_gecko_sdk) - - FetchContent_GetProperties(gecko_sdk) - - # set include directories - list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Include) - - # general files - - #series specific files - if("${TARGET_SERIES}" STREQUAL "EFM32GG1") - - set(GECKO_SDK_SRCS - system_efm32gg11b.c - startup_efm32gg11b.c - startup_efm32gg11b.S - ) - - foreach(SRC_FILE ${GECKO_SDK_SRCS}) - - set(GECKO_SDK_SRCS_SRC_FILE SRC_FILE-NOTFOUND) - - find_file(GECKO_SDK_SRCS_SRC_FILE ${SRC_FILE} - PATHS - - ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source - ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source/GCC - - CMAKE_FIND_ROOT_PATH_BOTH - ) - - if (BUILD_VERBOSE) - message("${SRC_FILE} >> ${GECKO_SDK_SRCS_SRC_FILE}") - endif() - - list(APPEND Gecko_SDK_SOURCES ${GECKO_SDK_SRCS_SRC_FILE}) - - endforeach() - - list(REMOVE_DUPLICATES GECKO_SDK_SRCS_INCLUDE_DIRS) - - include(FindPackageHandleStandardArgs) - - endif() - -endmacro() - -# macro to be called from binutils to add Gecko SDK as a library -# optional EXTRA_INCLUDES with include paths to be added to the library -# optional EXTRA_COMPILE_DEFINITIONS with compiler definitions to be added to the library -macro(nf_add_gecko_sdk) - - # parse arguments - cmake_parse_arguments(NFGCKSDK "" "BUILD_TARGET" "EXTRA_INCLUDES;EXTRA_COMPILE_DEFINITIONS" ${ARGN}) - - if("${NFGCKSDK_BUILD_TARGET}" STREQUAL "${NANOBOOTER_PROJECT_NAME}") - set(CONFIG_FILES_PATH "${TARGET_BASE_LOCATION}/nanoBooter") - elseif("${NFGCKSDK_BUILD_TARGET}" STREQUAL "${NANOCLR_PROJECT_NAME}") - set(CONFIG_FILES_PATH "${TARGET_BASE_LOCATION}/nanoCLR") - endif() - - # add THESE has a library - set(LIB_NAME gecko_sdk) - - add_library( - ${LIB_NAME} STATIC - gecko_sdk_SOURCES - ) - - target_include_directories( - ${LIB_NAME} - PUBLIC - "gecko_sdk_INCLUDE_DIRS}" - ${NFGCKSDK_EXTRA_INCLUDES} - ) - - nf_set_compile_options(TARGET ${LIB_NAME} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) - nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS ${NFGCKSDK_EXTRA_COMPILE_DEFINITIONS} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) - nf_set_link_options(TARGET ${LIB_NAME}) - - # add alias - add_library("nano::${LIB_NAME}" ALIAS ${LIB_NAME}) - -endmacro() diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index 2fe0070b4a..cd32d7900b 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -133,7 +133,11 @@ macro(nf_add_platform_packages) if(STM32_CUBE_PACKAGE_REQUIRED) find_package(${TARGET_STM32_CUBE_PACKAGE}_CubePackage REQUIRED QUIET) endif() - + + if(SILABS_GECKO_SDK_REQUIRED) + find_package(Gecko_SDK REQUIRED QUIET) + endif() + # packages specific for nanoBooter if(NFAPP_TARGET STREQUAL ${NANOBOOTER_PROJECT_NAME}) # no packages for booter @@ -195,6 +199,7 @@ macro(nf_add_platform_dependencies target) ${NF_Network_INCLUDE_DIRS} ${CHIBIOS_CONTRIB_INCLUDE_DIRS} ${CHIBIOS_HAL_INCLUDE_DIRS} + ${Gecko_SDK_INCLUDE_DIRS} ${azure_rtos_SOURCE_DIR}/common/inc ${AZRTOS_INCLUDES} ) @@ -213,6 +218,7 @@ macro(nf_add_platform_dependencies target) ${TARGET_AZURERTOS_COMMON_INCLUDE_DIRS} ${CHIBIOS_CONTRIB_INCLUDE_DIRS} ${CHIBIOS_HAL_INCLUDE_DIRS} + ${Gecko_SDK_INCLUDE_DIRS} ${azure_rtos_SOURCE_DIR}/common/inc ${AZRTOS_INCLUDES} ) @@ -226,6 +232,7 @@ macro(nf_add_platform_dependencies target) ${TARGET_AZURERTOS_COMMON_INCLUDE_DIRS} ${CHIBIOS_CONTRIB_INCLUDE_DIRS} ${CHIBIOS_HAL_INCLUDE_DIRS} + ${Gecko_SDK_INCLUDE_DIRS} ${azure_rtos_SOURCE_DIR}/common/inc ${AZRTOS_INCLUDES} ) @@ -240,6 +247,7 @@ macro(nf_add_platform_dependencies target) ${ChibiOSnfOverlay_INCLUDE_DIRS} ${CHIBIOS_CONTRIB_INCLUDE_DIRS} ${CHIBIOS_HAL_INCLUDE_DIRS} + ${Gecko_SDK_INCLUDE_DIRS} ${azure_rtos_SOURCE_DIR}/common/inc ${NETXDUO_INCLUDES} ${TARGET_BASE_LOCATION} @@ -321,6 +329,12 @@ macro(nf_add_platform_include_directories target) ) endif() + if(SILABS_GECKO_SDK_REQUIRED) + target_include_directories(${target}.elf PUBLIC + ${Gecko_SDK_INCLUDE_DIRS} + ) + endif() + # includes specific to nanoBooter if(${target} STREQUAL ${NANOBOOTER_PROJECT_NAME}) @@ -424,6 +438,24 @@ macro(nf_add_platform_sources target) endif() + if(SILABS_GECKO_SDK_REQUIRED) + + nf_add_gecko_sdk( + BUILD_TARGET + ${target} + EXTRA_INCLUDES + ${AZRTOS_INCLUDES} + # ${TARGET_AZURERTOS_COMMON_INCLUDE_DIRS} + ) + + # add_dependencies(${target}.elf nano::gecko_sdk_${target}) + + target_link_libraries(${target}.elf + nano::gecko_sdk_${target} + ) + + endif() + target_link_libraries(${target}.elf azrtos::threadx ) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 724639e32b..0dfe088850 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -4,10 +4,8 @@ # include(binutils.common) -include(Gecko_SDK) -# Set target series -nf_set_silabs_target_series() +set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) # check if GECKO_SDK_SOURCE was specified or if it's empty (default is empty) set(NO_GECKO_SDK_SOURCE TRUE) @@ -42,6 +40,7 @@ if(NO_GECKO_SDK_SOURCE) gecko_sdk GIT_REPOSITORY https://github.com/SiliconLabs/gecko_sdk.git GIT_TAG ${GECKO_SDK_VERSION} + GIT_SHALLOW 1 ) else() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 6f0d4f04ca..47c66022d5 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -25,6 +25,20 @@ nf_setup_target_build( CLR_LINKER_FILE efm32gg11b_CLR + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GL192=1 + SL_BOARD_NAME=\"BRD2204A\" + SL_BOARD_REV=\"B07\" + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GL192=1 + SL_BOARD_NAME=\"BRD2204A\" + SL_BOARD_REV=\"B07\" + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + # BOOTER_EXTRA_LINKMAP_PROPERTIES # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x4000" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c new file mode 100644 index 0000000000..e8d0624c39 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c @@ -0,0 +1,63 @@ +/***************************************************************************//** + * @file + * @brief LED Driver Instances + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_simple_led.h" +#include "em_gpio.h" +#include "sl_simple_led_led0_config.h" +#include "sl_simple_led_led1_config.h" + +sl_simple_led_context_t simple_led0_context = { + .port = SL_SIMPLE_LED_LED0_PORT, + .pin = SL_SIMPLE_LED_LED0_PIN, + .polarity = SL_SIMPLE_LED_LED0_POLARITY, +}; + +sl_simple_led_context_t simple_led1_context = { + .port = SL_SIMPLE_LED_LED1_PORT, + .pin = SL_SIMPLE_LED_LED1_PIN, + .polarity = SL_SIMPLE_LED_LED1_POLARITY, +}; + +const sl_led_t sl_led_led0 = { + .context = &simple_led0_context, + .init = sl_simple_led_init, + .turn_on = sl_simple_led_turn_on, + .turn_off = sl_simple_led_turn_off, + .toggle = sl_simple_led_toggle, + .get_state = sl_simple_led_get_state, +}; + + +const sl_led_t sl_led_led1 = { + .context = &simple_led1_context, + .init = sl_simple_led_init, + .turn_on = sl_simple_led_turn_on, + .turn_off = sl_simple_led_turn_off, + .toggle = sl_simple_led_toggle, + .get_state = sl_simple_led_get_state, +}; + +const sl_led_t *sl_simple_led_array[] = { + &sl_led_led0, + &sl_led_led1 +}; + +void sl_simple_led_init_instances(void) +{ + sl_led_init(&sl_led_led0); + sl_led_init(&sl_led_led1); +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h new file mode 100644 index 0000000000..f96e8d0232 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h @@ -0,0 +1,33 @@ +/***************************************************************************//** + * @file + * @brief LED Driver Instances + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_INSTANCES_H +#define SL_SIMPLE_LED_INSTANCES_H + +#include "sl_simple_led.h" + +extern const sl_led_t sl_led_led0; +extern const sl_led_t sl_led_led1; + +extern const sl_led_t *sl_simple_led_array[]; + +#define SL_SIMPLE_LED_COUNT 2 +#define SL_SIMPLE_LED_INSTANCE(n) (sl_simple_led_array[n]) + +void sl_simple_led_init_instances(void); + +#endif // SL_SIMPLE_LED_INIT_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S index ef21b2660d..39ad790f18 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/tx_initialize_low_level.S @@ -49,7 +49,7 @@ @ @ SYSTEM_CLOCK = 38000000 -SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) .text 32 .align 4 diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h new file mode 100644 index 0000000000..ec44b774f6 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h @@ -0,0 +1,82 @@ +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..e3dd619a75 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 64 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h new file mode 100644 index 0000000000..33b25efd3d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED0_CONFIG_H +#define SL_SIMPLE_LED_LED0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED0_PORT gpioPortH +#define SL_SIMPLE_LED_LED0_PIN 10 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h new file mode 100644 index 0000000000..570c4b6c01 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h @@ -0,0 +1,44 @@ +/***************************************************************************//** + * @file + * @brief Simple Led Driver Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_LED_LED1_CONFIG_H +#define SL_SIMPLE_LED_LED1_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Simple LED configuration +// +// Active low +// Active high +// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH +#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW +// end led configuration + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_SIMPLE_LED_LED0 +// $[GPIO_SL_SIMPLE_LED_LED0] +#define SL_SIMPLE_LED_LED1_PORT gpioPortH +#define SL_SIMPLE_LED_LED1_PIN 14 + +// [GPIO_SL_SIMPLE_LED_LED0]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..be04808312 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,107 @@ +/***************************************************************************/ /** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories + *Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is + *Silicon Laboratories Inc. Your use of + *this software is governed by the terms + *of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. + *This software is distributed to you in + *Source Code format and is governed by + *the sections of the MSLA applicable to + *Source Code. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json index 9bacbe281d..81a3cfbd9e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json @@ -2,114 +2,76 @@ "version": "0.2.0", "configurations": [ { - "name": "ST_B_L475E_IOT01A nanoBooter", + "name": "SL_STK3701A nanoBooter", "type": "cppdbg", "request": "launch", "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "targetArchitecture": "ARM", "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", "setupCommands": [ - { - "text": "target extended-remote localhost:3333" - }, - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - }, - { - "text": "monitor flash write_image erase \"/build/nanoBooter.hex\" " - }, - { - "text": "file /build/nanoBooter.elf" - }, - { - "text": "monitor reset halt" - }, - { - "text": "set output-radix 16", - "description": "set the default numeric base to 16", - "ignoreFailures": false - } - ], - "customLaunchSetupCommands": [ - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - } + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor reset 0" + }, + { + "text": "load" + } ], + "launchCompleteCommand": "None", "logging": { - "moduleLoad": false, - "trace": false, - "engineLogging": false, - "programOutput": true, - "exceptions": true - }, - "launchCompleteCommand": "exec-continue", - "debugServerPath": "/bin/openocd.exe", - "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", - "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", - "filterStderr": true, - "externalConsole": true, - "cwd": "${cwd}" + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } }, { - "name": "ST_B_L475E_IOT01A nanoCLR", + "name": "SL_STK3701A nanoCLR", "type": "cppdbg", "request": "launch", "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "targetArchitecture": "ARM", "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", "setupCommands": [ - { - "text": "target extended-remote localhost:3333" - }, - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - }, - { - "text": "monitor flash write_image erase \"/build/nanoCLR.hex\" " - }, - { - "text": "file /build/nanoCLR.elf" - }, - { - "text": "monitor reset halt" - }, - { - "text": "set output-radix 16", - "description": "set the default numeric base to 16", - "ignoreFailures": false - } - ], - "customLaunchSetupCommands": [ - { - "text": "monitor reset_config none separate" - }, - { - "text": "monitor reset halt" - } + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor reset 0" + }, + { + "text": "load" + } ], + "launchCompleteCommand": "None", "logging": { - "moduleLoad": false, - "trace": false, - "engineLogging": false, - "programOutput": true, - "exceptions": true - }, - "launchCompleteCommand": "exec-continue", - "debugServerPath": "/bin/openocd.exe", - "debugServerArgs": "-s \"/scripts/\" -f board/stm32l4discovery.cfg", - "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", - "filterStderr": true, - "externalConsole": true, - "cwd": "${cwd}" + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } } ] } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index d547592f88..e81afa95f8 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -27,11 +27,14 @@ * ******************************************************************************/ +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 + config (rw) : ORIGIN = 0x00000000, len = 0 /* space reserved for configuration block */ } /* Linker script to place sections and symbol values. Should be used together @@ -69,6 +72,11 @@ MEMORY */ ENTRY(Reset_Handler) +__nanoConfig_start__ = ORIGIN(config); +__nanoConfig_size__ = LENGTH(config); +__nanoConfig_end__ = __nanoConfig_start__ + __nanoConfig_size__; + + SECTIONS { .text : diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index f56cc17fab..6936299bc0 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -3,12 +3,18 @@ // See LICENSE file in the project root for full license information. // -#include +#include +#include +#include +#include #include #include -#include -#include + +#include + +// #include +// #include // byte pool configuration and definitions #define DEFAULT_BYTE_POOL_SIZE 4096 @@ -31,6 +37,8 @@ extern void ReceiverThread_entry(uint32_t parameter); TX_THREAD blinkThread; uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; +TX_THREAD blinkThread1; +uint32_t blinkThread1Stack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; void BlinkThread_entry(uint32_t parameter) { @@ -38,8 +46,19 @@ void BlinkThread_entry(uint32_t parameter) while (1) { - // palTogglePad(GPIOB, GPIOB_LD2); + sl_led_toggle(&sl_led_led0); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void BlinkThread1_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + sl_led_toggle(&sl_led_led1); } } @@ -62,13 +81,13 @@ void tx_application_define(void *first_unused_memory) // initialize block storage list and devices // in CLR this is called in nanoHAL_Initialize() // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - BlockStorageList_Initialize(); - BlockStorage_AddDevices(); + // BlockStorageList_Initialize(); + // BlockStorage_AddDevices(); // initialize configuration manager // in CLR this is called in nanoHAL_Initialize() // for nanoBooter we have to init it here to have access to network configuration blocks - ConfigurationManager_Initialize(); + // ConfigurationManager_Initialize(); // Create blink thread status = tx_thread_create( @@ -90,6 +109,26 @@ void tx_application_define(void *first_unused_memory) } } + // Create blink thread + status = tx_thread_create( + &blinkThread1, + "Blink Thread1", + BlinkThread1_entry, + 0, + blinkThread1Stack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + // Create receiver thread status = tx_thread_create( &receiverThread, @@ -117,7 +156,8 @@ void tx_application_define(void *first_unused_memory) // Application entry point. int main(void) { - //halInit(); + // Initialize the board + sl_system_init(); // init boot clipboard InitBootClipboard(); @@ -142,6 +182,12 @@ int main(void) // } // } - // Enter the ThreadX kernel - tx_kernel_enter(); +/*Set unbuffered mode for stdout (newlib)*/ +// setvbuf(stdout, NULL, _IONBF, 0); +// /*Set unbuffered mode for stdin (newlib)*/ +// setvbuf(stdin, NULL, _IONBF, 0); + + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index d547592f88..12726e390c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -27,11 +27,14 @@ * ******************************************************************************/ +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x200000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x80000 + config (rw) : ORIGIN = 0x00000000, len = 0 /* space reserved for configuration block */ } /* Linker script to place sections and symbol values. Should be used together @@ -69,6 +72,11 @@ MEMORY */ ENTRY(Reset_Handler) +__nanoConfig_start__ = ORIGIN(config); +__nanoConfig_size__ = LENGTH(config); +__nanoConfig_end__ = __nanoConfig_start__ + __nanoConfig_size__; + + SECTIONS { .text : diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 48e004773f..bb9513ef29 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -6,7 +6,7 @@ // #include // #include -// #include +#include // #include // #include @@ -45,9 +45,9 @@ // uint32_t __attribute__((section(".ram4"))) clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; // extern void ClrStartupThread_entry(uint32_t parameter); -// void tx_application_define(void *first_unused_memory) -// { -// (void)first_unused_memory; +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; // uint16_t status; // // Create a byte memory pool from which to allocate the thread stacks. @@ -117,16 +117,16 @@ // { // } // } -// } +} -// // Application entry point. -// int main(void) -// { -// halInit(); +// Application entry point. +int main(void) +{ + // halInit(); -// // init boot clipboard -// InitBootClipboard(); + // // init boot clipboard + // InitBootClipboard(); -// // Enter the ThreadX kernel -// tx_kernel_enter(); -// } + // Enter the ThreadX kernel + tx_kernel_enter(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index e69de29bb2..e2377fccc9 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -0,0 +1,38 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# Azure RTOS ST specific file +# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_STM32FlashDriver.c) +list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c) +# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c) + +# # append Target files +# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c) +# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/LaunchCLR.c) + +# include configuration manager file, if feature is enabled +if(NF_FEATURE_HAS_CONFIG_BLOCK) + list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp) +endif() + +# if(NF_TRACE_TO_STDIO) +# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_GenericPort_stdio.c) +# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_BASE_LOCATION}/target_stdio_config.c) +# endif() + +# if(USE_NETWORKING_OPTION) + +# configure_file(${CMAKE_CURRENT_SOURCE_DIR}/network_options.h.in +# ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}/network_options.h @ONLY) + +# endif() + +# # append hard fault handler if the build type is to include debug info +# if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") +# # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/hard_fault_handler.c) +# endif() + +# make vars global +set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c new file mode 100644 index 0000000000..9d43fa1a25 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c @@ -0,0 +1,76 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include + +#if defined(TRACE_MASK) && (TRACE_MASK & TRACE_VERBOSE) != 0 +// used WP_Message_Process() and methods it calls to avoid flooding TRACE +extern uint32_t traceLoopCounter; +#endif + +void WP_ReceiveBytes(uint8_t **ptr, uint32_t *size) +{ + // save for later comparison + uint32_t requestedSize = *size; + size_t bytesRead; + sl_status_t requestResult; + + // check for requests with 0 size + if (*size) + { + // blocking receive as SL API does not support non-blocking + requestResult = sl_iostream_read(sl_iostream_vcom_handle, *ptr, requestedSize, &bytesRead); + + // Warning: Including TRACE_VERBOSE will NOT output the following TRACE on every loop of the statemachine to + // avoid flooding the trace. + TRACE_LIMIT(TRACE_VERBOSE, 100, "RXMSG: Expecting %d bytes, received %d.\n", requestedSize, read); + + if (requestResult == SL_STATUS_EMPTY) + { + // hang here for a bit + tx_thread_sleep(10); + } + else if (requestResult == SL_STATUS_OK) + { + // update pointer and size + *ptr += bytesRead; + *size -= bytesRead; + } + } + + return; +} + +uint8_t WP_TransmitMessage(WP_Message *message) +{ + TRACE_WP_HEADER(WP_TXMSG, message); + + // non-blocking transmit + if (sl_iostream_write(sl_iostream_vcom_handle, (uint8_t *)&message->m_header, sizeof(message->m_header)) != + SL_STATUS_OK) + { + return false; + } + + // if there is anything on the payload send it to the output stream + if (message->m_header.m_size && message->m_payload) + { + // non-blocking transmit + if (sl_iostream_write(sl_iostream_vcom_handle, message->m_payload, message->m_header.m_size) != SL_STATUS_OK) + { + return false; + } + } + + return true; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/RTE_Components.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/RTE_Components.h new file mode 100644 index 0000000000..c62a617c82 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/RTE_Components.h @@ -0,0 +1,16 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_board_default_init_stub.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_board_default_init_stub.c new file mode 100644 index 0000000000..034a7d9f08 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_board_default_init_stub.c @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2022 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// defined as weak to allow overriding at target level +__nfweak void sl_board_default_init(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h new file mode 100644 index 0000000000..d9773b6755 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h @@ -0,0 +1,17 @@ +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_LED0_PRESENT +#define SL_CATALOG_LED1_PRESENT +#define SL_CATALOG_SIMPLE_LED_PRESENT +#define SL_CATALOG_SIMPLE_LED_LED0_PRESENT +#define SL_CATALOG_SLEEPTIMER_PRESENT +#define SL_CATALOG_IOSTREAM_UART_COMMON_PRESENT +#define SL_CATALOG_IOSTREAM_USART_PRESENT +// TODO +// #define SL_CATALOG_KERNEL_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..cd38b3777c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c new file mode 100644 index 0000000000..9c44014998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c @@ -0,0 +1,91 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_simple_led_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + sl_device_init_hfxo(); + sl_device_init_lfxo(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); +} + +void sl_kernel_start(void) +{ + // Enter the ThreadX kernel. + tx_kernel_enter(); +} + +void sl_driver_init(void) +{ + GPIOINT_Init(); + // sl_i2cspm_init_instances(); + sl_uartdrv_init_instances(); + sl_simple_led_init_instances(); +} + +void sl_service_init(void) +{ + sl_board_configure_vcom(); + sl_sleeptimer_init(); + sl_iostream_init_instances(); +} + +void sl_stack_init(void) +{ +} + +void sl_internal_app_init(void) +{ +} + +void sl_platform_process_action(void) +{ +} + +void sl_service_process_action(void) +{ +} + +void sl_stack_process_action(void) +{ +} + +void sl_internal_app_process_action(void) +{ +} + +void sl_iostream_init_instances(void) +{ + sl_iostream_usart_init_instances(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h new file mode 100644 index 0000000000..e4198ae67c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h @@ -0,0 +1,22 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_kernel_start(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_platform_process_action(void); +void sl_service_process_action(void); +void sl_stack_process_action(void); +void sl_internal_app_process_action(void); +void sl_iostream_init_instances(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c new file mode 100644 index 0000000000..483e9f8381 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c @@ -0,0 +1,42 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_i2cspm.h" +#include "em_cmu.h" +// Include instance config +#include "sl_i2cspm_sensor_config.h" + +sl_i2cspm_t *sl_i2cspm_sensor = SL_I2CSPM_SENSOR_PERIPHERAL; + +#if SL_I2CSPM_SENSOR_SPEED_MODE == 0 +#define SL_I2CSPM_SENSOR_HLR i2cClockHLRStandard +#define SL_I2CSPM_SENSOR_MAX_FREQ I2C_FREQ_STANDARD_MAX +#elif SL_I2CSPM_SENSOR_SPEED_MODE == 1 +#define SL_I2CSPM_SENSOR_HLR i2cClockHLRAsymetric +#define SL_I2CSPM_SENSOR_MAX_FREQ I2C_FREQ_FAST_MAX +#elif SL_I2CSPM_SENSOR_SPEED_MODE == 2 +#define SL_I2CSPM_SENSOR_HLR i2cClockHLRFast +#define SL_I2CSPM_SENSOR_MAX_FREQ I2C_FREQ_FASTPLUS_MAX +#endif + +I2CSPM_Init_TypeDef init_sensor = { + .port = SL_I2CSPM_SENSOR_PERIPHERAL, + .sclPort = SL_I2CSPM_SENSOR_SCL_PORT, + .sclPin = SL_I2CSPM_SENSOR_SCL_PIN, + .sdaPort = SL_I2CSPM_SENSOR_SDA_PORT, + .sdaPin = SL_I2CSPM_SENSOR_SDA_PIN, + .portLocationScl = SL_I2CSPM_SENSOR_SCL_LOC, + .portLocationSda = SL_I2CSPM_SENSOR_SDA_LOC, + .i2cRefFreq = 0, + .i2cMaxFreq = SL_I2CSPM_SENSOR_MAX_FREQ, + .i2cClhr = SL_I2CSPM_SENSOR_HLR +}; + +void sl_i2cspm_init_instances(void) +{ + CMU_ClockEnable(cmuClock_GPIO, true); + //I2CSPM_Init(&init_sensor); +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_instances.h new file mode 100644 index 0000000000..dfcdd79f7e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_instances.h @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_I2CSPM_INSTANCES_H +#define SL_I2CSPM_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_i2cspm.h" + + +#define SL_I2CSPM_SENSOR_PRESENT + + +extern sl_i2cspm_t *sl_i2cspm_sensor; + +void sl_i2cspm_init_instances(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_I2CSPM_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c new file mode 100644 index 0000000000..fc0d9d21e2 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c @@ -0,0 +1,27 @@ +#include "sl_iostream.h" +#include "sl_iostream_handles.h" +#include "string.h" + +const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { + + &sl_iostream_instance_vcom_info, + +}; + +const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); + +/***************************************************************************//** + * Get iostream instance handle for a given name + * + * @return Instance handle if it exist, NULL otherwise. + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_handle(char *name) +{ + for (uint32_t i = 0; i < sl_iostream_instances_count; i++) { + if (strcmp(sl_iostream_instances_info[i]->name, name) == 0) { + return sl_iostream_instances_info[i]->handle; + } + } + + return NULL; +} \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.h new file mode 100644 index 0000000000..0edcc71ed1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.h @@ -0,0 +1,20 @@ +#ifndef SL_IOSTREAM_HANDLES_H +#define SL_IOSTREAM_HANDLES_H +#include "sl_iostream.h" +#include "sl_iostream_init_usart_instances.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +extern const sl_iostream_instance_info_t *sl_iostream_instances_info[]; +extern const uint32_t sl_iostream_instances_count; + +sl_iostream_t *sl_iostream_get_handle(char *name); + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_HANDLES_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h new file mode 100644 index 0000000000..c092c37eec --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h @@ -0,0 +1,16 @@ +#ifndef SL_IOSTREAM_INIT_INSTANCES_H +#define SL_IOSTREAM_INIT_INSTANCES_H + +#include "sl_iostream.h" +#ifdef __cplusplus +extern "C" { +#endif + +// Initialize iostream component(s) / instance(s) +void sl_iostream_init_instances(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_INIT_INSTANCES_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c new file mode 100644 index 0000000000..c376c82810 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -0,0 +1,208 @@ +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif +#include "em_device.h" +#include "sl_iostream.h" +#include "sl_iostream_uart.h" +#include "sl_iostream_usart.h" +// Include instance config + #include "sl_iostream_usart_vcom_config.h" + +// MACROs for generating name and IRQ handler function +#define SL_IOSTREAM_USART_CONCAT_PASTER(first, second, third) first ## second ## third + + + + +#define SL_IOSTREAM_USART_TX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQn) +#define SL_IOSTREAM_USART_RX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQn) +#define SL_IOSTREAM_USART_TX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQHandler) +#define SL_IOSTREAM_USART_RX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQHandler) + +#define SL_IOSTREAM_USART_CLOCK_REF(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(cmuClock_, USART, periph_nbr) + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +// EM Events +#define SLEEP_EM_EVENT_MASK ( SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ + | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ + | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ + | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +static void events_handler(sl_power_manager_em_t from, + sl_power_manager_em_t to); +static sl_power_manager_em_transition_event_info_t events_info = +{ + .event_mask = SLEEP_EM_EVENT_MASK, + .on_event = events_handler, +}; +static sl_power_manager_em_transition_event_handle_t events_handle; +#endif + + +sl_status_t sl_iostream_usart_init_vcom(void); + + +// Instance(s) handle and context variable +static sl_iostream_uart_t sl_iostream_vcom; +sl_iostream_t *sl_iostream_vcom_handle = &sl_iostream_vcom.stream; +sl_iostream_uart_t *sl_iostream_uart_vcom_handle = &sl_iostream_vcom; +static sl_iostream_usart_context_t context_vcom; +static uint8_t rx_buffer_vcom[SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE]; +sl_iostream_instance_info_t sl_iostream_instance_vcom_info = { + .handle = &sl_iostream_vcom.stream, + .name = "vcom", + .type = SL_IOSTREAM_TYPE_UART, + .periph_id = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, + .init = sl_iostream_usart_init_vcom, +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +sl_status_t sl_iostream_usart_init_vcom(void) +{ + sl_status_t status; + USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; + init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; + init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; + init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; +#if (_SILICON_LABS_32B_SERIES > 0) +#if (SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE != uartFlowControlSoftware) + init_vcom.hwFlowControl = SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE; +#else + init_vcom.hwFlowControl = usartHwFlowControlNone; +#endif +#endif + sl_iostream_usart_config_t config_vcom = { + .usart = SL_IOSTREAM_USART_VCOM_PERIPHERAL, + .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .tx_port = SL_IOSTREAM_USART_VCOM_TX_PORT, + .tx_pin = SL_IOSTREAM_USART_VCOM_TX_PIN, + .rx_port = SL_IOSTREAM_USART_VCOM_RX_PORT, + .rx_pin = SL_IOSTREAM_USART_VCOM_RX_PIN, +#if (_SILICON_LABS_32B_SERIES > 0) +#if defined(SL_IOSTREAM_USART_VCOM_CTS_PORT) + .cts_port = SL_IOSTREAM_USART_VCOM_CTS_PORT, + .cts_pin = SL_IOSTREAM_USART_VCOM_CTS_PIN, +#endif +#if defined(SL_IOSTREAM_USART_VCOM_RTS_PORT) + .rts_port = SL_IOSTREAM_USART_VCOM_RTS_PORT, + .rts_pin = SL_IOSTREAM_USART_VCOM_RTS_PIN, +#endif +#endif +#if defined(GPIO_USART_ROUTEEN_TXPEN) + .usart_index = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, +#elif defined(USART_ROUTEPEN_RXPEN) + .usart_tx_location = SL_IOSTREAM_USART_VCOM_TX_LOC, + .usart_rx_location = SL_IOSTREAM_USART_VCOM_RX_LOC, +#if defined(SL_IOSTREAM_USART_VCOM_CTS_PORT) + .usart_cts_location = SL_IOSTREAM_USART_VCOM_CTS_LOC, +#endif +#if defined(SL_IOSTREAM_USART_VCOM_RTS_PORT) + .usart_rts_location = SL_IOSTREAM_USART_VCOM_RTS_LOC, +#endif +#else + .usart_location = SL_IOSTREAM_USART_VCOM_ROUTE_LOC, +#endif + }; + sl_iostream_uart_config_t uart_config_vcom = { + .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .rx_buffer = rx_buffer_vcom, + .rx_buffer_length = SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE, + .lf_to_crlf = SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF, + .rx_when_sleeping = SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, +#if defined(SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE) +#if (SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE == uartFlowControlSoftware) + .sw_flow_control = true, +#else + .sw_flow_control = false, +#endif +#else + .sw_flow_control = false, +#endif + }; + // Instantiate usart instance + status = sl_iostream_usart_init(&sl_iostream_vcom, + &uart_config_vcom, + &init_vcom, + &config_vcom, + &context_vcom); + EFM_ASSERT(status == SL_STATUS_OK); + + return status; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +void sl_iostream_usart_init_instances(void) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) + // Enable power manager notifications + sl_power_manager_subscribe_em_transition_event(&events_handle, &events_info); +#endif + + // Instantiate usart instance(s) + + sl_iostream_usart_init_vcom(); + +} + + +// VCOM IRQ Handler +void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) +{ + sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); +} + +void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) +{ + sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); +} + + + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + +sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void) +{ + return sl_iostream_uart_sleep_on_isr_exit(&sl_iostream_vcom); +} + +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +static void events_handler(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + uint32_t out; + if (((from == SL_POWER_MANAGER_EM2) + || (from == SL_POWER_MANAGER_EM3)) + && ((to == SL_POWER_MANAGER_EM1) + || (to == SL_POWER_MANAGER_EM0))) { + + // Wake the USART Tx pin back up + out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); + GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); + + } else if (((to == SL_POWER_MANAGER_EM2) + || (to == SL_POWER_MANAGER_EM3)) + && ((from == SL_POWER_MANAGER_EM1) + || (from == SL_POWER_MANAGER_EM0))) { + + // Sleep the USART Tx pin on series 2 devices to save energy + out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); + GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); + + } +} +#endif \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h new file mode 100644 index 0000000000..2301dbe600 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h @@ -0,0 +1,34 @@ +#ifndef SL_IOSTREAM_INIT_USART_INSTANCES_H +#define SL_IOSTREAM_INIT_USART_INSTANCES_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif +#include "sl_iostream.h" +#include "sl_iostream_uart.h" +#ifdef __cplusplus +extern "C" { +#endif + + +extern sl_iostream_t *sl_iostream_vcom_handle; +extern sl_iostream_uart_t *sl_iostream_uart_vcom_handle; +extern sl_iostream_instance_info_t sl_iostream_instance_vcom_info; + + +// Initialize only iostream usart instance(s) +void sl_iostream_usart_init_instances(void); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + +sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_INIT_USART_INSTANCES_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/dmadrv_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/dmadrv_config.h new file mode 100644 index 0000000000..fd584e666d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/dmadrv_config.h @@ -0,0 +1,26 @@ +#ifndef DMADRV_CONFIG_H +#define DMADRV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMA interrupt priority <0-7> +// Priority of the DMA interrupt. Smaller number equals higher priority. +// Default: 4 +#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 + +// Number of available channels <1-24> +// Number of DMA channels supported by the driver. A lower channel count +// will reduce RAM memory footprint. The default is to support all channels +// on the device. +// Default: 24 +#define EMDRV_DMADRV_DMA_CH_COUNT 24 + +// Number of fixed priority channels +// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, +// and channels [CH_PRIORITY, CH_COUNT] as round-robin. +// Default: 0 +#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 + +// <<< end of configuration section >>> + +#endif // DMADRV_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/emlib_core_debug_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/emlib_core_debug_config.h new file mode 100644 index 0000000000..50dbbed9bc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/emlib_core_debug_config.h @@ -0,0 +1,46 @@ +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +// If Enabled, either cycle_counter or systemview component must be added to project. +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h new file mode 100644 index 0000000000..88e1491e0c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h @@ -0,0 +1,252 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// USART1 CLK on PC15 +#define USART1_CLK_PORT gpioPortC +#define USART1_CLK_PIN 15 +#define USART1_CLK_LOC 3 + +// USART1 TX on PA14 +#define USART1_TX_PORT gpioPortA +#define USART1_TX_PIN 14 +#define USART1_TX_LOC 6 + +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +#define SL_SIMPLE_LED_LED0_PORT_PORT gpioPortH +#define SL_SIMPLE_LED_LED0_PORT_PIN 11 + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_dcdc_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_dcdc_config.h new file mode 100644 index 0000000000..615e91cf20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_dcdc_config.h @@ -0,0 +1,28 @@ +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 0 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL DCDC_PFMXCTRL_IPKVAL_DEFAULT + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_emu_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_emu_config.h new file mode 100644 index 0000000000..387abf94f4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_emu_config.h @@ -0,0 +1,68 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_EMU Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_EMU_CONFIG_H +#define SL_DEVICE_INIT_EMU_CONFIG_H + +#include "em_emu.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// EM4H Voltage scaling level +// Fast-wakeup voltage level +// Low-power optimized voltage level +// Default: emuVScaleEM4H_LowPower +#define SL_DEVICE_INIT_EMU_EM4_VSCALE emuVScaleEM4H_LowPower + +// Retain LFXO in EM4 +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_LFXO 0 + +// Retain LFRCO in EM4 +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_LFRCO 0 + +// Retain ULFRCO in EM4S +#define SL_DEVICE_INIT_EMU_EM4_RETAIN_ULFRCO 0 + +// Hibernate or shutoff EM4 state +// EM4 Shutoff +// EM4 Hibernate +// Default: emuEM4Shutoff +#define SL_DEVICE_INIT_EMU_EM4_STATE emuEM4Shutoff + +// EM4 pin retention mode +// No Retention: Pads enter reset state when entering EM4. +// Retention through EM4: Pads enter reset state when exiting EM4. +// Retention through EM4 and wakeup. +// Default: emuPinRetentionDisable +#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_EMU_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..ec442f5030 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfxo_config.h @@ -0,0 +1,39 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_i2cspm_sensor_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_i2cspm_sensor_config.h new file mode 100644 index 0000000000..b90117722b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_i2cspm_sensor_config.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file + * @brief I2CSPM Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_I2CSPM_SENSOR_CONFIG_H +#define SL_I2CSPM_SENSOR_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu + +// I2CSPM settings + +// Reference clock frequency +// Frequency in Hz of the reference clock. +// Select 0 to use the frequency of the currently selected clock. +// Default: 0 +#define SL_I2CSPM_SENSOR_REFERENCE_CLOCK 0 + +// Speed mode +// <0=> Standard mode (100kbit/s) +// <1=> Fast mode (400kbit/s) +// <2=> Fast mode plus (1Mbit/s) +// Default: 0 +#define SL_I2CSPM_SENSOR_SPEED_MODE 0 +// end I2CSPM config + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_I2CSPM_SENSOR +// $[I2C_SL_I2CSPM_SENSOR] +#define SL_I2CSPM_SENSOR_PERIPHERAL I2C0 +#define SL_I2CSPM_SENSOR_PERIPHERAL_NO 0 + +// I2C0 SCL on PC10 +#define SL_I2CSPM_SENSOR_SCL_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SCL_PIN 10 +#define SL_I2CSPM_SENSOR_SCL_LOC 14 + +// I2C0 SDA on PC11 +#define SL_I2CSPM_SENSOR_SDA_PORT gpioPortC +#define SL_I2CSPM_SENSOR_SDA_PIN 11 +#define SL_I2CSPM_SENSOR_SDA_LOC 16 +// [I2C_SL_I2CSPM_SENSOR]$ +// <<< sl:end pin_tool >>> + +#endif // SL_I2CSPM_SENSOR_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_memlcd_usart_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memlcd_usart_config.h new file mode 100644 index 0000000000..e535fd32f9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memlcd_usart_config.h @@ -0,0 +1,35 @@ +#ifndef SL_MEMLCD_CONFIG_H +#define SL_MEMLCD_CONFIG_H + +// <<< sl:start pin_tool >>> +// SL_MEMLCD_SPI +// $[USART_SL_MEMLCD_SPI] +#define SL_MEMLCD_SPI_PERIPHERAL USART1 +#define SL_MEMLCD_SPI_PERIPHERAL_NO 1 + +// USART1 TX on PA14 +#define SL_MEMLCD_SPI_TX_PORT gpioPortA +#define SL_MEMLCD_SPI_TX_PIN 14 +#define SL_MEMLCD_SPI_TX_LOC 6 + +// USART1 CLK on PC15 +#define SL_MEMLCD_SPI_CLK_PORT gpioPortC +#define SL_MEMLCD_SPI_CLK_PIN 15 +#define SL_MEMLCD_SPI_CLK_LOC 3 +// [USART_SL_MEMLCD_SPI]$ + +// SL_MEMLCD_SPI_CS +// $[GPIO_SL_MEMLCD_SPI_CS] +#define SL_MEMLCD_SPI_CS_PORT gpioPortC +#define SL_MEMLCD_SPI_CS_PIN 14 +// [GPIO_SL_MEMLCD_SPI_CS]$ + +// SL_MEMLCD_EXTCOMIN +// $[GPIO_SL_MEMLCD_EXTCOMIN] +#define SL_MEMLCD_EXTCOMIN_PORT gpioPortA +#define SL_MEMLCD_EXTCOMIN_PIN 11 +// [GPIO_SL_MEMLCD_EXTCOMIN]$ + +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h new file mode 100644 index 0000000000..b43ebcba02 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h @@ -0,0 +1,28 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE + #define SL_STACK_SIZE 4096 +#endif + +// Minimum heap size for the application. +// Default: 2048 +// Note that this value will configure the c heap which is normally used by +// malloc() and free() from the c library. The value defines a minimum heap +// size that is guaranteed to be available. The available heap may be larger +// to make use of any memory that would otherwise remain unused. +#ifndef SL_HEAP_SIZE + #define SL_HEAP_SIZE 2048 +#endif + +// +// <<< end of configuration section >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_power_manager_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_power_manager_config.h new file mode 100644 index 0000000000..735287ee7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_power_manager_config.h @@ -0,0 +1,70 @@ +/***************************************************************************//** + * @file + * @brief Power Manager configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_POWER_MANAGER_CONFIG_H +#define SL_POWER_MANAGER_CONFIG_H + +// Power Manager Configuration + +// Enable custom IRQ handler for external HF oscillator. +// Enable if CMU_IRQHandler/HFXO0_IRQHandler is needed from your application. +// The function sl_power_manager_irq_handler() will have to be called from you custom handler if this is enabled. +// Default: 0 +#define SL_POWER_MANAGER_CUSTOM_HF_OSCILLATOR_IRQ_HANDLER 0 + +// Lowest Energy mode allowed +// <2=> EM2 +// <3=> EM3 +// Default: 2 +#define SL_POWER_MANAGER_LOWEST_EM_ALLOWED 2 + +// Enable fast wakeup (disable voltage scaling in EM2/3 mode) +// Enable or disable voltage scaling in EM2/3 modes (when available). This decreases wakeup time by about 30 us. +// Deprecated. It is replaced by the function sl_power_manager_em23_voltage_scaling_enable_fast_wakeup() +// Default: 0 +#define SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP 0 + +// Enable debugging feature +// Enable or disable debugging features (trace the different modules that have requirements). +// Default: 0 +#define SL_POWER_MANAGER_DEBUG 0 + +// Maximum numbers of requirements that can be logged +// Default: 10 +#define SL_POWER_MANAGER_DEBUG_POOL_SIZE 10 +// + +// + +#endif /* SL_POWER_MANAGER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_sleeptimer_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_sleeptimer_config.h new file mode 100644 index 0000000000..846d37d608 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_sleeptimer_config.h @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp b/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 0000000000..77f66bb623 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,764 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +// #include +// #include + +#if defined(WIFI_DRIVER_ISM43362) && defined(I_AM_NANOCLR) +#include +#endif + +uint8_t programWidth = 0; + +uint32_t GetExistingConfigSize() +{ + uint32_t currentConfigSize = 0; + + // currentConfigSize = + // g_TargetConfiguration.NetworkInterfaceConfigs->Count * sizeof(HAL_Configuration_NetworkInterface); + // currentConfigSize += g_TargetConfiguration.Wireless80211Configs->Count * sizeof(HAL_Configuration_Wireless80211); + + return currentConfigSize; +} + +// initialization of configuration manager +// provided as weak so it can be replaced at target level, if required because of the target implementing the storage +// with a mechanism other then saving to flash +__nfweak void ConfigurationManager_Initialize() +{ + BlockStorageStream stream; + memset(&stream, 0, sizeof(BlockStorageStream)); + BlockStorageStream_Initialize(&stream, BlockUsage_CONFIG); + + BlockStorageDevice* device = BlockStorageList_GetFirstDevice(); + DeviceBlockInfo * deviceBlockInfo = BlockStorageDevice_GetDeviceInfo(device); + + if(deviceBlockInfo->Regions[stream.RegionIndex].Attributes & BlockRegionAttribute_ProgramWidthIs64bits) + { + programWidth = 64 / 8; + } + + // init g_TargetConfiguration + memset(&g_TargetConfiguration, 0, sizeof(HAL_TARGET_CONFIGURATION)); + + // enumerate the blocks + ConfigurationManager_EnumerateConfigurationBlocks(); +}; + +// Enumerates the configuration blocks from the configuration flash sector +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is +// used +__nfweak void ConfigurationManager_EnumerateConfigurationBlocks() +{ + // start checking if this device has config block + if (((uint32_t)&__nanoConfig_end__ - (uint32_t)&__nanoConfig_start__) > 0) + { + // find network configuration blocks + HAL_CONFIGURATION_NETWORK *networkConfigs = + (HAL_CONFIGURATION_NETWORK *)ConfigurationManager_FindNetworkConfigurationBlocks( + (uint32_t)&__nanoConfig_start__, + (uint32_t)&__nanoConfig_end__); + + // check network configs count + if (networkConfigs->Count == 0) + { + // there is no network config block available, get a default + HAL_Configuration_NetworkInterface *networkConfig = + (HAL_Configuration_NetworkInterface *)platform_malloc(sizeof(HAL_Configuration_NetworkInterface)); + + if (InitialiseNetworkDefaultConfig(networkConfig, 0)) + { + // config block created, store it + ConfigurationManager_StoreConfigurationBlock( + networkConfig, + DeviceConfigurationOption_Network, + 0, + sizeof(HAL_Configuration_NetworkInterface), + 0, + false); + + // have to enumerate again to pick it up + networkConfigs = (HAL_CONFIGURATION_NETWORK *)ConfigurationManager_FindNetworkConfigurationBlocks( + (uint32_t)&__nanoConfig_start__, + (uint32_t)&__nanoConfig_end__); + } + + platform_free(networkConfig); + } + +// // find wireless 80211 network configuration blocks +// HAL_CONFIGURATION_NETWORK_WIRELESS80211 *networkWirelessConfigs = +// (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks( +// (uint32_t)&__nanoConfig_start__, +// (uint32_t)&__nanoConfig_end__); + +// #if (TARGET_HAS_WIFI_SUPPORT == 1) +// if (networkWirelessConfigs->Count == 0) +// { +// // there is no network config block available, get a default +// HAL_Configuration_Wireless80211 *wirelessConfig = +// (HAL_Configuration_Wireless80211 *)platform_malloc(sizeof(HAL_Configuration_Wireless80211)); + +// InitialiseWirelessDefaultConfig(wirelessConfig, 0); + +// // config block created, store it +// ConfigurationManager_StoreConfigurationBlock( +// wirelessConfig, +// DeviceConfigurationOption_Wireless80211Network, +// 0, +// sizeof(HAL_Configuration_Wireless80211), +// 0, +// false); + +// // have to enumerate again to pick it up +// networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *) +// ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks( +// (uint32_t)&__nanoConfig_start__, +// (uint32_t)&__nanoConfig_end__); + +// platform_free(wirelessConfig); +// } +// #endif + + // find X509 certificate blocks + HAL_CONFIGURATION_X509_CERTIFICATE *certificateStore = + (HAL_CONFIGURATION_X509_CERTIFICATE *)ConfigurationManager_FindX509CertificateConfigurationBlocks( + (uint32_t)&__nanoConfig_start__, + (uint32_t)&__nanoConfig_end__); + + // find X509 device certificate blocks + HAL_CONFIGURATION_X509_DEVICE_CERTIFICATE *deviceCertificates = (HAL_CONFIGURATION_X509_DEVICE_CERTIFICATE *) + ConfigurationManager_FindX509DeviceCertificatesConfigurationBlocks( + (uint32_t)&__nanoConfig_start__, + (uint32_t)&__nanoConfig_end__); + + // alloc memory for g_TargetConfiguration + // because this is a struct of structs that use flexible members the memory has to be allocated from the heap + // the malloc size for each struct is computed separately + uint32_t sizeOfNetworkInterfaceConfigs = + offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); + // uint32_t sizeOfWireless80211Configs = + // offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + + // networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + + certificateStore->Count * sizeof(certificateStore->Certificates[0]); + uint32_t sizeOfX509DeviceCertificate = offsetof(HAL_CONFIGURATION_X509_DEVICE_CERTIFICATE, Certificates) + + deviceCertificates->Count * sizeof(deviceCertificates->Certificates[0]); + + g_TargetConfiguration.NetworkInterfaceConfigs = + (HAL_CONFIGURATION_NETWORK *)platform_malloc(sizeOfNetworkInterfaceConfigs); + // g_TargetConfiguration.Wireless80211Configs = + // (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)platform_malloc(sizeOfWireless80211Configs); + g_TargetConfiguration.CertificateStore = + (HAL_CONFIGURATION_X509_CERTIFICATE *)platform_malloc(sizeOfX509CertificateStore); + g_TargetConfiguration.DeviceCertificates = + (HAL_CONFIGURATION_X509_DEVICE_CERTIFICATE *)platform_malloc(sizeOfX509DeviceCertificate); + + // copy structs to g_TargetConfiguration + memcpy( + (HAL_CONFIGURATION_NETWORK *)g_TargetConfiguration.NetworkInterfaceConfigs, + networkConfigs, + sizeOfNetworkInterfaceConfigs); + // memcpy( + // (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)g_TargetConfiguration.Wireless80211Configs, + // networkWirelessConfigs, + // sizeOfWireless80211Configs); + memcpy( + (HAL_CONFIGURATION_X509_CERTIFICATE *)g_TargetConfiguration.CertificateStore, + certificateStore, + sizeOfX509CertificateStore); + memcpy( + (HAL_CONFIGURATION_X509_DEVICE_CERTIFICATE *)g_TargetConfiguration.DeviceCertificates, + deviceCertificates, + sizeOfX509DeviceCertificate); + + // now free the memory of the original structs + platform_free(networkConfigs); + // platform_free(networkWirelessConfigs); + platform_free(certificateStore); + platform_free(deviceCertificates); + } + else + { + // no config block + } +} + +// Gets the network configuration block from the configuration flash sector +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is +// used +__nfweak bool ConfigurationManager_GetConfigurationBlock( + void *configurationBlock, + DeviceConfigurationOption configuration, + uint32_t configurationIndex) +{ + int sizeOfBlock = 0; + uint8_t *blockAddress = NULL; + + // validate if the requested block exists + // Count has to be non zero + // requested Index has to exist (array index starts at zero, so need to add one) + if (configuration == DeviceConfigurationOption_Network) + { + if (g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + // the requested config block is beyond the available count + return false; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); + + // get block address + blockAddress = (uint8_t *)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + } + else if (configuration == DeviceConfigurationOption_Wireless80211Network) + { + if (g_TargetConfiguration.Wireless80211Configs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + { + return FALSE; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); + + // get block address + blockAddress = (uint8_t *)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + } + else if (configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if (g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + { + return FALSE; + } + + // get block address + blockAddress = (uint8_t *)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // set block size + // because X509 certificate has a variable length need to compute the block size in two steps + sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + sizeOfBlock += ((HAL_Configuration_X509CaRootBundle *)blockAddress)->CertificateSize; + } + else if (configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if (g_TargetConfiguration.DeviceCertificates->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.DeviceCertificates->Count) + { + return FALSE; + } + + // get block address + blockAddress = (uint8_t *)g_TargetConfiguration.DeviceCertificates->Certificates[configurationIndex]; + + // set block size + // because X509 certificate has a variable length need to compute the block size in two steps + sizeOfBlock = offsetof(HAL_Configuration_X509DeviceCertificate, Certificate); + sizeOfBlock += ((HAL_Configuration_X509DeviceCertificate *)blockAddress)->CertificateSize; + } + + // copy the config block content to the pointer in the argument + memcpy(configurationBlock, blockAddress, sizeOfBlock); + + return TRUE; +} + +// Stores the configuration block to the configuration flash sector +// NOTE: because inserting or removing a configuration block it's very 'RAM expensive' we choose not to support those +// operations the host debugger will have to be used to manage these operations on the device configuration collection +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is +// used +__nfweak bool ConfigurationManager_StoreConfigurationBlock( + void *configurationBlock, + DeviceConfigurationOption configuration, + uint32_t configurationIndex, + uint32_t blockSize, + uint32_t offset, + bool done) +{ + ByteAddress storageAddress = 0; + bool requiresEnumeration = FALSE; + bool success = FALSE; + + if (configuration == DeviceConfigurationOption_Network) + { + if (g_TargetConfiguration.NetworkInterfaceConfigs == NULL || + (g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 && configurationIndex == 0)) + { + // there is no network config block, we are storing the default one + // THIS IS THE FIRST CONFIG BLOCK THAT'S AUTO-CREATED + // OK to continue + // set storage address as the start of the flash configuration sector + storageAddress = (ByteAddress)&__nanoConfig_start__; + } + else + { + // the requested config block is beyond the available count + if ((configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + return FALSE; + } + + // set storage address from block address, plus the requested offset + storageAddress = + (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex] + offset; + } + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_NetworkInterface); + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + _ASSERTE(((HAL_Configuration_NetworkInterface *)configurationBlock)->StartupAddressMode > 0); + } + else if (configuration == DeviceConfigurationOption_Wireless80211Network) + { + +// #if (TARGET_HAS_WIFI_SUPPORT == 1) + +// if (g_TargetConfiguration.Wireless80211Configs == NULL || +// (g_TargetConfiguration.Wireless80211Configs->Count == 0 && configurationIndex == 0)) +// { +// // there is no wireless 80211 config block, so we are storing the default one +// // THIS IS THE SECOND CONFIG BLOCK THAT'S AUTO-CREATED +// // OK to continue +// // set storage address contiguous to the network config block +// storageAddress = (uint32_t)&__nanoConfig_start__ + sizeof(HAL_Configuration_NetworkInterface); + +// // check programming width +// if(programWidth > 0) +// { +// // round address to the next valid programming width +// storageAddress += programWidth - storageAddress % programWidth; +// } +// } +// else +// { +// // the requested config block is beyond the available count +// if ((configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) +// { +// return FALSE; +// } + +// // set storage address from block address, plus the requested offset +// storageAddress = +// (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex] + offset; +// } + +// // set block size, in case it's not already set +// blockSize = sizeof(HAL_Configuration_Wireless80211); + +// // make sure the config block marker is set +// memcpy( +// configurationBlock, +// c_MARKER_CONFIGURATION_WIRELESS80211_V1, +// sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + +// #else +// // no support for WIFI in this STM32 build +// return FALSE; +// #endif + } + else if (configuration == DeviceConfigurationOption_X509CaRootBundle) + { + // compute block size + // because X509 certificate has a variable length need to compute the block size in two steps + blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + blockSize += ((HAL_Configuration_X509CaRootBundle *)configurationBlock)->CertificateSize; + + // + if (g_TargetConfiguration.CertificateStore->Count == 0) + { + // there is nothing at the certificate store + // find size of existing config blocks + storageAddress = (uint32_t)&__nanoConfig_start__ + GetExistingConfigSize(); + } + else + { + // set storage address from block address, plus the requested offset + storageAddress = + (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex] + offset; + } + + if (g_TargetConfiguration.CertificateStore == NULL || + (g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count)) + { + // there is no block stored + // check if there is room for it + if (((uint32_t)&__nanoConfig_end__ - storageAddress) < blockSize) + { + // not enough room + return FALSE; + } + + // // now check if memory is erase, so the block can be stored + // if (!STM32FlashDriver_IsBlockErased(NULL, storageAddress, blockSize)) + // { + // // memory not erased, can't store + // return FALSE; + // } + } + + // make sure the config block marker is set, ONLY required on the 1st chunk + if (offset == 0) + { + memcpy( + configurationBlock, + c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, + sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); + } + } + else if (configuration == DeviceConfigurationOption_X509DeviceCertificates) + { + // compute block size + // because X509 certificate has a variable length need to compute the block size in two steps + blockSize = offsetof(HAL_Configuration_X509DeviceCertificate, Certificate); + blockSize += ((HAL_Configuration_X509DeviceCertificate *)configurationBlock)->CertificateSize; + + // + if (g_TargetConfiguration.DeviceCertificates->Count == 0) + { + // there is nothing at the certificate store + // find size of existing config blocks + storageAddress = (uint32_t)&__nanoConfig_start__ + GetExistingConfigSize(); + } + else + { + // set storage address from block address, plus the requested offset + storageAddress = + (ByteAddress)g_TargetConfiguration.DeviceCertificates->Certificates[configurationIndex] + offset; + } + + if (g_TargetConfiguration.DeviceCertificates == NULL || + (g_TargetConfiguration.DeviceCertificates->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.DeviceCertificates->Count)) + { + // there is no block stored + // check if there is room for it + if (((uint32_t)&__nanoConfig_end__ - storageAddress) < blockSize) + { + // not enough room + return FALSE; + } + + // // now check if memory is erase, so the block can be stored + // if (!STM32FlashDriver_IsBlockErased(NULL, storageAddress, blockSize)) + // { + // // memory not erased, can't store + // return FALSE; + // } + } + + // make sure the config block marker is set, ONLY required on the 1st chunk + if (offset == 0) + { + memcpy( + configurationBlock, + c_MARKER_CONFIGURATION_X509DEVICECERTIFICATE_V1, + sizeof(c_MARKER_CONFIGURATION_X509DEVICECERTIFICATE_V1)); + } + } + else if (configuration == DeviceConfigurationOption_All) + { + // particular situation where we are receiving the full configuration block + + // set storage address as the start of the flash configuration sector, plus the requested offset + storageAddress = (ByteAddress)&__nanoConfig_start__ + offset; + + // for save all the block size has to be provided, check that + if (blockSize == 0) + { + return FALSE; + } + } + + // // copy the config block content to the config block storage + // success = STM32FlashDriver_Write(NULL, storageAddress, blockSize, (unsigned char *)configurationBlock, true); + + // enumeration is required after we are DONE with SUCCESSFULLY storing all the config chunks + requiresEnumeration = (success && done); + + if (requiresEnumeration) + { + // free the current allocation(s) + platform_free(g_TargetConfiguration.NetworkInterfaceConfigs); + platform_free(g_TargetConfiguration.Wireless80211Configs); + platform_free(g_TargetConfiguration.CertificateStore); + platform_free(g_TargetConfiguration.DeviceCertificates); + + // perform enumeration of configuration blocks + ConfigurationManager_EnumerateConfigurationBlocks(); + } + + return success; +} + +// Updates a configuration block in the configuration flash sector +// The flash sector has to be erased before writing the updated block +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is +// used +__nfweak bool ConfigurationManager_UpdateConfigurationBlock( + void *configurationBlock, + DeviceConfigurationOption configuration, + uint32_t configurationIndex) +{ + ByteAddress storageAddress; + (void)storageAddress; + // uint32_t blockOffset; + // uint8_t *blockAddressInCopy; + uint32_t blockSize; + bool success = FALSE; + + // config sector size + int sizeOfConfigSector = (uint32_t)&__nanoConfig_end__ - (uint32_t)&__nanoConfig_start__; + + // allocate memory from CRT heap + uint8_t *configSectorCopy = (uint8_t *)platform_malloc(sizeOfConfigSector); + + if (configSectorCopy != NULL) + { + // copy config sector from flash to RAM + memcpy(configSectorCopy, &__nanoConfig_start__, sizeOfConfigSector); + + // find out the address for the config block to update in the configSectorCopy + // because we are copying back the config block to flash and just replacing the config block content + // the addresses in g_TargetConfiguration will remain the same + // plus we can calculate the offset of the config block from g_TargetConfiguration + if (configuration == DeviceConfigurationOption_Network) + { + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + // check if the configuration block is the same + if (ConfigurationManager_CheckExistingConfigurationBlock( + g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex], + configurationBlock, + sizeof(HAL_Configuration_NetworkInterface), + sizeof(HAL_Configuration_NetworkInterface))) + { + // block is the same + // free memory + platform_free(configSectorCopy); + + // operation is successfull (nothing to update) + return TRUE; + } + + // get storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_NetworkInterface); + + _ASSERTE(((HAL_Configuration_NetworkInterface *)configurationBlock)->StartupAddressMode > 0); + } + else if (configuration == DeviceConfigurationOption_Wireless80211Network) + { + // make sure the config block marker is set + memcpy( + configurationBlock, + c_MARKER_CONFIGURATION_WIRELESS80211_V1, + sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + + // check if the configuration block is the same + if (ConfigurationManager_CheckExistingConfigurationBlock( + g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex], + configurationBlock, + sizeof(HAL_Configuration_Wireless80211), + sizeof(HAL_Configuration_Wireless80211))) + { + // block is the same + // free memory + platform_free(configSectorCopy); + + // operation is successfull (nothing to update) + return TRUE; + } + + // storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_Wireless80211); + } + else if (configuration == DeviceConfigurationOption_X509CaRootBundle) + { + // make sure the config block marker is set + memcpy( + configurationBlock, + c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, + sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); + + // check if certificate is the same + if (ConfigurationManager_CheckExistingConfigurationBlock( + g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]->Certificate, + ((HAL_Configuration_X509CaRootBundle *)configurationBlock)->Certificate, + g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]->CertificateSize, + ((HAL_Configuration_X509CaRootBundle *)configurationBlock)->CertificateSize)) + { + // block is the same + // free memory + platform_free(configSectorCopy); + + // operation is successfull (nothing to update) + return TRUE; + } + + // storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // set block size, in case it's not already set + // because X509 certificate has a variable length need to compute the block size in two steps + blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + blockSize += ((HAL_Configuration_X509CaRootBundle *)configurationBlock)->CertificateSize; + } + else if (configuration == DeviceConfigurationOption_X509DeviceCertificates) + { + // make sure the config block marker is set + memcpy( + configurationBlock, + c_MARKER_CONFIGURATION_X509DEVICECERTIFICATE_V1, + sizeof(c_MARKER_CONFIGURATION_X509DEVICECERTIFICATE_V1)); + + // check if certificate is the same + if (ConfigurationManager_CheckExistingConfigurationBlock( + g_TargetConfiguration.DeviceCertificates->Certificates[configurationIndex]->Certificate, + ((HAL_Configuration_X509DeviceCertificate *)configurationBlock)->Certificate, + g_TargetConfiguration.DeviceCertificates->Certificates[configurationIndex]->CertificateSize, + ((HAL_Configuration_X509DeviceCertificate *)configurationBlock)->CertificateSize)) + { + // block is the same + // free memory + platform_free(configSectorCopy); + + // operation is successfull (nothing to update) + return TRUE; + } + + // storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.DeviceCertificates->Certificates[configurationIndex]; + + // set block size, in case it's not already set + // because X509 certificate has a variable length need to compute the block size in two steps + blockSize = offsetof(HAL_Configuration_X509DeviceCertificate, Certificate); + blockSize += ((HAL_Configuration_X509DeviceCertificate *)configurationBlock)->CertificateSize; + } + else + { + // this not a valid configuration option to update, quit + // free memory first + platform_free(configSectorCopy); + + return FALSE; + } + + // // erase config sector + // if (STM32FlashDriver_EraseBlock(NULL, (uint32_t)&__nanoConfig_start__) == TRUE) + // { + // // flash block is erased + + // // subtract the start address of config sector to get the offset + // blockOffset = storageAddress - (uint32_t)&__nanoConfig_start__; + + // // set pointer to block to udpate + // blockAddressInCopy = configSectorCopy + blockOffset; + + // // replace config block with new content by replacing memory + // memcpy(blockAddressInCopy, configurationBlock, blockSize); + + // // copy the config block copy back to the config block storage + // success = STM32FlashDriver_Write( + // NULL, + // (uint32_t)&__nanoConfig_start__, + // sizeOfConfigSector, + // (unsigned char *)configSectorCopy, + // true); + // } + + // free memory + platform_free(configSectorCopy); + } + + return success; +} + +// Default initialisation for wireless config block +// it's implemented with 'weak' attribute so it can be replaced at target level if different configurations are intended +__nfweak void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 *config, uint32_t configurationIndex) +{ + memset(config, 0, sizeof(HAL_Configuration_Wireless80211)); + + // make sure the config block marker is set + memcpy(config, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + + // Wireless station + config->Id = configurationIndex; + + config->Options = + (Wireless80211Configuration_ConfigurationOptions)(Wireless80211Configuration_ConfigurationOptions_AutoConnect | Wireless80211Configuration_ConfigurationOptions_Enable); +} + +// Default initialisation for Network interface config blocks +// it's implemented with 'weak' attribute so it can be replaced at target level if different configurations are intended +__nfweak bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface *config, uint32_t configurationIndex) +{ + (void)configurationIndex; + +// #if (TARGET_HAS_WIFI_SUPPORT == 1) + +// memset(config, 0, sizeof(HAL_Configuration_NetworkInterface)); + +// // make sure the config block marker is set +// memcpy(config->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + +// // currently only Wireless station is supported +// config->InterfaceType = NetworkInterfaceType_Wireless80211; +// config->StartupAddressMode = AddressMode_DHCP; +// config->AutomaticDNS = 1; +// config->SpecificConfigId = 0; + +// // fill in MAX with 0xFF to allow it updating it later +// memset(config->MacAddress, 0xFF, sizeof(config->MacAddress)); + +// // get default MAC +// #if defined(WIFI_DRIVER_ISM43362) && defined(I_AM_NANOCLR) +// // OK to ignore the return value, no harm done if it fails +// WIFI_GetMAC_Address(config->MacAddress); +// #endif + +// return TRUE; + +// #else + + (void)config; + + // can't create a "default" network config because we are lacking definition of a MAC address + + return FALSE; +// #endif +} + +int32_t ConfigurationManager_FindNetworkConfigurationMatchingWirelessConfigurationFromId(uint32_t configurationId) +{ + // loop though all Network config blocks trying to find one that has this ID as its SpecificConfig ID + for (int index = 0; index < g_TargetConfiguration.NetworkInterfaceConfigs->Count; index++) + { + if (g_TargetConfiguration.NetworkInterfaceConfigs->Configs[index]->SpecificConfigId == configurationId) + { + return index; + } + } + + // not found + return -1; +} diff --git a/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c b/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c index 5d589c81dd..93b7bde49f 100644 --- a/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c +++ b/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c @@ -20,7 +20,7 @@ __attribute__((noreturn)) void ReceiverThread_entry(uint32_t parameter) WP_Message_Process(); // pass control to the OS - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1)); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(10)); } // this function never returns From d1fee2ed7fc7ca05983eddafb3a7d08216b011e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 8 Jun 2022 16:00:02 +0100 Subject: [PATCH 007/572] Improve debug launch settings --- .../SiliconLabs/SL_STK3701A/launch.json | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json index 81a3cfbd9e..a4a945a94e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/launch.json @@ -9,7 +9,7 @@ "program": "${workspaceRoot}/build/nanoBooter.elf", "MIMode": "gdb", "debugServerPath": "/JLinkGDBServerCL.exe", - "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -singlerun -strict -nogui", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", "stopAtEntry": false, "serverStarted": "Connected to target", "cwd": "${cwd}", @@ -21,11 +21,14 @@ "text": "target extended-remote localhost:2331" }, { - "text": "monitor reset 0" + "text": "monitor halt" + }, + { + "text": "monitor reset" }, { "text": "load" - } + } ], "launchCompleteCommand": "None", "logging": { @@ -45,7 +48,7 @@ "program": "${workspaceRoot}/build/nanoCLR.elf", "MIMode": "gdb", "debugServerPath": "/JLinkGDBServerCL.exe", - "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -singlerun -strict -nogui", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", "stopAtEntry": false, "serverStarted": "Connected to target", "cwd": "${cwd}", @@ -57,11 +60,14 @@ "text": "target extended-remote localhost:2331" }, { - "text": "monitor reset 0" + "text": "monitor halt" + }, + { + "text": "monitor reset" }, { "text": "load" - } + } ], "launchCompleteCommand": "None", "logging": { From 542639bf2cf367ded2e689f6370e015eb215cad1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 8 Jun 2022 23:21:25 +0100 Subject: [PATCH 008/572] Add Flash driver for Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 1 + .../SiliconLabs/_common/CMakeLists.txt | 2 +- .../Target_BlockStorage_SL_MscFlashDriver.c | 100 ++++++++++++++++++ .../sl_iostream_init_usart_instances.c | 1 + .../Target_BlockStorage_SL_MscFlashDriver.h | 34 ++++++ .../WireProtocol_MonitorCommands.c | 69 ++++++------ 6 files changed, 170 insertions(+), 37 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/Target_BlockStorage_SL_MscFlashDriver.c create mode 100644 targets/AzureRTOS/SiliconLabs/_include/Target_BlockStorage_SL_MscFlashDriver.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 20958def53..b9dce69af4 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -57,6 +57,7 @@ set(gecko_sdk_srcs em_lcd.c em_leuart.c em_lesense.c + em_msc.c em_prs.c em_rmu.c em_rtc.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index e2377fccc9..69029c2dcc 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -4,7 +4,7 @@ # # Azure RTOS ST specific file -# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_STM32FlashDriver.c) +list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_SL_MscFlashDriver.c) list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c) # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c) diff --git a/targets/AzureRTOS/SiliconLabs/_common/Target_BlockStorage_SL_MscFlashDriver.c b/targets/AzureRTOS/SiliconLabs/_common/Target_BlockStorage_SL_MscFlashDriver.c new file mode 100644 index 0000000000..fe0e003c71 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/Target_BlockStorage_SL_MscFlashDriver.c @@ -0,0 +1,100 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#define FLASH_ERASED_WORD ((uint32_t)0xFFFFFFFF) + +bool SL_MscFlashDriver_InitializeDevice(void *context) +{ + (void)context; + + // Gecko SDK driver takes care of this, so always true + return true; +} + +bool SL_MscFlashDriver_UninitializeDevice(void *context) +{ + (void)context; + + // Gecko SDK driver takes care of this, so always true + return true; +} + +DeviceBlockInfo *SL_MscFlashDriver_GetDeviceInfo(void *context) +{ + + MEMORY_MAPPED_NOR_BLOCK_CONFIG *config = context; + + return config->BlockConfig.BlockDeviceInformation; +} + +bool SL_MscFlashDriver_Read(void *context, ByteAddress startAddress, unsigned int numBytes, unsigned char *buffer) +{ + (void)context; + + volatile uint8_t *cursor = (volatile uint8_t *)startAddress; + volatile uint8_t *endAddress = (volatile uint8_t *)(startAddress + numBytes); + + // copy contents from flash to buffer starting from the start address + while (cursor < endAddress) + { + *buffer++ = *cursor++; + } + + return true; +} + +bool SL_MscFlashDriver_Write( + void *context, + ByteAddress startAddress, + unsigned int numBytes, + unsigned char *buffer, + bool readModifyWrite) +{ + (void)context; + (void)readModifyWrite; + + MSC_Status_TypeDef mscReturn; + + MSC_Init(); + + mscReturn = MSC_WriteWord((uint32_t *)startAddress, (void const *)buffer, numBytes); + + MSC_Deinit(); + + return mscReturn == mscReturnOk; +} + +bool SL_MscFlashDriver_IsBlockErased(void *context, ByteAddress blockAddress, unsigned int length) +{ + (void)context; + (void)blockAddress; + (void)length; + + uint32_t *cursor = (uint32_t *)blockAddress; + uint32_t *endAddress = (uint32_t *)(blockAddress + length); + + // an erased flash address has to read FLASH_ERASED_WORD + // OK to check by word (32 bits) because the erase is performed by 'page' whose size is word multiple + while (cursor < endAddress) + { + if (*cursor++ != FLASH_ERASED_WORD) + { + // found an address with something other than FLASH_ERASED_WORD!! + return false; + } + } + + // reached here so the segment must be erased + return true; +} + +bool SL_MscFlashDriver_EraseBlock(void *context, ByteAddress address) +{ + (void)context; + + return MSC_ErasePage((uint32_t *)address) == mscReturnOk; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index c376c82810..697030c171 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -71,6 +71,7 @@ sl_status_t sl_iostream_usart_init_vcom(void) sl_status_t status; USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; + //init_vcom.oversampling = usartOVS16; init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; #if (_SILICON_LABS_32B_SERIES > 0) diff --git a/targets/AzureRTOS/SiliconLabs/_include/Target_BlockStorage_SL_MscFlashDriver.h b/targets/AzureRTOS/SiliconLabs/_include/Target_BlockStorage_SL_MscFlashDriver.h new file mode 100644 index 0000000000..5e80811b80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/Target_BlockStorage_SL_MscFlashDriver.h @@ -0,0 +1,34 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGET_SL_MSCFLASH_DRIVER_H +#define TARGET_SL_MSCFLASH_DRIVER_H + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + bool SL_MscFlashDriver_InitializeDevice(void *); + bool SL_MscFlashDriver_UninitializeDevice(void *); + DeviceBlockInfo *SL_MscFlashDriver_GetDeviceInfo(void *); + bool SL_MscFlashDriver_Read(void *, ByteAddress startAddress, unsigned int numBytes, unsigned char *buffer); + bool SL_MscFlashDriver_Write( + void *, + ByteAddress startAddress, + unsigned int numBytes, + unsigned char *buffer, + bool readModifyWrite); + bool SL_MscFlashDriver_IsBlockErased(void *, ByteAddress blockAddress, unsigned int length); + bool SL_MscFlashDriver_EraseBlock(void *, ByteAddress address); + +#ifdef __cplusplus +} +#endif + +#endif // TARGET_SL_MSCFLASH_DRIVER_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c b/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c index 66eb37a9ef..b791dd4743 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c @@ -4,49 +4,46 @@ // See LICENSE file in the project root for full license information. // -// #include -// #include -// #include -// #include -// #include -// #include +#include +#include +#include +#include +#include +#include -// int AccessMemory(uint32_t location, uint32_t lengthInBytes, uint8_t *buffer, int32_t mode, uint32_t *errorCode) -// { -// // reset error code -// *errorCode = AccessMemoryErrorCode_NoError; +int AccessMemory(uint32_t location, uint32_t lengthInBytes, uint8_t *buffer, int32_t mode, uint32_t *errorCode) +{ + // reset error code + *errorCode = AccessMemoryErrorCode_NoError; -// switch (mode) -// { -// case AccessMemory_Write: -// // use FLASH driver to perform write operation -// // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h -// return STM32FlashDriver_Write(NULL, location, lengthInBytes, buffer, true); + switch (mode) + { + case AccessMemory_Write: + // use FLASH driver to perform write operation + return SL_MscFlashDriver_Write(NULL, location, lengthInBytes, buffer, true); -// case AccessMemory_Erase: -// // erase using FLASH driver -// // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h -// return STM32FlashDriver_EraseBlock(NULL, location); + case AccessMemory_Erase: + // erase using FLASH driver + return SL_MscFlashDriver_EraseBlock(NULL, location); -// case AccessMemory_Check: -// // compute CRC32 of the memory segment -// *(unsigned int *)buffer = SUPPORT_ComputeCRC((uint32_t *)location, lengthInBytes, 0); -// // done here -// return true; + case AccessMemory_Check: + // compute CRC32 of the memory segment + *(unsigned int *)buffer = SUPPORT_ComputeCRC((uint32_t *)location, lengthInBytes, 0); + // done here + return true; -// case AccessMemory_Read: -// // use FLASH driver to perform read operation -// // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h -// STM32FlashDriver_Read(NULL, location, lengthInBytes, buffer); -// return true; + case AccessMemory_Read: + // use FLASH driver to perform read operation + SL_MscFlashDriver_Read(NULL, location, lengthInBytes, buffer); + return true; -// default: -// // default return is FALSE -// return false; -// } -// } + default: + // default return is FALSE + return false; + } +} -// //////////////////////////////////////////////////// +//////////////////////////////////////////////////// // int Monitor_Reboot(WP_Message *message) // { From 5900d59f044dec7c4fd0656e2b95b09aa8401941 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 01:33:25 +0100 Subject: [PATCH 009/572] Fix linker file - Now includes managed heap, config section, etc. --- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 8 +-- .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 36 ++++++++------ .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 49 +++++++++++++------ 3 files changed, 60 insertions(+), 33 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 47c66022d5..fffa820659 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -39,11 +39,11 @@ nf_setup_target_build( SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - # BOOTER_EXTRA_LINKMAP_PROPERTIES - # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x4000" + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common,--defsym=__crt_heap_size__=0x4000" - # CLR_EXTRA_LINKMAP_PROPERTIES - # ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/ST/_common,--defsym=__main_stack_size__=0x200,--defsym=__process_stack_size__=0x0,--defsym=__crt_heap_size__=0x2000" + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common,--defsym=__crt_heap_size__=0x2000" ) # make vars global diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index e81afa95f8..28c9959ee0 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -32,13 +32,15 @@ __RAM_segment_used_end__ = 0; MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 2097152 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 524288 - config (rw) : ORIGIN = 0x00000000, len = 0 /* space reserved for configuration block */ + flash0 (rx) : org = 0x00000000, len = 44k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00000000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ } /* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. + * with other linker script that defines memory regions flash0 and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * @@ -72,10 +74,8 @@ MEMORY */ ENTRY(Reset_Handler) -__nanoConfig_start__ = ORIGIN(config); -__nanoConfig_size__ = LENGTH(config); -__nanoConfig_end__ = __nanoConfig_start__ + __nanoConfig_size__; - +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); SECTIONS { @@ -108,18 +108,18 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - } > FLASH + } > flash0 .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH + } > flash0 __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH + } > flash0 __exidx_end = .; /* To copy multiple ROM to RAM sections, @@ -137,7 +137,7 @@ SECTIONS LONG (__data2_start__) LONG (__data2_end__ - __data2_start__) __copy_table_end__ = .; - } > FLASH + } > flash0 */ /* To clear multiple BSS sections, @@ -153,7 +153,7 @@ SECTIONS LONG (__bss2_start__) LONG (__bss2_end__ - __bss2_start__) __zero_table_end__ = .; - } > FLASH + } > flash0 */ __etext = .; @@ -232,6 +232,12 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") } + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 12726e390c..5453d92ad2 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,13 +32,15 @@ __RAM_segment_used_end__ = 0; MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x200000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x80000 - config (rw) : ORIGIN = 0x00000000, len = 0 /* space reserved for configuration block */ + flash0 (rx) : org = 0x00008000, len = 2M - 44k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x080C0000, len = 908k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ } /* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. + * with other linker script that defines memory regions flash0 and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * @@ -72,10 +74,11 @@ MEMORY */ ENTRY(Reset_Handler) -__nanoConfig_start__ = ORIGIN(config); -__nanoConfig_size__ = LENGTH(config); -__nanoConfig_end__ = __nanoConfig_start__ + __nanoConfig_size__; +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); SECTIONS { @@ -108,18 +111,18 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) - } > FLASH + } > flash0 .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH + } > flash0 __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH + } > flash0 __exidx_end = .; /* To copy multiple ROM to RAM sections, @@ -137,7 +140,7 @@ SECTIONS LONG (__data2_start__) LONG (__data2_end__ - __data2_start__) __copy_table_end__ = .; - } > FLASH + } > flash0 */ /* To clear multiple BSS sections, @@ -153,7 +156,7 @@ SECTIONS LONG (__bss2_start__) LONG (__bss2_end__ - __bss2_start__) __zero_table_end__ = .; - } > FLASH + } > flash0 */ __etext = .; @@ -223,6 +226,18 @@ SECTIONS KEEP(*(.stack*)) } > RAM + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ __StackTop = ORIGIN(RAM) + LENGTH(RAM); @@ -232,6 +247,12 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - /* Check if FLASH usage exceeds FLASH size */ - ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") } + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld From 1440b6ddb98a538fc7bcf68cccc637168b567747 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 01:33:55 +0100 Subject: [PATCH 010/572] Update WP baud rate to 921600 --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md | 2 ++ .../SL_STK3701A/config/sl_iostream_usart_vcom_config.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md new file mode 100644 index 0000000000..b7afefe0b2 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -0,0 +1,2 @@ +Setting the VCP baud rate to 921600 +https://community.silabs.com/s/article/kba-bt-1208-using-virtual-com-port-vcom-x \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h index e3dd619a75..e596b6c1eb 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h @@ -37,7 +37,7 @@ // Baud rate // Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 // Parity mode to use // No Parity From 1cf0599fd7ce5e67f5e9a6a8fb0014315f34e7b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 01:34:23 +0100 Subject: [PATCH 011/572] Fix memory map --- .../common/Device_BlockStorage-DEBUG.c | 21 +++++++++---------- .../SL_STK3701A/target_common.h.in | 6 +++--- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c index 39d1668d73..28c0f7e74e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -9,13 +9,13 @@ // 2kB blocks const BlockRange BlockRange1[] = { - // 08000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 9}, - // 08008000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 16, 237}, + // 00008000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 10, 237}, - // 08077000 deployment + // 00077000 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 509}, /////////////////////////////////////////////////////////////////////////////////////// @@ -23,24 +23,23 @@ const BlockRange BlockRange1[] = { // configuration manager files to the CMake and call ConfigurationManager_Initialize() // in nanoBooter so the configuration can be managed when in booter mode /////////////////////////////////////////////////////////////////////////////////////// - // 080FF000 configuration block + // 001FF000 configuration block {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, /////////////////////////////////////////////////////////////////////////////////////// }; const BlockRegionInfo BlockRegions[] = { { - // STM32L4 flash requires 64bits width programming - (BlockRegionAttribute_ProgramWidthIs64bits), + (0), // start address for block region - 0x08000000, + 0x00000000, // total number of blocks in this region 512, // total number of bytes per block - 0x800, + 0x1000, ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, @@ -49,7 +48,7 @@ const BlockRegionInfo BlockRegions[] = { const DeviceBlockInfo Device_BlockInfo = { - // STM32 flash memory is XIP + // GG11 flash memory is XIP (MediaAttribute_SupportsXIP), // UINT32 BytesPerSector diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in index f62324c82a..a3d794155d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in @@ -18,12 +18,12 @@ // they also must be coherent with what's in the linker file for nanoBooter and nanoCLR // RAM base address -#define RAM1_MEMORY_StartAddress ((uint32_t)0x10000000) +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) // RAM size -#define RAM1_MEMORY_Size ((uint32_t)0x00008000) +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) // FLASH base address -#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) // FLASH size #define FLASH1_MEMORY_Size ((uint32_t)0x00100000) From ca0ad9838a3263560705fb400c0cf017b65cdc6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 01:34:52 +0100 Subject: [PATCH 012/572] Add missing platform files --- .../SiliconLabs/_common/CMakeLists.txt | 6 +- .../AzureRTOS/SiliconLabs/_common/LaunchCLR.c | 84 +++++++++++++++++++ .../_common/platform_BlockStorage.c | 22 +++++ .../_include/Target_GenericPort_stdio.h | 23 +++++ 4 files changed, 132 insertions(+), 3 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/platform_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/_include/Target_GenericPort_stdio.h diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index 69029c2dcc..b0322128b3 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -8,9 +8,9 @@ list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_B list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c) # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c) -# # append Target files -# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c) -# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/LaunchCLR.c) +# append Target files +list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c) +list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/LaunchCLR.c) # include configuration manager file, if feature is enabled if(NF_FEATURE_HAS_CONFIG_BLOCK) diff --git a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c new file mode 100644 index 0000000000..83078e09f1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c @@ -0,0 +1,84 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +void LaunchCLR(uint32_t address) +{ + // function pointer to load nanoCLR ResetHandler address + irq_vector_t JumpToNanoCLR; + + // load nanoCLR vector table + const vectors_t *nanoCLRVectorTable = (vectors_t *)address; + + // load the jump address with the nanoCLR ResetHandler address + JumpToNanoCLR = nanoCLRVectorTable->ResetHandler; + + // disable all interrupts + // __disable_irq(); + + // clear any pending interrupts to make sure we are jumping straight to nanoCLR ResetHandler + // SCB->ICSR &= SCB_ICSR_PENDSVCLR_Msk; + + // need to set stack pointer from CLR vector table + // __set_MSP((uint32_t)nanoCLRVectorTable->InitStack); + + // make the jump to nanoCLR, at last + JumpToNanoCLR(); +} + +bool CheckValidCLRImage(uint32_t address) +{ + uint32_t resetVectorAddress; + + // load nanoCLR vector table + const vectors_t *nanoCLRVectorTable = (vectors_t *)address; + + // 1st check: the flash content pointed by the address can't be all 0's neither all F's + // meaning that the Flash is neither 'all burnt' or erased + if ((uint32_t)(*(uint32_t **)((uint32_t *)address)) == 0xFFFFFFFF || + (uint32_t)(*(uint32_t **)((uint32_t *)address)) == 0x00000000) + { + // check failed, there is no valid CLR image + return false; + } + +// 2nd check: the content pointed by the reset vector has to be 0xE002 +// that's an assembly "b.n" (branch instruction) the very first one in the Reset_Handler function +// see os\common\startup\ARMCMx\compilers\GCC\vectors.S + + // "regular" address mapping + resetVectorAddress = (uint32_t)((uint32_t *)nanoCLRVectorTable->ResetHandler); + + // sanity check for invalid address (out of flash range which causes a hard fault) + if (resetVectorAddress <= FLASH1_MEMORY_StartAddress || + resetVectorAddress >= (FLASH1_MEMORY_StartAddress + FLASH1_MEMORY_Size)) + { + // check failed, doesn't seem to be a valid CLR image + return false; + } + + // the linker can place this anywhere on the address space because of optimizations so we better check where the + // reset pointer points to + uint32_t opCodeAddress = (uint32_t)((uint32_t **)nanoCLRVectorTable->ResetHandler); + + // real address is -1 + opCodeAddress -= 1; + + uint32_t opCode = *((uint32_t *)opCodeAddress); + if ((uint16_t)opCode == 0xE002) + { + // check, there seems to be a valid CLR image + return true; + } + else + { + // got here so there isn't a valid CLR imaged flashed + return false; + } +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/platform_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/_common/platform_BlockStorage.c new file mode 100644 index 0000000000..f81dfb9356 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/platform_BlockStorage.c @@ -0,0 +1,22 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// map here the Block Storage Interface to the SL_Msc driver +IBlockStorageDevice SL_MscFlash_BlockStorageInterface = +{ + &SL_MscFlashDriver_InitializeDevice, + &SL_MscFlashDriver_UninitializeDevice, + &SL_MscFlashDriver_GetDeviceInfo, + &SL_MscFlashDriver_Read, + &SL_MscFlashDriver_Write, + NULL, + &SL_MscFlashDriver_IsBlockErased, + &SL_MscFlashDriver_EraseBlock, + NULL, + NULL +}; diff --git a/targets/AzureRTOS/SiliconLabs/_include/Target_GenericPort_stdio.h b/targets/AzureRTOS/SiliconLabs/_include/Target_GenericPort_stdio.h new file mode 100644 index 0000000000..e025c16e1e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/Target_GenericPort_stdio.h @@ -0,0 +1,23 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGET_GENERIC_PORT_STDIO_H +#define TARGET_GENERIC_PORT_STDIO_H + +#include +#include + +// // the following macro defines a function that configures the GPIO pins for a STM32 UART/USART +// // this is required because the UART/USART peripherals can use multiple GPIO configuration combinations +// #define STDIO_UART_CONFIG_PINS(gpio_port_tx, gpio_port_rx, tx_pin, rx_pin, alternate_function) \ +// void StdioConfigPins_UART() \ +// { \ +// palSetPadMode(gpio_port_tx, tx_pin, PAL_MODE_ALTERNATE(alternate_function)); \ +// palSetPadMode(gpio_port_rx, rx_pin, PAL_MODE_ALTERNATE(alternate_function)); \ +// } + +// void StdioConfigPins_UART(void); + +#endif // TARGET_GENERIC_PORT_STDIO_H From af05def8d1ca3bdf94cd262ee673a947c6bfb579 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 01:43:23 +0100 Subject: [PATCH 013/572] Add block storage to bootloader --- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 6 ++--- .../SL_STK3701A/target_BlockStorage.c | 22 +++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 6936299bc0..638f94b67d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -13,7 +13,7 @@ #include -// #include +#include // #include // byte pool configuration and definitions @@ -81,8 +81,8 @@ void tx_application_define(void *first_unused_memory) // initialize block storage list and devices // in CLR this is called in nanoHAL_Initialize() // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - // BlockStorageList_Initialize(); - // BlockStorage_AddDevices(); + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); // initialize configuration manager // in CLR this is called in nanoHAL_Initialize() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c index e0e9fe93fc..ad32a4cff7 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_BlockStorage.c @@ -5,15 +5,15 @@ #include -// extern struct BlockStorageDevice Device_BlockStorage; -// extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; -// extern IBlockStorageDevice STM32Flash_BlockStorageInterface; +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; -// void BlockStorage_AddDevices() -// { -// BlockStorageList_AddDevice( -// (BlockStorageDevice *)&Device_BlockStorage, -// &STM32Flash_BlockStorageInterface, -// &Device_BlockStorageConfig, -// false); -// } +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} From b92340ec150fa5bf3f1b632d4e5e8b83fe37d5a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 01:43:41 +0100 Subject: [PATCH 014/572] Add back Monitor_Reboot implementation --- .../WireProtocol_MonitorCommands.c | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c b/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c index b791dd4743..28a62e2560 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoBooter/WireProtocol_MonitorCommands.c @@ -45,26 +45,26 @@ int AccessMemory(uint32_t location, uint32_t lengthInBytes, uint8_t *buffer, int //////////////////////////////////////////////////// -// int Monitor_Reboot(WP_Message *message) -// { -// Monitor_Reboot_Command *cmd = (Monitor_Reboot_Command *)message->m_payload; +int Monitor_Reboot(WP_Message *message) +{ + Monitor_Reboot_Command *cmd = (Monitor_Reboot_Command *)message->m_payload; -// WP_ReplyToCommand(message, true, false, NULL, 0); + WP_ReplyToCommand(message, true, false, NULL, 0); -// if (cmd != NULL) -// { -// if (Monitor_Reboot_c_EnterProprietaryBooter == (cmd->m_flags & Monitor_Reboot_c_EnterProprietaryBooter)) -// { -// // request to load proprietary bootloader -// // OK to call directly as this will launch the bootloader only if the target has support for it -// LaunchProprietaryBootloader(); -// } -// else -// { -// // RESET CPU to load nanoCLR -// NVIC_SystemReset(); -// } -// } + if (cmd != NULL) + { + if (Monitor_Reboot_c_EnterProprietaryBooter == (cmd->m_flags & Monitor_Reboot_c_EnterProprietaryBooter)) + { + // request to load proprietary bootloader + // OK to call directly as this will launch the bootloader only if the target has support for it + LaunchProprietaryBootloader(); + } + else + { + // RESET CPU to load nanoCLR + NVIC_SystemReset(); + } + } -// return true; -// } + return true; +} From d0bbcf9e67d5a84ff6eefa75fcce0721299fd5aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 02:14:41 +0100 Subject: [PATCH 015/572] Fix FPU compiler defs --- CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index f0a5421a1d..d8f6ad5cfe 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -34,7 +34,7 @@ macro(nf_set_compile_options) # enable: # - FPU # - DEBUG_EFM from Gecko SDK - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DDEBUG_EFM=1) + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=FALSE -DDEBUG_EFM=1) endmacro() From 9b1cbd51e1602ba1412b068b9db20ca27aa64368 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 02:15:12 +0100 Subject: [PATCH 016/572] Work on CLR launch from bootloader --- .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 2 +- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 35 +++++++++---------- .../AzureRTOS/SiliconLabs/_common/LaunchCLR.c | 14 ++++---- 3 files changed, 25 insertions(+), 26 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index 28c9959ee0..4e290c91ed 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -33,7 +33,7 @@ __RAM_segment_used_end__ = 0; MEMORY { flash0 (rx) : org = 0x00000000, len = 44k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00000000, len = 0 /* space reserved for application deployment */ + deployment (rx) : org = 0x00008000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 638f94b67d..ebd53f4297 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -70,9 +70,6 @@ void tx_application_define(void *first_unused_memory) // Create a byte memory pool from which to allocate the thread stacks. tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - // starts the serial driver - // sdStart(&SERIAL_DRIVER, NULL); - // #if (HAL_NF_USE_STM32_CRC == TRUE) // // startup crc // crcStart(NULL); @@ -165,22 +162,22 @@ int main(void) // the following IF is not mandatory, it's just providing a way for a user to 'force' // the board to remain in nanoBooter and not launching nanoCLR - // // check if there is a request to remain on nanoBooter - // if (!IsToRemainInBooter()) - // { - // // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter - // if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) - // { - // // check for valid CLR image - // // we are checking for a valid image at the deployment address, which is pointing to the CLR address - // if (CheckValidCLRImage((uint32_t)&__deployment_start__)) - // { - // // there seems to be a valid CLR image - // // launch nanoCLR - // LaunchCLR((uint32_t)&__deployment_start__); - // } - // } - // } + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + //if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } /*Set unbuffered mode for stdout (newlib)*/ // setvbuf(stdout, NULL, _IONBF, 0); diff --git a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c index 83078e09f1..915b09fe65 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c +++ b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c @@ -8,6 +8,8 @@ #include #include +#include + void LaunchCLR(uint32_t address) { // function pointer to load nanoCLR ResetHandler address @@ -20,13 +22,13 @@ void LaunchCLR(uint32_t address) JumpToNanoCLR = nanoCLRVectorTable->ResetHandler; // disable all interrupts - // __disable_irq(); + __disable_irq(); // clear any pending interrupts to make sure we are jumping straight to nanoCLR ResetHandler - // SCB->ICSR &= SCB_ICSR_PENDSVCLR_Msk; + SCB->ICSR &= SCB_ICSR_PENDSVCLR_Msk; // need to set stack pointer from CLR vector table - // __set_MSP((uint32_t)nanoCLRVectorTable->InitStack); + __set_MSP((uint32_t)nanoCLRVectorTable->InitStack); // make the jump to nanoCLR, at last JumpToNanoCLR(); @@ -48,9 +50,9 @@ bool CheckValidCLRImage(uint32_t address) return false; } -// 2nd check: the content pointed by the reset vector has to be 0xE002 -// that's an assembly "b.n" (branch instruction) the very first one in the Reset_Handler function -// see os\common\startup\ARMCMx\compilers\GCC\vectors.S + // 2nd check: the content pointed by the reset vector has to be 0xE002 + // that's an assembly "b.n" (branch instruction) the very first one in the Reset_Handler function + // see os\common\startup\ARMCMx\compilers\GCC\vectors.S // "regular" address mapping resetVectorAddress = (uint32_t)((uint32_t *)nanoCLRVectorTable->ResetHandler); From ae8cec50f6b380ac5e6be3bef15db5d545bf9be8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 10:01:19 +0100 Subject: [PATCH 017/572] Improvements in inclusion of series and board --- CMake/Modules/FindGecko_SDK.cmake | 7 +++++-- CMake/Modules/Gecko_SDK.cmake | 10 ++++++++++ targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 3 +++ .../AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 ++ 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index b9dce69af4..e7f357db8a 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -14,7 +14,8 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/board/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/Include) @@ -111,9 +112,11 @@ set(gecko_sdk_srcs ) -#series specific files +#series specific files and includes if("${TARGET_SERIES}" STREQUAL "EFM32GG11") + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Include) + list(APPEND gecko_sdk_srcs system_efm32gg11b.c) list(APPEND gecko_sdk_srcs startup_efm32gg11b.c) diff --git a/CMake/Modules/Gecko_SDK.cmake b/CMake/Modules/Gecko_SDK.cmake index f8dd2a9cc1..38d280f911 100644 --- a/CMake/Modules/Gecko_SDK.cmake +++ b/CMake/Modules/Gecko_SDK.cmake @@ -4,3 +4,13 @@ # include(FetchContent) + +macro(ProcessGSDKPackage) + + # process target name, which is in the format "SL_xxxxxxxx" + string(REPLACE "SL_" "SL" TARGET_BOARD_SHORT "${TARGET_BOARD}") + + # store the target name for later use + set(TARGET_BOARD_SHORT ${TARGET_BOARD_SHORT} CACHE INTERNAL "Gecko SDK board short name") + +endmacro() diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 0dfe088850..b199fd18c7 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -4,9 +4,12 @@ # include(binutils.common) +include(Gecko_SDK) set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) +ProcessGSDKPackage() + # check if GECKO_SDK_SOURCE was specified or if it's empty (default is empty) set(NO_GECKO_SDK_SOURCE TRUE) if(GECKO_SDK_SOURCE) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index fffa820659..201117a51b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -13,6 +13,8 @@ set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable T # set(STM32_DRIVER_TARGET_DEVICE STM32L475xx CACHE BOOL "Set STM32 target for HAL Driver") +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) # add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) From 9f1c6e892c6a43fb86627dec9f077e456762bac9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 10:16:24 +0100 Subject: [PATCH 018/572] Rework implementation of LED on booter - Remove SDK LED driver from build. - Replace with simple GPIO access. --- CMake/Modules/FindGecko_SDK.cmake | 7 --- .../autogen/sl_simple_led_instances.c | 63 ------------------- .../autogen/sl_simple_led_instances.h | 33 ---------- .../config/sl_simple_led_led0_config.h | 44 ------------- .../config/sl_simple_led_led1_config.h | 44 ------------- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 29 +++++---- .../_common/autogen/sl_event_handler.c | 2 - 7 files changed, 16 insertions(+), 206 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index e7f357db8a..173e33897f 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -33,7 +33,6 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/slee list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/leddrv/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) @@ -104,12 +103,7 @@ set(gecko_sdk_srcs sl_iostream_handles.c sl_iostream_init_usart_instances.c - sl_led.c - sl_simple_led.c - # autogen at target level - sl_simple_led_instances.c - ) #series specific files and includes @@ -142,7 +136,6 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") ${gecko_sdk_SOURCE_DIR}/platform/service/system/src ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/src ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/src - ${gecko_sdk_SOURCE_DIR}/platform/driver/leddrv/src # device specific paths ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c deleted file mode 100644 index e8d0624c39..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.c +++ /dev/null @@ -1,63 +0,0 @@ -/***************************************************************************//** - * @file - * @brief LED Driver Instances - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_simple_led.h" -#include "em_gpio.h" -#include "sl_simple_led_led0_config.h" -#include "sl_simple_led_led1_config.h" - -sl_simple_led_context_t simple_led0_context = { - .port = SL_SIMPLE_LED_LED0_PORT, - .pin = SL_SIMPLE_LED_LED0_PIN, - .polarity = SL_SIMPLE_LED_LED0_POLARITY, -}; - -sl_simple_led_context_t simple_led1_context = { - .port = SL_SIMPLE_LED_LED1_PORT, - .pin = SL_SIMPLE_LED_LED1_PIN, - .polarity = SL_SIMPLE_LED_LED1_POLARITY, -}; - -const sl_led_t sl_led_led0 = { - .context = &simple_led0_context, - .init = sl_simple_led_init, - .turn_on = sl_simple_led_turn_on, - .turn_off = sl_simple_led_turn_off, - .toggle = sl_simple_led_toggle, - .get_state = sl_simple_led_get_state, -}; - - -const sl_led_t sl_led_led1 = { - .context = &simple_led1_context, - .init = sl_simple_led_init, - .turn_on = sl_simple_led_turn_on, - .turn_off = sl_simple_led_turn_off, - .toggle = sl_simple_led_toggle, - .get_state = sl_simple_led_get_state, -}; - -const sl_led_t *sl_simple_led_array[] = { - &sl_led_led0, - &sl_led_led1 -}; - -void sl_simple_led_init_instances(void) -{ - sl_led_init(&sl_led_led0); - sl_led_init(&sl_led_led1); -} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h deleted file mode 100644 index f96e8d0232..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_simple_led_instances.h +++ /dev/null @@ -1,33 +0,0 @@ -/***************************************************************************//** - * @file - * @brief LED Driver Instances - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_INSTANCES_H -#define SL_SIMPLE_LED_INSTANCES_H - -#include "sl_simple_led.h" - -extern const sl_led_t sl_led_led0; -extern const sl_led_t sl_led_led1; - -extern const sl_led_t *sl_simple_led_array[]; - -#define SL_SIMPLE_LED_COUNT 2 -#define SL_SIMPLE_LED_INSTANCE(n) (sl_simple_led_array[n]) - -void sl_simple_led_init_instances(void); - -#endif // SL_SIMPLE_LED_INIT_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h deleted file mode 100644 index 33b25efd3d..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led0_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED0_CONFIG_H -#define SL_SIMPLE_LED_LED0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED0_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED0 -// $[GPIO_SL_SIMPLE_LED_LED0] -#define SL_SIMPLE_LED_LED0_PORT gpioPortH -#define SL_SIMPLE_LED_LED0_PIN 10 - -// [GPIO_SL_SIMPLE_LED_LED0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h deleted file mode 100644 index 570c4b6c01..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_simple_led_led1_config.h +++ /dev/null @@ -1,44 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Simple Led Driver Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_LED_LED1_CONFIG_H -#define SL_SIMPLE_LED_LED1_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Simple LED configuration -// -// Active low -// Active high -// Default: SL_SIMPLE_LED_POLARITY_ACTIVE_HIGH -#define SL_SIMPLE_LED_LED1_POLARITY SL_SIMPLE_LED_POLARITY_ACTIVE_LOW -// end led configuration - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_SIMPLE_LED_LED0 -// $[GPIO_SL_SIMPLE_LED_LED0] -#define SL_SIMPLE_LED_LED1_PORT gpioPortH -#define SL_SIMPLE_LED_LED1_PIN 14 - -// [GPIO_SL_SIMPLE_LED_LED0]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_SIMPLE_LED_LED1_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index ebd53f4297..39f1b696a5 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include @@ -46,7 +46,7 @@ void BlinkThread_entry(uint32_t parameter) while (1) { - sl_led_toggle(&sl_led_led0); + GPIO_PinOutToggle(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN); tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); } } @@ -58,7 +58,7 @@ void BlinkThread1_entry(uint32_t parameter) while (1) { tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); - sl_led_toggle(&sl_led_led1); + GPIO_PinOutToggle(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN); } } @@ -70,10 +70,10 @@ void tx_application_define(void *first_unused_memory) // Create a byte memory pool from which to allocate the thread stacks. tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); -// #if (HAL_NF_USE_STM32_CRC == TRUE) -// // startup crc -// crcStart(NULL); -// #endif + // #if (HAL_NF_USE_STM32_CRC == TRUE) + // // startup crc + // crcStart(NULL); + // #endif // initialize block storage list and devices // in CLR this is called in nanoHAL_Initialize() @@ -156,6 +156,10 @@ int main(void) // Initialize the board sl_system_init(); + // Configure LED0 and LED1 as output + GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN, gpioModePushPull, 0); + GPIO_PinModeSet(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN, gpioModePushPull, 0); + // init boot clipboard InitBootClipboard(); @@ -166,7 +170,7 @@ int main(void) if (!IsToRemainInBooter()) { // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter - //if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) + // if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) { // check for valid CLR image // we are checking for a valid image at the deployment address, which is pointing to the CLR address @@ -179,11 +183,10 @@ int main(void) } } -/*Set unbuffered mode for stdout (newlib)*/ -// setvbuf(stdout, NULL, _IONBF, 0); -// /*Set unbuffered mode for stdin (newlib)*/ -// setvbuf(stdin, NULL, _IONBF, 0); - + /*Set unbuffered mode for stdout (newlib)*/ + // setvbuf(stdout, NULL, _IONBF, 0); + // /*Set unbuffered mode for stdin (newlib)*/ + // setvbuf(stdin, NULL, _IONBF, 0); // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running sl_system_kernel_start(); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c index 9c44014998..955d4ece92 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c @@ -20,7 +20,6 @@ #include "sl_uartdrv_instances.h" #include "sl_iostream_init_usart_instances.h" #include "sl_iostream_init_instances.h" -#include "sl_simple_led_instances.h" #include "sl_i2cspm_instances.h" #include "sl_power_manager.h" @@ -51,7 +50,6 @@ void sl_driver_init(void) GPIOINT_Init(); // sl_i2cspm_init_instances(); sl_uartdrv_init_instances(); - sl_simple_led_init_instances(); } void sl_service_init(void) From 615c84caa5c17663a6b30ccec697c4a29de1a751 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 10:28:34 +0100 Subject: [PATCH 019/572] Implement remain on booter feature --- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 39f1b696a5..0e44d35498 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -160,6 +160,10 @@ int main(void) GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN, gpioModePushPull, 0); GPIO_PinModeSet(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN, gpioModePushPull, 0); + // configure + GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInputPullFilter, 1); + + // init boot clipboard InitBootClipboard(); @@ -169,8 +173,8 @@ int main(void) // check if there is a request to remain on nanoBooter if (!IsToRemainInBooter()) { - // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter - // if (palReadPad(GPIOC, GPIOC_BUTTON_USER)) + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN)) { // check for valid CLR image // we are checking for a valid image at the deployment address, which is pointing to the CLR address @@ -183,11 +187,6 @@ int main(void) } } - /*Set unbuffered mode for stdout (newlib)*/ - // setvbuf(stdout, NULL, _IONBF, 0); - // /*Set unbuffered mode for stdin (newlib)*/ - // setvbuf(stdin, NULL, _IONBF, 0); - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running sl_system_kernel_start(); } From 6b407929074d66a9516d3acdf9bb0e939bd7d0bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 11:00:03 +0100 Subject: [PATCH 020/572] Fix block storage config and linker file --- .../SL_STK3701A/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld | 2 +- .../SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c index 28c0f7e74e..e04c645491 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -12,10 +12,10 @@ const BlockRange BlockRange1[] = { // 00000000 nanoBooter {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 9}, - // 00008000 nanoCLR + // 0000A000 nanoCLR {BlockRange_BLOCKTYPE_CODE, 10, 237}, - // 00077000 deployment + // 000EE000 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 509}, /////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index 4e290c91ed..ae513222dc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -33,7 +33,7 @@ __RAM_segment_used_end__ = 0; MEMORY { flash0 (rx) : org = 0x00000000, len = 44k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00008000, len = 0 /* space reserved for application deployment */ + deployment (rx) : org = 0x0000A000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 5453d92ad2..0bb48b6ad8 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,11 +32,11 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00008000, len = 2M - 44k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x080C0000, len = 908k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ + flash0 (rx) : org = 0x0000A000, len = 2M - 44k - 4k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 908k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ } /* Linker script to place sections and symbol values. Should be used together From cd85e123a6963a1b0ccef283d003ed34b0265b62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 11:00:24 +0100 Subject: [PATCH 021/572] Fix launch CLR check for Gecko SDK --- targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c index 915b09fe65..077bd50dcf 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c +++ b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c @@ -50,9 +50,9 @@ bool CheckValidCLRImage(uint32_t address) return false; } - // 2nd check: the content pointed by the reset vector has to be 0xE002 - // that's an assembly "b.n" (branch instruction) the very first one in the Reset_Handler function - // see os\common\startup\ARMCMx\compilers\GCC\vectors.S + // 2nd check: the content pointed by the reset vector has to be 0xB510 + // that's an assembly "push {r4, lr}" the very first one in the Reset_Handler function + // see platform\Device\SiliconLabs\EFM32GG11B\Source\GCC\startup_efm32gg11b.c // "regular" address mapping resetVectorAddress = (uint32_t)((uint32_t *)nanoCLRVectorTable->ResetHandler); From 5a43df5bc9ec46161fa21a1c1a9d230ec746d757 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 9 Jun 2022 11:34:38 +0100 Subject: [PATCH 022/572] Fix option name in nf_set_compile_options --- CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake | 2 +- CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake | 2 +- CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake | 2 +- CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake | 2 +- CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake | 2 +- CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake | 2 +- CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake | 2 +- CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake | 2 +- CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake | 2 +- CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake | 2 +- CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake | 2 +- CMake/Modules/CHIBIOS_STM32L4xx_GCC_options.cmake | 2 +- CMake/Modules/ESP32_GCC_options.cmake | 2 +- CMake/Modules/ESP32_S2_GCC_options.cmake | 2 +- CMake/Modules/FreeRTOS_IMXRT10xx_GCC_options.cmake | 2 +- CMake/Modules/TI_SimpleLink_CC13X2_GCC_options.cmake | 2 +- CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake | 2 +- 17 files changed, 17 insertions(+), 17 deletions(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index d8f6ad5cfe..1c79c6e180 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -29,7 +29,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU diff --git a/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake b/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake index d0af96942c..bb1ec47f9d 100644 --- a/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake @@ -25,7 +25,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # can't include -Wundef because of MAXIM SDK - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mfpu=fpv4-sp-d16 -mfloat-abi=soft -Wa,-mimplicit-it=thumb -Wall -Wextra -Werror -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mfpu=fpv4-sp-d16 -mfloat-abi=soft -Wa,-mimplicit-it=thumb -Wall -Wextra -Werror -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DTARGET=MAX78000 -DTARGET_REV=0x4131 -DFTHR_RevA ) diff --git a/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake b/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake index 5c91424175..3376589d61 100644 --- a/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake @@ -27,7 +27,7 @@ macro(nf_set_compile_options) endif() # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE) diff --git a/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake b/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake index 0f0418060e..68fa72f417 100644 --- a/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake @@ -25,7 +25,7 @@ macro(nf_set_compile_options) endif() # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m0plus -mtune=cortex-m0plus -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m0plus -mtune=cortex-m0plus -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # this series doesn't have FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DUSE_FPU=FALSE) diff --git a/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake b/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake index b832f51c96..ff338f48fc 100644 --- a/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake @@ -29,7 +29,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU diff --git a/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake b/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake index 3e356d4540..944d24cc04 100644 --- a/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake @@ -30,7 +30,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # STMF7 cores have SP and DP, the default is SP. DP can be set if developer realy needs that. # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # enable: # - FPU diff --git a/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake b/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake index b832f51c96..ff338f48fc 100644 --- a/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake @@ -29,7 +29,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU diff --git a/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake b/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake index cdab7ae22b..0472e7f54a 100644 --- a/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake +++ b/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake @@ -27,7 +27,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake b/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake index ed0b609b2f..78373cb95c 100644 --- a/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake +++ b/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake @@ -27,7 +27,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # STMF7 cores have SP and DP, the default is SP. DP can be set if developer realy needs that. - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake b/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake index 2498d8ed32..e5f31b71d9 100644 --- a/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake +++ b/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake @@ -28,7 +28,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # STMF7 cores have SP and DP, the default is SP. DP can be set if developer realy needs that. - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake b/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake index e21672ddba..74638004bb 100644 --- a/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake +++ b/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake @@ -31,7 +31,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m0plus -mfloat-abi=soft -mabi=aapcs -mtune=cortex-m0plus -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m0plus -mfloat-abi=soft -mabi=aapcs -mtune=cortex-m0plus -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # this series doesn't have FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/CHIBIOS_STM32L4xx_GCC_options.cmake b/CMake/Modules/CHIBIOS_STM32L4xx_GCC_options.cmake index 95ea65a7a2..c05bf7f3e8 100644 --- a/CMake/Modules/CHIBIOS_STM32L4xx_GCC_options.cmake +++ b/CMake/Modules/CHIBIOS_STM32L4xx_GCC_options.cmake @@ -27,7 +27,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/ESP32_GCC_options.cmake b/CMake/Modules/ESP32_GCC_options.cmake index 5e6b799382..cfd2e57cc4 100644 --- a/CMake/Modules/ESP32_GCC_options.cmake +++ b/CMake/Modules/ESP32_GCC_options.cmake @@ -19,7 +19,7 @@ macro(nf_set_compile_options) endif() # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -Wall -Wextra -Werror -Wno-unused-parameter -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -Wall -Wextra -Werror -Wno-unused-parameter -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -fno-exceptions -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DTARGET=esp32 -DUSE_FPU=TRUE -DPLATFORM_ESP32) diff --git a/CMake/Modules/ESP32_S2_GCC_options.cmake b/CMake/Modules/ESP32_S2_GCC_options.cmake index 71c8c11f9d..01a124db19 100644 --- a/CMake/Modules/ESP32_S2_GCC_options.cmake +++ b/CMake/Modules/ESP32_S2_GCC_options.cmake @@ -18,7 +18,7 @@ macro(nf_set_compile_options) endif() # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -Wall -Wextra -Werror -Wno-unused-parameter -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -fno-exceptions -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -Wall -Wextra -Werror -Wno-unused-parameter -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -fno-exceptions -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DTARGET=esp32s2 -DUSE_FPU=TRUE -DPLATFORM_ESP32) diff --git a/CMake/Modules/FreeRTOS_IMXRT10xx_GCC_options.cmake b/CMake/Modules/FreeRTOS_IMXRT10xx_GCC_options.cmake index 63484c5df8..18a6f57d5b 100644 --- a/CMake/Modules/FreeRTOS_IMXRT10xx_GCC_options.cmake +++ b/CMake/Modules/FreeRTOS_IMXRT10xx_GCC_options.cmake @@ -28,7 +28,7 @@ macro(nf_set_compile_options) # include any extra options comming from any extra args? # TODO: removed -Wundef until fix with FatFS is merged (https://github.com/abbrev/fatfs/pull/8) - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/TI_SimpleLink_CC13X2_GCC_options.cmake b/CMake/Modules/TI_SimpleLink_CC13X2_GCC_options.cmake index 64369fcca9..58a054eb2d 100644 --- a/CMake/Modules/TI_SimpleLink_CC13X2_GCC_options.cmake +++ b/CMake/Modules/TI_SimpleLink_CC13X2_GCC_options.cmake @@ -30,7 +30,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -w -static -ffunction-sections -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -w -static -ffunction-sections -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake index 71e72af045..d70778418d 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake @@ -28,7 +28,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -w -static -ffunction-sections -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -w -static -ffunction-sections -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) # this series has FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE) From f47c106e64e0711c2d1e05b5da864be4b5aad0c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 12:04:41 +0100 Subject: [PATCH 023/572] Rework configuration of CRT stack and heap size - Now they are set through a define in the target CMake. - Remove inclusion of sl memory as it wasn't being useful at all. --- CMake/Modules/FindGecko_SDK.cmake | 3 +- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 8 ++++-- .../_common/config/sl_memory_config.h | 28 ------------------- 3 files changed, 7 insertions(+), 32 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 173e33897f..905d1f4783 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -17,6 +17,7 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/board/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/Include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/RTOS2/Include) @@ -41,8 +42,6 @@ set(gecko_sdk_srcs sl_board_control_gpio.c sl_board_init.c - sl_memory.c - em_acmp.c em_adc.c em_assert.c diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 201117a51b..0eb9216aad 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -33,6 +33,8 @@ nf_setup_target_build( SL_BOARD_REV=\"B07\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 + __STACK_SIZE=4096 + __HEAP_SIZE=2048 CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -40,12 +42,14 @@ nf_setup_target_build( SL_BOARD_REV=\"B07\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 + __STACK_SIZE=4096 + __HEAP_SIZE=2048 BOOTER_EXTRA_LINKMAP_PROPERTIES - ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common,--defsym=__crt_heap_size__=0x4000" + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" CLR_EXTRA_LINKMAP_PROPERTIES - ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common,--defsym=__crt_heap_size__=0x2000" + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" ) # make vars global diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h deleted file mode 100644 index b43ebcba02..0000000000 --- a/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef SL_MEMORY_CONFIG_H -#define SL_MEMORY_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Memory configuration - -// Stack size for the application. -// Default: 4096 -// The stack size configured here will be used by the stack that the -// application uses when coming out of a reset. -#ifndef SL_STACK_SIZE - #define SL_STACK_SIZE 4096 -#endif - -// Minimum heap size for the application. -// Default: 2048 -// Note that this value will configure the c heap which is normally used by -// malloc() and free() from the c library. The value defines a minimum heap -// size that is guaranteed to be available. The available heap may be larger -// to make use of any memory that would otherwise remain unused. -#ifndef SL_HEAP_SIZE - #define SL_HEAP_SIZE 2048 -#endif - -// -// <<< end of configuration section >>> - -#endif From 20bdc4fd73e2706c1ef3d3d3f934afe2f5a0fe7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 12:20:39 +0100 Subject: [PATCH 024/572] Adjust heap and stack size for booter and CLR --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 0eb9216aad..7c6c372e03 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -33,8 +33,8 @@ nf_setup_target_build( SL_BOARD_REV=\"B07\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - __STACK_SIZE=4096 - __HEAP_SIZE=2048 + __STACK_SIZE=0x4000 + __HEAP_SIZE=0x4000 CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -42,8 +42,8 @@ nf_setup_target_build( SL_BOARD_REV=\"B07\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - __STACK_SIZE=4096 - __HEAP_SIZE=2048 + __STACK_SIZE=0x4000 + __HEAP_SIZE=0x4000 BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From 8eff2adee9065e19b19e1dc4f84665869f639add Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 12:43:49 +0100 Subject: [PATCH 025/572] Fix GPIO detection BTN0 --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 0e44d35498..e4e336bb13 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -161,7 +161,7 @@ int main(void) GPIO_PinModeSet(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN, gpioModePushPull, 0); // configure - GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInputPullFilter, 1); + GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInput, 0); // init boot clipboard From 59783d8dc4c2a433b4dce0fc33fc2c645b835698 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 14:03:36 +0100 Subject: [PATCH 026/572] Add VS Code task to erase GG11 flash --- .jlink/erase_gg11.jlink | 3 +++ .vscode/tasks.TEMPLATE.json | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 .jlink/erase_gg11.jlink diff --git a/.jlink/erase_gg11.jlink b/.jlink/erase_gg11.jlink new file mode 100644 index 0000000000..f859bf7395 --- /dev/null +++ b/.jlink/erase_gg11.jlink @@ -0,0 +1,3 @@ +speed auto +erase 0x0000000 0x001FF000 +Exit \ No newline at end of file diff --git a/.vscode/tasks.TEMPLATE.json b/.vscode/tasks.TEMPLATE.json index 26ce81a4b7..65a9f30935 100644 --- a/.vscode/tasks.TEMPLATE.json +++ b/.vscode/tasks.TEMPLATE.json @@ -55,6 +55,22 @@ "panel": "dedicated" }, "problemMatcher": [] + }, + { + "label": "Erase flash Silabs GG11", + "type": "shell", + "command": "${env:JLINK_PATH}/Jlink.exe -device default -si swd -CommandFile ${workspaceRoot}/.jlink/erase_gg11.jlink", + "windows": { + "options": { + "shell": { + "executable": "cmd.exe", + "args": [ + "/c" + ] + } + } + }, + "problemMatcher": [] } ], "inputs": [ From 2d86821307b9c8577e16ba232fc4a5a80521c62d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 14:35:21 +0100 Subject: [PATCH 027/572] Fix check for valid CLR image --- targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c index 077bd50dcf..5dc7d2e9ad 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c +++ b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c @@ -73,7 +73,7 @@ bool CheckValidCLRImage(uint32_t address) opCodeAddress -= 1; uint32_t opCode = *((uint32_t *)opCodeAddress); - if ((uint16_t)opCode == 0xE002) + if ((uint16_t)opCode == 0xB510) { // check, there seems to be a valid CLR image return true; From 6b6925f9517c35966d7d6811dc62d41298b5fb48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 9 Jun 2022 14:35:46 +0100 Subject: [PATCH 028/572] Fix check for proper GPIO state to remain on booter --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index e4e336bb13..914429da3f 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -163,7 +163,6 @@ int main(void) // configure GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInput, 0); - // init boot clipboard InitBootClipboard(); @@ -174,7 +173,7 @@ int main(void) if (!IsToRemainInBooter()) { // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter - if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN)) + if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN) != 0) { // check for valid CLR image // we are checking for a valid image at the deployment address, which is pointing to the CLR address From 3aa432f81a59c860e8fb90f6a1297bcade19149c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 10 Jun 2022 11:29:01 +0100 Subject: [PATCH 029/572] Fix block storage for config --- .../SL_STK3701A/common/Device_BlockStorage-DEBUG.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c index e04c645491..5c66fa5b98 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -16,7 +16,7 @@ const BlockRange BlockRange1[] = { {BlockRange_BLOCKTYPE_CODE, 10, 237}, // 000EE000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 509}, + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the @@ -24,7 +24,7 @@ const BlockRange BlockRange1[] = { // in nanoBooter so the configuration can be managed when in booter mode /////////////////////////////////////////////////////////////////////////////////////// // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, /////////////////////////////////////////////////////////////////////////////////////// }; From 4bc00f73696b7a377444b075660d6ec6cceaa688 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 10 Jun 2022 11:29:58 +0100 Subject: [PATCH 030/572] Add initial version of platform GPIO driver --- .../SiliconLabs/_include/targetPAL.h | 3 + .../_nanoCLR/System.Device.Gpio/cpu_gpio.cpp | 1013 +++++++++-------- .../sys_dev_gpio_native_target.h | 6 +- .../SiliconLabs/_nanoCLR/targetPAL.c | 22 + 4 files changed, 556 insertions(+), 488 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c diff --git a/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h b/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h index 1f7f186093..16d37d6c40 100644 --- a/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h +++ b/targets/AzureRTOS/SiliconLabs/_include/targetPAL.h @@ -6,4 +6,7 @@ #ifndef TARGETPAL_H #define TARGETPAL_H +// Gets the GPIO port according to a pin number +#define GPIO_PORT(pin) ((GPIO_Port_TypeDef)(pin / 16)) + #endif // TARGETPAL_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp index 789b2144e0..b10ab93051 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp @@ -9,490 +9,529 @@ #define GPIO_MAX_PIN 256 #define TOTAL_GPIO_PORTS ((GPIO_MAX_PIN + 15) / 16) -// // Double linkedlist to hold the state of each Input pin -// struct gpio_input_state : public HAL_DblLinkedNode -// { -// // Pin number -// GPIO_PIN pinNumber; -// // debounce timer for this Pin -// TX_TIMER debounceTimer; -// // Ptr to user ISR or null -// GPIO_INTERRUPT_SERVICE_ROUTINE isrPtr; -// // debounce Millsecs, no debonce=0 -// uint32_t debounceMs; -// // Interrupt mode -// uint8_t mode; -// // Param to user isr call -// void *param; -// // Expected state for debounce handler -// bool expected; -// // True if waiting for debounce timer to complete -// bool waitingDebounce; -// }; - -// static HAL_DblLinkedList gpioInputList; // Double Linked list for GPIO input status -// static uint16_t pinReserved[TOTAL_GPIO_PORTS]; // reserved - 1 bit per pin - -// // this is an utility function to get a ChibiOS PAL IoLine from our "encoded" pin number -// static ioline_t GetIoLine(int16_t pinNumber) -// { -// stm32_gpio_t *port = GPIO_PORT(pinNumber); -// int16_t pad = pinNumber % 16; - -// return PAL_LINE(port, pad); -// } - -// bool IsValidGpioPin(GPIO_PIN pinNumber) -// { -// return (pinNumber <= GPIO_MAX_PIN); -// } - -// // Get pointer to gpio_input_state for GPIO pin -// // return NULL if not found -// gpio_input_state *GetGpioWithInterrupt(uint16_t gpioPin) -// { -// gpio_input_state *ptr = gpioInputList.FirstNode(); -// while (ptr->Next() != NULL) -// { -// if (GPIO_PIN(ptr->pinNumber) == gpioPin) -// { -// return ptr; -// } - -// ptr = ptr->Next(); -// } - -// return NULL; -// } - -// static void DebounceTimerCallback(uint32_t id) -// { -// gpio_input_state *pState = (gpio_input_state *)id; - -// // get current pin state -// bool actual = palReadLine(GetIoLine(pState->pinNumber)); - -// if (actual == pState->expected) -// { -// pState->isrPtr(pState->pinNumber, actual, pState->param); -// if (pState->mode == GPIO_INT_EDGE_BOTH) -// { -// // both edges -// // update expected state -// pState->expected ^= 1; -// } -// } - -// pState->waitingDebounce = false; -// } - -// void GpioEventCallback(void *arg) -// { -// NATIVE_INTERRUPT_START - -// TX_DISABLE - -// gpio_input_state *pGpio = (gpio_input_state *)arg; - -// if (pGpio != NULL) -// { -// // Ignore any pin changes during debounce -// if (!pGpio->waitingDebounce) -// { -// // check if there is a debounce time set -// if (pGpio->debounceMs > 0) -// { -// // Set flag we are waiting for debounce on this pin -// pGpio->waitingDebounce = true; - -// // setup timer -// tx_timer_deactivate(&pGpio->debounceTimer); -// tx_timer_change(&pGpio->debounceTimer, 0, pGpio->debounceMs / 10); -// tx_timer_activate(&pGpio->debounceTimer); -// } -// else -// { -// // get IoLine from pin number -// ioline_t ioLine = GetIoLine(pGpio->pinNumber); - -// TX_RESTORE - -// pGpio->isrPtr(pGpio->pinNumber, palReadLine(ioLine), pGpio->param); - -// TX_DISABLE -// } -// } -// } - -// TX_RESTORE - -// NATIVE_INTERRUPT_END -// } - -// // Get pointer to gpio_input_state for Gpio pin -// // return NULL if not found -// gpio_input_state *GetInputState(GPIO_PIN pinNumber) -// { -// gpio_input_state *ptr = gpioInputList.FirstNode(); - -// while (ptr->Next() != NULL) -// { -// if (ptr->pinNumber == pinNumber) -// { -// return ptr; -// } - -// ptr = ptr->Next(); -// } - -// return NULL; -// } - -// // Allocate a new gpio_input_state and add to end of list -// // if already exist then just return current ptr -// gpio_input_state *AllocateGpioInputState(GPIO_PIN pinNumber) -// { -// gpio_input_state *ptr = GetInputState(pinNumber); - -// if (ptr == NULL) -// { -// ptr = (gpio_input_state *)platform_malloc(sizeof(gpio_input_state)); - -// // sanity check -// if (ptr != NULL) -// { -// memset(ptr, 0, sizeof(gpio_input_state)); -// ptr->pinNumber = pinNumber; - -// tx_timer_create( -// &ptr->debounceTimer, -// (char *)"GPIO debounce timer", -// DebounceTimerCallback, -// 0, -// 0, -// 1, -// TX_NO_ACTIVATE); - -// gpioInputList.LinkAtBack(ptr); -// } -// } - -// return ptr; -// } - -// void UnlinkInputState(gpio_input_state *pState) -// { -// tx_timer_delete(&pState->debounceTimer); - -// // disable the EXT interrupt channel -// // it's OK to do always this, no matter if it's enabled or not -// palDisableLineEvent(GetIoLine(pState->pinNumber)); - -// pState->Unlink(); - -// platform_free(pState); -// } - -// // Delete gpio_input_state from List and tidy up ( Timer & ISR handler ) -// void DeleteInputState(GPIO_PIN pinNumber) -// { -// gpio_input_state *pState = GetInputState(pinNumber); - -// if (pState) -// { -// UnlinkInputState(pState); -// } -// } - -// bool CPU_GPIO_Initialize() -// { -// // Initialise Double linked list for input pin states -// gpioInputList.Initialize(); - -// // Make sure all pins are not reserved -// memset(pinReserved, 0, sizeof(pinReserved)); - -// return true; -// } - -// bool CPU_GPIO_Uninitialize() -// { -// NANOCLR_FOREACH_NODE(gpio_input_state, pGpio, gpioInputList) -// { -// UnlinkInputState(pGpio); -// } -// NANOCLR_FOREACH_NODE_END(); - -// return true; -// } - -// // Set/reset reserved state of pin -// bool CPU_GPIO_ReservePin(GPIO_PIN pinNumber, bool fReserve) -// { -// // Check if valid pin number -// if (!IsValidGpioPin(pinNumber)) -// { -// return false; -// } - -// int port = pinNumber >> 4, bit = 1 << (pinNumber & 0x0F); -// bool ret = true; -// GLOBAL_LOCK(); - -// if (fReserve) -// { -// if (pinReserved[port] & bit) -// { -// ret = false; // already reserved -// } -// else -// { -// pinReserved[port] |= bit; -// } -// } -// else -// { -// pinReserved[port] &= ~bit; -// } - -// GLOBAL_UNLOCK(); -// return ret; -// } - -// // Return if Pin is reserved -// bool CPU_GPIO_PinIsBusy(GPIO_PIN pinNumber) -// { -// // Check if valid pin number -// if (!IsValidGpioPin(pinNumber)) -// { -// return false; -// } - -// int port = pinNumber >> 4, sh = pinNumber & 0x0F; -// return (pinReserved[port] >> sh) & 1; -// } - -// // Return maximum number of pins -// int32_t CPU_GPIO_GetPinCount() -// { -// return GPIO_MAX_PIN; -// } - -// // Get current state of pin -// GpioPinValue CPU_GPIO_GetPinState(GPIO_PIN pin) -// { -// return (GpioPinValue)palReadLine(GetIoLine(pin)); -// } - -// // Set Pin state -// void CPU_GPIO_SetPinState(GPIO_PIN pin, GpioPinValue pinState) -// { -// palWriteLine(GetIoLine(pin), (int)pinState); -// } - -// void CPU_GPIO_TogglePinState(GPIO_PIN pinNumber) -// { -// palToggleLine(GetIoLine(pinNumber)); -// } - -// bool CPU_GPIO_EnableInputPin( -// GPIO_PIN pinNumber, -// uint32_t debounceTimeMilliseconds, -// GPIO_INTERRUPT_SERVICE_ROUTINE pinISR, -// void *isrParam, -// GPIO_INT_EDGE intEdge, -// PinMode driveMode) -// { -// gpio_input_state *pState; - -// // Check Input drive mode -// if (driveMode >= (int)PinMode_Output) -// { -// return false; -// } - -// // Set as Input GPIO_INT_EDGE intEdge, GPIO_RESISTOR ResistorState -// if (!CPU_GPIO_SetDriveMode(pinNumber, driveMode)) -// { -// return false; -// } - -// pState = AllocateGpioInputState(pinNumber); - -// // Link ISR ptr supplied and not already set up -// // CPU_GPIO_EnableInputPin could be called a 2nd time with changed parameters -// if (pinISR != NULL && (pState->isrPtr == NULL)) -// { -// // there are callbacks registered and... -// // the drive mode is input so need to setup the interrupt - -// // get IoLine from pin number -// ioline_t ioLine = GetIoLine(pinNumber); - -// palEnableLineEvent(ioLine, PAL_EVENT_MODE_BOTH_EDGES); -// palSetLineCallback(ioLine, GpioEventCallback, pState); - -// // store parameters & configs -// pState->isrPtr = pinISR; -// pState->mode = intEdge; -// pState->param = (void *)isrParam; -// pState->debounceMs = (uint32_t)(debounceTimeMilliseconds); - -// switch (intEdge) -// { -// case GPIO_INT_EDGE_LOW: -// case GPIO_INT_LEVEL_LOW: -// pState->expected = PAL_LOW; -// break; - -// case GPIO_INT_EDGE_HIGH: -// case GPIO_INT_LEVEL_HIGH: -// pState->expected = PAL_HIGH; -// break; - -// case GPIO_INT_EDGE_BOTH: -// pState->expected = !CPU_GPIO_GetPinState(pinNumber); // expected NOT current state -// break; - -// default: -// break; -// } -// } -// else if (pinISR == NULL && (pState->isrPtr != NULL)) -// { -// // there is no managed handler setup anymore - -// // disable the EXT interrupt channel -// // it's OK to do always this, no matter if it's enabled or not -// palDisableLineEvent(GetIoLine(pState->pinNumber)); - -// // clear parameters & configs -// pState->isrPtr = NULL; -// pState->mode = GPIO_INT_NONE; -// pState->param = NULL; -// pState->debounceMs = 0; -// } - -// return true; -// } - -// // Enable an output pin -// // -// // pinNumber - Gpio pin number -// // InitialState - Initial state of pin -// // driveMode - Drive mode and resistors -// // return - True if succesful, false invalid pin, pin not putput, invalid drive mode for ouptput -// // -// bool CPU_GPIO_EnableOutputPin(GPIO_PIN pinNumber, GpioPinValue InitialState, PinMode driveMode) -// { -// // check not an output drive mode -// if (driveMode < (int)PinMode_Output) -// { -// return false; -// } - -// // If this is currently an input pin then clean up -// DeleteInputState(pinNumber); - -// if (CPU_GPIO_SetDriveMode(pinNumber, driveMode) == false) -// { -// return false; -// } - -// CPU_GPIO_SetPinState(pinNumber, InitialState); - -// return true; -// } - -// void CPU_GPIO_DisablePin(GPIO_PIN pinNumber, PinMode driveMode, uint32_t alternateFunction) -// { -// DeleteInputState(pinNumber); - -// GLOBAL_LOCK(); - -// CPU_GPIO_SetDriveMode(pinNumber, driveMode); - -// // get IoLine from pin number -// ioline_t ioLine = GetIoLine(pinNumber); -// palSetLineMode(ioLine, PAL_MODE_ALTERNATE(alternateFunction)); - -// GLOBAL_UNLOCK(); - -// CPU_GPIO_ReservePin(pinNumber, false); -// } - -// // Validate pin and set drive mode -// // return true if ok -// bool CPU_GPIO_SetDriveMode(GPIO_PIN pinNumber, PinMode driveMode) -// { -// // get IoLine from pin number -// ioline_t ioLine = GetIoLine(pinNumber); - -// switch (driveMode) -// { -// case PinMode_Input: -// palSetLineMode(ioLine, PAL_MODE_INPUT); -// break; - -// case PinMode_InputPullDown: -// palSetLineMode(ioLine, PAL_MODE_INPUT_PULLDOWN); -// break; - -// case PinMode_InputPullUp: -// palSetLineMode(ioLine, PAL_MODE_INPUT_PULLUP); -// break; - -// case PinMode_Output: -// palSetLineMode(ioLine, PAL_MODE_OUTPUT_PUSHPULL); -// break; - -// case PinMode_OutputOpenDrain: -// palSetLineMode(ioLine, PAL_MODE_OUTPUT_OPENDRAIN); -// break; - -// default: -// // all other modes are NOT supported -// return false; -// } - -// return true; -// } - -// bool CPU_GPIO_DriveModeSupported(GPIO_PIN pinNumber, PinMode driveMode) -// { -// (void)pinNumber; - -// bool driveModeSupported = false; - -// // check if the requested drive mode is support by ChibiOS config -// if ((driveMode == PinMode_Input) || (driveMode == PinMode_InputPullDown) || (driveMode == PinMode_InputPullUp) || -// (driveMode == PinMode_Output) || (driveMode == PinMode_OutputOpenDrain)) -// { -// driveModeSupported = true; -// } - -// return driveModeSupported; -// } - -// uint32_t CPU_GPIO_GetPinDebounce(GPIO_PIN pinNumber) -// { -// gpio_input_state *ptr = GetInputState(pinNumber); - -// if (ptr) -// { -// return ptr->debounceMs; -// } - -// return 0; -// } - -// bool CPU_GPIO_SetPinDebounce(GPIO_PIN pinNumber, uint32_t debounceTimeMilliseconds) -// { -// gpio_input_state *ptr = GetInputState(pinNumber); -// if (ptr) -// { -// ptr->debounceMs = debounceTimeMilliseconds; -// return true; -// } -// return false; -// } +// Double linkedlist to hold the state of each Input pin +struct gpio_input_state : public HAL_DblLinkedNode +{ + // Pin number + GPIO_PIN pinNumber; + // debounce timer for this Pin + TX_TIMER debounceTimer; + // Ptr to user ISR or null + GPIO_INTERRUPT_SERVICE_ROUTINE isrPtr; + // debounce Millsecs, no debonce=0 + uint32_t debounceMs; + // Interrupt mode + uint8_t mode; + // Param to user isr call + void *param; + // Expected state for debounce handler + bool expected; + // True if waiting for debounce timer to complete + bool waitingDebounce; +}; + +static HAL_DblLinkedList gpioInputList; // Double Linked list for GPIO input status +static uint16_t pinReserved[TOTAL_GPIO_PORTS]; // reserved - 1 bit per pin + +// this is an utility function to get a Gecko API port and pin from our "encoded" pin number +void GetIoLine(int16_t pinNumber, GPIO_Port_TypeDef *port, uint32_t *portPin) +{ + *port = GPIO_PORT(pinNumber); + *portPin = pinNumber % 16; +} + +bool IsValidGpioPin(GPIO_PIN pinNumber) +{ + return (pinNumber <= GPIO_MAX_PIN); +} + +// Get pointer to gpio_input_state for GPIO pin +// return NULL if not found +gpio_input_state *GetGpioWithInterrupt(uint16_t gpioPin) +{ + gpio_input_state *ptr = gpioInputList.FirstNode(); + while (ptr->Next() != NULL) + { + if (GPIO_PIN(ptr->pinNumber) == gpioPin) + { + return ptr; + } + + ptr = ptr->Next(); + } + + return NULL; +} + +static void DebounceTimerCallback(uint32_t id) +{ + gpio_input_state *pState = (gpio_input_state *)id; + + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pState->pinNumber, &port, &portPin); + + // get current pin state + bool actual = GPIO_PinInGet(port, portPin); + + if (actual == pState->expected) + { + pState->isrPtr(pState->pinNumber, actual, pState->param); + if (pState->mode == GPIO_INT_EDGE_BOTH) + { + // both edges + // update expected state + pState->expected ^= 1; + } + } + + pState->waitingDebounce = false; +} + +void GpioEventCallback(void *arg) +{ + NATIVE_INTERRUPT_START + + TX_DISABLE + + gpio_input_state *pGpio = (gpio_input_state *)arg; + + if (pGpio != NULL) + { + // Ignore any pin changes during debounce + if (!pGpio->waitingDebounce) + { + // check if there is a debounce time set + if (pGpio->debounceMs > 0) + { + // Set flag we are waiting for debounce on this pin + pGpio->waitingDebounce = true; + + // setup timer + tx_timer_deactivate(&pGpio->debounceTimer); + tx_timer_change(&pGpio->debounceTimer, 0, pGpio->debounceMs / 10); + tx_timer_activate(&pGpio->debounceTimer); + } + else + { + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pGpio->pinNumber, &port, &portPin); + + TX_RESTORE + + pGpio->isrPtr(pGpio->pinNumber, GPIO_PinInGet(port, portPin), pGpio->param); + + TX_DISABLE + } + } + } + + TX_RESTORE + + NATIVE_INTERRUPT_END +} + +// Get pointer to gpio_input_state for Gpio pin +// return NULL if not found +gpio_input_state *GetInputState(GPIO_PIN pinNumber) +{ + gpio_input_state *ptr = gpioInputList.FirstNode(); + + while (ptr->Next() != NULL) + { + if (ptr->pinNumber == pinNumber) + { + return ptr; + } + + ptr = ptr->Next(); + } + + return NULL; +} + +// Allocate a new gpio_input_state and add to end of list +// if already exist then just return current ptr +gpio_input_state *AllocateGpioInputState(GPIO_PIN pinNumber) +{ + gpio_input_state *ptr = GetInputState(pinNumber); + + if (ptr == NULL) + { + ptr = (gpio_input_state *)platform_malloc(sizeof(gpio_input_state)); + + // sanity check + if (ptr != NULL) + { + memset(ptr, 0, sizeof(gpio_input_state)); + ptr->pinNumber = pinNumber; + + tx_timer_create( + &ptr->debounceTimer, + (char *)"GPIO debounce timer", + DebounceTimerCallback, + 0, + 0, + 1, + TX_NO_ACTIVATE); + + gpioInputList.LinkAtBack(ptr); + } + } + + return ptr; +} + +void UnlinkInputState(gpio_input_state *pState) +{ + tx_timer_delete(&pState->debounceTimer); + + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pState->pinNumber, &port, &portPin); + + // disable the EXT interrupt channel + // it's OK to do always this, no matter if it's enabled or not + // TODO + // palDisableLineEvent(GetIoLine(pState->pinNumber)); + + pState->Unlink(); + + platform_free(pState); +} + +// Delete gpio_input_state from List and tidy up ( Timer & ISR handler ) +void DeleteInputState(GPIO_PIN pinNumber) +{ + gpio_input_state *pState = GetInputState(pinNumber); + + if (pState) + { + UnlinkInputState(pState); + } +} + +bool CPU_GPIO_Initialize() +{ + // Initialise Double linked list for input pin states + gpioInputList.Initialize(); + + // Make sure all pins are not reserved + memset(pinReserved, 0, sizeof(pinReserved)); + + return true; +} + +bool CPU_GPIO_Uninitialize() +{ + NANOCLR_FOREACH_NODE(gpio_input_state, pGpio, gpioInputList) + { + UnlinkInputState(pGpio); + } + NANOCLR_FOREACH_NODE_END(); + + return true; +} + +// Set/reset reserved state of pin +bool CPU_GPIO_ReservePin(GPIO_PIN pinNumber, bool fReserve) +{ + // Check if valid pin number + if (!IsValidGpioPin(pinNumber)) + { + return false; + } + + int port = pinNumber >> 4, bit = 1 << (pinNumber & 0x0F); + bool ret = true; + GLOBAL_LOCK(); + + if (fReserve) + { + if (pinReserved[port] & bit) + { + // already reserved + ret = false; + } + else + { + pinReserved[port] |= bit; + } + } + else + { + pinReserved[port] &= ~bit; + } + + GLOBAL_UNLOCK(); + return ret; +} + +// Return if Pin is reserved +bool CPU_GPIO_PinIsBusy(GPIO_PIN pinNumber) +{ + // Check if valid pin number + if (!IsValidGpioPin(pinNumber)) + { + return false; + } + + int port = pinNumber >> 4, sh = pinNumber & 0x0F; + return (pinReserved[port] >> sh) & 1; +} + +// Return maximum number of pins +int32_t CPU_GPIO_GetPinCount() +{ + return GPIO_MAX_PIN; +} + +// Get current state of pin +GpioPinValue CPU_GPIO_GetPinState(GPIO_PIN pin) +{ + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pin, &port, &portPin); + + return (GpioPinValue)GPIO_PinInGet(port, portPin); +} + +// Set Pin state +void CPU_GPIO_SetPinState(GPIO_PIN pin, GpioPinValue pinState) +{ + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pin, &port, &portPin); + + if (pinState == GpioPinValue_High) + { + GPIO_PortOutSet(port, portPin); + } + else + { + GPIO_PortOutClear(port, portPin); + } +} + +void CPU_GPIO_TogglePinState(GPIO_PIN pin) +{ + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pin, &port, &portPin); + + GPIO_PortOutToggle(port, portPin); +} + +bool CPU_GPIO_EnableInputPin( + GPIO_PIN pinNumber, + uint32_t debounceTimeMilliseconds, + GPIO_INTERRUPT_SERVICE_ROUTINE pinISR, + void *isrParam, + GPIO_INT_EDGE intEdge, + PinMode driveMode) +{ + gpio_input_state *pState; + + // Check Input drive mode + if (driveMode >= (int)PinMode_Output) + { + return false; + } + + // Set as Input GPIO_INT_EDGE intEdge, GPIO_RESISTOR ResistorState + if (!CPU_GPIO_SetDriveMode(pinNumber, driveMode)) + { + return false; + } + + pState = AllocateGpioInputState(pinNumber); + + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pinNumber, &port, &portPin); + + // Link ISR ptr supplied and not already set up + // CPU_GPIO_EnableInputPin could be called a 2nd time with changed parameters + if (pinISR != NULL && (pState->isrPtr == NULL)) + { + // there are callbacks registered and... + // the drive mode is input so need to setup the interrupt + + GPIO_ExtIntConfig(port, portPin, portPin, 1, 1, true); + + // TODO + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + // palSetLineCallback(ioLine, GpioEventCallback, pState); + + // store parameters & configs + pState->isrPtr = pinISR; + pState->mode = intEdge; + pState->param = (void *)isrParam; + pState->debounceMs = (uint32_t)(debounceTimeMilliseconds); + + switch (intEdge) + { + case GPIO_INT_EDGE_LOW: + case GPIO_INT_LEVEL_LOW: + pState->expected = 1; + break; + + case GPIO_INT_EDGE_HIGH: + case GPIO_INT_LEVEL_HIGH: + pState->expected = 0; + break; + + case GPIO_INT_EDGE_BOTH: + pState->expected = !CPU_GPIO_GetPinState(pinNumber); // expected NOT current state + break; + + default: + break; + } + } + else if (pinISR == NULL && (pState->isrPtr != NULL)) + { + // there is no managed handler setup anymore + + // disable the EXT interrupt channel + // it's OK to do always this, no matter if it's enabled or not + // TODO + // palDisableLineEvent(GetIoLine(pState->pinNumber)); + + // clear parameters & configs + pState->isrPtr = NULL; + pState->mode = GPIO_INT_NONE; + pState->param = NULL; + pState->debounceMs = 0; + } + + return true; +} + +// Enable an output pin +// +// pinNumber - Gpio pin number +// InitialState - Initial state of pin +// driveMode - Drive mode and resistors +// return - True if successful, false invalid pin, pin not output, invalid drive mode for output +// +bool CPU_GPIO_EnableOutputPin(GPIO_PIN pinNumber, GpioPinValue InitialState, PinMode driveMode) +{ + // check not an output drive mode + if (driveMode < (int)PinMode_Output) + { + return false; + } + + // If this is currently an input pin then clean up + DeleteInputState(pinNumber); + + if (CPU_GPIO_SetDriveMode(pinNumber, driveMode) == false) + { + return false; + } + + CPU_GPIO_SetPinState(pinNumber, InitialState); + + return true; +} + +void CPU_GPIO_DisablePin(GPIO_PIN pinNumber, PinMode driveMode, uint32_t alternateFunction) +{ + DeleteInputState(pinNumber); + + GLOBAL_LOCK(); + + CPU_GPIO_SetDriveMode(pinNumber, driveMode); + + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pinNumber, &port, &portPin); + + GPIO_PinModeSet(port, portPin, (GPIO_Mode_TypeDef)alternateFunction, 0); + + GLOBAL_UNLOCK(); + + CPU_GPIO_ReservePin(pinNumber, false); +} + +// Validate pin and set drive mode +// return true if ok +bool CPU_GPIO_SetDriveMode(GPIO_PIN pinNumber, PinMode driveMode) +{ + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pinNumber, &port, &portPin); + + switch (driveMode) + { + case PinMode_Input: + GPIO_PinModeSet(port, portPin, gpioModeInput, 0); + break; + + case PinMode_InputPullDown: + GPIO_PinModeSet(port, portPin, gpioModeInputPull, 0); + break; + + case PinMode_InputPullUp: + GPIO_PinModeSet(port, portPin, gpioModeInputPull, 1); + break; + + case PinMode_Output: + GPIO_PinModeSet(port, portPin, gpioModePushPull, 0); + + break; + + case PinMode_OutputOpenDrain: + GPIO_PinModeSet(port, portPin, gpioModeWiredAnd, 1); + break; + + default: + // all other modes are NOT supported + return false; + } + + return true; +} + +bool CPU_GPIO_DriveModeSupported(GPIO_PIN pinNumber, PinMode driveMode) +{ + (void)pinNumber; + + bool driveModeSupported = false; + + // check if the requested drive mode is support by ChibiOS config + if ((driveMode == PinMode_Input) || (driveMode == PinMode_InputPullDown) || (driveMode == PinMode_InputPullUp) || + (driveMode == PinMode_Output) || (driveMode == PinMode_OutputOpenDrain)) + { + driveModeSupported = true; + } + + return driveModeSupported; +} + +uint32_t CPU_GPIO_GetPinDebounce(GPIO_PIN pinNumber) +{ + gpio_input_state *ptr = GetInputState(pinNumber); + + if (ptr) + { + return ptr->debounceMs; + } + + return 0; +} + +bool CPU_GPIO_SetPinDebounce(GPIO_PIN pinNumber, uint32_t debounceTimeMilliseconds) +{ + gpio_input_state *ptr = GetInputState(pinNumber); + + if (ptr) + { + ptr->debounceMs = debounceTimeMilliseconds; + return true; + } + + return false; +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h index 202ac24153..58299b78e1 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/sys_dev_gpio_native_target.h @@ -8,6 +8,10 @@ #include #include -// #include + +#include +#include + +#include #endif // SYS_DEV_GPIO_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c new file mode 100644 index 0000000000..6aa289c658 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c @@ -0,0 +1,22 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +unsigned int interrupt_save; +// GPIO_Port_TypeDef *gpioPort[] = { + +// #if (_GPIO_PORT_A_PIN_COUNT > 0) +// gpioPortA, + +// gpioPortB, +// gpioPortC, +// gpioPortD, +// gpioPortE, +// gpioPortF, +// gpioPortG, +// gpioPortH +// }; From b7d2d34a5865f2b183c0e7a8b54b2aab44f07bd4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 10 Jun 2022 11:31:00 +0100 Subject: [PATCH 031/572] Work on CLR boot and adding more features --- .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 224 ++++++++------ .../SL_STK3701A/nanoCLR/targetHAL.cpp | 286 ++++++++++++++++++ .../SiliconLabs/_nanoCLR/targetHAL_Power.c | 9 +- .../SiliconLabs/_nanoCLR/targetHAL_Time.cpp | 19 +- 4 files changed, 438 insertions(+), 100 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index bb9513ef29..5be7962296 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -3,130 +3,176 @@ // See LICENSE file in the project root for full license information. // -// #include -// #include +#include +#include +#include +#include + +#include +#include +// #include #include +#include +// #include + // #include // #include // #include // #include // #include -// #include -// #include // #include // #include // extern TX_EVENT_FLAGS_GROUP wpUartEvent; -// extern CLR_SETTINGS clrSettings; +extern CLR_SETTINGS clrSettings; -// // byte pool configuration and definitions -// // need to be at least as big as the config sector -// #define DEFAULT_BYTE_POOL_SIZE 0x2000 -// TX_BYTE_POOL byte_pool_0; -// uint8_t __attribute__((section(".ram4"))) memory_area[DEFAULT_BYTE_POOL_SIZE]; +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; -// // threads definitions and configurations +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 -// // receiver thread -// #define RECEIVER_THREAD_STACK_SIZE 2048 -// #define RECEIVER_THREAD_PRIORITY 5 +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; -// TX_THREAD receiverThread; -// uint32_t __attribute__((section(".ram4"))) receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -// extern void ReceiverThread_entry(uint32_t parameter); +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 -// // CLR thread -// #define CLR_THREAD_STACK_SIZE 4092 -// #define CLR_THREAD_PRIORITY 5 +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); -// TX_THREAD clrStartupThread; -// uint32_t __attribute__((section(".ram4"))) clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -// extern void ClrStartupThread_entry(uint32_t parameter); +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(250)); + } +} void tx_application_define(void *first_unused_memory) { (void)first_unused_memory; -// uint16_t status; + uint16_t status; -// // Create a byte memory pool from which to allocate the thread stacks. -// tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); -// // start watchdog -// Watchdog_Init(); - -// // turn LED2 off -// palClearPad(GPIOB, GPIOB_LD2); + // start watchdog + // Watchdog_Init(); // #if (HAL_NF_USE_STM32_CRC == TRUE) // // startup crc // crcStart(NULL); // #endif -// // starts the serial driver -// sdStart(&SERIAL_DRIVER, NULL); - -// #if (TRACE_TO_STDIO == TRUE) -// StdioPort_Init(); -// #endif - -// // Create receiver thread -// status = tx_thread_create( -// &receiverThread, -// "Receiver Thread", -// ReceiverThread_entry, -// 0, -// receiverThreadStack, -// RECEIVER_THREAD_STACK_SIZE, -// RECEIVER_THREAD_PRIORITY, -// RECEIVER_THREAD_PRIORITY, -// TX_NO_TIME_SLICE, -// TX_AUTO_START); - -// if (status != TX_SUCCESS) -// { -// while (1) -// { -// } -// } - -// // CLR settings to launch CLR thread -// memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - -// clrSettings.MaxContextSwitches = 50; -// clrSettings.WaitForDebugger = false; -// clrSettings.EnterDebuggerLoopAfterExit = true; - -// // Create CLR startup thread -// status = tx_thread_create( -// &clrStartupThread, -// "CLR Thread", -// ClrStartupThread_entry, -// (uint32_t)&clrSettings, -// clrStartupThreadStack, -// CLR_THREAD_STACK_SIZE, -// CLR_THREAD_PRIORITY, -// CLR_THREAD_PRIORITY, -// TX_NO_TIME_SLICE, -// TX_AUTO_START); - -// if (status != TX_SUCCESS) -// { -// while (1) -// { -// } -// } +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } } // Application entry point. int main(void) { - // halInit(); + // Initialize the board + sl_system_init(); + + // Configure LED0 as output + GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1, gpioModePushPull, 0); + + // turn off LEDs, just in case + GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN, gpioModeDisabled, 0); + GPIO_PinModeSet(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN, gpioModeDisabled, 0); - // // init boot clipboard - // InitBootClipboard(); + // init boot clipboard + InitBootClipboard(); - // Enter the ThreadX kernel - tx_kernel_enter(); + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp new file mode 100644 index 0000000000..55024d32d5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp @@ -0,0 +1,286 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include +#include + +// #if (HAL_USE_CAN == TRUE) +// #include +// #endif +// #if (HAL_USE_I2C == TRUE) +// #include +// #endif +// #if (HAL_USE_SPI == TRUE) +// #include +// #endif +// #if (HAL_USE_UART == TRUE) +// #include +// #endif + +// global mutex protecting the internal state of the interpreter, including event flags +// mutex_t interpreterGlobalMutex; + +// because nanoHAL_Initialize/Uninitialize needs to be called in both C and C++ we need a proxy to allow it to be called +// in 'C' +extern "C" +{ + + void nanoHAL_Initialize_C() + { + nanoHAL_Initialize(); + } + + void nanoHAL_Uninitialize_C() + { + nanoHAL_Uninitialize(); + } +} + +void nanoHAL_Initialize() +{ + // initialize global mutex + // chMtxObjectInit(&interpreterGlobalMutex); + + HAL_CONTINUATION::InitializeList(); + HAL_COMPLETION ::InitializeList(); + + BlockStorageList_Initialize(); + + // initialize block storage devices + BlockStorage_AddDevices(); + + BlockStorageList_InitializeDevices(); + + // clear managed heap region + unsigned char *heapStart = NULL; + unsigned int heapSize = 0; + + ::HeapLocation(heapStart, heapSize); + memset(heapStart, 0, heapSize); + +#if (NANOCLR_GRAPHICS == TRUE) + g_GraphicsMemoryHeap.Initialize(); +#endif + + ConfigurationManager_Initialize(); + + Events_Initialize(); + + CPU_GPIO_Initialize(); + +// #if (HAL_USE_CAN == TRUE) + +// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) +// Can1_PAL.Driver = NULL; +// #endif +// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) +// Can2_PAL.Driver = NULL; +// #endif +// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) +// Can3_PAL.Driver = NULL; +// #endif + +// #endif + +// #if (HAL_USE_I2C == TRUE) + +// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) +// I2C1_PAL.Driver = NULL; +// #endif +// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) +// I2C2_PAL.Driver = NULL; +// #endif +// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) +// I2C3_PAL.Driver = NULL; +// #endif +// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) +// I2C4_PAL.Driver = NULL; +// #endif + +// #endif + +// #if (HAL_USE_SPI == TRUE) +// nanoSPI_Initialize(); +// #endif + +// #if (HAL_USE_UART == TRUE) + +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) +// Uart1_PAL.UartDriver = NULL; +// Uart1_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) +// Uart2_PAL.UartDriver = NULL; +// Uart2_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) +// Uart3_PAL.UartDriver = NULL; +// Uart3_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) +// Uart4_PAL.UartDriver = NULL; +// Uart4_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) +// Uart5_PAL.UartDriver = NULL; +// Uart5_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) +// Uart6_PAL.UartDriver = NULL; +// Uart6_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) +// Uart7_PAL.UartDriver = NULL; +// Uart7_PAL__.UartDriver = NULL; +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) +// Uart8_PAL.UartDriver = NULL; +// Uart8_PAL__.UartDriver = NULL; +// #endif + +// #endif + +#if (NANOCLR_GRAPHICS == TRUE) + DisplayInterfaceConfig config; // not used for DSI display + g_DisplayInterface.Initialize(config); + g_DisplayDriver.Initialize(); + + // g_TouchInterface.Initialize(); + // g_TouchDevice.Initialize(); + + // PalEvent_Initialize(); + // Gesture_Initialize(); + // Ink_Initialize(); +#endif + + // Initialise Network Stack + Network_Initialize(); +} + +void nanoHAL_Uninitialize() +{ + // release the global mutex, just in case it's locked somewhere + // chMtxUnlock(&interpreterGlobalMutex); + + // TODO check for s_rebootHandlers + // for(int i = 0; i< ARRAYSIZE(s_rebootHandlers); i++) + // { + // if(s_rebootHandlers[i] != NULL) + // { + // s_rebootHandlers[i](); + // } + // else + // { + // break; + // } + // } + + // TODO + SOCKETS_CloseConnections(); + +#if !defined(HAL_REDUCESIZE) + // TODO need to call this but it's preventing the debug session from starting + Network_Uninitialize(); +#endif + + BlockStorageList_UnInitializeDevices(); + + // need to be sure that: + // - all mutexes for drivers that use them are released + // - all drivers are stopped + +// #if (HAL_USE_SPI == TRUE) +// nanoSPI_Uninitialize(); +// #endif + +// #if (HAL_USE_CAN == TRUE) + +// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) +// canStop(&CAND1); +// #endif +// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) +// canStop(&CAND2); +// #endif +// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) +// canStop(&CAND3); +// #endif + +// #endif + +// #if (HAL_USE_I2C == TRUE) + +// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) +// i2cReleaseBus(&I2CD1); +// i2cStop(&I2CD1); +// #endif +// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) +// i2cReleaseBus(&I2CD2); +// i2cStop(&I2CD2); +// #endif +// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) +// i2cReleaseBus(&I2CD3); +// i2cStop(&I2CD3); +// #endif +// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) +// i2cReleaseBus(&I2CD4); +// i2cStop(&I2CD4); +// #endif + +// #endif + +// #if (HAL_USE_SPI == TRUE) +// nanoSPI_Uninitialize(); +// #endif + +// #if (HAL_USE_UART == TRUE) + +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) +// uartReleaseBus(&UARTD1); +// uartStop(&UARTD1); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) +// uartReleaseBus(&UARTD2); +// uartStop(&UARTD2); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) +// uartReleaseBus(&UARTD3); +// uartStop(&UARTD3); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) +// uartReleaseBus(&UARTD4); +// uartStop(&UARTD4); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) +// uartReleaseBus(&UARTD5); +// uartStop(&UARTD5); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) +// uartReleaseBus(&UARTD6); +// uartStop(&UARTD6); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) +// uartReleaseBus(&UARTD7); +// uartStop(&UARTD7); +// #endif +// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) +// uartReleaseBus(&UARTD8); +// uartStop(&UARTD8); +// #endif + +// #endif + + CPU_GPIO_Uninitialize(); + + Events_Uninitialize(); + + HAL_CONTINUATION::Uninitialize(); + HAL_COMPLETION ::Uninitialize(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c index 74e40f1035..4770eb2ed5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c @@ -7,6 +7,7 @@ #include #include #include +#include #ifdef HAL_RTC_MODULE_ENABLED extern RTC_HandleTypeDef RtcHandle; @@ -16,7 +17,7 @@ extern RTC_HandleTypeDef RtcHandle; inline void CPU_Reset() { - //NVIC_SystemReset(); + NVIC_SystemReset(); }; inline bool CPU_IsSoftRebootSupported() @@ -45,7 +46,7 @@ void CPU_SetPowerMode(PowerLevel_type powerLevel) // gracefully shutdown everything nanoHAL_Uninitialize_C(); - //__disable_irq(); + __disable_irq(); // ///////////////////////////////////////////////////////////////////////// // // stop the idependent watchdog, for series where the option is available @@ -116,10 +117,10 @@ void CPU_SetPowerMode(PowerLevel_type powerLevel) // #endif // set SLEEPDEEP bit of Cortex SCR - //SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + SCB->SCR &= SCB_SCR_SLEEPDEEP_Msk; // wait for interrupt, and the execution dies here - //__WFI(); + __WFI(); break; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp index 2289d35121..2ac221bf24 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Time.cpp @@ -11,9 +11,12 @@ #include -// // Returns the current date time from the RTC -// uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) -// { +// Returns the current date time from the RTC +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +{ + (void)datePartOnly; + + return 0; // #if (HAL_USE_RTC == TRUE) // // use RTC to get date time @@ -70,10 +73,12 @@ // } // #endif -// }; +}; + +void HAL_Time_SetUtcTime(uint64_t utcTime) +{ + (void)utcTime; -// void HAL_Time_SetUtcTime(uint64_t utcTime) -// { // SYSTEMTIME systemTime; // HAL_Time_ToSystemTime(utcTime, &systemTime); @@ -101,7 +106,7 @@ // // can't mess with the systicks because the scheduling can fail // #endif -// } +} bool HAL_Time_TimeSpanToStringEx(const int64_t &ticks, char *&buf, size_t &len) { From 9d27ee559df46090b4dcda7f7318a022d9785ae0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 10 Jun 2022 11:31:19 +0100 Subject: [PATCH 032/572] Add hardfault helper --- .../SiliconLabs/_common/CMakeLists.txt | 8 +- .../SiliconLabs/_common/hard_fault_handler.c | 184 ++++++++++++++++++ 2 files changed, 188 insertions(+), 4 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index b0322128b3..8e6ae8d6bd 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -29,10 +29,10 @@ endif() # endif() -# # append hard fault handler if the build type is to include debug info -# if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") -# # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/hard_fault_handler.c) -# endif() +# append hard fault handler if the build type is to include debug info +if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") + list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/hard_fault_handler.c) +endif() # make vars global set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c b/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c new file mode 100644 index 0000000000..a9f03e98e2 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c @@ -0,0 +1,184 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html +typedef enum { + Reset = 1, + NMI = 2, + HardFault = 3, + MemManage = 4, + BusFault = 5, + UsageFault = 6, +} FaultType; + +// Generic ARM register +typedef void *regarm_t; + +// This structure represents the stack frame saved during an interrupt handler. +struct port_extctx { + regarm_t spsr_irq; + regarm_t lr_irq; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_usr; +}; + +void NMI_Handler(void) { + while(1); +} + +// dev note: on all the following the variables need to be declared as volatile so they don't get optimized out by the linker +// dev note: the pragma below is to ignore the warning because the variables aren't actually being used despite needing to remain there for debug + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-variable" +#pragma GCC diagnostic ignored "-Wunused-but-set-variable" +#endif + +// hard fault handler for Cortex-M3 & M4 + +void HardFault_Handler(void) { + + //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + struct port_extctx ctx; + + //Get thread context. Contains main registers including PC and LR + memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + (void)ctx; + + //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + volatile FaultType faultType = (FaultType)__get_IPSR(); + + // these are not available in all the STM32 series + + //Flags about hardfault / busfault + //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + volatile bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false); + volatile bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false); + volatile bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false); + volatile bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false); + volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false); + + // Hard Fault Status Register + volatile unsigned long _HFSR = (*((volatile unsigned long *)(0xE000ED2C))) ; + + // Debug Fault Status Register + volatile unsigned long _DFSR = (*((volatile unsigned long *)(0xE000ED30))) ; + + // Auxiliary Fault Status Register + volatile unsigned long _AFSR = (*((volatile unsigned long *)(0xE000ED3C))) ; + + // Read the Fault Address Registers. These may not contain valid values. + // Check BFARVALID/MMARVALID to see if they are valid values + + // MemManage Fault Address Register + volatile unsigned long _MMAR = (*((volatile unsigned long *)(0xE000ED34))) ; + + //For HardFault/BusFault this is the address that was accessed causing the error + volatile uint32_t faultAddress = SCB->BFAR; + + // forces a breakpoint causing the debugger to stop + // if no debugger is attached this is ignored + __asm volatile("BKPT #0\n"); + + // If no debugger connected, just reset the board + NVIC_SystemReset(); +} + +void BusFault_Handler(void) __attribute__((alias("HardFault_Handler"))); + +void UsageFault_Handler(void) { + + //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + //Get thread context. Contains main registers including PC and LR + struct port_extctx ctx; + memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + (void)ctx; + + //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + FaultType faultType = (FaultType)__get_IPSR(); + (void)faultType; + + // these are not available in all the STM32 series + #if defined(STM32L4XX_HAL_VERSION) + + //Flags about hardfault / busfault + //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + volatile bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false); + volatile bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false); + volatile bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false); + volatile bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false); + volatile bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false); + volatile bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false); + + #endif + + // forces a breakpoint causing the debugger to stop + // if no debugger is attached this is ignored + __asm volatile("BKPT #0\n"); + + // If no debugger connected, just reset the board + NVIC_SystemReset(); +} + +void MemManage_Handler(void) { + + //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + //Get thread context. Contains main registers including PC and LR + struct port_extctx ctx; + memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + (void)ctx; + + //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + FaultType faultType = (FaultType)__get_IPSR(); + (void)faultType; + + // these are not available in all the STM32 series + #if defined(STM32L4XX_HAL_VERSION) + + //For HardFault/BusFault this is the address that was accessed causing the error + volatile uint32_t faultAddress = SCB->MMFAR; + + //Flags about hardfault / busfault + //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + volatile bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false); + volatile bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false); + volatile bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false); + volatile bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false); + volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false); + + #endif + + // forces a breakpoint causing the debugger to stop + // if no debugger is attached this is ignored + __asm volatile("BKPT #0\n"); + + // If no debugger connected, just reset the board + NVIC_SystemReset(); +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +/////////////////////////////////////////////////////////////////////////////////////////// +// Hard Fault test code. +// Call this to cause a hard fault by accessing a nonexistent memory address @ 0xCCCCCCCC. +void HardFaultTest() +{ + volatile uint32_t*p; + uint32_t n; + p = (uint32_t*)0xCCCCCCCC; + n = *p; + (void)n; +} +/////////////////////////////////////////////////////////////////////////////////////////// From 4c4344a15e8796abaf38d67bcf62609711b3f47d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Jun 2022 12:38:05 +0100 Subject: [PATCH 033/572] Fix access modifiers for boot clipboard --- .../SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld | 2 +- .../SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index ae513222dc..05b7620cfa 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -36,7 +36,7 @@ MEMORY deployment (rx) : org = 0x0000A000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ } /* Linker script to place sections and symbol values. Should be used together diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 0bb48b6ad8..c470e0619e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -36,7 +36,7 @@ MEMORY deployment (rx) : org = 0x000EE000, len = 908k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (wx) : org = 0x2007FFD0, len = 48 /* boot clipboard area */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ } /* Linker script to place sections and symbol values. Should be used together From 3701345bb4c81f656514268ad8c404245a3edf40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Jun 2022 12:38:41 +0100 Subject: [PATCH 034/572] Add cast to help compiler figuring it out --- src/CLR/Core/CLR_RT_Memory.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/CLR/Core/CLR_RT_Memory.cpp b/src/CLR/Core/CLR_RT_Memory.cpp index a64262515e..2da9ee3471 100644 --- a/src/CLR/Core/CLR_RT_Memory.cpp +++ b/src/CLR/Core/CLR_RT_Memory.cpp @@ -25,8 +25,8 @@ void CLR_RT_Memory::Reset() ::HeapLocation(s_CLR_RT_Heap.m_location, s_CLR_RT_Heap.m_size); // adjust GC thresholds - g_CLR_RT_GarbageCollector.c_memoryThreshold = s_CLR_RT_Heap.m_size * HEAP_SIZE_THRESHOLD_RATIO; - g_CLR_RT_GarbageCollector.c_memoryThreshold2 = s_CLR_RT_Heap.m_size * HEAP_SIZE_THRESHOLD_UPPER_RATIO; + g_CLR_RT_GarbageCollector.c_memoryThreshold = (CLR_UINT32)(s_CLR_RT_Heap.m_size * HEAP_SIZE_THRESHOLD_RATIO); + g_CLR_RT_GarbageCollector.c_memoryThreshold2 = (CLR_UINT32)(s_CLR_RT_Heap.m_size * HEAP_SIZE_THRESHOLD_UPPER_RATIO); #if defined(NANOCLR_TRACE_MALLOC) s_TotalAllocated = 0; From 6381bc94fbf726b1dd0a16a2ac9b3693e7a90328 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Jun 2022 17:23:45 +0100 Subject: [PATCH 035/572] Migrate Gecko SDK to v4.1.0 - Update CMake. - Update linker files. - Remove DEBUG_EFM compiler definition - Remove -Wundef which was causing issues because on bad #ifdef (reported to Silabs https://community.silabs.com/s/question/0D58Y00008nzldISAQ). --- .../AzureRTOS_EFM32GG11_GCC_options.cmake | 5 +- CMake/Modules/FindGecko_SDK.cmake | 3 +- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 100 +++++++++++++----- .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 100 +++++++++++++----- 5 files changed, 156 insertions(+), 54 deletions(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index 1c79c6e180..0abb9da87e 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -29,12 +29,11 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU - # - DEBUG_EFM from Gecko SDK - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=FALSE -DDEBUG_EFM=1) + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=FALSE) endmacro() diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 905d1f4783..3a733a7cbf 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -19,7 +19,7 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/board/inc) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/Include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/Core/Include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/CMSIS/RTOS2/Include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/device_init/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/inc) @@ -44,7 +44,6 @@ set(gecko_sdk_srcs em_acmp.c em_adc.c - em_assert.c em_cmu.c em_core.c em_cryotimer.c diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index b199fd18c7..a06761a89f 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -32,7 +32,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.0.2") + set(GECKO_SDK_VERSION "v4.1.0") endif() if(NO_GECKO_SDK_SOURCE) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index 05b7620cfa..0dcac6e556 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -69,8 +69,6 @@ MEMORY * __StackLimit * __StackTop * __stack - * __Vectors_End - * __Vectors_Size */ ENTRY(Reset_Handler) @@ -82,9 +80,6 @@ SECTIONS .text : { KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; *(.text*) @@ -110,6 +105,19 @@ SECTIONS KEEP(*(.eh_frame*)) } > flash0 + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > flash0 +*/ + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -122,41 +130,43 @@ SECTIONS } > flash0 __exidx_end = .; - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* .copy.table : { . = ALIGN(4); __copy_table_start__ = .; + LONG (__etext) LONG (__data_start__) - LONG (__data_end__ - __data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* LONG (__etext2) LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ __copy_table_end__ = .; } > flash0 - */ - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* .zero.table : { . = ALIGN(4); __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) + /* Add each additional bss section here */ +/* LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ __zero_table_end__ = .; } > flash0 - */ - __etext = .; + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); .data : AT (__etext) { @@ -195,17 +205,59 @@ SECTIONS } > RAM + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + .bss : { . = ALIGN(4); __bss_start__ = .; - *(.bss*) + *(.bss) + *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM - .heap (COPY): + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : { __HeapBase = .; __end__ = .; @@ -218,7 +270,7 @@ SECTIONS /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy (COPY): + .stack_dummy (COPY): { KEEP(*(.stack*)) } > RAM diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index c470e0619e..1c46da3b8b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -69,8 +69,6 @@ MEMORY * __StackLimit * __StackTop * __stack - * __Vectors_End - * __Vectors_Size */ ENTRY(Reset_Handler) @@ -85,9 +83,6 @@ SECTIONS .text : { KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; *(.text*) @@ -113,6 +108,19 @@ SECTIONS KEEP(*(.eh_frame*)) } > flash0 + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > flash0 +*/ + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -125,41 +133,43 @@ SECTIONS } > flash0 __exidx_end = .; - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* .copy.table : { . = ALIGN(4); __copy_table_start__ = .; + LONG (__etext) LONG (__data_start__) - LONG (__data_end__ - __data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* LONG (__etext2) LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ __copy_table_end__ = .; } > flash0 - */ - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* .zero.table : { . = ALIGN(4); __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) + /* Add each additional bss section here */ +/* LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ __zero_table_end__ = .; } > flash0 - */ - __etext = .; + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); .data : AT (__etext) { @@ -198,17 +208,59 @@ SECTIONS } > RAM + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + .bss : { . = ALIGN(4); __bss_start__ = .; - *(.bss*) + *(.bss) + *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM - .heap (COPY): + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : { __HeapBase = .; __end__ = .; @@ -221,7 +273,7 @@ SECTIONS /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy (COPY): + .stack_dummy (COPY): { KEEP(*(.stack*)) } > RAM From 8cb9b2b0641fdb3244f8e14660438ea5f153b444 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Jun 2022 17:30:18 +0100 Subject: [PATCH 036/572] Add missing file --- .../AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt | 1 + targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c | 14 +------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt index b2f67531a3..ae8fd07bb6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt @@ -9,6 +9,7 @@ configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in # append target Azure RTOS nanoCLR source files list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) +list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c index 6aa289c658..9043c3db0f 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c @@ -6,17 +6,5 @@ #include #include +// required for Azure RTOS TX_INTERRUPT_SAVE_AREA implementation at platform level unsigned int interrupt_save; -// GPIO_Port_TypeDef *gpioPort[] = { - -// #if (_GPIO_PORT_A_PIN_COUNT > 0) -// gpioPortA, - -// gpioPortB, -// gpioPortC, -// gpioPortD, -// gpioPortE, -// gpioPortF, -// gpioPortG, -// gpioPortH -// }; From 969b99895a7b1776f8fbbcf60da8677d8ea15ab6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Jun 2022 18:28:06 +0100 Subject: [PATCH 037/572] Fix check to launch CLR - Code changed with Gecko SDK v4.1.0. --- CMake/Modules/FindGecko_SDK.cmake | 1 - .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 10 ++-- .../SL_STK3701A/common/CMakeLists.txt | 3 ++ .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 20 +++----- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 50 +++++++++---------- .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 12 ----- .../AzureRTOS/SiliconLabs/_common/LaunchCLR.c | 6 +-- .../_common/config/sl_memory_config.h | 16 ++++++ 8 files changed, 60 insertions(+), 58 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 3a733a7cbf..185f3e12d3 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -122,7 +122,6 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") # common paths ${gecko_sdk_SOURCE_DIR}/hardware/board/src ${gecko_sdk_SOURCE_DIR}/platform/common/src - ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/gpiointerrupt/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/src diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 7c6c372e03..c929fb8423 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -33,8 +33,10 @@ nf_setup_target_build( SL_BOARD_REV=\"B07\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - __STACK_SIZE=0x4000 - __HEAP_SIZE=0x4000 + __START=main + __STARTUP_CLEAR_BSS=1 + SL_STACK_SIZE=0x9000 + SL_HEAP_SIZE=0x9000 CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -42,8 +44,8 @@ nf_setup_target_build( SL_BOARD_REV=\"B07\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - __STACK_SIZE=0x4000 - __HEAP_SIZE=0x4000 + SL_STACK_SIZE=0x4000 + SL_HEAP_SIZE=0x4000 BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt index 8ea7907f60..027777da05 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt @@ -6,5 +6,8 @@ # append common source files list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) +# this needs to be added here, otherewise the stack and heap arrays are not allocated +list(APPEND COMMON_PROJECT_SOURCES ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/src/sl_memory.c) + # make var global set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index 0dcac6e556..80abcbe1f5 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -69,6 +69,8 @@ MEMORY * __StackLimit * __StackTop * __stack + * __Vectors_End + * __Vectors_Size */ ENTRY(Reset_Handler) @@ -80,6 +82,9 @@ SECTIONS .text : { KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; *(.text*) @@ -130,6 +135,7 @@ SECTIONS } > flash0 __exidx_end = .; + .copy.table : { . = ALIGN(4); @@ -138,13 +144,6 @@ SECTIONS LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ __copy_table_end__ = .; } > flash0 @@ -152,11 +151,6 @@ SECTIONS { . = ALIGN(4); __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ __zero_table_end__ = .; } > flash0 @@ -277,7 +271,7 @@ SECTIONS /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackTop = ORIGIN(RAM) + LENGTH(RAM) - 4; __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 914429da3f..6a39add195 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -19,7 +19,7 @@ // byte pool configuration and definitions #define DEFAULT_BYTE_POOL_SIZE 4096 TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; // threads definitions and configurations @@ -28,7 +28,7 @@ uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; #define RECEIVER_THREAD_PRIORITY 5 TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; extern void ReceiverThread_entry(uint32_t parameter); // blink thread @@ -36,9 +36,9 @@ extern void ReceiverThread_entry(uint32_t parameter); #define BLINK_THREAD_PRIORITY 5 TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; TX_THREAD blinkThread1; -uint32_t blinkThread1Stack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; +ALIGN_TYPE blinkThread1Stack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; void BlinkThread_entry(uint32_t parameter) { @@ -92,7 +92,7 @@ void tx_application_define(void *first_unused_memory) "Blink Thread", BlinkThread_entry, 0, - blinkThreadStack, + (uint8_t*)blinkThreadStack, BLINK_THREAD_STACK_SIZE, BLINK_THREAD_PRIORITY, BLINK_THREAD_PRIORITY, @@ -106,25 +106,25 @@ void tx_application_define(void *first_unused_memory) } } - // Create blink thread - status = tx_thread_create( - &blinkThread1, - "Blink Thread1", - BlinkThread1_entry, - 0, - blinkThread1Stack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } + // // Create blink thread + // status = tx_thread_create( + // &blinkThread1, + // "Blink Thread1", + // BlinkThread1_entry, + // 0, + // (uint8_t*)blinkThread1Stack, + // BLINK_THREAD_STACK_SIZE, + // BLINK_THREAD_PRIORITY, + // BLINK_THREAD_PRIORITY, + // TX_NO_TIME_SLICE, + // TX_AUTO_START); + + // if (status != TX_SUCCESS) + // { + // while (1) + // { + // } + // } // Create receiver thread status = tx_thread_create( @@ -160,7 +160,7 @@ int main(void) GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN, gpioModePushPull, 0); GPIO_PinModeSet(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN, gpioModePushPull, 0); - // configure + // configure GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInput, 0); // init boot clipboard diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 1c46da3b8b..b0b08586ec 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -141,13 +141,6 @@ SECTIONS LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ __copy_table_end__ = .; } > flash0 @@ -155,11 +148,6 @@ SECTIONS { . = ALIGN(4); __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ __zero_table_end__ = .; } > flash0 diff --git a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c index 5dc7d2e9ad..8bf4e23bf1 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c +++ b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c @@ -50,8 +50,8 @@ bool CheckValidCLRImage(uint32_t address) return false; } - // 2nd check: the content pointed by the reset vector has to be 0xB510 - // that's an assembly "push {r4, lr}" the very first one in the Reset_Handler function + // 2nd check: the content pointed by the reset vector has to be 0xB508 + // that's an assembly "push {r3, lr}" the very first one in the Reset_Handler function // see platform\Device\SiliconLabs\EFM32GG11B\Source\GCC\startup_efm32gg11b.c // "regular" address mapping @@ -73,7 +73,7 @@ bool CheckValidCLRImage(uint32_t address) opCodeAddress -= 1; uint32_t opCode = *((uint32_t *)opCodeAddress); - if ((uint16_t)opCode == 0xB510) + if ((uint16_t)opCode == 0xB508) { // check, there seems to be a valid CLR image return true; diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h new file mode 100644 index 0000000000..d641ca4017 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_memory_config.h @@ -0,0 +1,16 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// Stack size for the application. +// This is set to a value that will blow up memory assignment to force this to be set at target level +#ifndef SL_STACK_SIZE + #define SL_STACK_SIZE 0xDEADBEEF +#endif + +// Minimum heap size for the application. +// This is set to a value that will blow up memory assignment to force this to be set at target level +#ifndef SL_HEAP_SIZE + #define SL_HEAP_SIZE 0xDEADBEEF +#endif + +#endif From 30b9b808ca3706694139ec4e9efa57ad2fd83798 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 13:43:07 +0100 Subject: [PATCH 038/572] Fix build fos Gecko SDK v4.1.0 --- .../AzureRTOS_EFM32GG11_GCC_options.cmake | 13 ++-- CMake/Modules/FindGecko_SDK.cmake | 4 +- CMake/binutils.AzureRTOS.cmake | 5 +- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 14 ++-- .../SL_STK3701A/common/CMakeLists.txt | 3 - .../config/pin_config.h | 33 +++++---- .../config/sl_board_control_config.h | 58 +++++++++++---- .../SL_STK3701A/config/sl_memory_config.h | 13 ++++ .../config/sl_uartdrv_usart_vcom_config.h | 22 ------ .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 68 ++---------------- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 38 +++++----- .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 71 +++---------------- .../_common/autogen/sl_iostream_handles.c | 2 +- .../autogen/sl_iostream_init_instances.h | 2 +- .../sl_iostream_init_usart_instances.c | 18 ++--- .../sl_iostream_init_usart_instances.h | 2 +- 16 files changed, 147 insertions(+), 219 deletions(-) rename targets/AzureRTOS/SiliconLabs/{_common => SL_STK3701A}/config/pin_config.h (74%) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_memory_config.h diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index 0abb9da87e..9ea33706db 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -8,12 +8,12 @@ ################################################################# # need to specify this for assembler -set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") -set(CMAKE_C_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") -set(CMAKE_CXX_FLAGS " -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") +set(CMAKE_ASM_FLAGS " -gdwarf-2 -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") +set(CMAKE_C_FLAGS " -gdwarf-2 -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") +set(CMAKE_CXX_FLAGS " -gdwarf-2 -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new " CACHE INTERNAL "asm compiler flags") # need to specify linker flags here -set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs " CACHE INTERNAL "executable linker flags") +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -gdwarf-2 -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs " CACHE INTERNAL "executable linker flags") # TARGET parameter to set the target that's setting them for @@ -29,12 +29,17 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA + # disabling -Wundef for now as this is causing issues in Gecko SDK target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=FALSE) + if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DDEBUG_EFM=1) + endif() + endmacro() diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 185f3e12d3..c4715ac4c6 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -41,6 +41,8 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) set(gecko_sdk_srcs sl_board_control_gpio.c sl_board_init.c + sl_memory.c + sl_assert.c em_acmp.c em_adc.c @@ -122,6 +124,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") # common paths ${gecko_sdk_SOURCE_DIR}/hardware/board/src ${gecko_sdk_SOURCE_DIR}/platform/common/src + ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/gpiointerrupt/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/src @@ -139,7 +142,6 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") # target series specific ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source - ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source/GCC ${TARGET_BASE_LOCATION}/autogen ${TARGET_BASE_LOCATION}/config diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index cd32d7900b..d6ad1f072d 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -445,13 +445,14 @@ macro(nf_add_platform_sources target) ${target} EXTRA_INCLUDES ${AZRTOS_INCLUDES} - # ${TARGET_AZURERTOS_COMMON_INCLUDE_DIRS} ) - # add_dependencies(${target}.elf nano::gecko_sdk_${target}) + add_dependencies(${target}.elf nano::gecko_sdk_${target}) target_link_libraries(${target}.elf + -Wl,-whole-archive nano::gecko_sdk_${target} + -Wl,-no-whole-archive ) endif() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index c929fb8423..4e8d2503b7 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -29,19 +29,17 @@ nf_setup_target_build( BOOTER_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 - SL_BOARD_NAME=\"BRD2204A\" - SL_BOARD_REV=\"B07\" + SL_BOARD_NAME=\"BRD2204C\" + SL_BOARD_REV=\"A02\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - __START=main - __STARTUP_CLEAR_BSS=1 - SL_STACK_SIZE=0x9000 - SL_HEAP_SIZE=0x9000 + SL_STACK_SIZE=0x4000 + SL_HEAP_SIZE=0x4000 CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 - SL_BOARD_NAME=\"BRD2204A\" - SL_BOARD_REV=\"B07\" + SL_BOARD_NAME=\"BRD2204C\" + SL_BOARD_REV=\"A02\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 SL_STACK_SIZE=0x4000 diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt index 027777da05..8ea7907f60 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/CMakeLists.txt @@ -6,8 +6,5 @@ # append common source files list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) -# this needs to be added here, otherewise the stack and heap arrays are not allocated -list(APPEND COMMON_PROJECT_SOURCES ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/src/sl_memory.c) - # make var global set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/pin_config.h similarity index 74% rename from targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/pin_config.h index 88e1491e0c..158edf847a 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/config/pin_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/pin_config.h @@ -197,16 +197,6 @@ // [USART0]$ // $[USART1] -// USART1 CLK on PC15 -#define USART1_CLK_PORT gpioPortC -#define USART1_CLK_PIN 15 -#define USART1_CLK_LOC 3 - -// USART1 TX on PA14 -#define USART1_TX_PORT gpioPortA -#define USART1_TX_PIN 14 -#define USART1_TX_LOC 6 - // [USART1]$ // $[USART2] @@ -216,6 +206,26 @@ // [USART3]$ // $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + // [USART4]$ // $[USART5] @@ -243,9 +253,6 @@ // [WTIMER3]$ // $[CUSTOM_PIN_NAME] -#define SL_SIMPLE_LED_LED0_PORT_PORT gpioPortH -#define SL_SIMPLE_LED_LED0_PORT_PIN 11 - // [CUSTOM_PIN_NAME]$ #endif // PIN_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h index ec44b774f6..079efde3b3 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h @@ -1,3 +1,33 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + #ifndef SL_BOARD_CONTROL_CONFIG_H #define SL_BOARD_CONTROL_CONFIG_H @@ -37,44 +67,44 @@ // SL_BOARD_ENABLE_VCOM // $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE -#define SL_BOARD_ENABLE_VCOM_PIN 1 +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 // [GPIO_SL_BOARD_ENABLE_VCOM]$ // SL_BOARD_ENABLE_DISPLAY // $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA -#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 // [GPIO_SL_BOARD_ENABLE_DISPLAY]$ // SL_BOARD_ENABLE_SENSOR_RHT // $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 // [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ // SL_BOARD_ENABLE_SENSOR_HALL // $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] -#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB -#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 // [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ // SL_BOARD_ENABLE_SENSOR_MICROPHONE // $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 // [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ // SL_BOARD_ENABLE_MEMORY_QSPI // $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] -#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG -#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 // [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ // SL_BOARD_ENABLE_MEMORY_SDCARD // $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] -#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE -#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 // [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ // <<< sl:end pin_tool >>> diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h index be04808312..b9b92ff77c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_uartdrv_usart_vcom_config.h @@ -1,25 +1,3 @@ -/***************************************************************************/ /** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories - *Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is - *Silicon Laboratories Inc. Your use of - *this software is governed by the terms - *of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. - *This software is distributed to you in - *Source Code format and is governed by - *the sections of the MSLA applicable to - *Source Code. - * - ******************************************************************************/ - #ifndef SL_UARTDRV_USART_VCOM_CONFIG_H #define SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index 80abcbe1f5..dad977c826 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -74,9 +74,6 @@ MEMORY */ ENTRY(Reset_Handler) -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - SECTIONS { .text : @@ -110,19 +107,6 @@ SECTIONS KEEP(*(.eh_frame*)) } > flash0 - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > flash0 -*/ - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -199,59 +183,18 @@ SECTIONS } > RAM - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) - *(.bss.*) + *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : + .heap (COPY): { __HeapBase = .; __end__ = .; @@ -264,14 +207,14 @@ SECTIONS /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy (COPY): + .stack_dummy (COPY): { KEEP(*(.stack*)) } > RAM /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM) - 4; + __StackTop = ORIGIN(RAM) + LENGTH(RAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); @@ -282,6 +225,9 @@ SECTIONS ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") } +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + /* Code rules inclusion.*/ INCLUDE rules_code.ld diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 6a39add195..b915bd21c9 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -106,25 +106,25 @@ void tx_application_define(void *first_unused_memory) } } - // // Create blink thread - // status = tx_thread_create( - // &blinkThread1, - // "Blink Thread1", - // BlinkThread1_entry, - // 0, - // (uint8_t*)blinkThread1Stack, - // BLINK_THREAD_STACK_SIZE, - // BLINK_THREAD_PRIORITY, - // BLINK_THREAD_PRIORITY, - // TX_NO_TIME_SLICE, - // TX_AUTO_START); - - // if (status != TX_SUCCESS) - // { - // while (1) - // { - // } - // } + // Create blink thread + status = tx_thread_create( + &blinkThread1, + "Blink Thread1", + BlinkThread1_entry, + 0, + (uint8_t*)blinkThread1Stack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } // Create receiver thread status = tx_thread_create( diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index b0b08586ec..4f13bd754c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -69,6 +69,8 @@ MEMORY * __StackLimit * __StackTop * __stack + * __Vectors_End + * __Vectors_Size */ ENTRY(Reset_Handler) @@ -83,6 +85,9 @@ SECTIONS .text : { KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; *(.text*) @@ -108,19 +113,6 @@ SECTIONS KEEP(*(.eh_frame*)) } > flash0 - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option ‘--section-start’ or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > flash0 -*/ - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -196,28 +188,6 @@ SECTIONS } > RAM - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - .bss : { . = ALIGN(4); @@ -229,25 +199,6 @@ SECTIONS __bss_end__ = .; } > RAM - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - .heap (COPY) : { __HeapBase = .; @@ -266,6 +217,12 @@ SECTIONS KEEP(*(.stack*)) } > RAM + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + /* nanoFramework CLR managed heap section at the specified RAM section.*/ .clr_managed_heap (NOLOAD) : { @@ -278,12 +235,6 @@ SECTIONS PROVIDE(HeapEnd = .); } > CLR_MANAGED_HEAP_RAM - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c index fc0d9d21e2..fee0efcc62 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c @@ -24,4 +24,4 @@ sl_iostream_t *sl_iostream_get_handle(char *name) } return NULL; -} \ No newline at end of file +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h index c092c37eec..7bd47c07f2 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_instances.h @@ -13,4 +13,4 @@ void sl_iostream_init_instances(void); } #endif -#endif // SL_IOSTREAM_INIT_INSTANCES_H \ No newline at end of file +#endif // SL_IOSTREAM_INIT_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 697030c171..31c2c50a6e 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -61,17 +61,13 @@ sl_iostream_instance_info_t sl_iostream_instance_vcom_info = { .init = sl_iostream_usart_init_vcom, }; -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif + sl_status_t sl_iostream_usart_init_vcom(void) { sl_status_t status; USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; - //init_vcom.oversampling = usartOVS16; init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; #if (_SILICON_LABS_32B_SERIES > 0) @@ -141,9 +137,7 @@ sl_status_t sl_iostream_usart_init_vcom(void) return status; } -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif + void sl_iostream_usart_init_instances(void) { @@ -206,4 +200,10 @@ static void events_handler(sl_power_manager_em_t from, } } -#endif \ No newline at end of file +#endif + +// implementation required (even if empty) to keep debugger happy +void sli_iostream_on_uart_rx(sl_iostream_t *handle) +{ + (void)handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h index 2301dbe600..3c31aabb4a 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h @@ -31,4 +31,4 @@ sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void); } #endif -#endif // SL_IOSTREAM_INIT_USART_INSTANCES_H \ No newline at end of file +#endif // SL_IOSTREAM_INIT_USART_INSTANCES_H From 0e18798fbc9441785ed53563b4e91985c056fb6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 18:08:16 +0100 Subject: [PATCH 039/572] Fix CLR init from bootloader --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 5be7962296..df3c260e82 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -161,7 +162,10 @@ void tx_application_define(void *first_unused_memory) int main(void) { // Initialize the board - sl_system_init(); + sl_driver_init(); + sl_service_init(); + sl_stack_init(); + sl_internal_app_init(); // Configure LED0 as output GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1, gpioModePushPull, 0); From 18dcc294eb4d5d3476e7d26dd2467b53052bf5ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 18:10:54 +0100 Subject: [PATCH 040/572] Add call to generate full image with booter and CLR --- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 4e8d2503b7..b9d60c63bc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -54,3 +54,26 @@ nf_setup_target_build( # make vars global set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + A000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + A000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() From de674675544d449692587c8bbe5d6d8421465862 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 18:11:11 +0100 Subject: [PATCH 041/572] Remove unnecessary code in target CMake --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index b9d60c63bc..7067cb3b9e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -52,8 +52,6 @@ nf_setup_target_build( ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" ) -# make vars global -set(TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_AZURERTOS_COMMON_SOURCES} CACHE INTERNAL "make global") # generate bin file for deployment if(SRECORD_TOOL_AVAILABLE) From 5b717cbe3c768b560bebb5dd0001512e451ea535 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 18:11:28 +0100 Subject: [PATCH 042/572] Add JLink command file to flash full image in GG11 --- .jlink/flash_gg11.jlink | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 .jlink/flash_gg11.jlink diff --git a/.jlink/flash_gg11.jlink b/.jlink/flash_gg11.jlink new file mode 100644 index 0000000000..03a12a7dd7 --- /dev/null +++ b/.jlink/flash_gg11.jlink @@ -0,0 +1,3 @@ +speed auto +LoadFile nanobooter-nanoclr.bin,0 +Exit \ No newline at end of file From 9d73b9dffe70baa547c1e1a6482e622d8fd6e236 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 18:22:31 +0100 Subject: [PATCH 043/572] Add J-Link to target capabilities --- .../AzureRTOS/_common/include/platform_target_capabilities.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/AzureRTOS/_common/include/platform_target_capabilities.h b/targets/AzureRTOS/_common/include/platform_target_capabilities.h index 49e7d72a00..b56c182d4a 100644 --- a/targets/AzureRTOS/_common/include/platform_target_capabilities.h +++ b/targets/AzureRTOS/_common/include/platform_target_capabilities.h @@ -26,6 +26,9 @@ extern "C" // using Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_TargetCapability_1 TargetCapabilities_DfuUpdate = 0x20000000, + // J-Link update capable + TargetCapabilities_JlinkUpdate = 0x30000000, + } TargetCapabilities; #ifdef __cplusplus From 4221e889823dc58a51b808771ff5bf1177bbbcd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 13 Jun 2022 18:23:22 +0100 Subject: [PATCH 044/572] Fix target capabilities - Now reporting update available through J-Link, no proprietary bootloader. --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c index 0635f76a6c..fcca09213e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c @@ -24,7 +24,6 @@ HAL_SYSTEM_CONFIG HalSystemConfig = HAL_TARGET_CONFIGURATION g_TargetConfiguration; -// this target can use JTAG for updates -// TODO -// inline GET_TARGET_CAPABILITIES(TargetCapabilities_JtagUpdate); -inline TARGET_HAS_PROPRIETARY_BOOTER(true); +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); From 57c532c9d6f56cf00b0f9e503dfdda81980e5309 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 14 Jun 2022 02:12:11 +0100 Subject: [PATCH 045/572] Completed implementation of CPU GPIO layer for Silabs Gecko SDK - Rework interrupt set/unset and debounce processing. - Remove adding SDK GPIO interrupts code and call to GPIOINT_Init(). --- CMake/Modules/FindGecko_SDK.cmake | 2 +- .../_common/autogen/sl_event_handler.c | 1 - .../_nanoCLR/System.Device.Gpio/cpu_gpio.cpp | 209 +++++++++++++----- 3 files changed, 160 insertions(+), 52 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index c4715ac4c6..ae96d3961f 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -70,7 +70,6 @@ set(gecko_sdk_srcs # emdrv dmadrv.c uartdrv.c - gpiointerrupt.c sl_device_init_dcdc_s1.c sl_device_init_emu_s1.c @@ -143,6 +142,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") # target series specific ${gecko_sdk_SOURCE_DIR}/platform/Device/SiliconLabs/EFM32GG11B/Source + # target specifics ${TARGET_BASE_LOCATION}/autogen ${TARGET_BASE_LOCATION}/config diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c index 955d4ece92..9952a568a1 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c @@ -47,7 +47,6 @@ void sl_kernel_start(void) void sl_driver_init(void) { - GPIOINT_Init(); // sl_i2cspm_init_instances(); sl_uartdrv_init_instances(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp index b10ab93051..aa279c4905 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp @@ -6,23 +6,29 @@ #include #include "sys_dev_gpio_native_target.h" -#define GPIO_MAX_PIN 256 -#define TOTAL_GPIO_PORTS ((GPIO_MAX_PIN + 15) / 16) +#define _GPIOINT_IF_EVEN_MASK ((_GPIO_IF_MASK)&0x55555555UL) +#define _GPIOINT_IF_ODD_MASK ((_GPIO_IF_MASK)&0xAAAAAAAAUL) +#define INTERRUPT_UNAVAILABLE (0xFF) -// Double linkedlist to hold the state of each Input pin +#define GPIO_MAX_PIN \ + _GPIO_PORT_A_PIN_COUNT + _GPIO_PORT_B_PIN_COUNT + _GPIO_PORT_C_PIN_COUNT + _GPIO_PORT_D_PIN_COUNT + \ + _GPIO_PORT_E_PIN_COUNT + _GPIO_PORT_F_PIN_COUNT + _GPIO_PORT_G_PIN_COUNT + _GPIO_PORT_H_PIN_COUNT + \ + _GPIO_PORT_I_PIN_COUNT + _GPIO_PORT_J_PIN_COUNT + _GPIO_PORT_K_PIN_COUNT + +// Double linked list to hold the state of each Input pin struct gpio_input_state : public HAL_DblLinkedNode { - // Pin number + // pin number GPIO_PIN pinNumber; - // debounce timer for this Pin + // debounce timer for this pin TX_TIMER debounceTimer; - // Ptr to user ISR or null + // pointer to user ISR or null GPIO_INTERRUPT_SERVICE_ROUTINE isrPtr; - // debounce Millsecs, no debonce=0 + // debounce milliseconds, NO debounce set to 0 uint32_t debounceMs; // Interrupt mode uint8_t mode; - // Param to user isr call + // Param to user ISR call void *param; // Expected state for debounce handler bool expected; @@ -30,8 +36,13 @@ struct gpio_input_state : public HAL_DblLinkedNode bool waitingDebounce; }; -static HAL_DblLinkedList gpioInputList; // Double Linked list for GPIO input status -static uint16_t pinReserved[TOTAL_GPIO_PORTS]; // reserved - 1 bit per pin +// Double Linked list for GPIO input status +static HAL_DblLinkedList gpioInputList; +// reserved - 1 bit per pin +static uint16_t pinReserved[GPIO_PORT_MAX]; + +// Array of user callbacks. One for each pin interrupt number. +static gpio_input_state *gpioCallbacks[32]; // this is an utility function to get a Gecko API port and pin from our "encoded" pin number void GetIoLine(int16_t pinNumber, GPIO_Port_TypeDef *port, uint32_t *portPin) @@ -45,11 +56,54 @@ bool IsValidGpioPin(GPIO_PIN pinNumber) return (pinNumber <= GPIO_MAX_PIN); } +// Register (or unregister) ISR for a pin +// send NULL in pinState to unregister callback +unsigned int CallbackRegisterExt(uint8_t pin, gpio_input_state *pinState) +{ + uint16_t intNo = INTERRUPT_UNAVAILABLE; + + TX_DISABLE + +#if defined(_GPIO_EXTIPINSELL_MASK) + uint32_t intToCheck; + uint32_t intGroupStart = (pin & 0xFFC); + uint32_t intsEnabled = GPIO_EnabledIntGet(); + + // loop through the interrupt group, starting + // from the pin number, and take + // the first available + for (uint8_t i = 0; i < 4; i++) + { + intToCheck = intGroupStart + ((pin + i) & 0x3); // modulo 4 + if (((intsEnabled >> intToCheck) & 0x1) == 0) + { + intNo = (unsigned int)intToCheck; + break; + } + } +#else + if (gpioCallbacks[pin] == NULL) + { + intNo = (unsigned int)pin; + } +#endif + + if (intNo != INTERRUPT_UNAVAILABLE) + { + gpioCallbacks[intNo] = pinState; + } + + TX_RESTORE + + return intNo; +} + // Get pointer to gpio_input_state for GPIO pin // return NULL if not found gpio_input_state *GetGpioWithInterrupt(uint16_t gpioPin) { gpio_input_state *ptr = gpioInputList.FirstNode(); + while (ptr->Next() != NULL) { if (GPIO_PIN(ptr->pinNumber) == gpioPin) @@ -88,51 +142,60 @@ static void DebounceTimerCallback(uint32_t id) pState->waitingDebounce = false; } -void GpioEventCallback(void *arg) +static void GpioEventCallback(uint32_t intFlags) { - NATIVE_INTERRUPT_START - - TX_DISABLE - - gpio_input_state *pGpio = (gpio_input_state *)arg; + // TX_DISABLE + uint32_t irqIdx; + gpio_input_state *pGpio; - if (pGpio != NULL) + // check for all flags set in IF register + while (intFlags != 0U) { - // Ignore any pin changes during debounce - if (!pGpio->waitingDebounce) - { - // check if there is a debounce time set - if (pGpio->debounceMs > 0) - { - // Set flag we are waiting for debounce on this pin - pGpio->waitingDebounce = true; - - // setup timer - tx_timer_deactivate(&pGpio->debounceTimer); - tx_timer_change(&pGpio->debounceTimer, 0, pGpio->debounceMs / 10); - tx_timer_activate(&pGpio->debounceTimer); - } - else - { - GPIO_Port_TypeDef port; - uint32_t portPin; - GetIoLine(pGpio->pinNumber, &port, &portPin); + irqIdx = SL_CTZ(intFlags); - TX_RESTORE + /* clear flag*/ + intFlags &= ~(1UL << irqIdx); - pGpio->isrPtr(pGpio->pinNumber, GPIO_PinInGet(port, portPin), pGpio->param); + pGpio = gpioCallbacks[irqIdx]; - TX_DISABLE + if (pGpio != NULL) + { + // Ignore any pin changes during debounce + if (!pGpio->waitingDebounce) + { + // check if there is a debounce time set + if (pGpio->debounceMs > 0) + { + // Set flag we are waiting for debounce on this pin + pGpio->waitingDebounce = true; + + // setup timer + tx_timer_deactivate(&pGpio->debounceTimer); + tx_timer_change(&pGpio->debounceTimer, 0, pGpio->debounceMs / 10); + tx_timer_activate(&pGpio->debounceTimer); + } + else + { + GPIO_Port_TypeDef port; + uint32_t portPin; + GetIoLine(pGpio->pinNumber, &port, &portPin); + + TX_RESTORE + + pGpio->isrPtr(pGpio->pinNumber, GPIO_PinInGet(port, portPin), pGpio->param); + + TX_DISABLE + } } } - } - TX_RESTORE + TX_RESTORE - NATIVE_INTERRUPT_END + NATIVE_INTERRUPT_END + } } -// Get pointer to gpio_input_state for Gpio pin +// Get pointer to gpio_input_state for GPIO pin // return NULL if not found gpio_input_state *GetInputState(GPIO_PIN pinNumber) { @@ -193,8 +256,7 @@ void UnlinkInputState(gpio_input_state *pState) // disable the EXT interrupt channel // it's OK to do always this, no matter if it's enabled or not - // TODO - // palDisableLineEvent(GetIoLine(pState->pinNumber)); + CallbackRegisterExt(portPin, NULL); pState->Unlink(); @@ -220,6 +282,21 @@ bool CPU_GPIO_Initialize() // Make sure all pins are not reserved memset(pinReserved, 0, sizeof(pinReserved)); + // "free" all GPIO interrupts + memset(gpioCallbacks, 0x0, sizeof(gpioCallbacks)); + + // enable the interrupt handler for all GPIOs + if (CORE_NvicIRQDisabled(GPIO_ODD_IRQn)) + { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + if (CORE_NvicIRQDisabled(GPIO_EVEN_IRQn)) + { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } + return true; } @@ -278,6 +355,7 @@ bool CPU_GPIO_PinIsBusy(GPIO_PIN pinNumber) } int port = pinNumber >> 4, sh = pinNumber & 0x0F; + return (pinReserved[port] >> sh) & 1; } @@ -357,12 +435,10 @@ bool CPU_GPIO_EnableInputPin( { // there are callbacks registered and... // the drive mode is input so need to setup the interrupt - GPIO_ExtIntConfig(port, portPin, portPin, 1, 1, true); // TODO - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - // palSetLineCallback(ioLine, GpioEventCallback, pState); + CallbackRegisterExt(portPin, pState); // store parameters & configs pState->isrPtr = pinISR; @@ -396,8 +472,7 @@ bool CPU_GPIO_EnableInputPin( // disable the EXT interrupt channel // it's OK to do always this, no matter if it's enabled or not - // TODO - // palDisableLineEvent(GetIoLine(pState->pinNumber)); + CallbackRegisterExt(portPin, NULL); // clear parameters & configs pState->isrPtr = NULL; @@ -535,3 +610,37 @@ bool CPU_GPIO_SetPinDebounce(GPIO_PIN pinNumber, uint32_t debounceTimeMillisecon return false; } + +void GPIO_EVEN_IRQHandler(void) +{ + NATIVE_INTERRUPT_START + + uint32_t intFlags; + + // Get all even interrupts + intFlags = GPIO_IntGetEnabled() & _GPIOINT_IF_EVEN_MASK; + + // Clean only even interrupts + GPIO_IntClear(intFlags); + + GpioEventCallback(intFlags); + + NATIVE_INTERRUPT_END +} + +void GPIO_ODD_IRQHandler(void) +{ + NATIVE_INTERRUPT_START + + uint32_t intFlags; + + // Get all odd interrupts + intFlags = GPIO_IntGetEnabled() & _GPIOINT_IF_ODD_MASK; + + // Clean only odd interrupts + GPIO_IntClear(intFlags); + + GpioEventCallback(intFlags); + + NATIVE_INTERRUPT_END +} From 4c188749d27659a426086d17acad3c990958a01d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Jun 2022 12:01:05 +0100 Subject: [PATCH 046/572] Initial work on I2C implementation --- CMakePresets.json | 2 +- .../target_system_device_i2c_config.cpp | 26 + .../target_system_device_i2c_config.h | 8 + .../_common/autogen/sl_event_handler.c | 2 +- ...i2c_native_System_Device_I2c_I2cDevice.cpp | 702 ++++++++++++++++++ .../sys_dev_i2c_native_target.h | 81 ++ 6 files changed, 819 insertions(+), 2 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h diff --git a/CMakePresets.json b/CMakePresets.json index e17b3d3b66..9308c91344 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -293,7 +293,7 @@ "API_Hardware.Stm32": "OFF", "API_System.Device.Gpio": "ON", "API_System.Device.Spi": "OFF", - "API_System.Device.I2c": "OFF", + "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6b72e6fbac --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C1 // +////////// + +////////// +// I2C2 // +////////// + +// Devices available in GG11 dev kit +// Modules | Description | +// Si7021 | Relative Humidity and Temperature Sensor | +// Si7210 | Hall-Effect Sensor | + +// pin configuration for I2C2 +// port for I2C2_SCL is: GPIOI_5 +// port for I2C2_SDA is: GPIOI_4 + +// GPIO alternate pin function is 7 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, gpioPortI, gpioPortI, 5, 4, 7, 7) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h new file mode 100644 index 0000000000..ce4adacec1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE +#define GECKO_USE_I2C2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c index 9952a568a1..2da9084cbe 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c @@ -47,7 +47,7 @@ void sl_kernel_start(void) void sl_driver_init(void) { - // sl_i2cspm_init_instances(); + sl_i2cspm_init_instances(); sl_uartdrv_init_instances(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp new file mode 100644 index 0000000000..a3879f33b4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -0,0 +1,702 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_i2c_native_target.h" + +typedef Library_sys_dev_i2c_native_System_Device_I2c_I2cConnectionSettings I2cConnectionSettings; +typedef Library_sys_dev_i2c_native_System_Device_I2c_I2cTransferResult I2cTransferResult; +typedef Library_corlib_native_System_SpanByte SpanByte; + +//////////////////////////////////////////// +// declaration of the the I2C PAL structs // +//////////////////////////////////////////// +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +NF_PAL_I2C I2C1_PAL; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +NF_PAL_I2C I2C2_PAL; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +NF_PAL_I2C I2C3_PAL; +#endif + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +uint8_t I2C1_DeviceCounter = 0; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +uint8_t I2C2_DeviceCounter = 0; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +uint8_t I2C3_DeviceCounter = 0; +#endif + +void GetI2cConfig(CLR_RT_HeapBlock *managedConfig, I2CSPM_Init_TypeDef *llConfig) +{ + I2cBusSpeed busSpeed = (I2cBusSpeed)managedConfig[I2cConnectionSettings::FIELD___busSpeed].NumericByRef().s4; + + llConfig->i2cRefFreq = busSpeed == I2cBusSpeed_StandardMode ? 0 : 1; +} + +// estimate the time required to perform the I2C transaction +bool IsLongRunningOperation( + uint16_t writeSize, + uint16_t readSize, + float byteTime, + uint32_t &estimatedDurationMiliseconds) +{ + // add an extra byte to account for the address + estimatedDurationMiliseconds = byteTime * (writeSize + readSize + 1); + + if (estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +// ThreadX I2C Working thread +static void I2CWorkingThread_entry(uint32_t arg) +{ + NF_PAL_I2C *palI2c = (NF_PAL_I2C *)arg; + + // int estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->WriteSize + palI2c->ReadSize + 1); + + // if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + // { + // // this is a Write/Read transaction + // palI2c->TransactionResult = i2cMasterTransmitTimeout( + // palI2c->Driver, + // palI2c->Address, + // palI2c->WriteBuffer, + // palI2c->WriteSize, + // palI2c->ReadBuffer, + // palI2c->ReadSize, + // TX_TICKS_PER_MILLISEC(estimatedDurationMiliseconds)); + // } + // else + // { + // if (palI2c->ReadSize == 0) + // { + // // this is Write only transaction + + // estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->WriteSize + 1); + + // palI2c->TransactionResult = i2cMasterTransmitTimeout( + // palI2c->Driver, + // palI2c->Address, + // palI2c->WriteBuffer, + // palI2c->WriteSize, + // NULL, + // 0, + // TX_TICKS_PER_MILLISEC(estimatedDurationMiliseconds)); + // } + // else + // { + // // this is a Read only transaction + + // estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->ReadSize + 1); + + // palI2c->TransactionResult = i2cMasterReceiveTimeout( + // palI2c->Driver, + // palI2c->Address, + // palI2c->ReadBuffer, + // palI2c->ReadSize, + // TX_TICKS_PER_MILLISEC(estimatedDurationMiliseconds)); + // } + // } + + // fire event for I2C transaction complete + Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); + + // terminate this thread + tx_thread_terminate(palI2c->WorkingThread); +} + +HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_I2C *palI2c = NULL; + CLR_RT_HeapBlock *connectionSettings; + uint8_t busIndex; + I2CSPM_Init_TypeDef i2cInit = I2CSPM_INIT_DEFAULT; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get a pointer to the managed I2C connectionSettings object instance + connectionSettings = pThis[FIELD___connectionSettings].Dereference(); + + // get bus index + busIndex = (uint8_t)connectionSettings[I2cConnectionSettings::FIELD___busId].NumericByRef().s4; + + // config GPIO pins used by the I2C peripheral + // init the PAL struct for this I2C bus and assign the respective driver + // all this occurs if not already done + // why do we need to check if this is already done? because several I2cDevice objects can be created associated to + // the same bus just using different addresses + switch (busIndex) + { + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 1: + if (I2C1_PAL.Configuration == NULL) + { + I2C1_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C1_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C1_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C1(); + + I2C1_PAL.Configuration->port = I2C0; + palI2c = &I2C1_PAL; + + // increase device counter + I2C1_DeviceCounter++; + } + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 2: + if (I2C2_PAL.Configuration == NULL) + { + I2C2_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C2_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C2_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C2(); + + I2C2_PAL.Configuration->port = I2C1; + palI2c = &I2C2_PAL; + + // increase device counter + I2C2_DeviceCounter++; + } + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 3: + if (I2C3_PAL.Configuration == NULL) + { + I2C3_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C3_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C3_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C3(); + + I2C3_PAL.Configuration->port = I2C2; + palI2c = &I2C1_PAL; + + // increase device counter + I2C3_DeviceCounter++; + } + + break; +#endif + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Get a general low-level I2C configuration, depending on user's managed parameters + GetI2cConfig(connectionSettings, palI2c->Configuration); + + I2CSPM_Init(palI2c->Configuration); + + // compute rough estimate on the time to tx/rx a byte (in milliseconds) + if ((I2cBusSpeed)connectionSettings[I2cConnectionSettings::FIELD___busSpeed].NumericByRef().s4 == + I2cBusSpeed_StandardMode) + { + // 100kbit/s: this is roughly 0.10ms per byte, give or take + palI2c->ByteTime = 0.1; + } + else + { + // 400kbit/s: this is roughly 0.02ms per byte, give or take + palI2c->ByteTime = 0.02; + } + + // clear pointer to working thread + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeDispose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t busIndex; + NF_PAL_I2C *palI2c = NULL; + + CLR_RT_HeapBlock *connectionSettings; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get a pointer to the managed I2C connectionSettings object instance + connectionSettings = pThis[FIELD___connectionSettings].Dereference(); + + // get bus index + busIndex = (uint8_t)connectionSettings[I2cConnectionSettings::FIELD___busId].NumericByRef().s4; + + // get the driver for the I2C bus + switch (busIndex) + { +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 1: + palI2c = &I2C1_PAL; + + // remove device + I2C1_DeviceCounter--; + + if (I2C1_DeviceCounter == 0) + { + // no more devices on the bus + + // free memory + platform_free(I2C1_PAL.Configuration); + + // clears configuration + I2C1_PAL.Configuration = NULL; + } + + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 2: + palI2c = &I2C2_PAL; + + // remove device + I2C2_DeviceCounter--; + + if (I2C2_DeviceCounter == 0) + { + // no more devices on the bus + + // free memory + platform_free(I2C2_PAL.Configuration); + + // clears configuration + I2C2_PAL.Configuration = NULL; + } + + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 3: + palI2c = &I2C3_PAL; + + // remove device + I2C3_DeviceCounter--; + + if (I2C3_DeviceCounter == 0) + { + // no more devices on the bus + + // free memory + platform_free(I2C3_PAL.Configuration); + + // clears configuration + I2C3_PAL.Configuration = NULL; + } + + break; +#endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // stop working thread, if it's running + if (palI2c->WorkingThread != NULL) + { + // delete thread + tx_thread_delete(palI2c->WorkingThread); + + // free stack memory + platform_free(palI2c->WorkingThreadStack); + + // clear pointers + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: + NativeTransmit___SystemDeviceI2cI2cTransferResult__SystemSpanByte__SystemSpanByte(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + { + uint8_t busIndex; + NF_PAL_I2C *palI2c = NULL; + bool isLongRunningOperation = false; + // msg_t transactionResult = MSG_OK; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + CLR_RT_HeapBlock *result; + CLR_RT_HeapBlock *writeSpanByte; + CLR_RT_HeapBlock *readSpanByte; + CLR_RT_HeapBlock_Array *writeBuffer = NULL; + CLR_RT_HeapBlock_Array *readBuffer = NULL; + int readOffset = 0; + int writeOffset = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get pointer to connection settings field + CLR_RT_HeapBlock *connectionSettings = pThis[FIELD___connectionSettings].Dereference(); + + // get bus index + busIndex = (uint8_t)connectionSettings[I2cConnectionSettings::FIELD___busId].NumericByRef().s4; + + // get the driver for the I2C bus + switch (busIndex) + { +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 1: + palI2c = &I2C1_PAL; + break; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 2: + palI2c = &I2C2_PAL; + break; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 3: + palI2c = &I2C3_PAL; + break; +#endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // dereference the write and read SpanByte from the arguments + writeSpanByte = stack.Arg1().Dereference(); + + if (writeSpanByte != NULL) + { + // get buffer + writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (writeBuffer != NULL) + { + // Get the write offset, only the elements defined by the span must be written, not the whole array + writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as write size, only the elements defined by the span must be written + palI2c->WriteSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + } + } + + if (writeBuffer == NULL) + { + // nothing to write, have to zero this + palI2c->WriteSize = 0; + } + + readSpanByte = stack.Arg2().Dereference(); + + if (readSpanByte != NULL) + { + // get buffer + readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (readBuffer != NULL) + { + // Get the read offset, only the elements defined by the span must be read, not the whole array + readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as read size, only the elements defined by the span must be read + palI2c->ReadSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + } + } + + if (readBuffer == NULL) + { + // nothing to read, have to zero this + palI2c->ReadSize = 0; + } + + // check if this is a long running operation + isLongRunningOperation = IsLongRunningOperation( + palI2c->WriteSize, + palI2c->ReadSize, + palI2c->ByteTime, + (uint32_t &)estimatedDurationMiliseconds); + + if (isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in + // milliseconds this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer(*writeBuffer); + CLR_RT_ProtectFromGC gcReadBuffer(*readBuffer); + } + + // this is going to be used to check for the right event in case of simultaneous I2C transaction + if (!isLongRunningOperation || stack.m_customState == 1) + { + // get slave address from connection settings field + palI2c->Address = + (i2caddr_t)connectionSettings[I2cConnectionSettings::FIELD___deviceAddress].NumericByRef().s4; + + // when using I2Cv1 driver the address needs to be loaded in the I2C driver struct +#if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32L1XX) + palI2c->Driver->addr = palI2c->Address; +#endif + + if (writeBuffer != NULL) + { + // grab the pointer to the array by starting and the offset specified in the span + palI2c->WriteBuffer = (uint8_t *)writeBuffer->GetElement(writeOffset); + } + + if (readBuffer != NULL) + { + // grab the pointer to the array by starting and the offset specified in the span + palI2c->ReadBuffer = (uint8_t *)readBuffer->GetElement(readOffset); + } + + // because the bus access is shared, acquire the appropriate bus + i2cAcquireBus(palI2c->Driver); + i2cStart(palI2c->Driver, &palI2c->Configuration); + } + + if (isLongRunningOperation) + { + // this is a long running operation and hasn't started yet + // perform I2C transaction using driver's ASYNC API which is launching a thread to perform it + if (stack.m_customState == 1) + { + // spawn working thread to perform the I2C transaction + + // 1. allocate memory for I2C thread + palI2c->WorkingThreadStack = (uint32_t *)platform_malloc(I2C_THREAD_STACK_SIZE); + + if (palI2c->WorkingThreadStack == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // 2. create thread + uint16_t status = tx_thread_create( + palI2c->WorkingThread, +#if !defined(BUILD_RTM) + (CHAR *)"I2C Thread", +#else + NULL, +#endif + I2CWorkingThread_entry, + (uint32_t)palI2c, + palI2c->WorkingThreadStack, + I2C_THREAD_STACK_SIZE, + I2C_THREAD_PRIORITY, + I2C_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + else + { + // this is NOT a long running operation + // perform I2C transaction using driver's SYNC API + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + transactionResult = i2cMasterTransmitTimeout( + palI2c->Driver, + palI2c->Address, + palI2c->WriteBuffer, + palI2c->WriteSize, + palI2c->ReadBuffer, + palI2c->ReadSize, + TX_TICKS_PER_MILLISEC(20)); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + transactionResult = i2cMasterTransmitTimeout( + palI2c->Driver, + palI2c->Address, + palI2c->WriteBuffer, + palI2c->WriteSize, + NULL, + 0, + TX_TICKS_PER_MILLISEC(20)); + } + else + { + // this is a Read only transaction + transactionResult = i2cMasterReceiveTimeout( + palI2c->Driver, + palI2c->Address, + palI2c->ReadBuffer, + palI2c->ReadSize, + TX_TICKS_PER_MILLISEC(20)); + } + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + if (palI2c->WorkingThread->tx_thread_state == TX_TERMINATED) + { + // I2C working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_I2cMaster, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + if (eventResult || !isLongRunningOperation) + { + // event occurred + // OR this is NOT a long running operation + + i2cReleaseBus(palI2c->Driver); + + // create the return object (I2cTransferResult) + // only at this point we are sure that there will be a return from this thread so it's OK to use the + // managed stack + CLR_RT_HeapBlock &top = stack.PushValueAndClear(); + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_I2cTransferResult)); + result = top.Dereference(); + FAULT_ON_NULL(result); + + if (isLongRunningOperation) + { + // get transaction result from I2C struct + transactionResult = palI2c->TransactionResult; + + // delete thread + tx_thread_delete(palI2c->WorkingThread); + + // free stack memory + platform_free(palI2c->WorkingThreadStack); + + // clear pointers + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + } + + // get the result from the working thread execution + if (transactionResult != MSG_OK) + { + // error in transaction + int errors = i2cGetErrors(palI2c->Driver); + + // figure out what was the error and set the status field + switch (errors) + { + case I2C_ACK_FAILURE: + result[I2cTransferResult::FIELD___status].SetInteger( + (CLR_UINT32)I2cTransferStatus_SlaveAddressNotAcknowledged); + break; + + case I2C_TIMEOUT: + result[I2cTransferResult::FIELD___status].SetInteger( + (CLR_UINT32)I2cTransferStatus_ClockStretchTimeout); + break; + + default: + result[I2cTransferResult::FIELD___status].SetInteger( + (CLR_UINT32)I2cTransferStatus_UnknownError); + } + + // set the bytes transferred count to 0 because we don't have a way to know how many bytes were + // actually sent/received + result[I2cTransferResult::FIELD___bytesTransferred].SetInteger(0); + } + else + { + // successful transaction + // set the result field + result[I2cTransferResult::FIELD___status].SetInteger((CLR_UINT32)I2cTransferStatus_FullTransfer); + + // set the bytes transferred field + result[I2cTransferResult::FIELD___bytesTransferred].SetInteger( + (CLR_UINT32)(palI2c->WriteSize + palI2c->ReadSize)); + } + } + } + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h new file mode 100644 index 0000000000..efc04f4687 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h @@ -0,0 +1,81 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_I2C_NATIVE_TARGET_H +#define SYS_DEV_I2C_NATIVE_TARGET_H + +#include +#include +#include + +#include +#include +#include +#include + +// receiver thread +#define I2C_THREAD_STACK_SIZE 256 +#define I2C_THREAD_PRIORITY 5 + +// struct representing the I2C +typedef struct NF_PAL_I2C +{ + I2CSPM_Init_TypeDef *Configuration; + TX_THREAD *WorkingThread; + uint32_t *WorkingThreadStack; + // msg_t TransactionResult; + // i2caddr_t Address; + float ByteTime; + + uint8_t *WriteBuffer; + uint8_t WriteSize; + + uint8_t *ReadBuffer; + uint8_t ReadSize; +} NF_PAL_I2C; + +//////////////////////////////////////////// +// declaration of the the I2C PAL structs // +//////////////////////////////////////////// +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +extern NF_PAL_I2C I2C1_PAL; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +extern NF_PAL_I2C I2C2_PAL; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +extern NF_PAL_I2C I2C2_PAL; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + +// the following macro defines a function that configures the GPIO pins for a Gecko I2C peripheral +// it gets called in the System_Device_I2c_I2cDevice::NativeInit function +// this is required because the I2C peripherals can use multiple GPIO configuration combinations +#define I2C_CONFIG_PINS(num, gpio_port_scl, gpio_port_sda, scl_pin, sda_pin, scl_port_location, sda_port_location) \ + void ConfigPins_I2C##num() \ + { \ + I2C##num##_PAL.Configuration->sclPort = gpio_port_scl; \ + I2C##num##_PAL.Configuration->sdaPort = gpio_port_sda; \ + I2C##num##_PAL.Configuration->sclPin = scl_pin; \ + I2C##num##_PAL.Configuration->sdaPin = sda_pin; \ + I2C##num##_PAL.Configuration->portLocationScl = scl_port_location; \ + I2C##num##_PAL.Configuration->portLocationSda = sda_port_location; \ + } + +#else +#error \ + "Only _SILICON_LABS_32B_SERIES_1 is supported at this time. To add support for other series declaration above has to be updated" +#endif + +////////////////////////////////////////////////////////////////////////////////////////////// +// when an I2C is defined the declarations below will have the real function/configuration // +// in the target folder @ target_windows_devices_i2c_config.cpp // +////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_I2C1(); +void ConfigPins_I2C2(); +void ConfigPins_I2C3(); + +#endif // SYS_DEV_I2C_NATIVE_TARGET_H From c73c1a81cb8d5d9aea7231c251fe1e0ba498dd2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Jun 2022 13:59:44 +0100 Subject: [PATCH 047/572] Complete work on I2C implementation --- .../target_system_device_i2c_config.cpp | 6 +- .../target_system_device_i2c_config.h | 4 +- ...i2c_native_System_Device_I2c_I2cDevice.cpp | 162 ++++++++---------- .../sys_dev_i2c_native_target.h | 15 +- 4 files changed, 90 insertions(+), 97 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp index 6b72e6fbac..07ac77a270 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp @@ -16,11 +16,11 @@ // Devices available in GG11 dev kit // Modules | Description | // Si7021 | Relative Humidity and Temperature Sensor | -// Si7210 | Hall-Effect Sensor | +// Si7210 | Hall-Effect Sensor | // pin configuration for I2C2 -// port for I2C2_SCL is: GPIOI_5 -// port for I2C2_SDA is: GPIOI_4 +// port for I2C2_SCL is: GPIOI_5 +// port for I2C2_SDA is: GPIOI_4 // GPIO alternate pin function is 7 for both pins (see alternate function mapping table in device datasheet) I2C_CONFIG_PINS(2, gpioPortI, gpioPortI, 5, 4, 7, 7) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h index ce4adacec1..3f5d19af26 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h @@ -3,6 +3,4 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE -#define GECKO_USE_I2C2 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp index a3879f33b4..8c3c2fe835 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -64,52 +64,45 @@ bool IsLongRunningOperation( static void I2CWorkingThread_entry(uint32_t arg) { NF_PAL_I2C *palI2c = (NF_PAL_I2C *)arg; + I2C_TransferSeq_TypeDef i2cTransfer; - // int estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->WriteSize + palI2c->ReadSize + 1); - - // if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) - // { - // // this is a Write/Read transaction - // palI2c->TransactionResult = i2cMasterTransmitTimeout( - // palI2c->Driver, - // palI2c->Address, - // palI2c->WriteBuffer, - // palI2c->WriteSize, - // palI2c->ReadBuffer, - // palI2c->ReadSize, - // TX_TICKS_PER_MILLISEC(estimatedDurationMiliseconds)); - // } - // else - // { - // if (palI2c->ReadSize == 0) - // { - // // this is Write only transaction - - // estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->WriteSize + 1); - - // palI2c->TransactionResult = i2cMasterTransmitTimeout( - // palI2c->Driver, - // palI2c->Address, - // palI2c->WriteBuffer, - // palI2c->WriteSize, - // NULL, - // 0, - // TX_TICKS_PER_MILLISEC(estimatedDurationMiliseconds)); - // } - // else - // { - // // this is a Read only transaction - - // estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->ReadSize + 1); - - // palI2c->TransactionResult = i2cMasterReceiveTimeout( - // palI2c->Driver, - // palI2c->Address, - // palI2c->ReadBuffer, - // palI2c->ReadSize, - // TX_TICKS_PER_MILLISEC(estimatedDurationMiliseconds)); - // } - // } + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + i2cTransfer.flags = I2C_FLAG_WRITE_READ; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = palI2c->ReadBuffer; + i2cTransfer.buf[1].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + i2cTransfer.flags = I2C_FLAG_WRITE; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + // this is a Read only transaction + i2cTransfer.flags = I2C_FLAG_READ; + i2cTransfer.buf[0].data = palI2c->ReadBuffer; + i2cTransfer.buf[0].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + } // fire event for I2C transaction complete Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); @@ -368,7 +361,6 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: uint8_t busIndex; NF_PAL_I2C *palI2c = NULL; bool isLongRunningOperation = false; - // msg_t transactionResult = MSG_OK; CLR_RT_HeapBlock hbTimeout; CLR_INT64 *timeout; @@ -382,6 +374,8 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: CLR_RT_HeapBlock_Array *readBuffer = NULL; int readOffset = 0; int writeOffset = 0; + I2C_TransferSeq_TypeDef i2cTransfer; + I2C_TransferReturn_TypeDef transactionResult = i2cTransferInProgress; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -488,14 +482,10 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: // this is going to be used to check for the right event in case of simultaneous I2C transaction if (!isLongRunningOperation || stack.m_customState == 1) { - // get slave address from connection settings field - palI2c->Address = - (i2caddr_t)connectionSettings[I2cConnectionSettings::FIELD___deviceAddress].NumericByRef().s4; - // when using I2Cv1 driver the address needs to be loaded in the I2C driver struct -#if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32L1XX) - palI2c->Driver->addr = palI2c->Address; -#endif + // get slave address from connection settings field + i2cTransfer.addr = + (uint16_t)connectionSettings[I2cConnectionSettings::FIELD___deviceAddress].NumericByRef().s4; if (writeBuffer != NULL) { @@ -508,10 +498,6 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: // grab the pointer to the array by starting and the offset specified in the span palI2c->ReadBuffer = (uint8_t *)readBuffer->GetElement(readOffset); } - - // because the bus access is shared, acquire the appropriate bus - i2cAcquireBus(palI2c->Driver); - i2cStart(palI2c->Driver, &palI2c->Configuration); } if (isLongRunningOperation) @@ -559,43 +545,43 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: else { // this is NOT a long running operation - // perform I2C transaction using driver's SYNC API + // perform I2C transaction if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) { // this is a Write/Read transaction - transactionResult = i2cMasterTransmitTimeout( - palI2c->Driver, - palI2c->Address, - palI2c->WriteBuffer, - palI2c->WriteSize, - palI2c->ReadBuffer, - palI2c->ReadSize, - TX_TICKS_PER_MILLISEC(20)); + i2cTransfer.flags = I2C_FLAG_WRITE_READ; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = palI2c->ReadBuffer; + i2cTransfer.buf[1].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); } else { if (palI2c->ReadSize == 0) { // this is Write only transaction - transactionResult = i2cMasterTransmitTimeout( - palI2c->Driver, - palI2c->Address, - palI2c->WriteBuffer, - palI2c->WriteSize, - NULL, - 0, - TX_TICKS_PER_MILLISEC(20)); + i2cTransfer.flags = I2C_FLAG_WRITE; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); } else { // this is a Read only transaction - transactionResult = i2cMasterReceiveTimeout( - palI2c->Driver, - palI2c->Address, - palI2c->ReadBuffer, - palI2c->ReadSize, - TX_TICKS_PER_MILLISEC(20)); + i2cTransfer.flags = I2C_FLAG_READ; + i2cTransfer.buf[0].data = palI2c->ReadBuffer; + i2cTransfer.buf[0].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); } } } @@ -630,8 +616,6 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: // event occurred // OR this is NOT a long running operation - i2cReleaseBus(palI2c->Driver); - // create the return object (I2cTransferResult) // only at this point we are sure that there will be a return from this thread so it's OK to use the // managed stack @@ -658,20 +642,20 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: } // get the result from the working thread execution - if (transactionResult != MSG_OK) + if (transactionResult != i2cTransferDone) { - // error in transaction - int errors = i2cGetErrors(palI2c->Driver); - // figure out what was the error and set the status field - switch (errors) + switch (transactionResult) { - case I2C_ACK_FAILURE: + case i2cTransferNack: result[I2cTransferResult::FIELD___status].SetInteger( (CLR_UINT32)I2cTransferStatus_SlaveAddressNotAcknowledged); break; - case I2C_TIMEOUT: + case i2cTransferBusErr: + case i2cTransferArbLost: + case i2cTransferUsageFault: + case i2cTransferSwFault: result[I2cTransferResult::FIELD___status].SetInteger( (CLR_UINT32)I2cTransferStatus_ClockStretchTimeout); break; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h index efc04f4687..1897e3d711 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h @@ -19,14 +19,25 @@ #define I2C_THREAD_STACK_SIZE 256 #define I2C_THREAD_PRIORITY 5 +// set missing defines +#ifndef GECKO_USE_I2C0 +#define GECKO_USE_I2C0 FALSE +#endif +#ifndef GECKO_USE_I2C1 +#define GECKO_USE_I2C1 TRUE +#endif +#ifndef GECKO_USE_I2C2 +#define GECKO_USE_I2C2 FALSE +#endif + // struct representing the I2C typedef struct NF_PAL_I2C { I2CSPM_Init_TypeDef *Configuration; TX_THREAD *WorkingThread; uint32_t *WorkingThreadStack; - // msg_t TransactionResult; - // i2caddr_t Address; + I2C_TransferReturn_TypeDef TransactionResult; + uint16_t Address; float ByteTime; uint8_t *WriteBuffer; From 5062c0f6897d69ff6ad4bd74e92d5899a3f93951 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Jun 2022 14:28:32 +0100 Subject: [PATCH 048/572] Enable Sys.Math --- CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakePresets.json b/CMakePresets.json index 9308c91344..ade239bef3 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -289,7 +289,7 @@ "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", - "API_System.Math": "OFF", + "API_System.Math": "ON", "API_Hardware.Stm32": "OFF", "API_System.Device.Gpio": "ON", "API_System.Device.Spi": "OFF", From 89de0180115d2631a8ebdf09746834dd96e4c0c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Jun 2022 15:04:43 +0100 Subject: [PATCH 049/572] Fix WP for large packets - Increase internal buffer size. - Set WP packet size to 512. --- .../SL_STK3701A/config/sl_iostream_usart_vcom_config.h | 2 +- .../AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h index e596b6c1eb..59d33b8885 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_iostream_usart_vcom_config.h @@ -65,7 +65,7 @@ // Receive buffer size // Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 64 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 // Convert \n to \r\n // It can be changed at runtime using the C API. diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in index a3d794155d..e5a3715d66 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.h.in @@ -34,6 +34,13 @@ #define PLATFORMNAMESTRING "GGECKO_S1" ////////////////////////////////////////////// +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + ///////////////////////////////////// #define PLATFORM_HAS_RNG TRUE ///////////////////////////////////// From 4b1901c7dcba08844946e354b6df38a5e662c294 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 14 Jun 2022 19:11:08 +0100 Subject: [PATCH 050/572] Fixes in I2C implementation --- .../target_system_device_i2c_config.cpp | 4 - .../target_system_device_i2c_config.h | 2 +- .../_common/autogen/sl_i2cspm_init.c | 1 - ...i2c_native_System_Device_I2c_I2cDevice.cpp | 122 +++++++++++------- .../sys_dev_i2c_native_target.h | 8 +- 5 files changed, 80 insertions(+), 57 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp index 07ac77a270..2914cfa6c8 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp @@ -5,10 +5,6 @@ #include -////////// -// I2C1 // -////////// - ////////// // I2C2 // ////////// diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h index 3f5d19af26..847fb55566 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h @@ -3,4 +3,4 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_I2C1 TRUE +#define GECKO_USE_I2C2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c index 483e9f8381..042abb18a8 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_i2cspm_init.c @@ -38,5 +38,4 @@ I2CSPM_Init_TypeDef init_sensor = { void sl_i2cspm_init_instances(void) { CMU_ClockEnable(cmuClock_GPIO, true); - //I2CSPM_Init(&init_sensor); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp index 8c3c2fe835..319f678956 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -13,30 +13,39 @@ typedef Library_corlib_native_System_SpanByte SpanByte; // declaration of the the I2C PAL structs // //////////////////////////////////////////// #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) -NF_PAL_I2C I2C1_PAL; +NF_PAL_I2C I2C0_PAL; #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) -NF_PAL_I2C I2C2_PAL; +NF_PAL_I2C I2C1_PAL; #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) -NF_PAL_I2C I2C3_PAL; +NF_PAL_I2C I2C2_PAL; #endif #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) -uint8_t I2C1_DeviceCounter = 0; +uint8_t I2C0_DeviceCounter = 0; #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) -uint8_t I2C2_DeviceCounter = 0; +uint8_t I2C1_DeviceCounter = 0; #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) -uint8_t I2C3_DeviceCounter = 0; +uint8_t I2C2_DeviceCounter = 0; #endif void GetI2cConfig(CLR_RT_HeapBlock *managedConfig, I2CSPM_Init_TypeDef *llConfig) { I2cBusSpeed busSpeed = (I2cBusSpeed)managedConfig[I2cConnectionSettings::FIELD___busSpeed].NumericByRef().s4; - llConfig->i2cRefFreq = busSpeed == I2cBusSpeed_StandardMode ? 0 : 1; + if (busSpeed == I2cBusSpeed_StandardMode) + { + llConfig->i2cMaxFreq = I2C_FREQ_STANDARD_MAX; + llConfig->i2cClhr = i2cClockHLRStandard; + } + else + { + llConfig->i2cMaxFreq = I2C_FREQ_FAST_MAX; + llConfig->i2cClhr = i2cClockHLRAsymetric; + } } // estimate the time required to perform the I2C transaction @@ -138,11 +147,15 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOI switch (busIndex) { + //////////////////////////////////// + // Gecko I2C bus index is 0 based // + //////////////////////////////////// + #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) case 1: - if (I2C1_PAL.Configuration == NULL) + if (I2C0_PAL.Configuration == NULL) { - I2C1_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + I2C0_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); if (I2C1_PAL.Configuration == NULL) { @@ -150,65 +163,65 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOI } // copy init struct - memcpy(I2C1_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + memcpy(I2C0_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); - ConfigPins_I2C1(); + ConfigPins_I2C0(); - I2C1_PAL.Configuration->port = I2C0; + I2C0_PAL.Configuration->port = I2C0; palI2c = &I2C1_PAL; // increase device counter - I2C1_DeviceCounter++; + I2C0_DeviceCounter++; } break; #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) case 2: - if (I2C2_PAL.Configuration == NULL) + if (I2C1_PAL.Configuration == NULL) { - I2C2_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + I2C1_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); - if (I2C2_PAL.Configuration == NULL) + if (I2C1_PAL.Configuration == NULL) { NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); } // copy init struct - memcpy(I2C2_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + memcpy(I2C1_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); - ConfigPins_I2C2(); + ConfigPins_I2C1(); - I2C2_PAL.Configuration->port = I2C1; - palI2c = &I2C2_PAL; + I2C1_PAL.Configuration->port = I2C1; + palI2c = &I2C1_PAL; // increase device counter - I2C2_DeviceCounter++; + I2C1_DeviceCounter++; } break; #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) case 3: - if (I2C3_PAL.Configuration == NULL) + if (I2C2_PAL.Configuration == NULL) { - I2C3_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + I2C2_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); - if (I2C3_PAL.Configuration == NULL) + if (I2C2_PAL.Configuration == NULL) { NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); } // copy init struct - memcpy(I2C3_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + memcpy(I2C2_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); - ConfigPins_I2C3(); + ConfigPins_I2C2(); - I2C3_PAL.Configuration->port = I2C2; - palI2c = &I2C1_PAL; + I2C2_PAL.Configuration->port = I2C2; + palI2c = &I2C2_PAL; // increase device counter - I2C3_DeviceCounter++; + I2C2_DeviceCounter++; } break; @@ -265,24 +278,29 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeDispose___ busIndex = (uint8_t)connectionSettings[I2cConnectionSettings::FIELD___busId].NumericByRef().s4; // get the driver for the I2C bus + // Gecko I2C bus index is 0 based switch (busIndex) { + //////////////////////////////////// + // Gecko I2C bus index is 0 based // + //////////////////////////////////// + #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) case 1: - palI2c = &I2C1_PAL; + palI2c = &I2C0_PAL; // remove device - I2C1_DeviceCounter--; + I2C0_DeviceCounter--; - if (I2C1_DeviceCounter == 0) + if (I2C0_DeviceCounter == 0) { // no more devices on the bus // free memory - platform_free(I2C1_PAL.Configuration); + platform_free(I2C0_PAL.Configuration); // clears configuration - I2C1_PAL.Configuration = NULL; + I2C0_PAL.Configuration = NULL; } break; @@ -290,20 +308,20 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeDispose___ #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) case 2: - palI2c = &I2C2_PAL; + palI2c = &I2C1_PAL; // remove device - I2C2_DeviceCounter--; + I2C1_DeviceCounter--; - if (I2C2_DeviceCounter == 0) + if (I2C1_DeviceCounter == 0) { // no more devices on the bus // free memory - platform_free(I2C2_PAL.Configuration); + platform_free(I2C1_PAL.Configuration); // clears configuration - I2C2_PAL.Configuration = NULL; + I2C1_PAL.Configuration = NULL; } break; @@ -311,20 +329,20 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeDispose___ #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) case 3: - palI2c = &I2C3_PAL; + palI2c = &I2C2_PAL; // remove device - I2C3_DeviceCounter--; + I2C2_DeviceCounter--; - if (I2C3_DeviceCounter == 0) + if (I2C2_DeviceCounter == 0) { // no more devices on the bus // free memory - platform_free(I2C3_PAL.Configuration); + platform_free(I2C2_PAL.Configuration); // clears configuration - I2C3_PAL.Configuration = NULL; + I2C2_PAL.Configuration = NULL; } break; @@ -390,19 +408,25 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: // get the driver for the I2C bus switch (busIndex) { + //////////////////////////////////// + // Gecko I2C bus index is 0 based // + //////////////////////////////////// + #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) case 1: - palI2c = &I2C1_PAL; + palI2c = &I2C0_PAL; break; #endif + #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) case 2: - palI2c = &I2C2_PAL; + palI2c = &I2C1_PAL; break; #endif + #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) case 3: - palI2c = &I2C3_PAL; + palI2c = &I2C2_PAL; break; #endif @@ -569,6 +593,8 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: i2cTransfer.buf[0].data = palI2c->WriteBuffer; i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = NULL; + i2cTransfer.buf[1].len = 0; // Perform the transfer and return status from the transfer transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); @@ -579,6 +605,8 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: i2cTransfer.flags = I2C_FLAG_READ; i2cTransfer.buf[0].data = palI2c->ReadBuffer; i2cTransfer.buf[0].len = palI2c->ReadSize; + i2cTransfer.buf[1].data = NULL; + i2cTransfer.buf[1].len = 0; // Perform the transfer and return status from the transfer transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h index 1897e3d711..ea061edc53 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h @@ -24,7 +24,7 @@ #define GECKO_USE_I2C0 FALSE #endif #ifndef GECKO_USE_I2C1 -#define GECKO_USE_I2C1 TRUE +#define GECKO_USE_I2C1 FALSE #endif #ifndef GECKO_USE_I2C2 #define GECKO_USE_I2C2 FALSE @@ -51,10 +51,10 @@ typedef struct NF_PAL_I2C // declaration of the the I2C PAL structs // //////////////////////////////////////////// #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) -extern NF_PAL_I2C I2C1_PAL; +extern NF_PAL_I2C I2C0_PAL; #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) -extern NF_PAL_I2C I2C2_PAL; +extern NF_PAL_I2C I2C1_PAL; #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) extern NF_PAL_I2C I2C2_PAL; @@ -85,8 +85,8 @@ extern NF_PAL_I2C I2C2_PAL; // when an I2C is defined the declarations below will have the real function/configuration // // in the target folder @ target_windows_devices_i2c_config.cpp // ////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_I2C0(); void ConfigPins_I2C1(); void ConfigPins_I2C2(); -void ConfigPins_I2C3(); #endif // SYS_DEV_I2C_NATIVE_TARGET_H From a623198b2fb9b624701362ca460b619b85311a5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 14 Jun 2022 19:11:38 +0100 Subject: [PATCH 051/572] Enable RHT sensor in board --- .../SiliconLabs/SL_STK3701A/config/sl_board_control_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h index 079efde3b3..498641cd43 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h @@ -43,7 +43,7 @@ // Enable Relative Humidity and Temperature sensor // Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 // Enable Hall Effect sensor // Default: 0 From 40884db67ec2129fc358da5e3a5e707c7830d98d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 14 Jun 2022 19:12:04 +0100 Subject: [PATCH 052/572] Fix CLR init - Also clean up unused includes. --- .../AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index df3c260e82..a44296c778 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -8,24 +8,16 @@ #include #include #include +#include #include #include -// #include #include #include // #include -// #include -// #include -// #include -// #include -// #include -// #include -// #include - // extern TX_EVENT_FLAGS_GROUP wpUartEvent; extern CLR_SETTINGS clrSettings; @@ -162,6 +154,8 @@ void tx_application_define(void *first_unused_memory) int main(void) { // Initialize the board + sl_board_preinit(); + sl_board_init(); sl_driver_init(); sl_service_init(); sl_stack_init(); From 5fc897888659b1b6c1d2cc8ca01eac6b5ac16751 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Jun 2022 01:24:04 +0100 Subject: [PATCH 053/572] More fixes in I2C - Address has to be rotated to match expected left alignment in Gecko I2C API. - No need to set empty values on just read or just write transactions. --- .../sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp index 319f678956..80c16fa267 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -509,7 +509,7 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: // get slave address from connection settings field i2cTransfer.addr = - (uint16_t)connectionSettings[I2cConnectionSettings::FIELD___deviceAddress].NumericByRef().s4; + (uint16_t)connectionSettings[I2cConnectionSettings::FIELD___deviceAddress].NumericByRef().s4 << 1; if (writeBuffer != NULL) { @@ -593,8 +593,6 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: i2cTransfer.buf[0].data = palI2c->WriteBuffer; i2cTransfer.buf[0].len = palI2c->WriteSize; - i2cTransfer.buf[1].data = NULL; - i2cTransfer.buf[1].len = 0; // Perform the transfer and return status from the transfer transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); @@ -605,8 +603,6 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice:: i2cTransfer.flags = I2C_FLAG_READ; i2cTransfer.buf[0].data = palI2c->ReadBuffer; i2cTransfer.buf[0].len = palI2c->ReadSize; - i2cTransfer.buf[1].data = NULL; - i2cTransfer.buf[1].len = 0; // Perform the transfer and return status from the transfer transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); From d7b3fc0185ad9445c86f5c776ae75f4fdd41044d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Jun 2022 01:55:13 +0100 Subject: [PATCH 054/572] Improve HAL init and uninit to deal with I2C peripherals --- .../SL_STK3701A/nanoCLR/targetHAL.cpp | 286 ------------------ .../SiliconLabs/_nanoCLR/targetHAL.cpp | 284 +++++++++-------- 2 files changed, 139 insertions(+), 431 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp deleted file mode 100644 index 55024d32d5..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/targetHAL.cpp +++ /dev/null @@ -1,286 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include -#include -#include -#include -#include -#include -#include - -// #if (HAL_USE_CAN == TRUE) -// #include -// #endif -// #if (HAL_USE_I2C == TRUE) -// #include -// #endif -// #if (HAL_USE_SPI == TRUE) -// #include -// #endif -// #if (HAL_USE_UART == TRUE) -// #include -// #endif - -// global mutex protecting the internal state of the interpreter, including event flags -// mutex_t interpreterGlobalMutex; - -// because nanoHAL_Initialize/Uninitialize needs to be called in both C and C++ we need a proxy to allow it to be called -// in 'C' -extern "C" -{ - - void nanoHAL_Initialize_C() - { - nanoHAL_Initialize(); - } - - void nanoHAL_Uninitialize_C() - { - nanoHAL_Uninitialize(); - } -} - -void nanoHAL_Initialize() -{ - // initialize global mutex - // chMtxObjectInit(&interpreterGlobalMutex); - - HAL_CONTINUATION::InitializeList(); - HAL_COMPLETION ::InitializeList(); - - BlockStorageList_Initialize(); - - // initialize block storage devices - BlockStorage_AddDevices(); - - BlockStorageList_InitializeDevices(); - - // clear managed heap region - unsigned char *heapStart = NULL; - unsigned int heapSize = 0; - - ::HeapLocation(heapStart, heapSize); - memset(heapStart, 0, heapSize); - -#if (NANOCLR_GRAPHICS == TRUE) - g_GraphicsMemoryHeap.Initialize(); -#endif - - ConfigurationManager_Initialize(); - - Events_Initialize(); - - CPU_GPIO_Initialize(); - -// #if (HAL_USE_CAN == TRUE) - -// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) -// Can1_PAL.Driver = NULL; -// #endif -// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) -// Can2_PAL.Driver = NULL; -// #endif -// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) -// Can3_PAL.Driver = NULL; -// #endif - -// #endif - -// #if (HAL_USE_I2C == TRUE) - -// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) -// I2C1_PAL.Driver = NULL; -// #endif -// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) -// I2C2_PAL.Driver = NULL; -// #endif -// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) -// I2C3_PAL.Driver = NULL; -// #endif -// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) -// I2C4_PAL.Driver = NULL; -// #endif - -// #endif - -// #if (HAL_USE_SPI == TRUE) -// nanoSPI_Initialize(); -// #endif - -// #if (HAL_USE_UART == TRUE) - -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) -// Uart1_PAL.UartDriver = NULL; -// Uart1_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) -// Uart2_PAL.UartDriver = NULL; -// Uart2_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) -// Uart3_PAL.UartDriver = NULL; -// Uart3_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) -// Uart4_PAL.UartDriver = NULL; -// Uart4_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) -// Uart5_PAL.UartDriver = NULL; -// Uart5_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) -// Uart6_PAL.UartDriver = NULL; -// Uart6_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) -// Uart7_PAL.UartDriver = NULL; -// Uart7_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) -// Uart8_PAL.UartDriver = NULL; -// Uart8_PAL__.UartDriver = NULL; -// #endif - -// #endif - -#if (NANOCLR_GRAPHICS == TRUE) - DisplayInterfaceConfig config; // not used for DSI display - g_DisplayInterface.Initialize(config); - g_DisplayDriver.Initialize(); - - // g_TouchInterface.Initialize(); - // g_TouchDevice.Initialize(); - - // PalEvent_Initialize(); - // Gesture_Initialize(); - // Ink_Initialize(); -#endif - - // Initialise Network Stack - Network_Initialize(); -} - -void nanoHAL_Uninitialize() -{ - // release the global mutex, just in case it's locked somewhere - // chMtxUnlock(&interpreterGlobalMutex); - - // TODO check for s_rebootHandlers - // for(int i = 0; i< ARRAYSIZE(s_rebootHandlers); i++) - // { - // if(s_rebootHandlers[i] != NULL) - // { - // s_rebootHandlers[i](); - // } - // else - // { - // break; - // } - // } - - // TODO - SOCKETS_CloseConnections(); - -#if !defined(HAL_REDUCESIZE) - // TODO need to call this but it's preventing the debug session from starting - Network_Uninitialize(); -#endif - - BlockStorageList_UnInitializeDevices(); - - // need to be sure that: - // - all mutexes for drivers that use them are released - // - all drivers are stopped - -// #if (HAL_USE_SPI == TRUE) -// nanoSPI_Uninitialize(); -// #endif - -// #if (HAL_USE_CAN == TRUE) - -// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) -// canStop(&CAND1); -// #endif -// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) -// canStop(&CAND2); -// #endif -// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) -// canStop(&CAND3); -// #endif - -// #endif - -// #if (HAL_USE_I2C == TRUE) - -// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) -// i2cReleaseBus(&I2CD1); -// i2cStop(&I2CD1); -// #endif -// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) -// i2cReleaseBus(&I2CD2); -// i2cStop(&I2CD2); -// #endif -// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) -// i2cReleaseBus(&I2CD3); -// i2cStop(&I2CD3); -// #endif -// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) -// i2cReleaseBus(&I2CD4); -// i2cStop(&I2CD4); -// #endif - -// #endif - -// #if (HAL_USE_SPI == TRUE) -// nanoSPI_Uninitialize(); -// #endif - -// #if (HAL_USE_UART == TRUE) - -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) -// uartReleaseBus(&UARTD1); -// uartStop(&UARTD1); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) -// uartReleaseBus(&UARTD2); -// uartStop(&UARTD2); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) -// uartReleaseBus(&UARTD3); -// uartStop(&UARTD3); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) -// uartReleaseBus(&UARTD4); -// uartStop(&UARTD4); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) -// uartReleaseBus(&UARTD5); -// uartStop(&UARTD5); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) -// uartReleaseBus(&UARTD6); -// uartStop(&UARTD6); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) -// uartReleaseBus(&UARTD7); -// uartStop(&UARTD7); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) -// uartReleaseBus(&UARTD8); -// uartStop(&UARTD8); -// #endif - -// #endif - - CPU_GPIO_Uninitialize(); - - Events_Uninitialize(); - - HAL_CONTINUATION::Uninitialize(); - HAL_COMPLETION ::Uninitialize(); -} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 55024d32d5..b447fdfccd 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -15,9 +15,6 @@ // #if (HAL_USE_CAN == TRUE) // #include // #endif -// #if (HAL_USE_I2C == TRUE) -// #include -// #endif // #if (HAL_USE_SPI == TRUE) // #include // #endif @@ -76,77 +73,70 @@ void nanoHAL_Initialize() CPU_GPIO_Initialize(); -// #if (HAL_USE_CAN == TRUE) - -// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) -// Can1_PAL.Driver = NULL; -// #endif -// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) -// Can2_PAL.Driver = NULL; -// #endif -// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) -// Can3_PAL.Driver = NULL; -// #endif - -// #endif - -// #if (HAL_USE_I2C == TRUE) + // #if (HAL_USE_CAN == TRUE) -// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) -// I2C1_PAL.Driver = NULL; -// #endif -// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) -// I2C2_PAL.Driver = NULL; -// #endif -// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) -// I2C3_PAL.Driver = NULL; -// #endif -// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) -// I2C4_PAL.Driver = NULL; -// #endif + // #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) + // Can1_PAL.Driver = NULL; + // #endif + // #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) + // Can2_PAL.Driver = NULL; + // #endif + // #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) + // Can3_PAL.Driver = NULL; + // #endif -// #endif + // #endif -// #if (HAL_USE_SPI == TRUE) -// nanoSPI_Initialize(); -// #endif - -// #if (HAL_USE_UART == TRUE) - -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) -// Uart1_PAL.UartDriver = NULL; -// Uart1_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) -// Uart2_PAL.UartDriver = NULL; -// Uart2_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) -// Uart3_PAL.UartDriver = NULL; -// Uart3_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) -// Uart4_PAL.UartDriver = NULL; -// Uart4_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) -// Uart5_PAL.UartDriver = NULL; -// Uart5_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) -// Uart6_PAL.UartDriver = NULL; -// Uart6_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) -// Uart7_PAL.UartDriver = NULL; -// Uart7_PAL__.UartDriver = NULL; -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) -// Uart8_PAL.UartDriver = NULL; -// Uart8_PAL__.UartDriver = NULL; -// #endif +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + I2C0_PAL = {0}; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + I2C1_PAL = {0}; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + I2C1_PAL = {0}; +#endif -// #endif + // #if (HAL_USE_SPI == TRUE) + // nanoSPI_Initialize(); + // #endif + + // #if (HAL_USE_UART == TRUE) + + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) + // Uart1_PAL.UartDriver = NULL; + // Uart1_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) + // Uart2_PAL.UartDriver = NULL; + // Uart2_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) + // Uart3_PAL.UartDriver = NULL; + // Uart3_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) + // Uart4_PAL.UartDriver = NULL; + // Uart4_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) + // Uart5_PAL.UartDriver = NULL; + // Uart5_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) + // Uart6_PAL.UartDriver = NULL; + // Uart6_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) + // Uart7_PAL.UartDriver = NULL; + // Uart7_PAL__.UartDriver = NULL; + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) + // Uart8_PAL.UartDriver = NULL; + // Uart8_PAL__.UartDriver = NULL; + // #endif + + // #endif #if (NANOCLR_GRAPHICS == TRUE) DisplayInterfaceConfig config; // not used for DSI display @@ -184,7 +174,7 @@ void nanoHAL_Uninitialize() // } // TODO - SOCKETS_CloseConnections(); + SOCKETS_CloseConnections(); #if !defined(HAL_REDUCESIZE) // TODO need to call this but it's preventing the debug session from starting @@ -197,85 +187,89 @@ void nanoHAL_Uninitialize() // - all mutexes for drivers that use them are released // - all drivers are stopped -// #if (HAL_USE_SPI == TRUE) -// nanoSPI_Uninitialize(); -// #endif + // #if (HAL_USE_SPI == TRUE) + // nanoSPI_Uninitialize(); + // #endif -// #if (HAL_USE_CAN == TRUE) + // #if (HAL_USE_CAN == TRUE) -// #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) -// canStop(&CAND1); -// #endif -// #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) -// canStop(&CAND2); -// #endif -// #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) -// canStop(&CAND3); -// #endif - -// #endif - -// #if (HAL_USE_I2C == TRUE) + // #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) + // canStop(&CAND1); + // #endif + // #if (STM32_CAN_USE_CAN2) && (STM32_CAN_USE_CAN2 == TRUE) + // canStop(&CAND2); + // #endif + // #if (STM32_CAN_USE_CAN3) && (STM32_CAN_USE_CAN3 == TRUE) + // canStop(&CAND3); + // #endif -// #if defined(STM32_I2C_USE_I2C1) && (STM32_I2C_USE_I2C1 == TRUE) -// i2cReleaseBus(&I2CD1); -// i2cStop(&I2CD1); -// #endif -// #if defined(STM32_I2C_USE_I2C2) && (STM32_I2C_USE_I2C2 == TRUE) -// i2cReleaseBus(&I2CD2); -// i2cStop(&I2CD2); -// #endif -// #if defined(STM32_I2C_USE_I2C3) && (STM32_I2C_USE_I2C3 == TRUE) -// i2cReleaseBus(&I2CD3); -// i2cStop(&I2CD3); -// #endif -// #if defined(STM32_I2C_USE_I2C4) && (STM32_I2C_USE_I2C4 == TRUE) -// i2cReleaseBus(&I2CD4); -// i2cStop(&I2CD4); -// #endif + // #endif -// #endif - -// #if (HAL_USE_SPI == TRUE) -// nanoSPI_Uninitialize(); -// #endif - -// #if (HAL_USE_UART == TRUE) - -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) -// uartReleaseBus(&UARTD1); -// uartStop(&UARTD1); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) -// uartReleaseBus(&UARTD2); -// uartStop(&UARTD2); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) -// uartReleaseBus(&UARTD3); -// uartStop(&UARTD3); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) -// uartReleaseBus(&UARTD4); -// uartStop(&UARTD4); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) -// uartReleaseBus(&UARTD5); -// uartStop(&UARTD5); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) -// uartReleaseBus(&UARTD6); -// uartStop(&UARTD6); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) -// uartReleaseBus(&UARTD7); -// uartStop(&UARTD7); -// #endif -// #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) -// uartReleaseBus(&UARTD8); -// uartStop(&UARTD8); -// #endif +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + if (I2C0_PAL.Configuration != NULL) + { + platform_free(I2C0_PAL.Configuration); + I2C0_PAL.Configuration = NULL; + } + I2C_Reset(I2C0); +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + if (I2C1_PAL.Configuration != NULL) + { + platform_free(I2C1_PAL.Configuration); + I2C1_PAL.Configuration = NULL; + } + I2C_Reset(I2C1); +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + if (I2C2_PAL.Configuration != NULL) + { + platform_free(I2C2_PAL.Configuration); + I2C2_PAL.Configuration = NULL; + } + I2C_Reset(I2C2); +#endif -// #endif + // #if (HAL_USE_SPI == TRUE) + // nanoSPI_Uninitialize(); + // #endif + + // #if (HAL_USE_UART == TRUE) + + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) + // uartReleaseBus(&UARTD1); + // uartStop(&UARTD1); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART2) && (NF_SERIAL_COMM_STM32_UART_USE_USART2 == TRUE) + // uartReleaseBus(&UARTD2); + // uartStop(&UARTD2); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART3) && (NF_SERIAL_COMM_STM32_UART_USE_USART3 == TRUE) + // uartReleaseBus(&UARTD3); + // uartStop(&UARTD3); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART4) && (NF_SERIAL_COMM_STM32_UART_USE_UART4 == TRUE) + // uartReleaseBus(&UARTD4); + // uartStop(&UARTD4); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART5) && (NF_SERIAL_COMM_STM32_UART_USE_UART5 == TRUE) + // uartReleaseBus(&UARTD5); + // uartStop(&UARTD5); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART6) && (NF_SERIAL_COMM_STM32_UART_USE_USART6 == TRUE) + // uartReleaseBus(&UARTD6); + // uartStop(&UARTD6); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART7) && (NF_SERIAL_COMM_STM32_UART_USE_UART7 == TRUE) + // uartReleaseBus(&UARTD7); + // uartStop(&UARTD7); + // #endif + // #if defined(NF_SERIAL_COMM_STM32_UART_USE_UART8) && (NF_SERIAL_COMM_STM32_UART_USE_UART8 == TRUE) + // uartReleaseBus(&UARTD8); + // uartStop(&UARTD8); + // #endif + + // #endif CPU_GPIO_Uninitialize(); From 81ba8e39dbc7290b11266b422e1e0f9812efc1c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Jun 2022 02:32:29 +0100 Subject: [PATCH 055/572] Replace official I2CSPM with nano version - Requited to perform a wait with gadelho --- CMake/Modules/FindGecko_SDK.cmake | 8 +- .../System.Device.I2c/nano_sl_i2cspm.c | 158 ++++++++++++++++++ 2 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/nano_sl_i2cspm.c diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index ae96d3961f..5f848fb3d8 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -98,10 +98,13 @@ set(gecko_sdk_srcs sl_event_handler.c sl_board_default_init_stub.c sl_i2cspm_init.c - sl_i2cspm.c + # sl_i2cspm.c sl_iostream_handles.c sl_iostream_init_usart_instances.c + # nanoFramework implementations + nano_sl_i2cspm.c + # autogen at target level ) @@ -146,6 +149,9 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") ${TARGET_BASE_LOCATION}/autogen ${TARGET_BASE_LOCATION}/config + # nanoFramework implementations + ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c + CMAKE_FIND_ROOT_PATH_BOTH ) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/nano_sl_i2cspm.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/nano_sl_i2cspm.c new file mode 100644 index 0000000000..65a575de4d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/nano_sl_i2cspm.c @@ -0,0 +1,158 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include +#include "em_cmu.h" +#include "em_gpio.h" +#include "sl_assert.h" +#include "sl_i2cspm.h" +#include "sl_udelay.h" + +#include + +/* transfer timeout (how many polls) */ +#ifndef I2CSPM_TRANSFER_TIMEOUT +#define I2CSPM_TRANSFER_TIMEOUT 300 +#endif + +/* SCL hold time (in initialization function) in microseconds */ +#ifndef SL_I2CSPM_SCL_HOLD_TIME_US +#define SL_I2CSPM_SCL_HOLD_TIME_US 100 +#endif + +/******************************************************************************* + * Initalize I2C peripheral + ******************************************************************************/ +void I2CSPM_Init(I2CSPM_Init_TypeDef *init) +{ + int i; + CMU_Clock_TypeDef i2cClock; + I2C_Init_TypeDef i2cInit; + + EFM_ASSERT(init != NULL); + +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + + /* Select I2C peripheral clock */ + if (false) + { +#if defined(I2C0) + } + else if (init->port == I2C0) + { + i2cClock = cmuClock_I2C0; +#endif +#if defined(I2C1) + } + else if (init->port == I2C1) + { + i2cClock = cmuClock_I2C1; +#endif +#if defined(I2C2) + } + else if (init->port == I2C2) + { + i2cClock = cmuClock_I2C2; +#endif + } + else + { + /* I2C clock is not defined */ + EFM_ASSERT(false); + return; + } + CMU_ClockEnable(i2cClock, true); + + /* Output value must be set to 1 to not drive lines low. Set + SCL first, to ensure it is high before changing SDA. */ + GPIO_PinModeSet(init->sclPort, init->sclPin, gpioModeWiredAndPullUp, 1); + GPIO_PinModeSet(init->sdaPort, init->sdaPin, gpioModeWiredAndPullUp, 1); + + /* In some situations, after a reset during an I2C transfer, the slave + device may be left in an unknown state. Send 9 clock pulses to + set slave in a defined state. */ + for (i = 0; i < 9; i++) + { + GPIO_PinOutClear(init->sclPort, init->sclPin); + sl_udelay_wait(SL_I2CSPM_SCL_HOLD_TIME_US); + GPIO_PinOutSet(init->sclPort, init->sclPin); + sl_udelay_wait(SL_I2CSPM_SCL_HOLD_TIME_US); + } + + /* Enable pins and set location */ +#if defined(_I2C_ROUTEPEN_MASK) + init->port->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN; + init->port->ROUTELOC0 = + (uint32_t)((init->portLocationSda << _I2C_ROUTELOC0_SDALOC_SHIFT) | (init->portLocationScl << _I2C_ROUTELOC0_SCLLOC_SHIFT)); +#elif defined(_I2C_ROUTE_MASK) + init->port->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (init->portLocation << _I2C_ROUTE_LOCATION_SHIFT); +#else +#if defined(I2C0) + if (init->port == I2C0) + { + GPIO->I2CROUTE[0].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[0].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[0].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#if defined(I2C1) + if (init->port == I2C1) + { + GPIO->I2CROUTE[1].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[1].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[1].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#if defined(I2C2) + if (init->port == I2C2) + { + GPIO->I2CROUTE[2].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[2].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[2].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#endif + + /* Set emlib init parameters */ + i2cInit.enable = true; + i2cInit.master = true; /* master mode only */ + i2cInit.freq = init->i2cMaxFreq; + i2cInit.refFreq = init->i2cRefFreq; + i2cInit.clhr = init->i2cClhr; + + I2C_Init(init->port, &i2cInit); +} + +/******************************************************************************* + * Perform I2C transfer + ******************************************************************************/ +I2C_TransferReturn_TypeDef I2CSPM_Transfer(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq) +{ + I2C_TransferReturn_TypeDef ret; + uint32_t timeout = I2CSPM_TRANSFER_TIMEOUT; + + // Do a polled transfer + ret = I2C_TransferInit(i2c, seq); + + while (ret == i2cTransferInProgress && timeout--) + { + + ret = I2C_Transfer(i2c); + + // allow other tasks to run + tx_thread_sleep(10); + } + + return ret; +} From 0b7701656010cb05c572a157c2b19d0640f995e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Jun 2022 02:44:31 +0100 Subject: [PATCH 056/572] Simplification of CLR init --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index a44296c778..c5d17b0d25 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -153,10 +153,6 @@ void tx_application_define(void *first_unused_memory) // Application entry point. int main(void) { - // Initialize the board - sl_board_preinit(); - sl_board_init(); - sl_driver_init(); sl_service_init(); sl_stack_init(); sl_internal_app_init(); From f27dbaabb80aef79a4b7e2df3b7acd831e682821 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Jun 2022 02:56:01 +0100 Subject: [PATCH 057/572] Fix call to Gecko GPIO API - Now using correct API. --- .../SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp index aa279c4905..2b514da54b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp @@ -384,11 +384,11 @@ void CPU_GPIO_SetPinState(GPIO_PIN pin, GpioPinValue pinState) if (pinState == GpioPinValue_High) { - GPIO_PortOutSet(port, portPin); + GPIO_PinOutSet(port, portPin); } else { - GPIO_PortOutClear(port, portPin); + GPIO_PinOutClear(port, portPin); } } @@ -398,7 +398,7 @@ void CPU_GPIO_TogglePinState(GPIO_PIN pin) uint32_t portPin; GetIoLine(pin, &port, &portPin); - GPIO_PortOutToggle(port, portPin); + GPIO_PinOutToggle(port, portPin); } bool CPU_GPIO_EnableInputPin( From ac1b0fe7c74f299921b405562fe29097a2835ca1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 15 Jun 2022 10:16:04 +0100 Subject: [PATCH 058/572] Adjust CRT stack and heap --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 7067cb3b9e..fe2a73a685 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -33,8 +33,8 @@ nf_setup_target_build( SL_BOARD_REV=\"A02\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - SL_STACK_SIZE=0x4000 - SL_HEAP_SIZE=0x4000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -42,8 +42,8 @@ nf_setup_target_build( SL_BOARD_REV=\"A02\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 - SL_STACK_SIZE=0x4000 - SL_HEAP_SIZE=0x4000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From 7b023b36e9950c4a636a2391b3dab31f9af2b2f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 15 Jun 2022 10:16:23 +0100 Subject: [PATCH 059/572] Improve flash script for GG11 --- .jlink/flash_gg11.jlink | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.jlink/flash_gg11.jlink b/.jlink/flash_gg11.jlink index 03a12a7dd7..cc3418b21f 100644 --- a/.jlink/flash_gg11.jlink +++ b/.jlink/flash_gg11.jlink @@ -1,3 +1,5 @@ speed auto +Halt LoadFile nanobooter-nanoclr.bin,0 +Reset Exit \ No newline at end of file From 7926d252cffb2d846f925333c1afcca07788b88d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 15 Jun 2022 14:46:35 +0100 Subject: [PATCH 060/572] Improvements in I2C - Add define to set transaction timeout. - Replace i2cspm back to SDK official code. --- CMake/Modules/FindGecko_SDK.cmake | 5 +++-- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 5f848fb3d8..fa473466de 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -98,12 +98,13 @@ set(gecko_sdk_srcs sl_event_handler.c sl_board_default_init_stub.c sl_i2cspm_init.c - # sl_i2cspm.c + # candidate for replacement with RTOS friendly version + sl_i2cspm.c sl_iostream_handles.c sl_iostream_init_usart_instances.c # nanoFramework implementations - nano_sl_i2cspm.c + # nano_sl_i2cspm.c # autogen at target level ) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index fe2a73a685..754794ef45 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -33,6 +33,7 @@ nf_setup_target_build( SL_BOARD_REV=\"A02\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 + I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 @@ -42,6 +43,7 @@ nf_setup_target_build( SL_BOARD_REV=\"A02\" SL_COMPONENT_CATALOG_PRESENT=1 _SILICON_LABS_32B_SERIES_2_CONFIG=0 + I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 From 9b6110db66a461cd86b7ba8b4ca96f521a8b3581 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Jun 2022 18:51:05 +0100 Subject: [PATCH 061/572] Fix default initialization of I2C config --- ...v_i2c_native_System_Device_I2c_I2cDevice.cpp | 17 ++++++++++++++++- .../sys_dev_i2c_native_target.h | 1 - 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp index 80c16fa267..cf4ea3efd6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -127,7 +127,22 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOI NF_PAL_I2C *palI2c = NULL; CLR_RT_HeapBlock *connectionSettings; uint8_t busIndex; - I2CSPM_Init_TypeDef i2cInit = I2CSPM_INIT_DEFAULT; + I2CSPM_Init_TypeDef i2cInit = { + NULL, + 0, + 0, + 0, + 0, +#if defined(_SILICON_LABS_32B_SERIES_0) + 0, +#elif defined(_SILICON_LABS_32B_SERIES_1) + 0, + 0, +#endif + 0, + I2C_FREQ_STANDARD_MAX, + i2cClockHLRStandard, + }; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h index ea061edc53..01989f1fe3 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_target.h @@ -8,7 +8,6 @@ #include #include -#include #include #include From 6d4fe3edac08a4995bd1f849f7ff7506c6d33900 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 1 Jul 2022 16:32:49 +0100 Subject: [PATCH 062/572] Initial work on SPI for Gecko SDK - Add drivers and target config file. --- CMakePresets.json | 2 +- .../target_system_device_spi_config.cpp | 48 + .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 841 ++++++++++++++++++ .../sys_dev_spi_native_target.h | 78 ++ 4 files changed, 968 insertions(+), 1 deletion(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h diff --git a/CMakePresets.json b/CMakePresets.json index ade239bef3..21a858e9ca 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -292,7 +292,7 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "OFF", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "OFF", + "API_System.Device.Spi": "ON", "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..4ebd4a5ab9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI1 // +////////// + +// Note on ST_B_L457EIOT01A SPI1 connects to CN1 ARDUINO connector + +// pin configuration for SPI1 on GPIOA AF5 +// port for SPI1_SCK is: GPIOA_5 : ARD.D13-SPI1_SCK/LED1 pin CN1_6 +// port for SPI1_MISO is: GPIOA_6 : ARD.D12-SPI1_MISO pin CN1_5 +// port for SPI1_MOSI is: GPIOA_7 : ARD.D11-SPI1_MOSI/PWM pin CN1_4 + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(1, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) + +////////// +// SPI2 // +////////// + +// Note on ST_B_L457EIOT01A SPI2 connects to PMOD port (with defaault solder jumper settings) + +// pin configuration for SPI2 on GPIOD AF5 +// port for SPI2_SCK is: GPIOD_1 PMOD-SPI2_SCK +// port for SPI2_MISO is: GPIOD_3 PMOD-UART2_CTS/SPI2_MISO +// port for SPI2_MOSI is: GPIOD_4 PMOD-UART2_RTS/SPI2_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(2, GPIOD, 1, GPIOD, 3, GPIOD, 4, 5) + +////////// +// SPI3 // +////////// + +// Note on ST_B_L457EIOT01A SPI3 connects to Bluetooth SPBTLE-RF module + +// pin configuration for SPI3 on GPIOD AF5 +// port for SPI3_SCK is: GPIOD_10 INTERNAL-SPI3_SCK +// port for SPI3_MISO is: GPIOD_11 INTERNAL-SPI3_MISO +// port for SPI3_MOSI is: GPIOD_12 INTERNAL-SPI3_MOSI + +// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) +SPI_CONFIG_PINS(3, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp new file mode 100644 index 0000000000..ded08e9f55 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -0,0 +1,841 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +///////////////////////////////////////////////////// +// SPI PAL strucs declared in win_dev_spi_native.h // +///////////////////////////////////////////////////// +#if STM32_SPI_USE_SPI1 +NF_PAL_SPI SPI1_PAL; +#endif +#if STM32_SPI_USE_SPI2 +NF_PAL_SPI SPI2_PAL; +#endif +#if STM32_SPI_USE_SPI3 +NF_PAL_SPI SPI3_PAL; +#endif +#if STM32_SPI_USE_SPI4 +NF_PAL_SPI SPI4_PAL; +#endif +#if STM32_SPI_USE_SPI5 +NF_PAL_SPI SPI5_PAL; +#endif +#if STM32_SPI_USE_SPI6 +NF_PAL_SPI SPI6_PAL; +#endif + +// Tidy up after completing tranfer +static void CompleteTranfer(NF_PAL_SPI *palSpi) +{ + // just to satisfy the driver ceremony, no actual implementation for STM32 + spiUnselect(palSpi->Driver); + + // Release the bus + spiReleaseBus(palSpi->Driver); + + // event occurred + if (palSpi->ReadSize > 0) + { + // because this was a Read transaction, need to copy from DMA buffer to managed buffer + int ReadSize = palSpi->ReadSize; + + // Adjust read size for data width of 16bits + if (palSpi->BufferIs16bits) + ReadSize *= 2; + + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + // get the pointer to the read buffer as UINT16 because it's really an UINT16 (2 bytes) + cacheBufferInvalidate(palSpi->ReadBuffer, (palSpi->ReadSize * 2)); + } +} + +// Callback used when a async opertion completes +static void SpiCallback(SPIDriver *spip) +{ + (void)spip; + + NATIVE_INTERRUPT_START + + NF_PAL_SPI *palSpi = NULL; + + // Find the NF_PAL_SPI * for driver +#if STM32_SPI_USE_SPI1 + if (spip == &SPID1) + { + palSpi = &SPI1_PAL; + } +#endif +#if STM32_SPI_USE_SPI2 + if (spip == &SPID2) + { + palSpi = &SPI2_PAL; + } +#endif +#if STM32_SPI_USE_SPI3 + if (spip == &SPID3) + { + palSpi = &SPI3_PAL; + } +#endif +#if STM32_SPI_USE_SPI4 + if (spip == &SPID4) + { + palSpi = &SPI4_PAL; + } +#endif +#if STM32_SPI_USE_SPI5 + if (spip == &SPID5) + { + palSpi = &SPI5_PAL; + } +#endif +#if STM32_SPI_USE_SPI6 + if (spip == &SPID6) + { + palSpi = &SPI6_PAL; + } +#endif + + // check if there is any Rx operation due + if (palSpi->SequentialTxRx) + { + // yes there is! + // clear flag and... + palSpi->SequentialTxRx = false; + + // ... start it + if (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex) + { + // half duplex operation, clear output enable bit + palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + } + spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + else + { + // all done here! + + // Tidy up, release etc + CompleteTranfer(palSpi); + + // fire callback for SPI transaction complete + // only if callback set + if (palSpi->Callback) + palSpi->Callback(palSpi->BusIndex); + } + + NATIVE_INTERRUPT_END +}; + +// Computes the SPI peripheral baud rate according to the requested frequency +uint16_t ComputeBaudRate(SPI_DEVICE_CONFIGURATION &config, int32_t &actualFrequency) +{ + uint16_t divider = 0; + int32_t maxSpiFrequency; + int32_t requestedFrequency = config.Clock_RateHz; + int busIndex = config.Spi_Bus; + +#if defined(STM32L0XX) + + // SP1 is feed by APB2 (STM32_PCLK2) + actualFrequency = STM32_PCLK2; + + // SPI2 is feed by APB1 (STM32_PCLK1) + if (busIndex == 1) + { + actualFrequency = STM32_PCLK1; + } + + // from datasheet + maxSpiFrequency = 12000000; + +#elif defined(STM32F0XX) + + (void)busIndex; + + // STM32F0 SPI is always feed by APB1 + actualFrequency = STM32_PCLK1; + + // from datasheet + maxSpiFrequency = 18000000; + +#elif defined(STM32F4XX) || defined(STM32F7XX) + + // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2) + actualFrequency = STM32_PCLK2; + + // SPI2 and SPI3 are feed by APB1 (STM32_PCLK1) + if (busIndex == 2 || busIndex == 3) + { + actualFrequency = STM32_PCLK1; + } + + // this is not really accurate because there are different max SPI clocks depending on which APB clock source if + // feeding the SPI because ChibiOS doesn't offer that we have to go with minimum common denominator + maxSpiFrequency = STM32_SPII2S_MAX; + +#elif defined(STM32H7XX) + + // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2) + actualFrequency = STM32_PCLK2; + maxSpiFrequency = STM32_SPI456_MAX; + + // SPI1, SPI2 and SPI3 are feed by APB1 (STM32_PCLK1) + if (busIndex == 2 || busIndex == 3) + { + actualFrequency = STM32_PCLK1; + maxSpiFrequency = STM32_SPI123_MAX; + } + +#else + +#error "Error setting max SPI frequency. Check if the target series is defined." + +#endif + + // when requested frequency is 0, means that the developer hasn't set ClockFrequency in SpiConnectionSettings + // default to the max possible SPI frequency + if (requestedFrequency == 0) + { + requestedFrequency = maxSpiFrequency; + } + + for (; divider < 8; divider++) + { + actualFrequency = actualFrequency / 2; + + if (actualFrequency <= requestedFrequency) + { + // best match for the requested frequency + // just check if it's below the max SPI frequency + if (actualFrequency <= maxSpiFrequency) + { + // we are good with this value + break; + } + } + } + + // the baud rate bits are in the position B5:3 so need to left shit the divider value + return divider << 3; +} + +// Return the NF_PAL structure for busIndex +// Return NULL is invalid bus +NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) +{ + NF_PAL_SPI *palSpi = NULL; + + // get the PAL struct for the SPI bus + switch (busIndex) + { +#if STM32_SPI_USE_SPI1 + case 1: + palSpi = &SPI1_PAL; + break; +#endif +#if STM32_SPI_USE_SPI2 + case 2: + palSpi = &SPI2_PAL; + break; +#endif +#if STM32_SPI_USE_SPI3 + case 3: + palSpi = &SPI3_PAL; + break; +#endif +#if STM32_SPI_USE_SPI4 + case 4: + palSpi = &SPI4_PAL; + break; +#endif +#if STM32_SPI_USE_SPI5 + case 5: + palSpi = &SPI5_PAL; + break; +#endif +#if STM32_SPI_USE_SPI6 + case 6: + palSpi = &SPI6_PAL; + break; +#endif + default: + // the requested SPI bus is not valid + break; + } + + return palSpi; +} + +// Give a complete low-level SPI configuration from passed SPI_DEVICE_CONFIGURATION +void GetSPIConfig(SPI_DEVICE_CONFIGURATION &config, SPI_WRITE_READ_SETTINGS &wrc, SPIConfig *llConfig) +{ + int32_t actualFrequency; + + // clear values + llConfig->cr1 = 0; + llConfig->cr2 = 0; + + // get chip select pin + int csPin = config.DeviceChipSelect; + + // SPI mode + switch (config.Spi_Mode) + { + case SpiMode_Mode1: + llConfig->cr1 |= SPI_CR1_CPHA; + break; + + case SpiMode_Mode2: + llConfig->cr1 |= SPI_CR1_CPOL; + break; + + case SpiMode_Mode3: + llConfig->cr1 |= SPI_CR1_CPHA | SPI_CR1_CPOL; + break; + + default: // Default to Mode0 if invalid mode specified + break; + } + + // compute baud rate of SPI peripheral according to the requested frequency + llConfig->cr1 |= ComputeBaudRate(config, actualFrequency); + + // set data transfer length according passed setting + if (wrc.Bits16ReadWrite) + { + // Set data transfer length to 16 bits +#ifdef STM32F4XX + llConfig->cr1 |= SPI_CR1_DFF; +#endif +#ifdef STM32F7XX + llConfig->cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; +#endif + // Sets the order of bytes transmission : MSB first or LSB first + int bitOrder = config.DataOrder16; + if (bitOrder == DataBitOrder_LSB) + { + llConfig->cr1 |= SPI_CR1_LSBFIRST; + } + } + else + { + // set transfer length to 8bits +#ifdef STM32F4XX + llConfig->cr1 &= ~SPI_CR1_DFF; +#endif +#ifdef STM32F7XX + llConfig->cr2 |= SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; +#endif + } + + // set bus configuration + // only required for half duplex mode + if (config.BusConfiguration == SpiBusConfiguration_HalfDuplex) + { +#ifdef STM32F4XX + llConfig->cr1 |= SPI_CR1_BIDIMODE; +#endif +#ifdef STM32F7XX + llConfig->cr2 |= SPI_CR1_BIDIMODE; +#endif + } + + // Create the low level configuration + llConfig->data_cb = SpiCallback; + + // make sure the CS pin is properly configured as GPIO, output & pushpull + palSetPadMode(GPIO_PORT(csPin), csPin % 16, (PAL_STM32_OSPEED_HIGHEST | PAL_MODE_OUTPUT_PUSHPULL)); + + // being SPI CS active low, default it to high + palSetPad(GPIO_PORT(csPin), csPin % 16); + + // set port&pad for CS pin + llConfig->ssport = GPIO_PORT(csPin); + llConfig->sspad = csPin % 16; +} + +// Performs a read/write operation on 8-bit word data. +// +// Parameters +// deviceHandle +// Device handle from add_device +// sdev +// reference to SPI_DEVICE_CONFIGURATION +// wrc +// reference to SPI_WRITE_READ_SETTINGS +// writeData +// A pointer to the buffer from which the data is to be written to the device. +// writeSize +// The number of elements(8 or 16) to be written. +// readData +// A pointer to the buffer into which the data is to be read from the device. +// readSize +// The number of elements(8 or 16) to be read. +// +// return S_OK=Successful, Async started=CLR_BUSY, Error=CLR_E_OUT_OF_MEMORY, CLR_E_INVALID_PARAMETER, CLR_E_FAIL +// +HRESULT CPU_SPI_nWrite_nRead( + uint32_t deviceHandle, + SPI_DEVICE_CONFIGURATION &sdev, + SPI_WRITE_READ_SETTINGS &wrc, + uint8_t *writeBuffer, + int32_t writeSize, + uint8_t *readBuffer, + int32_t readSize) +{ + NANOCLR_HEADER(); + { + bool busConfigIsHalfDuplex; + NF_PAL_SPI *palSpi = (NF_PAL_SPI *)deviceHandle; + bool sync = (wrc.callback == 0); // If callback then use aync operation + + // Save width of transfer + palSpi->BufferIs16bits = wrc.Bits16ReadWrite; + + // Callback sync / async + palSpi->Callback = wrc.callback; + + if (writeBuffer != NULL) + { + palSpi->WriteSize = writeSize; + } + + if (readBuffer != NULL) + { + palSpi->ReadSize = readSize; + } + + // === Setup the operation and init buffers === + palSpi->BusIndex = sdev.Spi_Bus; + + // get the LL SPI configuration, depending on passed parameters and buffer element size + GetSPIConfig(sdev, wrc, &palSpi->Configuration); + + // set bus config flag + busConfigIsHalfDuplex = palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex; + + // Clear callback if sync + if (sync) + { + palSpi->Configuration.data_cb = NULL; + } + + if (writeBuffer != NULL) + { + // set the pointer to the write buffer as BYTE + palSpi->WriteBuffer = (uint8_t *)writeBuffer; + + // set DMA write buffer + if (palSpi->BufferIs16bits) + { + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(palSpi->WriteBuffer, (palSpi->WriteSize * 2)); + } + else + { + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(palSpi->WriteBuffer, palSpi->WriteSize); + } + } + + if (readBuffer != NULL) + { + // set DMA read buffer + if (palSpi->ReadSize > 0) + { + palSpi->ReadBuffer = (uint8_t *)readBuffer; + } + } + + // because the bus access is shared, acquire and select the appropriate bus + spiAcquireBus(palSpi->Driver); + spiStart(palSpi->Driver, &palSpi->Configuration); + + // just to satisfy the driver ceremony, no actual implementation for STM32 + spiSelect(palSpi->Driver); + + if (sync) + { + // Sync operation + // perform SPI operation using driver's SYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (wrc.fullDuplex) + { + // Full duplex + // Uses the largest buffer size as transfer size + spiExchange( + palSpi->Driver, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + palSpi->WriteBuffer, + palSpi->ReadBuffer); + } + else + { + // send operation + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + } + spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + + // receive operation + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + } + spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // receive + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + } + + spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + else + { + // send + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + } + + spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + } + } + + // Release bus & cacheBufferInvalidate etc + CompleteTranfer(palSpi); + } + else + // Start an Asyncronous SPI transfer + // perform SPI operation using driver's ASYNC API + // Completed on calling Spi Callback + { + // this is a Async operation + // perform SPI operation using driver's ASYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (wrc.fullDuplex) + { + // Full duplex + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // Uses the largest buffer size as transfer size + spiStartExchange( + palSpi->Driver, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + palSpi->WriteBuffer, + palSpi->ReadBuffer); + } + else + { + // flag that an Rx is required after the Tx operation completes + palSpi->SequentialTxRx = true; + + // start send operation + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + } + + spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // receive operation will be started in the callback after the above completes + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start receive + spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + else + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start send + spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + } + } + + // Inform caller async operation started + NANOCLR_SET_AND_LEAVE(CLR_E_BUSY); + } + } + + NANOCLR_NOCLEANUP(); +} + +SPI_OP_STATUS CPU_SPI_OP_Status(uint8_t spi_bus, uint32_t deviceHandle) +{ + (void)spi_bus; + + NF_PAL_SPI *palSpi = (NF_PAL_SPI *)deviceHandle; + SPI_OP_STATUS os; + + switch (palSpi->Driver->state) + { + default: + case SPI_UNINIT: + case SPI_STOP: + case SPI_READY: + os = SPI_OP_READY; + break; + + case SPI_ACTIVE: + os = SPI_OP_RUNNING; + break; + + case SPI_COMPLETE: + os = SPI_OP_COMPLETE; + break; + } + return os; +} + +bool CPU_SPI_Initialize(uint8_t busIndex, SpiBusConfiguration busConfiguration) +{ + // init the PAL struct for this SPI bus and assign the respective driver + // all this occurs if not already done + // why do we need this? because several SPIDevice objects can be created associated to the same bus + switch (busIndex + 1) + { +#if STM32_SPI_USE_SPI1 + case 1: + if (SPI1_PAL.Driver == NULL) + { + ConfigPins_SPI1(busConfiguration == SpiBusConfiguration_HalfDuplex); + SPI1_PAL.Driver = &SPID1; + } + break; +#endif +#if STM32_SPI_USE_SPI2 + case 2: + if (SPI2_PAL.Driver == NULL) + { + ConfigPins_SPI2(busConfiguration == SpiBusConfiguration_HalfDuplex); + SPI2_PAL.Driver = &SPID2; + } + break; +#endif +#if STM32_SPI_USE_SPI3 + case 3: + if (SPI3_PAL.Driver == NULL) + { + ConfigPins_SPI3(busConfiguration == SpiBusConfiguration_HalfDuplex); + SPI3_PAL.Driver = &SPID3; + } + break; +#endif +#if STM32_SPI_USE_SPI4 + case 4: + if (SPI4_PAL.Driver == NULL) + { + ConfigPins_SPI4(busConfiguration == SpiBusConfiguration_HalfDuplex); + SPI4_PAL.Driver = &SPID4; + } + break; +#endif +#if STM32_SPI_USE_SPI5 + case 5: + if (SPI5_PAL.Driver == NULL) + { + ConfigPins_SPI5(busConfiguration == SpiBusConfiguration_HalfDuplex); + SPI5_PAL.Driver = &SPID5; + } + break; +#endif +#if STM32_SPI_USE_SPI6 + case 6: + if (SPI6_PAL.Driver == NULL) + { + ConfigPins_SPI6(busConfiguration == SpiBusConfiguration_HalfDuplex); + SPI6_PAL.Driver = &SPID6; + } + break; +#endif + default: + // this SPI bus is not valid + return false; + } + + return true; +} + +bool CPU_SPI_Uninitialize(uint8_t busIndex) +{ + // get the PAL struct for the SPI bus + switch (busIndex + 1) + { +#if STM32_SPI_USE_SPI1 + case 1: + spiStop(&SPID1); + SPI1_PAL.Driver = NULL; + spiReleaseBus(&SPID1); + break; +#endif + +#if STM32_SPI_USE_SPI2 + case 2: + spiStop(&SPID2); + SPI2_PAL.Driver = NULL; + spiReleaseBus(&SPID2); + break; +#endif + +#if STM32_SPI_USE_SPI3 + case 3: + spiStop(&SPID3); + SPI3_PAL.Driver = NULL; + spiReleaseBus(&SPID3); + break; +#endif + +#if STM32_SPI_USE_SPI4 + case 4: + spiStop(&SPID4); + SPI4_PAL.Driver = NULL; + spiReleaseBus(&SPID4); + break; +#endif + +#if STM32_SPI_USE_SPI5 + case 5: + spiStop(&SPID5); + SPI5_PAL.Driver = NULL; + spiReleaseBus(&SPID5); + break; +#endif + +#if STM32_SPI_USE_SPI6 + case 6: + spiStop(&SPID6); + SPI6_PAL.Driver = NULL; + spiReleaseBus(&SPID6); + break; +#endif + + default: + // the requested SPI bus is not valid + return false; + } + + return true; +} + +// return Map of available SPI ports +uint32_t CPU_SPI_PortsMap() +{ + uint32_t map = 0; + +#if STM32_SPI_USE_SPI1 + map |= 0x01; +#endif +#if STM32_SPI_USE_SPI2 + map |= 0x02; +#endif +#if STM32_SPI_USE_SPI3 + map |= 0x04; +#endif +#if STM32_SPI_USE_SPI4 + map |= 0x08; +#endif +#if STM32_SPI_USE_SPI5 + map |= 0x10; +#endif +#if STM32_SPI_USE_SPI6 + map |= 0x20; +#endif + return map; +} + +// Add a device to SPi Bus (Optional) +// Returns a device handle. Returns 0 if error +HRESULT CPU_SPI_Add_Device(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, uint32_t &handle) +{ + // check supported bus configuration: all valid except simplex + if (spiDeviceConfig.BusConfiguration == SpiBusConfiguration_Simplex) + { + return CLR_E_NOT_SUPPORTED; + } + + handle = (uint32_t)GetNfPalfromBusIndex(spiDeviceConfig.Spi_Bus); + + return S_OK; +} + +// Return pins used for SPI bus +void CPU_SPI_GetPins(uint32_t spi_bus, GPIO_PIN &clk, GPIO_PIN &miso, GPIO_PIN &mosi) +{ + (void)spi_bus; + + clk = (GPIO_PIN)-1; + miso = (GPIO_PIN)-1; + mosi = (GPIO_PIN)-1; +} + +// Minimum and Maximum clock frequency available based on bus and configured pins +HRESULT CPU_SPI_MinClockFrequency(uint32_t spiBus, int32_t *frequency) +{ + if (spiBus - 1 >= NUM_SPI_BUSES) + { + return CLR_E_INVALID_PARAMETER; + } + + // Max prescaler value = 256 + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + *frequency = (spiBus == 2 or spiBus == 3) ? SystemCoreClock >>= 9 : SystemCoreClock >> 8; + + return S_OK; +} + +HRESULT CPU_SPI_MaxClockFrequency(uint32_t spiBus, int32_t *frequency) +{ + if (spiBus - 1 >= NUM_SPI_BUSES) + { + return CLR_E_INVALID_PARAMETER; + } + + // According to STM : "At a minimum, the clock frequency should be twice the required communication frequency." + // So maximum useable frequency is CoreClock / 2. + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + *frequency = (spiBus == 2 or spiBus == 3) ? SystemCoreClock >>= 2 : SystemCoreClock >> 1; + + return S_OK; +} + +// Maximum number of SPI devices that can be opened on a bus +uint32_t CPU_SPI_ChipSelectLineCount(uint32_t spi_bus) +{ + (void)spi_bus; + return 10; +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h new file mode 100644 index 0000000000..9bde0a49e0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -0,0 +1,78 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_SPI_NATIVE_TARGET_H +#define SYS_DEV_SPI_NATIVE_TARGET_H + + +// #include +// #include +// #include + + +#include + +#include +#include + +// struct representing the SPI bus +struct NF_PAL_SPI +{ + int BusIndex; + SPIDRV_Handle_t *Driver; + SPIDRV_Init_t Configuration; + // SpiBusConfiguration BusConfiguration; + + //SPI_Callback Callback; + + bool SequentialTxRx; + bool BufferIs16bits; + + uint8_t *WriteBuffer; + uint16_t WriteSize; + + uint8_t *ReadBuffer; + uint16_t ReadSize; +}; + +// the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral +// it gets called in the System_Device_SPi_SPiDevice::NativeInit function +// this is required because the SPI peripherals can use multiple GPIO configuration combinations +#define SPI_CONFIG_PINS( \ + num, \ + gpio_port_sck, \ + sck_pin, + sck_port_location, \ + gpio_port_miso, \ + miso_pin, + miso_port_location, \ + gpio_port_mosi, \ + mosi_pin, + mosi_port_location \ + ) + \ + void ConfigPins_SPI##num(bool isHalfDuplex) \ + { + SPI##num##_PAL.Configuration->sclPort = gpio_port_scl; \ + SPI##num##_PAL.Configuration->sdaPort = gpio_port_sda; \ + SPI##num##_PAL.Configuration->sclPin = scl_pin; \ + SPI##num##_PAL.Configuration->sdaPin = sda_pin; \ + SPI##num##_PAL.Configuration->portLocationScl = scl_port_location; \ + SPI##num##_PAL.Configuration->portLocationSda = sda_port_location; \ + \ + } + +////////////////////////////////////////////////////////////////////////////////////////////// +// when an SPI is defined the declarations below will have the real function/configuration // +// in the target folder @ target_windows_devices_spi_config.cpp // +////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_SPI1(bool isHalfDuplex); +void ConfigPins_SPI2(bool isHalfDuplex); +void ConfigPins_SPI3(bool isHalfDuplex); +void ConfigPins_SPI4(bool isHalfDuplex); +void ConfigPins_SPI5(bool isHalfDuplex); +void ConfigPins_SPI6(bool isHalfDuplex); + +#endif // SYS_DEV_SPI_NATIVE_TARGET_H From e6131f823f858e2555c385e41d2409979e7f9938 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Jul 2022 12:30:29 +0100 Subject: [PATCH 063/572] More work on SPI for Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 4 + .../target_system_device_spi_config.cpp | 16 +- .../target_system_device_spi_config.h | 6 + .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 859 +++++++++--------- .../sys_dev_spi_native_target.h | 152 +++- 5 files changed, 542 insertions(+), 495 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index fa473466de..add9fefbac 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -32,6 +32,8 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolc list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/system/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/sleeptimer/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/spidrv/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/spidrv/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) @@ -70,6 +72,7 @@ set(gecko_sdk_srcs # emdrv dmadrv.c uartdrv.c + spidrv.c sl_device_init_dcdc_s1.c sl_device_init_emu_s1.c @@ -131,6 +134,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/gpiointerrupt/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/src + ${gecko_sdk_SOURCE_DIR}/platform/emdrv/spidrv/src ${gecko_sdk_SOURCE_DIR}/platform/emlib/src ${gecko_sdk_SOURCE_DIR}/platform/service/device_init/src ${gecko_sdk_SOURCE_DIR}/platform/service/iostream/src diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp index 4ebd4a5ab9..d0d4ee81fa 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -9,15 +9,15 @@ // SPI1 // ////////// -// Note on ST_B_L457EIOT01A SPI1 connects to CN1 ARDUINO connector +// Note on SL_STK3701A SPI1 connects to LCD-TFT Display // pin configuration for SPI1 on GPIOA AF5 -// port for SPI1_SCK is: GPIOA_5 : ARD.D13-SPI1_SCK/LED1 pin CN1_6 -// port for SPI1_MISO is: GPIOA_6 : ARD.D12-SPI1_MISO pin CN1_5 -// port for SPI1_MOSI is: GPIOA_7 : ARD.D11-SPI1_MOSI/PWM pin CN1_4 +// port for SPI1_SCK is: PC15 +// port for SPI1_MISO is: Not used +// port for SPI1_MOSI is: PC14 +// CS: PC14 -// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -SPI_CONFIG_PINS(1, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) +SPI_CONFIG_PINS(1, gpioPortC, 15, 0, -1, gpioPortC, 14, 0) ////////// // SPI2 // @@ -31,7 +31,7 @@ SPI_CONFIG_PINS(1, GPIOA, 5, GPIOA, 6, GPIOA, 7, 5) // port for SPI2_MOSI is: GPIOD_4 PMOD-UART2_RTS/SPI2_MOSI // GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -SPI_CONFIG_PINS(2, GPIOD, 1, GPIOD, 3, GPIOD, 4, 5) +// SPI_CONFIG_PINS(2, GPIOD, 1, GPIOD, 3, GPIOD, 4, 5) ////////// // SPI3 // @@ -45,4 +45,4 @@ SPI_CONFIG_PINS(2, GPIOD, 1, GPIOD, 3, GPIOD, 4, 5) // port for SPI3_MOSI is: GPIOD_12 INTERNAL-SPI3_MOSI // GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -SPI_CONFIG_PINS(3, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5) +// SPI_CONFIG_PINS(3, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h new file mode 100644 index 0000000000..56b68d1d4e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index ded08e9f55..9bcf75a2e7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -6,223 +6,113 @@ #include ///////////////////////////////////////////////////// -// SPI PAL strucs declared in win_dev_spi_native.h // +// SPI PAL strucs declared in sys_dev_spi_native.h // ///////////////////////////////////////////////////// -#if STM32_SPI_USE_SPI1 +#if GECKO_USE_SPI0 == TRUE +NF_PAL_SPI SPI0_PAL; +#endif +#if GECKO_USE_SPI1 == TRUE NF_PAL_SPI SPI1_PAL; #endif -#if STM32_SPI_USE_SPI2 +#if GECKO_USE_SPI2 == TRUE NF_PAL_SPI SPI2_PAL; #endif -#if STM32_SPI_USE_SPI3 +#if GECKO_USE_SPI3 == TRUE NF_PAL_SPI SPI3_PAL; #endif -#if STM32_SPI_USE_SPI4 +#if GECKO_USE_SPI4 == TRUE NF_PAL_SPI SPI4_PAL; #endif -#if STM32_SPI_USE_SPI5 +#if GECKO_USE_SPI5 == TRUE NF_PAL_SPI SPI5_PAL; -#endif -#if STM32_SPI_USE_SPI6 -NF_PAL_SPI SPI6_PAL; -#endif - -// Tidy up after completing tranfer -static void CompleteTranfer(NF_PAL_SPI *palSpi) -{ - // just to satisfy the driver ceremony, no actual implementation for STM32 - spiUnselect(palSpi->Driver); - - // Release the bus - spiReleaseBus(palSpi->Driver); - - // event occurred - if (palSpi->ReadSize > 0) - { - // because this was a Read transaction, need to copy from DMA buffer to managed buffer - int ReadSize = palSpi->ReadSize; - - // Adjust read size for data width of 16bits - if (palSpi->BufferIs16bits) - ReadSize *= 2; - - // invalidate cache over read buffer to ensure that content from DMA is read - // (only required for Cortex-M7) - // get the pointer to the read buffer as UINT16 because it's really an UINT16 (2 bytes) - cacheBufferInvalidate(palSpi->ReadBuffer, (palSpi->ReadSize * 2)); - } -} - -// Callback used when a async opertion completes -static void SpiCallback(SPIDriver *spip) -{ - (void)spip; - - NATIVE_INTERRUPT_START - - NF_PAL_SPI *palSpi = NULL; - - // Find the NF_PAL_SPI * for driver -#if STM32_SPI_USE_SPI1 - if (spip == &SPID1) - { - palSpi = &SPI1_PAL; - } -#endif -#if STM32_SPI_USE_SPI2 - if (spip == &SPID2) - { - palSpi = &SPI2_PAL; - } -#endif -#if STM32_SPI_USE_SPI3 - if (spip == &SPID3) - { - palSpi = &SPI3_PAL; - } -#endif -#if STM32_SPI_USE_SPI4 - if (spip == &SPID4) - { - palSpi = &SPI4_PAL; - } -#endif -#if STM32_SPI_USE_SPI5 - if (spip == &SPID5) - { - palSpi = &SPI5_PAL; - } -#endif -#if STM32_SPI_USE_SPI6 - if (spip == &SPID6) - { - palSpi = &SPI6_PAL; - } -#endif - - // check if there is any Rx operation due - if (palSpi->SequentialTxRx) - { - // yes there is! - // clear flag and... - palSpi->SequentialTxRx = false; - - // ... start it - if (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex) - { - // half duplex operation, clear output enable bit - palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; - } - spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); - } - else - { - // all done here! - - // Tidy up, release etc - CompleteTranfer(palSpi); - - // fire callback for SPI transaction complete - // only if callback set - if (palSpi->Callback) - palSpi->Callback(palSpi->BusIndex); - } - - NATIVE_INTERRUPT_END -}; - -// Computes the SPI peripheral baud rate according to the requested frequency -uint16_t ComputeBaudRate(SPI_DEVICE_CONFIGURATION &config, int32_t &actualFrequency) -{ - uint16_t divider = 0; - int32_t maxSpiFrequency; - int32_t requestedFrequency = config.Clock_RateHz; - int busIndex = config.Spi_Bus; - -#if defined(STM32L0XX) - - // SP1 is feed by APB2 (STM32_PCLK2) - actualFrequency = STM32_PCLK2; - - // SPI2 is feed by APB1 (STM32_PCLK1) - if (busIndex == 1) - { - actualFrequency = STM32_PCLK1; - } - - // from datasheet - maxSpiFrequency = 12000000; - -#elif defined(STM32F0XX) - - (void)busIndex; - - // STM32F0 SPI is always feed by APB1 - actualFrequency = STM32_PCLK1; - - // from datasheet - maxSpiFrequency = 18000000; - -#elif defined(STM32F4XX) || defined(STM32F7XX) - - // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2) - actualFrequency = STM32_PCLK2; - - // SPI2 and SPI3 are feed by APB1 (STM32_PCLK1) - if (busIndex == 2 || busIndex == 3) - { - actualFrequency = STM32_PCLK1; - } - - // this is not really accurate because there are different max SPI clocks depending on which APB clock source if - // feeding the SPI because ChibiOS doesn't offer that we have to go with minimum common denominator - maxSpiFrequency = STM32_SPII2S_MAX; - -#elif defined(STM32H7XX) - - // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2) - actualFrequency = STM32_PCLK2; - maxSpiFrequency = STM32_SPI456_MAX; - - // SPI1, SPI2 and SPI3 are feed by APB1 (STM32_PCLK1) - if (busIndex == 2 || busIndex == 3) - { - actualFrequency = STM32_PCLK1; - maxSpiFrequency = STM32_SPI123_MAX; - } - -#else - -#error "Error setting max SPI frequency. Check if the target series is defined." - #endif - // when requested frequency is 0, means that the developer hasn't set ClockFrequency in SpiConnectionSettings - // default to the max possible SPI frequency - if (requestedFrequency == 0) - { - requestedFrequency = maxSpiFrequency; - } - - for (; divider < 8; divider++) - { - actualFrequency = actualFrequency / 2; - - if (actualFrequency <= requestedFrequency) - { - // best match for the requested frequency - // just check if it's below the max SPI frequency - if (actualFrequency <= maxSpiFrequency) - { - // we are good with this value - break; - } - } - } - - // the baud rate bits are in the position B5:3 so need to left shit the divider value - return divider << 3; -} +// // Callback used when a async opertion completes +// static void SpiCallback(int BusIndex) +// { +// (void)spip; + +// NATIVE_INTERRUPT_START + +// NF_PAL_SPI *palSpi = NULL; + +// // Find the NF_PAL_SPI * for driver +// #if STM32_SPI_USE_SPI2 +// if (spip == &SPID1) +// { +// palSpi = &SPI2_PAL; +// } +// #endif +// #if STM32_SPI_USE_SPI3 +// if (spip == &SPID2) +// { +// palSpi = &SPI3_PAL; +// } +// #endif +// #if STM32_SPI_USE_SPI4 +// if (spip == &SPID3) +// { +// palSpi = &SPI4_PAL; +// } +// #endif +// #if STM32_SPI_USE_SPI5 +// if (spip == &SPID4) +// { +// palSpi = &SPI5_PAL; +// } +// #endif +// #if STM32_SPI_USE_SPI6 +// if (spip == &SPID5) +// { +// palSpi = &SPI6_PAL; +// } +// #endif +// #if STM32_SPI_USE_SPI6 +// if (spip == &SPID6) +// { +// palSpi = &SPI6_PAL; +// } +// #endif + +// // check if there is any Rx operation due +// if (palSpi->SequentialTxRx) +// { +// // yes there is! +// // clear flag and... +// palSpi->SequentialTxRx = false; + +// // ... start it +// if (palSpi->busConfiguration) +// { +// // half duplex operation, clear output enable bit +// palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; +// } +// spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); +// } +// else +// { +// // all done here! + +// if (palSpi->ReadSize > 0) +// { +// // because this was a Read transaction, need to copy from DMA buffer to managed buffer +// int ReadSize = palSpi->ReadSize; + +// // Adjust read size for data width of 16bits +// if (palSpi->BufferIs16bits) +// { +// ReadSize *= 2; +// } +// } + +// // fire callback for SPI transaction complete +// // only if callback set +// if (palSpi->Callback) +// palSpi->Callback(palSpi->BusIndex); +// } + +// NATIVE_INTERRUPT_END +// }; // Return the NF_PAL structure for busIndex // Return NULL is invalid bus @@ -233,36 +123,43 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) // get the PAL struct for the SPI bus switch (busIndex) { -#if STM32_SPI_USE_SPI1 + +#if GECKO_USE_SPI0 == TRUE + case 0: + palSpi = &SPI0_PAL; + break; +#endif + +#if GECKO_USE_SPI1 == TRUE case 1: palSpi = &SPI1_PAL; break; #endif -#if STM32_SPI_USE_SPI2 + +#if GECKO_USE_SPI2 == TRUE case 2: palSpi = &SPI2_PAL; break; #endif -#if STM32_SPI_USE_SPI3 + +#if GECKO_USE_SPI3 == TRUE case 3: palSpi = &SPI3_PAL; break; #endif -#if STM32_SPI_USE_SPI4 + +#if GECKO_USE_SPI4 == TRUE case 4: palSpi = &SPI4_PAL; break; #endif -#if STM32_SPI_USE_SPI5 + +#if GECKO_USE_SPI5 == TRUE case 5: palSpi = &SPI5_PAL; break; #endif -#if STM32_SPI_USE_SPI6 - case 6: - palSpi = &SPI6_PAL; - break; -#endif + default: // the requested SPI bus is not valid break; @@ -272,91 +169,42 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) } // Give a complete low-level SPI configuration from passed SPI_DEVICE_CONFIGURATION -void GetSPIConfig(SPI_DEVICE_CONFIGURATION &config, SPI_WRITE_READ_SETTINGS &wrc, SPIConfig *llConfig) +void GetSPIConfig(SPI_DEVICE_CONFIGURATION &config, SPI_WRITE_READ_SETTINGS &wrc, SPIDRV_Init_t *spiDrivInit) { - int32_t actualFrequency; - - // clear values - llConfig->cr1 = 0; - llConfig->cr2 = 0; - - // get chip select pin - int csPin = config.DeviceChipSelect; + (void)config; + (void)wrc; // SPI mode - switch (config.Spi_Mode) - { - case SpiMode_Mode1: - llConfig->cr1 |= SPI_CR1_CPHA; - break; - - case SpiMode_Mode2: - llConfig->cr1 |= SPI_CR1_CPOL; - break; - - case SpiMode_Mode3: - llConfig->cr1 |= SPI_CR1_CPHA | SPI_CR1_CPOL; - break; - - default: // Default to Mode0 if invalid mode specified - break; - } + // matches SPIDRV_ClockMode_t + spiDrivInit->clockMode = config.Spi_Mode; - // compute baud rate of SPI peripheral according to the requested frequency - llConfig->cr1 |= ComputeBaudRate(config, actualFrequency); - - // set data transfer length according passed setting + // set data transfer length if (wrc.Bits16ReadWrite) { - // Set data transfer length to 16 bits -#ifdef STM32F4XX - llConfig->cr1 |= SPI_CR1_DFF; -#endif -#ifdef STM32F7XX - llConfig->cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; -#endif - // Sets the order of bytes transmission : MSB first or LSB first - int bitOrder = config.DataOrder16; - if (bitOrder == DataBitOrder_LSB) - { - llConfig->cr1 |= SPI_CR1_LSBFIRST; - } + spiDrivInit->frameLength = 16; } else { - // set transfer length to 8bits -#ifdef STM32F4XX - llConfig->cr1 &= ~SPI_CR1_DFF; -#endif -#ifdef STM32F7XX - llConfig->cr2 |= SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; -#endif + spiDrivInit->frameLength = 8; } - // set bus configuration - // only required for half duplex mode - if (config.BusConfiguration == SpiBusConfiguration_HalfDuplex) + // baud rate + spiDrivInit->bitRate = config.Clock_RateHz; + + // Sets the order of bytes transmission : MSB first or LSB first + if (config.DataOrder16 == DataBitOrder_LSB) { -#ifdef STM32F4XX - llConfig->cr1 |= SPI_CR1_BIDIMODE; -#endif -#ifdef STM32F7XX - llConfig->cr2 |= SPI_CR1_BIDIMODE; -#endif + spiDrivInit->bitOrder = spidrvBitOrderLsbFirst; + } + else + { + spiDrivInit->bitOrder = spidrvBitOrderMsbFirst; } - // Create the low level configuration - llConfig->data_cb = SpiCallback; - - // make sure the CS pin is properly configured as GPIO, output & pushpull - palSetPadMode(GPIO_PORT(csPin), csPin % 16, (PAL_STM32_OSPEED_HIGHEST | PAL_MODE_OUTPUT_PUSHPULL)); - - // being SPI CS active low, default it to high - palSetPad(GPIO_PORT(csPin), csPin % 16); - - // set port&pad for CS pin - llConfig->ssport = GPIO_PORT(csPin); - llConfig->sspad = csPin % 16; + // TODO handle half duplex + // set bus configuration + // if (config.busConfiguration) + // } } // Performs a read/write operation on 8-bit word data. @@ -392,7 +240,8 @@ HRESULT CPU_SPI_nWrite_nRead( { bool busConfigIsHalfDuplex; NF_PAL_SPI *palSpi = (NF_PAL_SPI *)deviceHandle; - bool sync = (wrc.callback == 0); // If callback then use aync operation + // If callback then use aync operation + bool sync = (wrc.callback == 0); // Save width of transfer palSpi->BufferIs16bits = wrc.Bits16ReadWrite; @@ -413,36 +262,22 @@ HRESULT CPU_SPI_nWrite_nRead( // === Setup the operation and init buffers === palSpi->BusIndex = sdev.Spi_Bus; - // get the LL SPI configuration, depending on passed parameters and buffer element size - GetSPIConfig(sdev, wrc, &palSpi->Configuration); + // get the SPI configuration, depending on passed parameters and buffer element size + GetSPIConfig(sdev, wrc, &(palSpi->Handle->initData)); // set bus config flag busConfigIsHalfDuplex = palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex; - // Clear callback if sync - if (sync) - { - palSpi->Configuration.data_cb = NULL; - } + // // Clear callback if sync + // if (sync) + // { + // palSpi->Configuration..data_cb = NULL; + // } if (writeBuffer != NULL) { // set the pointer to the write buffer as BYTE palSpi->WriteBuffer = (uint8_t *)writeBuffer; - - // set DMA write buffer - if (palSpi->BufferIs16bits) - { - // flush DMA buffer to ensure cache coherency - // (only required for Cortex-M7) - cacheBufferFlush(palSpi->WriteBuffer, (palSpi->WriteSize * 2)); - } - else - { - // flush DMA buffer to ensure cache coherency - // (only required for Cortex-M7) - cacheBufferFlush(palSpi->WriteBuffer, palSpi->WriteSize); - } } if (readBuffer != NULL) @@ -454,12 +289,12 @@ HRESULT CPU_SPI_nWrite_nRead( } } - // because the bus access is shared, acquire and select the appropriate bus - spiAcquireBus(palSpi->Driver); - spiStart(palSpi->Driver, &palSpi->Configuration); + // // because the bus access is shared, acquire and select the appropriate bus + // spiAcquireBus(palSpi->Driver); + // spiStart(palSpi->Driver, &palSpi->Configuration); - // just to satisfy the driver ceremony, no actual implementation for STM32 - spiSelect(palSpi->Driver); + // // just to satisfy the driver ceremony, no actual implementation for STM32 + // spiSelect(palSpi->Driver); if (sync) { @@ -470,31 +305,31 @@ HRESULT CPU_SPI_nWrite_nRead( // Transmit+Receive if (wrc.fullDuplex) { - // Full duplex - // Uses the largest buffer size as transfer size - spiExchange( - palSpi->Driver, - palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, - palSpi->WriteBuffer, - palSpi->ReadBuffer); + // // Full duplex + // // Uses the largest buffer size as transfer size + // spiExchange( + // palSpi->Driver, + // palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + // palSpi->WriteBuffer, + // palSpi->ReadBuffer); } else { - // send operation - if (busConfigIsHalfDuplex) - { - // half duplex operation, set output enable - palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; - } - spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); - - // receive operation - if (busConfigIsHalfDuplex) - { - // half duplex operation, set output enable - palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; - } - spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + // // send operation + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + // } + // spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + + // // receive operation + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + // spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); } } else @@ -502,14 +337,14 @@ HRESULT CPU_SPI_nWrite_nRead( // Transmit only or Receive only if (palSpi->ReadSize != 0) { - // receive - if (busConfigIsHalfDuplex) - { - // half duplex operation, set output enable - palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; - } - - spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + // // receive + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + + // spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); } else { @@ -517,15 +352,25 @@ HRESULT CPU_SPI_nWrite_nRead( if (busConfigIsHalfDuplex) { // half duplex operation, set output enable - palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; } - spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); } } - // Release bus & cacheBufferInvalidate etc - CompleteTranfer(palSpi); + // event occurred + if (palSpi->ReadSize > 0) + { + // because this was a Read transaction, need to copy from DMA buffer to managed buffer + int ReadSize = palSpi->ReadSize; + + // Adjust read size for data width of 16bits + if (palSpi->BufferIs16bits) + { + ReadSize *= 2; + } + } } else // Start an Asyncronous SPI transfer @@ -543,12 +388,12 @@ HRESULT CPU_SPI_nWrite_nRead( // single operation, clear flag palSpi->SequentialTxRx = false; - // Uses the largest buffer size as transfer size - spiStartExchange( - palSpi->Driver, - palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, - palSpi->WriteBuffer, - palSpi->ReadBuffer); + // // Uses the largest buffer size as transfer size + // spiStartExchange( + // palSpi->Driver, + // palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + // palSpi->WriteBuffer, + // palSpi->ReadBuffer); } else { @@ -558,11 +403,11 @@ HRESULT CPU_SPI_nWrite_nRead( // start send operation if (busConfigIsHalfDuplex) { - // half duplex operation, set output enable - palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + // // half duplex operation, set output enable + // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; } - spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); // receive operation will be started in the callback after the above completes } } @@ -574,16 +419,16 @@ HRESULT CPU_SPI_nWrite_nRead( // single operation, clear flag palSpi->SequentialTxRx = false; - // start receive - spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + // // start receive + // spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); } else { // single operation, clear flag palSpi->SequentialTxRx = false; - // start send - spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // // start send + // spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); } } @@ -595,94 +440,183 @@ HRESULT CPU_SPI_nWrite_nRead( NANOCLR_NOCLEANUP(); } -SPI_OP_STATUS CPU_SPI_OP_Status(uint8_t spi_bus, uint32_t deviceHandle) +bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) { - (void)spi_bus; - - NF_PAL_SPI *palSpi = (NF_PAL_SPI *)deviceHandle; - SPI_OP_STATUS os; - - switch (palSpi->Driver->state) + (void)busConfiguration; + + SPIDRV_Init_t spiInit = { + NULL, +#if defined(_USART_ROUTELOC0_MASK) + 0, + 0, + 0, + 0, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +#else + 0, +#endif + SL_SPIDRV_EXP_BITRATE, + 0, + 0, + spidrvMaster, + 0, + spidrvClockMode0, + 0, + spidrvSlaveStartImmediate + }; + + // set CS control upfront + if (busConfiguration.DeviceChipSelect >= 0) { - default: - case SPI_UNINIT: - case SPI_STOP: - case SPI_READY: - os = SPI_OP_READY; - break; - - case SPI_ACTIVE: - os = SPI_OP_RUNNING; - break; - - case SPI_COMPLETE: - os = SPI_OP_COMPLETE; - break; + spiInit.csControl = spidrvCsControlAuto; + } + else + { + spiInit.csControl = spidrvCsControlApplication; } - return os; -} -bool CPU_SPI_Initialize(uint8_t busIndex, SpiBusConfiguration busConfiguration) -{ // init the PAL struct for this SPI bus and assign the respective driver // all this occurs if not already done // why do we need this? because several SPIDevice objects can be created associated to the same bus - switch (busIndex + 1) + switch (busIndex) { -#if STM32_SPI_USE_SPI1 + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if GECKO_USE_SPI0 == TRUE + case 0: + if (SPI0_PAL.Handle == NULL) + { + SPI0_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + + if (SPI1_PAL.Configuration == NULL) + { + return false; + } + + // copy init struct + memcpy(SPI0_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); + + ConfigPins_SPI0(busConfiguration); + } + break; +#endif + +#if GECKO_USE_SPI1 == TRUE case 1: - if (SPI1_PAL.Driver == NULL) + if (SPI1_PAL.Handle == NULL) { - ConfigPins_SPI1(busConfiguration == SpiBusConfiguration_HalfDuplex); - SPI1_PAL.Driver = &SPID1; + // allocate memory for the SPIDRV_HandleData + SPI1_PAL.Handle = (SPIDRV_Handle_t)platform_malloc(sizeof(SPIDRV_HandleData_t)); + // sanity check allocation + if (SPI1_PAL.Handle == NULL) + { + return false; + } + + // allocate memory for the SPIDRV_Init_t + SPIDRV_Init_t *initSpinConfig = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + // sanity check allocation + if (initSpinConfig == NULL) + { + return false; + } + + // copy init struct + memcpy(initSpinConfig, &spiInit, sizeof(SPIDRV_Init_t)); + + ConfigPins_SPI1(busConfiguration, *initSpinConfig); + + SPIDRV_Init(SPI1_PAL.Handle, initSpinConfig); } break; #endif -#if STM32_SPI_USE_SPI2 + +#if GECKO_USE_SPI2 == TRUE case 2: - if (SPI2_PAL.Driver == NULL) + if (SPI2_PAL.Handle == NULL) { - ConfigPins_SPI2(busConfiguration == SpiBusConfiguration_HalfDuplex); - SPI2_PAL.Driver = &SPID2; + SPI2_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + + if (SPI2_PAL.Configuration == NULL) + { + return false; + } + + // copy init struct + memcpy(SPI2_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); + + ConfigPins_SPI2(busConfiguration); } break; #endif -#if STM32_SPI_USE_SPI3 + +#if GECKO_USE_SPI3 == TRUE case 3: - if (SPI3_PAL.Driver == NULL) + if (SPI3_PAL.Handle == NULL) { - ConfigPins_SPI3(busConfiguration == SpiBusConfiguration_HalfDuplex); - SPI3_PAL.Driver = &SPID3; + SPI3_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + + if (SPI3_PAL.Configuration == NULL) + { + return false; + } + + // copy init struct + memcpy(SPI3_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); + + ConfigPins_SPI3(busConfiguration); } break; #endif -#if STM32_SPI_USE_SPI4 + +#if GECKO_USE_SPI4 == TRUE case 4: - if (SPI4_PAL.Driver == NULL) + if (SPI4_PAL.Handle == NULL) { - ConfigPins_SPI4(busConfiguration == SpiBusConfiguration_HalfDuplex); - SPI4_PAL.Driver = &SPID4; + SPI4_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + + if (SPI4_PAL.Configuration == NULL) + { + return false; + } + + // copy init struct + memcpy(SPI4_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); + + ConfigPins_SPI4(busConfiguration); } break; #endif -#if STM32_SPI_USE_SPI5 + +#if GECKO_USE_SPI5 == TRUE case 5: - if (SPI5_PAL.Driver == NULL) - { - ConfigPins_SPI5(busConfiguration == SpiBusConfiguration_HalfDuplex); - SPI5_PAL.Driver = &SPID5; - } - break; -#endif -#if STM32_SPI_USE_SPI6 - case 6: - if (SPI6_PAL.Driver == NULL) + if (SPI5_PAL.Handle == NULL) { - ConfigPins_SPI6(busConfiguration == SpiBusConfiguration_HalfDuplex); - SPI6_PAL.Driver = &SPID6; + SPI5_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + + if (SPI5_PAL.Configuration == NULL) + { + return false; + } + + // copy init struct + memcpy(SPI5_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); + + ConfigPins_SPI5(busConfiguration); } break; #endif + default: // this SPI bus is not valid return false; @@ -694,53 +628,66 @@ bool CPU_SPI_Initialize(uint8_t busIndex, SpiBusConfiguration busConfiguration) bool CPU_SPI_Uninitialize(uint8_t busIndex) { // get the PAL struct for the SPI bus - switch (busIndex + 1) + switch (busIndex) { -#if STM32_SPI_USE_SPI1 + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if GECKO_USE_SPI0 == TRUE + case 0: + // spiStop(&SPID0); + SPI0_PAL.Configuration = NULL; + // spiReleaseBus(&SPID1); + break; +#endif + +#if GECKO_USE_SPI1 == TRUE case 1: - spiStop(&SPID1); - SPI1_PAL.Driver = NULL; - spiReleaseBus(&SPID1); + + SPIDRV_DeInit(SPI1_PAL.Handle); + + // free memory + platform_free(&SPI1_PAL.Handle->initData); + platform_free(SPI1_PAL.Handle); + + // clears configuration + SPI1_PAL.Handle = NULL; + break; #endif -#if STM32_SPI_USE_SPI2 +#if GECKO_USE_SPI2 == TRUE case 2: - spiStop(&SPID2); - SPI2_PAL.Driver = NULL; - spiReleaseBus(&SPID2); + // spiStop(&SPID3); + SPI2_PAL.Configuration = NULL; + // spiReleaseBus(&SPID3); break; #endif -#if STM32_SPI_USE_SPI3 +#if GECKO_USE_SPI3 == TRUE case 3: - spiStop(&SPID3); - SPI3_PAL.Driver = NULL; - spiReleaseBus(&SPID3); + // spiStop(&SPID3); + SPI3_PAL.Configuration = NULL; + // spiReleaseBus(&SPID4); break; #endif -#if STM32_SPI_USE_SPI4 +#if GECKO_USE_SPI4 == TRUE case 4: - spiStop(&SPID4); - SPI4_PAL.Driver = NULL; - spiReleaseBus(&SPID4); + // spiStop(&SPID5); + SPI4_PAL.Configuration = NULL; + // spiReleaseBus(&SPID5); break; #endif -#if STM32_SPI_USE_SPI5 +#if GECKO_USE_SPI5 == TRUE case 5: - spiStop(&SPID5); - SPI5_PAL.Driver = NULL; - spiReleaseBus(&SPID5); - break; -#endif + // free memory + platform_free(SPI5_PAL.Configuration); -#if STM32_SPI_USE_SPI6 - case 6: - spiStop(&SPID6); - SPI6_PAL.Driver = NULL; - spiReleaseBus(&SPID6); + // clears configuration + SPI5_PAL.Configuration = NULL; break; #endif @@ -757,24 +704,34 @@ uint32_t CPU_SPI_PortsMap() { uint32_t map = 0; -#if STM32_SPI_USE_SPI1 + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if GECKO_USE_SPI0 == TRUE map |= 0x01; #endif -#if STM32_SPI_USE_SPI2 + +#if GECKO_USE_SPI1 == TRUE map |= 0x02; #endif -#if STM32_SPI_USE_SPI3 + +#if GECKO_USE_SPI2 == TRUE map |= 0x04; #endif -#if STM32_SPI_USE_SPI4 + +#if GECKO_USE_SPI3 == TRUE map |= 0x08; #endif -#if STM32_SPI_USE_SPI5 + +#if GECKO_USE_SPI4 == TRUE map |= 0x10; #endif -#if STM32_SPI_USE_SPI6 + +#if GECKO_USE_SPI5 == TRUE map |= 0x20; #endif + return map; } @@ -812,7 +769,7 @@ HRESULT CPU_SPI_MinClockFrequency(uint32_t spiBus, int32_t *frequency) } // Max prescaler value = 256 - // SPI2 or SPI3 are on APB1, so divide max frequency by four. + // SPI3 or SPI4 are on APB1, so divide max frequency by four. *frequency = (spiBus == 2 or spiBus == 3) ? SystemCoreClock >>= 9 : SystemCoreClock >> 8; return S_OK; @@ -827,7 +784,7 @@ HRESULT CPU_SPI_MaxClockFrequency(uint32_t spiBus, int32_t *frequency) // According to STM : "At a minimum, the clock frequency should be twice the required communication frequency." // So maximum useable frequency is CoreClock / 2. - // SPI2 or SPI3 are on APB1, so divide max frequency by four. + // SPI3 or SPI4 are on APB1, so divide max frequency by four. *frequency = (spiBus == 2 or spiBus == 3) ? SystemCoreClock >>= 2 : SystemCoreClock >> 1; return S_OK; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 9bde0a49e0..bc1bf919c0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -6,26 +6,72 @@ #ifndef SYS_DEV_SPI_NATIVE_TARGET_H #define SYS_DEV_SPI_NATIVE_TARGET_H - -// #include -// #include -// #include - - #include +#include +#include #include #include +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// set missing defines +#if defined(USART0) +#ifndef GECKO_USE_SPI0 +#define GECKO_USE_SPI0 FALSE +#endif +#else +#define GECKO_USE_SPI0 FALSE +#endif + +#if defined(USART1) +#ifndef GECKO_USE_SPI1 +#define GECKO_USE_SPI1 FALSE +#endif +#else +#define GECKO_USE_SPI1 FALSE +#endif + +#if defined(USART2) +#ifndef GECKO_USE_SPI2 +#define GECKO_USE_SPI2 FALSE +#endif +#else +#define GECKO_USE_SPI2 FALSE +#endif + +#if defined(USART3) +#ifndef GECKO_USE_SPI3 +#define GECKO_USE_SPI3 FALSE +#endif +#else +#define GECKO_USE_SPI3 FALSE +#endif + +#if defined(USART4) +#ifndef GECKO_USE_SPI4 +#define GECKO_USE_SPI4 FALSE +#endif +#else +#define GECKO_USE_SPI4 FALSE +#endif + +#if defined(USART5) +#ifndef GECKO_USE_SPI5 +#define GECKO_USE_SPI5 FALSE +#endif +#else +#define GECKO_USE_SPI5 FALSE +#endif + // struct representing the SPI bus struct NF_PAL_SPI { int BusIndex; - SPIDRV_Handle_t *Driver; - SPIDRV_Init_t Configuration; - // SpiBusConfiguration BusConfiguration; + SPIDRV_Handle_t Handle; + SpiBusConfiguration BusConfiguration; - //SPI_Callback Callback; + SPI_Callback Callback; bool SequentialTxRx; bool BufferIs16bits; @@ -37,42 +83,76 @@ struct NF_PAL_SPI uint16_t ReadSize; }; +//////////////////////////////////////////// +// declaration of the the SPI PAL structs // +//////////////////////////////////////////// +#if GECKO_USE_SPI0 == TRUE +extern NF_PAL_SPI SPI0_PAL; +#endif +#if GECKO_USE_SPI1 == TRUE +extern NF_PAL_SPI SPI1_PAL; +#endif +#if GECKO_USE_SPI2 == TRUE +extern NF_PAL_SPI SPI2_PAL; +#endif +#if GECKO_USE_SPI3 == TRUE +extern NF_PAL_SPI SPI3_PAL; +#endif +#if GECKO_USE_SPI4 == TRUE +extern NF_PAL_SPI SPI4_PAL; +#endif +#if GECKO_USE_SPI5 == TRUE +extern NF_PAL_SPI SPI5_PAL; +#endif + +#if defined(_USART_ROUTELOC0_MASK) + // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations #define SPI_CONFIG_PINS( \ num, \ - gpio_port_sck, \ - sck_pin, - sck_port_location, \ - gpio_port_miso, \ - miso_pin, - miso_port_location, \ - gpio_port_mosi, \ - mosi_pin, - mosi_port_location \ - ) - \ - void ConfigPins_SPI##num(bool isHalfDuplex) \ - { - SPI##num##_PAL.Configuration->sclPort = gpio_port_scl; \ - SPI##num##_PAL.Configuration->sdaPort = gpio_port_sda; \ - SPI##num##_PAL.Configuration->sclPin = scl_pin; \ - SPI##num##_PAL.Configuration->sdaPin = sda_pin; \ - SPI##num##_PAL.Configuration->portLocationScl = scl_port_location; \ - SPI##num##_PAL.Configuration->portLocationSda = sda_port_location; \ - \ + port_location_mosi, \ + port_location_miso, \ + port_location_clk, \ + pin_mosi, \ + pin_miso, \ + pin_clk, \ + port_location) \ + \ + void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit) \ + { \ + spiInit.portLocationTx = port_location_mosi; \ + spiInit.portLocationClk = port_location_clk; \ + if (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + { \ + spiInit.portLocationRx = port_location_miso; \ + } \ + if (spiDeviceConfig.DeviceChipSelect >= 0) \ + { \ + spiInit.portLocationCs = GPIO_PORT(spiDeviceConfig.DeviceChipSelect); \ + if (spiDeviceConfig.ChipSelectActive) \ + { \ + } \ + else \ + { \ + } \ + } \ } +#else +#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#endif + ////////////////////////////////////////////////////////////////////////////////////////////// // when an SPI is defined the declarations below will have the real function/configuration // // in the target folder @ target_windows_devices_spi_config.cpp // ////////////////////////////////////////////////////////////////////////////////////////////// -void ConfigPins_SPI1(bool isHalfDuplex); -void ConfigPins_SPI2(bool isHalfDuplex); -void ConfigPins_SPI3(bool isHalfDuplex); -void ConfigPins_SPI4(bool isHalfDuplex); -void ConfigPins_SPI5(bool isHalfDuplex); -void ConfigPins_SPI6(bool isHalfDuplex); +void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); #endif // SYS_DEV_SPI_NATIVE_TARGET_H From 2bca72e8c184baee269106af77c12178c0301f58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Jul 2022 14:54:35 +0100 Subject: [PATCH 064/572] Complete implementation of SPI driver for Gecko SDK - Add handling of CS. - Improve init and configuration. --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 545 +++++++++--------- .../sys_dev_spi_native_target.h | 3 + 2 files changed, 269 insertions(+), 279 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 9bcf75a2e7..de2e11fde5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -27,92 +27,108 @@ NF_PAL_SPI SPI4_PAL; NF_PAL_SPI SPI5_PAL; #endif -// // Callback used when a async opertion completes -// static void SpiCallback(int BusIndex) -// { -// (void)spip; - -// NATIVE_INTERRUPT_START - -// NF_PAL_SPI *palSpi = NULL; - -// // Find the NF_PAL_SPI * for driver -// #if STM32_SPI_USE_SPI2 -// if (spip == &SPID1) -// { -// palSpi = &SPI2_PAL; -// } -// #endif -// #if STM32_SPI_USE_SPI3 -// if (spip == &SPID2) -// { -// palSpi = &SPI3_PAL; -// } -// #endif -// #if STM32_SPI_USE_SPI4 -// if (spip == &SPID3) -// { -// palSpi = &SPI4_PAL; -// } -// #endif -// #if STM32_SPI_USE_SPI5 -// if (spip == &SPID4) -// { -// palSpi = &SPI5_PAL; -// } -// #endif -// #if STM32_SPI_USE_SPI6 -// if (spip == &SPID5) -// { -// palSpi = &SPI6_PAL; -// } -// #endif -// #if STM32_SPI_USE_SPI6 -// if (spip == &SPID6) -// { -// palSpi = &SPI6_PAL; -// } -// #endif - -// // check if there is any Rx operation due -// if (palSpi->SequentialTxRx) -// { -// // yes there is! -// // clear flag and... -// palSpi->SequentialTxRx = false; - -// // ... start it -// if (palSpi->busConfiguration) -// { -// // half duplex operation, clear output enable bit -// palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; -// } -// spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); -// } -// else -// { -// // all done here! - -// if (palSpi->ReadSize > 0) -// { -// // because this was a Read transaction, need to copy from DMA buffer to managed buffer -// int ReadSize = palSpi->ReadSize; - -// // Adjust read size for data width of 16bits -// if (palSpi->BufferIs16bits) -// { -// ReadSize *= 2; -// } -// } - -// // fire callback for SPI transaction complete -// // only if callback set -// if (palSpi->Callback) -// palSpi->Callback(palSpi->BusIndex); -// } - -// NATIVE_INTERRUPT_END -// }; +#if defined(USART_PRESENT) +static USART_TypeDef *GetUsartFromHandle(struct SPIDRV_HandleData *handle) +{ + return handle->peripheral.usartPort; +} +#endif +#if defined(EUSART_PRESENT) +static EUSART_TypeDef *GetUsartFromHandle(struct SPIDRV_HandleData *handle) +{ + return handle->peripheral.eusartPort; +} +#endif + +// Callback used when a async transfer operation completes +static void SpiTransferCompleteCallback(struct SPIDRV_HandleData *handle, Ecode_t transferStatus, int itemsTransferred) +{ + (void)transferStatus; + (void)itemsTransferred; + NATIVE_INTERRUPT_START + + NF_PAL_SPI *palSpi = NULL; + + // Find the NF_PAL_SPI* for driver +#if GECKO_USE_SPI0 == TRUE + if (GetUsartFromHandle(handle) == USART0) + { + palSpi = &SPI0_PAL; + } +#endif + +#if GECKO_USE_SPI1 == TRUE + if (GetUsartFromHandle(handle) == USART1) + { + palSpi = &SPI1_PAL; + } +#endif + +#if GECKO_USE_SPI2 == TRUE + if (GetUsartFromHandle(handle) == USART2) + { + palSpi = &SPI2_PAL; + } +#endif + +#if GECKO_USE_SPI3 == TRUE + if (GetUsartFromHandle(handle) == USART3) + { + palSpi = &SPI3_PAL; + } +#endif + +#if GECKO_USE_SPI4 == TRUE + if (GetUsartFromHandle(handle) == USART4) + { + palSpi = &SPI4_PAL; + } +#endif + +#if GECKO_USE_SPI5 == TRUE + if (GetUsartFromHandle(handle) == USART5) + { + palSpi = &SPI5_PAL; + } +#endif + + // check if there is any Rx operation due + if (palSpi->SequentialTxRx) + { + // yes there is! + // clear flag and... + palSpi->SequentialTxRx = false; + + // ... start it + // TODO + // if (palSpi->busConfiguration) + // { + // // half duplex operation, clear output enable bit + // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + SPIDRV_MReceive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + } + else + { + // all done here! + + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) + { + // de-assert pin based on CS active level + CPU_GPIO_TogglePinState(palSpi->ChipSelect); + } + + // fire callback for SPI transaction complete + // only if callback set + if (palSpi->Callback) + { + palSpi->Callback(palSpi->BusIndex); + } + } + + NATIVE_INTERRUPT_END +}; // Return the NF_PAL structure for busIndex // Return NULL is invalid bus @@ -169,25 +185,12 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) } // Give a complete low-level SPI configuration from passed SPI_DEVICE_CONFIGURATION -void GetSPIConfig(SPI_DEVICE_CONFIGURATION &config, SPI_WRITE_READ_SETTINGS &wrc, SPIDRV_Init_t *spiDrivInit) +void GetSPIConfig(const SPI_DEVICE_CONFIGURATION &config, SPIDRV_Init_t *spiDrivInit) { - (void)config; - (void)wrc; - // SPI mode // matches SPIDRV_ClockMode_t spiDrivInit->clockMode = config.Spi_Mode; - // set data transfer length - if (wrc.Bits16ReadWrite) - { - spiDrivInit->frameLength = 16; - } - else - { - spiDrivInit->frameLength = 8; - } - // baud rate spiDrivInit->bitRate = config.Clock_RateHz; @@ -262,18 +265,11 @@ HRESULT CPU_SPI_nWrite_nRead( // === Setup the operation and init buffers === palSpi->BusIndex = sdev.Spi_Bus; - // get the SPI configuration, depending on passed parameters and buffer element size - GetSPIConfig(sdev, wrc, &(palSpi->Handle->initData)); + SPIDRV_SetFramelength(palSpi->Handle, wrc.Bits16ReadWrite ? 16 : 8); // set bus config flag busConfigIsHalfDuplex = palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex; - // // Clear callback if sync - // if (sync) - // { - // palSpi->Configuration..data_cb = NULL; - // } - if (writeBuffer != NULL) { // set the pointer to the write buffer as BYTE @@ -289,12 +285,12 @@ HRESULT CPU_SPI_nWrite_nRead( } } - // // because the bus access is shared, acquire and select the appropriate bus - // spiAcquireBus(palSpi->Driver); - // spiStart(palSpi->Driver, &palSpi->Configuration); - - // // just to satisfy the driver ceremony, no actual implementation for STM32 - // spiSelect(palSpi->Driver); + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) + { + // assert pin based on CS active level + CPU_GPIO_SetPinState(GPIO_PORT(palSpi->ChipSelect), (GpioPinValue)sdev.ChipSelectActive); + } if (sync) { @@ -305,31 +301,33 @@ HRESULT CPU_SPI_nWrite_nRead( // Transmit+Receive if (wrc.fullDuplex) { - // // Full duplex - // // Uses the largest buffer size as transfer size - // spiExchange( - // palSpi->Driver, - // palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, - // palSpi->WriteBuffer, - // palSpi->ReadBuffer); + // Full duplex + // Uses the largest buffer size as transfer size + SPIDRV_MTransferB( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->ReadBuffer, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize); } else { - // // send operation + // send operation + // TODO // if (busConfigIsHalfDuplex) // { // // half duplex operation, set output enable // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; // } - // spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + SPIDRV_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); - // // receive operation + // receive operation + // TODO // if (busConfigIsHalfDuplex) // { // // half duplex operation, set output enable // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - // spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + SPIDRV_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } } else @@ -337,46 +335,48 @@ HRESULT CPU_SPI_nWrite_nRead( // Transmit only or Receive only if (palSpi->ReadSize != 0) { - // // receive + // receive + // TODO // if (busConfigIsHalfDuplex) // { // // half duplex operation, set output enable // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - - // spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + SPIDRV_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } else { // send + // TODO if (busConfigIsHalfDuplex) { // half duplex operation, set output enable // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; } - - // spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + SPIDRV_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); } } - // event occurred - if (palSpi->ReadSize > 0) + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) { - // because this was a Read transaction, need to copy from DMA buffer to managed buffer - int ReadSize = palSpi->ReadSize; - - // Adjust read size for data width of 16bits - if (palSpi->BufferIs16bits) - { - ReadSize *= 2; - } + // de-assert pin based on CS active level + CPU_GPIO_TogglePinState(palSpi->ChipSelect); } } else - // Start an Asyncronous SPI transfer - // perform SPI operation using driver's ASYNC API - // Completed on calling Spi Callback { + // Start an Asyncronous SPI transfer + // perform SPI operation using driver's ASYNC API + // Completed on calling SPI Callback + + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) + { + // assert pin based on CS active level + CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); + } + // this is a Async operation // perform SPI operation using driver's ASYNC API if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) @@ -388,12 +388,13 @@ HRESULT CPU_SPI_nWrite_nRead( // single operation, clear flag palSpi->SequentialTxRx = false; - // // Uses the largest buffer size as transfer size - // spiStartExchange( - // palSpi->Driver, - // palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, - // palSpi->WriteBuffer, - // palSpi->ReadBuffer); + // Uses the largest buffer size as transfer size + SPIDRV_MTransfer( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->ReadBuffer, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + SpiTransferCompleteCallback); } else { @@ -407,8 +408,12 @@ HRESULT CPU_SPI_nWrite_nRead( // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; } - // spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); // receive operation will be started in the callback after the above completes + SPIDRV_MTransmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); } } else @@ -419,16 +424,20 @@ HRESULT CPU_SPI_nWrite_nRead( // single operation, clear flag palSpi->SequentialTxRx = false; - // // start receive - // spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + // start receive + SPIDRV_MReceive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); } else { // single operation, clear flag palSpi->SequentialTxRx = false; - // // start send - // spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // start send + SPIDRV_MTransmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); } } @@ -442,7 +451,15 @@ HRESULT CPU_SPI_nWrite_nRead( bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) { - (void)busConfiguration; + NF_PAL_SPI *palSpi = NULL; + void (*configPinsHandler)(const struct SPI_DEVICE_CONFIGURATION &, struct SPIDRV_Init &) = NULL; + +#if defined(USART_PRESENT) + USART_TypeDef *usart = NULL; +#endif +#if defined(EUSART_PRESENT) + EUSART_TypeDef *usart = NULL; +#endif SPIDRV_Init_t spiInit = { NULL, @@ -463,26 +480,18 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #else 0, #endif - SL_SPIDRV_EXP_BITRATE, 0, 0, + 0, + // always MASTER mode spidrvMaster, 0, - spidrvClockMode0, 0, + // we'll be controlling CS + spidrvCsControlApplication, spidrvSlaveStartImmediate }; - // set CS control upfront - if (busConfiguration.DeviceChipSelect >= 0) - { - spiInit.csControl = spidrvCsControlAuto; - } - else - { - spiInit.csControl = spidrvCsControlApplication; - } - // init the PAL struct for this SPI bus and assign the respective driver // all this occurs if not already done // why do we need this? because several SPIDevice objects can be created associated to the same bus @@ -494,126 +503,45 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI0 == TRUE case 0: - if (SPI0_PAL.Handle == NULL) - { - SPI0_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); - - if (SPI1_PAL.Configuration == NULL) - { - return false; - } - - // copy init struct - memcpy(SPI0_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); - - ConfigPins_SPI0(busConfiguration); - } + palSpi = &SPI0_PAL; + usart = USART0; + configPinsHandler = &ConfigPins_SPI0; break; #endif #if GECKO_USE_SPI1 == TRUE case 1: - if (SPI1_PAL.Handle == NULL) - { - // allocate memory for the SPIDRV_HandleData - SPI1_PAL.Handle = (SPIDRV_Handle_t)platform_malloc(sizeof(SPIDRV_HandleData_t)); - // sanity check allocation - if (SPI1_PAL.Handle == NULL) - { - return false; - } - - // allocate memory for the SPIDRV_Init_t - SPIDRV_Init_t *initSpinConfig = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); - // sanity check allocation - if (initSpinConfig == NULL) - { - return false; - } - - // copy init struct - memcpy(initSpinConfig, &spiInit, sizeof(SPIDRV_Init_t)); - - ConfigPins_SPI1(busConfiguration, *initSpinConfig); - - SPIDRV_Init(SPI1_PAL.Handle, initSpinConfig); - } + palSpi = &SPI1_PAL; + usart = USART1; + configPinsHandler = ConfigPins_SPI1; break; #endif #if GECKO_USE_SPI2 == TRUE case 2: - if (SPI2_PAL.Handle == NULL) - { - SPI2_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); - - if (SPI2_PAL.Configuration == NULL) - { - return false; - } - - // copy init struct - memcpy(SPI2_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); - - ConfigPins_SPI2(busConfiguration); - } + palSpi = &SPI2_PAL; + usart = USART2; break; #endif #if GECKO_USE_SPI3 == TRUE case 3: - if (SPI3_PAL.Handle == NULL) - { - SPI3_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); - - if (SPI3_PAL.Configuration == NULL) - { - return false; - } - - // copy init struct - memcpy(SPI3_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); - - ConfigPins_SPI3(busConfiguration); - } + palSpi = &SPI3_PAL; + usart = USART3; break; #endif #if GECKO_USE_SPI4 == TRUE case 4: - if (SPI4_PAL.Handle == NULL) - { - SPI4_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); - - if (SPI4_PAL.Configuration == NULL) - { - return false; - } - - // copy init struct - memcpy(SPI4_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); - - ConfigPins_SPI4(busConfiguration); - } + palSpi = &SPI4_PAL; + usart = USART4; break; #endif #if GECKO_USE_SPI5 == TRUE case 5: - if (SPI5_PAL.Handle == NULL) - { - SPI5_PAL.Configuration = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); - - if (SPI5_PAL.Configuration == NULL) - { - return false; - } - - // copy init struct - memcpy(SPI5_PAL.Configuration, &spiInit, sizeof(SPIDRV_Init_t)); - - ConfigPins_SPI5(busConfiguration); - } + palSpi = &SPI5_PAL; + usart = USART5; break; #endif @@ -622,6 +550,44 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon return false; } + if (palSpi->Handle == NULL) + { + // allocate memory for the SPIDRV_HandleData + palSpi->Handle = (SPIDRV_Handle_t)platform_malloc(sizeof(SPIDRV_HandleData_t)); + // sanity check allocation + if (palSpi->Handle == NULL) + { + return false; + } + + // allocate memory for the SPIDRV_Init_t + SPIDRV_Init_t *initSpinConfig = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + // sanity check allocation + if (initSpinConfig == NULL) + { + // need to free this + platform_free(palSpi->Handle); + + return false; + } + + // copy init struct + memcpy(initSpinConfig, &spiInit, sizeof(SPIDRV_Init_t)); + + // set USART + initSpinConfig->port = usart; + + // call handler to configure pins + configPinsHandler(busConfiguration, *initSpinConfig); + + palSpi->ChipSelect = busConfiguration.DeviceChipSelect; + + // get the SPI configuration + GetSPIConfig(busConfiguration, initSpinConfig); + + SPIDRV_Init(palSpi->Handle, initSpinConfig); + } + return true; } @@ -636,22 +602,25 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) #if GECKO_USE_SPI0 == TRUE case 0: - // spiStop(&SPID0); - SPI0_PAL.Configuration = NULL; - // spiReleaseBus(&SPID1); + SPIDRV_DeInit(SPI0_PAL.Handle); + + // free memory + platform_free(&SPI0_PAL.Handle->initData); + platform_free(SPI0_PAL.Handle); + + SPI0_PAL.Handle = NULL; + break; #endif #if GECKO_USE_SPI1 == TRUE case 1: - SPIDRV_DeInit(SPI1_PAL.Handle); // free memory platform_free(&SPI1_PAL.Handle->initData); platform_free(SPI1_PAL.Handle); - // clears configuration SPI1_PAL.Handle = NULL; break; @@ -659,35 +628,53 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) #if GECKO_USE_SPI2 == TRUE case 2: - // spiStop(&SPID3); - SPI2_PAL.Configuration = NULL; - // spiReleaseBus(&SPID3); + SPIDRV_DeInit(SPI2_PAL.Handle); + + // free memory + platform_free(&SPI2_PAL.Handle->initData); + platform_free(SPI2_PAL.Handle); + + SPI2_PAL.Handle = NULL; + break; #endif #if GECKO_USE_SPI3 == TRUE case 3: - // spiStop(&SPID3); - SPI3_PAL.Configuration = NULL; - // spiReleaseBus(&SPID4); + SPIDRV_DeInit(SPI3_PAL.Handle); + + // free memory + platform_free(&SPI3_PAL.Handle->initData); + platform_free(SPI3_PAL.Handle); + + SPI3_PAL.Handle = NULL; + break; #endif #if GECKO_USE_SPI4 == TRUE case 4: - // spiStop(&SPID5); - SPI4_PAL.Configuration = NULL; - // spiReleaseBus(&SPID5); + SPIDRV_DeInit(SPI3_PAL.Handle); + + // free memory + platform_free(&SPI3_PAL.Handle->initData); + platform_free(SPI3_PAL.Handle); + + SPI3_PAL.Handle = NULL; + break; #endif #if GECKO_USE_SPI5 == TRUE case 5: + SPIDRV_DeInit(SPI5_PAL.Handle); + // free memory - platform_free(SPI5_PAL.Configuration); + platform_free(&SPI5_PAL.Handle->initData); + platform_free(SPI5_PAL.Handle); + + SPI5_PAL.Handle = NULL; - // clears configuration - SPI5_PAL.Configuration = NULL; break; #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index bc1bf919c0..748d4a24c2 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -81,6 +81,9 @@ struct NF_PAL_SPI uint8_t *ReadBuffer; uint16_t ReadSize; + + // -1 = Chip Select is not handled | >0 Chip Select is to be controlled with this GPIO + int32_t ChipSelect; }; //////////////////////////////////////////// From af1aa196767c6af0a2447664df38a198ba7b74e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 9 Jul 2022 15:29:17 +0100 Subject: [PATCH 065/572] Fix passing SPI configurations --- .../SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index de2e11fde5..73f04c3656 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -187,12 +187,10 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) // Give a complete low-level SPI configuration from passed SPI_DEVICE_CONFIGURATION void GetSPIConfig(const SPI_DEVICE_CONFIGURATION &config, SPIDRV_Init_t *spiDrivInit) { - // SPI mode - // matches SPIDRV_ClockMode_t + // SPI mode (matches SPIDRV_ClockMode_t) spiDrivInit->clockMode = config.Spi_Mode; - - // baud rate spiDrivInit->bitRate = config.Clock_RateHz; + spiDrivInit->frameLength = config.MD16bits ? 16 : 8; // Sets the order of bytes transmission : MSB first or LSB first if (config.DataOrder16 == DataBitOrder_LSB) @@ -559,7 +557,6 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon { return false; } - // allocate memory for the SPIDRV_Init_t SPIDRV_Init_t *initSpinConfig = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); // sanity check allocation From 3188b2cc94835e7a1a8be20463135f241e332d15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 9 Jul 2022 15:30:43 +0100 Subject: [PATCH 066/572] Fix configuring GPIOs for SPI --- .../target_system_device_spi_config.cpp | 42 ++++--------------- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 6 ++- .../sys_dev_spi_native_target.h | 11 +---- 3 files changed, 12 insertions(+), 47 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp index d0d4ee81fa..2edc671816 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -9,40 +9,12 @@ // SPI1 // ////////// -// Note on SL_STK3701A SPI1 connects to LCD-TFT Display +// Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display -// pin configuration for SPI1 on GPIOA AF5 -// port for SPI1_SCK is: PC15 -// port for SPI1_MISO is: Not used -// port for SPI1_MOSI is: PC14 -// CS: PC14 +// pin configuration for SPI1 (EMC encoded "port location") +// SPI1_MOSI in PC14: 6 +// SPI1_MISO: -1 +// SPI1_SCK in PC15: 3 +// CS: PC14 (not used in SPI configuration) -SPI_CONFIG_PINS(1, gpioPortC, 15, 0, -1, gpioPortC, 14, 0) - -////////// -// SPI2 // -////////// - -// Note on ST_B_L457EIOT01A SPI2 connects to PMOD port (with defaault solder jumper settings) - -// pin configuration for SPI2 on GPIOD AF5 -// port for SPI2_SCK is: GPIOD_1 PMOD-SPI2_SCK -// port for SPI2_MISO is: GPIOD_3 PMOD-UART2_CTS/SPI2_MISO -// port for SPI2_MOSI is: GPIOD_4 PMOD-UART2_RTS/SPI2_MOSI - -// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -// SPI_CONFIG_PINS(2, GPIOD, 1, GPIOD, 3, GPIOD, 4, 5) - -////////// -// SPI3 // -////////// - -// Note on ST_B_L457EIOT01A SPI3 connects to Bluetooth SPBTLE-RF module - -// pin configuration for SPI3 on GPIOD AF5 -// port for SPI3_SCK is: GPIOD_10 INTERNAL-SPI3_SCK -// port for SPI3_MISO is: GPIOD_11 INTERNAL-SPI3_MISO -// port for SPI3_MOSI is: GPIOD_12 INTERNAL-SPI3_MOSI - -// GPIO alternate pin function is 5 (see alternate function mapping table in device datasheet) -// SPI_CONFIG_PINS(3, GPIOC, 10, GPIOC, 11, GPIOC, 12, 5) +SPI_CONFIG_PINS(1, 6, -1, 3) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 73f04c3656..b9029e7c59 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -459,6 +459,10 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon EUSART_TypeDef *usart = NULL; #endif + // create SPI init struct with the defaults: + // ports and pins with "invalid" values + // always MASTER mode + // we'll be controlling CS programmatically SPIDRV_Init_t spiInit = { NULL, #if defined(_USART_ROUTELOC0_MASK) @@ -481,11 +485,9 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon 0, 0, 0, - // always MASTER mode spidrvMaster, 0, 0, - // we'll be controlling CS spidrvCsControlApplication, spidrvSlaveStartImmediate }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 748d4a24c2..b81d938e6a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -113,15 +113,7 @@ extern NF_PAL_SPI SPI5_PAL; // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations -#define SPI_CONFIG_PINS( \ - num, \ - port_location_mosi, \ - port_location_miso, \ - port_location_clk, \ - pin_mosi, \ - pin_miso, \ - pin_clk, \ - port_location) \ +#define SPI_CONFIG_PINS(num, port_location_mosi, port_location_miso, port_location_clk) \ \ void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit) \ { \ @@ -133,7 +125,6 @@ extern NF_PAL_SPI SPI5_PAL; } \ if (spiDeviceConfig.DeviceChipSelect >= 0) \ { \ - spiInit.portLocationCs = GPIO_PORT(spiDeviceConfig.DeviceChipSelect); \ if (spiDeviceConfig.ChipSelectActive) \ { \ } \ From 6862cb9958ccb770f8aaa27ed2d1a7d023762a9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 11 Jul 2022 17:08:53 +0100 Subject: [PATCH 067/572] Add Skyworks I2C API - Add native implementation. - Remove standard I2C API from build. --- ...kyworksInc.NanoFramework.Devices.I2c.cmake | 52 ++ CMake/Modules/FindNF_NativeAssemblies.cmake | 1 + CMakePresets.json | 3 +- .../com_sky_nf_dev_i2c_native.cpp | 34 + .../com_sky_nf_dev_i2c_native.h | 54 ++ ...p => target_com_sky_nf_dev_i2c_config.cpp} | 2 +- .../target_com_sky_nf_dev_i2c_config.h | 3 + .../target_system_device_i2c_config.h | 6 - ...ksInc_NanoFramework_Devices_I2c_I2cBus.cpp | 684 ++++++++++++++++++ .../com_sky_nf_dev_i2c_native_target.h | 88 +++ .../nano_sl_i2cspm.c | 158 ++++ 11 files changed, 1077 insertions(+), 8 deletions(-) create mode 100644 CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake create mode 100644 src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp create mode 100644 src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h rename targets/AzureRTOS/SiliconLabs/SL_STK3701A/{target_system_device_i2c_config.cpp => target_com_sky_nf_dev_i2c_config.cpp} (93%) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake new file mode 100644 index 0000000000..938c7800db --- /dev/null +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake @@ -0,0 +1,52 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Com.SkyworksInc.NanoFramework.Devices.I2c) + + +# set include directories +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Core) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/HAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c) + +# source files +set(Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS + + # nano_sl_i2cspm.c + + com_sky_nf_dev_i2c_native.cpp + com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp + + target_com_sky_nf_dev_i2c_config.cpp +) + +foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS}) + + set(Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + #if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE}") + #endif() + + list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_SOURCES ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Com.SkyworksInc.NanoFramework.Devices.I2c DEFAULT_MSG Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS Com.SkyworksInc.NanoFramework.Devices.I2c_SOURCES) diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index afdfea9f08..5d30c1406d 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -23,6 +23,7 @@ option(API_System.Device.Adc "option for System.Device.Adc AP option(API_System.Device.Dac "option for System.Device.Dac API") option(API_System.Device.Gpio "option for System.Device.Gpio API") option(API_System.Device.I2c "option for System.Device.I2c API") +option(API_Com.SkyworksInc.NanoFramework.Devices.I2c "option for Skyworks I2C API") option(API_System.Device.Pwm "option for System.Device.Pwm API") option(API_System.IO.Ports "option for System.IO.Ports API") option(API_System.Device.Spi "option for System.Device.Spi API") diff --git a/CMakePresets.json b/CMakePresets.json index 21a858e9ca..71dce5c915 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -293,7 +293,8 @@ "API_Hardware.Stm32": "OFF", "API_System.Device.Gpio": "ON", "API_System.Device.Spi": "ON", - "API_System.Device.I2c": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp new file mode 100644 index 0000000000..6eadd9f0c5 --- /dev/null +++ b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp @@ -0,0 +1,34 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_i2c_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus::NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_I2c = +{ + "Com.SkyworksInc.NanoFramework.Devices.I2c", + 0xF6A356D7, + method_lookup, + { 1, 0, 0, 0 } +}; + +// clang-format on diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h new file mode 100644 index 0000000000..aa55925633 --- /dev/null +++ b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h @@ -0,0 +1,54 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef _COM_SKY_NF_DEV_I2C_NATIVE_H_ +#define _COM_SKY_NF_DEV_I2C_NATIVE_H_ + +#include +#include +#include +#include + +typedef enum __nfpack I2cBusSpeed +{ + I2cBusSpeed_StandardMode = 0, + I2cBusSpeed_FastMode = 1, +} I2cBusSpeed; + +typedef enum __nfpack I2cTransferStatus +{ + I2cTransferStatus_UnknownError = 0, + I2cTransferStatus_ClockStretchTimeout = 1, + I2cTransferStatus_PartialTransfer = 2, + I2cTransferStatus_SlaveAddressNotAcknowledged = 3, +} I2cTransferStatus; + +struct Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus +{ + static const int FIELD_STATIC___busSpeed = 0; + + static const int FIELD___syncLock = 1; + static const int FIELD___buffer = 2; + + NANOCLR_NATIVE_DECLARE(NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte); + + //--// +}; + +struct Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cException +{ + static const int FIELD___bytesTransferred = 5; + static const int FIELD___status = 6; + + //--// +}; + +struct Library_com_sky_nf_dev_i2c_native_ThisAssembly +{ + static const int FIELD_STATIC__GitCommitDate = 1; + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_I2c; + +#endif //_COM_SKY_NF_DEV_I2C_NATIVE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.cpp similarity index 93% rename from targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.cpp index 2914cfa6c8..b167de77ff 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.cpp @@ -3,7 +3,7 @@ // See LICENSE file in the project root for full license information. // -#include +#include ////////// // I2C2 // diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..85223e2e09 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,3 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h deleted file mode 100644 index 847fb55566..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h +++ /dev/null @@ -1,6 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#define GECKO_USE_I2C2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp new file mode 100644 index 0000000000..94a762365c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -0,0 +1,684 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_i2c_native_target.h" + +typedef Library_corlib_native_System_SpanByte SpanByte; +typedef Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cException I2cException; + +//////////////////////////////////////////// +// declaration of the the I2C PAL structs // +//////////////////////////////////////////// +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +NF_PAL_I2C I2C0_PAL; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +NF_PAL_I2C I2C1_PAL; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +NF_PAL_I2C I2C2_PAL; +#endif + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +uint8_t I2C0_DeviceCounter = 0; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +uint8_t I2C1_DeviceCounter = 0; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +uint8_t I2C2_DeviceCounter = 0; +#endif + +// estimate the time required to perform the I2C transaction +bool IsLongRunningOperation( + uint16_t writeSize, + uint16_t readSize, + float byteTime, + uint32_t &estimatedDurationMiliseconds) +{ + // add an extra byte to account for the address + estimatedDurationMiliseconds = byteTime * (writeSize + readSize + 1); + + if (estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +// ThreadX I2C Working thread +static void I2CWorkingThread_entry(uint32_t arg) +{ + NF_PAL_I2C *palI2c = (NF_PAL_I2C *)arg; + I2C_TransferSeq_TypeDef i2cTransfer; + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + i2cTransfer.flags = I2C_FLAG_WRITE_READ; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = palI2c->ReadBuffer; + i2cTransfer.buf[1].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + i2cTransfer.flags = I2C_FLAG_WRITE; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + // this is a Read only transaction + i2cTransfer.flags = I2C_FLAG_READ; + i2cTransfer.buf[0].data = palI2c->ReadBuffer; + i2cTransfer.buf[0].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + palI2c->TransactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + } + + // fire event for I2C transaction complete + Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); + + // terminate this thread + tx_thread_terminate(palI2c->WorkingThread); +} + +HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2c) +{ + NANOCLR_HEADER(); + + I2CSPM_Init_TypeDef i2cInit = { + NULL, + 0, + 0, + 0, + 0, +#if defined(_SILICON_LABS_32B_SERIES_0) + 0, +#elif defined(_SILICON_LABS_32B_SERIES_1) + 0, + 0, +#endif + 0, + I2C_FREQ_STANDARD_MAX, + i2cClockHLRStandard, + }; + + // config GPIO pins used by the I2C peripheral + // init the PAL struct for this I2C bus and assign the respective driver + // all this occurs if not already done + // why do we need to check if this is already done? because several I2cDevice objects can be created associated to + // the same bus just using different addresses + switch (busIndex) + { + + //////////////////////////////////// + // Gecko I2C bus index is 0 based // + //////////////////////////////////// + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 1: + if (I2C0_PAL.Configuration == NULL) + { + I2C0_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C1_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C0_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C0(); + + I2C0_PAL.Configuration->port = I2C0; + palI2c = I2C1_PAL; + + // increase device counter + I2C0_DeviceCounter++; + } + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 2: + if (I2C1_PAL.Configuration == NULL) + { + I2C1_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C1_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C1_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C1(); + + I2C1_PAL.Configuration->port = I2C1; + palI2c = I2C1_PAL; + + // increase device counter + I2C1_DeviceCounter++; + } + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 3: + if (I2C2_PAL.Configuration == NULL) + { + I2C2_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); + + if (I2C2_PAL.Configuration == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // copy init struct + memcpy(I2C2_PAL.Configuration, &i2cInit, sizeof(I2CSPM_Init_TypeDef)); + + ConfigPins_I2C2(); + + I2C2_PAL.Configuration->port = I2C2; + palI2c = &I2C2_PAL; + + // increase device counter + I2C2_DeviceCounter++; + } + + break; +#endif + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Get a general low-level I2C configuration, depending on user's managed parameters + if (busSpeed == I2cBusSpeed_StandardMode) + { + palI2c->Configuration->i2cMaxFreq = I2C_FREQ_STANDARD_MAX; + palI2c->Configuration->i2cClhr = i2cClockHLRStandard; + } + else + { + palI2c->Configuration->i2cMaxFreq = I2C_FREQ_FAST_MAX; + palI2c->Configuration->i2cClhr = i2cClockHLRAsymetric; + } + + I2CSPM_Init(palI2c->Configuration); + + // compute rough estimate on the time to tx/rx a byte (in milliseconds) + if (busSpeed == I2cBusSpeed_StandardMode) + { + // 100kbit/s: this is roughly 0.10ms per byte, give or take + palI2c->ByteTime = 0.1; + } + else + { + // 400kbit/s: this is roughly 0.02ms per byte, give or take + palI2c->ByteTime = 0.02; + } + + // clear pointer to working thread + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + + NANOCLR_NOCLEANUP(); +} + +HRESULT DisposeI2c(uint8_t busIndex, NF_PAL_I2C *&palI2c) +{ + NANOCLR_HEADER(); + + // get the driver for the I2C bus + // Gecko I2C bus index is 0 based + switch (busIndex) + { + //////////////////////////////////// + // Gecko I2C bus index is 0 based // + //////////////////////////////////// + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 1: + palI2c = &I2C0_PAL; + + // free memory + platform_free(I2C0_PAL.Configuration); + + // clears configuration + I2C0_PAL.Configuration = NULL; + + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 2: + // free memory + platform_free(I2C1_PAL.Configuration); + + // clears configuration + I2C1_PAL.Configuration = NULL; + + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 3: + // free memory + platform_free(I2C2_PAL.Configuration); + + // clears configuration + I2C2_PAL.Configuration = NULL; + + break; +#endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // stop working thread, if it's running + if (palI2c->WorkingThread != NULL) + { + // delete thread + tx_thread_delete(palI2c->WorkingThread); + + // free stack memory + platform_free(palI2c->WorkingThreadStack); + + // clear pointers + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + } + + NANOCLR_NOCLEANUP(); +} + +static HRESULT ThrowOnError(CLR_RT_StackFrame &stack, I2C_TransferReturn_TypeDef transactionResult, int bytesTransfered) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index i2cExceptionTypeDef; + CLR_RT_HeapBlock *hbObj; + + CLR_RT_HeapBlock &res = stack.m_owningThread->m_currentException; + + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("I2cException", "Com.SkyworksInc.NanoFramework.Devices.I2c", i2cExceptionTypeDef); + + if ((Library_corlib_native_System_Exception::CreateInstance(res, i2cExceptionTypeDef, CLR_E_FAIL, &stack)) == S_OK) + { + // dereference the exception object in order to reach its fields + hbObj = res.Dereference(); + + // figure out what was the error and set the status field + switch (transactionResult) + { + case i2cTransferNack: + hbObj[I2cException::FIELD___status].SetInteger( + (CLR_UINT32)I2cTransferStatus_SlaveAddressNotAcknowledged); + break; + + case i2cTransferBusErr: + case i2cTransferArbLost: + case i2cTransferUsageFault: + case i2cTransferSwFault: + hbObj[I2cException::FIELD___status].SetInteger((CLR_UINT32)I2cTransferStatus_ClockStretchTimeout); + break; + + default: + hbObj[I2cException::FIELD___status].SetInteger((CLR_UINT32)I2cTransferStatus_UnknownError); + + // set the bytes transferred field + hbObj[I2cException::FIELD___bytesTransferred].SetInteger(bytesTransfered); + } + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +static HRESULT NativeTransmit(uint8_t busIndex, NF_PAL_I2C *&palI2c, CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + { + bool isLongRunningOperation = false; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + CLR_RT_HeapBlock *writeSpanByte; + CLR_RT_HeapBlock *readSpanByte; + CLR_RT_HeapBlock_Array *writeBuffer = NULL; + CLR_RT_HeapBlock_Array *readBuffer = NULL; + int readOffset = 0; + int writeOffset = 0; + I2C_TransferSeq_TypeDef i2cTransfer; + I2C_TransferReturn_TypeDef transactionResult = i2cTransferInProgress; + + // get the driver for the I2C bus + switch (busIndex) + { + //////////////////////////////////// + // Gecko I2C bus index is 0 based // + //////////////////////////////////// + +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) + case 1: + palI2c = &I2C0_PAL; + break; +#endif + +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) + case 2: + palI2c = &I2C1_PAL; + break; +#endif + +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) + case 3: + palI2c = &I2C2_PAL; + break; +#endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // dereference the write and read SpanByte from the arguments + writeSpanByte = stack.Arg3().Dereference(); + + if (writeSpanByte != NULL) + { + // get buffer + writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (writeBuffer != NULL) + { + // Get the write offset, only the elements defined by the span must be written, not the whole array + writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as write size, only the elements defined by the span must be written + palI2c->WriteSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + } + } + + if (writeBuffer == NULL) + { + // nothing to write, have to zero this + palI2c->WriteSize = 0; + } + + readSpanByte = stack.Arg4().Dereference(); + + if (readSpanByte != NULL) + { + // get buffer + readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (readBuffer != NULL) + { + // Get the read offset, only the elements defined by the span must be read, not the whole array + readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as read size, only the elements defined by the span must be read + palI2c->ReadSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + } + } + + if (readBuffer == NULL) + { + // nothing to read, have to zero this + palI2c->ReadSize = 0; + } + + // check if this is a long running operation + isLongRunningOperation = IsLongRunningOperation( + palI2c->WriteSize, + palI2c->ReadSize, + palI2c->ByteTime, + (uint32_t &)estimatedDurationMiliseconds); + + if (isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in + // milliseconds this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer(*writeBuffer); + CLR_RT_ProtectFromGC gcReadBuffer(*readBuffer); + } + + // this is going to be used to check for the right event in case of simultaneous I2C transaction + if (!isLongRunningOperation || stack.m_customState == 1) + { + + // get slave address from connection settings field + i2cTransfer.addr = (uint16_t)stack.Arg2().NumericByRef().s4 << 1; + + if (writeBuffer != NULL) + { + // grab the pointer to the array by starting and the offset specified in the span + palI2c->WriteBuffer = (uint8_t *)writeBuffer->GetElement(writeOffset); + } + + if (readBuffer != NULL) + { + // grab the pointer to the array by starting and the offset specified in the span + palI2c->ReadBuffer = (uint8_t *)readBuffer->GetElement(readOffset); + } + } + + if (isLongRunningOperation) + { + // this is a long running operation and hasn't started yet + // perform I2C transaction using driver's ASYNC API which is launching a thread to perform it + if (stack.m_customState == 1) + { + // spawn working thread to perform the I2C transaction + + // 1. allocate memory for I2C thread + palI2c->WorkingThreadStack = (uint32_t *)platform_malloc(I2C_THREAD_STACK_SIZE); + + if (palI2c->WorkingThreadStack == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // 2. create thread + uint16_t status = tx_thread_create( + palI2c->WorkingThread, +#if !defined(BUILD_RTM) + (CHAR *)"I2C Thread", +#else + NULL, +#endif + I2CWorkingThread_entry, + (uint32_t)palI2c, + palI2c->WorkingThreadStack, + I2C_THREAD_STACK_SIZE, + I2C_THREAD_PRIORITY, + I2C_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + else + { + // this is NOT a long running operation + // perform I2C transaction + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + i2cTransfer.flags = I2C_FLAG_WRITE_READ; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + i2cTransfer.buf[1].data = palI2c->ReadBuffer; + i2cTransfer.buf[1].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + i2cTransfer.flags = I2C_FLAG_WRITE; + + i2cTransfer.buf[0].data = palI2c->WriteBuffer; + i2cTransfer.buf[0].len = palI2c->WriteSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + else + { + // this is a Read only transaction + i2cTransfer.flags = I2C_FLAG_READ; + i2cTransfer.buf[0].data = palI2c->ReadBuffer; + i2cTransfer.buf[0].len = palI2c->ReadSize; + + // Perform the transfer and return status from the transfer + transactionResult = I2CSPM_Transfer(palI2c->Configuration->port, &i2cTransfer); + } + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + if (palI2c->WorkingThread->tx_thread_state == TX_TERMINATED) + { + // I2C working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_I2cMaster, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + if (eventResult || !isLongRunningOperation) + { + // event occurred + // OR this is NOT a long running operation + + if (isLongRunningOperation) + { + // get transaction result from I2C struct + transactionResult = palI2c->TransactionResult; + + // delete thread + tx_thread_delete(palI2c->WorkingThread); + + // free stack memory + platform_free(palI2c->WorkingThreadStack); + + // clear pointers + palI2c->WorkingThread = NULL; + palI2c->WorkingThreadStack = NULL; + } + + // get the result from the working thread execution + if (transactionResult != i2cTransferDone) + { + + NANOCLR_CHECK_HRESULT(ThrowOnError(stack, transactionResult, palI2c->WriteSize + palI2c->ReadSize)); + } + else + { + // successful transaction + // set the result field + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus:: + NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t busIndex; + I2cBusSpeed busSpeed; + NF_PAL_I2C *palI2c = NULL; + CLR_RT_HeapBlock_Array *busSpeedCollection = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + busIndex = (uint8_t)stack.Arg2().NumericByRef().s4; + + // get a pointer to the managed I2C connectionSettings object instance + busSpeedCollection = (CLR_RT_HeapBlock_Array *)pThis[FIELD_STATIC___busSpeed].DereferenceArray(); + + busSpeed = (I2cBusSpeed)*busSpeedCollection->GetElement(busIndex); + + // init I2C bus + NANOCLR_CHECK_HRESULT(InitI2c(busIndex, busSpeed, palI2c)); + + // perform transfer + // dereference the write and read SpanByte from the arguments + NANOCLR_CHECK_HRESULT(NativeTransmit(busIndex, palI2c, stack)); + + // dispose I2C bus + NANOCLR_CHECK_HRESULT(DisposeI2c(busIndex, palI2c)); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h new file mode 100644 index 0000000000..22e67c93ac --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_target.h @@ -0,0 +1,88 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef COM_SKY_NF_DEV_I2C_NATIVE_TARGET_H +#define COM_SKY_NF_DEV_I2C_NATIVE_TARGET_H + +#include +#include + +#include +#include +#include +#include + +// receiver thread +#define I2C_THREAD_STACK_SIZE 256 +#define I2C_THREAD_PRIORITY 5 + +// set missing defines +#ifndef GECKO_USE_I2C0 +#define GECKO_USE_I2C0 FALSE +#endif +#ifndef GECKO_USE_I2C1 +#define GECKO_USE_I2C1 FALSE +#endif +#ifndef GECKO_USE_I2C2 +#define GECKO_USE_I2C2 FALSE +#endif + +// struct representing the I2C +typedef struct NF_PAL_I2C +{ + I2CSPM_Init_TypeDef *Configuration; + TX_THREAD *WorkingThread; + uint32_t *WorkingThreadStack; + I2C_TransferReturn_TypeDef TransactionResult; + uint16_t Address; + float ByteTime; + + uint8_t *WriteBuffer; + uint8_t WriteSize; + + uint8_t *ReadBuffer; + uint8_t ReadSize; +} NF_PAL_I2C; + +//////////////////////////////////////////// +// declaration of the the I2C PAL structs // +//////////////////////////////////////////// +#if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) +extern NF_PAL_I2C I2C0_PAL; +#endif +#if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) +extern NF_PAL_I2C I2C1_PAL; +#endif +#if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) +extern NF_PAL_I2C I2C2_PAL; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + +// the following macro defines a function that configures the GPIO pins for a Gecko I2C peripheral +// it gets called in the System_Device_I2c_I2cDevice::NativeInit function +// this is required because the I2C peripherals can use multiple GPIO configuration combinations +#define I2C_CONFIG_PINS(num, gpio_port_scl, gpio_port_sda, scl_pin, sda_pin, scl_port_location, sda_port_location) \ + void ConfigPins_I2C##num() \ + { \ + I2C##num##_PAL.Configuration->sclPort = gpio_port_scl; \ + I2C##num##_PAL.Configuration->sdaPort = gpio_port_sda; \ + I2C##num##_PAL.Configuration->sclPin = scl_pin; \ + I2C##num##_PAL.Configuration->sdaPin = sda_pin; \ + I2C##num##_PAL.Configuration->portLocationScl = scl_port_location; \ + I2C##num##_PAL.Configuration->portLocationSda = sda_port_location; \ + } + +#else +#error \ + "Only _SILICON_LABS_32B_SERIES_1 is supported at this time. To add support for other series declaration above has to be updated" +#endif + +////////////////////////////////////////////////////////////////////////////////////////////// +// when an I2C is defined the declarations below will have the real function/configuration // +// in the target folder @ target_windows_devices_i2c_config.cpp // +////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_I2C0(); +void ConfigPins_I2C1(); +void ConfigPins_I2C2(); + +#endif // COM_SKY_NF_DEV_I2C_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c new file mode 100644 index 0000000000..65a575de4d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/nano_sl_i2cspm.c @@ -0,0 +1,158 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include +#include "em_cmu.h" +#include "em_gpio.h" +#include "sl_assert.h" +#include "sl_i2cspm.h" +#include "sl_udelay.h" + +#include + +/* transfer timeout (how many polls) */ +#ifndef I2CSPM_TRANSFER_TIMEOUT +#define I2CSPM_TRANSFER_TIMEOUT 300 +#endif + +/* SCL hold time (in initialization function) in microseconds */ +#ifndef SL_I2CSPM_SCL_HOLD_TIME_US +#define SL_I2CSPM_SCL_HOLD_TIME_US 100 +#endif + +/******************************************************************************* + * Initalize I2C peripheral + ******************************************************************************/ +void I2CSPM_Init(I2CSPM_Init_TypeDef *init) +{ + int i; + CMU_Clock_TypeDef i2cClock; + I2C_Init_TypeDef i2cInit; + + EFM_ASSERT(init != NULL); + +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + + /* Select I2C peripheral clock */ + if (false) + { +#if defined(I2C0) + } + else if (init->port == I2C0) + { + i2cClock = cmuClock_I2C0; +#endif +#if defined(I2C1) + } + else if (init->port == I2C1) + { + i2cClock = cmuClock_I2C1; +#endif +#if defined(I2C2) + } + else if (init->port == I2C2) + { + i2cClock = cmuClock_I2C2; +#endif + } + else + { + /* I2C clock is not defined */ + EFM_ASSERT(false); + return; + } + CMU_ClockEnable(i2cClock, true); + + /* Output value must be set to 1 to not drive lines low. Set + SCL first, to ensure it is high before changing SDA. */ + GPIO_PinModeSet(init->sclPort, init->sclPin, gpioModeWiredAndPullUp, 1); + GPIO_PinModeSet(init->sdaPort, init->sdaPin, gpioModeWiredAndPullUp, 1); + + /* In some situations, after a reset during an I2C transfer, the slave + device may be left in an unknown state. Send 9 clock pulses to + set slave in a defined state. */ + for (i = 0; i < 9; i++) + { + GPIO_PinOutClear(init->sclPort, init->sclPin); + sl_udelay_wait(SL_I2CSPM_SCL_HOLD_TIME_US); + GPIO_PinOutSet(init->sclPort, init->sclPin); + sl_udelay_wait(SL_I2CSPM_SCL_HOLD_TIME_US); + } + + /* Enable pins and set location */ +#if defined(_I2C_ROUTEPEN_MASK) + init->port->ROUTEPEN = I2C_ROUTEPEN_SDAPEN | I2C_ROUTEPEN_SCLPEN; + init->port->ROUTELOC0 = + (uint32_t)((init->portLocationSda << _I2C_ROUTELOC0_SDALOC_SHIFT) | (init->portLocationScl << _I2C_ROUTELOC0_SCLLOC_SHIFT)); +#elif defined(_I2C_ROUTE_MASK) + init->port->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (init->portLocation << _I2C_ROUTE_LOCATION_SHIFT); +#else +#if defined(I2C0) + if (init->port == I2C0) + { + GPIO->I2CROUTE[0].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[0].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[0].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#if defined(I2C1) + if (init->port == I2C1) + { + GPIO->I2CROUTE[1].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[1].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[1].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#if defined(I2C2) + if (init->port == I2C2) + { + GPIO->I2CROUTE[2].ROUTEEN = GPIO_I2C_ROUTEEN_SDAPEN | GPIO_I2C_ROUTEEN_SCLPEN; + GPIO->I2CROUTE[2].SCLROUTE = + (uint32_t)((init->sclPin << _GPIO_I2C_SCLROUTE_PIN_SHIFT) | (init->sclPort << _GPIO_I2C_SCLROUTE_PORT_SHIFT)); + GPIO->I2CROUTE[2].SDAROUTE = + (uint32_t)((init->sdaPin << _GPIO_I2C_SDAROUTE_PIN_SHIFT) | (init->sdaPort << _GPIO_I2C_SDAROUTE_PORT_SHIFT)); + } +#endif +#endif + + /* Set emlib init parameters */ + i2cInit.enable = true; + i2cInit.master = true; /* master mode only */ + i2cInit.freq = init->i2cMaxFreq; + i2cInit.refFreq = init->i2cRefFreq; + i2cInit.clhr = init->i2cClhr; + + I2C_Init(init->port, &i2cInit); +} + +/******************************************************************************* + * Perform I2C transfer + ******************************************************************************/ +I2C_TransferReturn_TypeDef I2CSPM_Transfer(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq) +{ + I2C_TransferReturn_TypeDef ret; + uint32_t timeout = I2CSPM_TRANSFER_TIMEOUT; + + // Do a polled transfer + ret = I2C_TransferInit(i2c, seq); + + while (ret == i2cTransferInProgress && timeout--) + { + + ret = I2C_Transfer(i2c); + + // allow other tasks to run + tx_thread_sleep(10); + } + + return ret; +} From a5a4bc7d10b99d7386871946952bf2323f38ff40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 11 Jul 2022 18:14:58 +0100 Subject: [PATCH 068/572] Add Skyworks SPI API --- ...kyworksInc.NanoFramework.Devices.Spi.cmake | 51 ++++++ CMake/Modules/FindNF_NativeAssemblies.cmake | 13 ++ CMakePresets.json | 3 +- .../com_sky_nf_dev_spi_native.cpp | 50 ++++++ .../com_sky_nf_dev_spi_native.h | 71 +++++++++ .../nanoHAL_Spi.h | 9 ++ ...p => target_com_sky_nf_dev_spi_config.cpp} | 2 +- ...g.h => target_com_sky_nf_dev_spi_config.h} | 0 ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 22 +++ .../com_sky_nf_dev_spi_native_target.h | 149 ++++++++++++++++++ 10 files changed, 368 insertions(+), 2 deletions(-) create mode 100644 CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake create mode 100644 src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp create mode 100644 src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h create mode 100644 src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h rename targets/AzureRTOS/SiliconLabs/SL_STK3701A/{target_system_device_spi_config.cpp => target_com_sky_nf_dev_spi_config.cpp} (90%) rename targets/AzureRTOS/SiliconLabs/SL_STK3701A/{target_system_device_spi_config.h => target_com_sky_nf_dev_spi_config.h} (100%) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake new file mode 100644 index 0000000000..4956660d1a --- /dev/null +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake @@ -0,0 +1,51 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Com.SkyworksInc.NanoFramework.Devices.Spi) + + +# set include directories +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Core) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/HAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi) + +# source files +set(Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS + + com_sky_nf_dev_spi_native.cpp + com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp + + target_com_sky_nf_dev_spi_config.cpp +) + +foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS}) + + set(Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${CMAKE_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + #if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE}") + #endif() + + list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_SOURCES ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Com.SkyworksInc.NanoFramework.Devices.Spi DEFAULT_MSG Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS Com.SkyworksInc.NanoFramework.Devices.Spi_SOURCES) diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index 5d30c1406d..a7586a4ca1 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -27,6 +27,7 @@ option(API_Com.SkyworksInc.NanoFramework.Devices.I2c "option f option(API_System.Device.Pwm "option for System.Device.Pwm API") option(API_System.IO.Ports "option for System.IO.Ports API") option(API_System.Device.Spi "option for System.Device.Spi API") +option(API_Com.SkyworksInc.NanoFramework.Devices.Spi "option for Skyworks SPI API") option(API_Windows.Storage "option for Windows.Storage") option(API_nanoFramework.Graphics "option for nanoFramework.Graphics") option(API_nanoFramework.Device.Bluetooth "option for nanoFramework.Device.Bluetooth") @@ -294,6 +295,12 @@ if(API_System.Device.I2c) PerformSettingsForApiEntry("System.Device.I2c") endif() +# Com.SkyworksInc.NanoFramework.Devices.I2c +if(API_Com.SkyworksInc.NanoFramework.Devices.I2c) + ##### API name here (doted name) + PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.I2c") +endif() + # System.Device.Pwm if(API_System.Device.Pwm) ##### API name here (doted name) @@ -306,6 +313,12 @@ if(API_System.IO.Ports) PerformSettingsForApiEntry("System.IO.Ports") endif() +# Com.SkyworksInc.NanoFramework.Devices.Spi +if(API_Com.SkyworksInc.NanoFramework.Devices.Spi) + ##### API name here (doted name) + PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.Spi") +endif() + # System.Device.Spi if(API_System.Device.Spi) ##### API name here (doted name) diff --git a/CMakePresets.json b/CMakePresets.json index 71dce5c915..f2d52b7837 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -292,7 +292,8 @@ "API_System.Math": "ON", "API_Hardware.Stm32": "OFF", "API_System.Device.Gpio": "ON", - "API_System.Device.Spi": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.Pwm": "OFF", diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp new file mode 100644 index 0000000000..0c74bd5f4b --- /dev/null +++ b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -0,0 +1,50 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_spi_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = +{ + "Com.SkyworksInc.NanoFramework.Devices.Spi", + 0x6E9C1C37, + method_lookup, + { 1, 0, 0, 0 } +}; + +// clang-format on diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h new file mode 100644 index 0000000000..435a63bab4 --- /dev/null +++ b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -0,0 +1,71 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef _COM_SKY_NF_DEV_SPI_NATIVE_H_ +#define _COM_SKY_NF_DEV_SPI_NATIVE_H_ + +#include +#include +#include +#include + +typedef enum __nfpack DataFlow +{ + DataFlow_MsbFirst = 0, + DataFlow_LsbFirst = 1, +} DataFlow; + +// moved to src\PAL\Include\CPU_SPI_decl.h for convenience +// typedef enum __nfpack SpiBusConfiguration +// { +// SpiBusConfiguration_FullDuplex = 0, +// SpiBusConfiguration_HalfDuplex = 1, +// SpiBusConfiguration_Simplex = 2, +// } SpiBusConfiguration; + +// moved to src\PAL\Include\CPU_SPI_decl.h for convenience +// typedef enum __nfpack SpiMode +// { +// SpiMode_Mode0 = 0, +// SpiMode_Mode1 = 1, +// SpiMode_Mode2 = 2, +// SpiMode_Mode3 = 3, +// } SpiMode; + +struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration +{ + static const int FIELD___csLine = 1; + static const int FIELD___clockFrequency = 2; + static const int FIELD___databitLength = 3; + static const int FIELD___spiMode = 4; + static const int FIELD___dataFlow = 5; + static const int FIELD___busConfiguration = 6; + + //--// + +}; + +struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus +{ + static const int FIELD_STATIC___busConnectionSettings = 0; + + static const int FIELD___syncLock = 1; + static const int FIELD___bufferSingleOperation = 2; + + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + + //--// + +}; + +struct Library_com_sky_nf_dev_spi_native_ThisAssembly +{ + static const int FIELD_STATIC__GitCommitDate = 1; + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi; + +#endif //_COM_SKY_NF_DEV_SPI_NATIVE_H_ diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h new file mode 100644 index 0000000000..5d568902fc --- /dev/null +++ b/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE SKYWORKS SPI IMPLEMENTATION IS NO USING CPU SPI // +/////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp similarity index 90% rename from targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp index 2edc671816..af8c25ab3d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp @@ -3,7 +3,7 @@ // See LICENSE file in the project root for full license information. // -#include +#include ////////// // SPI1 // diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp new file mode 100644 index 0000000000..92b2a499be --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -0,0 +1,22 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#include "com_sky_nf_dev_spi_native.h" + + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h new file mode 100644 index 0000000000..047c7a4a55 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h @@ -0,0 +1,149 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#ifndef COM_SKY_NF_DEV_SPI_NATIVE_TARGET_H +#define COM_SKY_NF_DEV_SPI_NATIVE_TARGET_H + +#include +#include +#include + +#include +#include + +#define SL_SPIDRV_EXP_BITRATE 1000000 + +// set missing defines +#if defined(USART0) +#ifndef GECKO_USE_SPI0 +#define GECKO_USE_SPI0 FALSE +#endif +#else +#define GECKO_USE_SPI0 FALSE +#endif + +#if defined(USART1) +#ifndef GECKO_USE_SPI1 +#define GECKO_USE_SPI1 FALSE +#endif +#else +#define GECKO_USE_SPI1 FALSE +#endif + +#if defined(USART2) +#ifndef GECKO_USE_SPI2 +#define GECKO_USE_SPI2 FALSE +#endif +#else +#define GECKO_USE_SPI2 FALSE +#endif + +#if defined(USART3) +#ifndef GECKO_USE_SPI3 +#define GECKO_USE_SPI3 FALSE +#endif +#else +#define GECKO_USE_SPI3 FALSE +#endif + +#if defined(USART4) +#ifndef GECKO_USE_SPI4 +#define GECKO_USE_SPI4 FALSE +#endif +#else +#define GECKO_USE_SPI4 FALSE +#endif + +#if defined(USART5) +#ifndef GECKO_USE_SPI5 +#define GECKO_USE_SPI5 FALSE +#endif +#else +#define GECKO_USE_SPI5 FALSE +#endif + +// struct representing the SPI bus +struct NF_PAL_SPI +{ + int BusIndex; + SPIDRV_Handle_t Handle; + SpiBusConfiguration BusConfiguration; + + SPI_Callback Callback; + + bool SequentialTxRx; + bool BufferIs16bits; + + uint8_t *WriteBuffer; + uint16_t WriteSize; + + uint8_t *ReadBuffer; + uint16_t ReadSize; + + // -1 = Chip Select is not handled | >0 Chip Select is to be controlled with this GPIO + int32_t ChipSelect; +}; + +//////////////////////////////////////////// +// declaration of the the SPI PAL structs // +//////////////////////////////////////////// +#if GECKO_USE_SPI0 == TRUE +extern NF_PAL_SPI SPI0_PAL; +#endif +#if GECKO_USE_SPI1 == TRUE +extern NF_PAL_SPI SPI1_PAL; +#endif +#if GECKO_USE_SPI2 == TRUE +extern NF_PAL_SPI SPI2_PAL; +#endif +#if GECKO_USE_SPI3 == TRUE +extern NF_PAL_SPI SPI3_PAL; +#endif +#if GECKO_USE_SPI4 == TRUE +extern NF_PAL_SPI SPI4_PAL; +#endif +#if GECKO_USE_SPI5 == TRUE +extern NF_PAL_SPI SPI5_PAL; +#endif + +#if defined(_USART_ROUTELOC0_MASK) + +// the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral +// it gets called in the System_Device_SPi_SPiDevice::NativeInit function +// this is required because the SPI peripherals can use multiple GPIO configuration combinations +#define SPI_CONFIG_PINS(num, port_location_mosi, port_location_miso, port_location_clk) \ + \ + void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit) \ + { \ + spiInit.portLocationTx = port_location_mosi; \ + spiInit.portLocationClk = port_location_clk; \ + if (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + { \ + spiInit.portLocationRx = port_location_miso; \ + } \ + if (spiDeviceConfig.DeviceChipSelect >= 0) \ + { \ + if (spiDeviceConfig.ChipSelectActive) \ + { \ + } \ + else \ + { \ + } \ + } \ + } + +#else +#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#endif + +////////////////////////////////////////////////////////////////////////////////////////////// +// when an SPI is defined the declarations below will have the real function/configuration // +// in the target folder @ target_windows_devices_spi_config.cpp // +////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); + +#endif // COM_SKY_NF_DEV_SPI_NATIVE_TARGET_H From 3890308ab89d93f2236be7c304ff4b3de4810c33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 00:40:53 +0100 Subject: [PATCH 069/572] Rework SPI driver to replace SPIDRV with UART API - Rework config pins. - Rework SPI PAL struc. - Rework SPI init, deinit and transfer. - Rework target configuration. --- .../target_system_device_spi_config.cpp | 8 +- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 190 ++++++++---------- .../sys_dev_spi_native_target.h | 59 ++++-- 3 files changed, 128 insertions(+), 129 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp index 2edc671816..9427e7c33b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -12,9 +12,9 @@ // Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display // pin configuration for SPI1 (EMC encoded "port location") -// SPI1_MOSI in PC14: 6 -// SPI1_MISO: -1 -// SPI1_SCK in PC15: 3 +// SPI1_MOSI in PC6, location 1 +// SPI1_MISO: (not used for LCD) +// SPI1_SCK in PC8, location 1 // CS: PC14 (not used in SPI configuration) -SPI_CONFIG_PINS(1, 6, -1, 3) +SPI_CONFIG_PINS(1, gpioPortC, 6, 1, 0, -1, -1, gpioPortC, 8, 1) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index b9029e7c59..20139dfcc0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -185,27 +185,36 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) } // Give a complete low-level SPI configuration from passed SPI_DEVICE_CONFIGURATION -void GetSPIConfig(const SPI_DEVICE_CONFIGURATION &config, SPIDRV_Init_t *spiDrivInit) +void GetSPIConfig(const SPI_DEVICE_CONFIGURATION &config, USART_InitSync_TypeDef *uartInit) { // SPI mode (matches SPIDRV_ClockMode_t) - spiDrivInit->clockMode = config.Spi_Mode; - spiDrivInit->bitRate = config.Clock_RateHz; - spiDrivInit->frameLength = config.MD16bits ? 16 : 8; + uartInit->baudrate = config.Clock_RateHz; - // Sets the order of bytes transmission : MSB first or LSB first - if (config.DataOrder16 == DataBitOrder_LSB) - { - spiDrivInit->bitOrder = spidrvBitOrderLsbFirst; - } - else + switch (config.Spi_Mode) { - spiDrivInit->bitOrder = spidrvBitOrderMsbFirst; + case SpiMode_Mode0: + uartInit->clockMode = usartClockMode0; + break; + + case SpiMode_Mode1: + uartInit->clockMode = usartClockMode1; + break; + + case SpiMode_Mode2: + uartInit->clockMode = usartClockMode2; + break; + + case SpiMode_Mode3: + uartInit->clockMode = usartClockMode3; + break; + + default: + ASSERT(false); + break; } - // TODO handle half duplex - // set bus configuration - // if (config.busConfiguration) - // } + // Sets the order of bytes transmission : MSB first or LSB first + uartInit->msbf = config.DataOrder16 == DataBitOrder_MSB; } // Performs a read/write operation on 8-bit word data. @@ -240,7 +249,9 @@ HRESULT CPU_SPI_nWrite_nRead( NANOCLR_HEADER(); { bool busConfigIsHalfDuplex; + NF_PAL_SPI *palSpi = (NF_PAL_SPI *)deviceHandle; + // If callback then use aync operation bool sync = (wrc.callback == 0); @@ -263,10 +274,8 @@ HRESULT CPU_SPI_nWrite_nRead( // === Setup the operation and init buffers === palSpi->BusIndex = sdev.Spi_Bus; - SPIDRV_SetFramelength(palSpi->Handle, wrc.Bits16ReadWrite ? 16 : 8); - // set bus config flag - busConfigIsHalfDuplex = palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex; + busConfigIsHalfDuplex = (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex); if (writeBuffer != NULL) { @@ -283,6 +292,9 @@ HRESULT CPU_SPI_nWrite_nRead( } } + palSpi->Usart->FRAME = + (palSpi->Usart->FRAME & ~_USART_FRAME_DATABITS_MASK) | wrc.Bits16ReadWrite ? usartDatabits16 : usartDatabits8; + // if CS is to be controlled by the driver, set the GPIO if (palSpi->ChipSelect >= 0) { @@ -450,46 +462,29 @@ HRESULT CPU_SPI_nWrite_nRead( bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) { NF_PAL_SPI *palSpi = NULL; - void (*configPinsHandler)(const struct SPI_DEVICE_CONFIGURATION &, struct SPIDRV_Init &) = NULL; + void (*configPinsHandler)(const struct SPI_DEVICE_CONFIGURATION &) = NULL; -#if defined(USART_PRESENT) - USART_TypeDef *usart = NULL; -#endif -#if defined(EUSART_PRESENT) - EUSART_TypeDef *usart = NULL; -#endif - - // create SPI init struct with the defaults: + // create USART init struct with the defaults: // ports and pins with "invalid" values // always MASTER mode // we'll be controlling CS programmatically - SPIDRV_Init_t spiInit = { - NULL, -#if defined(_USART_ROUTELOC0_MASK) - 0, - 0, + USART_InitSync_TypeDef configInit = { + usartDisable, 0, + 1000000, + usartDatabits8, + true, + false, + usartClockMode0, + false, 0, -#elif defined(_GPIO_USART_ROUTEEN_MASK) - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, -#else + false, + false, + false, +#if (_SILICON_LABS_32B_SERIES > 0) 0, + 0 #endif - 0, - 0, - 0, - spidrvMaster, - 0, - 0, - spidrvCsControlApplication, - spidrvSlaveStartImmediate }; // init the PAL struct for this SPI bus and assign the respective driver @@ -504,7 +499,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI0 == TRUE case 0: palSpi = &SPI0_PAL; - usart = USART0; + palSpi->Usart = USART0; configPinsHandler = &ConfigPins_SPI0; break; #endif @@ -512,36 +507,41 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI1 == TRUE case 1: palSpi = &SPI1_PAL; - usart = USART1; - configPinsHandler = ConfigPins_SPI1; + palSpi->Usart = USART1; + configPinsHandler = &ConfigPins_SPI1; break; #endif #if GECKO_USE_SPI2 == TRUE case 2: palSpi = &SPI2_PAL; - usart = USART2; + palSpi->Usart = USART2; + configPinsHandler = &ConfigPins_SPI2; + break; #endif #if GECKO_USE_SPI3 == TRUE case 3: palSpi = &SPI3_PAL; - usart = USART3; + palSpi->Usart = USART3; + configPinsHandler = &ConfigPins_SPI3; break; #endif #if GECKO_USE_SPI4 == TRUE case 4: palSpi = &SPI4_PAL; - usart = USART4; + palSpi->Usart = USART4; + configPinsHandler = &ConfigPins_SPI4; break; #endif #if GECKO_USE_SPI5 == TRUE case 5: palSpi = &SPI5_PAL; - usart = USART5; + palSpi->Usart = USART5; + configPinsHandler = &ConfigPins_SPI5; break; #endif @@ -550,41 +550,29 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon return false; } - if (palSpi->Handle == NULL) + if (palSpi->Configuration == NULL) { - // allocate memory for the SPIDRV_HandleData - palSpi->Handle = (SPIDRV_Handle_t)platform_malloc(sizeof(SPIDRV_HandleData_t)); - // sanity check allocation - if (palSpi->Handle == NULL) - { - return false; - } - // allocate memory for the SPIDRV_Init_t - SPIDRV_Init_t *initSpinConfig = (SPIDRV_Init_t *)platform_malloc(sizeof(SPIDRV_Init_t)); + // allocate memory for the USART_InitSync_TypeDef + palSpi->Configuration = (USART_InitSync_TypeDef *)platform_malloc(sizeof(USART_InitSync_TypeDef)); + // sanity check allocation - if (initSpinConfig == NULL) + if (palSpi->Configuration == NULL) { - // need to free this - platform_free(palSpi->Handle); - return false; } // copy init struct - memcpy(initSpinConfig, &spiInit, sizeof(SPIDRV_Init_t)); + memcpy(palSpi->Configuration, &configInit, sizeof(USART_InitSync_TypeDef)); - // set USART - initSpinConfig->port = usart; + // get the SPI configuration + GetSPIConfig(busConfiguration, palSpi->Configuration); - // call handler to configure pins - configPinsHandler(busConfiguration, *initSpinConfig); + USART_InitSync(palSpi->Usart, palSpi->Configuration); palSpi->ChipSelect = busConfiguration.DeviceChipSelect; - // get the SPI configuration - GetSPIConfig(busConfiguration, initSpinConfig); - - SPIDRV_Init(palSpi->Handle, initSpinConfig); + // call handler to configure pins + configPinsHandler(busConfiguration); } return true; @@ -601,78 +589,72 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) #if GECKO_USE_SPI0 == TRUE case 0: - SPIDRV_DeInit(SPI0_PAL.Handle); + USART_Reset(UART0); // free memory - platform_free(&SPI0_PAL.Handle->initData); - platform_free(SPI0_PAL.Handle); + platform_free(SPI0_PAL.Configuration); - SPI0_PAL.Handle = NULL; + SPI0_PAL.Configuration = NULL; break; #endif #if GECKO_USE_SPI1 == TRUE case 1: - SPIDRV_DeInit(SPI1_PAL.Handle); + USART_Reset(UART1); // free memory - platform_free(&SPI1_PAL.Handle->initData); - platform_free(SPI1_PAL.Handle); + platform_free(SPI1_PAL.Configuration); - SPI1_PAL.Handle = NULL; + SPI1_PAL.Configuration = NULL; break; #endif #if GECKO_USE_SPI2 == TRUE case 2: - SPIDRV_DeInit(SPI2_PAL.Handle); + USART_Reset(UART2); // free memory - platform_free(&SPI2_PAL.Handle->initData); - platform_free(SPI2_PAL.Handle); + platform_free(SPI2_PAL.Configuration); - SPI2_PAL.Handle = NULL; + SPI2_PAL.Configuration = NULL; break; #endif #if GECKO_USE_SPI3 == TRUE case 3: - SPIDRV_DeInit(SPI3_PAL.Handle); + USART_Reset(UART3); // free memory - platform_free(&SPI3_PAL.Handle->initData); - platform_free(SPI3_PAL.Handle); + platform_free(SPI3_PAL.Configuration); - SPI3_PAL.Handle = NULL; + SPI3_PAL.Configuration = NULL; break; #endif #if GECKO_USE_SPI4 == TRUE case 4: - SPIDRV_DeInit(SPI3_PAL.Handle); + USART_Reset(UART4); // free memory - platform_free(&SPI3_PAL.Handle->initData); - platform_free(SPI3_PAL.Handle); + platform_free(SPI4_PAL.Configuration); - SPI3_PAL.Handle = NULL; + SPI4_PAL.Configuration = NULL; break; #endif #if GECKO_USE_SPI5 == TRUE case 5: - SPIDRV_DeInit(SPI5_PAL.Handle); + USART_Reset(UART5); // free memory - platform_free(&SPI5_PAL.Handle->initData); - platform_free(SPI5_PAL.Handle); + platform_free(SPI5_PAL.Configuration); - SPI5_PAL.Handle = NULL; + SPI5_PAL.Configuration = NULL; break; #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index b81d938e6a..355334a9e1 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -11,7 +11,9 @@ #include #include -#include +#include +#include +#include #define SL_SPIDRV_EXP_BITRATE 1000000 @@ -68,7 +70,8 @@ struct NF_PAL_SPI { int BusIndex; - SPIDRV_Handle_t Handle; + USART_TypeDef *Usart; + USART_InitSync_TypeDef *Configuration; SpiBusConfiguration BusConfiguration; SPI_Callback Callback; @@ -113,25 +116,39 @@ extern NF_PAL_SPI SPI5_PAL; // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations -#define SPI_CONFIG_PINS(num, port_location_mosi, port_location_miso, port_location_clk) \ - \ - void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit) \ +#define SPI_CONFIG_PINS( \ + num, \ + gpio_port_sck, \ + sck_pin, \ + sck_port_location, \ + gpio_port_mosi, \ + mosi_pin, \ + mosi_port_location, \ + gpio_port_miso, \ + miso_pin, \ + miso_port_location) \ + void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig) \ { \ - spiInit.portLocationTx = port_location_mosi; \ - spiInit.portLocationClk = port_location_clk; \ + GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 1); \ + SPI##num##_PAL.Usart->ROUTELOC0 = \ + (SPI##num##_PAL.Usart->ROUTELOC0 & ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ + _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ + mosi_port_location | (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ if (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ { \ - spiInit.portLocationRx = port_location_miso; \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 1); \ + GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 1); \ + SPI##num##_PAL.Usart->ROUTELOC0 |= (miso_port_location << _USART_ROUTELOC0_RXLOC_SHIFT); \ } \ - if (spiDeviceConfig.DeviceChipSelect >= 0) \ + else \ { \ - if (spiDeviceConfig.ChipSelectActive) \ - { \ - } \ - else \ - { \ - } \ + SPI##num##_PAL.Usart->CTRL |= USART_CTRL_LOOPBK; \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ } \ + SPI##num##_PAL.Usart->ROUTEPEN = USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_CSPEN | USART_ROUTEPEN_TXPEN | \ + (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + ? USART_ROUTEPEN_RXPEN \ + : 0; \ } #else @@ -142,11 +159,11 @@ extern NF_PAL_SPI SPI5_PAL; // when an SPI is defined the declarations below will have the real function/configuration // // in the target folder @ target_windows_devices_spi_config.cpp // ////////////////////////////////////////////////////////////////////////////////////////////// -void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); +void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); #endif // SYS_DEV_SPI_NATIVE_TARGET_H From c8ee574c25faa1de0b01cb7c73ab9df89ad03be4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 15:14:56 +0100 Subject: [PATCH 070/572] Add nanoHardwareEvents - RTOS event group for hardware events. --- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 16 ++++++++-- .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 30 +++++++++++++------ 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index b915bd21c9..7540d92c82 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -16,6 +16,9 @@ #include // #include +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + // byte pool configuration and definitions #define DEFAULT_BYTE_POOL_SIZE 4096 TX_BYTE_POOL byte_pool_0; @@ -92,7 +95,7 @@ void tx_application_define(void *first_unused_memory) "Blink Thread", BlinkThread_entry, 0, - (uint8_t*)blinkThreadStack, + (uint8_t *)blinkThreadStack, BLINK_THREAD_STACK_SIZE, BLINK_THREAD_PRIORITY, BLINK_THREAD_PRIORITY, @@ -112,7 +115,7 @@ void tx_application_define(void *first_unused_memory) "Blink Thread1", BlinkThread1_entry, 0, - (uint8_t*)blinkThread1Stack, + (uint8_t *)blinkThread1Stack, BLINK_THREAD_STACK_SIZE, BLINK_THREAD_PRIORITY, BLINK_THREAD_PRIORITY, @@ -146,6 +149,15 @@ void tx_application_define(void *first_unused_memory) } } + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + // report successfull nanoBooter execution ReportSuccessfullNanoBooter(); } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index c5d17b0d25..d1511b71e3 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -18,7 +18,8 @@ #include // #include -// extern TX_EVENT_FLAGS_GROUP wpUartEvent; +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; extern CLR_SETTINGS clrSettings; // byte pool configuration and definitions @@ -50,7 +51,6 @@ TX_THREAD clrStartupThread; uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; extern void ClrStartupThread_entry(uint32_t parameter); - void BlinkThread_entry(uint32_t parameter) { (void)parameter; @@ -73,10 +73,10 @@ void tx_application_define(void *first_unused_memory) // start watchdog // Watchdog_Init(); -// #if (HAL_NF_USE_STM32_CRC == TRUE) -// // startup crc -// crcStart(NULL); -// #endif + // #if (HAL_NF_USE_STM32_CRC == TRUE) + // // startup crc + // crcStart(NULL); + // #endif #if (TRACE_TO_STDIO == TRUE) StdioPort_Init(); @@ -148,14 +148,22 @@ void tx_application_define(void *first_unused_memory) { } } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } } // Application entry point. int main(void) { - sl_service_init(); - sl_stack_init(); - sl_internal_app_init(); + // Initialize the board + sl_system_init(); // Configure LED0 as output GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1, gpioModePushPull, 0); @@ -164,6 +172,10 @@ int main(void) GPIO_PinModeSet(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN, gpioModeDisabled, 0); GPIO_PinModeSet(BSP_GPIO_LED1_PORT, BSP_GPIO_LED1_PIN, gpioModeDisabled, 0); + // enable display + GPIO_PinModeSet(BSP_DISP_ENABLE_PORT, BSP_DISP_ENABLE_PIN, gpioModePushPull, 0); + GPIO_PinOutSet(BSP_DISP_ENABLE_PORT, BSP_DISP_ENABLE_PIN); + // init boot clipboard InitBootClipboard(); From 12e1cf4af8a174a0ba7a01768c6c918177fca63f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 16:49:42 +0100 Subject: [PATCH 071/572] Fix path on template generator output - Affecting target_common and target_board. - Add new TARGET_BASE_LOCATION_BINARY. --- CMake/binutils.AzureRTOS.cmake | 8 ++++---- targets/AzureRTOS/CMakeLists.txt | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index d6ad1f072d..ce01032134 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -339,7 +339,7 @@ macro(nf_add_platform_include_directories target) if(${target} STREQUAL ${NANOBOOTER_PROJECT_NAME}) target_include_directories(${target}.elf PUBLIC - ${TARGET_AZURERTOS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_AZURERTOS_NANOBOOTER_INCLUDE_DIRS} ) endif() @@ -361,7 +361,7 @@ macro(nf_add_platform_sources target) # add header files with common OS definitions and board definitions configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in - ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}/target_common.h @ONLY) + ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_VENDOR}/${TARGET_BOARD}/target_common.h @ONLY) # sources common to both builds target_sources(${target}.elf PUBLIC @@ -389,7 +389,7 @@ macro(nf_add_platform_sources target) # add header file for board definition configure_file(${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in - ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}/nanoBooter/target_board.h @ONLY) + ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_VENDOR}/${TARGET_BOARD}/nanoBooter/target_board.h @ONLY) target_sources(${target}.elf PUBLIC @@ -406,7 +406,7 @@ macro(nf_add_platform_sources target) if(${target} STREQUAL ${NANOCLR_PROJECT_NAME}) configure_file(${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in - ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}/nanoCLR/target_board.h @ONLY) + ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_VENDOR}/${TARGET_BOARD}/nanoCLR/target_board.h @ONLY) target_sources(${target}.elf PUBLIC ${TARGET_AZURERTOS_NANOCLR_SOURCES} diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index 22ceff22b9..a0115a6dbd 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -423,6 +423,8 @@ else() endif() +set(TARGET_BASE_LOCATION_BINARY ${CMAKE_CURRENT_BINARY_DIR}/${TARGET_VENDOR}/${TARGET_BOARD}) + ############################## # AzureRTOS common directories add_subdirectory(_common) From 4e0b90e16023c0a3fd58bd3cbf4c1dd547a9309e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 16:50:38 +0100 Subject: [PATCH 072/572] Work CI-CD - Add missing path section for platforms with TARGET_VENDOR. ***NO_CI*** --- CMake/Modules/FindNF_CoreCLR.cmake | 4 ++-- CMake/binutils.common.cmake | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/CMake/Modules/FindNF_CoreCLR.cmake b/CMake/Modules/FindNF_CoreCLR.cmake index 30cd48cef0..b0fa81bbe7 100644 --- a/CMake/Modules/FindNF_CoreCLR.cmake +++ b/CMake/Modules/FindNF_CoreCLR.cmake @@ -30,8 +30,8 @@ list(APPEND NF_CoreCLR_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/DeviceInterfaces/Net list(APPEND NF_CoreCLR_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) list(APPEND NF_CoreCLR_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/nanoCLR) -list(APPEND NF_CoreCLR_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}) -list(APPEND NF_CoreCLR_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}/nanoCLR) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_VENDOR}/${TARGET_BOARD}) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_VENDOR}/${TARGET_BOARD}/nanoCLR) # source files for nanoFramework Core, CoreLib and CLR startup set(NF_CoreCLR_SRCS diff --git a/CMake/binutils.common.cmake b/CMake/binutils.common.cmake index 874eda4cc6..4ed252952b 100644 --- a/CMake/binutils.common.cmake +++ b/CMake/binutils.common.cmake @@ -117,7 +117,7 @@ macro(nf_add_common_dependencies target) if("${target}" STREQUAL "${NANOCLR_PROJECT_NAME}") configure_file(${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/target_platform.h.in - ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_BOARD}/target_platform.h @ONLY) + ${CMAKE_BINARY_DIR}/targets/${RTOS}/${TARGET_VENDOR}/${TARGET_BOARD}/target_platform.h @ONLY) endif() From 8412d141a7b6934ab218335fa3f349981b83e7ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 16:51:21 +0100 Subject: [PATCH 073/572] Adjust block storage config for SL_STK3701A --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 4 ++-- .../SL_STK3701A/common/Device_BlockStorage-DEBUG.c | 6 +++--- .../SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c | 6 +++--- .../SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld | 4 ++-- .../SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 4 ++-- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 754794ef45..a53c266dd1 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -66,13 +66,13 @@ if(SRECORD_TOOL_AVAILABLE) nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - A000 + B000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) else() nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - A000 + B000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) endif() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c index 5c66fa5b98..87e972d6fc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -10,10 +10,10 @@ const BlockRange BlockRange1[] = { // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 9}, + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 10}, - // 0000A000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 10, 237}, + // 0000B000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 11, 237}, // 000EE000 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c index c52a00f600..dcf2d55e8c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c @@ -10,10 +10,10 @@ const BlockRange BlockRange1[] = { // 08000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 15}, + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 10}, - // 08008000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 16, 158}, + // 0800B000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 11, 158}, // 0804F800 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index dad977c826..f6eaa9df4f 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00000000, len = 44k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x0000A000, len = 0 /* space reserved for application deployment */ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000B000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 4f13bd754c..686af9b153 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x0000A000, len = 2M - 44k - 4k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x000EE000, len = 908k /* space reserved for application deployment */ + flash0 (rx) : org = 0x0000B000, len = 2M - 48k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 904k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 9838ad153019488b48afc2b324927e2abadbb24b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 16:52:56 +0100 Subject: [PATCH 074/572] Extract Gecko SPI DMA driver from driver - Allows reusing in other SPI libraries (Skyworks serial APIs). --- CMake/Modules/FindGecko_SDK.cmake | 3 + .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 142 ++++--- .../System.Device.Spi/nf_gecko_spi_driver.cpp | 364 ++++++++++++++++++ .../System.Device.Spi/nf_gecko_spi_driver.h | 79 ++++ .../sys_dev_spi_native_target.h | 30 +- 5 files changed, 542 insertions(+), 76 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index add9fefbac..b3fc0c7e06 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -70,6 +70,7 @@ set(gecko_sdk_srcs em_vdac.c # emdrv + dmactrl.c dmadrv.c uartdrv.c spidrv.c @@ -108,6 +109,7 @@ set(gecko_sdk_srcs # nanoFramework implementations # nano_sl_i2cspm.c + nf_gecko_spi_driver.cpp # autogen at target level ) @@ -156,6 +158,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") # nanoFramework implementations ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c + ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi CMAKE_FIND_ROOT_PATH_BOTH ) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 20139dfcc0..dc517b5c3e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -27,66 +27,63 @@ NF_PAL_SPI SPI4_PAL; NF_PAL_SPI SPI5_PAL; #endif -#if defined(USART_PRESENT) -static USART_TypeDef *GetUsartFromHandle(struct SPIDRV_HandleData *handle) -{ - return handle->peripheral.usartPort; -} -#endif #if defined(EUSART_PRESENT) -static EUSART_TypeDef *GetUsartFromHandle(struct SPIDRV_HandleData *handle) +#error "Only USART type is supported. Drivar can't handle EUSART." +#endif + +static USART_TypeDef *GetUsartFromHandle(struct Gecko_SpiDriver *handle) { - return handle->peripheral.eusartPort; + return handle->Usart; } -#endif // Callback used when a async transfer operation completes -static void SpiTransferCompleteCallback(struct SPIDRV_HandleData *handle, Ecode_t transferStatus, int itemsTransferred) +static void SpiTransferCompleteCallback(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred) { (void)transferStatus; (void)itemsTransferred; + NATIVE_INTERRUPT_START NF_PAL_SPI *palSpi = NULL; // Find the NF_PAL_SPI* for driver #if GECKO_USE_SPI0 == TRUE - if (GetUsartFromHandle(handle) == USART0) + if (GetUsartFromHandle(driver) == USART0) { palSpi = &SPI0_PAL; } #endif #if GECKO_USE_SPI1 == TRUE - if (GetUsartFromHandle(handle) == USART1) + if (GetUsartFromHandle(driver) == USART1) { palSpi = &SPI1_PAL; } #endif #if GECKO_USE_SPI2 == TRUE - if (GetUsartFromHandle(handle) == USART2) + if (GetUsartFromHandle(driver) == USART2) { palSpi = &SPI2_PAL; } #endif #if GECKO_USE_SPI3 == TRUE - if (GetUsartFromHandle(handle) == USART3) + if (GetUsartFromHandle(driver) == USART3) { palSpi = &SPI3_PAL; } #endif #if GECKO_USE_SPI4 == TRUE - if (GetUsartFromHandle(handle) == USART4) + if (GetUsartFromHandle(driver) == USART4) { palSpi = &SPI4_PAL; } #endif #if GECKO_USE_SPI5 == TRUE - if (GetUsartFromHandle(handle) == USART5) + if (GetUsartFromHandle(driver) == USART5) { palSpi = &SPI5_PAL; } @@ -106,7 +103,7 @@ static void SpiTransferCompleteCallback(struct SPIDRV_HandleData *handle, Ecode_ // // half duplex operation, clear output enable bit // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - SPIDRV_MReceive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + SpiReceive(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); } else { @@ -274,6 +271,8 @@ HRESULT CPU_SPI_nWrite_nRead( // === Setup the operation and init buffers === palSpi->BusIndex = sdev.Spi_Bus; + palSpi->Driver->DataIs16bits = wrc.Bits16ReadWrite; + // set bus config flag busConfigIsHalfDuplex = (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex); @@ -292,8 +291,10 @@ HRESULT CPU_SPI_nWrite_nRead( } } - palSpi->Usart->FRAME = - (palSpi->Usart->FRAME & ~_USART_FRAME_DATABITS_MASK) | wrc.Bits16ReadWrite ? usartDatabits16 : usartDatabits8; + if (!SpiDmaStart(palSpi->Driver)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_TOO_MANY_OPEN_HANDLES); + } // if CS is to be controlled by the driver, set the GPIO if (palSpi->ChipSelect >= 0) @@ -313,8 +314,8 @@ HRESULT CPU_SPI_nWrite_nRead( { // Full duplex // Uses the largest buffer size as transfer size - SPIDRV_MTransferB( - palSpi->Handle, + SpiTransferBlocking( + palSpi->Driver, palSpi->WriteBuffer, palSpi->ReadBuffer, palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize); @@ -328,7 +329,7 @@ HRESULT CPU_SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; // } - SPIDRV_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + SpiTransmitBlocking(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize); // receive operation // TODO @@ -337,7 +338,7 @@ HRESULT CPU_SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - SPIDRV_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + SpiReceiveBlocking(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize); } } else @@ -352,7 +353,7 @@ HRESULT CPU_SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - SPIDRV_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + SpiReceiveBlocking(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize); } else { @@ -363,7 +364,7 @@ HRESULT CPU_SPI_nWrite_nRead( // half duplex operation, set output enable // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; } - SPIDRV_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + SpiTransmitBlocking(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize); } } @@ -399,8 +400,8 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // Uses the largest buffer size as transfer size - SPIDRV_MTransfer( - palSpi->Handle, + SpiTransfer( + palSpi->Driver, palSpi->WriteBuffer, palSpi->ReadBuffer, palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, @@ -419,11 +420,7 @@ HRESULT CPU_SPI_nWrite_nRead( } // receive operation will be started in the callback after the above completes - SPIDRV_MTransmit( - palSpi->Handle, - palSpi->WriteBuffer, - palSpi->WriteSize, - SpiTransferCompleteCallback); + SpiTransmit(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize, SpiTransferCompleteCallback); } } else @@ -435,7 +432,7 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start receive - SPIDRV_MReceive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + SpiReceive(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); } else { @@ -443,11 +440,7 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start send - SPIDRV_MTransmit( - palSpi->Handle, - palSpi->WriteBuffer, - palSpi->WriteSize, - SpiTransferCompleteCallback); + SpiTransmit(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize, SpiTransferCompleteCallback); } } @@ -462,6 +455,7 @@ HRESULT CPU_SPI_nWrite_nRead( bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) { NF_PAL_SPI *palSpi = NULL; + USART_TypeDef *usart = NULL; void (*configPinsHandler)(const struct SPI_DEVICE_CONFIGURATION &) = NULL; // create USART init struct with the defaults: @@ -499,7 +493,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI0 == TRUE case 0: palSpi = &SPI0_PAL; - palSpi->Usart = USART0; + usart = USART0; configPinsHandler = &ConfigPins_SPI0; break; #endif @@ -507,7 +501,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI1 == TRUE case 1: palSpi = &SPI1_PAL; - palSpi->Usart = USART1; + usart = USART1; configPinsHandler = &ConfigPins_SPI1; break; #endif @@ -515,7 +509,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI2 == TRUE case 2: palSpi = &SPI2_PAL; - palSpi->Usart = USART2; + usart = USART2; configPinsHandler = &ConfigPins_SPI2; break; @@ -524,7 +518,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI3 == TRUE case 3: palSpi = &SPI3_PAL; - palSpi->Usart = USART3; + usart = USART3; configPinsHandler = &ConfigPins_SPI3; break; #endif @@ -532,7 +526,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI4 == TRUE case 4: palSpi = &SPI4_PAL; - palSpi->Usart = USART4; + usart = USART4; configPinsHandler = &ConfigPins_SPI4; break; #endif @@ -540,7 +534,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI5 == TRUE case 5: palSpi = &SPI5_PAL; - palSpi->Usart = USART5; + usart = USART5; configPinsHandler = &ConfigPins_SPI5; break; #endif @@ -550,29 +544,47 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon return false; } - if (palSpi->Configuration == NULL) + if (palSpi->Driver == NULL) { + + // allocate memory for the USART_InitSync_TypeDef + palSpi->Driver = (Gecko_SpiDriver *)platform_malloc(sizeof(Gecko_SpiDriver)); + + // sanity check allocation + if (palSpi->Driver == NULL) + { + return false; + } + // allocate memory for the USART_InitSync_TypeDef - palSpi->Configuration = (USART_InitSync_TypeDef *)platform_malloc(sizeof(USART_InitSync_TypeDef)); + palSpi->Driver->Configuration = (USART_InitSync_TypeDef *)platform_malloc(sizeof(USART_InitSync_TypeDef)); // sanity check allocation - if (palSpi->Configuration == NULL) + if (palSpi->Driver->Configuration == NULL) { + platform_free(palSpi->Driver); + return false; } // copy init struct - memcpy(palSpi->Configuration, &configInit, sizeof(USART_InitSync_TypeDef)); + memcpy(palSpi->Driver->Configuration, &configInit, sizeof(USART_InitSync_TypeDef)); + + // set USART + palSpi->Driver->Usart = usart; // get the SPI configuration - GetSPIConfig(busConfiguration, palSpi->Configuration); + GetSPIConfig(busConfiguration, palSpi->Driver->Configuration); - USART_InitSync(palSpi->Usart, palSpi->Configuration); + SpiDriverInit(palSpi->Driver); palSpi->ChipSelect = busConfiguration.DeviceChipSelect; // call handler to configure pins configPinsHandler(busConfiguration); + + // init DMA driver (don't bother check return value as if it's already started it won't fail)v + DMADRV_Init(); } return true; @@ -592,9 +604,10 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) USART_Reset(UART0); // free memory - platform_free(SPI0_PAL.Configuration); + platform_free(SPI0_PAL.Driver->Configuration); + platform_free(SPI0_PAL.Driver); - SPI0_PAL.Configuration = NULL; + SPI0_PAL.Driver = NULL; break; #endif @@ -604,9 +617,10 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) USART_Reset(UART1); // free memory - platform_free(SPI1_PAL.Configuration); + platform_free(SPI1_PAL.Driver->Configuration); + platform_free(SPI1_PAL.Driver); - SPI1_PAL.Configuration = NULL; + SPI1_PAL.Driver = NULL; break; #endif @@ -616,9 +630,10 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) USART_Reset(UART2); // free memory - platform_free(SPI2_PAL.Configuration); + platform_free(SPI2_PAL.Driver->Configuration); + platform_free(SPI2_PAL.Driver); - SPI2_PAL.Configuration = NULL; + SPI2_PAL.Driver = NULL; break; #endif @@ -628,9 +643,10 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) USART_Reset(UART3); // free memory - platform_free(SPI3_PAL.Configuration); + platform_free(SPI3_PAL.Driver->Configuration); + platform_free(SPI3_PAL.Driver); - SPI3_PAL.Configuration = NULL; + SPI3_PAL.Driver = NULL; break; #endif @@ -640,9 +656,10 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) USART_Reset(UART4); // free memory - platform_free(SPI4_PAL.Configuration); + platform_free(SPI4_PAL.Driver->Configuration); + platform_free(SPI4_PAL.Driver); - SPI4_PAL.Configuration = NULL; + SPI4_PAL.Driver = NULL; break; #endif @@ -652,9 +669,10 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) USART_Reset(UART5); // free memory - platform_free(SPI5_PAL.Configuration); + platform_free(SPI5_PAL.Driver->Configuration); + platform_free(SPI5_PAL.Driver); - SPI5_PAL.Configuration = NULL; + SPI5_PAL.Driver = NULL; break; #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp new file mode 100644 index 0000000000..7526232418 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -0,0 +1,364 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_gecko_spi_driver.h" + +#if defined(EUSART_PRESENT) +#error "Only USART type is supported. Drivar can't handle EUSART." +#endif + +// Adds track for a new DMA request +void DmaRequestAdd(struct Gecko_SpiDriver *driver) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + if (driver->DmaRequestCount == 0) + { + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + } + + driver->DmaRequestCount++; + + CORE_EXIT_ATOMIC(); +#else + driver->DmaRequestCount++; +#endif +} + +// Substracts track of a DMA request +void DmaRequestRemove(struct Gecko_SpiDriver *driver) +{ + if (driver->DmaRequestCount == 0) + { + return; + } + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + driver->DmaRequestCount--; + if (driver->DmaRequestCount == 0) + { + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + } + CORE_EXIT_ATOMIC(); +#else + driver->DmaRequestCount--; +#endif +} + +// Callback for DMA transfer completed +bool RxDmaComplete(unsigned int channel, unsigned int sequenceNo, void *userParam) +{ + (void)channel; + (void)sequenceNo; + Gecko_SpiDriver *driver = (Gecko_SpiDriver *)userParam; + + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + driver->DmaRemaningCount = 0; + + driver->DmaCallback(driver, ECODE_OK, 0); + + CORE_EXIT_ATOMIC(); + + DmaRequestRemove(driver); + + return true; +} + +// Callback for DMA blocking transfers +void DmaBlockingComplete(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred) +{ + (void)itemsTransferred; + (void)transferStatus; + + driver->BlockingOpCompleted = true; +} + +void WaitForTransferCompletion(struct Gecko_SpiDriver *driver) +{ + // TODO replace with RTOS semaphore + + // if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) + { + // Poll for completion by calling IRQ handler. + while (driver->BlockingOpCompleted == false) + { +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) + DMA_IRQHandler(); +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + LDMA_IRQHandler(); +#else +#error "No valid SPIDRV DMA engine defined." +#endif + } + } + // else + { + while (driver->BlockingOpCompleted == false) + ; + } +} + +void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback) +{ + void *rxPort, *txPort; + DMADRV_DataSize_t size; + + driver->BlockingOpCompleted = false; + driver->DmaTransferCount = count; + driver->DmaCallback = callback; + + driver->Usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (driver->DataIs16bits) + { + rxPort = (void *)&(driver->Usart->RXDOUBLE); + txPort = (void *)&(driver->Usart->TXDOUBLE); + } + else + { + rxPort = (void *)&(driver->Usart->RXDATA); + txPort = (void *)&(driver->Usart->TXDATA); + } + + if (driver->DataIs16bits) + { + size = dmadrvDataSize2; + } + else + { + size = dmadrvDataSize1; + } + + DmaRequestAdd(driver); + + // Start receive DMA. + DMADRV_PeripheralMemory( + driver->RxDmaChannel, + driver->RxDmaSignal, + (void *)buffer, + rxPort, + true, + count, + size, + RxDmaComplete, + driver); + + // Start transmit DMA. + DMADRV_MemoryPeripheral( + driver->TxDmaChannel, + driver->TxDmaSignal, + txPort, + (void *)&(driver->DmaDummyRxTxValue), + false, + count, + size, + NULL, + NULL); +} + +void StartTransmitDma(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback) +{ + void *rxPort, *txPort; + DMADRV_DataSize_t size; + + driver->BlockingOpCompleted = false; + driver->DmaTransferCount = count; + driver->DmaCallback = callback; + + driver->Usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (driver->DataIs16bits) + { + rxPort = (void *)&(driver->Usart->RXDOUBLE); + txPort = (void *)&(driver->Usart->TXDOUBLE); + } + else + { + rxPort = (void *)&(driver->Usart->RXDATA); + txPort = (void *)&(driver->Usart->TXDATA); + } + + if (driver->DataIs16bits) + { + size = dmadrvDataSize2; + } + else + { + size = dmadrvDataSize1; + } + + DmaRequestAdd(driver); + + // Receive DMA runs only to get precise numbers for SPIDRV_GetTransferStatus() + // Start receive DMA. + DMADRV_PeripheralMemory( + driver->RxDmaChannel, + driver->RxDmaSignal, + &(driver->DmaDummyRxTxValue), + rxPort, + false, + count, + size, + RxDmaComplete, + driver); + + // Start transmit DMA. + DMADRV_MemoryPeripheral( + driver->TxDmaChannel, + driver->TxDmaSignal, + txPort, + (void *)buffer, + true, + count, + size, + NULL, + NULL); +} + +void StartTransferDma( + struct Gecko_SpiDriver *driver, + const void *txBuffer, + void *rxBuffer, + int count, + SpiDmaCallback callback) +{ + void *rxPort, *txPort; + DMADRV_DataSize_t size; + + driver->BlockingOpCompleted = false; + driver->DmaTransferCount = count; + driver->DmaCallback = callback; + + driver->Usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (driver->DataIs16bits) + { + rxPort = (void *)&(driver->Usart->RXDOUBLE); + txPort = (void *)&(driver->Usart->TXDOUBLE); + } + else + { + rxPort = (void *)&(driver->Usart->RXDATA); + txPort = (void *)&(driver->Usart->TXDATA); + } + + if (driver->DataIs16bits) + { + size = dmadrvDataSize2; + } + else + { + size = dmadrvDataSize1; + } + + DmaRequestAdd(driver); + + // Start receive DMA. + DMADRV_PeripheralMemory( + driver->RxDmaChannel, + driver->RxDmaSignal, + rxBuffer, + rxPort, + true, + count, + size, + RxDmaComplete, + driver); + + // Start transmit DMA. + DMADRV_MemoryPeripheral( + driver->TxDmaChannel, + driver->TxDmaSignal, + txPort, + (void *)txBuffer, + true, + count, + size, + NULL, + NULL); +} + +// Start a blocking transfer +void SpiTransferBlocking(struct Gecko_SpiDriver *driver, const void *txBuffer, void *rxBuffer, int count) +{ + StartTransferDma(driver, txBuffer, rxBuffer, count, DmaBlockingComplete); + + WaitForTransferCompletion(driver); +} + +// Start a blocking receive transfer +void SpiReceiveBlocking(struct Gecko_SpiDriver *driver, void *buffer, int count) +{ + StartReceiveDma(driver, buffer, count, DmaBlockingComplete); + + WaitForTransferCompletion(driver); +} + +// Start a blocking transmit transfer +void SpiTransmitBlocking(struct Gecko_SpiDriver *driver, const void *buffer, int count) +{ + StartTransmitDma(driver, buffer, count, DmaBlockingComplete); + + WaitForTransferCompletion(driver); +} + +// Start a non-blocking transfer +void SpiTransfer( + struct Gecko_SpiDriver *driver, + const void *txBuffer, + void *rxBuffer, + int count, + SpiDmaCallback callback) +{ + StartTransferDma(driver, txBuffer, rxBuffer, count, callback); +} + +// Start a non-blocking transmit transfer +void SpiTransmit(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback) +{ + StartTransmitDma(driver, buffer, count, callback); +} + +// Start a non-blocking receive transfer +void SpiReceive(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback) +{ + SpiDmaStart(driver); + StartReceiveDma(driver, buffer, count, callback); +} + +// Initialize DMA for SPI transfers +bool SpiDmaStart(struct Gecko_SpiDriver *driver) +{ + // set frame size + driver->Usart->FRAME = + (driver->Usart->FRAME & ~_USART_FRAME_DATABITS_MASK) | driver->DataIs16bits ? usartDatabits16 : usartDatabits8; + + // set DMA + if (DMADRV_AllocateChannel(&driver->TxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return false; + } + + if (DMADRV_AllocateChannel(&driver->RxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return false; + } + + return true; +} + +void SpiDriverInit(struct Gecko_SpiDriver *driver) +{ + USART_InitSync(driver->Usart, driver->Configuration); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h new file mode 100644 index 0000000000..d9557b8a77 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h @@ -0,0 +1,79 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef NF_GECKO_SPI_DRIVER_H +#define NF_GECKO_SPI_DRIVER_H + +#include + +#include + +#include +#include +#include +#include +#include + +// flags for hardware events +extern TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +typedef void (*SpiDmaCallback)(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred); + +#ifdef __cplusplus +extern "C" +{ +#endif + + struct Gecko_SpiDriver + { + USART_TypeDef *Usart; + USART_InitSync_TypeDef *Configuration; + + bool DataIs16bits; + + unsigned int TxDmaChannel; + unsigned int RxDmaChannel; + DMADRV_PeripheralSignal_t TxDmaSignal; + DMADRV_PeripheralSignal_t RxDmaSignal; + bool BlockingOpCompleted; + int32_t DmaTransferCount; + int32_t DmaRemaningCount; + int32_t DmaRequestCount; + uint32_t DmaDummyRxTxValue; + SpiDmaCallback DmaCallback; + }; + + void SpiReceive(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback); + void SpiTransmit(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback); + void SpiTransfer( + struct Gecko_SpiDriver *driver, + const void *txBuffer, + void *rxBuffer, + int count, + SpiDmaCallback callback); + void SpiTransmitBlocking(struct Gecko_SpiDriver *driver, const void *buffer, int count); + void SpiReceiveBlocking(struct Gecko_SpiDriver *driver, void *buffer, int count); + void SpiTransferBlocking(struct Gecko_SpiDriver *driver, const void *txBuffer, void *rxBuffer, int count); + void StartTransferDma( + struct Gecko_SpiDriver *driver, + const void *txBuffer, + void *rxBuffer, + int count, + SpiDmaCallback callback); + void StartTransmitDma(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback); + void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback); + void WaitForTransferCompletion(struct Gecko_SpiDriver *driver); + void DmaBlockingComplete(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred); + bool RxDmaComplete(unsigned int channel, unsigned int sequenceNo, void *userParam); + void DmaRequestRemove(struct Gecko_SpiDriver *driver); + void DmaRequestAdd(struct Gecko_SpiDriver *driver); + void SpiDriverInit(struct Gecko_SpiDriver *driver); + bool SpiDmaStart(struct Gecko_SpiDriver *driver); + +#ifdef __cplusplus +} +#endif + +#endif // NF_GECKO_SPI_DRIVER_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 355334a9e1..3cd4d75208 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -12,8 +12,7 @@ #include #include -#include -#include +#include #define SL_SPIDRV_EXP_BITRATE 1000000 @@ -70,8 +69,6 @@ struct NF_PAL_SPI { int BusIndex; - USART_TypeDef *Usart; - USART_InitSync_TypeDef *Configuration; SpiBusConfiguration BusConfiguration; SPI_Callback Callback; @@ -87,6 +84,9 @@ struct NF_PAL_SPI // -1 = Chip Select is not handled | >0 Chip Select is to be controlled with this GPIO int32_t ChipSelect; + + // DMA transfer control + Gecko_SpiDriver *Driver; }; //////////////////////////////////////////// @@ -130,25 +130,27 @@ extern NF_PAL_SPI SPI5_PAL; void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig) \ { \ GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 1); \ - SPI##num##_PAL.Usart->ROUTELOC0 = \ - (SPI##num##_PAL.Usart->ROUTELOC0 & ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ - _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ - mosi_port_location | (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ + SPI##num##_PAL.Driver->Usart->ROUTELOC0 = (SPI##num##_PAL.Driver->Usart->ROUTELOC0 & \ + ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ + _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ + mosi_port_location | \ + (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ if (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ { \ GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 1); \ GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 1); \ - SPI##num##_PAL.Usart->ROUTELOC0 |= (miso_port_location << _USART_ROUTELOC0_RXLOC_SHIFT); \ + SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= (miso_port_location << _USART_ROUTELOC0_RXLOC_SHIFT); \ } \ else \ { \ - SPI##num##_PAL.Usart->CTRL |= USART_CTRL_LOOPBK; \ + SPI##num##_PAL.Driver->Usart->CTRL |= USART_CTRL_LOOPBK; \ GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ } \ - SPI##num##_PAL.Usart->ROUTEPEN = USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_CSPEN | USART_ROUTEPEN_TXPEN | \ - (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ - ? USART_ROUTEPEN_RXPEN \ - : 0; \ + SPI##num##_PAL.Driver->Usart->ROUTEPEN = \ + USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_CSPEN | USART_ROUTEPEN_TXPEN | \ + (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + ? USART_ROUTEPEN_RXPEN \ + : 0; \ } #else From e1a682860b3809d7ac8f585424cc9765e37f5347 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 18:22:45 +0100 Subject: [PATCH 075/572] Fix configuring GPIO pins for SPI --- .../target_system_device_spi_config.cpp | 8 ++++---- .../System.Device.Spi/sys_dev_spi_native_target.h | 15 ++++++++------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp index 9427e7c33b..04517ecca1 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -12,9 +12,9 @@ // Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display // pin configuration for SPI1 (EMC encoded "port location") -// SPI1_MOSI in PC6, location 1 +// SPI1_MOSI in PA14, location 6 // SPI1_MISO: (not used for LCD) -// SPI1_SCK in PC8, location 1 -// CS: PC14 (not used in SPI configuration) +// SPI1_SCK in PC15, location 3 +// CS: PC11 (not used in SPI configuration) -SPI_CONFIG_PINS(1, gpioPortC, 6, 1, 0, -1, -1, gpioPortC, 8, 1) +SPI_CONFIG_PINS(1, gpioPortC, 15, 3, gpioPortA, 14, 6, 0, -1, -1) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 3cd4d75208..7301bf7ad1 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -135,19 +135,20 @@ extern NF_PAL_SPI SPI5_PAL; _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ mosi_port_location | \ (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ - if (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + if (spiDeviceConfig.BusConfiguration == SpiBusConfiguration_HalfDuplex) \ { \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 1); \ - GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 1); \ - SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= (miso_port_location << _USART_ROUTELOC0_RXLOC_SHIFT); \ + SPI##num##_PAL.Driver->Usart->CTRL |= USART_CTRL_LOOPBK; \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ } \ else \ { \ - SPI##num##_PAL.Driver->Usart->CTRL |= USART_CTRL_LOOPBK; \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 1); \ + GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 1); \ + SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= \ + (miso_port_location) | (mosi_port_location << _USART_ROUTELOC0_TXLOC_SHIFT); \ } \ SPI##num##_PAL.Driver->Usart->ROUTEPEN = \ - USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_CSPEN | USART_ROUTEPEN_TXPEN | \ + USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_TXPEN | \ (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ ? USART_ROUTEPEN_RXPEN \ : 0; \ From f5944f7bc30c97f5051e4089b24d37c4ee88ea1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 12 Jul 2022 19:07:56 +0100 Subject: [PATCH 076/572] Fixes for SPI driver - Driver memory is now cleared. - USART is now started at beginning of transfer. - Add call to start and release SPI driver. --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 22 ++++++++++++++++++- .../System.Device.Spi/nf_gecko_spi_driver.cpp | 19 ++++++---------- .../System.Device.Spi/nf_gecko_spi_driver.h | 3 ++- 3 files changed, 30 insertions(+), 14 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index dc517b5c3e..34efd9fad4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -36,6 +36,11 @@ static USART_TypeDef *GetUsartFromHandle(struct Gecko_SpiDriver *handle) return handle->Usart; } +static void CompleteTransfer(struct Gecko_SpiDriver *driver) +{ + SpiRelease(driver); +} + // Callback used when a async transfer operation completes static void SpiTransferCompleteCallback(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred) { @@ -291,7 +296,7 @@ HRESULT CPU_SPI_nWrite_nRead( } } - if (!SpiDmaStart(palSpi->Driver)) + if (!SpiStart(palSpi->Driver)) { NANOCLR_SET_AND_LEAVE(CLR_E_TOO_MANY_OPEN_HANDLES); } @@ -368,6 +373,8 @@ HRESULT CPU_SPI_nWrite_nRead( } } + CompleteTransfer(palSpi->Driver); + // if CS is to be controlled by the driver, set the GPIO if (palSpi->ChipSelect >= 0) { @@ -556,6 +563,8 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon return false; } + memset(palSpi->Driver, 0, sizeof(Gecko_SpiDriver)); + // allocate memory for the USART_InitSync_TypeDef palSpi->Driver->Configuration = (USART_InitSync_TypeDef *)platform_malloc(sizeof(USART_InitSync_TypeDef)); @@ -585,6 +594,17 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon // init DMA driver (don't bother check return value as if it's already started it won't fail)v DMADRV_Init(); + + // set DMA + if (DMADRV_AllocateChannel(&palSpi->Driver->TxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return false; + } + + if (DMADRV_AllocateChannel(&palSpi->Driver->RxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return false; + } } return true; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp index 7526232418..77accdb886 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -333,31 +333,26 @@ void SpiTransmit(struct Gecko_SpiDriver *driver, const void *buffer, int count, // Start a non-blocking receive transfer void SpiReceive(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback) { - SpiDmaStart(driver); StartReceiveDma(driver, buffer, count, callback); } // Initialize DMA for SPI transfers -bool SpiDmaStart(struct Gecko_SpiDriver *driver) +bool SpiStart(struct Gecko_SpiDriver *driver) { // set frame size driver->Usart->FRAME = (driver->Usart->FRAME & ~_USART_FRAME_DATABITS_MASK) | driver->DataIs16bits ? usartDatabits16 : usartDatabits8; - // set DMA - if (DMADRV_AllocateChannel(&driver->TxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) - { - return false; - } - - if (DMADRV_AllocateChannel(&driver->RxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) - { - return false; - } + USART_Enable(driver->Usart, usartEnable); return true; } +void SpiRelease(struct Gecko_SpiDriver *driver) +{ + USART_Enable(driver->Usart, usartDisable); +} + void SpiDriverInit(struct Gecko_SpiDriver *driver) { USART_InitSync(driver->Usart, driver->Configuration); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h index d9557b8a77..236ea7f662 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h @@ -70,7 +70,8 @@ extern "C" void DmaRequestRemove(struct Gecko_SpiDriver *driver); void DmaRequestAdd(struct Gecko_SpiDriver *driver); void SpiDriverInit(struct Gecko_SpiDriver *driver); - bool SpiDmaStart(struct Gecko_SpiDriver *driver); + bool SpiStart(struct Gecko_SpiDriver *driver); + void SpiRelease(struct Gecko_SpiDriver *driver); #ifdef __cplusplus } From a7eb4577d635f8aeef4a316e8e26aa837d2b39b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 13 Jul 2022 14:05:39 +0100 Subject: [PATCH 077/572] More work on GECKO SPI DMA driver - Add RTOS flag for general hardware events. - Add SPI DMA event, implenet this on SPI driver. - Move DMA inits to HAL. - Fix CS pin for displya. --- CMake/Modules/FindGecko_SDK.cmake | 3 +- .../target_system_device_spi_config.cpp | 4 +- .../SiliconLabs/_include/platformHAL.h | 3 ++ .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 14 ----- .../System.Device.Spi/nf_gecko_spi_driver.cpp | 51 +++++++++++++------ .../System.Device.Spi/nf_gecko_spi_driver.h | 14 ++++- .../sys_dev_spi_native_target.h | 6 +-- .../SiliconLabs/_nanoCLR/targetHAL.cpp | 7 +++ 8 files changed, 66 insertions(+), 36 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index b3fc0c7e06..f4483c0d5d 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -10,8 +10,9 @@ FetchContent_GetProperties(gecko_sdk) # set include directories list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/config) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp index 04517ecca1..78f70b20e7 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -15,6 +15,6 @@ // SPI1_MOSI in PA14, location 6 // SPI1_MISO: (not used for LCD) // SPI1_SCK in PC15, location 3 -// CS: PC11 (not used in SPI configuration) +// CS: PC14 (not used in SPI configuration) -SPI_CONFIG_PINS(1, gpioPortC, 15, 3, gpioPortA, 14, 6, 0, -1, -1) +SPI_CONFIG_PINS(1, gpioPortC, 15, 3, gpioPortA, 14, 6, 0, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h b/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h index 6b58caa8f8..de17779923 100644 --- a/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h +++ b/targets/AzureRTOS/SiliconLabs/_include/platformHAL.h @@ -8,4 +8,7 @@ #define WIRE_PROTOCOL_UART_BUFFER_SIZE 32 +// event flag for SPI transaction completed +#define NANO_HW_EVENTS_SPI_TRANSACTION_FLAG 0x00000001 + #endif //_PLATFORM_HAL_TIME_H_ diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 34efd9fad4..9be01cc1f3 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -591,20 +591,6 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon // call handler to configure pins configPinsHandler(busConfiguration); - - // init DMA driver (don't bother check return value as if it's already started it won't fail)v - DMADRV_Init(); - - // set DMA - if (DMADRV_AllocateChannel(&palSpi->Driver->TxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) - { - return false; - } - - if (DMADRV_AllocateChannel(&palSpi->Driver->RxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) - { - return false; - } } return true; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp index 77accdb886..eeb2861c5f 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -82,31 +82,33 @@ void DmaBlockingComplete(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, (void)transferStatus; driver->BlockingOpCompleted = true; + } void WaitForTransferCompletion(struct Gecko_SpiDriver *driver) { - // TODO replace with RTOS semaphore + // RTOS semaphore + // (void)driver; + // uint32_t dummy; - // if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) - { - // Poll for completion by calling IRQ handler. - while (driver->BlockingOpCompleted == false) - { + // // wait forever for the SPI event + // tx_event_flags_get(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR_CLEAR, &dummy, TX_WAIT_FOREVER); + + // alternative approach with loop calling IRQ handlers + if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) { + // Poll for completion by calling IRQ handler. + while (driver->BlockingOpCompleted == false) { #if defined(DMA_PRESENT) && (DMA_COUNT == 1) - DMA_IRQHandler(); + DMA_IRQHandler(); #elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - LDMA_IRQHandler(); + LDMA_IRQHandler(); #else #error "No valid SPIDRV DMA engine defined." #endif - } - } - // else - { - while (driver->BlockingOpCompleted == false) - ; } + } else { + while (driver->BlockingOpCompleted == false) ; + } } void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback) @@ -353,7 +355,26 @@ void SpiRelease(struct Gecko_SpiDriver *driver) USART_Enable(driver->Usart, usartDisable); } -void SpiDriverInit(struct Gecko_SpiDriver *driver) +bool SpiDriverInit(struct Gecko_SpiDriver *driver) { + // set DMA + if (DMADRV_AllocateChannel(&driver->TxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return false; + } + + if (DMADRV_AllocateChannel(&driver->RxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return false; + } + USART_InitSync(driver->Usart, driver->Configuration); + + return true; +} + +void SpiDriverDeInit(struct Gecko_SpiDriver *driver) +{ + DMADRV_FreeChannel(driver->TxDmaChannel); + DMADRV_FreeChannel(driver->RxDmaChannel); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h index 236ea7f662..dc1bdf4ecc 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h @@ -16,6 +16,18 @@ #include #include +#include + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) +#define SPI_DMA_IRQ DMA_IRQn + +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) +#define SPI_DMA_IRQ LDMA_IRQn + +#else +#error "No valid SPIDRV DMA engine defined." +#endif + // flags for hardware events extern TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -69,7 +81,7 @@ extern "C" bool RxDmaComplete(unsigned int channel, unsigned int sequenceNo, void *userParam); void DmaRequestRemove(struct Gecko_SpiDriver *driver); void DmaRequestAdd(struct Gecko_SpiDriver *driver); - void SpiDriverInit(struct Gecko_SpiDriver *driver); + bool SpiDriverInit(struct Gecko_SpiDriver *driver); bool SpiStart(struct Gecko_SpiDriver *driver); void SpiRelease(struct Gecko_SpiDriver *driver); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 7301bf7ad1..4c082670ee 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -129,7 +129,7 @@ extern NF_PAL_SPI SPI5_PAL; miso_port_location) \ void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig) \ { \ - GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 1); \ + GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 0); \ SPI##num##_PAL.Driver->Usart->ROUTELOC0 = (SPI##num##_PAL.Driver->Usart->ROUTELOC0 & \ ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ @@ -142,8 +142,8 @@ extern NF_PAL_SPI SPI5_PAL; } \ else \ { \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 1); \ - GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 1); \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ + GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 0); \ SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= \ (miso_port_location) | (mosi_port_location << _USART_ROUTELOC0_TXLOC_SHIFT); \ } \ diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index b447fdfccd..aa1de60837 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -12,6 +12,8 @@ #include #include +#include + // #if (HAL_USE_CAN == TRUE) // #include // #endif @@ -151,6 +153,9 @@ void nanoHAL_Initialize() // Ink_Initialize(); #endif + // init DMA driver (don't bother check return value as if it's already started it won't fail)v + DMADRV_Init(); + // Initialise Network Stack Network_Initialize(); } @@ -173,6 +178,8 @@ void nanoHAL_Uninitialize() // } // } + DMADRV_DeInit(); + // TODO SOCKETS_CloseConnections(); From c16274f5f412dbd349b71940b94890dc17f7b144 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 14 Jul 2022 17:23:43 +0100 Subject: [PATCH 078/572] Add build option to set serial BR in Azure RTOS and Silabs targets - Add new board variant in CMake User presets for GG11 revB. - Fix target name to SL_STK3701A. --- CMake/AzureRTOS_target_os.h.in | 1 + CMakeUserPresets.TEMPLATE.json | 29 ++++++++++++++++--- .../sl_iostream_init_usart_instances.c | 9 ++++++ 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/CMake/AzureRTOS_target_os.h.in b/CMake/AzureRTOS_target_os.h.in index 87c18a1249..34a7228cc2 100644 --- a/CMake/AzureRTOS_target_os.h.in +++ b/CMake/AzureRTOS_target_os.h.in @@ -31,5 +31,6 @@ #define NANOCLR_SYSTEM_COLLECTIONS @TARGET_SYSTEM_COLLECTIONS@ #define TARGET_HAS_NANOBOOTER @TARGET_HAS_NANOBOOTER@ #define TRACE_TO_STDIO @TARGET_TRACE_TO_STDIO@ +#cmakedefine TARGET_SERIAL_BAUDRATE @TARGET_SERIAL_BAUDRATE@ #endif // TARGET_OS_H diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 9d881fc97b..cab473ce23 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -137,7 +137,7 @@ } }, { - "name": "EFM32GG11", + "name": "SL_STK3701A", "inherits": [ "user-local-tools", "user-prefs", @@ -151,6 +151,22 @@ "NF_INTEROP_ASSEMBLIES": null } }, + { + "name": "SL_STK3701A_REVB", + "inherits": [ + "user-local-tools", + "user-prefs", + "SL_STK3701A_preset" + ], + "cacheVariables": { + "TARGET_BOARD": { + "type": "STRING", + "value": "SL_STK3701A" + }, + "TARGET_SERIAL_BAUDRATE": "115200", + "NF_INTEROP_ASSEMBLIES": null + } + }, { "name": "ESP32_PSRAM_REV0", "inherits": [ @@ -637,9 +653,14 @@ "configurePreset": "ST_B_L475E_IOT01A" }, { - "name": "EFM32GG11", - "displayName": "EFM32GG11", - "configurePreset": "EFM32GG11" + "name": "SL_STK3701A", + "displayName": "SL_STK3701A", + "configurePreset": "SL_STK3701A" + }, + { + "name": "SL_STK3701A_REVB", + "displayName": "SL_STK3701A_REVB", + "configurePreset": "SL_STK3701A_REVB" }, { "name": "ESP32_PSRAM_REV0", diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 31c2c50a6e..7c43f9e846 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -11,6 +11,15 @@ // Include instance config #include "sl_iostream_usart_vcom_config.h" +//////////////////////////////////////////////////////////////// +// Baudrate for the serial port // +// Override default setting from board if build option is set // +//////////////////////////////////////////////////////////////// +#ifdef TARGET_SERIAL_BAUDRATE +#undef SL_IOSTREAM_USART_VCOM_BAUDRATE +#define SL_IOSTREAM_USART_VCOM_BAUDRATE TARGET_SERIAL_BAUDRATE +#endif + // MACROs for generating name and IRQ handler function #define SL_IOSTREAM_USART_CONCAT_PASTER(first, second, third) first ## second ## third From 245bc6aeac571c71f47ec59fa19969f9994f3ee4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 15 Jul 2022 17:25:19 +0100 Subject: [PATCH 079/572] More work to allow revB to work at 115200 --- CMake/Modules/FindGecko_SDK.cmake | 1 + targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md | 13 +++++++++++-- .../autogen/sl_iostream_init_usart_instances.c | 3 ++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index f4483c0d5d..f75621db9f 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -12,6 +12,7 @@ FetchContent_GetProperties(gecko_sdk) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/AzureRTOS) list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index b7afefe0b2..4b4271952b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -1,2 +1,11 @@ -Setting the VCP baud rate to 921600 -https://community.silabs.com/s/article/kba-bt-1208-using-virtual-com-port-vcom-x \ No newline at end of file +# Silabs EFM32 Giant Gecko GG11 Starter Kit (revC hardware) + +This target is for revC hardware. This can be easily identified by the presence of a USB-C connector for JLink connection. +Opposed to revB which carries a micro USB connector instead. For revB user the firmware for target `SL_STK3701A_REVB`. + +## Setting the VCP baud rate to 921600 + +https://community.silabs.com/s/article/kba-bt-1208-using-virtual-com-port-vcom-x + +:warning: +Only possible for revC hardware. diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 7c43f9e846..ce3f84e0ae 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -9,7 +9,8 @@ #include "sl_iostream_uart.h" #include "sl_iostream_usart.h" // Include instance config - #include "sl_iostream_usart_vcom_config.h" +#include "sl_iostream_usart_vcom_config.h" +#include //////////////////////////////////////////////////////////////// // Baudrate for the serial port // From 2a3b097bb7e5c977b813299215c34a79fabc4e9a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Jul 2022 15:19:27 +0100 Subject: [PATCH 080/572] Definitive fix on the booter to CLR transition - Had to reconfigure HF clock to RCO to allow reconfigure at CLR. --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c | 5 +++++ targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 7540d92c82..b1babc469d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -192,6 +193,10 @@ int main(void) if (CheckValidCLRImage((uint32_t)&__deployment_start__)) { // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + // launch nanoCLR LaunchCLR((uint32_t)&__deployment_start__); } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index d1511b71e3..1626c3a82f 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -162,7 +162,6 @@ void tx_application_define(void *first_unused_memory) // Application entry point. int main(void) { - // Initialize the board sl_system_init(); // Configure LED0 as output From 7c58f47b4325d999f5722e89ebee99a52bf8eb9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Jul 2022 16:42:56 +0100 Subject: [PATCH 081/572] Add support for ADC --- CMakePresets.json | 2 +- .../SiliconLabs/SL_STK3701A/README.md | 10 ++ .../target_system_device_adc_config.cpp | 20 +++ .../target_system_device_adc_config.h | 6 + ...dc_native_System_Device_Adc_AdcChannel.cpp | 97 +++++++++++++ ...native_System_Device_Adc_AdcController.cpp | 132 ++++++++++++++++++ .../sys_dev_adc_native_target.h | 39 ++++++ 7 files changed, 305 insertions(+), 1 deletion(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcChannel.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcController.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_target.h diff --git a/CMakePresets.json b/CMakePresets.json index 21a858e9ca..566c37e040 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -296,7 +296,7 @@ "API_System.Device.I2c": "ON", "API_System.Device.Pwm": "OFF", "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", + "API_System.Device.Adc": "ON", "API_System.Device.Dac": "OFF", "API_System.Net": "OFF", "API_nanoFramework.Device.OneWire": "OFF", diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index 4b4271952b..a0e0016067 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -9,3 +9,13 @@ https://community.silabs.com/s/article/kba-bt-1208-using-virtual-com-port-vcom-x :warning: Only possible for revC hardware. + +## ADC channels + +ADC has enabled the following channels: +0 - reading from PE11 (pin 6 on the expansion header) +1 - internal temperature +2 - VCC + +:warning: +Vref is 2.5V for all channels, except for VCC which is 5V. diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..e675ce5e97 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PE11- ADC0 Port 4X Channel 11 (Expansion Header Pin 6) + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC0 + {0, adcPosSelAPORT4XCH11}, + + // these are the internal sources + {0, adcPosSelTEMP}, + {0, adcPosSelAVDD}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.h new file mode 100644 index 0000000000..9423e913ff --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcChannel.cpp new file mode 100644 index 0000000000..a6063c44bb --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcChannel.cpp @@ -0,0 +1,97 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcChannel::NativeReadValue___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + int channelNumber; + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + ADC_InitSingle_TypeDef adcInitSingle; + + // ADC related variables + adcInitSingle = ADC_INITSINGLE_DEFAULT; + uint32_t sample; + ADC_TypeDef *adcDriver = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + adcDefinition = AdcPortPinConfig[channelNumber]; + + // we should remove form the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch (adcDefinition.adcIndex) + { + +#if GECKO_USE_ADC0 + case 0: + adcDriver = ADC0; + break; +#endif + +#if GECKO_USE_ADC1 + case 1: + adcDriver = ADC1; + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if (adcDefinition.posSel == adcPosSelAVDD) + { + // Ref is 5V to measure VDD + adcInitSingle.reference = adcRef2V5; + } + else + { + // Ref is internal 2.5V for all the others, including the internal signals + adcInitSingle.reference = adcRef2V5; + } + + // single ended + adcInitSingle.diff = false; + // set acquisition time to meet minimum requirement + adcInitSingle.acqTime = adcAcqTime4; + // set pos + adcInitSingle.posSel = adcDefinition.posSel; + + ADC_InitSingle(adcDriver, &adcInitSingle); + + // Start ADC conversion + ADC_Start(adcDriver, adcStartSingle); + + // Wait for conversion to be complete + while (!(ADC0->STATUS & _ADC_STATUS_SINGLEDV_MASK)) + ; + + // perform the conversion + sample = ADC_DataSingleGet(adcDriver); + + // set the return result with the conversion value from the array + stack.SetResult_I4(sample); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcChannel::NativeDisposeChannel___VOID(CLR_RT_StackFrame &stack) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcController.cpp new file mode 100644 index 0000000000..082848d5f7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_System_Device_Adc_AdcController.cpp @@ -0,0 +1,132 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +#define ADC_FREQ 16000000 + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeOpenChannel___VOID__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + int channel; + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + ADC_Init_TypeDef adcInit; + CMU_Clock_TypeDef adcClock; + ADC_TypeDef *adcDriver = NULL; + + adcInit = ADC_INIT_DEFAULT; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Get channel from argument + channel = stack.Arg1().NumericByRef().s4; + + adcDefinition = AdcPortPinConfig[channel]; + + // we should remove from the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch (adcDefinition.adcIndex) + { + +#if GECKO_USE_ADC0 + case 0: + adcDriver = ADC0; + adcClock = cmuClock_ADC0; + break; +#endif + +#if GECKO_USE_ADC1 + case 1: + adcDriver = ADC1; + adcClock = cmuClock_ADC1; + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Enable ADC clock + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(adcClock, true); + + // Init to max ADC clock for Series 1 + adcInit.prescale = ADC_PrescaleCalc(ADC_FREQ, 0); + adcInit.timebase = ADC_TimebaseCalc(0); + + // start ADC + ADC_Init(adcDriver, &adcInit); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeGetChannelCount___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // Return value to the managed application + stack.SetResult_I4(AdcChannelCount); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeGetMaxValue___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // Currently fixed at 12 bit so return 4095 = ((2^12) - 1) + stack.SetResult_I4(4095); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeGetMinValue___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + stack.SetResult_I4(0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + int mode = stack.Arg1().NumericByRef().s4; + + // Only support Single ended mode for now + stack.SetResult_Boolean((mode == (int)AdcChannelMode_SingleEnded)); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeGetResolutionInBits___I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // Fixed at 12 bit + stack.SetResult_I4(12); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_adc_native_System_Device_Adc_AdcController::NativeInit___VOID(CLR_RT_StackFrame &stack) +{ + (void)stack; + + NANOCLR_HEADER(); + + // all required initialization for ADC is already handled in OpenChannel call + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_target.h new file mode 100644 index 0000000000..eb39c07f6d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/sys_dev_adc_native_target.h @@ -0,0 +1,39 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_ADC_NATIVE_TARGET_H +#define SYS_DEV_ADC_NATIVE_TARGET_H + +#include +#include +#include +#include "em_cmu.h" + +#include + +// set missing defines +#ifndef GECKO_USE_ADC0 +#define GECKO_USE_ADC0 FALSE +#endif +#ifndef GECKO_USE_ADC1 +#define GECKO_USE_ADC1 FALSE +#endif +#ifndef GECKO_USE_ADC2 +#define GECKO_USE_ADC2 FALSE +#endif +#ifndef GECKO_USE_ADC3 +#define GECKO_USE_ADC3 FALSE +#endif + +typedef struct +{ + uint8_t adcIndex; + ADC_PosSel_TypeDef posSel; +} NF_PAL_ADC_PORT_PIN_CHANNEL; + +extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; +extern const int AdcChannelCount; + +#endif // SYS_DEV_ADC_NATIVE_TARGET_H From 69a9f3b6df35cc49f0b031d038727e88503d7eca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Jul 2022 17:17:14 +0100 Subject: [PATCH 082/572] Ported changes from mainstream SPI implementation --- .../target_com_sky_nf_dev_spi_config.cpp | 4 +- .../com_sky_nf_dev_spi_native_target.h | 67 ++++++++++++------- .../sys_dev_spi_native_target.h | 7 ++ 3 files changed, 52 insertions(+), 26 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp index 7666e595cb..e762102b29 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp @@ -3,7 +3,7 @@ // See LICENSE file in the project root for full license information. // -#include +#include ////////// // SPI1 // @@ -17,4 +17,4 @@ // SPI1_SCK in PC15, location 3 // CS: PC14 (not used in SPI configuration) -SPI_CONFIG_PINS(1, gpioPortC, 15, 3, gpioPortA, 14, 6, 0, 0, 0) +SPI_CONFIG_PINS(1, gpioPortC, 15, 3, gpioPortA, 14, 6, 0, 0, 0) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h index 047c7a4a55..bb77b1f84d 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h @@ -9,6 +9,7 @@ #include #include +#include <../System.Device.Spi/nf_gecko_spi_driver.h> #define SL_SPIDRV_EXP_BITRATE 1000000 @@ -61,11 +62,9 @@ #define GECKO_USE_SPI5 FALSE #endif -// struct representing the SPI bus struct NF_PAL_SPI { int BusIndex; - SPIDRV_Handle_t Handle; SpiBusConfiguration BusConfiguration; SPI_Callback Callback; @@ -81,6 +80,9 @@ struct NF_PAL_SPI // -1 = Chip Select is not handled | >0 Chip Select is to be controlled with this GPIO int32_t ChipSelect; + + // DMA transfer control + Gecko_SpiDriver *Driver; }; //////////////////////////////////////////// @@ -110,25 +112,42 @@ extern NF_PAL_SPI SPI5_PAL; // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations -#define SPI_CONFIG_PINS(num, port_location_mosi, port_location_miso, port_location_clk) \ - \ - void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit) \ +#define SPI_CONFIG_PINS( \ + num, \ + gpio_port_sck, \ + sck_pin, \ + sck_port_location, \ + gpio_port_mosi, \ + mosi_pin, \ + mosi_port_location, \ + gpio_port_miso, \ + miso_pin, \ + miso_port_location) \ + void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig) \ { \ - spiInit.portLocationTx = port_location_mosi; \ - spiInit.portLocationClk = port_location_clk; \ - if (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 0); \ + SPI##num##_PAL.Driver->Usart->ROUTELOC0 = (SPI##num##_PAL.Driver->Usart->ROUTELOC0 & \ + ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ + _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ + mosi_port_location | \ + (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ + if (spiDeviceConfig.BusConfiguration == SpiBusConfiguration_HalfDuplex) \ { \ - spiInit.portLocationRx = port_location_miso; \ + SPI##num##_PAL.Driver->Usart->CTRL |= USART_CTRL_LOOPBK; \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ } \ - if (spiDeviceConfig.DeviceChipSelect >= 0) \ + else \ { \ - if (spiDeviceConfig.ChipSelectActive) \ - { \ - } \ - else \ - { \ - } \ + GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ + GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 0); \ + SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= \ + (miso_port_location) | (mosi_port_location << _USART_ROUTELOC0_TXLOC_SHIFT); \ } \ + SPI##num##_PAL.Driver->Usart->ROUTEPEN = \ + USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_TXPEN | \ + (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ + ? USART_ROUTEPEN_RXPEN \ + : 0; \ } #else @@ -139,11 +158,11 @@ extern NF_PAL_SPI SPI5_PAL; // when an SPI is defined the declarations below will have the real function/configuration // // in the target folder @ target_windows_devices_spi_config.cpp // ////////////////////////////////////////////////////////////////////////////////////////////// -void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); -void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, SPIDRV_Init_t &spiInit); - -#endif // COM_SKY_NF_DEV_SPI_NATIVE_TARGET_H +void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); + +#endif // SYS_DEV_SPI_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h new file mode 100644 index 0000000000..72756c9502 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/sys_dev_spi_native_target.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// using this to "map" the include file with the standard name +#include "com_sky_nf_dev_spi_native_target.h" \ No newline at end of file From 229d8918267b2bc744cbccfacca0adbc8907eca4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 28 Jul 2022 18:51:12 +0100 Subject: [PATCH 083/572] Implement native support for Sys.Devices.Pwm - Add native drivers using Gecko SDK. - Update build system. - Improve PWM config. --- CMake/Modules/FindSystem.Device.Pwm.cmake | 3 +- CMakePresets.json | 2 +- .../target_system_device_pwm_config.cpp | 17 + .../_common/autogen/sl_device_init_clocks.c | 2 + ...wm_native_System_Device_Pwm_PwmChannel.cpp | 441 ++++++++++++++++++ .../sys_dev_pwm_native_target.h | 45 ++ .../SiliconLabs/_nanoCLR/targetHAL.cpp | 8 + .../SiliconLabs/_nanoCLR/target_platform.h.in | 4 +- 8 files changed, 518 insertions(+), 4 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_target.h diff --git a/CMake/Modules/FindSystem.Device.Pwm.cmake b/CMake/Modules/FindSystem.Device.Pwm.cmake index c018c6434b..5371304b0e 100644 --- a/CMake/Modules/FindSystem.Device.Pwm.cmake +++ b/CMake/Modules/FindSystem.Device.Pwm.cmake @@ -22,7 +22,8 @@ set(System.Device.Pwm_SRCS sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp - + + target_system_device_pwm_config.cpp ) foreach(SRC_FILE ${System.Device.Pwm_SRCS}) diff --git a/CMakePresets.json b/CMakePresets.json index 6618bee9d0..8b7c88a04d 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -296,7 +296,7 @@ "API_System.Device.Gpio": "ON", "API_System.Device.Spi": "ON", "API_System.Device.I2c": "ON", - "API_System.Device.Pwm": "OFF", + "API_System.Device.Pwm": "ON", "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "ON", "API_System.Device.Dac": "OFF", diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..aadc62f3bd --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortC, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c index cd38b3777c..30080ed43b 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c @@ -13,6 +13,8 @@ sl_status_t sl_device_init_clocks(void) CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); #if defined(_CMU_LFCCLKSEL_MASK) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp new file mode 100644 index 0000000000..c49e1820d4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp @@ -0,0 +1,441 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#define CAP_COMPARE_CHANNELS_COUNT 4 + +// flag to prevent duplicate initialization +static bool DcRegulatorInit = false; + +NF_PAL_PWM_INSTANCE PwmInstances[PWM_TIMERS_COUNT] = { + {false, false, {255, 255, 255}}, + {false, false, {255, 255, 255}}, + {false, false, {255, 255, 255}}}; + +uint32_t ComputeDutyCycle(uint32_t currentCount, uint32_t dutyCycle) +{ + // Return a duty cycle in the range of the current timer duty resolution + uint32_t dutyCycleValue = + currentCount * dutyCycle / Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::CONST_DutyCycleFactor; + + return dutyCycleValue; +} + +int32_t GetPwmConfigFromPin(int pin) +{ + if (pin >= -1) + { + for (int i = 0; i < PwmConfigCount; i++) + { + if (GET_ENCODED_PWM_PORT_PIN(PwmPortPinConfig[i]) == pin) + { + return i; + } + } + } + + return -1; +} + +int32_t GetPwmConfigFromTimeAndChannel(int timerId, int channelId) +{ + for (int i = 0; i < PwmConfigCount; i++) + { + if (PwmPortPinConfig[i].wtimerIndex == timerId && PwmPortPinConfig[i].capCompIndex == channelId) + { + return i; + } + } + + return -1; +} + +int32_t GetPwmConfig(int pinNumber, int timerId, int channelId) +{ + int32_t configIndex = -1; + + if (pinNumber != -1) + { + configIndex = GetPwmConfigFromPin(pinNumber); + } + + if (configIndex == -1) + { + configIndex = GetPwmConfigFromTimeAndChannel(timerId, channelId); + } + + return configIndex; +} + +TIMER_TypeDef *GetPwmTimer(int timerId) +{ + switch (timerId) + { + + case 0: + return WTIMER0; + + case 1: + return WTIMER1; + + case 2: + return WTIMER2; + + default: + return NULL; + } +} + +CMU_Clock_TypeDef_enum GetPwmClock(int timerId) +{ + switch (timerId) + { + + case 0: + return cmuClock_WTIMER0; + + case 1: + return cmuClock_WTIMER1; + + case 2: + return cmuClock_WTIMER1; + + default: + return (CMU_Clock_TypeDef_enum)-1; + } +} + +void StopChannel(int32_t configIndex) +{ + bool okToDisable; + const NF_PAL_PWM_PORT_PIN_CONFIG *pwmConfig; + + // grab PWM config + pwmConfig = &PwmPortPinConfig[configIndex]; + + // Stops PWM output on the channel associated with the selected pin + // disable CC route pin + GetPwmTimer(pwmConfig->wtimerIndex)->ROUTEPEN &= ~(TIMER_ROUTEPEN_CC0PEN << pwmConfig->capCompIndex); + + // reset GPIO + GPIO_PinModeSet(pwmConfig->gpioPort, pwmConfig->portPin, gpioModeDisabled, 0); + + // free channel + PwmInstances[pwmConfig->wtimerIndex].ChannelArray[pwmConfig->capCompIndex] = 255; + + // check if we can disable the timer + okToDisable = true; + for (int i = 0; i < PWM_CHANNEL_COUNT; i++) + { + if (PwmInstances[pwmConfig->wtimerIndex].ChannelArray[i] != 255) + { + // we can't disable the timer yet + okToDisable = false; + break; + } + } + + if (okToDisable) + { + // disable timer + TIMER_Reset(GetPwmTimer(pwmConfig->wtimerIndex)); + + // disable clock for WTIMER module + CMU_ClockEnable(GetPwmClock(pwmConfig->wtimerIndex), false); + + // lower flag about time being configured + PwmInstances[pwmConfig->wtimerIndex].IsConfigured = false; + } +} + +void DeInitPwm() +{ + for (int i = 0; i < PWM_TIMERS_COUNT; i++) + { + for (int j = 0; j < PWM_CHANNEL_COUNT; j++) + { + if (PwmInstances[i].ChannelArray[j] != 255) + { + StopChannel(GetPwmConfigFromPin(PwmInstances[i].ChannelArray[j])); + } + } + } +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeInit___VOID(CLR_RT_StackFrame &stack) +{ + int32_t timerId; + int32_t pinNumber; + int32_t channelId; + int32_t configIndex; + int32_t desiredFrequency; + PwmPulsePolarity polarity; + // int32_t routeLocationBit; + TIMER_InitCC_TypeDef timerCCInit; + const NF_PAL_PWM_PORT_PIN_CONFIG *pwmConfig; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // reset config for NOT FOUND + configIndex = -1; + + if (!DcRegulatorInit) + { + // init DCDC regulator with kit specific parameters + EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; + EMU_DCDCInit(&dcdcInit); + } + + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + channelId = pThis[FIELD___channelNumber].NumericByRef().s4; + desiredFrequency = pThis[FIELD___frequency].NumericByRef().s4; + polarity = (PwmPulsePolarity)(pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___polarity] + .NumericByRef() + .u4); + + // try to find config + configIndex = GetPwmConfig(pinNumber, timerId, channelId); + + if (configIndex == -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // grab PWM config + pwmConfig = &PwmPortPinConfig[configIndex]; + + // check if this channel is already in use + if (PwmInstances[pwmConfig->wtimerIndex].ChannelArray[pwmConfig->capCompIndex] != 255) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PIN_UNAVAILABLE); + } + + // store encoded GPIO port and pin number + pThis[FIELD___pinNumber].NumericByRef().s4 = GET_ENCODED_PWM_PORT_PIN(PwmPortPinConfig[configIndex]); + PwmInstances[pwmConfig->wtimerIndex].ChannelArray[pwmConfig->capCompIndex] = + pThis[FIELD___pinNumber].NumericByRef().s4; + + // check if timer needs to be initialized + if (!PwmInstances[pwmConfig->wtimerIndex].IsConfigured) + { + // timer is not configured, configure it + + // Enable clock for WTIMER module + CMU_ClockEnable(GetPwmClock(timerId), true); + + // set top value to max PWM_FREQ frequency + TIMER_TopSet(GetPwmTimer(timerId), CMU_ClockFreqGet(GetPwmClock(timerId)) / desiredFrequency); + + // set duty cycle to 100% + TIMER_CompareSet(WTIMER0, 0, TIMER_TopGet(WTIMER0) - 1); + + // Initialize the timer + TIMER_Init_TypeDef timerInit = TIMER_INIT_DEFAULT; + TIMER_Init(GetPwmTimer(pwmConfig->wtimerIndex), &timerInit); + + // set flag to indicate that timer is configured + PwmInstances[pwmConfig->wtimerIndex].IsConfigured = true; + } + + // config GPIO + GPIO_PinModeSet(pwmConfig->gpioPort, pwmConfig->portPin, gpioModePushPull, polarity); + + // Route WTIMER CC to location + GetPwmTimer(pwmConfig->wtimerIndex)->ROUTELOC0 |= pwmConfig->capCompLocation << pwmConfig->capCompIndex * 8; + + // Configure WTIMER Compare/Capture for output compare + // Use PWM mode and config polarity too + timerCCInit = TIMER_INITCC_DEFAULT; + timerCCInit.mode = timerCCModePWM; + timerCCInit.outInvert = (polarity == PwmPulsePolarity_ActiveLow); + TIMER_InitCC(GetPwmTimer(pwmConfig->wtimerIndex), pwmConfig->capCompIndex, &timerCCInit); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetDesiredFrequency___VOID__I4( + CLR_RT_StackFrame &stack) +{ + uint32_t timerId; + int32_t desiredFrequency; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; + desiredFrequency = stack.Arg1().NumericByRef().s4; + + // parameter check + if (desiredFrequency < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Set top value to overflow at the desired PWM_FREQ frequency + TIMER_TopSet(GetPwmTimer(timerId), (CMU_ClockFreqGet(GetPwmClock(timerId)) / desiredFrequency) - 1); + + // store the frequency + pThis[FIELD___frequency].NumericByRef().s4 = desiredFrequency; + + stack.SetResult_R8((double)desiredFrequency); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetActiveDutyCyclePercentage___VOID__R8( + CLR_RT_StackFrame &stack) +{ + uint32_t pinNumber; + int32_t configIndex; + uint32_t dutyCycle; + const NF_PAL_PWM_PORT_PIN_CONFIG *pwmConfig; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // parameter check + if (stack.Arg1().NumericByRef().r8 < 0 || stack.Arg1().NumericByRef().r8 > 1.0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + + // try to find config + configIndex = GetPwmConfigFromPin(pinNumber); + + // grab PWM config + pwmConfig = &PwmPortPinConfig[configIndex]; + + dutyCycle = (uint32_t)(stack.Arg1().NumericByRef().r8 * CONST_DutyCycleFactor); + + // set compare value for initial duty cycle + TIMER_CompareSet( + GetPwmTimer(pwmConfig->wtimerIndex), + pwmConfig->capCompIndex, + ComputeDutyCycle(TIMER_TopGet(GetPwmTimer(pwmConfig->wtimerIndex)), dutyCycle)); + + // store the new duty cycle + pThis[FIELD___dutyCycle].NumericByRef().u4 = dutyCycle; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeStart___VOID(CLR_RT_StackFrame &stack) +{ + uint32_t pinNumber; + int32_t configIndex; + const NF_PAL_PWM_PORT_PIN_CONFIG *pwmConfig; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + + // try to find config + configIndex = GetPwmConfigFromPin(pinNumber); + + // grab PWM config + pwmConfig = &PwmPortPinConfig[configIndex]; + + // enable CC route pin so the GPIO get driven by the timer + GetPwmTimer(pwmConfig->wtimerIndex)->ROUTEPEN |= TIMER_ROUTEPEN_CC0PEN << pwmConfig->capCompIndex; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeStop___VOID(CLR_RT_StackFrame &stack) +{ + uint32_t pinNumber; + int32_t configIndex; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + + // try to find config + configIndex = GetPwmConfigFromPin(pinNumber); + + StopChannel(configIndex); + + // "dispose" pin number + pThis[FIELD___pinNumber].NumericByRef().s4 = -1; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::DisposeNative___VOID(CLR_RT_StackFrame &stack) +{ + uint32_t pinNumber; + int32_t configIndex; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + + // try to find config + configIndex = GetPwmConfigFromPin(pinNumber); + + if (configIndex > -1) + { + // hasn't been disposed yet, so stop the channel + StopChannel(configIndex); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::GetChannel___STATIC__I4__I4__I4( + CLR_RT_StackFrame &stack) +{ + int32_t configIndex; + const NF_PAL_PWM_PORT_PIN_CONFIG *pwmConfig; + + NANOCLR_HEADER(); + + // Get pin and potential TIM + int pinNumber = stack.Arg0().NumericByRef().s4; + + // try to find config + configIndex = GetPwmConfigFromPin(pinNumber); + + if (configIndex > -1) + { + // grab PWM config + pwmConfig = &PwmPortPinConfig[configIndex]; + + // Check if the combination is ok and set the result + stack.SetResult_I4(pwmConfig->capCompIndex); + } + else + { + stack.SetResult_I4(-1); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_target.h new file mode 100644 index 0000000000..b85767bd8d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_target.h @@ -0,0 +1,45 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_PWM_NATIVE_TARGET_H +#define SYS_DEV_PWM_NATIVE_TARGET_H + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#define GET_ENCODED_PWM_PORT_PIN(pwmPPConfig) (int)pwmPPConfig.gpioPort * 16 + pwmPPConfig.portPin +#define PWM_CHANNEL_COUNT (3) +#define PWM_TIMERS_COUNT (3) + +typedef struct +{ + bool IsRunning; + bool IsConfigured; + uint8_t ChannelArray[PWM_CHANNEL_COUNT]; +} NF_PAL_PWM_INSTANCE; + +typedef struct +{ + uint8_t wtimerIndex; + uint8_t capCompIndex; + GPIO_Port_TypeDef gpioPort; + uint8_t portPin; + uint8_t capCompLocation; +} NF_PAL_PWM_PORT_PIN_CONFIG; + +extern const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[]; +extern const int PwmConfigCount; +// using the 1st three WTIMER instances for PWM +extern NF_PAL_PWM_INSTANCE PwmInstances[PWM_TIMERS_COUNT]; + +#endif // SYS_DEV_PWM_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index aa1de60837..7ab5297dae 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -24,6 +24,10 @@ // #include // #endif +#if (HAL_USE_PWM == TRUE) +extern void DeInitPwm(); +#endif + // global mutex protecting the internal state of the interpreter, including event flags // mutex_t interpreterGlobalMutex; @@ -278,6 +282,10 @@ void nanoHAL_Uninitialize() // #endif +#if (HAL_USE_PWM == TRUE) + DeInitPwm(); +#endif + CPU_GPIO_Uninitialize(); Events_Uninitialize(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 86d7716d84..1b2657dc09 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -15,10 +15,10 @@ #define NF_FEATURE_USE_SPIFFS @NF_FEATURE_USE_SPIFFS_OPTION@ #define HAL_USE_RTC @HAL_USE_RTC_OPTION@ -// // takes care of enabling the HAL subsystems required for API options +// takes care of enabling the HAL subsystems required for API options // #define HAL_USE_SPI @HAL_USE_SPI_OPTION@ // #define HAL_USE_I2C @HAL_USE_I2C_OPTION@ -// #define HAL_USE_PWM @HAL_USE_PWM_OPTION@ +#define HAL_USE_PWM @HAL_USE_PWM_OPTION@ // #define HAL_USE_ADC @HAL_USE_ADC_OPTION@ // #define HAL_USE_DAC @HAL_USE_DAC_OPTION@ // #define HAL_USE_UART @HAL_USE_UART_OPTION@ From 4f75948d373cb8418e2be4da3379a9c62b822a7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 28 Jul 2022 18:58:39 +0100 Subject: [PATCH 084/572] Add list of PWM GPIOs - Fixed declaration of 2nh PWM channel. --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md | 6 ++++++ .../SL_STK3701A/target_system_device_pwm_config.cpp | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index a0e0016067..2ec34ed193 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -19,3 +19,9 @@ ADC has enabled the following channels: :warning: Vref is 2.5V for all channels, except for VCC which is 5V. + +## PWM + +PWM has enabled the following GPIOs: +0 - PC1 (pin 15 on the expansion header) +1 - PI1 (through hole connector at bottom side) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp index aadc62f3bd..7653e6d1c4 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_pwm_config.cpp @@ -10,7 +10,7 @@ const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { // using WTIMER0, CC0, PC1, location 7 {0, 0, gpioPortC, 1, 7}, // using WTIMER1, CC2, PI1, location 5 - {1, 2, gpioPortC, 1, 5}, + {1, 2, gpioPortI, 1, 5}, }; From d45746d3e360449e17c533fef6d663ad44880680 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 3 Aug 2022 12:43:20 +0100 Subject: [PATCH 085/572] Complete rework of SPI driver in order to use DMA --- CMake/Modules/FindGecko_SDK.cmake | 4 - .../config/sl_board_control_config.h | 2 +- .../target_system_device_spi_config.cpp | 20 +- .../target_system_device_spi_config.h | 1 + .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 258 ++- .../System.Device.Spi/nf_gecko_spi_driver.cpp | 1517 ++++++++++++++--- .../System.Device.Spi/nf_gecko_spi_driver.h | 213 ++- .../sys_dev_spi_native_target.h | 57 +- .../SiliconLabs/_nanoCLR/targetHAL.cpp | 38 +- .../SiliconLabs/_nanoCLR/target_platform.h.in | 2 +- 10 files changed, 1667 insertions(+), 445 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index f75621db9f..120417bd00 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -34,8 +34,6 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolc list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/system/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/sleeptimer/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/inc) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/spidrv/inc) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/spidrv/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) @@ -75,7 +73,6 @@ set(gecko_sdk_srcs dmactrl.c dmadrv.c uartdrv.c - spidrv.c sl_device_init_dcdc_s1.c sl_device_init_emu_s1.c @@ -138,7 +135,6 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") ${gecko_sdk_SOURCE_DIR}/platform/emdrv/dmadrv/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/gpiointerrupt/src ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/src - ${gecko_sdk_SOURCE_DIR}/platform/emdrv/spidrv/src ${gecko_sdk_SOURCE_DIR}/platform/emlib/src ${gecko_sdk_SOURCE_DIR}/platform/service/device_init/src ${gecko_sdk_SOURCE_DIR}/platform/service/iostream/src diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h index 498641cd43..5796117234 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_board_control_config.h @@ -39,7 +39,7 @@ // Enable Display // Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 0 +#define SL_BOARD_ENABLE_DISPLAY 1 // Enable Relative Humidity and Temperature sensor // Default: 0 diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp index 78f70b20e7..e35066d900 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.cpp @@ -5,6 +5,20 @@ #include +////////// +// SPI0 // +////////// + +// Note: on SL_STK3701A SPI0 is available at EXP connector + +// pin configuration for SPI0 (EMC encoded "port location") +// SPI0_SCK: PE12, location 0, EXP Header Pin 8 +// SPI0_MOSI: PE10, location 0, EXP Header Pin 4 +// SPI0_MISO: PE11, location 0, EXP Header Pin 6 +// CS: PE13, EXP Header Pin 10 + +INIT_SPI_CONFIG(0, 0, 0, 0) + ////////// // SPI1 // ////////// @@ -12,9 +26,9 @@ // Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display // pin configuration for SPI1 (EMC encoded "port location") -// SPI1_MOSI in PA14, location 6 +// SPI1_SCK: PC15, location 3 +// SPI1_MOSI: PA14, location 6 // SPI1_MISO: (not used for LCD) -// SPI1_SCK in PC15, location 3 // CS: PC14 (not used in SPI configuration) -SPI_CONFIG_PINS(1, gpioPortC, 15, 3, gpioPortA, 14, 6, 0, 0, 0) +INIT_SPI_CONFIG(1, 3, 6, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h index 56b68d1d4e..6dfccbd22e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h @@ -3,4 +3,5 @@ // See LICENSE file in the project root for full license information. // +#define GECKO_USE_SPI0 TRUE #define GECKO_USE_SPI1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 9be01cc1f3..76c5708c5e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -28,21 +28,24 @@ NF_PAL_SPI SPI5_PAL; #endif #if defined(EUSART_PRESENT) -#error "Only USART type is supported. Drivar can't handle EUSART." +#error "Only USART type is supported. Driver can't handle EUSART." #endif -static USART_TypeDef *GetUsartFromHandle(struct Gecko_SpiDriver *handle) +extern void GetIoLine(int16_t pinNumber, GPIO_Port_TypeDef *port, uint32_t *portPin); + +static USART_TypeDef *GetUsartFromHandle(NF_SpiDriver_Handle_t handle) { - return handle->Usart; + return handle->peripheral.usartPort; } -static void CompleteTransfer(struct Gecko_SpiDriver *driver) +static void CompleteTransfer(NF_SpiDriver_Handle_t handle) { - SpiRelease(driver); + (void)handle; + // SpiRelease(driver); } // Callback used when a async transfer operation completes -static void SpiTransferCompleteCallback(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred) +static void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) { (void)transferStatus; (void)itemsTransferred; @@ -51,44 +54,44 @@ static void SpiTransferCompleteCallback(struct Gecko_SpiDriver *driver, Ecode_t NF_PAL_SPI *palSpi = NULL; - // Find the NF_PAL_SPI* for driver + // Find the NF_PAL_SPI* for handle #if GECKO_USE_SPI0 == TRUE - if (GetUsartFromHandle(driver) == USART0) + if (GetUsartFromHandle(handle) == USART0) { palSpi = &SPI0_PAL; } #endif #if GECKO_USE_SPI1 == TRUE - if (GetUsartFromHandle(driver) == USART1) + if (GetUsartFromHandle(handle) == USART1) { palSpi = &SPI1_PAL; } #endif #if GECKO_USE_SPI2 == TRUE - if (GetUsartFromHandle(driver) == USART2) + if (GetUsartFromHandle(handle) == USART2) { palSpi = &SPI2_PAL; } #endif #if GECKO_USE_SPI3 == TRUE - if (GetUsartFromHandle(driver) == USART3) + if (GetUsartFromHandle(handle) == USART3) { palSpi = &SPI3_PAL; } #endif #if GECKO_USE_SPI4 == TRUE - if (GetUsartFromHandle(driver) == USART4) + if (GetUsartFromHandle(handle) == USART4) { palSpi = &SPI4_PAL; } #endif #if GECKO_USE_SPI5 == TRUE - if (GetUsartFromHandle(driver) == USART5) + if (GetUsartFromHandle(handle) == USART5) { palSpi = &SPI5_PAL; } @@ -106,9 +109,9 @@ static void SpiTransferCompleteCallback(struct Gecko_SpiDriver *driver, Ecode_t // if (palSpi->busConfiguration) // { // // half duplex operation, clear output enable bit - // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - SpiReceive(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + NF_SpiDriver_Receive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); } else { @@ -187,27 +190,27 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) } // Give a complete low-level SPI configuration from passed SPI_DEVICE_CONFIGURATION -void GetSPIConfig(const SPI_DEVICE_CONFIGURATION &config, USART_InitSync_TypeDef *uartInit) +void GetSpiConfig(const SPI_DEVICE_CONFIGURATION &config, NF_SpiDriver_Init_t &initSpiData) { // SPI mode (matches SPIDRV_ClockMode_t) - uartInit->baudrate = config.Clock_RateHz; + initSpiData.bitRate = config.Clock_RateHz; switch (config.Spi_Mode) { case SpiMode_Mode0: - uartInit->clockMode = usartClockMode0; + initSpiData.clockMode = spidrvClockMode0; break; case SpiMode_Mode1: - uartInit->clockMode = usartClockMode1; + initSpiData.clockMode = spidrvClockMode1; break; case SpiMode_Mode2: - uartInit->clockMode = usartClockMode2; + initSpiData.clockMode = spidrvClockMode2; break; case SpiMode_Mode3: - uartInit->clockMode = usartClockMode3; + initSpiData.clockMode = spidrvClockMode3; break; default: @@ -215,8 +218,11 @@ void GetSPIConfig(const SPI_DEVICE_CONFIGURATION &config, USART_InitSync_TypeDef break; } + initSpiData.csControl = spidrvCsControlApplication; + initSpiData.dummyTxValue = 0; // Sets the order of bytes transmission : MSB first or LSB first - uartInit->msbf = config.DataOrder16 == DataBitOrder_MSB; + initSpiData.bitOrder = config.DataOrder16 == DataBitOrder_MSB ? spidrvBitOrderMsbFirst : spidrvBitOrderLsbFirst; + initSpiData.frameLength = config.MD16bits ? 16 : 8; } // Performs a read/write operation on 8-bit word data. @@ -276,7 +282,8 @@ HRESULT CPU_SPI_nWrite_nRead( // === Setup the operation and init buffers === palSpi->BusIndex = sdev.Spi_Bus; - palSpi->Driver->DataIs16bits = wrc.Bits16ReadWrite; + // adjust the bus index to match the PAL struct + NF_SpiDriver_SetFramelength(palSpi->Handle, wrc.Bits16ReadWrite ? 16 : 8); // set bus config flag busConfigIsHalfDuplex = (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex); @@ -296,16 +303,11 @@ HRESULT CPU_SPI_nWrite_nRead( } } - if (!SpiStart(palSpi->Driver)) - { - NANOCLR_SET_AND_LEAVE(CLR_E_TOO_MANY_OPEN_HANDLES); - } - // if CS is to be controlled by the driver, set the GPIO if (palSpi->ChipSelect >= 0) { // assert pin based on CS active level - CPU_GPIO_SetPinState(GPIO_PORT(palSpi->ChipSelect), (GpioPinValue)sdev.ChipSelectActive); + CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); } if (sync) @@ -319,8 +321,8 @@ HRESULT CPU_SPI_nWrite_nRead( { // Full duplex // Uses the largest buffer size as transfer size - SpiTransferBlocking( - palSpi->Driver, + NF_SpiDriver_TransferBlocking( + palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize); @@ -332,18 +334,18 @@ HRESULT CPU_SPI_nWrite_nRead( // if (busConfigIsHalfDuplex) // { // // half duplex operation, set output enable - // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; // } - SpiTransmitBlocking(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize); + NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); // receive operation // TODO // if (busConfigIsHalfDuplex) // { // // half duplex operation, set output enable - // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - SpiReceiveBlocking(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize); + NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } } else @@ -356,9 +358,9 @@ HRESULT CPU_SPI_nWrite_nRead( // if (busConfigIsHalfDuplex) // { // // half duplex operation, set output enable - // palSpi->Driver->spi->CR1 &= ~SPI_CR1_BIDIOE; + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - SpiReceiveBlocking(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize); + NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } else { @@ -367,13 +369,13 @@ HRESULT CPU_SPI_nWrite_nRead( if (busConfigIsHalfDuplex) { // half duplex operation, set output enable - // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; } - SpiTransmitBlocking(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize); + NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); } } - CompleteTransfer(palSpi->Driver); + CompleteTransfer(palSpi->Handle); // if CS is to be controlled by the driver, set the GPIO if (palSpi->ChipSelect >= 0) @@ -407,8 +409,8 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // Uses the largest buffer size as transfer size - SpiTransfer( - palSpi->Driver, + NF_SpiDriver_Transfer( + palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, @@ -423,11 +425,15 @@ HRESULT CPU_SPI_nWrite_nRead( if (busConfigIsHalfDuplex) { // // half duplex operation, set output enable - // palSpi->Driver->spi->CR1 |= SPI_CR1_BIDIOE; + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; } // receive operation will be started in the callback after the above completes - SpiTransmit(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize, SpiTransferCompleteCallback); + NF_SpiDriver_Transmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); } } else @@ -439,7 +445,11 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start receive - SpiReceive(palSpi->Driver, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + NF_SpiDriver_Receive( + palSpi->Handle, + palSpi->ReadBuffer, + palSpi->ReadSize, + SpiTransferCompleteCallback); } else { @@ -447,7 +457,11 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start send - SpiTransmit(palSpi->Driver, palSpi->WriteBuffer, palSpi->WriteSize, SpiTransferCompleteCallback); + NF_SpiDriver_Transmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); } } @@ -462,31 +476,11 @@ HRESULT CPU_SPI_nWrite_nRead( bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) { NF_PAL_SPI *palSpi = NULL; - USART_TypeDef *usart = NULL; - void (*configPinsHandler)(const struct SPI_DEVICE_CONFIGURATION &) = NULL; - - // create USART init struct with the defaults: - // ports and pins with "invalid" values - // always MASTER mode - // we'll be controlling CS programmatically - USART_InitSync_TypeDef configInit = { - usartDisable, - 0, - 1000000, - usartDatabits8, - true, - false, - usartClockMode0, - false, - 0, - false, - false, - false, -#if (_SILICON_LABS_32B_SERIES > 0) - 0, - 0 -#endif - }; + NF_SpiDriver_Init_t *initSpiData = NULL; + Ecode_t configResult; + GPIO_Port_TypeDef port; + uint32_t portPin; + void (*initSpiConfig)(NF_SpiDriver_Init_t &, bool) = NULL; // init the PAL struct for this SPI bus and assign the respective driver // all this occurs if not already done @@ -500,24 +494,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI0 == TRUE case 0: palSpi = &SPI0_PAL; - usart = USART0; - configPinsHandler = &ConfigPins_SPI0; + initSpiConfig = &InitSpiConfig0; break; #endif #if GECKO_USE_SPI1 == TRUE case 1: palSpi = &SPI1_PAL; - usart = USART1; - configPinsHandler = &ConfigPins_SPI1; + initSpiConfig = &InitSpiConfig1; break; #endif #if GECKO_USE_SPI2 == TRUE case 2: palSpi = &SPI2_PAL; - usart = USART2; - configPinsHandler = &ConfigPins_SPI2; + initSpiConfig = &InitSpiConfig2; break; #endif @@ -525,24 +516,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #if GECKO_USE_SPI3 == TRUE case 3: palSpi = &SPI3_PAL; - usart = USART3; - configPinsHandler = &ConfigPins_SPI3; + initSpiConfig = &InitSpiConfig3; break; #endif #if GECKO_USE_SPI4 == TRUE case 4: palSpi = &SPI4_PAL; - usart = USART4; - configPinsHandler = &ConfigPins_SPI4; + initSpiConfig = &InitSpiConfig4; break; #endif #if GECKO_USE_SPI5 == TRUE case 5: palSpi = &SPI5_PAL; - usart = USART5; - configPinsHandler = &ConfigPins_SPI5; + initSpiConfig = &InitSpiConfig5; break; #endif @@ -551,46 +539,50 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon return false; } - if (palSpi->Driver == NULL) + if (palSpi->Handle == NULL) { // allocate memory for the USART_InitSync_TypeDef - palSpi->Driver = (Gecko_SpiDriver *)platform_malloc(sizeof(Gecko_SpiDriver)); + palSpi->Handle = (NF_SpiDriver_Handle_t)platform_malloc(sizeof(NF_SpiDriver_HandleData_t)); // sanity check allocation - if (palSpi->Driver == NULL) + if (palSpi->Handle == NULL) { return false; } - memset(palSpi->Driver, 0, sizeof(Gecko_SpiDriver)); + memset(palSpi->Handle, 0, sizeof(NF_SpiDriver_HandleData_t)); - // allocate memory for the USART_InitSync_TypeDef - palSpi->Driver->Configuration = (USART_InitSync_TypeDef *)platform_malloc(sizeof(USART_InitSync_TypeDef)); + // allocate memory for the NF_SpiDriver_Init_t + initSpiData = (NF_SpiDriver_Init_t *)platform_malloc(sizeof(NF_SpiDriver_Init_t)); // sanity check allocation - if (palSpi->Driver->Configuration == NULL) + if (initSpiData == NULL) { - platform_free(palSpi->Driver); + platform_free(palSpi->Handle); return false; } - // copy init struct - memcpy(palSpi->Driver->Configuration, &configInit, sizeof(USART_InitSync_TypeDef)); + memset(initSpiData, 0, sizeof(NF_SpiDriver_Init_t)); - // set USART - palSpi->Driver->Usart = usart; + // call handler to configure pins + initSpiConfig(*initSpiData, busConfiguration.BusConfiguration == SpiBusConfiguration_HalfDuplex); // get the SPI configuration - GetSPIConfig(busConfiguration, palSpi->Driver->Configuration); + GetSpiConfig(busConfiguration, *initSpiData); - SpiDriverInit(palSpi->Driver); + configResult = NF_SpiDriver_Init(palSpi->Handle, initSpiData); + _ASSERTE(configResult == ECODE_OK); palSpi->ChipSelect = busConfiguration.DeviceChipSelect; - // call handler to configure pins - configPinsHandler(busConfiguration); + // setup GPIO for CS + if (busConfiguration.DeviceChipSelect >= 0) + { + GetIoLine(busConfiguration.DeviceChipSelect, &port, &portPin); + GPIO_PinModeSet(port, portPin, gpioModePushPull, busConfiguration.ChipSelectActive ? 0 : 1); + } } return true; @@ -598,6 +590,10 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon bool CPU_SPI_Uninitialize(uint8_t busIndex) { + NF_PAL_SPI *palSpi = NULL; + GPIO_Port_TypeDef port; + uint32_t portPin; + // get the PAL struct for the SPI bus switch (busIndex) { @@ -607,78 +603,41 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) #if GECKO_USE_SPI0 == TRUE case 0: - USART_Reset(UART0); - - // free memory - platform_free(SPI0_PAL.Driver->Configuration); - platform_free(SPI0_PAL.Driver); - - SPI0_PAL.Driver = NULL; + palSpi = &SPI0_PAL; break; #endif #if GECKO_USE_SPI1 == TRUE case 1: - USART_Reset(UART1); - - // free memory - platform_free(SPI1_PAL.Driver->Configuration); - platform_free(SPI1_PAL.Driver); - - SPI1_PAL.Driver = NULL; + palSpi = &SPI1_PAL; break; #endif #if GECKO_USE_SPI2 == TRUE case 2: - USART_Reset(UART2); - - // free memory - platform_free(SPI2_PAL.Driver->Configuration); - platform_free(SPI2_PAL.Driver); - - SPI2_PAL.Driver = NULL; + palSpi = &SPI2_PAL; break; #endif #if GECKO_USE_SPI3 == TRUE case 3: - USART_Reset(UART3); - - // free memory - platform_free(SPI3_PAL.Driver->Configuration); - platform_free(SPI3_PAL.Driver); - - SPI3_PAL.Driver = NULL; + palSpi = &SPI3_PAL; break; #endif #if GECKO_USE_SPI4 == TRUE case 4: - USART_Reset(UART4); - - // free memory - platform_free(SPI4_PAL.Driver->Configuration); - platform_free(SPI4_PAL.Driver); - - SPI4_PAL.Driver = NULL; - + palSpi = &SPI4_PAL; break; #endif #if GECKO_USE_SPI5 == TRUE case 5: - USART_Reset(UART5); - - // free memory - platform_free(SPI5_PAL.Driver->Configuration); - platform_free(SPI5_PAL.Driver); - - SPI5_PAL.Driver = NULL; + palSpi = &SPI5_PAL; break; #endif @@ -688,6 +647,21 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) return false; } + // reset GPIO for CS + if (palSpi->ChipSelect >= 0) + { + GetIoLine(palSpi->ChipSelect, &port, &portPin); + GPIO_PinModeSet(port, portPin, gpioModeInputPull, 0); + } + + NF_SpiDriver_DeInit(palSpi->Handle); + + // free memory + platform_free(palSpi->Handle->initData); + platform_free(palSpi->Handle); + + palSpi->Handle = NULL; + return true; } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp index eeb2861c5f..6e930f94a4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -6,134 +6,1214 @@ #include "nf_gecko_spi_driver.h" #if defined(EUSART_PRESENT) -#error "Only USART type is supported. Drivar can't handle EUSART." +#error "Only USART type is supported. Drivar can't driver EUSART." #endif -// Adds track for a new DMA request -void DmaRequestAdd(struct Gecko_SpiDriver *driver) +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "em_device.h" +#include "em_gpio.h" +#include "em_core.h" +#include "em_usart.h" +#include "dmadrv.h" +#include "nf_gecko_spi_driver.h" +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif +#include + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) +#define SPI_DMA_IRQ DMA_IRQn + +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) +#define SPI_DMA_IRQ LDMA_IRQn + +#else +#error "No valid SPIDRV DMA engine defined." +#endif + +#define EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET (3U) +#define EMDRV_SPIDRV_EUSART_FRAMELENGTH_REGVALUE_OFFSET (6U) + +// SPI Pins structure used when mapping from location to gpio port+pin. +typedef struct +{ + uint8_t mosiPort; + uint8_t mosiPin; + uint8_t misoPort; + uint8_t misoPin; + uint8_t clkPort; + uint8_t clkPin; + uint8_t csPort; + uint8_t csPin; +} SPI_Pins_t; + +static bool spidrvIsInitialized = false; + +static Ecode_t NF_SpiDriver_InitUsart(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData); + +static void BlockingComplete(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred); + +static Ecode_t ConfigGPIO(NF_SpiDriver_Handle_t handle, bool enable); + +static bool RxDMAComplete(unsigned int channel, unsigned int sequenceNo, void *userParam); + +static void StartReceiveDMA(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback); + +static void StartTransferDMA( + NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + NF_SpiDriver_Callback_t callback); + +static void StartTransmitDMA( + NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback); + +static Ecode_t TransferApiPrologue(NF_SpiDriver_Handle_t handle, void *buffer, int count); + +static Ecode_t TransferApiBlockingPrologue(NF_SpiDriver_Handle_t handle, void *buffer, int count); + +static void WaitForTransferCompletion(NF_SpiDriver_Handle_t handle); + +// +// Power management functions. +// +static void em1RequestAdd(NF_SpiDriver_Handle_t handle) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (handle->em1RequestCount == 0) + { + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + } + handle->em1RequestCount++; + CORE_EXIT_ATOMIC(); +#else + handle->em1RequestCount++; +#endif +} + +static void em1RequestRemove(NF_SpiDriver_Handle_t handle) +{ + EFM_ASSERT(handle->em1RequestCount > 0); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + handle->em1RequestCount--; + if (handle->em1RequestCount == 0) + { + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + } + CORE_EXIT_ATOMIC(); +#else + handle->em1RequestCount--; +#endif +} + +static void emRequestInit(NF_SpiDriver_Handle_t handle) +{ + handle->em1RequestCount = 0; +} + +static void emRequestDeinit(NF_SpiDriver_Handle_t handle) +{ + if (handle->em1RequestCount > 0) + { + handle->em1RequestCount = 1; + em1RequestRemove(handle); + } +} + +// +// +// Initialize an SPI driver instance. +// +// @param[out] handle Pointer to an SPI driver handle; refer to @ref +// NF_SpiDriver_Handle_t. +// @param[in] initData Pointer to an initialization data structure; +// refer to @ref NF_SpiDriver_Init. +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate +// SPIDRV @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_Init(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData) +{ + return NF_SpiDriver_InitUsart(handle, initData); +} + +// +// +// Initialize an SPI driver usart instance. +// +// @param[out] handle Pointer to an SPI driver handle; refer to @ref +// NF_SpiDriver_Handle_t. +// +// @param[in] initData Pointer to an initialization data structure; +// refer to @ref NF_SpiDriver_Init. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate +// SPIDRV @ref Ecode_t is returned. +// +static Ecode_t NF_SpiDriver_InitUsart(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + USART_InitSync_TypeDef usartInit = USART_INITSYNC_DEFAULT; +#if defined(_SILICON_LABS_32B_SERIES_2) + int8_t spiPortNum = -1; +#endif + + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if (initData == NULL) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(NF_SpiDriver_HandleData_t)); + emRequestInit(handle); + + if (0) + { +#if defined(USART0) + } + else if ((USART_TypeDef *)initData->port == USART0) + { + handle->usartClock = cmuClock_USART0; + handle->txDMASignal = dmadrvPeripheralSignal_USART0_TXBL; +#if defined(_SILICON_LABS_32B_SERIES_2) + handle->rxDMASignal = dmadrvPeripheralSignal_USART0_RXDATAV; + spiPortNum = 0; +#else + handle->rxDMASignal = dmadrvPeripheralSignal_USART0_RXDATAV; +#endif +#endif +#if defined(USART1) + } + else if ((USART_TypeDef *)initData->port == USART1) + { + handle->usartClock = cmuClock_USART1; + handle->txDMASignal = dmadrvPeripheralSignal_USART1_TXBL; +#if defined(_SILICON_LABS_32B_SERIES_2) + handle->rxDMASignal = dmadrvPeripheralSignal_USART1_RXDATAV; + spiPortNum = 1; +#else + handle->rxDMASignal = dmadrvPeripheralSignal_USART1_RXDATAV; +#endif +#endif +#if defined(USART2) + } + else if ((USART_TypeDef *)initData->port == USART2) + { + handle->usartClock = cmuClock_USART2; + handle->txDMASignal = dmadrvPeripheralSignal_USART2_TXBL; +#if defined(_SILICON_LABS_32B_SERIES_2) + handle->rxDMASignal = dmadrvPeripheralSignal_USART2_RXDATAV; + spiPortNum = 2; +#else + handle->rxDMASignal = dmadrvPeripheralSignal_USART2_RXDATAV; +#endif +#endif +#if defined(USART3) + } + else if ((USART_TypeDef *)initData->port == USART3) + { + handle->usartClock = cmuClock_USART3; + handle->txDMASignal = dmadrvPeripheralSignal_USART3_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USART3_RXDATAV; +#if defined(_SILICON_LABS_32B_SERIES_2) + spiPortNum = 3; +#endif +#endif +#if defined(USART4) + } + else if ((USART_TypeDef *)initData->port == USART4) + { + handle->usartClock = cmuClock_USART4; + handle->txDMASignal = dmadrvPeripheralSignal_USART4_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USART4_RXDATAV; +#if defined(_SILICON_LABS_32B_SERIES_2) + spiPortNum = 4; +#endif +#endif +#if defined(USART5) + } + else if ((USART_TypeDef *)initData->port == USART5) + { + handle->usartClock = cmuClock_USART5; + handle->txDMASignal = dmadrvPeripheralSignal_USART5_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USART5_RXDATAV; +#if defined(_SILICON_LABS_32B_SERIES_2) + spiPortNum = 5; +#endif +#endif +#if defined(USARTRF0) + } + else if ((USART_TypeDef *)initData->port == USARTRF0) + { + handle->usartClock = cmuClock_USARTRF0; + handle->txDMASignal = dmadrvPeripheralSignal_USARTRF0_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USARTRF0_RXDATAV; +#endif +#if defined(USARTRF1) + } + else if ((USART_TypeDef *)initData->port == USARTRF1) + { + handle->usartClock = cmuClock_USARTRF1; + handle->txDMASignal = dmadrvPeripheralSignal_USARTRF1_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USARTRF1_RXDATAV; +#endif + } + else + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + handle->peripheral.usartPort = (USART_TypeDef *)initData->port; + handle->peripheralType = spidrvPeripheralTypeUsart; + handle->initData = initData; + + if (initData->bitOrder == spidrvBitOrderMsbFirst) + { + usartInit.msbf = true; + } + + if (initData->clockMode == spidrvClockMode0) + { + usartInit.clockMode = usartClockMode0; + } + else if (initData->clockMode == spidrvClockMode1) + { + usartInit.clockMode = usartClockMode1; + } + else if (initData->clockMode == spidrvClockMode2) + { + usartInit.clockMode = usartClockMode2; + } + else if (initData->clockMode == spidrvClockMode3) + { + usartInit.clockMode = usartClockMode3; + } + else + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + usartInit.master = true; + usartInit.baudrate = initData->bitRate; + +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->usartClock, true); + + if ((initData->frameLength < 4U) || (initData->frameLength > 16U)) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + uint32_t databits = initData->frameLength - 4U + _USART_FRAME_DATABITS_FOUR; + usartInit.databits = (USART_Databits_TypeDef)databits; + + USART_InitSync((USART_TypeDef *)initData->port, &usartInit); + + if (initData->csControl == spidrvCsControlAuto) + { + handle->peripheral.usartPort->CTRL |= USART_CTRL_AUTOCS; + } + + if (initData->csControl == spidrvCsControlAuto) + { + // SPI 4 wire mode +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.usartPort->ROUTELOC0 = + (handle->peripheral.usartPort->ROUTELOC0 & ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | + _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | + (initData->portLocationTx << _USART_ROUTELOC0_TXLOC_SHIFT) | + (initData->portLocationRx << _USART_ROUTELOC0_RXLOC_SHIFT) | + (initData->portLocationClk << _USART_ROUTELOC0_CLKLOC_SHIFT) | + (initData->portLocationCs << _USART_ROUTELOC0_CSLOC_SHIFT); + + handle->peripheral.usartPort->ROUTEPEN = + USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_CSPEN; +#elif defined(_GPIO_USART_ROUTEEN_MASK) + GPIO->USARTROUTE[spiPortNum].ROUTEEN = + GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN | GPIO_USART_ROUTEEN_CLKPEN | GPIO_USART_ROUTEEN_CSPEN; + + GPIO->USARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx << _GPIO_USART_TXROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinTx << _GPIO_USART_TXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx << _GPIO_USART_RXROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinRx << _GPIO_USART_RXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].CLKROUTE = ((uint32_t)initData->portClk << _GPIO_USART_CLKROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinClk << _GPIO_USART_CLKROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].CSROUTE = ((uint32_t)initData->portCs << _GPIO_USART_CSROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinCs << _GPIO_USART_CSROUTE_PIN_SHIFT); +#else + handle->peripheral.usartPort->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | + USART_ROUTE_CSPEN | + (initData->portLocation << _USART_ROUTE_LOCATION_SHIFT); +#endif + } + else + { + // SPI 3 wire mode +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.usartPort->ROUTELOC0 = + (handle->peripheral.usartPort->ROUTELOC0 & + ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | _USART_ROUTELOC0_CLKLOC_MASK)) | + (initData->portLocationTx << _USART_ROUTELOC0_TXLOC_SHIFT) | + (initData->portLocationRx << _USART_ROUTELOC0_RXLOC_SHIFT) | + (initData->portLocationClk << _USART_ROUTELOC0_CLKLOC_SHIFT); + + handle->peripheral.usartPort->ROUTEPEN = USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_CLKPEN; +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE[spiPortNum].ROUTEEN = + GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN | GPIO_USART_ROUTEEN_CLKPEN; + + GPIO->USARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx << _GPIO_USART_TXROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinTx << _GPIO_USART_TXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx << _GPIO_USART_RXROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinRx << _GPIO_USART_RXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].CLKROUTE = ((uint32_t)initData->portClk << _GPIO_USART_CLKROUTE_PORT_SHIFT) | + ((uint32_t)initData->pinClk << _GPIO_USART_CLKROUTE_PIN_SHIFT); +#else + handle->peripheral.usartPort->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | + (initData->portLocation << _USART_ROUTE_LOCATION_SHIFT); +#endif + } + + if ((retVal = ConfigGPIO(handle, true)) != ECODE_EMDRV_SPIDRV_OK) + { + return retVal; + } + + CORE_ENTER_ATOMIC(); + if (!spidrvIsInitialized) + { + spidrvIsInitialized = true; + CORE_EXIT_ATOMIC(); + } + else + { + CORE_EXIT_ATOMIC(); + } + + // Initialize DMA. + DMADRV_Init(); + + if (DMADRV_AllocateChannel(&handle->txDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; + } + + if (DMADRV_AllocateChannel(&handle->rxDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) + { + return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; + } + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Deinitialize an SPI driver instance. +// +// This function should only be called with an initialized spidrv instance handle. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate +// SPIDRV @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_DeInit(NF_SpiDriver_Handle_t handle) +{ + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + // Stop DMAs. + DMADRV_StopTransfer(handle->rxDMACh); + DMADRV_StopTransfer(handle->txDMACh); + + ConfigGPIO(handle, false); + + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) + { + USART_Reset(handle->peripheral.usartPort); + } + + CMU_ClockEnable(handle->usartClock, false); + + DMADRV_FreeChannel(handle->txDMACh); + DMADRV_FreeChannel(handle->rxDMACh); + DMADRV_DeInit(); + emRequestDeinit(handle); + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Abort an ongoing SPI transfer. +// @param[in] handle Pointer to an SPI driver handle. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_IDLE if +// SPI is idle. On failure, an appropriate SPIDRV @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_AbortTransfer(NF_SpiDriver_Handle_t handle) +{ + CORE_DECLARE_IRQ_STATE; + + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + CORE_ENTER_ATOMIC(); + if (handle->state == spidrvStateIdle) + { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_IDLE; + } + + // Stop DMA's. + DMADRV_StopTransfer(handle->rxDMACh); + DMADRV_StopTransfer(handle->txDMACh); + DMADRV_TransferRemainingCount(handle->rxDMACh, &handle->remaining); + handle->transferStatus = ECODE_EMDRV_SPIDRV_ABORTED; + handle->state = spidrvStateIdle; + handle->transferStatus = ECODE_EMDRV_SPIDRV_ABORTED; + handle->blockingCompleted = true; + // signal RTOS event + tx_event_flags_set(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR); + + em1RequestRemove(handle); + + if (handle->userCallback != NULL) + { + handle->userCallback(handle, ECODE_EMDRV_SPIDRV_ABORTED, handle->transferCount - handle->remaining); + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Get current SPI bus bitrate. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[out] bitRate Current SPI bus bitrate. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_GetBitrate(NF_SpiDriver_Handle_t handle, uint32_t *bitRate) +{ + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if (bitRate == NULL) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) + { + *bitRate = USART_BaudrateGet(handle->peripheral.usartPort); + } + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Get current SPI framelength. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[out] frameLength Current SPI bus framelength. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_GetFramelength(NF_SpiDriver_Handle_t handle, uint32_t *frameLength) +{ + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if (frameLength == NULL) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + *frameLength = handle->initData->frameLength; + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Get the status of an SPI transfer. +// +// @details +// Returns status of an ongoing transfer. If no transfer is in progress, +// the status of the last transfer is reported. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[out] itemsTransferred Number of items (frames) transferred. +// +// @param[out] itemsRemaining Number of items (frames) remaining. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_GetTransferStatus(NF_SpiDriver_Handle_t handle, int *itemsTransferred, int *itemsRemaining) +{ + int remaining; + + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if ((itemsTransferred == NULL) || (itemsRemaining == NULL)) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + CORE_ATOMIC_SECTION( + if (handle->state == spidrvStateIdle) { remaining = handle->remaining; } else { + DMADRV_TransferRemainingCount(handle->rxDMACh, &remaining); + }) + + // itemsTransferred = (handle->transferCount - remaining); + *itemsRemaining = remaining; + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Start an SPI master receive transfer. +// +// @note +// The MOSI wire will transmit @ref SPIDRV_Init.dummyTxValue. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[out] buffer Receive data buffer. +// +// @param[in] count Number of bytes in transfer. +// +// @param[in] callback Transfer completion callback. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_Receive(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback) +{ + Ecode_t retVal; + + if ((retVal = TransferApiPrologue(handle, buffer, count)) != ECODE_EMDRV_SPIDRV_OK) + { + return retVal; + } + + StartReceiveDMA(handle, buffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Start an SPI master blocking receive transfer. +// +// @note +// The MOSI wire will transmit @ref SPIDRV_Init.dummyTxValue. +// @n This function is blocking and returns when the transfer is complete +// or when @ref SPIDRV_AbortTransfer() is called. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[out] buffer Receive data buffer. +// +// @param[in] count Number of bytes in transfer. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED +// if @ref SPIDRV_AbortTransfer() has been called. On failure, an appropriate +// SPIDRV @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_ReceiveBlocking(NF_SpiDriver_Handle_t handle, void *buffer, int count) +{ + Ecode_t retVal; + + if ((retVal = TransferApiBlockingPrologue(handle, buffer, count)) != ECODE_EMDRV_SPIDRV_OK) + { + return retVal; + } + + StartReceiveDMA(handle, buffer, count, BlockingComplete); + + WaitForTransferCompletion(handle); + + return handle->transferStatus; +} + +// +// +// Start an SPI master transfer. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[in] txBuffer Transmit data buffer. +// +// @param[out] rxBuffer Receive data buffer. +// +// @param[in] count Number of bytes in transfer. +// +// @param[in] callback Transfer completion callback. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_Transfer( + NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + NF_SpiDriver_Callback_t callback) +{ + Ecode_t retVal; + + if ((retVal = TransferApiPrologue(handle, (void *)txBuffer, count)) != ECODE_EMDRV_SPIDRV_OK) + { + return retVal; + } + + if (rxBuffer == NULL) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + StartTransferDMA(handle, txBuffer, rxBuffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Start an SPI master blocking transfer. +// +// @note +// This function is blocking and returns when the transfer is complete +// or when @ref SPIDRV_AbortTransfer() is called. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[in] txBuffer Transmit data buffer. +// +// @param[out] rxBuffer Receive data buffer. +// +// @param[in] count Number of bytes in transfer. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED +// if @ref SPIDRV_AbortTransfer() has been called. On failure, an appropriate +// SPIDRV @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_TransferBlocking(NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count) { -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; + Ecode_t retVal; - CORE_ENTER_ATOMIC(); + if ((retVal = TransferApiBlockingPrologue(handle, (void *)txBuffer, count)) != ECODE_EMDRV_SPIDRV_OK) + { + return retVal; + } - if (driver->DmaRequestCount == 0) + if (rxBuffer == NULL) { - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; } - driver->DmaRequestCount++; + StartTransferDMA(handle, txBuffer, rxBuffer, count, BlockingComplete); - CORE_EXIT_ATOMIC(); -#else - driver->DmaRequestCount++; -#endif + WaitForTransferCompletion(handle); + + return handle->transferStatus; } -// Substracts track of a DMA request -void DmaRequestRemove(struct Gecko_SpiDriver *driver) +// +// +// Start an SPI master transmit transfer. +// +// @note +// The data received on the MISO wire is discarded. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[in] buffer Transmit data buffer. +// +// @param[in] count Number of bytes in transfer. +// +// @param[in] callback Transfer completion callback. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_Transmit( + NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback) { - if (driver->DmaRequestCount == 0) + Ecode_t retVal; + + if ((retVal = TransferApiPrologue(handle, (void *)buffer, count)) != ECODE_EMDRV_SPIDRV_OK) { - return; + return retVal; } -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + StartTransmitDMA(handle, buffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; +} + +// +// +// Start an SPI master blocking transmit transfer. +// +// @note +// The data received on the MISO wire is discarded. +// @n This function is blocking and returns when the transfer is complete. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[in] buffer Transmit data buffer. +// +// @param[in] count Number of bytes in transfer. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED +// if @ref SPIDRV_AbortTransfer() has been called. On failure, an appropriate +// SPIDRV @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_TransmitBlocking(NF_SpiDriver_Handle_t handle, const void *buffer, int count) +{ + Ecode_t retVal; + + if ((retVal = TransferApiBlockingPrologue(handle, (void *)buffer, count)) != ECODE_EMDRV_SPIDRV_OK) + { + return retVal; + } + + StartTransmitDMA(handle, buffer, count, BlockingComplete); + + WaitForTransferCompletion(handle); + + return handle->transferStatus; +} + +// +// +// Set SPI bus bitrate. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[in] bitRate New SPI bus bitrate. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_SetBitrate(NF_SpiDriver_Handle_t handle, uint32_t bitRate) +{ CORE_DECLARE_IRQ_STATE; + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + CORE_ENTER_ATOMIC(); - driver->DmaRequestCount--; - if (driver->DmaRequestCount == 0) + if (handle->state != spidrvStateIdle) { - sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + + handle->initData->bitRate = bitRate; + + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) + { + USART_BaudrateSyncSet(handle->peripheral.usartPort, 0, bitRate); } CORE_EXIT_ATOMIC(); -#else - driver->DmaRequestCount--; -#endif + + return ECODE_EMDRV_SPIDRV_OK; } -// Callback for DMA transfer completed -bool RxDmaComplete(unsigned int channel, unsigned int sequenceNo, void *userParam) +// +// +// Set SPI framelength. +// +// @param[in] handle Pointer to an SPI driver handle. +// +// @param[in] frameLength New SPI bus framelength. +// +// @return +// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV +// @ref Ecode_t is returned. +// +Ecode_t NF_SpiDriver_SetFramelength(NF_SpiDriver_Handle_t handle, uint32_t frameLength) { - (void)channel; - (void)sequenceNo; - Gecko_SpiDriver *driver = (Gecko_SpiDriver *)userParam; - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - driver->DmaRemaningCount = 0; + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) + { + frameLength -= EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET; - driver->DmaCallback(driver, ECODE_OK, 0); + if ((frameLength < _USART_FRAME_DATABITS_FOUR) || (frameLength > _USART_FRAME_DATABITS_SIXTEEN)) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + } - CORE_EXIT_ATOMIC(); + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) + { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } - DmaRequestRemove(driver); + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) + { + handle->initData->frameLength = frameLength + EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET; - return true; + handle->peripheral.usartPort->FRAME = (handle->peripheral.usartPort->FRAME & ~_USART_FRAME_DATABITS_MASK) | + (frameLength << _USART_FRAME_DATABITS_SHIFT); + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_SPIDRV_OK; } -// Callback for DMA blocking transfers -void DmaBlockingComplete(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred) +// +// +// Transfer complete callback function used by blocking transfer API +// functions. Called by DMA interrupt handler, timer timeout handler +// or @ref SPIDRV_AbortTransfer() function. +// +static void BlockingComplete(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) { (void)itemsTransferred; - (void)transferStatus; - driver->BlockingOpCompleted = true; + handle->transferStatus = transferStatus; + handle->blockingCompleted = true; + // signal RTOS event + tx_event_flags_set(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR); +} + +#if defined(_SILICON_LABS_32B_SERIES_1) +// +// Get SPI pins for Series 1 devices. +// +static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t *pins) +{ + if (0) + { +#if defined(USART0) + } + else if (handle->peripheral.usartPort == USART0) + { + pins->mosiPort = AF_USART0_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART0_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART0_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART0_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART0_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART0_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART0_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART0_CS_PIN(handle->initData->portLocationCs); +#endif +#if defined(USART1) + } + else if (handle->peripheral.usartPort == USART1) + { + pins->mosiPort = AF_USART1_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART1_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART1_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART1_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART1_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART1_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART1_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART1_CS_PIN(handle->initData->portLocationCs); +#endif +#if defined(USART2) + } + else if (handle->peripheral.usartPort == USART2) + { + pins->mosiPort = AF_USART2_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART2_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART2_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART2_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART2_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART2_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART2_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART2_CS_PIN(handle->initData->portLocationCs); +#endif +#if defined(USART3) + } + else if (handle->peripheral.usartPort == USART3) + { + pins->mosiPort = AF_USART3_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART3_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART3_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART3_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART3_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART3_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART3_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART3_CS_PIN(handle->initData->portLocationCs); +#endif +#if defined(USART4) + } + else if (handle->peripheral.usartPort == USART4) + { + pins->mosiPort = AF_USART4_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART4_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART4_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART4_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART4_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART4_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART4_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART4_CS_PIN(handle->initData->portLocationCs); +#endif +#if defined(USART5) + } + else if (handle->peripheral.usartPort == USART5) + { + pins->mosiPort = AF_USART5_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART5_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART5_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART5_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART5_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART5_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART5_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART5_CS_PIN(handle->initData->portLocationCs); +#endif + } + else + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + return ECODE_EMDRV_SPIDRV_OK; +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) +// +// Get SPI pins for Series 2 devices. +// +static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t// pins) +{ + pins->mosiPort = handle->initData->portTx; + pins->misoPort = handle->initData->portRx; + pins->clkPort = handle->initData->portClk; + pins->csPort = handle->initData->portCs; + pins->mosiPin = handle->initData->pinTx; + pins->misoPin = handle->initData->pinRx; + pins->clkPin = handle->initData->pinClk; + pins->csPin = handle->initData->pinCs; + + return ECODE_EMDRV_SPIDRV_OK; +} +#endif + +// +// Configure/deconfigure SPI GPIO pins. +// +static Ecode_t ConfigGPIO(NF_SpiDriver_Handle_t handle, bool enable) +{ + SPI_Pins_t pins; + Ecode_t ret; + + ret = GetSpiPins(handle, &pins); + if (ret != ECODE_EMDRV_SPIDRV_OK) + { + return ret; + } + handle->portCs = (GPIO_Port_TypeDef)pins.csPort; + handle->pinCs = pins.csPin; + + if (enable) + { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, gpioModePushPull, 0); + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, gpioModeInput, 0); + + if ((handle->initData->clockMode == spidrvClockMode0) || (handle->initData->clockMode == spidrvClockMode1)) + { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModePushPull, 0); + } + else + { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModePushPull, 1); + } + + if (handle->initData->csControl == spidrvCsControlAuto) + { + GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, gpioModePushPull, 1); + } + } + else + { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, gpioModeInputPull, 0); + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, gpioModeInputPull, 0); + + if ((handle->initData->clockMode == spidrvClockMode0) || (handle->initData->clockMode == spidrvClockMode1)) + { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModeInputPull, 0); + } + else + { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModeInputPull, 1); + } + + if (handle->initData->csControl == spidrvCsControlAuto) + { + GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, gpioModeDisabled, 0); + } + } + return ECODE_EMDRV_SPIDRV_OK; } -void WaitForTransferCompletion(struct Gecko_SpiDriver *driver) +// +// DMA transfer completion callback. Called by the DMA interrupt handler. +// +static bool RxDMAComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam) { - // RTOS semaphore - // (void)driver; - // uint32_t dummy; + CORE_DECLARE_IRQ_STATE; + NF_SpiDriver_Handle_t handle; + (void)channel; + (void)sequenceNo; - // // wait forever for the SPI event - // tx_event_flags_get(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR_CLEAR, &dummy, TX_WAIT_FOREVER); + CORE_ENTER_ATOMIC(); - // alternative approach with loop calling IRQ handlers - if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) { - // Poll for completion by calling IRQ handler. - while (driver->BlockingOpCompleted == false) { -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) - DMA_IRQHandler(); -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - LDMA_IRQHandler(); -#else -#error "No valid SPIDRV DMA engine defined." -#endif + handle = (NF_SpiDriver_Handle_t)userParam; + + handle->transferStatus = ECODE_EMDRV_SPIDRV_OK; + handle->state = spidrvStateIdle; + handle->remaining = 0; + + if (handle->userCallback != NULL) + { + handle->userCallback(handle, ECODE_EMDRV_SPIDRV_OK, handle->transferCount); } - } else { - while (driver->BlockingOpCompleted == false) ; - } + + CORE_EXIT_ATOMIC(); + em1RequestRemove(handle); + + return true; } -void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback) +// +// Start an SPI receive DMA. +// +static void StartReceiveDMA(NF_SpiDriver_Handle_t handle, + void *buffer, + int count, + NF_SpiDriver_Callback_t callback) { void *rxPort, *txPort; DMADRV_DataSize_t size; - driver->BlockingOpCompleted = false; - driver->DmaTransferCount = count; - driver->DmaCallback = callback; + handle->blockingCompleted = false; + handle->transferCount = count; + handle->userCallback = callback; - driver->Usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - if (driver->DataIs16bits) + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { - rxPort = (void *)&(driver->Usart->RXDOUBLE); - txPort = (void *)&(driver->Usart->TXDOUBLE); + handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (handle->initData->frameLength > 9) + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); + txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); + } + else if (handle->initData->frameLength == 9) + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); + txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); + } + else + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); + txPort = (void *)&(handle->peripheral.usartPort->TXDATA); + } } else { - rxPort = (void *)&(driver->Usart->RXDATA); - txPort = (void *)&(driver->Usart->TXDATA); + return; } - if (driver->DataIs16bits) + if (handle->initData->frameLength > 8) { size = dmadrvDataSize2; } @@ -142,26 +1222,26 @@ void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, Sp size = dmadrvDataSize1; } - DmaRequestAdd(driver); + em1RequestAdd(handle); // Start receive DMA. DMADRV_PeripheralMemory( - driver->RxDmaChannel, - driver->RxDmaSignal, + handle->rxDMACh, + handle->rxDMASignal, (void *)buffer, rxPort, true, count, size, - RxDmaComplete, - driver); + RxDMAComplete, + handle); // Start transmit DMA. DMADRV_MemoryPeripheral( - driver->TxDmaChannel, - driver->TxDmaSignal, + handle->txDMACh, + handle->txDMASignal, txPort, - (void *)&(driver->DmaDummyRxTxValue), + (void *)&(handle->initData->dummyTxValue), false, count, size, @@ -169,29 +1249,51 @@ void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, Sp NULL); } -void StartTransmitDma(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback) +// +// Start an SPI transmit/receive DMA. +// +static void StartTransferDMA(NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + NF_SpiDriver_Callback_t callback) { void *rxPort, *txPort; DMADRV_DataSize_t size; - driver->BlockingOpCompleted = false; - driver->DmaTransferCount = count; - driver->DmaCallback = callback; + handle->blockingCompleted = false; + handle->transferCount = count; + handle->userCallback = callback; - driver->Usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - if (driver->DataIs16bits) + if (0) + { + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { - rxPort = (void *)&(driver->Usart->RXDOUBLE); - txPort = (void *)&(driver->Usart->TXDOUBLE); + handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (handle->initData->frameLength > 9) + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); + txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); + } + else if (handle->initData->frameLength == 9) + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); + txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); + } + else + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); + txPort = (void *)&(handle->peripheral.usartPort->TXDATA); + } } else { - rxPort = (void *)&(driver->Usart->RXDATA); - txPort = (void *)&(driver->Usart->TXDATA); + return; } - if (driver->DataIs16bits) + if (handle->initData->frameLength > 8) { size = dmadrvDataSize2; } @@ -200,27 +1302,26 @@ void StartTransmitDma(struct Gecko_SpiDriver *driver, const void *buffer, int co size = dmadrvDataSize1; } - DmaRequestAdd(driver); + em1RequestAdd(handle); - // Receive DMA runs only to get precise numbers for SPIDRV_GetTransferStatus() // Start receive DMA. DMADRV_PeripheralMemory( - driver->RxDmaChannel, - driver->RxDmaSignal, - &(driver->DmaDummyRxTxValue), + handle->rxDMACh, + handle->rxDMASignal, + rxBuffer, rxPort, - false, + true, count, size, - RxDmaComplete, - driver); + RxDMAComplete, + handle); // Start transmit DMA. DMADRV_MemoryPeripheral( - driver->TxDmaChannel, - driver->TxDmaSignal, + handle->txDMACh, + handle->txDMASignal, txPort, - (void *)buffer, + (void *)txBuffer, true, count, size, @@ -228,34 +1329,50 @@ void StartTransmitDma(struct Gecko_SpiDriver *driver, const void *buffer, int co NULL); } -void StartTransferDma( - struct Gecko_SpiDriver *driver, - const void *txBuffer, - void *rxBuffer, - int count, - SpiDmaCallback callback) +// +// Start an SPI transmit DMA. +// +static void StartTransmitDMA(NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback) { void *rxPort, *txPort; DMADRV_DataSize_t size; - driver->BlockingOpCompleted = false; - driver->DmaTransferCount = count; - driver->DmaCallback = callback; - - driver->Usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + handle->blockingCompleted = false; + handle->transferCount = count; + handle->userCallback = callback; - if (driver->DataIs16bits) + if (0) { - rxPort = (void *)&(driver->Usart->RXDOUBLE); - txPort = (void *)&(driver->Usart->TXDOUBLE); + } + else if (handle->peripheralType == spidrvPeripheralTypeUsart) + { + handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (handle->initData->frameLength > 9) + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); + txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); + } + else if (handle->initData->frameLength == 9) + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); + txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); + } + else + { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); + txPort = (void *)&(handle->peripheral.usartPort->TXDATA); + } } else { - rxPort = (void *)&(driver->Usart->RXDATA); - txPort = (void *)&(driver->Usart->TXDATA); + return; } - if (driver->DataIs16bits) + if (handle->initData->frameLength > 8) { size = dmadrvDataSize2; } @@ -264,26 +1381,27 @@ void StartTransferDma( size = dmadrvDataSize1; } - DmaRequestAdd(driver); + em1RequestAdd(handle); + // Receive DMA runs only to get precise numbers for SPIDRV_GetTransferStatus() // Start receive DMA. DMADRV_PeripheralMemory( - driver->RxDmaChannel, - driver->RxDmaSignal, - rxBuffer, + handle->rxDMACh, + handle->rxDMASignal, + &(handle->dummyRx), rxPort, - true, + false, count, size, - RxDmaComplete, - driver); + RxDMAComplete, + handle); // Start transmit DMA. DMADRV_MemoryPeripheral( - driver->TxDmaChannel, - driver->TxDmaSignal, + handle->txDMACh, + handle->txDMASignal, txPort, - (void *)txBuffer, + (void *)buffer, true, count, size, @@ -291,90 +1409,97 @@ void StartTransferDma( NULL); } -// Start a blocking transfer -void SpiTransferBlocking(struct Gecko_SpiDriver *driver, const void *txBuffer, void *rxBuffer, int count) -{ - StartTransferDma(driver, txBuffer, rxBuffer, count, DmaBlockingComplete); - - WaitForTransferCompletion(driver); -} - -// Start a blocking receive transfer -void SpiReceiveBlocking(struct Gecko_SpiDriver *driver, void *buffer, int count) +// +// Parameter checking function for blocking transfer API functions. +// +static Ecode_t TransferApiBlockingPrologue(NF_SpiDriver_Handle_t handle, + void *buffer, + int count) { - StartReceiveDma(driver, buffer, count, DmaBlockingComplete); + CORE_DECLARE_IRQ_STATE; - WaitForTransferCompletion(driver); -} + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } -// Start a blocking transmit transfer -void SpiTransmitBlocking(struct Gecko_SpiDriver *driver, const void *buffer, int count) -{ - StartTransmitDma(driver, buffer, count, DmaBlockingComplete); + if ((buffer == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - WaitForTransferCompletion(driver); -} + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) + { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + handle->state = spidrvStateTransferring; + CORE_EXIT_ATOMIC(); -// Start a non-blocking transfer -void SpiTransfer( - struct Gecko_SpiDriver *driver, - const void *txBuffer, - void *rxBuffer, - int count, - SpiDmaCallback callback) -{ - StartTransferDma(driver, txBuffer, rxBuffer, count, callback); + return ECODE_EMDRV_SPIDRV_OK; } -// Start a non-blocking transmit transfer -void SpiTransmit(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback) +// +// Parameter checking function for non-blocking transfer API functions. +// +static Ecode_t TransferApiPrologue(NF_SpiDriver_Handle_t handle, + void *buffer, + int count) { - StartTransmitDma(driver, buffer, count, callback); -} + CORE_DECLARE_IRQ_STATE; -// Start a non-blocking receive transfer -void SpiReceive(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback) -{ - StartReceiveDma(driver, buffer, count, callback); -} + if (handle == NULL) + { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } -// Initialize DMA for SPI transfers -bool SpiStart(struct Gecko_SpiDriver *driver) -{ - // set frame size - driver->Usart->FRAME = - (driver->Usart->FRAME & ~_USART_FRAME_DATABITS_MASK) | driver->DataIs16bits ? usartDatabits16 : usartDatabits8; + if ((buffer == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) + { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - USART_Enable(driver->Usart, usartEnable); + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) + { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + handle->state = spidrvStateTransferring; + CORE_EXIT_ATOMIC(); - return true; + return ECODE_EMDRV_SPIDRV_OK; } -void SpiRelease(struct Gecko_SpiDriver *driver) +// +// @brief Wait for transfer completion. +// +static void WaitForTransferCompletion(NF_SpiDriver_Handle_t handle) { - USART_Enable(driver->Usart, usartDisable); -} + uint32_t dummy; -bool SpiDriverInit(struct Gecko_SpiDriver *driver) -{ - // set DMA - if (DMADRV_AllocateChannel(&driver->TxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) { - return false; + // Poll for completion by calling IRQ handler. + while (handle->blockingCompleted == false) + { +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) + DMA_IRQHandler(); +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + LDMA_IRQHandler(); +#else +#error "No valid SPIDRV DMA engine defined." +#endif + } } - - if (DMADRV_AllocateChannel(&driver->RxDmaChannel, NULL) != ECODE_EMDRV_DMADRV_OK) + else { - return false; + // wait forever for the SPI event + tx_event_flags_get( + &nanoHardwareEvents, + NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, + TX_OR_CLEAR, + &dummy, + TX_WAIT_FOREVER); } - - USART_InitSync(driver->Usart, driver->Configuration); - - return true; -} - -void SpiDriverDeInit(struct Gecko_SpiDriver *driver) -{ - DMADRV_FreeChannel(driver->TxDmaChannel); - DMADRV_FreeChannel(driver->RxDmaChannel); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h index dc1bdf4ecc..2cca5c02fb 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h @@ -11,18 +11,22 @@ #include #include -#include +#include #include -#include + +#include +#include +#include #include +#include #include #if defined(DMA_PRESENT) && (DMA_COUNT == 1) -#define SPI_DMA_IRQ DMA_IRQn +#define SPI_DMA_IRQ DMA_IRQn #elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) -#define SPI_DMA_IRQ LDMA_IRQn +#define SPI_DMA_IRQ LDMA_IRQn #else #error "No valid SPIDRV DMA engine defined." @@ -31,59 +35,176 @@ // flags for hardware events extern TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -typedef void (*SpiDmaCallback)(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred); - #ifdef __cplusplus extern "C" { #endif - struct Gecko_SpiDriver + // clang-format off + +#define ECODE_EMDRV_SPIDRV_OK (ECODE_OK) ///< A successful return value. +#define ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE (ECODE_EMDRV_SPIDRV_BASE | 0x00000001) ///< An illegal SPI handle. +#define ECODE_EMDRV_SPIDRV_PARAM_ERROR (ECODE_EMDRV_SPIDRV_BASE | 0x00000002) ///< An illegal input parameter. +#define ECODE_EMDRV_SPIDRV_BUSY (ECODE_EMDRV_SPIDRV_BASE | 0x00000003) ///< The SPI port is busy. +#define ECODE_EMDRV_SPIDRV_TIMER_ALLOC_ERROR (ECODE_EMDRV_SPIDRV_BASE | 0x00000004) ///< Unable to allocate timeout timer. +#define ECODE_EMDRV_SPIDRV_TIMEOUT (ECODE_EMDRV_SPIDRV_BASE | 0x00000005) ///< An SPI transfer timeout. +#define ECODE_EMDRV_SPIDRV_IDLE (ECODE_EMDRV_SPIDRV_BASE | 0x00000006) ///< No SPI transfer in progress. +#define ECODE_EMDRV_SPIDRV_ABORTED (ECODE_EMDRV_SPIDRV_BASE | 0x00000007) ///< An SPI transfer has been aborted. +#define ECODE_EMDRV_SPIDRV_MODE_ERROR (ECODE_EMDRV_SPIDRV_BASE | 0x00000008) ///< SPI master used slave API or vice versa. +#define ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR (ECODE_EMDRV_SPIDRV_BASE | 0x00000009) ///< Unable to allocate DMA channels. + + // clang-format on + + /// SPI driver instance type. + SL_ENUM(NF_SpiDriver_Type_t){ + spidrvMaster = 0, ///< Act as an SPI master. + }; + + /// SPI bus bit order. + SL_ENUM(NF_SpiDriver_BitOrder_t){ + spidrvBitOrderLsbFirst = 0, ///< LSB bit is transmitted first. + spidrvBitOrderMsbFirst = 1 ///< MSB bit is transmitted first. + }; + + /// SPI clock mode (clock polarity and phase). + SL_ENUM(NF_SpiDriver_ClockMode_t){ + spidrvClockMode0 = 0, ///< SPI mode 0: CLKPOL=0, CLKPHA=0. + spidrvClockMode1 = 1, ///< SPI mode 1: CLKPOL=0, CLKPHA=1. + spidrvClockMode2 = 2, ///< SPI mode 2: CLKPOL=1, CLKPHA=0. + spidrvClockMode3 = 3 ///< SPI mode 3: CLKPOL=1, CLKPHA=1. + }; + + /// SPI master chip select (CS) control scheme. + SL_ENUM(NF_SpiDriver_CsControl_t){ + spidrvCsControlAuto = 0, ///< CS controlled by the SPI driver. + spidrvCsControlApplication = 1 ///< CS controlled by the application. + }; + + /// SPI slave transfer start scheme. + SL_ENUM(NF_SpiDriver_SlaveStart_t){ + spidrvSlaveStartImmediate = 0, ///< Transfer starts immediately. + spidrvSlaveStartDelayed = 1 ///< Transfer starts when the bus is idle (CS deasserted). + }; + + /// Type of a USART peripheral + SL_ENUM(NF_SpiDriver_PeripheralType_t) { - USART_TypeDef *Usart; - USART_InitSync_TypeDef *Configuration; - - bool DataIs16bits; - - unsigned int TxDmaChannel; - unsigned int RxDmaChannel; - DMADRV_PeripheralSignal_t TxDmaSignal; - DMADRV_PeripheralSignal_t RxDmaSignal; - bool BlockingOpCompleted; - int32_t DmaTransferCount; - int32_t DmaRemaningCount; - int32_t DmaRequestCount; - uint32_t DmaDummyRxTxValue; - SpiDmaCallback DmaCallback; + spidrvPeripheralTypeUsart = 0, ///< USART peripheral }; - void SpiReceive(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback); - void SpiTransmit(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback); - void SpiTransfer( - struct Gecko_SpiDriver *driver, - const void *txBuffer, - void *rxBuffer, - int count, - SpiDmaCallback callback); - void SpiTransmitBlocking(struct Gecko_SpiDriver *driver, const void *buffer, int count); - void SpiReceiveBlocking(struct Gecko_SpiDriver *driver, void *buffer, int count); - void SpiTransferBlocking(struct Gecko_SpiDriver *driver, const void *txBuffer, void *rxBuffer, int count); - void StartTransferDma( - struct Gecko_SpiDriver *driver, + SL_ENUM(NF_SpiDriver_State_t){spidrvStateIdle = 0, spidrvStateTransferring = 1}; + + struct NF_SpiDriver_HandleData; + + /* + * @brief + * NF_SpiDriver transfer completion callback function. + * + * @details + * Called when a transfer is complete. An + * application should check the transferStatus and itemsTransferred values. + * + * @param[in] handle + * The NF_SpiDriver device handle used to start the transfer. + * + * @param[in] transferStatus + * A number of bytes actually transferred. + * + * @param[in] itemsTransferred + * A number of bytes transferred. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_TIMEOUT + * on timeout. Timeouts are only relevant for slave mode transfers. + */ + typedef void (*NF_SpiDriver_Callback_t)(struct NF_SpiDriver_HandleData *handle, Ecode_t transferStatus, int itemsTransferred); + + /// An SPI driver instance initialization structure. + /// Contains a number of SPIDRV configuration options. + /// This structure is passed to @ref NF_SpiDriver_Init() when initializing a SPIDRV + /// instance. Some common initialization data sets are predefined in + /// @ref spidrv_init_structs + typedef struct NF_SpiDriver_Init + { + void *port; ///< The USART used for SPI. + uint8_t portLocationTx; ///< A location number for the SPI Tx pin. + uint8_t portLocationRx; ///< A location number for the SPI Rx pin. + uint8_t portLocationClk; ///< A location number for the SPI Clk pin. + uint8_t portLocationCs; ///< A location number for the SPI Cs pin. + uint32_t bitRate; ///< An SPI bitrate. + uint32_t frameLength; ///< An SPI framelength, valid numbers are 4..16 + uint32_t dummyTxValue; ///< The value to transmit when using SPI receive API functions. + NF_SpiDriver_BitOrder_t bitOrder; ///< A bit order on the SPI bus, MSB or LSB first. + NF_SpiDriver_ClockMode_t clockMode; ///< SPI mode, CLKPOL/CLKPHASE setting. + NF_SpiDriver_CsControl_t csControl; ///< A select master mode chip select (CS) control scheme. + } NF_SpiDriver_Init_t; + + /// An SPI driver instance handle data structure. + /// The handle is allocated by the application using the SPIDRV. + /// Several concurrent driver instances can exist in an application. The application is + /// neither supposed to write or read the contents of the handle. + typedef struct NF_SpiDriver_HandleData + { + union { + USART_TypeDef *usartPort; + void *__reserved_space; + } peripheral; + NF_SpiDriver_Init_t *initData; + unsigned int txDMACh; + unsigned int rxDMACh; + DMADRV_PeripheralSignal_t txDMASignal; + DMADRV_PeripheralSignal_t rxDMASignal; + NF_SpiDriver_Callback_t userCallback; + uint32_t dummyRx; + int transferCount; + int remaining; + GPIO_Port_TypeDef portCs; + uint8_t pinCs; + Ecode_t transferStatus; + volatile NF_SpiDriver_State_t state; + CMU_Clock_TypeDef usartClock; + volatile bool blockingCompleted; + int em1RequestCount; + NF_SpiDriver_PeripheralType_t peripheralType; + sl_sleeptimer_timer_handle_t timer; + sl_slist_node_t node; + } NF_SpiDriver_HandleData_t; + + /// An SPI driver instance handle. + typedef NF_SpiDriver_HandleData_t *NF_SpiDriver_Handle_t; + + Ecode_t NF_SpiDriver_AbortTransfer(NF_SpiDriver_Handle_t handle); + + Ecode_t NF_SpiDriver_DeInit(NF_SpiDriver_Handle_t handle); + + Ecode_t NF_SpiDriver_GetBitrate(NF_SpiDriver_Handle_t handle, uint32_t *bitRate); + + Ecode_t NF_SpiDriver_GetFramelength(NF_SpiDriver_Handle_t handle, uint32_t *frameLength); + + Ecode_t NF_SpiDriver_GetTransferStatus(NF_SpiDriver_Handle_t handle, int *itemsTransferred, int *itemsRemaining); + + Ecode_t NF_SpiDriver_Init(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData); + + Ecode_t NF_SpiDriver_Receive(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback); + + Ecode_t NF_SpiDriver_ReceiveBlocking(NF_SpiDriver_Handle_t handle, void *buffer, int count); + + Ecode_t NF_SpiDriver_Transfer( + NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count, - SpiDmaCallback callback); - void StartTransmitDma(struct Gecko_SpiDriver *driver, const void *buffer, int count, SpiDmaCallback callback); - void StartReceiveDma(struct Gecko_SpiDriver *driver, void *buffer, int count, SpiDmaCallback callback); - void WaitForTransferCompletion(struct Gecko_SpiDriver *driver); - void DmaBlockingComplete(struct Gecko_SpiDriver *driver, Ecode_t transferStatus, int itemsTransferred); - bool RxDmaComplete(unsigned int channel, unsigned int sequenceNo, void *userParam); - void DmaRequestRemove(struct Gecko_SpiDriver *driver); - void DmaRequestAdd(struct Gecko_SpiDriver *driver); - bool SpiDriverInit(struct Gecko_SpiDriver *driver); - bool SpiStart(struct Gecko_SpiDriver *driver); - void SpiRelease(struct Gecko_SpiDriver *driver); + NF_SpiDriver_Callback_t callback); + + Ecode_t NF_SpiDriver_TransferBlocking(NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count); + + Ecode_t NF_SpiDriver_Transmit(NF_SpiDriver_Handle_t handle, const void *buffer, int count, NF_SpiDriver_Callback_t callback); + + Ecode_t NF_SpiDriver_TransmitBlocking(NF_SpiDriver_Handle_t handle, const void *buffer, int count); + + Ecode_t NF_SpiDriver_SetBitrate(NF_SpiDriver_Handle_t handle, uint32_t bitRate); + + Ecode_t NF_SpiDriver_SetFramelength(NF_SpiDriver_Handle_t handle, uint32_t frameLength); #ifdef __cplusplus } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 4c082670ee..0cff2950ee 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -14,8 +14,6 @@ #include #include -#define SL_SPIDRV_EXP_BITRATE 1000000 - // set missing defines #if defined(USART0) #ifndef GECKO_USE_SPI0 @@ -85,8 +83,7 @@ struct NF_PAL_SPI // -1 = Chip Select is not handled | >0 Chip Select is to be controlled with this GPIO int32_t ChipSelect; - // DMA transfer control - Gecko_SpiDriver *Driver; + NF_SpiDriver_Handle_t Handle; }; //////////////////////////////////////////// @@ -116,42 +113,16 @@ extern NF_PAL_SPI SPI5_PAL; // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations -#define SPI_CONFIG_PINS( \ - num, \ - gpio_port_sck, \ - sck_pin, \ - sck_port_location, \ - gpio_port_mosi, \ - mosi_pin, \ - mosi_port_location, \ - gpio_port_miso, \ - miso_pin, \ - miso_port_location) \ - void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig) \ +#define INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location) \ + void InitSpiConfig##num(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex) \ { \ - GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 0); \ - SPI##num##_PAL.Driver->Usart->ROUTELOC0 = (SPI##num##_PAL.Driver->Usart->ROUTELOC0 & \ - ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ - _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ - mosi_port_location | \ - (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ - if (spiDeviceConfig.BusConfiguration == SpiBusConfiguration_HalfDuplex) \ - { \ - SPI##num##_PAL.Driver->Usart->CTRL |= USART_CTRL_LOOPBK; \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ - } \ - else \ + initSpiData.port = USART##num; \ + initSpiData.portLocationTx = mosi_port_location; \ + initSpiData.portLocationClk = sck_port_location; \ + if (!isHalfDuplex) \ { \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ - GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 0); \ - SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= \ - (miso_port_location) | (mosi_port_location << _USART_ROUTELOC0_TXLOC_SHIFT); \ + initSpiData.portLocationRx = miso_port_location; \ } \ - SPI##num##_PAL.Driver->Usart->ROUTEPEN = \ - USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_TXPEN | \ - (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ - ? USART_ROUTEPEN_RXPEN \ - : 0; \ } #else @@ -162,11 +133,11 @@ extern NF_PAL_SPI SPI5_PAL; // when an SPI is defined the declarations below will have the real function/configuration // // in the target folder @ target_windows_devices_spi_config.cpp // ////////////////////////////////////////////////////////////////////////////////////////////// -void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +void InitSpiConfig0(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex); +void InitSpiConfig1(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex); +void InitSpiConfig2(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex); +void InitSpiConfig3(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex); +void InitSpiConfig4(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex); +void InitSpiConfig5(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex); #endif // SYS_DEV_SPI_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 7ab5297dae..05abaa9bbb 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -17,9 +17,9 @@ // #if (HAL_USE_CAN == TRUE) // #include // #endif -// #if (HAL_USE_SPI == TRUE) -// #include -// #endif +#if (HAL_USE_SPI == TRUE) +#include +#endif // #if (HAL_USE_UART == TRUE) // #include // #endif @@ -103,9 +103,29 @@ void nanoHAL_Initialize() I2C1_PAL = {0}; #endif - // #if (HAL_USE_SPI == TRUE) - // nanoSPI_Initialize(); - // #endif +#if (HAL_USE_SPI == TRUE) + nanoSPI_Initialize(); + +#if (GECKO_USE_SPI0 == TRUE) + memset(&SPI0_PAL, 0, sizeof(NF_PAL_SPI)); +#endif +#if (GECKO_USE_SPI1 == TRUE) + memset(&SPI1_PAL, 0, sizeof(NF_PAL_SPI)); +#endif +#if (GECKO_USE_SPI2 == TRUE) + memset(&SPI0_PAL, 0, sizeof(NF_PAL_SPI)); +#endif +#if (GECKO_USE_SPI3 == TRUE) + memset(&SPI3_PAL, 0, sizeof(NF_PAL_SPI)); +#endif +#if (GECKO_USE_SPI4 == TRUE) + memset(&SPI4_PAL, 0, sizeof(NF_PAL_SPI)); +#endif +#if (GECKO_USE_SPI5 == TRUE) + memset(&SPI5_PAL, 0, sizeof(NF_PAL_SPI)); +#endif + +#endif // #if (HAL_USE_UART == TRUE) @@ -241,9 +261,9 @@ void nanoHAL_Uninitialize() I2C_Reset(I2C2); #endif - // #if (HAL_USE_SPI == TRUE) - // nanoSPI_Uninitialize(); - // #endif +#if (HAL_USE_SPI == TRUE) + nanoSPI_Uninitialize(); +#endif // #if (HAL_USE_UART == TRUE) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 1b2657dc09..861cf28cca 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -16,8 +16,8 @@ #define HAL_USE_RTC @HAL_USE_RTC_OPTION@ // takes care of enabling the HAL subsystems required for API options -// #define HAL_USE_SPI @HAL_USE_SPI_OPTION@ // #define HAL_USE_I2C @HAL_USE_I2C_OPTION@ +#define HAL_USE_SPI @HAL_USE_SPI_OPTION@ #define HAL_USE_PWM @HAL_USE_PWM_OPTION@ // #define HAL_USE_ADC @HAL_USE_ADC_OPTION@ // #define HAL_USE_DAC @HAL_USE_DAC_OPTION@ From 414040e5885fb8c281c4652395a693f454d10e3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 3 Aug 2022 16:47:37 +0100 Subject: [PATCH 086/572] Fix HAL initi/deinit for I2C --- .../AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 13 ++++++------- .../SiliconLabs/_nanoCLR/target_platform.h.in | 8 ++++---- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 05abaa9bbb..add5dcd9d3 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -17,6 +17,9 @@ // #if (HAL_USE_CAN == TRUE) // #include // #endif +#if (HAL_USE_I2C == TRUE) +#include +#endif #if (HAL_USE_SPI == TRUE) #include #endif @@ -94,13 +97,13 @@ void nanoHAL_Initialize() // #endif #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) - I2C0_PAL = {0}; + memset(&I2C0_PAL, 0, sizeof(NF_PAL_I2C)); #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) - I2C1_PAL = {0}; + memset(&I2C1_PAL, 0, sizeof(NF_PAL_I2C)); #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) - I2C1_PAL = {0}; + memset(&I2C2_PAL, 0, sizeof(NF_PAL_I2C)); #endif #if (HAL_USE_SPI == TRUE) @@ -218,10 +221,6 @@ void nanoHAL_Uninitialize() // - all mutexes for drivers that use them are released // - all drivers are stopped - // #if (HAL_USE_SPI == TRUE) - // nanoSPI_Uninitialize(); - // #endif - // #if (HAL_USE_CAN == TRUE) // #if defined(STM32_CAN_USE_CAN1) && (STM32_CAN_USE_CAN1 == TRUE) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 861cf28cca..cd2a9091a6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -16,12 +16,12 @@ #define HAL_USE_RTC @HAL_USE_RTC_OPTION@ // takes care of enabling the HAL subsystems required for API options -// #define HAL_USE_I2C @HAL_USE_I2C_OPTION@ #define HAL_USE_SPI @HAL_USE_SPI_OPTION@ +#define HAL_USE_I2C @HAL_USE_I2C_OPTION@ #define HAL_USE_PWM @HAL_USE_PWM_OPTION@ -// #define HAL_USE_ADC @HAL_USE_ADC_OPTION@ -// #define HAL_USE_DAC @HAL_USE_DAC_OPTION@ -// #define HAL_USE_UART @HAL_USE_UART_OPTION@ +#define HAL_USE_ADC @HAL_USE_ADC_OPTION@ +#define HAL_USE_DAC @HAL_USE_DAC_OPTION@ +#define HAL_USE_UART @HAL_USE_UART_OPTION@ // #define HAL_USE_SDC @HAL_USE_SDC_OPTION@ // #define HAL_USE_WDG @HAL_USE_WDG_OPTION@ // #define HAL_USE_CAN @HAL_USE_CAN_OPTION@ From ad72ff31da920582694818cc189cb6e60504a0b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 4 Aug 2022 10:30:54 +0100 Subject: [PATCH 087/572] Add SPI implementation for Skyworks API - Update declaration of SpiBus class. - Rework declarations and includes for generic SPI driver. - Relocate Com.SkyworksInc.NanoFramework.Devices.Spi declaration to follow pattern. --- ...kyworksInc.NanoFramework.Devices.Spi.cmake | 7 +- .../com_sky_nf_dev_spi_native.cpp | 0 .../com_sky_nf_dev_spi_native.h | 22 +- .../nanoHAL_Spi.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 2 +- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 542 +++++++++++++++++- .../com_sky_nf_dev_spi_native_target.h | 157 +---- .../target_system_device_spi_config.h | 8 + .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 2 +- .../sys_dev_spi_native_target.h | 2 +- 10 files changed, 567 insertions(+), 175 deletions(-) rename src/{PAL => }/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp (100%) rename src/{PAL => }/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h (81%) rename src/{PAL => }/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h (100%) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake index 4956660d1a..08e87d1c1c 100644 --- a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake @@ -13,7 +13,8 @@ list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURC list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/HAL/Include) list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) -list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.Spi) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/System.Device.Spi) # source files set(Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS @@ -22,6 +23,7 @@ set(Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp target_com_sky_nf_dev_spi_config.cpp + cpu_spi.cpp ) foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS}) @@ -32,7 +34,8 @@ foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS}) PATHS ${BASE_PATH_FOR_THIS_MODULE} ${TARGET_BASE_LOCATION} - ${CMAKE_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi + ${CMAKE_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.Spi + ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Device.Spi CMAKE_FIND_ROOT_PATH_BOTH ) diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp similarity index 100% rename from src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp rename to src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h similarity index 81% rename from src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h rename to src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 435a63bab4..b82d3ad68c 100644 --- a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -8,13 +8,15 @@ #include #include -typedef enum __nfpack DataFlow -{ - DataFlow_MsbFirst = 0, - DataFlow_LsbFirst = 1, -} DataFlow; -// moved to src\PAL\Include\CPU_SPI_decl.h for convenience +// defined src\System.Device.Spi\sys_dev_spi_native.h +// typedef enum __nfpack DataFlow +// { +// DataFlow_MsbFirst = 0, +// DataFlow_LsbFirst = 1, +// } DataFlow; + +// defined src\System.Device.Spi\sys_dev_spi_native.h // typedef enum __nfpack SpiBusConfiguration // { // SpiBusConfiguration_FullDuplex = 0, @@ -22,7 +24,7 @@ typedef enum __nfpack DataFlow // SpiBusConfiguration_Simplex = 2, // } SpiBusConfiguration; -// moved to src\PAL\Include\CPU_SPI_decl.h for convenience +// defined src\System.Device.Spi\sys_dev_spi_native.h // typedef enum __nfpack SpiMode // { // SpiMode_Mode0 = 0, @@ -41,12 +43,12 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S static const int FIELD___busConfiguration = 6; //--// - }; struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus { static const int FIELD_STATIC___busConnectionSettings = 0; + static const int FIELD_STATIC___busSettingsChanged = 1; static const int FIELD___syncLock = 1; static const int FIELD___bufferSingleOperation = 2; @@ -55,7 +57,6 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN); //--// - }; struct Library_com_sky_nf_dev_spi_native_ThisAssembly @@ -63,9 +64,8 @@ struct Library_com_sky_nf_dev_spi_native_ThisAssembly static const int FIELD_STATIC__GitCommitDate = 1; //--// - }; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi; -#endif //_COM_SKY_NF_DEV_SPI_NATIVE_H_ +#endif //_COM_SKY_NF_DEV_SPI_NATIVE_H_ diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h similarity index 100% rename from src/PAL/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h rename to src/Com.SkyworksInc.NanoFramework.Devices.Spi/nanoHAL_Spi.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp index e35066d900..6dbea05b69 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp @@ -3,7 +3,7 @@ // See LICENSE file in the project root for full license information. // -#include +#include ////////// // SPI0 // diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 92b2a499be..a11ba8a07b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -1,22 +1,554 @@ // Copyright Skyworks Solutions, Inc. All Rights Reserved. -#include "com_sky_nf_dev_spi_native.h" +#include "com_sky_nf_dev_spi_native_target.h" +extern NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex); +extern void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred); -HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN( CLR_RT_StackFrame &stack ) +typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus Devices_Spi_SpiBus; +typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration + SpiBaseConfiguration; +typedef Library_corlib_native_System_SpanByte SpanByte; + +static HRESULT SPI_nWrite_nRead( + NF_PAL_SPI *palSpi, + SPI_DEVICE_CONFIGURATION &sdev, + SPI_WRITE_READ_SETTINGS &wrc, + uint8_t *writeBuffer, + int32_t writeSize, + uint8_t *readBuffer, + int32_t readSize); + +// Saved config for each available SPI bus +SPI_DEVICE_CONFIGURATION SpiConfigs[NUM_SPI_BUSES]; + +void Com_Sky_Spi_Callback(int busIndex) +{ + (void)busIndex; + + // fire event for SPI transaction complete + Events_Set(SYSTEM_EVENT_FLAG_SPI_MASTER); +} + +// duplicated from src\System.Device.Spi\sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp +// estimate the time required to perform the SPI transaction +// TODO doesn't take into account of full duplex or sequential ( assumes sequential at the moment ) +bool System_Device_IsLongRunningOperation( + uint32_t writeSize, + uint32_t readSize, + bool fullDuplex, + bool bufferIs16bits, + float byteTime, + uint32_t &estimatedDurationMiliseconds) +{ + if (bufferIs16bits) + { + // double the buffers size + writeSize = 2 * writeSize; + readSize = 2 * readSize; + } + + if (fullDuplex) + { + estimatedDurationMiliseconds = byteTime * MAX(writeSize, readSize); + } + else + { + estimatedDurationMiliseconds = byteTime * (writeSize + readSize); + } + + if (estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock *config = NULL; + CLR_RT_HeapBlock_Array *writeBuffer; + CLR_RT_HeapBlock_Array *readBuffer; + CLR_RT_HeapBlock *writeSpanByte; + CLR_RT_HeapBlock *readSpanByte; + uint8_t *writeData = NULL; + uint8_t *readData = NULL; + int16_t writeSize = 0; + int16_t readSize = 0; + int16_t readOffset = 0; + int16_t writeOffset = 0; + bool fullDuplex; + + bool isLongRunningOperation; + uint32_t estimatedDurationMiliseconds; + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + int8_t busIndex; + SPI_WRITE_READ_SETTINGS rws; + NF_PAL_SPI *palSpi = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + busIndex = (int8_t)stack.Arg1().NumericByRef().s4; + + if (stack.m_customState == 0) + { + // check if this SPI has been initialized + palSpi = GetNfPalfromBusIndex(busIndex); + if (palSpi->Handle == NULL) + { + // compose SPI_DEVICE_CONFIGURATION + // get ref to SpiBaseConfiguration from static _busConnectionSettings array, access it by index + config = (CLR_RT_HeapBlock *)pThis[Devices_Spi_SpiBus::FIELD_STATIC___busConnectionSettings] + .DereferenceArray() + ->GetElement(busIndex); + + // CS is always active low + SpiConfigs[busIndex].ChipSelectActive = false; + // always bus master + SpiConfigs[busIndex].BusMode = SpiBusMode_master; + + // internally SPI bus ID is zero based, so better take care of that here + SpiConfigs[busIndex].Spi_Bus = busIndex; + + SpiConfigs[busIndex].DeviceChipSelect = config[SpiBaseConfiguration::FIELD___csLine].NumericByRef().s4; + + // sanity check chip select line + if (SpiConfigs[busIndex].DeviceChipSelect < -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + SpiConfigs[busIndex].Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiMode].NumericByRef().s4; + SpiConfigs[busIndex].DataOrder16 = + (DataBitOrder)config[SpiBaseConfiguration::FIELD___dataFlow].NumericByRef().s4; + SpiConfigs[busIndex].Clock_RateHz = config[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRef().s4; + SpiConfigs[busIndex].ByteTime = (1.0 / SpiConfigs[busIndex].Clock_RateHz) * 1000 * 8; + SpiConfigs[busIndex].BusConfiguration = + (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___busConfiguration].NumericByRef().s4; + SpiConfigs[busIndex].MD16bits = + config[SpiBaseConfiguration::FIELD___databitLength].NumericByRef().s4 == 16 ? true : false; + // store this here too + palSpi->BufferIs16bits = SpiConfigs[busIndex].MD16bits; + + CPU_SPI_Initialize(busIndex, SpiConfigs[busIndex]); + } + + // Buffers used either for the SpanBye either for the Byte array + + if (isSpanByte) + { + // dereference the write and read SpanByte from the arguments + writeSpanByte = stack.Arg1().Dereference(); + + if (writeSpanByte != NULL) + { + // get buffer + writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (writeBuffer != NULL) + { + // Get the write offset, only the elements defined by the span must be written, not the whole + // array + writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as write size, only the elements defined by the span must be written + writeSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + writeData = (unsigned char *)writeBuffer->GetElement(writeOffset); + } + } + + if (writeData == NULL) + { + // nothing to write, have to zero this + writeSize = 0; + } + + readSpanByte = stack.Arg2().Dereference(); + + if (readSpanByte != NULL) + { + // get buffer + readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); + + if (readBuffer != NULL) + { + // Get the read offset, only the elements defined by the span must be read, not the whole array + readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + + // use the span length as read size, only the elements defined by the span must be read + readSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + readData = (unsigned char *)readBuffer->GetElement(readOffset); + } + } + + if (readData == NULL) + { + // nothing to read, have to zero this + readSize = 0; + } + } + else + { + writeBuffer = stack.Arg1().DereferenceArray(); + + if (writeBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + writeData = (unsigned char *)writeBuffer->GetFirstElementUInt16(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + writeSize = writeBuffer->m_numOfElements; + } + + readBuffer = stack.Arg2().DereferenceArray(); + + if (readBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + readData = (unsigned char *)readBuffer->GetFirstElementUInt16(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + readSize = readBuffer->m_numOfElements; + } + } + + // assuming full duplex all the time + fullDuplex = true; + + // Set up read/write settings for SPI_Write_Read call + rws = {fullDuplex, 0, palSpi->BufferIs16bits, 0}; + + // Check to see if we should run async so as not to hold up other tasks + isLongRunningOperation = System_Device_IsLongRunningOperation( + writeSize, + readSize, + fullDuplex, + palSpi->BufferIs16bits, + SpiConfigs[busIndex].ByteTime, + (uint32_t &)estimatedDurationMiliseconds); + + if (isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in + // milliseconds this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + + // Use twice the estimated Duration as timeout + estimatedDurationMiliseconds *= 2; + + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + // if m_customState == 0 then push timeout on to eval stack[0] then move to m_customState = 1 + // Return current timeout value + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // protect the buffers from GC so DMA can find them where they are supposed to be + if (writeData != NULL) + { + CLR_RT_ProtectFromGC gcWriteBuffer(*writeBuffer); + } + if (readData != NULL) + { + CLR_RT_ProtectFromGC gcReadBuffer(*readBuffer); + } + + // Set callback for async calls to nano spi + rws.callback = Com_Sky_Spi_Callback; + } + + // Start SPI transfer + // We can ask for async transfer by setting callback but it depends if underlying supports it + // return of CLR_E_BUSY means async started + hr = SPI_nWrite_nRead( + palSpi, + SpiConfigs[busIndex], + rws, + (uint8_t *)writeData, + (int32_t)writeSize, + (uint8_t *)readData, + (int32_t)readSize); + + // Async transfer started, go to custom 2 state (wait completion) + if (hr == CLR_E_BUSY) + { + stack.m_customState = 2; + } + } + + // Waiting for Async operation to complete + if (stack.m_customState == 2) + { + // Get timeout from eval stack we set up + stack.SetupTimeoutFromTicks(hbTimeout, timeout); + + while (eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Spi transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_SpiMaster, eventResult)); + + if (!eventResult) + { + // Timeout + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // null pointers and vars + pThis = NULL; + } + + NANOCLR_NOCLEANUP(); +} + +static HRESULT SPI_nWrite_nRead( + NF_PAL_SPI *palSpi, + SPI_DEVICE_CONFIGURATION &sdev, + SPI_WRITE_READ_SETTINGS &wrc, + uint8_t *writeBuffer, + int32_t writeSize, + uint8_t *readBuffer, + int32_t readSize) +{ + NANOCLR_HEADER(); + + bool busConfigIsHalfDuplex; + + // If callback then use async operation + bool sync = (wrc.callback == 0); + + // Save width of transfer + palSpi->BufferIs16bits = wrc.Bits16ReadWrite; + + // Callback sync / async + palSpi->Callback = wrc.callback; + + if (writeBuffer != NULL) + { + palSpi->WriteSize = writeSize; + } + + if (readBuffer != NULL) + { + palSpi->ReadSize = readSize; + } + + // === Setup the operation and init buffers === + palSpi->BusIndex = sdev.Spi_Bus; + + // adjust the bus index to match the PAL struct + NF_SpiDriver_SetFramelength(palSpi->Handle, wrc.Bits16ReadWrite ? 16 : 8); + + // set bus config flag + busConfigIsHalfDuplex = (palSpi->BusConfiguration == SpiBusConfiguration_HalfDuplex); + + if (writeBuffer != NULL) + { + // set the pointer to the write buffer as BYTE + palSpi->WriteBuffer = (uint8_t *)writeBuffer; + } + + if (readBuffer != NULL) + { + // set DMA read buffer + if (palSpi->ReadSize > 0) + { + palSpi->ReadBuffer = (uint8_t *)readBuffer; + } + } + + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) + { + // assert pin based on CS active level + CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); + } + + if (sync) + { + // Sync operation + // perform SPI operation using driver's SYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (wrc.fullDuplex) + { + // Full duplex + // Uses the largest buffer size as transfer size + NF_SpiDriver_TransferBlocking( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->ReadBuffer, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize); + } + else + { + // send operation + // TODO + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; + // } + NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + + // receive operation + // TODO + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // receive + // TODO + // if (busConfigIsHalfDuplex) + // { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; + // } + NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + } + else + { + // send + // TODO + if (busConfigIsHalfDuplex) + { + // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; + } + NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + } + } + + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) + { + // de-assert pin based on CS active level + CPU_GPIO_TogglePinState(palSpi->ChipSelect); + } + } + else + { + // Start an Asyncronous SPI transfer + // perform SPI operation using driver's ASYNC API + // Completed on calling SPI Callback + + // if CS is to be controlled by the driver, set the GPIO + if (palSpi->ChipSelect >= 0) + { + // assert pin based on CS active level + CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); + } + + // this is a Async operation + // perform SPI operation using driver's ASYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (wrc.fullDuplex) + { + // Full duplex + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // Uses the largest buffer size as transfer size + NF_SpiDriver_Transfer( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->ReadBuffer, + palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, + SpiTransferCompleteCallback); + } + else + { + // flag that an Rx is required after the Tx operation completes + palSpi->SequentialTxRx = true; + + // start send operation + if (busConfigIsHalfDuplex) + { + // // half duplex operation, set output enable + // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; + } + + // receive operation will be started in the callback after the above completes + NF_SpiDriver_Transmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start receive + NF_SpiDriver_Receive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + } + else + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start send + NF_SpiDriver_Transmit( + palSpi->Handle, + palSpi->WriteBuffer, + palSpi->WriteSize, + SpiTransferCompleteCallback); + } + } + + // Inform caller async operation started + NANOCLR_SET_AND_LEAVE(CLR_E_BUSY); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_CHECK_HRESULT(ExecuteTransfer(stack, true)); NANOCLR_NOCLEANUP(); } -HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_CHECK_HRESULT(ExecuteTransfer(stack, false)); NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h index bb77b1f84d..46eefca216 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h @@ -8,161 +8,10 @@ #include #include -#include +#include #include <../System.Device.Spi/nf_gecko_spi_driver.h> +#include <../System.Device.Spi/sys_dev_spi_native_target.h> -#define SL_SPIDRV_EXP_BITRATE 1000000 - -// set missing defines -#if defined(USART0) -#ifndef GECKO_USE_SPI0 -#define GECKO_USE_SPI0 FALSE -#endif -#else -#define GECKO_USE_SPI0 FALSE -#endif - -#if defined(USART1) -#ifndef GECKO_USE_SPI1 -#define GECKO_USE_SPI1 FALSE -#endif -#else -#define GECKO_USE_SPI1 FALSE -#endif - -#if defined(USART2) -#ifndef GECKO_USE_SPI2 -#define GECKO_USE_SPI2 FALSE -#endif -#else -#define GECKO_USE_SPI2 FALSE -#endif - -#if defined(USART3) -#ifndef GECKO_USE_SPI3 -#define GECKO_USE_SPI3 FALSE -#endif -#else -#define GECKO_USE_SPI3 FALSE -#endif - -#if defined(USART4) -#ifndef GECKO_USE_SPI4 -#define GECKO_USE_SPI4 FALSE -#endif -#else -#define GECKO_USE_SPI4 FALSE -#endif - -#if defined(USART5) -#ifndef GECKO_USE_SPI5 -#define GECKO_USE_SPI5 FALSE -#endif -#else -#define GECKO_USE_SPI5 FALSE -#endif - -struct NF_PAL_SPI -{ - int BusIndex; - SpiBusConfiguration BusConfiguration; - - SPI_Callback Callback; - - bool SequentialTxRx; - bool BufferIs16bits; - - uint8_t *WriteBuffer; - uint16_t WriteSize; - - uint8_t *ReadBuffer; - uint16_t ReadSize; - - // -1 = Chip Select is not handled | >0 Chip Select is to be controlled with this GPIO - int32_t ChipSelect; - - // DMA transfer control - Gecko_SpiDriver *Driver; -}; - -//////////////////////////////////////////// -// declaration of the the SPI PAL structs // -//////////////////////////////////////////// -#if GECKO_USE_SPI0 == TRUE -extern NF_PAL_SPI SPI0_PAL; -#endif -#if GECKO_USE_SPI1 == TRUE -extern NF_PAL_SPI SPI1_PAL; -#endif -#if GECKO_USE_SPI2 == TRUE -extern NF_PAL_SPI SPI2_PAL; -#endif -#if GECKO_USE_SPI3 == TRUE -extern NF_PAL_SPI SPI3_PAL; -#endif -#if GECKO_USE_SPI4 == TRUE -extern NF_PAL_SPI SPI4_PAL; -#endif -#if GECKO_USE_SPI5 == TRUE -extern NF_PAL_SPI SPI5_PAL; -#endif - -#if defined(_USART_ROUTELOC0_MASK) - -// the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral -// it gets called in the System_Device_SPi_SPiDevice::NativeInit function -// this is required because the SPI peripherals can use multiple GPIO configuration combinations -#define SPI_CONFIG_PINS( \ - num, \ - gpio_port_sck, \ - sck_pin, \ - sck_port_location, \ - gpio_port_mosi, \ - mosi_pin, \ - mosi_port_location, \ - gpio_port_miso, \ - miso_pin, \ - miso_port_location) \ - void ConfigPins_SPI##num(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig) \ - { \ - GPIO_PinModeSet(gpio_port_sck, sck_pin, gpioModePushPull, 0); \ - SPI##num##_PAL.Driver->Usart->ROUTELOC0 = (SPI##num##_PAL.Driver->Usart->ROUTELOC0 & \ - ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | \ - _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | \ - mosi_port_location | \ - (sck_port_location << _USART_ROUTELOC0_CLKLOC_SHIFT); \ - if (spiDeviceConfig.BusConfiguration == SpiBusConfiguration_HalfDuplex) \ - { \ - SPI##num##_PAL.Driver->Usart->CTRL |= USART_CTRL_LOOPBK; \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ - } \ - else \ - { \ - GPIO_PinModeSet(gpio_port_mosi, mosi_pin, gpioModePushPull, 0); \ - GPIO_PinModeSet(gpio_port_miso, miso_pin, gpioModeInput, 0); \ - SPI##num##_PAL.Driver->Usart->ROUTELOC0 |= \ - (miso_port_location) | (mosi_port_location << _USART_ROUTELOC0_TXLOC_SHIFT); \ - } \ - SPI##num##_PAL.Driver->Usart->ROUTEPEN = \ - USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_TXPEN | \ - (spiDeviceConfig.BusConfiguration != SpiBusConfiguration_HalfDuplex) \ - ? USART_ROUTEPEN_RXPEN \ - : 0; \ - } - -#else -#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." -#endif - -////////////////////////////////////////////////////////////////////////////////////////////// -// when an SPI is defined the declarations below will have the real function/configuration // -// in the target folder @ target_windows_devices_spi_config.cpp // -////////////////////////////////////////////////////////////////////////////////////////////// -void ConfigPins_SPI0(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI1(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI2(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI3(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI4(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); -void ConfigPins_SPI5(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig); +// all PAL declarations are coming from CPU SPI #endif // SYS_DEV_SPI_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h new file mode 100644 index 0000000000..cc790a9b24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/target_system_device_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +//////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE // +//////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 76c5708c5e..7dabb10bc4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -45,7 +45,7 @@ static void CompleteTransfer(NF_SpiDriver_Handle_t handle) } // Callback used when a async transfer operation completes -static void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) +void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) { (void)transferStatus; (void)itemsTransferred; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 0cff2950ee..74b69316c0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -12,7 +12,7 @@ #include #include -#include +#include "nf_gecko_spi_driver.h" // set missing defines #if defined(USART0) From c5a98a4fa7bfdd892ad5f7f20c2f44f4771a8064 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 Aug 2022 10:05:21 +0100 Subject: [PATCH 088/572] Move ByteTime field to SPI_DEVICE_CONFIGURATION - Update code accordingly. --- src/HAL/Include/nanoHAL_Spi.h | 1 - src/PAL/Include/CPU_SPI_decl.h | 3 +++ src/System.Device.Spi/nanoHAL_Spi.cpp | 12 ++++++------ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/HAL/Include/nanoHAL_Spi.h b/src/HAL/Include/nanoHAL_Spi.h index 9c68bd24d6..072af6097a 100644 --- a/src/HAL/Include/nanoHAL_Spi.h +++ b/src/HAL/Include/nanoHAL_Spi.h @@ -20,7 +20,6 @@ struct nanoSPI_BusConfig int8_t devicesInUse; SPI_DEVICE_CONFIGURATION deviceConfig[MAX_SPI_DEVICES]; uint32_t deviceHandles[MAX_SPI_DEVICES]; - float byteTime[MAX_SPI_DEVICES]; SPI_OP_STATUS spiStatus; }; diff --git a/src/PAL/Include/CPU_SPI_decl.h b/src/PAL/Include/CPU_SPI_decl.h index 9da523f60a..605c7cb021 100644 --- a/src/PAL/Include/CPU_SPI_decl.h +++ b/src/PAL/Include/CPU_SPI_decl.h @@ -77,6 +77,9 @@ struct SPI_DEVICE_CONFIGURATION bool MD16bits; // Data order for 16 bit operation DataBitOrder DataOrder16; + // Rough estimate on the time it takes to send/receive one byte (in milliseconds) + // Used to compute length of time for each IO to see if this is a long running operation + float ByteTime; // Master Only uint32_t Clock_RateHz; // Master - SPI bus clock frequency, in hertz (Hz). diff --git a/src/System.Device.Spi/nanoHAL_Spi.cpp b/src/System.Device.Spi/nanoHAL_Spi.cpp index 7302c93a53..f5e86c9cb0 100644 --- a/src/System.Device.Spi/nanoHAL_Spi.cpp +++ b/src/System.Device.Spi/nanoHAL_Spi.cpp @@ -347,16 +347,16 @@ HRESULT nanoSPI_OpenDeviceEx( } } + // Compute rough estimate on the time to tx/rx a byte (in milliseconds) + // Used to compute length of time for each IO to see if this is a long running operation + // Store for each device as each device could use a different bit rate + spiDeviceConfig.ByteTime = (1.0 / spiDeviceConfig.Clock_RateHz) * 1000.0 * 8; + // Add next Device - Copy device config, save handle, increment number devices on bus nanoSPI_BusConfig *pBusConfig = &spiconfig[spiDeviceConfig.Spi_Bus]; pBusConfig->deviceConfig[spiDeviceConfig.Spi_Bus] = spiDeviceConfig; pBusConfig->deviceHandles[spiDeviceConfig.Spi_Bus] = deviceHandle; - // Compute rough estimate on the time to tx/rx a byte (in milliseconds) - // Used to compute length of time for each IO to see if this is a long running operation - // Store for each device as each device could use a different bit rate - pBusConfig->byteTime[spiDeviceConfig.Spi_Bus] = (float)(1.0 / spiDeviceConfig.Clock_RateHz) * 1000 * 8; - pBusConfig->devicesInUse++; // Return unique generated device handle @@ -419,7 +419,7 @@ float nanoSPI_GetByteTime(uint32_t handle) getDevice(handle, spiBus, deviceIndex); - return spiconfig[spiBus].byteTime[deviceIndex]; + return spiconfig[spiBus].deviceConfig->ByteTime; } void nanoSPI_Wait_Busy(uint32_t handle) From 6da313c5fc57af23fcc4454b06804af51bf1389a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 12 Aug 2022 01:50:35 +0100 Subject: [PATCH 089/572] Implement half duolex SPI --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 1 + .../System.Device.Spi/nf_gecko_spi_driver.cpp | 19 +++++++++++++++++-- .../System.Device.Spi/nf_gecko_spi_driver.h | 1 + 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 76c5708c5e..1e848afa5e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -223,6 +223,7 @@ void GetSpiConfig(const SPI_DEVICE_CONFIGURATION &config, NF_SpiDriver_Init_t &i // Sets the order of bytes transmission : MSB first or LSB first initSpiData.bitOrder = config.DataOrder16 == DataBitOrder_MSB ? spidrvBitOrderMsbFirst : spidrvBitOrderLsbFirst; initSpiData.frameLength = config.MD16bits ? 16 : 8; + initSpiData.isHalfDuplex = config.BusConfiguration == SpiBusConfiguration_HalfDuplex ? true : false; } // Performs a read/write operation on 8-bit word data. diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp index 6e930f94a4..63da94ffc6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -334,9 +334,13 @@ static Ecode_t NF_SpiDriver_InitUsart(NF_SpiDriver_Handle_t handle, NF_SpiDriver handle->peripheral.usartPort->CTRL |= USART_CTRL_AUTOCS; } + if (initData->isHalfDuplex) + { + handle->peripheral.usartPort->CTRL |= USART_CTRL_LOOPBK; + } + if (initData->csControl == spidrvCsControlAuto) { - // SPI 4 wire mode #if defined(USART_ROUTEPEN_TXPEN) handle->peripheral.usartPort->ROUTELOC0 = (handle->peripheral.usartPort->ROUTELOC0 & ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | @@ -371,7 +375,6 @@ static Ecode_t NF_SpiDriver_InitUsart(NF_SpiDriver_Handle_t handle, NF_SpiDriver } else { - // SPI 3 wire mode #if defined(USART_ROUTEPEN_TXPEN) handle->peripheral.usartPort->ROUTELOC0 = (handle->peripheral.usartPort->ROUTELOC0 & @@ -1155,6 +1158,12 @@ static bool RxDMAComplete(unsigned int channel, handle = (NF_SpiDriver_Handle_t)userParam; + if (handle->initData->isHalfDuplex) + { + // Turn off TX tri-stating + handle->peripheral.usartPort->CMD = USART_CMD_TXTRIDIS; + } + handle->transferStatus = ECODE_EMDRV_SPIDRV_OK; handle->state = spidrvStateIdle; handle->remaining = 0; @@ -1192,6 +1201,12 @@ static void StartReceiveDMA(NF_SpiDriver_Handle_t handle, { handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + if (handle->initData->isHalfDuplex) + { + // Block RX while sending from master + handle->peripheral.usartPort->CMD = USART_CMD_RXBLOCKEN; + } + if (handle->initData->frameLength > 9) { rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h index 2cca5c02fb..39e17cbaf9 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h @@ -137,6 +137,7 @@ extern "C" NF_SpiDriver_BitOrder_t bitOrder; ///< A bit order on the SPI bus, MSB or LSB first. NF_SpiDriver_ClockMode_t clockMode; ///< SPI mode, CLKPOL/CLKPHASE setting. NF_SpiDriver_CsControl_t csControl; ///< A select master mode chip select (CS) control scheme. + bool isHalfDuplex; ///< True if the SPI is half duplex. } NF_SpiDriver_Init_t; /// An SPI driver instance handle data structure. From 368ca30465282a0d818658582211a6a5b3957594 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 16 Aug 2022 15:02:09 +0100 Subject: [PATCH 090/572] Fix Azure USBx include from github --- CMake/binutils.AzureRTOS.cmake | 10 +++++++++- targets/AzureRTOS/CMakeLists.txt | 3 ++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index ce01032134..ba015e0234 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -412,13 +412,21 @@ macro(nf_add_platform_sources target) ${TARGET_AZURERTOS_NANOCLR_SOURCES} ) - if(AZURERTOS_NETXDUO_REQUIRED) + if(USE_NETWORKING_OPTION) target_link_libraries(${target}.elf nano::NF_Network azrtos::netxduo ) endif() + if(USBX_FEATURE_HID_OPTION) + target_link_libraries(${target}.elf + azrtos::netxduo + azrtos::filex + azrtos::usbx + ) + endif() + endif() if(STM32_CUBE_PACKAGE_REQUIRED) diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index 6f1b4584c0..f097d9ff09 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -129,7 +129,8 @@ if(AZURERTOS_USBX_REQUIRED) FetchContent_Declare( azure_rtos_usbx - SOURCE_DIR https://github.com/azure-rtos/usbx.git + GIT_REPOSITORY https://github.com/azure-rtos/usbx.git + GIT_TAG ${RTOS_VERSION} ) else() From 1d89f1b6e31c8159386da1928c0188ad19566f50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 16 Aug 2022 16:28:16 +0100 Subject: [PATCH 091/572] Work adding USBx to build and config target --- CMake/binutils.AzureRTOS.cmake | 3 +- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 6 +- .../SiliconLabs/SL_STK3701A/target_ux_user.h | 345 ++++++++++++++++++ 3 files changed, 350 insertions(+), 4 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_ux_user.h diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index ba015e0234..3eb5ff8373 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -157,7 +157,8 @@ macro(nf_add_platform_packages) # need to add ThreadX extension in order to use BSD if("${TARGET_SERIES}" STREQUAL "STM32F7xx") set(TX_PORT_FILE ${azure_rtos_SOURCE_DIR}/ports/cortex_m7/gnu/inc/tx_port.h) - elseif("${TARGET_SERIES}" STREQUAL "STM32L4xx") + elseif("${TARGET_SERIES}" STREQUAL "STM32L4xx" + OR "${TARGET_SERIES}" STREQUAL "EFM32GG11") set(TX_PORT_FILE ${azure_rtos_SOURCE_DIR}/ports/cortex_m4/gnu/inc/tx_port.h) else() message(FATAL_ERROR "Support for NetX Duo is not implemented for ${TARGET_SERIES}.") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index a53c266dd1..5e16a92bcd 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -11,12 +11,12 @@ set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable T # set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") # set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") -# set(STM32_DRIVER_TARGET_DEVICE STM32L475xx CACHE BOOL "Set STM32 target for HAL Driver") - set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) -# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) nf_setup_target_build( HAS_NANOBOOTER diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From ac6871c8ac86aed9baba6aeadc1d1f5605799fc3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 16 Aug 2022 16:28:35 +0100 Subject: [PATCH 092/572] Add build option for HID and Azure USBx --- targets/AzureRTOS/CMakeLists.txt | 16 ++++++++++++++++ .../SiliconLabs/_nanoCLR/target_platform.h.in | 1 + 2 files changed, 17 insertions(+) diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index f097d9ff09..9bee764449 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -14,6 +14,7 @@ option(AZURERTOS_USBX_REQUIRED "option to include Azure RTOS USBX") option(AZURERTOS_FILEX_REQUIRED "option to include Azure RTOS FileX") option(AZURERTOS_NETXDUO_REQUIRED "option to include Azure RTOS NetX Duo") option(USBX_FEATURE_CDC "option to use USBX CDC class") +option(USBX_FEATURE_HID "option to use USBX HID class") if(USBX_FEATURE_CDC) @@ -30,6 +31,21 @@ else() set(USBX_FEATURE_CDC_OPTION FALSE CACHE INTERNAL "USBX_FEATURE_CDC_OPTION for USBX_FEATURE_CDC") endif() +if(USBX_FEATURE_HID) + + set(USBX_FEATURE_HID_OPTION TRUE CACHE INTERNAL "USBX_FEATURE_HID_OPTION for USBX_FEATURE_HID") + # requires: + # AZURERTOS_USBX_REQUIRED + set(AZURERTOS_USBX_REQUIRED ON CACHE INTERNAL "AZURERTOS_USBX_REQUIRED for USBX_FEATURE_HID") + # AZURERTOS_FILEX_REQUIRED + set(AZURERTOS_FILEX_REQUIRED ON CACHE INTERNAL "AZURERTOS_FILEX_REQUIRED for USBX_FEATURE_HID") + # AZURERTOS_NETXDUO_REQUIRED + set(AZURERTOS_NETXDUO_REQUIRED ON CACHE INTERNAL "AZURERTOS_NETXDUO_REQUIRED for USBX_FEATURE_HID") + +else() + set(USBX_FEATURE_HID_OPTION FALSE CACHE INTERNAL "USBX_FEATURE_HID_OPTION for USBX_FEATURE_HID") +endif() + if(USE_NETWORKING_OPTION) set(AZURERTOS_NETXDUO_REQUIRED ON CACHE INTERNAL "AZURERTOS_NETXDUO_REQUIRED for Networking") endif() diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index cd2a9091a6..1ace91bd3f 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -29,5 +29,6 @@ // #define HAL_NF_USE_STM32_ONEWIRE @HAL_USE_STM32_ONEWIRE_OPTION@ // #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSD_OPTION@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ +#define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ #endif // TARGET_PLATFORM_H From 1dd836e82d86a0983a27e4f9f2680519df608eba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 17 Aug 2022 14:20:06 +0100 Subject: [PATCH 093/572] Adding USB HID from Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 30 +- CMake/binutils.AzureRTOS.cmake | 1 + targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 11 + .../autogen/sl_usbd_class_hid_instances.c | 299 ++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 43 ++ .../autogen/sl_usbd_configuration_instances.c | 66 +++ .../autogen/sl_usbd_configuration_instances.h | 20 + .../config/sl_usbd_class_mouse0_config.h | 143 +++++++ .../config/sl_usbd_config0_config.h | 51 +++ .../SL_STK3701A/config/sl_usbd_core_config.h | 196 +++++++++ .../config/sl_usbd_device_config.h | 62 +++ .../SL_STK3701A/nanoCLR/CMakeLists.txt | 4 + .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 13 + .../SL_STK3701A/nanoCLR/usb_hid_app.c | 284 +++++++++++++ .../_common/autogen/sl_component_catalog.h | 12 + .../_common/autogen/sl_event_handler.c | 13 + .../_common/autogen/sl_event_handler.h | 2 + .../_common/autogen/sl_usbd_init.c | 47 +++ .../_common/autogen/sl_usbd_init.h | 7 + .../_common/sl_usbd_class_hid_azurertos.c | 386 ++++++++++++++++++ .../_common/sl_usbd_core_azuretos.c | 364 +++++++++++++++++ .../_include/sli_usbd_class_hid_azurertos.h | 196 +++++++++ .../SiliconLabs/_nanoCLR/target_platform.h.in | 1 + 23 files changed, 2250 insertions(+), 1 deletion(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c create mode 100644 targets/AzureRTOS/SiliconLabs/_include/sli_usbd_class_hid_azurertos.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 120417bd00..456e80096a 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -37,7 +37,13 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdr list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/CLR/Include) +if(GECKO_FEATURE_USBD_HID) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/inc) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/src) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/util/silicon_labs/silabs_core/memory_manager) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common/include) +endif() # general files set(gecko_sdk_srcs @@ -105,6 +111,7 @@ set(gecko_sdk_srcs sl_i2cspm.c sl_iostream_handles.c sl_iostream_init_usart_instances.c + sl_string.c # nanoFramework implementations # nano_sl_i2cspm.c @@ -121,6 +128,22 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs system_efm32gg11b.c) list(APPEND gecko_sdk_srcs startup_efm32gg11b.c) + if(GECKO_FEATURE_USBD_HID) + + list(APPEND gecko_sdk_srcs sl_usbd_class_hid_azurertos.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_hid_report.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_hid.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_hid_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_init.c) + list(APPEND gecko_sdk_srcs sl_malloc.c) + + endif() + foreach(src_file ${gecko_sdk_srcs}) set(gecko_sdk_src_file src_file-NOTFOUND) @@ -143,7 +166,12 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") ${gecko_sdk_SOURCE_DIR}/platform/service/system/src ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/src ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/src + ${gecko_sdk_SOURCE_DIR}/util/silicon_labs/silabs_core/memory_manager + # USBD HID + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src + ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common + # device specific paths ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index 3eb5ff8373..efa5595fdd 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -454,6 +454,7 @@ macro(nf_add_platform_sources target) ${target} EXTRA_INCLUDES ${AZRTOS_INCLUDES} + ${NF_CoreCLR_INCLUDE_DIRS} ) add_dependencies(${target}.elf nano::gecko_sdk_${target}) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index a06761a89f..664aa6866f 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -8,8 +8,19 @@ include(Gecko_SDK) set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) +option(GECKO_FEATURE_USBD_HID "option to use Gecko SDK HID class") + ProcessGSDKPackage() +if(GECKO_FEATURE_USBD_HID) + + set(GECKO_FEATURE_USBD_HID_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_HID for USBD HID") + +else() + set(GECKO_FEATURE_USBD_HID_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_HID for USBD HID") +endif() + + # check if GECKO_SDK_SOURCE was specified or if it's empty (default is empty) set(NO_GECKO_SDK_SOURCE TRUE) if(GECKO_SDK_SOURCE) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..2e83a4a058 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,299 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" +#include "sl_usbd_core.h" +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include "sl_usbd_class_mouse0_config.h" + + +//**************************************************************************** +// Function declarations. + + + +/* callback prototypes for mouse0 instance */ +void sli_usbd_hid_mouse0_enable(uint8_t class_nbr); + +void sli_usbd_hid_mouse0_disable(uint8_t class_nbr); + +void sli_usbd_hid_mouse0_get_report_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len); + +void sli_usbd_hid_mouse0_get_phy_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len); + +void sli_usbd_hid_mouse0_set_output_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_mouse0_get_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_mouse0_set_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_mouse0_get_protocol(uint8_t class_nbr, + uint8_t *p_protocol); + +void sli_usbd_hid_mouse0_set_protocol(uint8_t class_nbr, + uint8_t protocol); + + +//**************************************************************************** +// Global variables. + + + + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_mouse0_number = 0; + +uint8_t sl_usbd_hid_mouse0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_mouse0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CA_MOUSE, + SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_APPLICATION, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CP_POINTER, + SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_PHYSICAL, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_BUTTON, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, + SL_USBD_HID_MAIN_ENDCOLLECTION +}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_mouse0_callbacks = { + sli_usbd_hid_mouse0_enable, + sli_usbd_hid_mouse0_disable, + sli_usbd_hid_mouse0_get_report_desc, + sli_usbd_hid_mouse0_get_phy_desc, + sli_usbd_hid_mouse0_set_output_report, + sli_usbd_hid_mouse0_get_feature_report, + sli_usbd_hid_mouse0_set_feature_report, + sli_usbd_hid_mouse0_get_protocol, + sli_usbd_hid_mouse0_set_protocol, +}; + + + +//**************************************************************************** +// Callback functions. + + + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_mouse0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_mouse0_on_enable_event(); + + return; +} + +void sli_usbd_hid_mouse0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_mouse0_on_disable_event(); + + return; +} + +void sli_usbd_hid_mouse0_get_report_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_mouse0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_mouse0_default_desc); + + sl_usbd_hid_mouse0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_mouse0_get_phy_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_mouse0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_mouse0_set_output_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_mouse0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + + +void sli_usbd_hid_mouse0_get_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_mouse0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_mouse0_set_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_mouse0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_mouse0_get_protocol(uint8_t class_nbr, + uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_mouse0_default_protocol; + + sl_usbd_hid_mouse0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_mouse0_set_protocol(uint8_t class_nbr, + uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_mouse0_default_protocol = protocol; + + sl_usbd_hid_mouse0_on_set_protocol_event(protocol); + + return; +} + + +//**************************************************************************** +// Global functions. + + + +/* initialize mouse0 instance */ +void sli_usbd_hid_mouse0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_MOUSE0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_MOUSE0_SUBCLASS; + protocol = SL_USBD_HID_MOUSE0_PROTOCOL; + country = SL_USBD_HID_MOUSE0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_MOUSE0_INTERVAL_IN; + interval_out = SL_USBD_HID_MOUSE0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_MOUSE0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance(subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_mouse0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_mouse0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + + /* next token */ + token = strtok(NULL, ", "); + } +} + diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..248d23309b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,43 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_mouse0_number; + + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_mouse0_on_enable_event(void); +__WEAK void sl_usbd_hid_mouse0_on_disable_event(void); +__WEAK void sl_usbd_hid_mouse0_on_get_report_desc_event(const uint8_t **p_report_ptr, + uint16_t *p_report_len); +__WEAK void sl_usbd_hid_mouse0_on_get_phy_desc_event(const uint8_t **p_report_ptr, + uint16_t *p_report_len); +__WEAK void sl_usbd_hid_mouse0_on_set_output_report_event(uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); +__WEAK void sl_usbd_hid_mouse0_on_get_feature_report_event(uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); +__WEAK void sl_usbd_hid_mouse0_on_set_feature_report_event(uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); +__WEAK void sl_usbd_hid_mouse0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_mouse0_on_set_protocol_event(uint8_t protocol); + + +/* init functions for all HID instances */ + +void sli_usbd_hid_mouse0_init(void); + + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..3ff6c727c9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,66 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" +#include "sl_usbd_core.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include "sl_usbd_config0_config.h" + + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + + +//**************************************************************************** +// Global functions. + + + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} + diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..500dd508c3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h new file mode 100644 index 0000000000..2df9c9b721 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_MOUSE0_CONFIG_H +#define SL_USBD_HID_MOUSE0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_MOUSE0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_MOUSE0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_MOUSE0_PROTOCOL SL_USBD_HID_PROTOCOL_MOUSE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_MOUSE0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_MOUSE0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_MOUSE0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_MOUSE0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_MOUSE0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..24ec038d55 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -0,0 +1,196 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..ab4e1b65b3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h @@ -0,0 +1,62 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Default: 0xFFFE +// Device vendor ID. +#define SL_USBD_DEVICE_VENDOR_ID 0xFFFE + +// Device Product ID +// Default: 0x1234 +// Device product ID. +#define SL_USBD_DEVICE_PRODUCT_ID 0x1234 + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Default: "Silicon Labs" +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Silicon Labs" + +// Device Product Name +// Default: "Product" +// Device product string. +#define SL_USBD_DEVICE_PRODUCT_STRING "Product" + +// Device Serial Number +// Default: "1234567890ABCDEF" +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING "1234567890ABCDEF" + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt index 3eee9275ee..966b5a01c7 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/CMakeLists.txt @@ -7,5 +7,9 @@ list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + # make var global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 1626c3a82f..678c9e4479 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -18,6 +18,11 @@ #include // #include +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_mouse0_init(void); +extern void sli_usbd_init(void); + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; extern CLR_SETTINGS clrSettings; @@ -157,6 +162,14 @@ void tx_application_define(void *first_unused_memory) { } } + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_hid_mouse0_init(); + + usb_device_hid_app_init(); +#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..3427756176 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c @@ -0,0 +1,284 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include "sl_usbd_core.h" +#include "sl_usbd_class_hid.h" + +#include "sl_usbd_class_hid_instances.h" + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_MOUSE_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Current protocol selected by host. +static uint8_t usb_hid_mouse_protocol; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_mouse_report_buffer[USB_HID_MOUSE_REPORT_LEN]; + +// HID mouse report +// The report buffer is sent to the host when it requests the report descriptor. The report +// descriptor describes the device itself (axis, quantity of button, scroll wheel, etc) and +// how the data for each element is reported in the report. +static const uint8_t usb_hid_mouse_report_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CA_MOUSE, + SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_APPLICATION, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CP_POINTER, + SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_PHYSICAL, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_BUTTON, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +static void hid_mouse_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID Mouse task", + hid_mouse_task, + (uint32_t)&sl_usbd_hid_mouse0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_mouse_task() +// Perform HID writes to host. +// The HID writes simulate the movement of a mouse. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_mouse_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_mouse_report_buffer[0u] = 0u; + usb_hid_mouse_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_mouse_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_mouse_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_mouse_report_buffer, USB_HID_MOUSE_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_mouse0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_mouse0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_mouse0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + + *p_report_ptr = usb_hid_mouse_report_desc; + *p_report_len = sizeof(usb_hid_mouse_report_desc); +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_mouse0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + + *p_report_ptr = NULL; + *p_report_len = 0; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_mouse0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_mouse0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + + memset(p_report_buf, 0, report_len); +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_mouse0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_mouse0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + + *p_protocol = usb_hid_mouse_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_mouse0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + + usb_hid_mouse_protocol = protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h index d9773b6755..e03724e450 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h @@ -1,6 +1,8 @@ #ifndef SL_COMPONENT_CATALOG_H #define SL_COMPONENT_CATALOG_H +#include + // APIs present in project #define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT #define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT @@ -14,4 +16,14 @@ // TODO // #define SL_CATALOG_KERNEL_PRESENT +#if defined(I_AM_NANOCLR) && GECKO_FEATURE_USBD_HID == TRUE + +#define SL_CATALOG_USB_DEVICE_PRESENT +#define SL_CATALOG_USB_DEVICE_HID_PRESENT +#define SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#define SL_CATALOG_USB_DEVICE_CORE_PRESENT +#define SL_CATALOG_USB_DEVICE_DRIVER_PRESENT + +#endif + #endif // SL_COMPONENT_CATALOG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c index 2da9084cbe..867e03e34f 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c @@ -24,6 +24,7 @@ #include "sl_power_manager.h" #include +#include void sl_platform_init(void) { @@ -49,6 +50,7 @@ void sl_driver_init(void) { sl_i2cspm_init_instances(); sl_uartdrv_init_instances(); + sl_driver_init_target(); } void sl_service_init(void) @@ -60,6 +62,7 @@ void sl_service_init(void) void sl_stack_init(void) { + sl_stack_init_target(); } void sl_internal_app_init(void) @@ -86,3 +89,13 @@ void sl_iostream_init_instances(void) { sl_iostream_usart_init_instances(); } + +// provided as weak so it can be replaced at target level +__nfweak void sl_stack_init_target(void) +{ +} + +// provided as weak so it can be replaced at target level +__nfweak void sl_driver_init_target(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h index e4198ae67c..508c65c203 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.h @@ -18,5 +18,7 @@ void sl_service_process_action(void); void sl_stack_process_action(void); void sl_internal_app_process_action(void); void sl_iostream_init_instances(void); +void sl_stack_init_target(void); +void sl_driver_init_target(void); #endif // SL_EVENT_HANDLER_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c new file mode 100644 index 0000000000..a482c424dd --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -0,0 +1,47 @@ +//**************************************************************************** +// Includes. + +#include "sl_status.h" + + +#include "sl_usbd_core.h" + + + + + + + +#include "sl_usbd_class_hid.h" + + + + + + + + +//**************************************************************************** +// Global functions. + +/* USB initialization function */ +void sli_usbd_init(void) +{ + + sl_usbd_core_init(); + + + + + + + + sl_usbd_hid_init(); + + + + + + + +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.h new file mode 100644 index 0000000000..b6fe5dc21c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.h @@ -0,0 +1,7 @@ +#ifndef SL_USBD_INIT +#define SL_USBD_INIT + +/* USB initialization function */ +void sli_usbd_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c new file mode 100644 index 0000000000..4db5698b5d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c @@ -0,0 +1,386 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include + +// parameters for task +// static osThreadId_t timer_task_handle; +// static const osThreadAttr_t timer_task_attr = { +// .name = "HID Timer Thread", +// .attr_bits = 0, +// .stack_mem = NULL, +// .stack_size = (uint32_t)SL_USBD_HID_TIMER_TASK_STACK_SIZE, +// .cb_mem = NULL, +// .cb_size = 0, +// .priority = (osPriority_t)SL_USBD_HID_TIMER_TASK_PRIORITY}; +TX_THREAD timer_task_handle; +uint32_t timerThreadStack[SL_USBD_HID_TIMER_TASK_STACK_SIZE / sizeof(uint32_t)]; + +// parameters for event flags +// static osEventFlagsId_t input_eventflags_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; +// static osEventFlagsAttr_t input_eventflags_attr[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +static TX_EVENT_FLAGS_GROUP input_eventflags_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +// static osEventFlagsId_t output_eventflags_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; +// static osEventFlagsAttr_t output_eventflags_attr[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +static TX_EVENT_FLAGS_GROUP output_eventflags_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +#define EVENT_FLAG_COMPLETE 0x1 // signal posted +#define EVENT_FLAG_ABORT 0x2 // signal aborted + +// parameters for mutexes +// static osMutexId_t input_mutex_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; +// static osMutexAttr_t input_mutex_attr[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +static TX_MUTEX input_mutex_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +// static osMutexId_t output_mutex_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; +// static osMutexAttr_t output_mutex_attr[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +static TX_MUTEX output_mutex_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +// static osMutexId_t tx_mutex_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; +// static osMutexAttr_t tx_mutex_attr[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +static TX_MUTEX tx_mutex_handle[SL_USBD_HID_CLASS_INSTANCE_QUANTITY]; + +static void usbd_hid_os_timer_task(uint32_t p_arg); + +static uint32_t usbd_hid_os_ms_to_ticks(uint32_t milliseconds); + +// Initialize HID OS interface +sl_status_t sli_usbd_hid_os_init(void) +{ + uint32_t class_nbr; + uint16_t status; + + for (class_nbr = 0u; class_nbr < SL_USBD_HID_CLASS_INSTANCE_QUANTITY; class_nbr++) + { + // tx_mutex_attr[class_nbr].name = "HID Tx mutex"; + // tx_mutex_attr[class_nbr].attr_bits = 0; + // tx_mutex_attr[class_nbr].cb_mem = NULL; + // tx_mutex_attr[class_nbr].cb_size = 0; + + // tx_mutex_handle[class_nbr] = osMutexNew(&tx_mutex_attr[class_nbr]); + + if (tx_mutex_create(&tx_mutex_handle[class_nbr], "HID Tx mutex", TX_NO_INHERIT) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + // output_mutex_attr[class_nbr].name = "HID Output mutex"; + // output_mutex_attr[class_nbr].attr_bits = 0; + // output_mutex_attr[class_nbr].cb_mem = NULL; + // output_mutex_attr[class_nbr].cb_size = 0; + + // output_mutex_handle[class_nbr] = osMutexNew(&output_mutex_attr[class_nbr]); + + if (tx_mutex_create(&output_mutex_handle[class_nbr], "HID Output mutex", TX_NO_INHERIT) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + // input_mutex_attr[class_nbr].name = "HID Input mutex"; + // input_mutex_attr[class_nbr].attr_bits = 0; + // input_mutex_attr[class_nbr].cb_mem = NULL; + // input_mutex_attr[class_nbr].cb_size = 0; + + // input_mutex_handle[class_nbr] = osMutexNew(&input_mutex_attr[class_nbr]); + + if (tx_mutex_create(&input_mutex_handle[class_nbr], "HID Input mutex", TX_NO_INHERIT) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + // input_eventflags_attr[class_nbr].name = "HID input events"; + // input_eventflags_attr[class_nbr].attr_bits = 0; + // input_eventflags_attr[class_nbr].cb_mem = NULL; + // input_eventflags_attr[class_nbr].cb_size = 0; + + // input_eventflags_handle[class_nbr] = osEventFlagsNew(&input_eventflags_attr[class_nbr]); + + if (tx_event_flags_create(&input_eventflags_handle[class_nbr], "HID input events") != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + // output_eventflags_attr[class_nbr].name = "HID output events"; + // output_eventflags_attr[class_nbr].attr_bits = 0; + // output_eventflags_attr[class_nbr].cb_mem = NULL; + // output_eventflags_attr[class_nbr].cb_size = 0; + + // output_eventflags_handle[class_nbr] = osEventFlagsNew(&output_eventflags_attr[class_nbr]); + + if (tx_event_flags_create(&output_eventflags_handle[class_nbr], "HID output events") != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + } + + status = tx_thread_create( + &timer_task_handle, + "HID Timer Thread", + usbd_hid_os_timer_task, + 0, + timerThreadStack, + SL_USBD_HID_TIMER_TASK_STACK_SIZE, + SL_USBD_HID_TIMER_TASK_PRIORITY, + SL_USBD_HID_TIMER_TASK_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + // timer_task_handle = osThreadNew(usbd_hid_os_timer_task, NULL, &timer_task_attr); + + // if (timer_task_handle == NULL) + // { + // return SL_STATUS_FAIL; + // } + + return SL_STATUS_OK; +} + +// Lock class input report +sl_status_t sli_usbd_hid_os_lock_input(uint8_t class_nbr) +{ + if (tx_mutex_get(&input_mutex_handle[class_nbr], TX_WAIT_FOREVER) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Unlock class input report +sl_status_t sli_usbd_hid_os_unlock_input(uint8_t class_nbr) +{ + if (tx_mutex_put(&input_mutex_handle[class_nbr]) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Abort class output report +sl_status_t sli_usbd_hid_os_pend_abort_output(uint8_t class_nbr) +{ + if (tx_event_flags_set(&output_eventflags_handle[class_nbr], EVENT_FLAG_ABORT, TX_OR) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Wait for output report data transfer to complete +sl_status_t sli_usbd_hid_os_pend_output(uint8_t class_nbr, uint16_t timeout_ms) +{ + uint32_t ticks; + uint32_t status; + uint32_t actual_events; + + if (timeout_ms == 0) + { + ticks = TX_WAIT_FOREVER; + } + else + { + ticks = usbd_hid_os_ms_to_ticks(timeout_ms); + } + + status = tx_event_flags_get( + &output_eventflags_handle[class_nbr], + EVENT_FLAG_COMPLETE | EVENT_FLAG_ABORT, + TX_OR_CLEAR, + &actual_events, + ticks); + + if (status == TX_NO_EVENTS) + { + return SL_STATUS_TIMEOUT; + } + + if (status != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + if ((actual_events & EVENT_FLAG_ABORT) == EVENT_FLAG_ABORT) + { + return SL_STATUS_ABORT; + } + + return SL_STATUS_OK; +} + +// Signal that output report data is available +sl_status_t sli_usbd_hid_os_post_output(uint8_t class_nbr) +{ + if (tx_event_flags_set(&output_eventflags_handle[class_nbr], EVENT_FLAG_COMPLETE, TX_OR) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Lock class output report +sl_status_t sli_usbd_hid_os_lock_output(uint8_t class_nbr) +{ + if (tx_mutex_get(&output_mutex_handle[class_nbr], TX_WAIT_FOREVER) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Unlock class output report +sl_status_t sli_usbd_hid_os_unlock_output(uint8_t class_nbr) +{ + if (tx_mutex_put(&output_mutex_handle[class_nbr]) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Lock class transmit +sl_status_t sli_usbd_hid_os_lock_tx(uint8_t class_nbr) +{ + if (tx_mutex_get(&tx_mutex_handle[class_nbr], TX_WAIT_FOREVER) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Unlock class transmit +sl_status_t sli_usbd_hid_os_unlock_tx(uint8_t class_nbr) +{ + if (tx_mutex_put(&tx_mutex_handle[class_nbr]) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Wait for input report data transfer to complete +sl_status_t sli_usbd_hid_os_pend_input(uint8_t class_nbr, uint16_t timeout_ms) +{ + uint32_t ticks; + uint32_t status; + uint32_t actual_events; + + if (timeout_ms == 0) + { + ticks = TX_WAIT_FOREVER; + } + else + { + ticks = usbd_hid_os_ms_to_ticks(timeout_ms); + } + + status = tx_event_flags_get( + &input_eventflags_handle[class_nbr], + EVENT_FLAG_COMPLETE | EVENT_FLAG_ABORT, + TX_OR_CLEAR, + &actual_events, + ticks); + + if (status == TX_NO_EVENTS) + { + return SL_STATUS_TIMEOUT; + } + + if (status != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + if ((actual_events & EVENT_FLAG_ABORT) == EVENT_FLAG_ABORT) + { + return SL_STATUS_ABORT; + } + + return SL_STATUS_OK; +} + +// Abort any operation on input report +sl_status_t sli_usbd_hid_os_pend_abort_input(uint8_t class_nbr) +{ + if (tx_event_flags_set(&input_eventflags_handle[class_nbr], EVENT_FLAG_ABORT, TX_OR) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// Signal that input report data transfer has completed +sl_status_t sli_usbd_hid_os_post_input(uint8_t class_nbr) +{ + if (tx_event_flags_set(&input_eventflags_handle[class_nbr], EVENT_FLAG_COMPLETE, TX_OR) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// usbd_hid_os_timer_task() +// OS - dependent shell task to process periodic HID input reports. +// **@param +// p_arg: Pointer to task initialization argument. +// @note(1) +// Assumes tick rate frequency is greater than or equal to 250 Hz. +// Otherwise, timer task scheduling rate will NOT be correct. +// @note(2) +// Timer task MUST delay without failure. +// (a)Failure to delay timer task will prevent some HID report task(s) operation(s) from functioning correctly. +// Thus, timer task is assumed to be successfully delayed since NO error handling *could be performed to counteract +// failure. +static void usbd_hid_os_timer_task(uint32_t p_arg) +{ + uint32_t dly_tick; + (void)p_arg; + + // Delay task at 4 ms rate (see Note #1). + dly_tick = usbd_hid_os_ms_to_ticks(4); + + while (true) + { + tx_thread_sleep(dly_tick); + sli_usbd_hid_report_timer_task_handler(); + } +} + +// Converts milliseconds to kernel ticks. +static uint32_t usbd_hid_os_ms_to_ticks(uint32_t milliseconds) +{ + return TX_TICKS_PER_MILLISEC(milliseconds); +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c new file mode 100644 index 0000000000..5027ecd015 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c @@ -0,0 +1,364 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include +#include + +TX_THREAD task_handle; +uint32_t usbdCoreThreadStack[SL_USBD_TASK_STACK_SIZE / sizeof(uint32_t)]; +uint8_t message_queue_storage[sizeof(sli_usbd_core_event_t) * SL_USBD_CORE_EVENT_BUS_NBR]; + +// // parameters for task +// static osThreadId_t task_handle; +// static const osThreadAttr_t task_attr = { +// .name = "USBD Thread", +// .attr_bits = 0, +// .stack_mem = NULL, +// .stack_size = (uint32_t)SL_USBD_TASK_STACK_SIZE, +// .cb_mem = NULL, +// .cb_size = 0, +// .priority = (osPriority_t)SL_USBD_TASK_PRIORITY +// }; + +// parameters for message queue +// static osMessageQueueId_t message_queue_handle; +// static const osMessageQueueAttr_t message_queue_attr = +// {.name = "USBD Queue", .attr_bits = 0, .cb_mem = NULL, .cb_size = 0, .mq_mem = NULL, .mq_size = 0}; + +static TX_QUEUE message_queue_handle; + +// parameters for event flags +// static osEventFlagsId_t eventflags_handle[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; +// static osEventFlagsAttr_t eventflags_attr[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; + +static TX_EVENT_FLAGS_GROUP eventflags_handle[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; + +#define EVENT_FLAG_COMPLETE 0x1 // signal posted +#define EVENT_FLAG_ABORT 0x2 // signal aborted + +// parameters for mutex +// static osMutexId_t mutex_handle[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; +// static osMutexAttr_t mutex_attr[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; + +static TX_MUTEX mutex_handle[SL_USBD_OPEN_ENDPOINTS_QUANTITY]; + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL FUNCTION PROTOTYPES + ******************************************************************************************************** + *******************************************************************************************************/ + +static void usbd_core_os_task_main(uint32_t p_arg); + +static uint32_t usbd_core_os_ms_to_ticks(uint32_t milliseconds); + +/******************************************************************************************************** + ******************************************************************************************************** + * INTERNAL FUNCTIONS + ******************************************************************************************************** + *******************************************************************************************************/ + +/******************************************************************************************************* + * Create task and queue for task to pend on + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_create_task(void) +{ + uint16_t status; + + status = tx_queue_create( + &message_queue_handle, + "USBD Queue", + sizeof(sli_usbd_core_event_t), + message_queue_storage, + sizeof(message_queue_storage)); + + // message_queue_handle = + // osMessageQueueNew(SL_USBD_CORE_EVENT_BUS_NBR, sizeof(sli_usbd_core_event_t), &message_queue_attr); + + if (status != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + // Create USB device Core thread + status = tx_thread_create( + &task_handle, + "USBD Core Thread", + usbd_core_os_task_main, + 0, + usbdCoreThreadStack, + SL_USBD_TASK_STACK_SIZE, + SL_USBD_TASK_PRIORITY, + SL_USBD_TASK_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Create an OS signal + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_create_endpoint_signal(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + // eventflags_attr[endpoint].name = "USBD events"; + // eventflags_attr[endpoint].attr_bits = 0; + // eventflags_attr[endpoint].cb_mem = NULL; + // eventflags_attr[endpoint].cb_size = 0; + + // eventflags_handle[endpoint] = osEventFlagsNew(&eventflags_attr[endpoint]); + + if (tx_event_flags_create(&eventflags_handle[endpoint], "USBD events") != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Delete an OS signal + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_delete_endpoint_signal(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_event_flags_delete(&eventflags_handle[endpoint]) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Wait for a signal to become available + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_pend_endpoint_signal(uint8_t endpoint, uint16_t timeout_ms) +{ + uint32_t ticks; + uint32_t status; + uint32_t actual_events; + + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (timeout_ms == 0) + { + ticks = TX_WAIT_FOREVER; + } + else + { + ticks = usbd_core_os_ms_to_ticks(timeout_ms); + } + + status = tx_event_flags_get( + &eventflags_handle[endpoint], + EVENT_FLAG_COMPLETE | EVENT_FLAG_ABORT, + TX_OR_CLEAR, + &actual_events, + ticks); + + if (status == TX_NO_EVENTS) + { + return SL_STATUS_TIMEOUT; + } + + if (status != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + if ((actual_events & EVENT_FLAG_ABORT) == EVENT_FLAG_ABORT) + { + return SL_STATUS_ABORT; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Abort any wait operation on signal + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_abort_endpoint_signal(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_event_flags_set(&eventflags_handle[endpoint], EVENT_FLAG_ABORT, TX_OR) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Make a signal available + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_post_endpoint_signal(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_event_flags_set(&eventflags_handle[endpoint], EVENT_FLAG_COMPLETE, TX_OR) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Create an OS resource to use as an endpoint lock + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_create_endpoint_lock(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_mutex_create(&mutex_handle[endpoint], "USBD mutex", TX_NO_INHERIT) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Delete the OS resource used as an endpoint lock + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_delete_endpoint_lock(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_mutex_delete(&mutex_handle[endpoint]) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Wait for an endpoint to become available and acquire its lock + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_acquire_endpoint_lock(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_mutex_get(&mutex_handle[endpoint], TX_WAIT_FOREVER) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Release an endpoint lock + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_release_endpoint_lock(uint8_t endpoint) +{ + if (endpoint >= SL_USBD_OPEN_ENDPOINTS_QUANTITY) + { + return SL_STATUS_FAIL; + } + + if (tx_mutex_put(&mutex_handle[endpoint]) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Wait until a core event is ready + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_get_core_event(void *p_event) +{ + if (tx_queue_receive(&message_queue_handle, p_event, TX_WAIT_FOREVER) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************* + * Queues core event + *******************************************************************************************************/ +sl_status_t sli_usbd_core_os_put_core_event(void *p_event) +{ + if (tx_queue_send(&message_queue_handle, p_event, TX_NO_WAIT) != TX_SUCCESS) + { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// usbd_core_os_task_main() +// OS-dependent shell task to process USB core events. +// @param p_arg: Pointer to task initialization argument +static void usbd_core_os_task_main(uint32_t p_arg) +{ + (void)p_arg; + + while (true) + { + sli_usbd_core_task_handler(); + } +} + +// usbd_core_os_ms_to_ticks() +// Converts milliseconds to kernel ticks +// @param milliseconds: milliseconds to convert to ticks +// @return Number of ticks +static uint32_t usbd_core_os_ms_to_ticks(uint32_t milliseconds) +{ + return TX_TICKS_PER_MILLISEC(milliseconds); +} diff --git a/targets/AzureRTOS/SiliconLabs/_include/sli_usbd_class_hid_azurertos.h b/targets/AzureRTOS/SiliconLabs/_include/sli_usbd_class_hid_azurertos.h new file mode 100644 index 0000000000..caf93d1396 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/sli_usbd_class_hid_azurertos.h @@ -0,0 +1,196 @@ +/***************************************************************************//** + * @file + * @brief USB Device - USB Hid Class Operating System Layer + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. + * The software is governed by the sections of the MSLA applicable to Micrium + * Software. + * + ******************************************************************************/ + +/******************************************************************************************************** + ******************************************************************************************************** + * MODULE + ******************************************************************************************************** + *******************************************************************************************************/ + +#ifndef SLI_USBD_CLASS_HID_OS_H +#define SLI_USBD_CLASS_HID_OS_H + +/******************************************************************************************************** + ******************************************************************************************************** + * INCLUDE FILES + ******************************************************************************************************** + *******************************************************************************************************/ + +#include + +#include "sl_usbd_core.h" + +/******************************************************************************************************** + ******************************************************************************************************** + * FUNCTION PROTOTYPES + ******************************************************************************************************** + *******************************************************************************************************/ + +/****************************************************************************************************//** + * sli_usbd_hid_os_init() + * + * @brief Initialize HID OS interface. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_init(void); + +/****************************************************************************************************//** + * sli_usbd_hid_os_lock_input() + * + * @brief Lock class input report. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_lock_input(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_unlock_input() + * + * @brief Unlock class input report. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_unlock_input(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_pend_input() + * + * @brief Wait for input report data transfer to complete. + * + * @param class_nbr Class instance number. + * + * @param timeout_ms Signal wait timeout in milliseconds. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_pend_input(uint8_t class_nbr, + uint16_t timeout_ms); + +/****************************************************************************************************//** + * sli_usbd_hid_os_pend_abort_input() + * + * @brief Abort any operation on input report. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_pend_abort_input(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_post_input() + * + * @brief Signal that input report data transfer has completed. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_post_input(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_lock_output() + * + * @brief Lock class output report. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_lock_output(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_unlock_output() + * + * @brief Unlock class output report. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_unlock_output(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_pend_abort_output() + * + * @brief Abort class output report. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_pend_abort_output(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_pend_output() + * + * @brief Wait for output report data transfer to complete. + * + * @param class_nbr Class instance number. + * + * @param timeout_ms Signal wait timeout, in milliseconds. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_pend_output(uint8_t class_nbr, + uint16_t timeout_ms); + +/****************************************************************************************************//** + * sli_usbd_hid_os_post_output() + * + * @brief Signal that output report data is available. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_post_output(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_lock_tx() + * + * @brief Lock class transmit. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_lock_tx(uint8_t class_nbr); + +/****************************************************************************************************//** + * sli_usbd_hid_os_unlock_tx() + * + * @brief Unlock class transmit. + * + * @param class_nbr Class instance number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sli_usbd_hid_os_unlock_tx(uint8_t class_nbr); + +/****************************************************************************************************//** + ******************************************************************************************************** + * MODULE END + ******************************************************************************************************** + *******************************************************************************************************/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 1ace91bd3f..6bd49b400a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -30,5 +30,6 @@ // #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSD_OPTION@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ #define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ +#define GECKO_FEATURE_USBD_HID @GECKO_FEATURE_USBD_HID_OPTION@ #endif // TARGET_PLATFORM_H From d8a0290ab2c92c31fef5ae5fb90f612581898487 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 17 Aug 2022 14:23:50 +0100 Subject: [PATCH 094/572] Fix inclusion of Azure RTOS user config file - Now define is set at GCC series define. - Remove setting CMake var from all targets, move it up at general CMake file. --- CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake | 3 ++- CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake | 7 +++++-- CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake | 6 ++++-- CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake | 4 +++- CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake | 3 ++- CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake | 4 +++- CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake | 4 +++- CMake/binutils.AzureRTOS.cmake | 2 -- targets/AzureRTOS/CMakeLists.txt | 1 + targets/AzureRTOS/Maxim/MAX78000_FTHR/CMakeLists.txt | 1 - targets/AzureRTOS/MicroBit/MICRO_BIT_2/CMakeLists.txt | 1 - targets/AzureRTOS/RaspberryPi/RPI_PICO/CMakeLists.txt | 1 - targets/AzureRTOS/ST/ORGPAL_PALTHREE/CMakeLists.txt | 5 ++--- targets/AzureRTOS/ST/ST_B_L475E_IOT01A/CMakeLists.txt | 5 ++--- targets/AzureRTOS/_common/include/targetHAL.h | 2 -- 15 files changed, 27 insertions(+), 22 deletions(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index 9ea33706db..a08f1f7d36 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -34,7 +34,8 @@ macro(nf_set_compile_options) # enable: # - FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=FALSE) + # - user TX file + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=FALSE -DUSE_FPU=FALSE -DTX_INCLUDE_USER_DEFINE_FILE ) if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") target_compile_definitions(${NFSCO_TARGET} PUBLIC -DDEBUG_EFM=1) diff --git a/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake b/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake index bb1ec47f9d..e3e2ff894d 100644 --- a/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_MAX78000_GCC_options.cmake @@ -27,8 +27,11 @@ macro(nf_set_compile_options) # can't include -Wundef because of MAXIM SDK target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mfpu=fpv4-sp-d16 -mfloat-abi=soft -Wa,-mimplicit-it=thumb -Wall -Wextra -Werror -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) - # this series has FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DTARGET=MAX78000 -DTARGET_REV=0x4131 -DFTHR_RevA ) + # enable: + # - FPU + # - user TX file + # - MAXIM target and revision + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DTARGET=MAX78000 -DTARGET_REV=0x4131 -DFTHR_RevA -DTX_INCLUDE_USER_DEFINE_FILE) endmacro() diff --git a/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake b/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake index 3376589d61..4a742f8348 100644 --- a/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_MICROBIT_GCC_options.cmake @@ -29,8 +29,10 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) - # this series has FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE) + # enable: + # - FPU + # - user TX file + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DTX_INCLUDE_USER_DEFINE_FILE ) endmacro() diff --git a/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake b/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake index 68fa72f417..e4e14b32d6 100644 --- a/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_RP2040_GCC_options.cmake @@ -28,7 +28,9 @@ macro(nf_set_compile_options) target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m0plus -mtune=cortex-m0plus -nostdlib -Wall -Wextra -Werror -Wundef -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -mno-long-calls -fno-exceptions -fcheck-new ) # this series doesn't have FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DUSE_FPU=FALSE) + # enable: + # - user TX file + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DUSE_FPU=FALSE -DTX_INCLUDE_USER_DEFINE_FILE ) endmacro() diff --git a/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake b/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake index ff338f48fc..0046e52ac1 100644 --- a/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_SILABS_GG_S1_GCC_options.cmake @@ -33,7 +33,8 @@ macro(nf_set_compile_options) # enable: # - FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX) + # - user TX file + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX -DTX_INCLUDE_USER_DEFINE_FILE ) endmacro() diff --git a/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake b/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake index 944d24cc04..cf2c745e17 100644 --- a/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_STM32F7xx_GCC_options.cmake @@ -34,7 +34,9 @@ macro(nf_set_compile_options) # enable: # - FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32F7XX) + # - user TX file + # - STM series + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32F7XX -DTX_INCLUDE_USER_DEFINE_FILE ) endmacro() diff --git a/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake b/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake index ff338f48fc..a2130f236c 100644 --- a/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_STM32L4xx_GCC_options.cmake @@ -33,7 +33,9 @@ macro(nf_set_compile_options) # enable: # - FPU - target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX) + # - user TX file + # - STM series + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DPLATFORM_ARM -DCORTEX_USE_FPU=TRUE -DUSE_FPU=TRUE -DSTM32L4XX -DTX_INCLUDE_USER_DEFINE_FILE ) endmacro() diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index efa5595fdd..6fdc580c26 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -256,7 +256,6 @@ macro(nf_add_platform_dependencies target) ${AZRTOS_INCLUDES} EXTRA_COMPILE_DEFINITIONS - -DTX_INCLUDE_USER_DEFINE_FILE -DNX_INCLUDE_USER_DEFINE_FILE ) @@ -276,7 +275,6 @@ macro(nf_add_platform_dependencies target) ${${TARGET_STM32_CUBE_PACKAGE}_CubePackage_INCLUDE_DIRS} EXTRA_COMPILE_DEFINITIONS - -DTX_INCLUDE_USER_DEFINE_FILE -DNX_INCLUDE_USER_DEFINE_FILE -DUSE_HAL_DRIVER -D${STM32_DRIVER_TARGET_DEVICE} diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index 9bee764449..6499e7add2 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -441,6 +441,7 @@ else() endif() set(TARGET_BASE_LOCATION_BINARY ${CMAKE_CURRENT_BINARY_DIR}/${TARGET_VENDOR}/${TARGET_BOARD}) +set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") ############################## # AzureRTOS common directories diff --git a/targets/AzureRTOS/Maxim/MAX78000_FTHR/CMakeLists.txt b/targets/AzureRTOS/Maxim/MAX78000_FTHR/CMakeLists.txt index 7a5036af01..abd31e93e6 100644 --- a/targets/AzureRTOS/Maxim/MAX78000_FTHR/CMakeLists.txt +++ b/targets/AzureRTOS/Maxim/MAX78000_FTHR/CMakeLists.txt @@ -14,7 +14,6 @@ set(THREADX_TOOLCHAIN "gnu") set(MCPU_FLAGS "-mthumb -mcpu=cortex-m4") set(VFP_FLAGS "") set(SPEC_FLAGS "--specs=nosys.specs") -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/tx_user.h) add_subdirectory(${azure_rtos_SOURCE_DIR} AzureSource) diff --git a/targets/AzureRTOS/MicroBit/MICRO_BIT_2/CMakeLists.txt b/targets/AzureRTOS/MicroBit/MICRO_BIT_2/CMakeLists.txt index 79500cf496..e37febd8a0 100644 --- a/targets/AzureRTOS/MicroBit/MICRO_BIT_2/CMakeLists.txt +++ b/targets/AzureRTOS/MicroBit/MICRO_BIT_2/CMakeLists.txt @@ -12,7 +12,6 @@ ENABLE_LANGUAGE(ASM) # Azure RTOS settings and inclusion of build system set(THREADX_ARCH "cortex_m4") set(THREADX_TOOLCHAIN "gnu") -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/tx_user.h) add_subdirectory(${CMAKE_BINARY_DIR}/AzureRTOS_Source AzureSource) # add packages diff --git a/targets/AzureRTOS/RaspberryPi/RPI_PICO/CMakeLists.txt b/targets/AzureRTOS/RaspberryPi/RPI_PICO/CMakeLists.txt index a2f3244a18..3dd8afa354 100644 --- a/targets/AzureRTOS/RaspberryPi/RPI_PICO/CMakeLists.txt +++ b/targets/AzureRTOS/RaspberryPi/RPI_PICO/CMakeLists.txt @@ -18,7 +18,6 @@ set(THREADX_TOOLCHAIN "gnu") set(MCPU_FLAGS "-mthumb -mcpu=cortex-m0") set(VFP_FLAGS "") set(SPEC_FLAGS "--specs=nosys.specs") -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/tx_user.h) add_subdirectory(${azure_rtos_SOURCE_DIR} AzureSource) # add packages diff --git a/targets/AzureRTOS/ST/ORGPAL_PALTHREE/CMakeLists.txt b/targets/AzureRTOS/ST/ORGPAL_PALTHREE/CMakeLists.txt index 55b4de5dd2..6c58964d37 100644 --- a/targets/AzureRTOS/ST/ORGPAL_PALTHREE/CMakeLists.txt +++ b/targets/AzureRTOS/ST/ORGPAL_PALTHREE/CMakeLists.txt @@ -14,9 +14,8 @@ include(AzureRTOS_${TARGET_SERIES}_GCC_options) # endif() # Azure RTOS settings and inclusion of build system -set(THREADX_ARCH "cortex_m7" ) -set(THREADX_TOOLCHAIN "gnu" ) -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") +set(THREADX_ARCH "cortex_m7") +set(THREADX_TOOLCHAIN "gnu") # set(UX_USER_FILE ${TARGET_BASE_LOCATION}/target_ux_user.h CACHE STRING "Enable UX user configuration") set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") diff --git a/targets/AzureRTOS/ST/ST_B_L475E_IOT01A/CMakeLists.txt b/targets/AzureRTOS/ST/ST_B_L475E_IOT01A/CMakeLists.txt index bd081c5859..2d4ee1719f 100644 --- a/targets/AzureRTOS/ST/ST_B_L475E_IOT01A/CMakeLists.txt +++ b/targets/AzureRTOS/ST/ST_B_L475E_IOT01A/CMakeLists.txt @@ -9,9 +9,8 @@ include(binutils.AzureRTOS) include(AzureRTOS_${TARGET_SERIES}_GCC_options) # Azure RTOS settings and inclusion of build system -set(THREADX_ARCH "cortex_m4" ) -set(THREADX_TOOLCHAIN "gnu" ) -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") +set(THREADX_ARCH "cortex_m4") +set(THREADX_TOOLCHAIN "gnu") set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") diff --git a/targets/AzureRTOS/_common/include/targetHAL.h b/targets/AzureRTOS/_common/include/targetHAL.h index b1cfaf28a1..b7f6b797d7 100644 --- a/targets/AzureRTOS/_common/include/targetHAL.h +++ b/targets/AzureRTOS/_common/include/targetHAL.h @@ -6,8 +6,6 @@ #ifndef _TARGET_HAL_H_ #define _TARGET_HAL_H_ -#include - #include #include From d94ad6197c07a24e5d8561bfbead2b222adf1459 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 17 Aug 2022 14:24:37 +0100 Subject: [PATCH 095/572] Revert inclusion of USBx and Azure RTOS config file --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 5e16a92bcd..cce1f8ebdc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -7,16 +7,15 @@ include(AzureRTOS_${TARGET_SERIES}_GCC_options) # Azure RTOS settings and inclusion of build system set(THREADX_ARCH "cortex_m4" ) set(THREADX_TOOLCHAIN "gnu" ) -set(TX_USER_FILE ${TARGET_BASE_LOCATION}/target_tx_user.h CACHE STRING "Enable TX user configuration") # set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") # set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) -add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) -add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) -add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) nf_setup_target_build( HAS_NANOBOOTER From b74ad61fe5e167a3c8041c7cf91992396b1474c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 23 Aug 2022 00:48:33 +0100 Subject: [PATCH 096/572] Update Gecko SDK to 4.1.1 --- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 664aa6866f..264eef38a9 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -43,7 +43,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.1.0") + set(GECKO_SDK_VERSION "v4.1.1") endif() if(NO_GECKO_SDK_SOURCE) From 0ad6f756ac862cb9f9120529f6947b8e732afd48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 02:08:50 +0100 Subject: [PATCH 097/572] Remove processing of targetplatform template in platform CLR --- targets/AzureRTOS/Maxim/_nanoCLR/CMakeLists.txt | 4 ---- targets/AzureRTOS/MicroBit/_nanoCLR/CMakeLists.txt | 4 ---- targets/AzureRTOS/Nordic/_nanoCLR/CMakeLists.txt | 4 ---- targets/AzureRTOS/RaspberryPi/_nanoCLR/CMakeLists.txt | 4 ---- targets/AzureRTOS/ST/_nanoCLR/CMakeLists.txt | 4 ---- 5 files changed, 20 deletions(-) diff --git a/targets/AzureRTOS/Maxim/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/Maxim/_nanoCLR/CMakeLists.txt index f432a73d8e..cdecf911e2 100644 --- a/targets/AzureRTOS/Maxim/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/Maxim/_nanoCLR/CMakeLists.txt @@ -3,10 +3,6 @@ # See LICENSE file in the project root for full license information. # -# add header file with common target definitions -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) - # append target Azure RTOS nanoCLR source files list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp) diff --git a/targets/AzureRTOS/MicroBit/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/MicroBit/_nanoCLR/CMakeLists.txt index 988cd8a92a..3f3e6725b9 100644 --- a/targets/AzureRTOS/MicroBit/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/MicroBit/_nanoCLR/CMakeLists.txt @@ -3,10 +3,6 @@ # See LICENSE file in the project root for full license information. # -# add header file with common target definitions -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) - # # append target Azure RTOS nanoCLR source files # list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) # list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c) diff --git a/targets/AzureRTOS/Nordic/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/Nordic/_nanoCLR/CMakeLists.txt index 988cd8a92a..3f3e6725b9 100644 --- a/targets/AzureRTOS/Nordic/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/Nordic/_nanoCLR/CMakeLists.txt @@ -3,10 +3,6 @@ # See LICENSE file in the project root for full license information. # -# add header file with common target definitions -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) - # # append target Azure RTOS nanoCLR source files # list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) # list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c) diff --git a/targets/AzureRTOS/RaspberryPi/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/RaspberryPi/_nanoCLR/CMakeLists.txt index 988cd8a92a..3f3e6725b9 100644 --- a/targets/AzureRTOS/RaspberryPi/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/RaspberryPi/_nanoCLR/CMakeLists.txt @@ -3,10 +3,6 @@ # See LICENSE file in the project root for full license information. # -# add header file with common target definitions -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) - # # append target Azure RTOS nanoCLR source files # list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) # list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c) diff --git a/targets/AzureRTOS/ST/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/ST/_nanoCLR/CMakeLists.txt index ae8fd07bb6..eb8981c659 100644 --- a/targets/AzureRTOS/ST/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/ST/_nanoCLR/CMakeLists.txt @@ -3,10 +3,6 @@ # See LICENSE file in the project root for full license information. # -# add header file with common target definitions -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) - # append target Azure RTOS nanoCLR source files list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c) From 78b11f58ca7e8480fafa34988350c57902cd4334 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 02:09:21 +0100 Subject: [PATCH 098/572] Remove processing of targetplatform template in platform CLR --- targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt index ae8fd07bb6..eb8981c659 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt @@ -3,10 +3,6 @@ # See LICENSE file in the project root for full license information. # -# add header file with common target definitions -configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_platform.h @ONLY) - # append target Azure RTOS nanoCLR source files list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c) From f2d931779fbfebaf4a233839c097e080b53cf2ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 02:12:29 +0100 Subject: [PATCH 099/572] Enable undefined warning for Azure RTOS GG11 series - Add pragmas where required. - Add compile flags to several Gecko SDK source files to allow undefined names. --- .../AzureRTOS_EFM32GG11_GCC_options.cmake | 3 +-- CMake/Modules/FindGecko_SDK.cmake | 7 +++++++ .../autogen/sl_usbd_configuration_instances.c | 16 ++++++++++++--- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 6 +++--- .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 6 +++--- .../sl_iostream_init_usart_instances.c | 3 +++ .../_common/autogen/sl_usbd_init.c | 20 +++++++++++++++---- .../_common/sl_usbd_core_azuretos.c | 20 +++++++++++++++++++ 8 files changed, 66 insertions(+), 15 deletions(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index a08f1f7d36..82eb618feb 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -29,8 +29,7 @@ macro(nf_set_compile_options) # include any extra options coming from any extra args? # disabling -Wshadow for now as it's causing issues with TX_INTERRUPT_SAVE_AREA - # disabling -Wundef for now as this is causing issues in Gecko SDK - target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO_EXTRA_COMPILE_OPTIONS} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -mabi=aapcs -Wall -Wextra -Werror -Wundef -Wimplicit-fallthrough -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) # enable: # - FPU diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 456e80096a..c881ab2a00 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -197,6 +197,13 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endforeach() + # unset this warning as error required for this source file + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_core.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_core_ep.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_init.c PROPERTIES COMPILE_FLAGS -Wno-undef) + list(REMOVE_DUPLICATES Gecko_SDK_INCLUDE_DIRS) else() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c index 3ff6c727c9..7427de8c50 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c @@ -7,15 +7,25 @@ //**************************************************************************** // Includes. -#include "sl_status.h" -#include "sl_usbd_core.h" +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif /* template headers */ #include "sl_usbd_configuration_instances.h" /* include config file for the instances */ -#include "sl_usbd_config0_config.h" +#include //**************************************************************************** diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index b1babc469d..555775c88a 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -3,15 +3,15 @@ // See LICENSE file in the project root for full license information. // +#include +#include + #include #include #include #include #include -#include -#include - #include #include diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 678c9e4479..3dc72635ed 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -3,6 +3,9 @@ // See LICENSE file in the project root for full license information. // +#include +#include + #include #include #include @@ -10,9 +13,6 @@ #include #include -#include -#include - #include #include diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index ce3f84e0ae..cf1c75e27b 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -12,6 +12,9 @@ #include "sl_iostream_usart_vcom_config.h" #include +// need to define this here to avoid compiler warning (error) +#define usartHwFlowControlNone 0 + //////////////////////////////////////////////////////////////// // Baudrate for the serial port // // Override default setting from board if build option is set // diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index a482c424dd..b865c378a4 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -1,20 +1,32 @@ //**************************************************************************** // Includes. -#include "sl_status.h" - +#include -#include "sl_usbd_core.h" +#include "sl_status.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif +#include +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif +#if GECKO_FEATURE_USBD_HID == TRUE #include "sl_usbd_class_hid.h" +#endif - +#if HAL_WP_USE_USB_CDC == TRUE +#include "sl_usbd_class_cdc.h" +#include "sl_usbd_class_cdc_acm.h" +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c index 5027ecd015..18989438c7 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c @@ -13,12 +13,32 @@ #include +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + #include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + #include +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + #include #include +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + TX_THREAD task_handle; uint32_t usbdCoreThreadStack[SL_USBD_TASK_STACK_SIZE / sizeof(uint32_t)]; uint8_t message_queue_storage[sizeof(sli_usbd_core_event_t) * SL_USBD_CORE_EVENT_BUS_NBR]; From c83b3d9edb6dc3c3dc56641919e0d6bf411d87c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 02:14:10 +0100 Subject: [PATCH 100/572] Add USB CDC to GG11 - Add config files. - Add new build options to set if WP uses USART or USB CDC. - Update build system accordingly. - Increase booter storage block. --- CMake/Modules/FindGecko_SDK.cmake | 44 ++++- CMakeUserPresets.TEMPLATE.json | 2 + targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 17 ++ .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 4 +- .../autogen/sl_usbd_class_cdc_acm_instances.c | 165 ++++++++++++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 36 ++++ .../common/Device_BlockStorage-DEBUG.c | 6 +- .../config/sl_usbd_class_acm0_config.h | 53 ++++++ .../config/sl_usbd_device_config.h | 12 +- .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 4 +- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 12 ++ .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 2 +- .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 15 +- .../SiliconLabs/SL_STK3701A/target_common.c | 20 +-- .../SiliconLabs/_common/CMakeLists.txt | 5 + .../_common/WireProtocol_HAL_Interface.c | 52 +++++- .../WireProtocol_ReceiverThread_Platform.c | 66 +++++++ .../_common/autogen/sl_component_catalog.h | 29 +++ .../_common/autogen/sl_event_handler.c | 9 + .../_common/autogen/sl_usbd_init.c | 30 +--- .../SiliconLabs/_common/usb_cdc_acm_app.c | 97 ++++++++++ .../SiliconLabs/_nanoCLR/target_platform.h.in | 6 +- .../_common/WireProtocol_ReceiverThread.c | 3 +- 23 files changed, 627 insertions(+), 62 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index c881ab2a00..ffd027ab68 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -37,12 +37,15 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdr list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) -if(GECKO_FEATURE_USBD_HID) +if(GECKO_FEATURE_USBD_HID OR + HAL_WP_USE_USB_CDC) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/src) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/util/silicon_labs/silabs_core/memory_manager) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common/include) + endif() # general files @@ -62,9 +65,9 @@ set(gecko_sdk_srcs em_ldma.c em_gpio.c em_i2c.c - em_lcd.c - em_leuart.c - em_lesense.c + # em_lcd.c + # em_leuart.c + # em_lesense.c em_msc.c em_prs.c em_rmu.c @@ -99,9 +102,6 @@ set(gecko_sdk_srcs sl_udelay.c sl_udelay_armv6m_gcc.S sl_uartdrv_init.c - sl_iostream_usart.c - sl_iostream_uart.c - sl_iostream.c sl_device_init_clocks.c sl_event_handler.c @@ -109,8 +109,6 @@ set(gecko_sdk_srcs sl_i2cspm_init.c # candidate for replacement with RTOS friendly version sl_i2cspm.c - sl_iostream_handles.c - sl_iostream_init_usart_instances.c sl_string.c # nanoFramework implementations @@ -144,6 +142,33 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endif() + if(HAL_WP_USE_SERIAL) + + list(APPEND gecko_sdk_srcs sl_iostream_usart.c) + list(APPEND gecko_sdk_srcs sl_iostream_uart.c) + list(APPEND gecko_sdk_srcs sl_iostream.c) + list(APPEND gecko_sdk_srcs sl_iostream_handles.c) + list(APPEND gecko_sdk_srcs sl_iostream_init_usart_instances.c) + + + endif() + + if(HAL_WP_USE_USB_CDC) + + list(APPEND gecko_sdk_srcs sl_usbd_class_cdc_acm_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_cdc_acm.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_cdc.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_init.c) + list(APPEND gecko_sdk_srcs sl_malloc.c) + + endif() + foreach(src_file ${gecko_sdk_srcs}) set(gecko_sdk_src_file src_file-NOTFOUND) @@ -202,6 +227,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_core_ep.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_init.c PROPERTIES COMPILE_FLAGS -Wno-undef) list(REMOVE_DUPLICATES Gecko_SDK_INCLUDE_DIRS) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 6980db4071..393e639792 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -166,6 +166,8 @@ "value": "SL_STK3701A" }, "TARGET_SERIAL_BAUDRATE": "115200", + "GECKO_FEATURE_USBD_HID": "OFF", + "HAL_WP_USE_USB_CDC": "ON", "NF_INTEROP_ASSEMBLIES": null } }, diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 264eef38a9..265cc0d8e3 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -10,6 +10,23 @@ set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) option(GECKO_FEATURE_USBD_HID "option to use Gecko SDK HID class") +################################################################# +# Options for Wire Protocol channel +option(HAL_WP_USE_SERIAL "option to use serial port (UART) to route Wire Protocol") +option(HAL_WP_USE_USB_CDC "option to use USB CDC to route Wire Protocol") + +if(HAL_WP_USE_SERIAL) + message(STATUS "Wire Protocol will use serial port (UART).") + set(HAL_WP_USE_SERIAL_OPTION TRUE CACHE INTERNAL "set HAL_WP_USE_SERIAL") + set(HAL_WP_USE_USB_CDC_OPTION FALSE CACHE INTERNAL "set HAL_WP_USE_USB_CDC") +elseif(HAL_WP_USE_USB_CDC) + message(STATUS "Wire Protocol will use USB CDC.") + set(HAL_WP_USE_USB_CDC_OPTION TRUE CACHE INTERNAL "set HAL_WP_USE_USB_CDC") + set(HAL_WP_USE_SERIAL_OPTION FALSE CACHE INTERNAL "set HAL_WP_USE_SERIAL") +else() + message(FATAL_ERROR "\n\nERROR: need to choose a channel for Wire Protocol. One of the build options HAL_WP_USE_SERIAL_OPTION or HAL_WP_USE_USB_CDC_OPTION have to be 'ON'.") +endif() + ProcessGSDKPackage() if(GECKO_FEATURE_USBD_HID) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index cce1f8ebdc..baa3eb7149 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -65,13 +65,13 @@ if(SRECORD_TOOL_AVAILABLE) nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - B000 + 12000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) else() nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - B000 + 12000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) endif() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..6e311890b9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,165 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..8fa8f62373 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,36 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c index 87e972d6fc..71c9310708 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -10,10 +10,10 @@ const BlockRange BlockRange1[] = { // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 10}, + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 17}, - // 0000B000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 11, 237}, + // 00012000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 18, 237}, // 000EE000 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h index ab4e1b65b3..4a3d86766f 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h @@ -12,14 +12,12 @@ // USB Device Configuration // Device Vendor ID -// Default: 0xFFFE -// Device vendor ID. -#define SL_USBD_DEVICE_VENDOR_ID 0xFFFE +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 // Device Product ID -// Default: 0x1234 -// Device product ID. -#define SL_USBD_DEVICE_PRODUCT_ID 0x1234 +// Device product ID. PID assigned to .NET nanoFramework +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAD // Device Release Number // Default: 0x0100 @@ -34,7 +32,7 @@ // Device Product Name // Default: "Product" // Device product string. -#define SL_USBD_DEVICE_PRODUCT_STRING "Product" +#define SL_USBD_DEVICE_PRODUCT_STRING "nanodevice" // Device Serial Number // Default: "1234567890ABCDEF" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index f6eaa9df4f..74c3541c99 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x0000B000, len = 0 /* space reserved for application deployment */ + flash0 (rx) : org = 0x00000000, len = 72k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00012000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index 555775c88a..e208520885 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -17,6 +17,11 @@ #include // #include +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -159,6 +164,13 @@ void tx_application_define(void *first_unused_memory) } } +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + // report successfull nanoBooter execution ReportSuccessfullNanoBooter(); } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 686af9b153..bbd167197f 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,7 +32,7 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x0000B000, len = 2M - 48k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash0 (rx) : org = 0x00012000, len = 2M - 72k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ deployment (rx) : org = 0x000EE000, len = 904k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 3dc72635ed..d1862d40c7 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -22,6 +22,9 @@ extern void usb_device_hid_app_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_hid_mouse0_init(void); extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -163,13 +166,23 @@ void tx_application_define(void *first_unused_memory) } } -#if GECKO_FEATURE_USBD_HID == TRUE +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE + // can't call USBD init twice sli_usbd_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE sli_usbd_configuration_config0_init(); sli_usbd_hid_mouse0_init(); usb_device_hid_app_init(); #endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c index fcca09213e..c2100dc5c5 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_common.c @@ -6,23 +6,21 @@ #include #include "target_board.h" -#include "target_common.h" +#include #include -HAL_SYSTEM_CONFIG HalSystemConfig = -{ - { true }, // HAL_DRIVER_CONFIG_HEADER Header; +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; - 1, //ConvertCOM_DebugHandle(1), - 0,//ConvertCOM_DebugHandle(0), + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), 921600, - 0, // STDIO = COM2 or COM1 + 0, // STDIO = COM2 or COM1 - { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, - { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } -}; + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; -HAL_TARGET_CONFIGURATION g_TargetConfiguration; +HAL_TARGET_CONFIGURATION g_TargetConfiguration; // this target can use J-Link for updates inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index 8e6ae8d6bd..089e772bdc 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -17,6 +17,11 @@ if(NF_FEATURE_HAS_CONFIG_BLOCK) list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp) endif() +if(HAL_WP_USE_USB_CDC) + list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_cdc_acm_app.c) + list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread_Platform.c) +endif() + # if(NF_TRACE_TO_STDIO) # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_GenericPort_stdio.c) # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${TARGET_BASE_LOCATION}/target_stdio_config.c) diff --git a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c index 9d43fa1a25..48229d589a 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c +++ b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c @@ -3,6 +3,8 @@ // See LICENSE file in the project root for full license information. // +#include + #include #include #include @@ -10,8 +12,26 @@ #include #include +#if HAL_WP_USE_SERIAL == TRUE #include #include +#elif HAL_WP_USE_USB_CDC == TRUE + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include "sl_usbd_core.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_cdc.h" +#include "sl_usbd_class_cdc_acm.h" +#include "sl_usbd_class_cdc_acm_instances.h" +#endif #if defined(TRACE_MASK) && (TRACE_MASK & TRACE_VERBOSE) != 0 // used WP_Message_Process() and methods it calls to avoid flooding TRACE @@ -22,25 +42,32 @@ void WP_ReceiveBytes(uint8_t **ptr, uint32_t *size) { // save for later comparison uint32_t requestedSize = *size; - size_t bytesRead; + uint32_t bytesRead; sl_status_t requestResult; // check for requests with 0 size if (*size) { +#if HAL_WP_USE_SERIAL == TRUE // blocking receive as SL API does not support non-blocking requestResult = sl_iostream_read(sl_iostream_vcom_handle, *ptr, requestedSize, &bytesRead); +#elif HAL_WP_USE_USB_CDC == TRUE + requestResult = sl_usbd_cdc_acm_read(sl_usbd_cdc_acm_acm0_number, *ptr, requestedSize, 200, &bytesRead); +#endif // Warning: Including TRACE_VERBOSE will NOT output the following TRACE on every loop of the statemachine to // avoid flooding the trace. TRACE_LIMIT(TRACE_VERBOSE, 100, "RXMSG: Expecting %d bytes, received %d.\n", requestedSize, read); +#if HAL_WP_USE_SERIAL == TRUE if (requestResult == SL_STATUS_EMPTY) { // hang here for a bit tx_thread_sleep(10); } - else if (requestResult == SL_STATUS_OK) + else +#endif + if (requestResult == SL_STATUS_OK) { // update pointer and size *ptr += bytesRead; @@ -53,11 +80,23 @@ void WP_ReceiveBytes(uint8_t **ptr, uint32_t *size) uint8_t WP_TransmitMessage(WP_Message *message) { + uint32_t dummy = 0; + TRACE_WP_HEADER(WP_TXMSG, message); +#if HAL_WP_USE_SERIAL == TRUE // non-blocking transmit if (sl_iostream_write(sl_iostream_vcom_handle, (uint8_t *)&message->m_header, sizeof(message->m_header)) != SL_STATUS_OK) +#elif HAL_WP_USE_USB_CDC == TRUE + if (sl_usbd_cdc_acm_write( + sl_usbd_cdc_acm_acm0_number, + (uint8_t *)&message->m_header, + sizeof(message->m_header), + 20, + &dummy) != SL_STATUS_OK) +#endif + { return false; } @@ -65,8 +104,17 @@ uint8_t WP_TransmitMessage(WP_Message *message) // if there is anything on the payload send it to the output stream if (message->m_header.m_size && message->m_payload) { +#if HAL_WP_USE_SERIAL == TRUE // non-blocking transmit if (sl_iostream_write(sl_iostream_vcom_handle, message->m_payload, message->m_header.m_size) != SL_STATUS_OK) +#elif HAL_WP_USE_USB_CDC == TRUE + if (sl_usbd_cdc_acm_write( + sl_usbd_cdc_acm_acm0_number, + message->m_payload, + message->m_header.m_size, + 200, + &dummy) != SL_STATUS_OK) +#endif { return false; } diff --git a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c new file mode 100644 index 0000000000..d791da3739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c @@ -0,0 +1,66 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include +#include + +#include + +#define TASK_DELAY_MS 250u + +__attribute__((noreturn)) void ReceiverThread_entry(uint32_t parameter) +{ + (void)parameter; + sl_status_t status = SL_STATUS_OK; + bool conn = false; + + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + tx_thread_sleep(50); + + WP_Message_PrepareReception(); + + // loop until thread receives a request to terminate + while (1) + { + // Wait until device is in configured state + status = sl_usbd_cdc_acm_is_enabled(sl_usbd_cdc_acm_acm0_number, &conn); + _ASSERTE(status == SL_STATUS_OK); + + // while ((conn != true) || ((line_state & SL_USBD_CDC_ACM_CTRL_DTR) == 0)) + while ((conn != true)) + { + // Delay Task + tx_thread_sleep(xDelay); + + status = sl_usbd_cdc_acm_is_enabled(sl_usbd_cdc_acm_acm0_number, &conn); + _ASSERTE(status == SL_STATUS_OK); + } + + WP_Message_Process(); + + // pass control to the OS + tx_thread_sleep(TX_TICKS_PER_MILLISEC(10)); + } + + // this function never returns +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h index e03724e450..bf0b2bd150 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h @@ -11,8 +11,14 @@ #define SL_CATALOG_SIMPLE_LED_PRESENT #define SL_CATALOG_SIMPLE_LED_LED0_PRESENT #define SL_CATALOG_SLEEPTIMER_PRESENT + +#if HAL_WP_USE_SERIAL == TRUE + #define SL_CATALOG_IOSTREAM_UART_COMMON_PRESENT #define SL_CATALOG_IOSTREAM_USART_PRESENT + +#endif + // TODO // #define SL_CATALOG_KERNEL_PRESENT @@ -26,4 +32,27 @@ #endif +#if HAL_WP_USE_USB_CDC == TRUE + +#ifndef SL_CATALOG_USB_DEVICE_PRESENT +#define SL_CATALOG_USB_DEVICE_PRESENT +#endif + +#define SL_CATALOG_USB_DEVICE_CDC_PRESENT +#define SL_CATALOG_USB_DEVICE_CDC_ACM_PRESENT + +#ifndef SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#define SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_CORE_PRESENT +#define SL_CATALOG_USB_DEVICE_CORE_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_DRIVER_PRESENT +#define SL_CATALOG_USB_DEVICE_DRIVER_PRESENT +#endif + +#endif + #endif // SL_COMPONENT_CATALOG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c index 867e03e34f..e9ae9cc710 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c @@ -49,7 +49,11 @@ void sl_kernel_start(void) void sl_driver_init(void) { sl_i2cspm_init_instances(); + +#if HAL_WP_USE_SERIAL == TRUE sl_uartdrv_init_instances(); +#endif + sl_driver_init_target(); } @@ -57,7 +61,10 @@ void sl_service_init(void) { sl_board_configure_vcom(); sl_sleeptimer_init(); + +#if HAL_WP_USE_SERIAL == TRUE sl_iostream_init_instances(); +#endif } void sl_stack_init(void) @@ -87,7 +94,9 @@ void sl_internal_app_process_action(void) void sl_iostream_init_instances(void) { +#if HAL_WP_USE_SERIAL == TRUE sl_iostream_usart_init_instances(); +#endif } // provided as weak so it can be replaced at target level diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index b865c378a4..2158c3b279 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -16,9 +16,6 @@ #pragma GCC diagnostic pop #endif - - - #if GECKO_FEATURE_USBD_HID == TRUE #include "sl_usbd_class_hid.h" #endif @@ -28,11 +25,6 @@ #include "sl_usbd_class_cdc_acm.h" #endif - - - - - //**************************************************************************** // Global functions. @@ -40,20 +32,14 @@ void sli_usbd_init(void) { - sl_usbd_core_init(); - - - - - - - - sl_usbd_hid_init(); - - - - - + sl_usbd_core_init(); +#if GECKO_FEATURE_USBD_HID == TRUE + sl_usbd_hid_init(); +#endif +#if HAL_WP_USE_USB_CDC == TRUE + sl_usbd_cdc_init(); + sl_usbd_cdc_acm_init(); +#endif } diff --git a/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c b/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c new file mode 100644 index 0000000000..a1d3153910 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c @@ -0,0 +1,97 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_cdc.h" +#include "sl_usbd_class_cdc_acm.h" + +#include "sl_usbd_class_cdc_acm_instances.h" + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 24u + +// sl_usbd_on_bus_event() +// @brief USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// sl_usbd_on_config_event() +// @brief USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// Initialize application. +void usb_device_cdc_acm_app_init(void) +{ + // need to configure the CDC with the proper WP settings + sl_usbd_cdc_acm_line_coding_t codingBaudRate; + codingBaudRate.baudrate = 921600; + codingBaudRate.data_bits = 8; + codingBaudRate.parity = SL_USBD_CDC_ACM_PARITY_NONE; + codingBaudRate.stop_bits = SL_USBD_CDC_ACM_STOP_BIT_1; + + sl_usbd_cdc_acm_set_line_coding(sl_usbd_cdc_acm_acm0_number, &codingBaudRate); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 6bd49b400a..879ca43c27 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -11,6 +11,8 @@ #ifndef TARGET_PLATFORM_H #define TARGET_PLATFORM_H +#include + #define NANOCLR_GRAPHICS @NANOCLR_GRAPHICS@ #define NF_FEATURE_USE_SPIFFS @NF_FEATURE_USE_SPIFFS_OPTION@ #define HAL_USE_RTC @HAL_USE_RTC_OPTION@ @@ -30,6 +32,8 @@ // #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSD_OPTION@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ #define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ -#define GECKO_FEATURE_USBD_HID @GECKO_FEATURE_USBD_HID_OPTION@ +#define GECKO_FEATURE_USBD_HID @GECKO_FEATURE_USBD_HID_OPTION@ +#define HAL_WP_USE_SERIAL @HAL_WP_USE_SERIAL_OPTION@ +#define HAL_WP_USE_USB_CDC @HAL_WP_USE_USB_CDC_OPTION@ #endif // TARGET_PLATFORM_H diff --git a/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c b/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c index 93b7bde49f..1b97f9dd58 100644 --- a/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c +++ b/targets/AzureRTOS/_common/WireProtocol_ReceiverThread.c @@ -6,7 +6,8 @@ #include #include -__attribute__((noreturn)) void ReceiverThread_entry(uint32_t parameter) +// defined as weak so it can be replaced with platform specific one +__nfweak __attribute__((noreturn)) void ReceiverThread_entry(uint32_t parameter) { (void)parameter; From b32aca3ee0751a0229cd4da414aad6d8af2e0666 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 17:24:36 +0100 Subject: [PATCH 101/572] Add new header to map to specific I2C header --- .../sys_dev_i2c_native_target.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h new file mode 100644 index 0000000000..3c1ec28f52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/sys_dev_i2c_native_target.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// using this to "map" the include file with the standard name +#include "com_sky_nf_dev_i2c_native_target.h" From 1b44ec85ed330ba0333f35ece7467542a2878df7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 17:24:55 +0100 Subject: [PATCH 102/572] Remove unnecessary if defs --- targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index add5dcd9d3..7ee6d6a2c6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -17,12 +17,8 @@ // #if (HAL_USE_CAN == TRUE) // #include // #endif -#if (HAL_USE_I2C == TRUE) #include -#endif -#if (HAL_USE_SPI == TRUE) #include -#endif // #if (HAL_USE_UART == TRUE) // #include // #endif From 0af81137e4ef237c53aa22df88434e5102ddfc44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Aug 2022 17:24:55 +0100 Subject: [PATCH 103/572] Remove unnecessary if defs --- targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index add5dcd9d3..7ee6d6a2c6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -17,12 +17,8 @@ // #if (HAL_USE_CAN == TRUE) // #include // #endif -#if (HAL_USE_I2C == TRUE) #include -#endif -#if (HAL_USE_SPI == TRUE) #include -#endif // #if (HAL_USE_UART == TRUE) // #include // #endif From 872b818a0cf6c9948835cb183936a1bbcc6a3928 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 26 Aug 2022 16:03:51 +0100 Subject: [PATCH 104/572] Fix WP_ReceiveBytes for HAL_WP_USE_SERIAL --- .../SiliconLabs/_common/WireProtocol_HAL_Interface.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c index 48229d589a..e9a6ccb89e 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c +++ b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c @@ -42,9 +42,14 @@ void WP_ReceiveBytes(uint8_t **ptr, uint32_t *size) { // save for later comparison uint32_t requestedSize = *size; - uint32_t bytesRead; sl_status_t requestResult; +#if HAL_WP_USE_SERIAL == TRUE + size_t bytesRead; +#elif HAL_WP_USE_USB_CDC == TRUE + uint32_t bytesRead; +#endif + // check for requests with 0 size if (*size) { @@ -80,7 +85,9 @@ void WP_ReceiveBytes(uint8_t **ptr, uint32_t *size) uint8_t WP_TransmitMessage(WP_Message *message) { +#if HAL_WP_USE_USB_CDC == TRUE uint32_t dummy = 0; +#endif TRACE_WP_HEADER(WP_TXMSG, message); From cb217a7c3fb6987812121f75a7f38eb7c1d64bc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 26 Aug 2022 16:05:19 +0100 Subject: [PATCH 105/572] Add option to use serial for SL_STK3701A --- CMakeUserPresets.TEMPLATE.json | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 393e639792..12977b9ff6 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -150,6 +150,7 @@ "type": "STRING", "value": "${presetName}" }, + "HAL_WP_USE_SERIAL": "ON", "NF_INTEROP_ASSEMBLIES": null } }, From 236a2e1349c6a27beb3ba4ebd651d40346f5bf97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 26 Aug 2022 16:27:56 +0100 Subject: [PATCH 106/572] Fixes for building HID device with Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 2 ++ .../autogen/sl_usbd_class_hid_instances.c | 12 +++++++++++- .../SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c | 13 +++++++++++-- .../_common/sl_usbd_class_hid_azurertos.c | 12 +++++++++++- 4 files changed, 35 insertions(+), 4 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index ffd027ab68..8f8967bdb1 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -227,6 +227,8 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_core_ep.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid_report.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_init.c PROPERTIES COMPILE_FLAGS -Wno-undef) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c index 2e83a4a058..55fd8d93fa 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -8,9 +8,19 @@ // Includes. #include "sl_status.h" -#include "sl_usbd_core.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include #include "sl_usbd_class_hid.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + /* template headers */ #include "sl_usbd_configuration_instances.h" #include "sl_usbd_class_hid_instances.h" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c index 3427756176..bf56fe2ef1 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c @@ -11,10 +11,19 @@ #include #include -#include "sl_usbd_core.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include #include "sl_usbd_class_hid.h" -#include "sl_usbd_class_hid_instances.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include // Task configuration #define TASK_STACK_SIZE 512u diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c index 4db5698b5d..4a48212a9c 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c @@ -12,8 +12,18 @@ #include +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + #include -#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + #include #include From f81035d127aea719e5904c5d0c24b3f640523580 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 29 Aug 2022 08:44:57 +0100 Subject: [PATCH 107/572] Work CI-CD - Add automatic inclusion of Sys.Text on IO.Ports inclusion. --- CMakeLists.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index b58b209614..3e8d813de3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -632,6 +632,13 @@ if(API_System.Net) endif() endif() +# include nanoFramework.System.Text because of IO.Ports +if( API_System.IO.Ports) + + # thi API requires nanoFramework.System.Text + set(API_nanoFramework.System.Text ON CACHE INTERNAL "enable of API_nanoFramework.System.Text") + +endif() ################################################################# # handles Networking support at HAL level From 124da9d5b1e40e7f8c159eb4f3ac22e1808bb90f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 29 Aug 2022 15:04:36 +0100 Subject: [PATCH 108/572] Initial work adding native implementation for nanoFramework.GiantGecko.Adc --- CMake/Modules/FindNF_NativeAssemblies.cmake | 9 + .../FindnanoFramework.GiantGecko.Adc.cmake | 48 ++++++ CMakePresets.json | 1 + CMakeUserPresets.TEMPLATE.json | 1 + .../nano_gg_adc_native.cpp | 55 ++++++ .../nano_gg_adc_native.h | 160 ++++++++++++++++++ ...Framework_GiantGecko_Adc_AdcController.cpp | 34 ++++ 7 files changed, 308 insertions(+) create mode 100644 CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index afdfea9f08..13785b75d2 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -42,6 +42,9 @@ option(API_Hardware.Stm32 "option for Hardware.Stm32") option(API_nanoFramework.TI.EasyLink "option for nanoFramework.TI.EasyLink API") option(API_nanoFramework.Hardware.TI "option for nanoFramework.Hardware.TI API") +# Silabs Giant Gecko only +option(API_nanoFramework.GiantGecko.Adc "option for nanoFramework.GiantGecko.Adc") + ################################################################# # macro to perform individual settings to add an API to the build macro(PerformSettingsForApiEntry apiNamespace) @@ -237,6 +240,12 @@ if(API_nanoFramework.Hardware.TI) PerformSettingsForApiEntry("nanoFramework.Hardware.TI") endif() +# nanoFramework.Hardware.TI +if(API_nanoFramework.GiantGecko.Adc) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.GiantGecko.Adc") +endif() + # nanoFramework.Runtime.Events if(API_nanoFramework.Runtime.Events) ##### API name here (doted name) diff --git a/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake b/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake new file mode 100644 index 0000000000..1fc2aaf8df --- /dev/null +++ b/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake @@ -0,0 +1,48 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.GiantGecko.Adc) + + +# set include directories +list(APPEND nanoFramework.Device.OneWire_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND nanoFramework.Device.OneWire_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) +list(APPEND nanoFramework.GiantGecko.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/nanoFramework.GiantGecko.Adc) + +# source files +set(nanoFramework.GiantGecko.Adc_SRCS + + nano_gg_adc_native.cpp + + + nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp + +) + +foreach(SRC_FILE ${nanoFramework.GiantGecko.Adc_SRCS}) + + set(nanoFramework.GiantGecko.Adc_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(nanoFramework.GiantGecko.Adc_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/nanoFramework.GiantGecko.Adc + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${nanoFramework.GiantGecko.Adc_SRC_FILE}") + endif() + + list(APPEND nanoFramework.GiantGecko.Adc_SOURCES ${nanoFramework.GiantGecko.Adc_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.GiantGecko.Adc DEFAULT_MSG nanoFramework.GiantGecko.Adc_INCLUDE_DIRS nanoFramework.GiantGecko.Adc_SOURCES) diff --git a/CMakePresets.json b/CMakePresets.json index 0396acb0d0..4fec11b28e 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -306,6 +306,7 @@ "API_nanoFramework.ResourceManager": "OFF", "API_nanoFramework.System.Collections": "OFF", "API_nanoFramework.System.Text": "OFF", + "API_nanoFramework.GiantGecko.Adc": "OFF", "API_Windows.Storage": "OFF", "API_nanoFramework.Graphics": "OFF" } diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 12977b9ff6..73a08bc841 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -169,6 +169,7 @@ "TARGET_SERIAL_BAUDRATE": "115200", "GECKO_FEATURE_USBD_HID": "OFF", "HAL_WP_USE_USB_CDC": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", "NF_INTEROP_ASSEMBLIES": null } }, diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp new file mode 100644 index 0000000000..5c5816e487 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -0,0 +1,55 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nano_gg_adc_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::GetSingleConversion___U4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::StartContinuousConversion___BOOLEAN, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = +{ + "nanoFramework.GiantGecko.Adc", + 0xF231CDFB, + method_lookup, + { 1, 0, 0, 0 } +}; + +// clang-format on diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h new file mode 100644 index 0000000000..0661431443 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -0,0 +1,160 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef NANO_GG_ADC_NATIVE_H +#define NANO_GG_ADC_NATIVE_H + +#include +#include +#include +#include + +typedef enum __nfpack AquisitionTime +{ + AquisitionTime__1Cyle = 1, + AquisitionTime__2Cyles = 2, + AquisitionTime__3Cyles = 3, + AquisitionTime__4Cyles = 4, + AquisitionTime__8Cyles = 5, + AquisitionTime__16Cyles = 6, + AquisitionTime__32Cyles = 7, + AquisitionTime__64Cyles = 8, + AquisitionTime__128Cyles = 9, + AquisitionTime__256Cyles = 10, +} AquisitionTime; + +typedef enum __nfpack InputOption +{ + InputOption_SingleEnded = 0, + InputOption_Differential = 1, +} InputOption; + +typedef enum __nfpack LowpassFilterMode +{ + LowpassFilterMode_Bypass = 0, + LowpassFilterMode_RcFilter = 1, + LowpassFilterMode_DecouplingCapacitor = 2, +} LowpassFilterMode; + +typedef enum __nfpack OversampleRate +{ + OversampleRate__2Samples = 0, + OversampleRate__4Samples = 1, + OversampleRate__8Samples = 2, + OversampleRate__16Samples = 3, + OversampleRate__32Samples = 4, + OversampleRate__64Samples = 5, + OversampleRate__128Samples = 6, + OversampleRate__256Samples = 7, + OversampleRate__512Samples = 8, + OversampleRate__1024Samples = 9, + OversampleRate__2048Samples = 10, + OversampleRate__4096Samples = 11, +} OversampleRate; + +typedef enum __nfpack PrsSampleTrigger +{ + PrsSampleTrigger_PrsChannel0 = 0, + PrsSampleTrigger_PrsChannel1 = 1, + PrsSampleTrigger_PrsChannel2 = 2, + PrsSampleTrigger_PrsChannel3 = 3, + PrsSampleTrigger_PrsChannel4 = 4, + PrsSampleTrigger_PrsChannel5 = 5, + PrsSampleTrigger_PrsChannel6 = 6, + PrsSampleTrigger_PrsChannel7 = 7, + PrsSampleTrigger_PrsChannel8 = 8, + PrsSampleTrigger_PrsChannel9 = 9, + PrsSampleTrigger_PrsChannel10 = 10, + PrsSampleTrigger_PrsChannel11 = 11, +} PrsSampleTrigger; + +typedef enum __nfpack ReferenceVoltage +{ + ReferenceVoltage_Internal1_25V = 0, + ReferenceVoltage_Internal2_5V = 1, + ReferenceVoltage_BufferedVdd = 2, + ReferenceVoltage_InternalDifferencial_5V = 3, + ReferenceVoltage_SingleEndedExternalPin6 = 4, + ReferenceVoltage_DiffExternalPin6And7 = 5, + ReferenceVoltage_Unbuffered2Vdd = 6, +} ReferenceVoltage; + +typedef enum __nfpack SampleResolution +{ + SampleResolution__12bits = 0, + SampleResolution__8bit = 1, + SampleResolution__6bit = 2, + SampleResolution_Oversampling = 3, +} SampleResolution; + +typedef enum __nfpack SingleSampleInput +{ + SingleSampleInput_Channel0 = 0, + SingleSampleInput_Channel1 = 1, + SingleSampleInput_Channel2 = 2, + SingleSampleInput_Channel3 = 3, + SingleSampleInput_Channel4 = 4, + SingleSampleInput_Channel5 = 5, + SingleSampleInput_Channel6 = 6, + SingleSampleInput_Channel7 = 7, + SingleSampleInput_TemperatureReference = 8, + SingleSampleInput_VddDiv3 = 9, + SingleSampleInput_Vdd = 10, + SingleSampleInput_Vss = 11, + SingleSampleInput_VrefDiv2 = 12, + SingleSampleInput_DacOutput0 = 13, + SingleSampleInput_DacOutput1 = 14, + SingleSampleInput_Atest = 15, + SingleSampleInput_Positive0Negative1 = 16, + SingleSampleInput_Positive2Negative3 = 17, + SingleSampleInput_Positive4Negative5 = 18, + SingleSampleInput_Positive6Negative7 = 19, + SingleSampleInput_Differential0 = 20, +} SingleSampleInput; + +typedef enum __nfpack WarmUpMode +{ + WarmUpMode_Normal = 0, + WarmUpMode_WarmupFastBG = 1, + WarmUpMode_KeepScanRefWarm = 2, + WarmUpMode_KeepAdcWarm = 3, +} WarmUpMode; + +struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AcdInitialization +{ + static const int FIELD___oversampleRate = 1; + static const int FIELD___lowpassFilterMode = 2; + static const int FIELD___warmUpMode = 3; + static const int FIELD___warnupTimeBase = 4; + static const int FIELD___prescale = 5; + static const int FIELD___tailgating = 6; + + //--// +}; + +struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___prsSampleTrigger = 2; + static const int FIELD___aquisitionTime = 3; + static const int FIELD___referenceVoltage = 4; + static const int FIELD___sampleResolution = 5; + static const int FIELD___scanInput = 6; + static const int FIELD___inputOption = 7; + static const int FIELD___prsEnable = 8; + static const int FIELD___acdInitialization = 9; + static const int FIELD__LedfAdjust = 10; + static const int FIELD__ContinuousConversion = 11; + + NANOCLR_NATIVE_DECLARE(GetSingleConversion___U4); + NANOCLR_NATIVE_DECLARE(StartContinuousConversion___BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc; + +#endif // NANO_GG_ADC_NATIVE_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp new file mode 100644 index 0000000000..8b12a007ef --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -0,0 +1,34 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nano_gg_adc_native.h" + + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::GetSingleConversion___U4( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::StartContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} From 5db64209bb403b41a8dd14164d2d21d512b76ea2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 2 Sep 2022 11:13:59 +0100 Subject: [PATCH 109/572] Replace USB mouse with HID --- .../autogen/sl_usbd_class_hid_instances.c | 115 +++++++++--------- .../autogen/sl_usbd_class_hid_instances.h | 22 ++-- ...0_config.h => sl_usbd_class_hid0_config.h} | 34 +++--- .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 5 +- .../SL_STK3701A/nanoCLR/usb_hid_app.c | 20 +-- 5 files changed, 98 insertions(+), 98 deletions(-) rename targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/{sl_usbd_class_mouse0_config.h => sl_usbd_class_hid0_config.h} (81%) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c index 55fd8d93fa..c37150d591 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -27,7 +27,7 @@ /* include config file for the instances */ -#include "sl_usbd_class_mouse0_config.h" +#include //**************************************************************************** @@ -35,38 +35,38 @@ -/* callback prototypes for mouse0 instance */ -void sli_usbd_hid_mouse0_enable(uint8_t class_nbr); +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); -void sli_usbd_hid_mouse0_disable(uint8_t class_nbr); +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); -void sli_usbd_hid_mouse0_get_report_desc(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_mouse0_get_phy_desc(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_mouse0_set_output_report(uint8_t class_nbr, +void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -void sli_usbd_hid_mouse0_get_feature_report(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -void sli_usbd_hid_mouse0_set_feature_report(uint8_t class_nbr, +void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -void sli_usbd_hid_mouse0_get_protocol(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); -void sli_usbd_hid_mouse0_set_protocol(uint8_t class_nbr, +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); @@ -78,11 +78,12 @@ void sli_usbd_hid_mouse0_set_protocol(uint8_t class_nbr, /* variables for mouse0 instance */ -uint8_t sl_usbd_hid_mouse0_number = 0; +uint8_t sl_usbd_hid_hid0_number = 0; -uint8_t sl_usbd_hid_mouse0_default_protocol = 0; +uint8_t sl_usbd_hid_hid0_default_protocol = 0; -static const uint8_t sli_usbd_hid_mouse0_default_desc[] = { + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CA_MOUSE, SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_APPLICATION, @@ -111,16 +112,16 @@ static const uint8_t sli_usbd_hid_mouse0_default_desc[] = { SL_USBD_HID_MAIN_ENDCOLLECTION }; -sl_usbd_hid_callbacks_t sli_usbd_hid_mouse0_callbacks = { - sli_usbd_hid_mouse0_enable, - sli_usbd_hid_mouse0_disable, - sli_usbd_hid_mouse0_get_report_desc, - sli_usbd_hid_mouse0_get_phy_desc, - sli_usbd_hid_mouse0_set_output_report, - sli_usbd_hid_mouse0_get_feature_report, - sli_usbd_hid_mouse0_set_feature_report, - sli_usbd_hid_mouse0_get_protocol, - sli_usbd_hid_mouse0_set_protocol, +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, }; @@ -131,39 +132,39 @@ sl_usbd_hid_callbacks_t sli_usbd_hid_mouse0_callbacks = { /* callback functions for mouse0 instance */ -void sli_usbd_hid_mouse0_enable(uint8_t class_nbr) +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) { (void)&class_nbr; - sl_usbd_hid_mouse0_on_enable_event(); + sl_usbd_hid_hid0_on_enable_event(); return; } -void sli_usbd_hid_mouse0_disable(uint8_t class_nbr) +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) { (void)&class_nbr; - sl_usbd_hid_mouse0_on_disable_event(); + sl_usbd_hid_hid0_on_disable_event(); return; } -void sli_usbd_hid_mouse0_get_report_desc(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { (void)&class_nbr; - *p_report_ptr = sli_usbd_hid_mouse0_default_desc; - *p_report_len = sizeof(sli_usbd_hid_mouse0_default_desc); + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); - sl_usbd_hid_mouse0_on_get_report_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); return; } -void sli_usbd_hid_mouse0_get_phy_desc(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { @@ -172,25 +173,25 @@ void sli_usbd_hid_mouse0_get_phy_desc(uint8_t class_nbr, *p_report_ptr = NULL; *p_report_len = 0; - sl_usbd_hid_mouse0_on_get_phy_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); return; } -void sli_usbd_hid_mouse0_set_output_report(uint8_t class_nbr, +void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) { (void)&class_nbr; - sl_usbd_hid_mouse0_on_set_output_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); return; } -void sli_usbd_hid_mouse0_get_feature_report(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) @@ -199,43 +200,43 @@ void sli_usbd_hid_mouse0_get_feature_report(uint8_t class_nbr, memset(p_report_buf, 0, report_len); - sl_usbd_hid_mouse0_on_get_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); return; } -void sli_usbd_hid_mouse0_set_feature_report(uint8_t class_nbr, +void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) { (void)&class_nbr; - sl_usbd_hid_mouse0_on_set_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); return; } -void sli_usbd_hid_mouse0_get_protocol(uint8_t class_nbr, +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) { (void)&class_nbr; - *p_protocol = sl_usbd_hid_mouse0_default_protocol; + *p_protocol = sl_usbd_hid_hid0_default_protocol; - sl_usbd_hid_mouse0_on_get_protocol_event(p_protocol); + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); return; } -void sli_usbd_hid_mouse0_set_protocol(uint8_t class_nbr, +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) { (void)&class_nbr; - sl_usbd_hid_mouse0_default_protocol = protocol; + sl_usbd_hid_hid0_default_protocol = protocol; - sl_usbd_hid_mouse0_on_set_protocol_event(protocol); + sl_usbd_hid_hid0_on_set_protocol_event(protocol); return; } @@ -246,8 +247,8 @@ void sli_usbd_hid_mouse0_set_protocol(uint8_t class_nbr, -/* initialize mouse0 instance */ -void sli_usbd_hid_mouse0_init() +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() { sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; @@ -264,17 +265,17 @@ void sli_usbd_hid_mouse0_init() char *token = NULL; /* configs to attach the class instance to */ - configs = SL_USBD_HID_MOUSE0_CONFIGURATIONS; + configs = SL_USBD_HID_HID0_CONFIGURATIONS; /* read subclass, protocol, and country codes */ - subclass = SL_USBD_HID_MOUSE0_SUBCLASS; - protocol = SL_USBD_HID_MOUSE0_PROTOCOL; - country = SL_USBD_HID_MOUSE0_COUNTRY_CODE; + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; /* read endpoint parameters */ - interval_in = SL_USBD_HID_MOUSE0_INTERVAL_IN; - interval_out = SL_USBD_HID_MOUSE0_INTERVAL_OUT; - ctrl_rd_en = SL_USBD_HID_MOUSE0_ENABLE_CTRL_RD; + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; /* create HID instance */ sl_usbd_hid_create_instance(subclass, @@ -283,11 +284,11 @@ void sli_usbd_hid_mouse0_init() interval_in, interval_out, ctrl_rd_en, - &sli_usbd_hid_mouse0_callbacks, + &sli_usbd_hid_hid0_callbacks, &class_number); /* store class number globally */ - sl_usbd_hid_mouse0_number = class_number; + sl_usbd_hid_hid0_number = class_number; /* tokenize configs by "," and spaces */ token = strtok(configs, ", "); diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h index 248d23309b..1243386c7e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h @@ -11,33 +11,33 @@ /* class numbers assigned by the USB stack after init */ -extern uint8_t sl_usbd_hid_mouse0_number; +extern uint8_t sl_usbd_hid_hid0_number; /* event handlers for all HID instances */ -__WEAK void sl_usbd_hid_mouse0_on_enable_event(void); -__WEAK void sl_usbd_hid_mouse0_on_disable_event(void); -__WEAK void sl_usbd_hid_mouse0_on_get_report_desc_event(const uint8_t **p_report_ptr, +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); -__WEAK void sl_usbd_hid_mouse0_on_get_phy_desc_event(const uint8_t **p_report_ptr, +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); -__WEAK void sl_usbd_hid_mouse0_on_set_output_report_event(uint8_t report_id, +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_mouse0_on_get_feature_report_event(uint8_t report_id, +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_mouse0_on_set_feature_report_event(uint8_t report_id, +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_mouse0_on_get_protocol_event(uint8_t *p_protocol); -__WEAK void sl_usbd_hid_mouse0_on_set_protocol_event(uint8_t protocol); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); /* init functions for all HID instances */ -void sli_usbd_hid_mouse0_init(void); +void sli_usbd_hid_hid0_init(void); #endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h similarity index 81% rename from targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h rename to targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h index 2df9c9b721..6dde9c8f46 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_mouse0_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h @@ -4,43 +4,43 @@ // See LICENSE file in the project root for full license information. // -#ifndef SL_USBD_HID_MOUSE0_CONFIG_H -#define SL_USBD_HID_MOUSE0_CONFIG_H +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H // <<< Use Configuration Wizard in Context Menu >>> // Class Configuration -// Configuration(s) to add this class instance to +// Configuration(s) to add this class instance to // Default: all // Comma separated list of configuration instances (like inst0, inst1) // that this HID class instance will be attached to. You can // use "all" to attach the class to all configs, or use an empty // string if you do not want to attach the interface to any configuration. -#define SL_USBD_HID_MOUSE0_CONFIGURATIONS "all" +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" // // Type Codes -// Subclass code +// Subclass code // None // Boot // Default: SL_USBD_HID_SUBCLASS_BOOT // This defines the standard USB subclass code for this interface. // For most use cases, you can just select "Boot". -#define SL_USBD_HID_MOUSE0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT -// Protocol code +// Protocol code // None // Keyboard // Mouse // Default: SL_USBD_HID_PROTOCOL_MOUSE // You can choose "Mouse" or "Keyboard" depending on what functionality // this HID class instance will provide. -#define SL_USBD_HID_MOUSE0_PROTOCOL SL_USBD_HID_PROTOCOL_MOUSE +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_MOUSE -// Country code +// Country code // Not supported // Arabic // Belgian @@ -82,13 +82,13 @@ // field helps the host operating system know which layout/language // the keyboard is manufactured for, or which country/localization // setting to use by default. -#define SL_USBD_HID_MOUSE0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US // // Protocol Details -// IN polling interval +// IN polling interval // <1=> 1ms // <2=> 2ms // <4=> 4ms @@ -108,9 +108,9 @@ // Default: 2 // Polling interval for input transfers, in milliseconds. // It must be a power of 2. -#define SL_USBD_HID_MOUSE0_INTERVAL_IN 2 +#define SL_USBD_HID_HID0_INTERVAL_IN 2 -// OUT polling interval +// OUT polling interval // <1=> 1ms // <2=> 2ms // <4=> 4ms @@ -130,14 +130,14 @@ // Default: 2 // Polling interval for input transfers, in milliseconds. // It must be a power of 2. -#define SL_USBD_HID_MOUSE0_INTERVAL_OUT 2 +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 -// Enable Control Read +// Enable Control Read // Default: 1 // Enable read operations through the control transfers. -#define SL_USBD_HID_MOUSE0_ENABLE_CTRL_RD 1 +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 // // <<< end of configuration section >>> -#endif // SL_USBD_HID_MOUSE0_CONFIG_H +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index d1862d40c7..8cb1512bd8 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -20,7 +20,7 @@ extern void usb_device_hid_app_init(void); extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_mouse0_init(void); +extern void sli_usbd_hid_hid0_init(void); extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); @@ -173,8 +173,7 @@ void tx_application_define(void *first_unused_memory) #if GECKO_FEATURE_USBD_HID == TRUE sli_usbd_configuration_config0_init(); - sli_usbd_hid_mouse0_init(); - + sli_usbd_hid_hid0_init(); usb_device_hid_app_init(); #endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c index bf56fe2ef1..89348fa060 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c @@ -85,7 +85,7 @@ void usb_device_hid_app_init(void) &task_handle, "USB HID Mouse task", hid_mouse_task, - (uint32_t)&sl_usbd_hid_mouse0_number, + (uint32_t)&sl_usbd_hid_hid0_number, hidThreadStack, TASK_STACK_SIZE, TASK_PRIO, @@ -196,20 +196,20 @@ void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) } // HID mouse0 instance Enable event. -void sl_usbd_hid_mouse0_on_enable_event(void) +void sl_usbd_hid_hid0_on_enable_event(void) { // Called when the HID device is connected to the USB host and a // RESET transfer succeeded. } // HID mouse0 instance Disable event. -void sl_usbd_hid_mouse0_on_disable_event(void) +void sl_usbd_hid_hid0_on_disable_event(void) { // Called when the HID device is disconnected to the USB host (cable removed). } // Hook function to pass the HID descriptor of the mouse0 instance. -void sl_usbd_hid_mouse0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) { // Called during the HID mouse0 instance initialization so the USB stack // can retrieve its HID descriptor. @@ -219,7 +219,7 @@ void sl_usbd_hid_mouse0_on_get_report_desc_event(const uint8_t **p_report_ptr, u } // Hook function to pass the HID PHY descriptor. -void sl_usbd_hid_mouse0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) { // Called during the HID mouse0 instance initialization so the USB stack // can retrieve the its HID physical descriptor. @@ -232,7 +232,7 @@ void sl_usbd_hid_mouse0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint // @param report_id Report ID. // @param p_report_buf Pointer to report buffer. // @param report_len Length of report, in octets. -void sl_usbd_hid_mouse0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) { // This function is called when host issues a SetReport request. // The application can take action in function of the report content. @@ -247,7 +247,7 @@ void sl_usbd_hid_mouse0_on_set_output_report_event(uint8_t report_id, uint8_t *p // @param p_report_buf Pointer to feature report buffer. // @param report_len Length of report, in octets. // @note (1) Report ID must not be written into the feature report buffer. -void sl_usbd_hid_mouse0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) { // This function is called when host issues a GetReport(feature) request. // The application can provide the report to send by copying it in p_report_buf. @@ -262,7 +262,7 @@ void sl_usbd_hid_mouse0_on_get_feature_report_event(uint8_t report_id, uint8_t * // @param p_report_buf Pointer to feature report buffer. // @param report_len Length of report, in octets. // @note (1) Report ID is not present in the feature report buffer. -void sl_usbd_hid_mouse0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) { // This function is called when host issues a SetReport(Feature) request. // The application can take action in function of the provided report in p_report_buf. @@ -274,7 +274,7 @@ void sl_usbd_hid_mouse0_on_set_feature_report_event(uint8_t report_id, uint8_t * // Retrieve active protocol: BOOT or REPORT protocol. // @param p_protocol Pointer to variable that will receive the protocol type. -void sl_usbd_hid_mouse0_on_get_protocol_event(uint8_t *p_protocol) +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) { // This function is called when host issues a GetProtocol request. // The application should return the current protocol. @@ -284,7 +284,7 @@ void sl_usbd_hid_mouse0_on_get_protocol_event(uint8_t *p_protocol) // Store active protocol: BOOT or REPORT protocol. // @param protocol Protocol. -void sl_usbd_hid_mouse0_on_set_protocol_event(uint8_t protocol) +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) { // This function is called when host issues a SetProtocol request. // The application should apply the new protocol. From f8eea9a1599843605d41d6c9f96db0465f1e8de2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 2 Sep 2022 11:14:20 +0100 Subject: [PATCH 110/572] Fix duplicated call to config0_init --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 8cb1512bd8..11e41ec529 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -169,16 +169,15 @@ void tx_application_define(void *first_unused_memory) #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE // can't call USBD init twice sli_usbd_init(); + sli_usbd_configuration_config0_init(); #endif #if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_configuration_config0_init(); sli_usbd_hid_hid0_init(); usb_device_hid_app_init(); #endif #if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_configuration_config0_init(); sli_usbd_cdc_acm_acm0_init(); usb_device_cdc_acm_app_init(); #endif From 068bf8220ce09cd77436eeb33f5cab6529287147 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 2 Sep 2022 14:06:54 +0100 Subject: [PATCH 111/572] More progress towards replacing USB Mouse with HID --- .../autogen/sl_usbd_class_hid_instances.c | 12 +-- .../config/sl_usbd_class_hid0_config.h | 2 +- .../SL_STK3701A/nanoCLR/usb_hid_app.c | 81 +++++-------------- 3 files changed, 28 insertions(+), 67 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c index c37150d591..f80d11f2c9 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -84,12 +84,12 @@ uint8_t sl_usbd_hid_hid0_default_protocol = 0; static const uint8_t sli_usbd_hid_hid0_default_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CA_MOUSE, - SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_APPLICATION, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CP_POINTER, - SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_PHYSICAL, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_BUTTON, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h index 6dde9c8f46..9e480375d0 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_hid0_config.h @@ -38,7 +38,7 @@ // Default: SL_USBD_HID_PROTOCOL_MOUSE // You can choose "Mouse" or "Keyboard" depending on what functionality // this HID class instance will provide. -#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_MOUSE +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE // Country code // Not supported diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c index 89348fa060..8f926ef311 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c @@ -30,50 +30,16 @@ #define TASK_PRIO 5u #define TASK_DELAY_MS 100u -#define USB_HID_MOUSE_REPORT_LEN 4u +#define USB_HID_REPORT_LEN 4u // FreeRTOS Task handle static TX_THREAD task_handle; uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; -// Current protocol selected by host. -static uint8_t usb_hid_mouse_protocol; - // Mouse report buffer. -__ALIGNED(4) static uint8_t usb_hid_mouse_report_buffer[USB_HID_MOUSE_REPORT_LEN]; - -// HID mouse report -// The report buffer is sent to the host when it requests the report descriptor. The report -// descriptor describes the device itself (axis, quantity of button, scroll wheel, etc) and -// how the data for each element is reported in the report. -static const uint8_t usb_hid_mouse_report_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CA_MOUSE, - SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_APPLICATION, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_CP_POINTER, - SL_USBD_HID_MAIN_COLLECTION + 1, SL_USBD_HID_COLLECTION_PHYSICAL, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_BUTTON, - SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, - SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, - SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; - -static void hid_mouse_task(uint32_t p_arg); +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); // Initialize application. void usb_device_hid_app_init(void) @@ -83,8 +49,8 @@ void usb_device_hid_app_init(void) // Create application task status = tx_thread_create( &task_handle, - "USB HID Mouse task", - hid_mouse_task, + "USB HID task", + hid_task, (uint32_t)&sl_usbd_hid_hid0_number, hidThreadStack, TASK_STACK_SIZE, @@ -96,11 +62,10 @@ void usb_device_hid_app_init(void) _ASSERTE(status == TX_SUCCESS); } -// hid_mouse_task() +// hid_task() // Perform HID writes to host. -// The HID writes simulate the movement of a mouse. // @param p_arg Task argument pointer. Class number in this case. -static void hid_mouse_task(uint32_t p_arg) +static void hid_task(uint32_t p_arg) { uint8_t class_nbr = *(uint8_t *)p_arg; bool x_is_pos = true; @@ -110,8 +75,8 @@ static void hid_mouse_task(uint32_t p_arg) uint32_t xfer_len = 0; const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); - usb_hid_mouse_report_buffer[0u] = 0u; - usb_hid_mouse_report_buffer[1u] = 0u; + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; while (true) { @@ -130,15 +95,15 @@ static void hid_mouse_task(uint32_t p_arg) } // Emulates back and fourth movement. - ((int8_t *)usb_hid_mouse_report_buffer)[2u] = (x_is_pos) ? 50 : -50; - ((int8_t *)usb_hid_mouse_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; x_is_pos = !x_is_pos; y_is_pos = !y_is_pos; // Send report. status = - sl_usbd_hid_write_sync(class_nbr, usb_hid_mouse_report_buffer, USB_HID_MOUSE_REPORT_LEN, 0u, &xfer_len); + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); // Delay Task tx_thread_sleep(xDelay); @@ -213,9 +178,8 @@ void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uin { // Called during the HID mouse0 instance initialization so the USB stack // can retrieve its HID descriptor. - - *p_report_ptr = usb_hid_mouse_report_desc; - *p_report_len = sizeof(usb_hid_mouse_report_desc); + (void)p_report_ptr; + (void)p_report_len; } // Hook function to pass the HID PHY descriptor. @@ -223,9 +187,8 @@ void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16 { // Called during the HID mouse0 instance initialization so the USB stack // can retrieve the its HID physical descriptor. - - *p_report_ptr = NULL; - *p_report_len = 0; + (void)p_report_ptr; + (void)p_report_len; } // Notification of a new set report received on control endpoint. @@ -253,8 +216,8 @@ void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_ // The application can provide the report to send by copying it in p_report_buf. (void)report_id; - - memset(p_report_buf, 0, report_len); + (void)p_report_buf; + (void)report_len; } // Set HID feature report corresponding to report ID. @@ -278,8 +241,7 @@ void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) { // This function is called when host issues a GetProtocol request. // The application should return the current protocol. - - *p_protocol = usb_hid_mouse_protocol; + (void)p_protocol; } // Store active protocol: BOOT or REPORT protocol. @@ -288,6 +250,5 @@ void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) { // This function is called when host issues a SetProtocol request. // The application should apply the new protocol. - - usb_hid_mouse_protocol = protocol; + (void)protocol; } From 11914a0c0a8456edbf0a41eb33851c18bf446f45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 2 Sep 2022 17:40:55 +0100 Subject: [PATCH 112/572] Add support for WinUSB devices **WIP*** --- CMake/Modules/FindGecko_SDK.cmake | 3 + .../autogen/sl_usbd_class_vendor_instances.c | 159 ++++++++++++++++++ .../autogen/sl_usbd_class_vendor_instances.h | 29 ++++ .../config/sl_usbd_class_winusb_config.h | 57 +++++++ .../_common/autogen/sl_usbd_init.c | 2 + 5 files changed, 250 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 8f8967bdb1..92b9988f2c 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -169,6 +169,9 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endif() + list(APPEND gecko_sdk_srcs sl_usbd_class_vendor.c) + + foreach(src_file ${gecko_sdk_srcs}) set(gecko_sdk_src_file src_file-NOTFOUND) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c new file mode 100644 index 0000000000..c9ec9ab105 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -0,0 +1,159 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" + + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_vendor.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_vendor_instances.h" + +/* include config file for the instances */ + +#include "sl_usbd_class_winusb_config.h" + + +//**************************************************************************** +// Function declarations. + + + + +/* callback prototypes for winusb instance */ + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req); + + + + +//**************************************************************************** +// Global variables. + + + + +/* variables for winusb instance */ + +uint8_t sl_usbd_vendor_winusb_number = 0; + +sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, +}; + + + +//**************************************************************************** +// Callback functions. + + + + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_enable_event(); + + return; +} + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_disable_event(); + + return; +} + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + + return; +} + + +//**************************************************************************** +// Global functions. + + + +/* initialize winusb instance */ +void sli_usbd_vendor_winusb_init() +{ + bool intr_en = true; + uint16_t interval = 0; + + uint8_t class_number = 0; + uint8_t config_number = 0; + + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, + interval, + &sli_usbd_vendor_winusb_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } + + + /* next token */ + token = strtok(NULL, ", "); + } +} + diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h new file mode 100644 index 0000000000..1cc98931e6 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h @@ -0,0 +1,29 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_VENDOR_INSTANCES_INIT +#define SL_USBD_CLASS_VENDOR_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_vendor_winusb_number; + + +/* event handlers for all vendor instances */ + +__WEAK void sl_usbd_vendor_winusb_on_enable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_disable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); + + +/* init functions for all vendor instances */ + +void sli_usbd_vendor_winusb_init(void); + + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..4da7f4409b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,57 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index 2158c3b279..0429a8f4f8 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -42,4 +42,6 @@ void sli_usbd_init(void) sl_usbd_cdc_init(); sl_usbd_cdc_acm_init(); #endif + +sl_usbd_vendor_init(); } From 4eca71efe383441b5ac148ca998be8779a14ff04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 7 Sep 2022 15:14:12 +0100 Subject: [PATCH 113/572] Add implementation for 1-Wire for Silabs Azure RTOS --- .../target_nf_dev_onewire_config.cpp | 29 ++ .../target_nf_dev_onewire_config.h | 12 + ...noFramework_Device_OneWire_OneWireHost.cpp | 401 ++++++++++++++++++ .../nf_dev_onewire_target.h | 118 ++++++ 4 files changed, 560 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..6eb0d5a2a4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_dev_onewire_config.h" +#include + +/////////// +// UART0 // +/////////// + +// pin configuration for UART4 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_10 +// GPIO alternate pin function is 8 +UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned(32))) +#endif +uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned(32))) +#endif +uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..840f02a3de --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_STM32_UART_USE_USART0 TRUE +#define GECKO_USE_USART0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp new file mode 100644 index 0000000000..a6ae6ff30b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -0,0 +1,401 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_dev_onewire_target.h" + + +// struct for working threads +static OneWireFindStruct FindStruct; +static bool OneWireOperationResult; +static TaskHandle_t WaitingTask; +static uint8_t LastDiscrepancy; +static uint8_t LastFamilyDiscrepancy; +static uint8_t LastDevice; +static uint8_t SerialNum[8]; + +// Driver state. +static oneWireState DriverState = ONEWIRE_UNINIT; + +// working thread to execute long running 1-Wire operations +static thread_t *OneWireWorkingThread; + + +void IRAM_ATTR oneWireStop() +{ + // stop UART + uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); + + // driver is stopped + DriverState = ONEWIRE_STOP; +} + +HRESULT IRAM_ATTR oneWireInit() +{ + DriverState = ONEWIRE_STOP; + + uart_config_t uart_config = { + .baud_rate = 115200, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, + .rx_flow_ctrl_thresh = 0, + .use_ref_tick = false, + }; + + // get GPIO pins configured for UART assigned to 1-Wire + // need to subtract one to get the correct index of UART in mapped device pins + int txPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, NF_ONEWIRE_ESP32_UART_NUM, Esp32SerialPin_Tx); + int rxPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, NF_ONEWIRE_ESP32_UART_NUM, Esp32SerialPin_Rx); + + // check if TX, RX pins have been previously set + if (txPin == UART_PIN_NO_CHANGE || rxPin == UART_PIN_NO_CHANGE) + { + return CLR_E_PIN_UNAVAILABLE; + } + + // configure GPIO and UART + if (gpio_set_direction(gpio_num_t(txPin), GPIO_MODE_OUTPUT_OD) != ESP_OK) + { + return CLR_E_INVALID_OPERATION; + } + + if (uart_param_config(NF_ONEWIRE_ESP32_UART_NUM, &uart_config) != ESP_OK) + { + return CLR_E_INVALID_OPERATION; + } + + if (uart_set_pin(NF_ONEWIRE_ESP32_UART_NUM, txPin, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE) != ESP_OK) + { + return CLR_E_INVALID_OPERATION; + } + + if (uart_driver_install(NF_ONEWIRE_ESP32_UART_NUM, 256, 256, 0, NULL, ESP_INTR_FLAG_IRAM) != ESP_OK) + { + return CLR_E_INVALID_OPERATION; + } + + // driver need to be deleted on soft reboot + HAL_AddSoftRebootHandler(oneWireStop); + + DriverState = ONEWIRE_READY; + + return S_OK; +} + + +uint8_t oneWireTouchReset(void) +{ + char reset = 0xF0; + uint8_t presence; + + // flush DMA buffer to ensure cache coherency + uart_flush(NF_ONEWIRE_ESP32_UART_NUM); + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) + uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 9600); + + uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&reset, 1); + uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &presence, 1, 20 / portTICK_RATE_MS); + + // set UART baud rate to 115200bps (normal comm is performed at this baud rate) + uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 115200); + + // check for presence pulse + return (presence != reset); +} + +//////////////////////////////////////// +// struct for working threads +OneWireFindStruct FindStruct; + +// ChibiOS OneWire working thread +static THD_FUNCTION(OneWireFindFirstWorkingThread, arg) +{ + msg_t deviceFound; + + OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; + + deviceFound = oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly); + + // fire event for 1-Wire operarion completed + Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + + chThdExit(deviceFound); +} + +static THD_FUNCTION(OneWireFindNextWorkingThread, arg) +{ + msg_t deviceFound; + + OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; + + deviceFound = oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); + + // fire event for 1-Wire operarion completed + Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + + chThdExit(deviceFound); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchReset___BOOLEAN(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + volatile bool reset = oneWireTouchReset(); + stack.SetResult_Boolean(reset); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchBit___BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + bool value = stack.Arg1().NumericByRefConst().u1 != 0; + + stack.SetResult_Boolean(oneWireTouchBit(value)); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchByte___U1__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t value = (uint8_t)stack.Arg1().NumericByRefConst().u1; + uint8_t result = oneWireTouchByte(value); + stack.SetResult_U1(result); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::WriteByte___U1__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t cmd = (uint8_t)stack.Arg1().NumericByRefConst().u1; + uint8_t result = oneWireWriteByte(cmd); + stack.SetResult_U1(result); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::ReadByte___U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t result = oneWireReadByte(); + stack.SetResult_U1(result); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t *serialNumberPointer; + msg_t oneWireOperationResult = FALSE; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + + // set an infinite timeout to wait forever for the operation to complete + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)-1); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // this is going to be used to check for the right event in case of simultaneous 1-Wire operations + if (stack.m_customState == 1) + { + FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; + FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + + // because the 1-Wire bus is shared, acquire the module + oneWireAcquireModule(); + + // spawn working thread to perform the 1-Wire operations + OneWireWorkingThread = chThdCreateFromHeap( + NULL, + THD_WORKING_AREA_SIZE(256), + "OWWT", + NORMALPRIO, + OneWireFindFirstWorkingThread, + &FindStruct); + + // bump custom state + stack.m_customState = 2; + } + + while (eventResult) + { + if (OneWireWorkingThread->state == CH_STATE_FINAL) + { + // OneWire working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); + } + + if (eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the + // heap, otherwise it won't be returned + oneWireOperationResult = chThdWait(OneWireWorkingThread); + + oneWireReleaseModule(); + + // get the result from the working thread execution + if (oneWireOperationResult) + { + // if a device was found update serialNumber field in managed class + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array *serialNumberField = pThis[FIELD___serialNumber].DereferenceArray(); + + _ASSERTE(serialNumberField->m_numOfElements == 8); + + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + + oneWireSerialNum(serialNumberPointer, TRUE); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // set result + stack.SetResult_Boolean(oneWireOperationResult); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + uint8_t *serialNumberPointer; + msg_t oneWireOperationResult = FALSE; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64 *timeout; + bool eventResult = true; + + // set an infinite timeout to wait forever for the operation to complete + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)-1); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + + // this is going to be used to check for the right event in case of simultaneous 1-Wire operations + if (stack.m_customState == 1) + { + FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; + FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + + // because the 1-Wire bus is shared, acquire the module + oneWireAcquireModule(); + + // spawn working thread to perform the 1-Wire operations + OneWireWorkingThread = chThdCreateFromHeap( + NULL, + THD_WORKING_AREA_SIZE(256), + "OWWT", + NORMALPRIO, + OneWireFindNextWorkingThread, + &FindStruct); + + // bump custom state + stack.m_customState = 2; + } + + while (eventResult) + { + if (OneWireWorkingThread->state == CH_STATE_FINAL) + { + // OneWire working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); + } + + if (eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the + // heap, otherwise it won't be returned + oneWireOperationResult = chThdWait(OneWireWorkingThread); + + oneWireReleaseModule(); + + // get the result from the working thread execution + if (oneWireOperationResult) + { + // update serialNumber field + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array *serialNumberField = pThis[FIELD___serialNumber].DereferenceArray(); + + _ASSERTE(serialNumberField->m_numOfElements == 8); + + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + + oneWireSerialNum(serialNumberPointer, TRUE); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // set result + stack.SetResult_Boolean(oneWireOperationResult); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeDispose___VOID(CLR_RT_StackFrame &stack) +{ + (void)stack; + + NANOCLR_HEADER(); + + oneWireStop(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeInit___VOID(CLR_RT_StackFrame &stack) +{ + (void)stack; + + NANOCLR_HEADER(); + + // startup 1-Wire driver + oneWireStart(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h new file mode 100644 index 0000000000..dbc6185ea9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -0,0 +1,118 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_DEV_ONEWIRE_TARGET_H_ +#define _NF_DEV_ONEWIRE_TARGET_H_ + +#include +#include +#include + +// set missing defines +#if defined(USART0) +#ifndef GECKO_USE_USART0 +#define GECKO_USE_USART0 FALSE +#endif +#else +#define GECKO_USE_USART0 FALSE +#endif + +#if defined(USART1) +#ifndef GECKO_USE_USART1 +#define GECKO_USE_USART1 FALSE +#endif +#else +#define GECKO_USE_USART1 FALSE +#endif + +#if defined(USART2) +#ifndef GECKO_USE_USART2 +#define GECKO_USE_USART2 FALSE +#endif +#else +#define GECKO_USE_USART2 FALSE +#endif + +#if defined(USART3) +#ifndef GECKO_USE_USART3 +#define GECKO_USE_USART3 FALSE +#endif +#else +#define GECKO_USE_USART3 FALSE +#endif + +#if defined(USART4) +#ifndef GECKO_USE_USART4 +#define GECKO_USE_USART4 FALSE +#endif +#else +#define GECKO_USE_USART4 FALSE +#endif + +#if defined(USART5) +#ifndef GECKO_USE_USART5 +#define GECKO_USE_USART5 FALSE +#endif +#else +#define GECKO_USE_USART5 FALSE +#endif + +// struct with parameters for 1-Wire working thread +struct OneWireFindStruct +{ + bool DoReset; + bool AlarmOnly; + bool FindFirst; +}; + +// @brief Driver state machine possible states. +typedef enum +{ + // Not initialized. + ONEWIRE_UNINIT, + // Stopped. + ONEWIRE_STOP, + // Ready. + ONEWIRE_READY, + // Generating random number. + ONEWIRE_ACTIVE +} oneWireState; + +// character to send on the UART to mimic 1-Wire bus signals +// 1-Wire write 0 time slot +#define IWIRE_WR0 0x00 +// 1-Wire write 1 time slot +#define IWIRE_WR1 0xFF +// 1-Wire read time slot +#define IWIRE_RD 0xFF + +// ROM commands +// search ROM +#define SEARCH_ROM 0xF0 +// conditional search ROM +#define COND_SEARCH_ROM 0xEC + +#if defined(_USART_ROUTELOC0_MASK) + +// the following macro defines a function that configures the GPIO pins for an Gecko USART peripheral +// it gets called in the oneWire_lld_start function +// this is required because the USART peripherals can use multiple GPIO configuration combinations +#define INIT_ONEWIRE_CONFIG(num, usart_tx_port_location, usart_rx_location) \ + void InitSpiConfig##num(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex) \ + { \ + initSpiData.port = USART##num; \ + initSpiData.portLocationTx = mosi_port_location; \ + initSpiData.portLocationClk = sck_port_location; \ + if (!isHalfDuplex) \ + { \ + initSpiData.portLocationRx = miso_port_location; \ + } \ + } + +#else +#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#endif + +#endif // _NF_DEV_ONEWIRE_TARGET_H_ From 5d6fa9c953d9f984d4ec713382e6f919a3e253a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 7 Sep 2022 18:44:21 +0100 Subject: [PATCH 114/572] Update cmake preset for SL_STK3701A_REVB --- CMakeUserPresets.TEMPLATE.json | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 73a08bc841..1d7babd9ec 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -168,6 +168,7 @@ }, "TARGET_SERIAL_BAUDRATE": "115200", "GECKO_FEATURE_USBD_HID": "OFF", + "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_nanoFramework.GiantGecko.Adc": "ON", "NF_INTEROP_ASSEMBLIES": null From 83ec15e9b3da0cb5303c4fb41521968a1fc46bc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 7 Sep 2022 18:47:16 +0100 Subject: [PATCH 115/572] Fix inclusion of sl_usbd_class_vendor --- CMake/Modules/FindGecko_SDK.cmake | 19 +++++++++++++++--- CMakeUserPresets.TEMPLATE.json | 1 + targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 9 +++++++++ .../autogen/sl_usbd_class_vendor_instances.c | 14 +++++++++++++ .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 7 ++++++- .../_common/autogen/sl_component_catalog.h | 20 +++++++++++++++++++ .../_common/autogen/sl_usbd_init.c | 9 ++++++++- .../SiliconLabs/_nanoCLR/target_platform.h.in | 1 + 8 files changed, 75 insertions(+), 5 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 92b9988f2c..90f0a3fd62 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -38,7 +38,8 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udel list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) if(GECKO_FEATURE_USBD_HID OR - HAL_WP_USE_USB_CDC) + HAL_WP_USE_USB_CDC OR + GECKO_FEATURE_USBD_WINUSB) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/src) @@ -139,7 +140,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_init.c) list(APPEND gecko_sdk_srcs sl_malloc.c) - + endif() if(HAL_WP_USE_SERIAL) @@ -169,8 +170,19 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endif() - list(APPEND gecko_sdk_srcs sl_usbd_class_vendor.c) + if(GECKO_FEATURE_USBD_WINUSB) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_vendor.c) + list(APPEND gecko_sdk_srcs sl_usbd_init.c) + list(APPEND gecko_sdk_srcs sl_malloc.c) + + endif() foreach(src_file ${gecko_sdk_srcs}) @@ -232,6 +244,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid_report.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_init.c PROPERTIES COMPILE_FLAGS -Wno-undef) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 1d7babd9ec..79a7751608 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -168,6 +168,7 @@ }, "TARGET_SERIAL_BAUDRATE": "115200", "GECKO_FEATURE_USBD_HID": "OFF", + "GECKO_FEATURE_USBD_WINUSB": "OFF", "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_nanoFramework.GiantGecko.Adc": "ON", diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 265cc0d8e3..e274b4bb46 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -9,6 +9,7 @@ include(Gecko_SDK) set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) option(GECKO_FEATURE_USBD_HID "option to use Gecko SDK HID class") +option(GECKO_FEATURE_USBD_WINUSB "option to use Gecko SDK USB vendor class for WinUSB") ################################################################# # Options for Wire Protocol channel @@ -37,6 +38,14 @@ else() set(GECKO_FEATURE_USBD_HID_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_HID for USBD HID") endif() +if(GECKO_FEATURE_USBD_WINUSB) + + set(GECKO_FEATURE_USBD_WINUSB_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") + +else() + set(GECKO_FEATURE_USBD_WINUSB_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") +endif() + # check if GECKO_SDK_SOURCE was specified or if it's empty (default is empty) set(NO_GECKO_SDK_SOURCE TRUE) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c index c9ec9ab105..4a5482daad 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -157,3 +157,17 @@ void sli_usbd_vendor_winusb_init() } } +void sl_usbd_vendor_winusb_on_enable_event(void) +{ + +} + +void sl_usbd_vendor_winusb_on_disable_event(void) +{ + +} + +void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) +{ + +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 11e41ec529..152cd22a14 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -166,7 +166,7 @@ void tx_application_define(void *first_unused_memory) } } -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); @@ -177,6 +177,11 @@ void tx_application_define(void *first_unused_memory) usb_device_hid_app_init(); #endif +#if GECKO_FEATURE_USBD_WINUSB == TRUE +// TODO + //usb_device_winusb_app_init(); +#endif + #if HAL_WP_USE_USB_CDC == TRUE sli_usbd_cdc_acm_acm0_init(); usb_device_cdc_acm_app_init(); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h index bf0b2bd150..a0ee173be4 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h @@ -32,6 +32,26 @@ #endif +#if defined(I_AM_NANOCLR) && GECKO_FEATURE_USBD_WINUSB == TRUE + +#ifndef SL_CATALOG_USB_DEVICE_PRESENT +#define SL_CATALOG_USB_DEVICE_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#define SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_CORE_PRESENT +#define SL_CATALOG_USB_DEVICE_CORE_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_DRIVER_PRESENT +#define SL_CATALOG_USB_DEVICE_DRIVER_PRESENT +#endif + +#endif + #if HAL_WP_USE_USB_CDC == TRUE #ifndef SL_CATALOG_USB_DEVICE_PRESENT diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index 0429a8f4f8..4f418ed9cf 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -20,6 +20,10 @@ #include "sl_usbd_class_hid.h" #endif +#if GECKO_FEATURE_USBD_WINUSB == TRUE +#include "sl_usbd_class_vendor.h" +#endif + #if HAL_WP_USE_USB_CDC == TRUE #include "sl_usbd_class_cdc.h" #include "sl_usbd_class_cdc_acm.h" @@ -43,5 +47,8 @@ void sli_usbd_init(void) sl_usbd_cdc_acm_init(); #endif -sl_usbd_vendor_init(); +#if GECKO_FEATURE_USBD_WINUSB == TRUE + sl_usbd_vendor_init(); +#endif + } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 879ca43c27..25339fb6ce 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -33,6 +33,7 @@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ #define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ #define GECKO_FEATURE_USBD_HID @GECKO_FEATURE_USBD_HID_OPTION@ +#define GECKO_FEATURE_USBD_WINUSB @GECKO_FEATURE_USBD_WINUSB_OPTION@ #define HAL_WP_USE_SERIAL @HAL_WP_USE_SERIAL_OPTION@ #define HAL_WP_USE_USB_CDC @HAL_WP_USE_USB_CDC_OPTION@ From fe7db32db1aec21ce1b693fb3bc5327df2134daa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 12 Sep 2022 13:03:16 +0100 Subject: [PATCH 116/572] Rework inclusion of several init functions - Now allows target to override default platform implementation. --- CMake/Modules/FindGecko_SDK.cmake | 14 ++++++-- .../_common/autogen/sl_device_init_clocks.c | 28 ---------------- .../autogen/sl_device_init_clocks_default.c | 30 +++++++++++++++++ ...t_handler.c => sl_event_handler_default.c} | 32 +++++++++++++------ 4 files changed, 64 insertions(+), 40 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c rename targets/AzureRTOS/SiliconLabs/_common/autogen/{sl_event_handler.c => sl_event_handler_default.c} (59%) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 90f0a3fd62..b64da64c3f 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -9,12 +9,18 @@ include(FetchContent) FetchContent_GetProperties(gecko_sdk) # set include directories + +# these are locations for SDK config headers +# the locations for the target need to come before the generic ones +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) +# now the locations for the generic one (to be used in case there are none for the target) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/config) + +# now all the rest list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/AzureRTOS) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) @@ -87,7 +93,9 @@ set(gecko_sdk_srcs sl_device_init_dcdc_s1.c sl_device_init_emu_s1.c sl_device_init_hfxo_s1.c + sl_device_init_hfrco.c sl_device_init_lfxo_s1.c + sl_device_init_lfrco.c sl_device_init_nvic.c sl_power_manager.c sl_power_manager_hal_s0_s1.c @@ -104,7 +112,9 @@ set(gecko_sdk_srcs sl_udelay_armv6m_gcc.S sl_uartdrv_init.c + sl_device_init_clocks_default.c sl_device_init_clocks.c + sl_event_handler_default.c sl_event_handler.c sl_board_default_init_stub.c sl_i2cspm_init.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c deleted file mode 100644 index 30080ed43b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Copyright 2019 Silicon Laboratories Inc. www.silabs.com -// See LICENSE file in the project root for full license information. -// - -#include "sl_device_init_clocks.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - - CMU_ClockEnable(cmuClock_HFLE, true); - CMU_ClockEnable(cmuClock_HFPER, true); - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); - CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); -#if defined(_CMU_LFCCLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); -#endif -#if defined(_CMU_LFECLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); -#endif - - return SL_STATUS_OK; -} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c new file mode 100644 index 0000000000..536bf44098 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c @@ -0,0 +1,30 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" +#include + +// implemented as weak function to allow overriding at platform level +__nfweak sl_status_t sl_device_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c similarity index 59% rename from targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c index e9ae9cc710..e33e721d06 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c @@ -12,6 +12,8 @@ #include "sl_device_init_dcdc.h" #include "sl_device_init_hfxo.h" #include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" #include "sl_device_init_clocks.h" #include "sl_device_init_emu.h" #include "sl_board_control.h" @@ -26,7 +28,8 @@ #include #include -void sl_platform_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_platform_init(void) { CHIP_Init(); sl_device_init_nvic(); @@ -40,13 +43,15 @@ void sl_platform_init(void) sl_power_manager_init(); } -void sl_kernel_start(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_kernel_start(void) { // Enter the ThreadX kernel. tx_kernel_enter(); } -void sl_driver_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_driver_init(void) { sl_i2cspm_init_instances(); @@ -57,7 +62,8 @@ void sl_driver_init(void) sl_driver_init_target(); } -void sl_service_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_service_init(void) { sl_board_configure_vcom(); sl_sleeptimer_init(); @@ -67,20 +73,24 @@ void sl_service_init(void) #endif } -void sl_stack_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_stack_init(void) { sl_stack_init_target(); } -void sl_internal_app_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_internal_app_init(void) { } -void sl_platform_process_action(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_platform_process_action(void) { } -void sl_service_process_action(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_service_process_action(void) { } @@ -88,11 +98,13 @@ void sl_stack_process_action(void) { } -void sl_internal_app_process_action(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_internal_app_process_action(void) { } -void sl_iostream_init_instances(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_iostream_init_instances(void) { #if HAL_WP_USE_SERIAL == TRUE sl_iostream_usart_init_instances(); From b44b4f5b8768a0462762341867af726887dce670 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 12 Sep 2022 16:49:08 +0100 Subject: [PATCH 117/572] Initial work on SKY_EEVB_PROTO1 board --- .../SKY_EEVB_PROTO1/CMakeLists.txt | 76 ++++ .../SiliconLabs/SKY_EEVB_PROTO1/README.md | 27 ++ .../autogen/sl_device_init_clocks.c | 28 ++ .../autogen/sl_event_handler.c | 45 +++ .../SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c | 91 +++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../autogen/sl_usbd_class_cdc_acm_instances.c | 165 +++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 36 ++ .../autogen/sl_usbd_class_hid_instances.c | 310 ++++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 43 +++ .../autogen/sl_usbd_class_vendor_instances.c | 173 +++++++++ .../autogen/sl_usbd_class_vendor_instances.h | 29 ++ .../autogen/sl_usbd_configuration_instances.c | 76 ++++ .../autogen/sl_usbd_configuration_instances.h | 20 + .../SKY_EEVB_PROTO1/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 123 +++++++ .../common/Device_BlockStorage.c | 124 +++++++ .../common/tx_initialize_low_level.S | 239 ++++++++++++ .../SKY_EEVB_PROTO1/config/pin_config.h | 259 +++++++++++++ .../config/sl_board_control_config.h | 112 ++++++ .../config/sl_device_init_hfrco_config.h | 27 ++ .../config/sl_device_init_hfxo_config.h | 39 ++ .../config/sl_device_init_lfrco_config.h | 34 ++ .../config/sl_device_init_lfxo_config.h | 37 ++ .../config/sl_iostream_usart_vcom_config.h | 112 ++++++ .../SKY_EEVB_PROTO1/config/sl_memory_config.h | 13 + .../config/sl_uartdrv_usart_vcom_config.h | 85 +++++ .../config/sl_usbd_class_acm0_config.h | 53 +++ .../config/sl_usbd_class_hid0_config.h | 143 ++++++++ .../config/sl_usbd_class_winusb_config.h | 57 +++ .../config/sl_usbd_config0_config.h | 51 +++ .../config/sl_usbd_core_config.h | 196 ++++++++++ .../config/sl_usbd_device_config.h | 60 +++ .../SKY_EEVB_PROTO1/config/uartdrv_config.h | 114 ++++++ .../SiliconLabs/SKY_EEVB_PROTO1/launch.json | 83 +++++ .../SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ++++++++++++ .../SKY_EEVB_PROTO1/nanoBooter/main.c | 222 +++++++++++ .../nanoBooter/target_board.h.in | 18 + .../SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt | 15 + .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 249 +++++++++++++ .../SKY_EEVB_PROTO1/nanoCLR/main.c | 200 ++++++++++ .../SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp | 8 + .../SKY_EEVB_PROTO1/nanoCLR/target_board.h.in | 18 + .../SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c | 254 +++++++++++++ .../SKY_EEVB_PROTO1/target_BlockStorage.c | 19 + .../SKY_EEVB_PROTO1/target_BlockStorage.h | 12 + .../target_com_sky_nf_dev_i2c_config.cpp | 22 ++ .../target_com_sky_nf_dev_i2c_config.h | 3 + .../target_com_sky_nf_dev_spi_config.cpp | 34 ++ .../target_com_sky_nf_dev_spi_config.h | 7 + .../SKY_EEVB_PROTO1/target_common.c | 27 ++ .../SKY_EEVB_PROTO1/target_common.h.in | 52 +++ .../target_nf_dev_onewire_config.cpp | 29 ++ .../target_nf_dev_onewire_config.h | 12 + .../SKY_EEVB_PROTO1/target_stdio_config.c | 15 + .../SKY_EEVB_PROTO1/target_stdio_config.h | 11 + .../target_system_device_adc_config.cpp | 20 + .../target_system_device_adc_config.h | 6 + .../target_system_device_pwm_config.cpp | 17 + .../SKY_EEVB_PROTO1/target_tx_user.h | 206 +++++++++++ .../SKY_EEVB_PROTO1/target_ux_user.h | 345 ++++++++++++++++++ 62 files changed, 5191 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/tx_initialize_low_level.S create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_hid0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_ux_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt new file mode 100644 index 0000000000..090d3d7cf6 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 12000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 12000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md new file mode 100644 index 0000000000..2ec34ed193 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md @@ -0,0 +1,27 @@ +# Silabs EFM32 Giant Gecko GG11 Starter Kit (revC hardware) + +This target is for revC hardware. This can be easily identified by the presence of a USB-C connector for JLink connection. +Opposed to revB which carries a micro USB connector instead. For revB user the firmware for target `SL_STK3701A_REVB`. + +## Setting the VCP baud rate to 921600 + +https://community.silabs.com/s/article/kba-bt-1208-using-virtual-com-port-vcom-x + +:warning: +Only possible for revC hardware. + +## ADC channels + +ADC has enabled the following channels: +0 - reading from PE11 (pin 6 on the expansion header) +1 - internal temperature +2 - VCC + +:warning: +Vref is 2.5V for all channels, except for VCC which is 5V. + +## PWM + +PWM has enabled the following GPIOs: +0 - PC1 (pin 15 on the expansion header) +1 - PI1 (through hole connector at bottom side) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..91f07c2383 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO); + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c new file mode 100644 index 0000000000..93eb4ef0a5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c @@ -0,0 +1,45 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + sl_device_init_hfxo(); + sl_device_init_hfrco(); + sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..6e311890b9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,165 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..8fa8f62373 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,36 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..f80d11f2c9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,310 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + + +//**************************************************************************** +// Function declarations. + + + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, + uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, + uint8_t protocol); + + +//**************************************************************************** +// Global variables. + + + + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, + SL_USBD_HID_MAIN_ENDCOLLECTION +}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + + + +//**************************************************************************** +// Callback functions. + + + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, + const uint8_t **p_report_ptr, + uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + + +void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, + uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, + uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + + +//**************************************************************************** +// Global functions. + + + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance(subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + + /* next token */ + token = strtok(NULL, ", "); + } +} + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..1243386c7e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,43 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, + uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, + uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c new file mode 100644 index 0000000000..4a5482daad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c @@ -0,0 +1,173 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" + + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_vendor.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_vendor_instances.h" + +/* include config file for the instances */ + +#include "sl_usbd_class_winusb_config.h" + + +//**************************************************************************** +// Function declarations. + + + + +/* callback prototypes for winusb instance */ + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req); + + + + +//**************************************************************************** +// Global variables. + + + + +/* variables for winusb instance */ + +uint8_t sl_usbd_vendor_winusb_number = 0; + +sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, +}; + + + +//**************************************************************************** +// Callback functions. + + + + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_enable_event(); + + return; +} + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_disable_event(); + + return; +} + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + + return; +} + + +//**************************************************************************** +// Global functions. + + + +/* initialize winusb instance */ +void sli_usbd_vendor_winusb_init() +{ + bool intr_en = true; + uint16_t interval = 0; + + uint8_t class_number = 0; + uint8_t config_number = 0; + + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, + interval, + &sli_usbd_vendor_winusb_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } + + + /* next token */ + token = strtok(NULL, ", "); + } +} + +void sl_usbd_vendor_winusb_on_enable_event(void) +{ + +} + +void sl_usbd_vendor_winusb_on_disable_event(void) +{ + +} + +void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) +{ + +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h new file mode 100644 index 0000000000..1cc98931e6 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h @@ -0,0 +1,29 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_VENDOR_INSTANCES_INIT +#define SL_USBD_CLASS_VENDOR_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_vendor_winusb_number; + + +/* event handlers for all vendor instances */ + +__WEAK void sl_usbd_vendor_winusb_on_enable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_disable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); + + +/* init functions for all vendor instances */ + +void sli_usbd_vendor_winusb_init(void); + + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..7427de8c50 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,76 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + + +//**************************************************************************** +// Global functions. + + + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..500dd508c3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..71c9310708 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 17}, + + // 00012000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 18, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c new file mode 100644 index 0000000000..dcf2d55e8c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c @@ -0,0 +1,124 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 08000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 10}, + + // 0800B000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 11, 158}, + + // 0804F800 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 080FF800 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + // STM32L4 flash requires 64bits width programming + (BlockRegionAttribute_ProgramWidthIs64bits), + + // start address for block region + 0x08000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x800, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..ec442f5030 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfxo_config.h @@ -0,0 +1,39 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..4da7f4409b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,57 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..24ec038d55 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h @@ -0,0 +1,196 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..4a3d86766f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to .NET nanoFramework +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAD + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Default: "Silicon Labs" +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Silicon Labs" + +// Device Product Name +// Default: "Product" +// Device product string. +#define SL_USBD_DEVICE_PRODUCT_STRING "nanodevice" + +// Device Serial Number +// Default: "1234567890ABCDEF" +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING "1234567890ABCDEF" + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..74c3541c99 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 72k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00012000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c new file mode 100644 index 0000000000..9d6a68a1e4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -0,0 +1,222 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +TX_THREAD blinkThread1; +ALIGN_TYPE blinkThread1Stack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 0); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void BlinkThread1_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + //GPIO_PinOutToggle(gpioPortB, 1); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // #if (HAL_NF_USE_STM32_CRC == TRUE) + // // startup crc + // crcStart(NULL); + // #endif + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create blink thread + status = tx_thread_create( + &blinkThread1, + "Blink Thread1", + BlinkThread1_entry, + 0, + (uint8_t *)blinkThread1Stack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure + // GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInput, 0); + GPIO_PinModeSet(gpioPortB, 0, gpioModePushPull, 0); + +// // output HFRCO onto PD7 +// GPIO_PinModeSet(gpioPortD, 7, gpioModePushPull, 0); +// CMU->ROUTELOC0 = CMU_ROUTELOC0_CLKOUT0LOC_LOC2; +// CMU->CTRL |= CMU_CTRL_CLKOUTSEL0_USHFRCOQ; +// CMU->ROUTEPEN = CMU_ROUTEPEN_CLKOUT0PEN; + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + // if (!IsToRemainInBooter()) + // { + // // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // //if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN) != 0) + // { + // // check for valid CLR image + // // we are checking for a valid image at the deployment address, which is pointing to the CLR address + // if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + // { + // // there seems to be a valid CLR image + + // // need to change HF clock to internal RCO so the CLR can boot smoothly + // CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + + // // launch nanoCLR + // LaunchCLR((uint32_t)&__deployment_start__); + // } + // } + // } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..bbd167197f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,249 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00012000, len = 2M - 72k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 904k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c new file mode 100644 index 0000000000..d81f479cd5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -0,0 +1,200 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + //GPIO_PinOutToggle(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(250)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + // Watchdog_Init(); + + // #if (HAL_NF_USE_STM32_CRC == TRUE) + // // startup crc + // crcStart(NULL); + // #endif + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if GECKO_FEATURE_USBD_WINUSB == TRUE +// TODO + //usb_device_winusb_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..8f926ef311 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c @@ -0,0 +1,254 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..b167de77ff --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,22 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C2 // +////////// + +// Devices available in GG11 dev kit +// Modules | Description | +// Si7021 | Relative Humidity and Temperature Sensor | +// Si7210 | Hall-Effect Sensor | + +// pin configuration for I2C2 +// port for I2C2_SCL is: GPIOI_5 +// port for I2C2_SDA is: GPIOI_4 + +// GPIO alternate pin function is 7 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, gpioPortI, gpioPortI, 5, 4, 7, 7) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..85223e2e09 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,3 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..6dbea05b69 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,34 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI0 // +////////// + +// Note: on SL_STK3701A SPI0 is available at EXP connector + +// pin configuration for SPI0 (EMC encoded "port location") +// SPI0_SCK: PE12, location 0, EXP Header Pin 8 +// SPI0_MOSI: PE10, location 0, EXP Header Pin 4 +// SPI0_MISO: PE11, location 0, EXP Header Pin 6 +// CS: PE13, EXP Header Pin 10 + +INIT_SPI_CONFIG(0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display + +// pin configuration for SPI1 (EMC encoded "port location") +// SPI1_SCK: PC15, location 3 +// SPI1_MOSI: PA14, location 6 +// SPI1_MISO: (not used for LCD) +// CS: PC14 (not used in SPI configuration) + +INIT_SPI_CONFIG(1, 3, 6, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..6dfccbd22e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..6eb0d5a2a4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_dev_onewire_config.h" +#include + +/////////// +// UART0 // +/////////// + +// pin configuration for UART4 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_10 +// GPIO alternate pin function is 8 +UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned(32))) +#endif +uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned(32))) +#endif +uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..840f02a3de --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_STM32_UART_USE_USART0 TRUE +#define GECKO_USE_USART0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c new file mode 100644 index 0000000000..457394d46b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// // pin configuration for stdio using UART4 +// // port for TX pin is: GPIOA +// // port for RX pin is: GPIOA +// // TX pin: is GPIOA_0 +// // RX pin: is GPIOA_1 +// // GPIO alternate pin function is 8 see alternate function mapping ST datasheet +// STDIO_UART_CONFIG_PINS(GPIOA, GPIOA, 0, 1, 8) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h new file mode 100644 index 0000000000..d5df942106 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// Select which STM32 uart/serial port used. +// If you change STDIO_SERIAL_DRIVER here to another UARTn, also +// edit mcuconf.h to set #define STM32_SERIAL_USE_UARTn TRUE +// and edit GPIO pins defined in target_stdio_config.c +// #define STDIO_SERIAL_DRIVER SD4 diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..e675ce5e97 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PE11- ADC0 Port 4X Channel 11 (Expansion Header Pin 6) + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC0 + {0, adcPosSelAPORT4XCH11}, + + // these are the internal sources + {0, adcPosSelTEMP}, + {0, adcPosSelAVDD}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h new file mode 100644 index 0000000000..9423e913ff --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From 38215cb39fe7c46ff8fea7dec95532da9e16fd3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 7 Sep 2022 18:47:16 +0100 Subject: [PATCH 118/572] Fix inclusion of sl_usbd_class_vendor --- CMake/Modules/FindGecko_SDK.cmake | 20 +- CMakeUserPresets.TEMPLATE.json | 4 +- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 9 + .../autogen/sl_usbd_class_vendor_instances.c | 173 ++++++++++++++++++ .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 7 +- .../_common/autogen/sl_component_catalog.h | 20 ++ .../_common/autogen/sl_usbd_init.c | 9 + .../SiliconLabs/_nanoCLR/target_platform.h.in | 1 + 8 files changed, 239 insertions(+), 4 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 8f8967bdb1..90f0a3fd62 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -38,7 +38,8 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udel list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) if(GECKO_FEATURE_USBD_HID OR - HAL_WP_USE_USB_CDC) + HAL_WP_USE_USB_CDC OR + GECKO_FEATURE_USBD_WINUSB) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/protocol/usb/src) @@ -139,7 +140,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_init.c) list(APPEND gecko_sdk_srcs sl_malloc.c) - + endif() if(HAL_WP_USE_SERIAL) @@ -169,6 +170,20 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endif() + if(GECKO_FEATURE_USBD_WINUSB) + + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) + list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) + list(APPEND gecko_sdk_srcs sl_usbd_class_vendor.c) + list(APPEND gecko_sdk_srcs sl_usbd_init.c) + list(APPEND gecko_sdk_srcs sl_malloc.c) + + endif() + foreach(src_file ${gecko_sdk_srcs}) set(gecko_sdk_src_file src_file-NOTFOUND) @@ -229,6 +244,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid_report.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_init.c PROPERTIES COMPILE_FLAGS -Wno-undef) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 73a08bc841..50b1e1b6f8 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -168,6 +168,8 @@ }, "TARGET_SERIAL_BAUDRATE": "115200", "GECKO_FEATURE_USBD_HID": "OFF", + "GECKO_FEATURE_USBD_WINUSB": "OFF", + "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_nanoFramework.GiantGecko.Adc": "ON", "NF_INTEROP_ASSEMBLIES": null @@ -859,4 +861,4 @@ "configurePreset": "TI_CC1352P1_LAUNCHXL" } ] -} \ No newline at end of file +} diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 265cc0d8e3..e274b4bb46 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -9,6 +9,7 @@ include(Gecko_SDK) set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) option(GECKO_FEATURE_USBD_HID "option to use Gecko SDK HID class") +option(GECKO_FEATURE_USBD_WINUSB "option to use Gecko SDK USB vendor class for WinUSB") ################################################################# # Options for Wire Protocol channel @@ -37,6 +38,14 @@ else() set(GECKO_FEATURE_USBD_HID_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_HID for USBD HID") endif() +if(GECKO_FEATURE_USBD_WINUSB) + + set(GECKO_FEATURE_USBD_WINUSB_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") + +else() + set(GECKO_FEATURE_USBD_WINUSB_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") +endif() + # check if GECKO_SDK_SOURCE was specified or if it's empty (default is empty) set(NO_GECKO_SDK_SOURCE TRUE) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c new file mode 100644 index 0000000000..4a5482daad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -0,0 +1,173 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" + + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_vendor.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_vendor_instances.h" + +/* include config file for the instances */ + +#include "sl_usbd_class_winusb_config.h" + + +//**************************************************************************** +// Function declarations. + + + + +/* callback prototypes for winusb instance */ + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req); + + + + +//**************************************************************************** +// Global variables. + + + + +/* variables for winusb instance */ + +uint8_t sl_usbd_vendor_winusb_number = 0; + +sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, +}; + + + +//**************************************************************************** +// Callback functions. + + + + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_enable_event(); + + return; +} + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_disable_event(); + + return; +} + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + + return; +} + + +//**************************************************************************** +// Global functions. + + + +/* initialize winusb instance */ +void sli_usbd_vendor_winusb_init() +{ + bool intr_en = true; + uint16_t interval = 0; + + uint8_t class_number = 0; + uint8_t config_number = 0; + + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, + interval, + &sli_usbd_vendor_winusb_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } + + + /* next token */ + token = strtok(NULL, ", "); + } +} + +void sl_usbd_vendor_winusb_on_enable_event(void) +{ + +} + +void sl_usbd_vendor_winusb_on_disable_event(void) +{ + +} + +void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) +{ + +} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 11e41ec529..152cd22a14 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -166,7 +166,7 @@ void tx_application_define(void *first_unused_memory) } } -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); @@ -177,6 +177,11 @@ void tx_application_define(void *first_unused_memory) usb_device_hid_app_init(); #endif +#if GECKO_FEATURE_USBD_WINUSB == TRUE +// TODO + //usb_device_winusb_app_init(); +#endif + #if HAL_WP_USE_USB_CDC == TRUE sli_usbd_cdc_acm_acm0_init(); usb_device_cdc_acm_app_init(); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h index bf0b2bd150..a0ee173be4 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_component_catalog.h @@ -32,6 +32,26 @@ #endif +#if defined(I_AM_NANOCLR) && GECKO_FEATURE_USBD_WINUSB == TRUE + +#ifndef SL_CATALOG_USB_DEVICE_PRESENT +#define SL_CATALOG_USB_DEVICE_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#define SL_CATALOG_USB_DEVICE_CONFIGURATION_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_CORE_PRESENT +#define SL_CATALOG_USB_DEVICE_CORE_PRESENT +#endif + +#ifndef SL_CATALOG_USB_DEVICE_DRIVER_PRESENT +#define SL_CATALOG_USB_DEVICE_DRIVER_PRESENT +#endif + +#endif + #if HAL_WP_USE_USB_CDC == TRUE #ifndef SL_CATALOG_USB_DEVICE_PRESENT diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index 2158c3b279..4f418ed9cf 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -20,6 +20,10 @@ #include "sl_usbd_class_hid.h" #endif +#if GECKO_FEATURE_USBD_WINUSB == TRUE +#include "sl_usbd_class_vendor.h" +#endif + #if HAL_WP_USE_USB_CDC == TRUE #include "sl_usbd_class_cdc.h" #include "sl_usbd_class_cdc_acm.h" @@ -42,4 +46,9 @@ void sli_usbd_init(void) sl_usbd_cdc_init(); sl_usbd_cdc_acm_init(); #endif + +#if GECKO_FEATURE_USBD_WINUSB == TRUE + sl_usbd_vendor_init(); +#endif + } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 879ca43c27..25339fb6ce 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -33,6 +33,7 @@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ #define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ #define GECKO_FEATURE_USBD_HID @GECKO_FEATURE_USBD_HID_OPTION@ +#define GECKO_FEATURE_USBD_WINUSB @GECKO_FEATURE_USBD_WINUSB_OPTION@ #define HAL_WP_USE_SERIAL @HAL_WP_USE_SERIAL_OPTION@ #define HAL_WP_USE_USB_CDC @HAL_WP_USE_USB_CDC_OPTION@ From a748a2a99f82256286d729aa19b79c303b436a30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 12 Sep 2022 13:03:16 +0100 Subject: [PATCH 119/572] Rework inclusion of several init functions - Now allows target to override default platform implementation. --- CMake/Modules/FindGecko_SDK.cmake | 14 ++++++-- .../_common/autogen/sl_device_init_clocks.c | 28 ---------------- .../autogen/sl_device_init_clocks_default.c | 30 +++++++++++++++++ ...t_handler.c => sl_event_handler_default.c} | 32 +++++++++++++------ 4 files changed, 64 insertions(+), 40 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c rename targets/AzureRTOS/SiliconLabs/_common/autogen/{sl_event_handler.c => sl_event_handler_default.c} (59%) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 90f0a3fd62..b64da64c3f 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -9,12 +9,18 @@ include(FetchContent) FetchContent_GetProperties(gecko_sdk) # set include directories + +# these are locations for SDK config headers +# the locations for the target need to come before the generic ones +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) +# now the locations for the generic one (to be used in case there are none for the target) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/autogen) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/config) + +# now all the rest list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/AzureRTOS) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/autogen) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/config) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) @@ -87,7 +93,9 @@ set(gecko_sdk_srcs sl_device_init_dcdc_s1.c sl_device_init_emu_s1.c sl_device_init_hfxo_s1.c + sl_device_init_hfrco.c sl_device_init_lfxo_s1.c + sl_device_init_lfrco.c sl_device_init_nvic.c sl_power_manager.c sl_power_manager_hal_s0_s1.c @@ -104,7 +112,9 @@ set(gecko_sdk_srcs sl_udelay_armv6m_gcc.S sl_uartdrv_init.c + sl_device_init_clocks_default.c sl_device_init_clocks.c + sl_event_handler_default.c sl_event_handler.c sl_board_default_init_stub.c sl_i2cspm_init.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c deleted file mode 100644 index 30080ed43b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks.c +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Copyright 2019 Silicon Laboratories Inc. www.silabs.com -// See LICENSE file in the project root for full license information. -// - -#include "sl_device_init_clocks.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - - CMU_ClockEnable(cmuClock_HFLE, true); - CMU_ClockEnable(cmuClock_HFPER, true); - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); - CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); -#if defined(_CMU_LFCCLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); -#endif -#if defined(_CMU_LFECLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); -#endif - - return SL_STATUS_OK; -} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c new file mode 100644 index 0000000000..536bf44098 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c @@ -0,0 +1,30 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" +#include + +// implemented as weak function to allow overriding at platform level +__nfweak sl_status_t sl_device_init_clocks(void) +{ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c similarity index 59% rename from targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c index e9ae9cc710..e33e721d06 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c @@ -12,6 +12,8 @@ #include "sl_device_init_dcdc.h" #include "sl_device_init_hfxo.h" #include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" #include "sl_device_init_clocks.h" #include "sl_device_init_emu.h" #include "sl_board_control.h" @@ -26,7 +28,8 @@ #include #include -void sl_platform_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_platform_init(void) { CHIP_Init(); sl_device_init_nvic(); @@ -40,13 +43,15 @@ void sl_platform_init(void) sl_power_manager_init(); } -void sl_kernel_start(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_kernel_start(void) { // Enter the ThreadX kernel. tx_kernel_enter(); } -void sl_driver_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_driver_init(void) { sl_i2cspm_init_instances(); @@ -57,7 +62,8 @@ void sl_driver_init(void) sl_driver_init_target(); } -void sl_service_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_service_init(void) { sl_board_configure_vcom(); sl_sleeptimer_init(); @@ -67,20 +73,24 @@ void sl_service_init(void) #endif } -void sl_stack_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_stack_init(void) { sl_stack_init_target(); } -void sl_internal_app_init(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_internal_app_init(void) { } -void sl_platform_process_action(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_platform_process_action(void) { } -void sl_service_process_action(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_service_process_action(void) { } @@ -88,11 +98,13 @@ void sl_stack_process_action(void) { } -void sl_internal_app_process_action(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_internal_app_process_action(void) { } -void sl_iostream_init_instances(void) +// implemented as weak function to allow overriding at platform level +__nfweak void sl_iostream_init_instances(void) { #if HAL_WP_USE_SERIAL == TRUE sl_iostream_usart_init_instances(); From 8c499c42bdfe82fa47e559e9552c91f77d56edcd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 13 Sep 2022 15:14:30 +0100 Subject: [PATCH 120/572] Add missing files for new configuration options --- .../autogen/sl_device_init_clocks.c | 8 +++++ .../SL_STK3701A/autogen/sl_event_handler.c | 8 +++++ .../config/sl_device_init_hfrco_config.h | 27 +++++++++++++++ .../config/sl_device_init_lfrco_config.h | 34 +++++++++++++++++++ 4 files changed, 77 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..4501c16160 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_device_init_clocks.c @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE THIS FUNCTIONS // +/////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_event_handler.c new file mode 100644 index 0000000000..4501c16160 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_event_handler.c @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE THIS FUNCTIONS // +/////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H From 80d09c54e2493574ca76d127f523f35f63437eda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 13 Sep 2022 17:02:07 +0100 Subject: [PATCH 121/572] Enable back loading the CLR - Still not checking for GPIO to remain in bootloader. --- .../SKY_EEVB_PROTO1/nanoBooter/main.c | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c index 9d6a68a1e4..a390e72e55 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -202,18 +202,18 @@ int main(void) // // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter // //if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN) != 0) // { - // // check for valid CLR image - // // we are checking for a valid image at the deployment address, which is pointing to the CLR address - // if (CheckValidCLRImage((uint32_t)&__deployment_start__)) - // { - // // there seems to be a valid CLR image - - // // need to change HF clock to internal RCO so the CLR can boot smoothly - // CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); - - // // launch nanoCLR - // LaunchCLR((uint32_t)&__deployment_start__); - // } + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } // } // } From 63184b8ea1f9b9f8018d59086b28659aa93e66e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 13 Sep 2022 17:02:26 +0100 Subject: [PATCH 122/572] Add missing bit in cmake user preset template --- CMakeUserPresets.TEMPLATE.json | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 50b1e1b6f8..137082ef77 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -670,6 +670,11 @@ "displayName": "SL_STK3701A_REVB", "configurePreset": "SL_STK3701A_REVB" }, + { + "name": "SKY_EEVB_PROTO1", + "displayName": "SKY_EEVB_PROTO1", + "configurePreset": "SKY_EEVB_PROTO1" + }, { "name": "ESP32_PSRAM_REV0", "displayName": "ESP32_PSRAM_REV0", From 59eef06c675f183fca743b92d2e1f45505dd5781 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 13 Sep 2022 17:47:36 +0100 Subject: [PATCH 123/572] Remove need for BSP config from Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 9 +++++++-- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index b64da64c3f..51736ce220 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -22,8 +22,13 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/Silicon list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/AzureRTOS) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) +# include path to Gecko SDK BSP only if required +# to include Gecko BSP, set the variable GECKO_SDK_BSP in the target CMakeLists.txt +if(GECKO_SDK_BSP) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) +endif() + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/board/inc) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index baa3eb7149..8bd99ba614 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -11,6 +11,8 @@ set(THREADX_TOOLCHAIN "gnu" ) # set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) +# include BSP from Gecko SDK +set(GECKO_SDK_BSP TRUE CACHE BOOL "Setting Gecko BSP flag ") add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) # add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) From cf8a3b5db0941f10fe3d26886c2023a7c815b094 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 13 Sep 2022 17:47:36 +0100 Subject: [PATCH 124/572] Remove need for BSP config from Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 9 +++++++-- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index b64da64c3f..51736ce220 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -22,8 +22,13 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/Silicon list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_include) list(APPEND Gecko_SDK_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/targets/AzureRTOS) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) -list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) +# include path to Gecko SDK BSP only if required +# to include Gecko BSP, set the variable GECKO_SDK_BSP in the target CMakeLists.txt +if(GECKO_SDK_BSP) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/common/bsp) + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/kit/${TARGET_BOARD_SHORT}_${TARGET_SERIES}/config) +endif() + list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/common/toolchain/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/hardware/board/inc) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index baa3eb7149..8bd99ba614 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -11,6 +11,8 @@ set(THREADX_TOOLCHAIN "gnu" ) # set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) +# include BSP from Gecko SDK +set(GECKO_SDK_BSP TRUE CACHE BOOL "Setting Gecko BSP flag ") add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) # add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) From feff0baaa91206ea09b2dce51b1441f48c5a505d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 14 Sep 2022 18:09:10 +0100 Subject: [PATCH 125/572] More work implementing Gecko ADC library --- .../FindnanoFramework.GiantGecko.Adc.cmake | 1 + .../nano_gg_adc_native.cpp | 41 +++++++++- .../nano_gg_adc_native.h | 74 ++++++++++++++----- ...anoFramework_GiantGecko_Adc_AdcChannel.cpp | 35 +++++++++ ...Framework_GiantGecko_Adc_AdcController.cpp | 63 +++++++++++++++- 5 files changed, 187 insertions(+), 27 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp diff --git a/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake b/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake index 1fc2aaf8df..f7febd93f2 100644 --- a/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake +++ b/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake @@ -18,6 +18,7 @@ set(nanoFramework.GiantGecko.Adc_SRCS nano_gg_adc_native.cpp + nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp ) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index 5c5816e487..6bfbb5f950 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -9,6 +9,24 @@ static const CLR_RT_MethodHandler method_lookup[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4, + NULL, + NULL, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, NULL, NULL, NULL, @@ -39,17 +57,32 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::GetSingleConversion___U4, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::StartContinuousConversion___BOOLEAN, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___BOOLEAN, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStoptContinuousConversion___BOOLEAN, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastScanSampleForChannel___I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0xF231CDFB, + 0x252EAE1B, method_lookup, - { 1, 0, 0, 0 } + { 100, 1, 0, 0 } }; // clang-format on diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index 0661431443..3b3f56e326 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -25,12 +25,6 @@ typedef enum __nfpack AquisitionTime AquisitionTime__256Cyles = 10, } AquisitionTime; -typedef enum __nfpack InputOption -{ - InputOption_SingleEnded = 0, - InputOption_Differential = 1, -} InputOption; - typedef enum __nfpack LowpassFilterMode { LowpassFilterMode_Bypass = 0, @@ -56,6 +50,7 @@ typedef enum __nfpack OversampleRate typedef enum __nfpack PrsSampleTrigger { + PrsSampleTrigger_Disabled = -1, PrsSampleTrigger_PrsChannel0 = 0, PrsSampleTrigger_PrsChannel1 = 1, PrsSampleTrigger_PrsChannel2 = 2, @@ -122,7 +117,39 @@ typedef enum __nfpack WarmUpMode WarmUpMode_KeepAdcWarm = 3, } WarmUpMode; -struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AcdInitialization +typedef enum __nfpack AdcChannelMode +{ + AdcChannelMode_SingleEnded = 0, + AdcChannelMode_Differential = 1, +} AdcChannelMode; + +struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel +{ + static const int FIELD___syncLock = 2; + static const int FIELD___disposed = 3; + static const int FIELD___channelNumber = 4; + static const int FIELD___adcChannelConfiguration = 5; + static const int FIELD___averageCount = 6; + + NANOCLR_NATIVE_DECLARE(get_LastContinuousValue___I4); + NANOCLR_NATIVE_DECLARE(NativeReadValue___I4); + NANOCLR_NATIVE_DECLARE(NativeDisposeChannel___VOID); + + //--// +}; + +struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannelConfiguration +{ + static const int FIELD___prsSampleTrigger = 1; + static const int FIELD___aquisitionTime = 2; + static const int FIELD___referenceVoltage = 3; + static const int FIELD___sampleResolution = 4; + static const int FIELD___channelMode = 5; + + //--// +}; + +struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcConfiguration { static const int FIELD___oversampleRate = 1; static const int FIELD___lowpassFilterMode = 2; @@ -137,20 +164,27 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AcdInitialization struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController { static const int FIELD___syncLock = 1; - static const int FIELD___prsSampleTrigger = 2; - static const int FIELD___aquisitionTime = 3; - static const int FIELD___referenceVoltage = 4; - static const int FIELD___sampleResolution = 5; - static const int FIELD___scanInput = 6; - static const int FIELD___inputOption = 7; - static const int FIELD___prsEnable = 8; - static const int FIELD___acdInitialization = 9; - static const int FIELD__LedfAdjust = 10; - static const int FIELD__ContinuousConversion = 11; - - NANOCLR_NATIVE_DECLARE(GetSingleConversion___U4); - NANOCLR_NATIVE_DECLARE(StartContinuousConversion___BOOLEAN); + static const int FIELD___scanChannels = 2; + static const int FIELD___averageCount = 3; + static const int FIELD___continuousSamplingStarted = 4; + static const int FIELD___acdConfiguration = 5; + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); + NANOCLR_NATIVE_DECLARE(NativeIsChannelModeSupported___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution); + NANOCLR_NATIVE_DECLARE(NativeStartContinuousConversion___BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeStoptContinuousConversion___BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeGetLastContinuousSamples___SZARRAY_I4); + NANOCLR_NATIVE_DECLARE(NativeGetLastScanSampleForChannel___I4__I4); + + //--// +}; + +struct Library_nano_gg_adc_native_System_Device_Adc_AdcChannelBase +{ + static const int FIELD___adcController = 1; //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp new file mode 100644 index 0000000000..db888d1e8f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nano_gg_adc_native.h" + + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 8b12a007ef..693801ed5a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -1,12 +1,24 @@ // // Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. // See LICENSE file in the project root for full license information. // #include "nano_gg_adc_native.h" -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::GetSingleConversion___U4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame &stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // all required initialization for ADC is handled in OpenChannel call + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -15,7 +27,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::G NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::StartContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -24,7 +36,52 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::S NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStoptContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastScanSampleForChannel___I4__I4( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); From 9c970f37f5b0ed38d1d218e62faf3c6db3045020 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 15 Sep 2022 15:04:20 +0100 Subject: [PATCH 126/572] Fix LTO options for Gecko SDK --- CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake | 8 ++++---- CMake/binutils.AzureRTOS.cmake | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index 82eb618feb..7066a3899d 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -54,14 +54,14 @@ macro(nf_set_link_options) message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_link_options()") endif() - # request specs from newlib nano - set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs --specs=nosys.specs") - # set optimization linker flags for RELEASE and MinSizeRel if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") - set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -Os -flto ") endif() + # request specs from newlib nano + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs --specs=nosys.specs ") + # include libraries in build nf_include_libraries_in_build(${NFSLO_TARGET}) diff --git a/CMake/binutils.AzureRTOS.cmake b/CMake/binutils.AzureRTOS.cmake index 6fdc580c26..7490d432ce 100644 --- a/CMake/binutils.AzureRTOS.cmake +++ b/CMake/binutils.AzureRTOS.cmake @@ -9,10 +9,10 @@ include(binutils.common) function(nf_set_optimization_options target) target_compile_options(${target} PRIVATE - $<$:-Og -femit-class-debug-always -g3 -ggdb> - $<$:-O3> - $<$:-Os> - $<$:-Os -femit-class-debug-always -g3 -ggdb> + $<$:-Og -ggdb> + $<$:-O3 -flto -ffat-lto-objects> + $<$:-Os -flto -ffat-lto-objects> + $<$:-Os -femit-class-debug-always -g3-ggdb> ) endfunction() From 37f47260692454a04a31f61b5e4fe2dba999c789 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 15 Sep 2022 15:09:18 +0100 Subject: [PATCH 127/572] Add dummy implementation for reentrant sys calls --- .../SiliconLabs/_common/CMakeLists.txt | 1 + .../AzureRTOS/SiliconLabs/_common/sys_calls.c | 80 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/sys_calls.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index 089e772bdc..e654b32e50 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -7,6 +7,7 @@ list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_SL_MscFlashDriver.c) list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c) # list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c) +list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/sys_calls.c) # append Target files list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c) diff --git a/targets/AzureRTOS/SiliconLabs/_common/sys_calls.c b/targets/AzureRTOS/SiliconLabs/_common/sys_calls.c new file mode 100644 index 0000000000..7a92128b64 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/sys_calls.c @@ -0,0 +1,80 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// dummy implementations for the newlib reentrant functions +// required to link with Gecko SDK as adding --specs=nosys.specs doesn't seem to work + +#include + +int _close(int file) +{ + (void)file; + return 0; +} + +void _exit(int status) +{ + (void)status; + while (1) + { + } /* Hang here forever... */ +} + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _getpid(void) +{ + return 1; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + return -1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _read(int file, char *ptr, int len) +{ + (void)file; + (void)ptr; + (void)len; + + return -1; +} + +int _write(int file, const char *ptr, int len) +{ + int txCount; + + (void)file; + + for (txCount = 0; txCount < len; txCount++) + { + ptr++; + } + + return len; +} From 99c204957455470f347c5ae821cae795ae535d7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 15 Sep 2022 18:13:46 +0100 Subject: [PATCH 128/572] Work on Gecko ADC --- .../FindnanoFramework.GiantGecko.Adc.cmake | 8 ++- CMakeUserPresets.TEMPLATE.json | 1 + .../SL_STK3701A/target_nano_gg_adc_config.cpp | 20 +++++++ .../SL_STK3701A/target_nano_gg_adc_config.h | 6 +++ ...anoFramework_GiantGecko_Adc_AdcChannel.cpp | 2 +- ...Framework_GiantGecko_Adc_AdcController.cpp | 53 ++++++++++++++++++- .../nano_gg_adc_native_target.h | 39 ++++++++++++++ 7 files changed, 122 insertions(+), 7 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h diff --git a/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake b/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake index f7febd93f2..7c51d1fe2a 100644 --- a/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake +++ b/CMake/Modules/FindnanoFramework.GiantGecko.Adc.cmake @@ -6,21 +6,19 @@ # native code directory set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.GiantGecko.Adc) - # set include directories -list(APPEND nanoFramework.Device.OneWire_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) -list(APPEND nanoFramework.Device.OneWire_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) -list(APPEND nanoFramework.GiantGecko.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/nanoFramework.GiantGecko.Adc) +list(APPEND nanoFramework.GiantGecko.Adc_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND nanoFramework.GiantGecko.Adc_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) # source files set(nanoFramework.GiantGecko.Adc_SRCS nano_gg_adc_native.cpp - nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp + target_nano_gg_adc_config.cpp ) foreach(SRC_FILE ${nanoFramework.GiantGecko.Adc_SRCS}) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 50b1e1b6f8..3e43b6bd05 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -171,6 +171,7 @@ "GECKO_FEATURE_USBD_WINUSB": "OFF", "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Adc": "OFF", "API_nanoFramework.GiantGecko.Adc": "ON", "NF_INTEROP_ASSEMBLIES": null } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..b5bc402a83 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PE11- ADC0 Port 4X Channel 11 (Expansion Header Pin 6) + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC0 + {0, adcPosSelAPORT4XCH11}, + + // these are the internal sources + {0, adcPosSelTEMP}, + {0, adcPosSelAVDD}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..9423e913ff --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nano_gg_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index db888d1e8f..f91a153254 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -5,7 +5,7 @@ // #include "nano_gg_adc_native.h" - +#include "nano_gg_adc_native_target.h" HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( CLR_RT_StackFrame &stack ) { diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 693801ed5a..7e887b077e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -5,7 +5,9 @@ // #include "nano_gg_adc_native.h" +#include "nano_gg_adc_native_target.h" +#define ADC_FREQ 16000000 HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame &stack ) { @@ -22,7 +24,56 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + int channel; + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + ADC_Init_TypeDef adcInit; + CMU_Clock_TypeDef adcClock; + ADC_TypeDef *adcDriver = NULL; + + adcInit = ADC_INIT_DEFAULT; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Get channel from argument + channel = stack.Arg1().NumericByRef().s4; + + adcDefinition = AdcPortPinConfig[channel]; + + // we should remove from the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch (adcDefinition.adcIndex) + { + +#if GECKO_USE_ADC0 + case 0: + adcDriver = ADC0; + adcClock = cmuClock_ADC0; + break; +#endif + +#if GECKO_USE_ADC1 + case 1: + adcDriver = ADC1; + adcClock = cmuClock_ADC1; + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Enable ADC clock + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(adcClock, true); + + // Init to max ADC clock for Series 1 + adcInit.prescale = ADC_PrescaleCalc(ADC_FREQ, 0); + adcInit.timebase = ADC_TimebaseCalc(0); + + // start ADC + ADC_Init(adcDriver, &adcInit); NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h new file mode 100644 index 0000000000..15895ece24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h @@ -0,0 +1,39 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_ADC_NATIVE_TARGET_H +#define SYS_DEV_ADC_NATIVE_TARGET_H + +#include +#include +#include "em_cmu.h" + +#include "nano_gg_adc_native.h" +#include + +// set missing defines +#ifndef GECKO_USE_ADC0 +#define GECKO_USE_ADC0 FALSE +#endif +#ifndef GECKO_USE_ADC1 +#define GECKO_USE_ADC1 FALSE +#endif +#ifndef GECKO_USE_ADC2 +#define GECKO_USE_ADC2 FALSE +#endif +#ifndef GECKO_USE_ADC3 +#define GECKO_USE_ADC3 FALSE +#endif + +typedef struct +{ + uint8_t adcIndex; + ADC_PosSel_TypeDef posSel; +} NF_PAL_ADC_PORT_PIN_CHANNEL; + +extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; +extern const int AdcChannelCount; + +#endif // SYS_DEV_ADC_NATIVE_TARGET_H From 68c4f3765754b0861de50bbf94a0b2a45947f9e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 16 Sep 2022 16:20:30 +0100 Subject: [PATCH 129/572] Add Gecko ADC config files --- .../target_nano_gg_adc_config.cpp | 20 +++++++++++++++++++ .../target_nano_gg_adc_config.h | 6 ++++++ 2 files changed, 26 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..b5bc402a83 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PE11- ADC0 Port 4X Channel 11 (Expansion Header Pin 6) + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC0 + {0, adcPosSelAPORT4XCH11}, + + // these are the internal sources + {0, adcPosSelTEMP}, + {0, adcPosSelAVDD}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..9423e913ff --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 TRUE From f0ed810853c41c0bafec4f6f19212bc4b8af1b71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Sep 2022 09:31:01 +0100 Subject: [PATCH 130/572] More work on Gecko ADC implementation --- ...anoFramework_GiantGecko_Adc_AdcChannel.cpp | 112 +++++++++++++++- ...Framework_GiantGecko_Adc_AdcController.cpp | 120 ++++++++++++++---- .../nano_gg_adc_native_target.h | 10 ++ .../SiliconLabs/_nanoCLR/targetHAL.cpp | 20 +++ 4 files changed, 233 insertions(+), 29 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index f91a153254..c44ae51d7b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -7,7 +7,32 @@ #include "nano_gg_adc_native.h" #include "nano_gg_adc_native_target.h" -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( CLR_RT_StackFrame &stack ) +// add typedef for AdcChannelConfiguration to ease access and improve readability +typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannelConfiguration AdcChannelConfiguration; + +void ParseAdcChannelConfig(CLR_RT_HeapBlock *channelConfiguration, void *adcInit) +{ + ADC_InitSingle_TypeDef channelInitSingle = ADC_INITSINGLE_DEFAULT; + ADC_InitScan_TypeDef channelInitScan = ADC_INITSINGLE_DEFAULT; + + // now map the AdcChannelConfiguration object to the native structure + channelInitSingle.prsSel = + (ADC_PRSSEL_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___prsSampleTrigger].NumericByRef().s4; + channelInitSingle.acqTime = + (ADC_AcqTime_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___aquisitionTime].NumericByRef().s4; + channelInitSingle.reference = + (ADC_Ref_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___referenceVoltage].NumericByRef().s4; + channelInitSingle.diff = + (AdcChannelMode)channelConfiguration[AdcChannelConfiguration::FIELD___channelMode].NumericByRef().s4 == + AdcChannelMode_Differential + ? true + : false; + + memcpy(adcInit, &channelInitSingle, sizeof(ADC_InitSingle_TypeDef)); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -16,20 +41,95 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_ NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + int channelNumber; + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + + // ADC related variables + ADC_TypeDef *adcDriver = NULL; + ADC_InitSingle_TypeDef channelInitSingle; + uint64_t samplesAccumulator = 0; + uint32_t averageCount; + uint32_t samplesCount; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + // OK to skip validation here because the channelNumber has been validated in the constructor + adcDefinition = AdcPortPinConfig[channelNumber]; + + // we should remove form the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch (adcDefinition.adcIndex) + { + +#if GECKO_USE_ADC0 + case 0: + adcDriver = ADC0; + break; +#endif + +#if GECKO_USE_ADC1 + case 1: + adcDriver = ADC1; + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get the average counter + averageCount = stack.Arg1().NumericByRef().s4; + + // sanity check (need to take at least one sample) + if (averageCount < 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + samplesCount = averageCount; + + // get a pointer to the channel AdcChannelConfiguration object instance + ParseAdcChannelConfig(pThis[FIELD___averageCount].Dereference(), &channelInitSingle); + + ADC_InitSingle(adcDriver, &channelInitSingle); + + while (samplesCount--) + { + // start the conversion + ADC_Start(adcDriver, adcStartSingle); + + // Wait for conversion to complete + while (ADC0->STATUS & ADC_STATUS_SINGLEACT) + ; + + // store sample + samplesAccumulator += ADC_DataSingleGet(adcDriver); + } + + // set the return result with the conversion value averaged from the accumulator + stack.SetResult_I4(samplesAccumulator / averageCount); NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID( + CLR_RT_StackFrame &stack) { + (void)stack; + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // left empty on purpose, nothing to do here - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP_NOLABEL(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 7e887b077e..b38abe3990 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -7,9 +7,22 @@ #include "nano_gg_adc_native.h" #include "nano_gg_adc_native_target.h" -#define ADC_FREQ 16000000 +#define ADC_IMPOSSIBLE_CLOCK 90000000UL -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame &stack ) +#if GECKO_USE_ADC0 +ADC_Init_TypeDef adc0Init; +bool adc0Initialized = false; +#endif +#if GECKO_USE_ADC1 +ADC_Init_TypeDef adc1Init; +bool adc1Initialized = false; +#endif + +// add typedef for AdcConfiguration to ease access and improve readability +typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcConfiguration AdcConfiguration; + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( + CLR_RT_StackFrame &stack) { (void)stack; @@ -20,17 +33,19 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP_NOLABEL(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); int channel; - NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; - ADC_Init_TypeDef adcInit; + NF_PAL_ADC_PORT_PIN_CHANNEL adcChannelDefinition; CMU_Clock_TypeDef adcClock; ADC_TypeDef *adcDriver = NULL; + ADC_Init_TypeDef *adcInit = NULL; + bool *adcInitialized = NULL; - adcInit = ADC_INIT_DEFAULT; + CLR_RT_HeapBlock *adcConfiguration; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -39,17 +54,26 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N // Get channel from argument channel = stack.Arg1().NumericByRef().s4; - adcDefinition = AdcPortPinConfig[channel]; + // sanity check for existing configuration + if (channel >= AdcChannelCount) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // grab ADC channel definition + adcChannelDefinition = AdcPortPinConfig[channel]; // we should remove from the build the ADC options that aren't implemented // plus we have to use the default to catch invalid ADC Ids - switch (adcDefinition.adcIndex) + switch (adcChannelDefinition.adcIndex) { #if GECKO_USE_ADC0 case 0: adcDriver = ADC0; adcClock = cmuClock_ADC0; + adcInit = &adc0Init; + adcInitialized = &adc0Initialized; break; #endif @@ -57,6 +81,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N case 1: adcDriver = ADC1; adcClock = cmuClock_ADC1; + adcInit = &adc1Init; + adcInitialized = &adc1Initialized; break; #endif @@ -64,21 +90,63 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // Enable ADC clock - CMU_ClockEnable(cmuClock_HFPER, true); - CMU_ClockEnable(adcClock, true); + // is this ADC already initialized? + if ( +#if GECKO_USE_ADC0 + (adcDriver == ADC0 && !adcInitialized) +#endif +#if GECKO_USE_ADC0 && GECKO_USE_ADC1 + || +#endif +#if GECKO_USE_ADC1 + (adcDriver == ADC1 && !adcInitialized) +#endif + ) + { + // get a pointer to the managed AdcConfiguration object instance + adcConfiguration = pThis[FIELD___acdConfiguration].Dereference(); + + // init with default values + *adcInit = ADC_INIT_DEFAULT; + + // now map the AdcConfiguration object to the native structure + adcInit->ovsRateSel = + (ADC_OvsRateSel_TypeDef)adcConfiguration[AdcConfiguration::FIELD___oversampleRate].NumericByRef().s4; + +#if defined(_ADC_CTRL_LPFMODE_MASK) + adcInit->lpfMode = + (ADC_LPFilter_TypeDef)adcConfiguration[AdcConfiguration::FIELD___lowpassFilterMode].NumericByRef().s4; +#endif - // Init to max ADC clock for Series 1 - adcInit.prescale = ADC_PrescaleCalc(ADC_FREQ, 0); - adcInit.timebase = ADC_TimebaseCalc(0); + adcInit->warmUpMode = + (ADC_Warmup_TypeDef)adcConfiguration[AdcConfiguration::FIELD___warmUpMode].NumericByRef().s4; + adcInit->tailgate = (bool)adcConfiguration[AdcConfiguration::FIELD___tailgating].NumericByRef().u1; - // start ADC - ADC_Init(adcDriver, &adcInit); + // Enable ADC clock + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(adcClock, true); + + // init to max possible ADC clock + adcInit->prescale = ADC_PrescaleCalc(ADC_IMPOSSIBLE_CLOCK, 0); + // let the drivers compute the appropriate value for the reference clock + adcInit->timebase = ADC_TimebaseCalc(0); + +#if defined(_ADC_CTRL_ADCCLKMODE_MASK) + adcInit->em2ClockConfig = adcEm2ClockOnDemand; +#endif + + // start ADC + ADC_Init(adcDriver, adcInit); + + // set ADC initialized flag + *adcInitialized = true; + } NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -87,7 +155,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeIsChannelModeSupported___BOOLEAN__I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -96,7 +165,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -105,7 +175,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeStartContinuousConversion___BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -114,7 +185,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStoptContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeStoptContinuousConversion___BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -123,7 +195,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetLastContinuousSamples___SZARRAY_I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -132,7 +205,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastScanSampleForChannel___I4__I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetLastScanSampleForChannel___I4__I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h index 15895ece24..40a908ad0e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h @@ -36,4 +36,14 @@ typedef struct extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; extern const int AdcChannelCount; +#if GECKO_USE_ADC0 +extern ADC_Init_TypeDef adc0Init; +extern bool adc0Initialized; +#endif +#if GECKO_USE_ADC1 +extern ADC_Init_TypeDef adc1Init; +extern bool adc1Initialized; +#endif + + #endif // SYS_DEV_ADC_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 7ee6d6a2c6..0c7e925eef 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -13,6 +13,7 @@ #include #include +#include // #if (HAL_USE_CAN == TRUE) // #include @@ -27,6 +28,10 @@ extern void DeInitPwm(); #endif +#if (GECKO_USE_ADC0 == TRUE) || (GECKO_USE_ADC1 == TRUE) +#include +#endif + // global mutex protecting the internal state of the interpreter, including event flags // mutex_t interpreterGlobalMutex; @@ -126,6 +131,12 @@ void nanoHAL_Initialize() #endif +#if GECKO_USE_ADC0 +adc0Initialized = false; +#endif +#if GECKO_USE_ADC1 +adc1Initialized = false; +#endif // #if (HAL_USE_UART == TRUE) // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) @@ -260,6 +271,15 @@ void nanoHAL_Uninitialize() nanoSPI_Uninitialize(); #endif +#if GECKO_USE_ADC0 +ADC_Reset(ADC0); +adc0Initialized = false; +#endif +#if GECKO_USE_ADC1 +ADC_Reset(ADC1); +adc1Initialized = false; +#endif + // #if (HAL_USE_UART == TRUE) // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) From 539bbf48af9ff7734657eb7210ac79f3da92b992 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Sep 2022 10:55:02 +0100 Subject: [PATCH 131/572] Add HAL/PAL configs for SKY_EEVB_PROTO1 --- .../SiliconLabs/SKY_EEVB_PROTO1/README.md | 40 ++++++++++--------- .../target_com_sky_nf_dev_i2c_config.cpp | 26 +++++++----- .../target_com_sky_nf_dev_i2c_config.h | 3 +- .../target_com_sky_nf_dev_spi_config.cpp | 29 ++++---------- .../target_com_sky_nf_dev_spi_config.h | 1 - .../target_nano_gg_adc_config.cpp | 19 ++++++++- .../target_nf_dev_onewire_config.cpp | 21 +++------- .../SKY_EEVB_PROTO1/target_stdio_config.c | 8 ---- .../SKY_EEVB_PROTO1/target_stdio_config.h | 6 --- .../target_system_device_adc_config.cpp | 16 +------- .../target_system_device_adc_config.h | 2 +- 11 files changed, 71 insertions(+), 100 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md index 2ec34ed193..30269171db 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md @@ -1,27 +1,31 @@ -# Silabs EFM32 Giant Gecko GG11 Starter Kit (revC hardware) - -This target is for revC hardware. This can be easily identified by the presence of a USB-C connector for JLink connection. -Opposed to revB which carries a micro USB connector instead. For revB user the firmware for target `SL_STK3701A_REVB`. - -## Setting the VCP baud rate to 921600 - -https://community.silabs.com/s/article/kba-bt-1208-using-virtual-com-port-vcom-x - -:warning: -Only possible for revC hardware. +# Skyworks EVB featuring Silabs EFM32 Giant Gecko GG11 ## ADC channels ADC has enabled the following channels: -0 - reading from PE11 (pin 6 on the expansion header) +0 - reading from PA15 (MCU_ADC1) +1 - reading from PE15 (MCU_ADC1) +2 - reading from PE14 (MCU_ADC2) +3 - reading from PE13 (MCU_ADC3) +4 - reading from PE12 (MCU_ADC4) +5 - reading from PE11 (MCU_ADC5) 1 - internal temperature 2 - VCC -:warning: -Vref is 2.5V for all channels, except for VCC which is 5V. +## I2C + +I2C0 +SCL is: PA1 +SDA is: PA0 + +I2C1 +SCL is: PC5 +SDA is: PC4 -## PWM +## SPI -PWM has enabled the following GPIOs: -0 - PC1 (pin 15 on the expansion header) -1 - PI1 (through hole connector at bottom side) +SPI1 +SCK: PD2 +MOSI: PD0 +MISO: PD1 +CS: PD3 diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp index b167de77ff..37dc3dbc9f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp @@ -6,17 +6,23 @@ #include ////////// -// I2C2 // +// I2C0 // ////////// -// Devices available in GG11 dev kit -// Modules | Description | -// Si7021 | Relative Humidity and Temperature Sensor | -// Si7210 | Hall-Effect Sensor | +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 -// pin configuration for I2C2 -// port for I2C2_SCL is: GPIOI_5 -// port for I2C2_SDA is: GPIOI_4 +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) -// GPIO alternate pin function is 7 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(2, gpioPortI, gpioPortI, 5, 4, 7, 7) +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h index 85223e2e09..ff99df51a3 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h @@ -1,3 +1,4 @@ // Copyright Skyworks Solutions, Inc. All Rights Reserved. -#define GECKO_USE_I2C2 TRUE +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp index 6dbea05b69..5eeab9653f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp @@ -5,30 +5,15 @@ #include -////////// -// SPI0 // -////////// - -// Note: on SL_STK3701A SPI0 is available at EXP connector - -// pin configuration for SPI0 (EMC encoded "port location") -// SPI0_SCK: PE12, location 0, EXP Header Pin 8 -// SPI0_MOSI: PE10, location 0, EXP Header Pin 4 -// SPI0_MISO: PE11, location 0, EXP Header Pin 6 -// CS: PE13, EXP Header Pin 10 - -INIT_SPI_CONFIG(0, 0, 0, 0) - ////////// // SPI1 // ////////// -// Note: on SL_STK3701A SPI1 connects to the LCD-TFT Display - -// pin configuration for SPI1 (EMC encoded "port location") -// SPI1_SCK: PC15, location 3 -// SPI1_MOSI: PA14, location 6 -// SPI1_MISO: (not used for LCD) -// CS: PC14 (not used in SPI configuration) +// pin configuration for SPI1 +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// CS: PD3 (not used in SPI configuration) +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(1, 3, 6, 0) +INIT_SPI_CONFIG(1, 1, 1, 1) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h index 6dfccbd22e..56b68d1d4e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h @@ -3,5 +3,4 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 TRUE #define GECKO_USE_SPI1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp index b5bc402a83..26e7a90b6e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp @@ -5,11 +5,26 @@ #include -// PE11- ADC0 Port 4X Channel 11 (Expansion Header Pin 6) +// PA15: ADC0 APORT2X Channel 15 +// PE15: ADC0 APORT4X Channel 15 +// PE14: ADC0 APORT4Y Channel 14 +// PE13: ADC0 APORT4X Channel 13 +// PE12: ADC0 APORT4Y Channel 12 +// PE11: ADC0 APORT4X Channel 11 const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - // ADC0 + // MCU_ADC1 + {0, adcPosSelAPORT2XCH15}, + // MCU_ADC2 + {0, adcPosSelAPORT4XCH15}, + // MCU_ADC3 + {0, adcPosSelAPORT4YCH14}, + // MCU_ADC4 + {0, adcPosSelAPORT4XCH13}, + // MCU_ADC5 + {0, adcPosSelAPORT4YCH12}, + // MCU_ADC6 {0, adcPosSelAPORT4XCH11}, // these are the internal sources diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp index 6eb0d5a2a4..3a019bb807 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp @@ -10,20 +10,9 @@ // UART0 // /////////// -// pin configuration for UART4 -// port for TX pin is: GPIOC -// TX pin: is GPIOC_10 -// GPIO alternate pin function is 8 -UART_CONFIG_PINS(4, GPIOC, 10, 8) +// pin configuration for UART0 +// UART0 TX: PE10, location 1 +// UART0 TX: PE11, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -// buffers -// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary -// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) -#if defined(__GNUC__) -__attribute__((aligned(32))) -#endif -uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; -#if defined(__GNUC__) -__attribute__((aligned(32))) -#endif -uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; +UART_CONFIG_PINS(0, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c index 457394d46b..efb9bced52 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c @@ -5,11 +5,3 @@ // #include - -// // pin configuration for stdio using UART4 -// // port for TX pin is: GPIOA -// // port for RX pin is: GPIOA -// // TX pin: is GPIOA_0 -// // RX pin: is GPIOA_1 -// // GPIO alternate pin function is 8 see alternate function mapping ST datasheet -// STDIO_UART_CONFIG_PINS(GPIOA, GPIOA, 0, 1, 8) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h index d5df942106..d560ea678f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h @@ -3,9 +3,3 @@ // Portions Copyright (c) Microsoft Corporation. All rights reserved. // See LICENSE file in the project root for full license information. // - -// Select which STM32 uart/serial port used. -// If you change STDIO_SERIAL_DRIVER here to another UARTn, also -// edit mcuconf.h to set #define STM32_SERIAL_USE_UARTn TRUE -// and edit GPIO pins defined in target_stdio_config.c -// #define STDIO_SERIAL_DRIVER SD4 diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp index e675ce5e97..370059f6f8 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp @@ -3,18 +3,4 @@ // See LICENSE file in the project root for full license information. // -#include - -// PE11- ADC0 Port 4X Channel 11 (Expansion Header Pin 6) - -const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - - // ADC0 - {0, adcPosSelAPORT4XCH11}, - - // these are the internal sources - {0, adcPosSelTEMP}, - {0, adcPosSelAVDD}, -}; - -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h index 9423e913ff..370059f6f8 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h @@ -3,4 +3,4 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_ADC0 TRUE +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. From 78aec862ab3198f05f932e1c80b13eb747cbc776 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Sep 2022 09:31:01 +0100 Subject: [PATCH 132/572] More work on Gecko ADC implementation --- ...anoFramework_GiantGecko_Adc_AdcChannel.cpp | 112 +++++++++++++++- ...Framework_GiantGecko_Adc_AdcController.cpp | 120 ++++++++++++++---- .../nano_gg_adc_native_target.h | 10 ++ .../SiliconLabs/_nanoCLR/targetHAL.cpp | 20 +++ 4 files changed, 233 insertions(+), 29 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index f91a153254..6f9b180558 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -7,7 +7,32 @@ #include "nano_gg_adc_native.h" #include "nano_gg_adc_native_target.h" -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( CLR_RT_StackFrame &stack ) +// add typedef for AdcChannelConfiguration to ease access and improve readability +typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannelConfiguration AdcChannelConfiguration; + +void ParseAdcChannelConfig(CLR_RT_HeapBlock *channelConfiguration, void *adcInit) +{ + ADC_InitSingle_TypeDef channelInitSingle = ADC_INITSINGLE_DEFAULT; + //ADC_InitScan_TypeDef channelInitScan = ADC_INITSCAN_DEFAULT; + + // now map the AdcChannelConfiguration object to the native structure + channelInitSingle.prsSel = + (ADC_PRSSEL_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___prsSampleTrigger].NumericByRef().s4; + channelInitSingle.acqTime = + (ADC_AcqTime_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___aquisitionTime].NumericByRef().s4; + channelInitSingle.reference = + (ADC_Ref_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___referenceVoltage].NumericByRef().s4; + channelInitSingle.diff = + (AdcChannelMode)channelConfiguration[AdcChannelConfiguration::FIELD___channelMode].NumericByRef().s4 == + AdcChannelMode_Differential + ? true + : false; + + memcpy(adcInit, &channelInitSingle, sizeof(ADC_InitSingle_TypeDef)); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -16,20 +41,95 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_ NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + int channelNumber; + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + + // ADC related variables + ADC_TypeDef *adcDriver = NULL; + ADC_InitSingle_TypeDef channelInitSingle; + uint64_t samplesAccumulator = 0; + uint32_t averageCount; + uint32_t samplesCount; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + // OK to skip validation here because the channelNumber has been validated in the constructor + adcDefinition = AdcPortPinConfig[channelNumber]; + + // we should remove form the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch (adcDefinition.adcIndex) + { + +#if GECKO_USE_ADC0 + case 0: + adcDriver = ADC0; + break; +#endif + +#if GECKO_USE_ADC1 + case 1: + adcDriver = ADC1; + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get the average counter + averageCount = stack.Arg1().NumericByRef().s4; + + // sanity check (need to take at least one sample) + if (averageCount < 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + samplesCount = averageCount; + + // get a pointer to the channel AdcChannelConfiguration object instance + ParseAdcChannelConfig(pThis[FIELD___averageCount].Dereference(), &channelInitSingle); + + ADC_InitSingle(adcDriver, &channelInitSingle); + + while (samplesCount--) + { + // start the conversion + ADC_Start(adcDriver, adcStartSingle); + + // Wait for conversion to complete + while (ADC0->STATUS & ADC_STATUS_SINGLEACT) + ; + + // store sample + samplesAccumulator += ADC_DataSingleGet(adcDriver); + } + + // set the return result with the conversion value averaged from the accumulator + stack.SetResult_I4(samplesAccumulator / averageCount); NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID( + CLR_RT_StackFrame &stack) { + (void)stack; + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // left empty on purpose, nothing to do here - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP_NOLABEL(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 7e887b077e..b38abe3990 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -7,9 +7,22 @@ #include "nano_gg_adc_native.h" #include "nano_gg_adc_native_target.h" -#define ADC_FREQ 16000000 +#define ADC_IMPOSSIBLE_CLOCK 90000000UL -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame &stack ) +#if GECKO_USE_ADC0 +ADC_Init_TypeDef adc0Init; +bool adc0Initialized = false; +#endif +#if GECKO_USE_ADC1 +ADC_Init_TypeDef adc1Init; +bool adc1Initialized = false; +#endif + +// add typedef for AdcConfiguration to ease access and improve readability +typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcConfiguration AdcConfiguration; + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( + CLR_RT_StackFrame &stack) { (void)stack; @@ -20,17 +33,19 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP_NOLABEL(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); int channel; - NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; - ADC_Init_TypeDef adcInit; + NF_PAL_ADC_PORT_PIN_CHANNEL adcChannelDefinition; CMU_Clock_TypeDef adcClock; ADC_TypeDef *adcDriver = NULL; + ADC_Init_TypeDef *adcInit = NULL; + bool *adcInitialized = NULL; - adcInit = ADC_INIT_DEFAULT; + CLR_RT_HeapBlock *adcConfiguration; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -39,17 +54,26 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N // Get channel from argument channel = stack.Arg1().NumericByRef().s4; - adcDefinition = AdcPortPinConfig[channel]; + // sanity check for existing configuration + if (channel >= AdcChannelCount) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // grab ADC channel definition + adcChannelDefinition = AdcPortPinConfig[channel]; // we should remove from the build the ADC options that aren't implemented // plus we have to use the default to catch invalid ADC Ids - switch (adcDefinition.adcIndex) + switch (adcChannelDefinition.adcIndex) { #if GECKO_USE_ADC0 case 0: adcDriver = ADC0; adcClock = cmuClock_ADC0; + adcInit = &adc0Init; + adcInitialized = &adc0Initialized; break; #endif @@ -57,6 +81,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N case 1: adcDriver = ADC1; adcClock = cmuClock_ADC1; + adcInit = &adc1Init; + adcInitialized = &adc1Initialized; break; #endif @@ -64,21 +90,63 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // Enable ADC clock - CMU_ClockEnable(cmuClock_HFPER, true); - CMU_ClockEnable(adcClock, true); + // is this ADC already initialized? + if ( +#if GECKO_USE_ADC0 + (adcDriver == ADC0 && !adcInitialized) +#endif +#if GECKO_USE_ADC0 && GECKO_USE_ADC1 + || +#endif +#if GECKO_USE_ADC1 + (adcDriver == ADC1 && !adcInitialized) +#endif + ) + { + // get a pointer to the managed AdcConfiguration object instance + adcConfiguration = pThis[FIELD___acdConfiguration].Dereference(); + + // init with default values + *adcInit = ADC_INIT_DEFAULT; + + // now map the AdcConfiguration object to the native structure + adcInit->ovsRateSel = + (ADC_OvsRateSel_TypeDef)adcConfiguration[AdcConfiguration::FIELD___oversampleRate].NumericByRef().s4; + +#if defined(_ADC_CTRL_LPFMODE_MASK) + adcInit->lpfMode = + (ADC_LPFilter_TypeDef)adcConfiguration[AdcConfiguration::FIELD___lowpassFilterMode].NumericByRef().s4; +#endif - // Init to max ADC clock for Series 1 - adcInit.prescale = ADC_PrescaleCalc(ADC_FREQ, 0); - adcInit.timebase = ADC_TimebaseCalc(0); + adcInit->warmUpMode = + (ADC_Warmup_TypeDef)adcConfiguration[AdcConfiguration::FIELD___warmUpMode].NumericByRef().s4; + adcInit->tailgate = (bool)adcConfiguration[AdcConfiguration::FIELD___tailgating].NumericByRef().u1; - // start ADC - ADC_Init(adcDriver, &adcInit); + // Enable ADC clock + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(adcClock, true); + + // init to max possible ADC clock + adcInit->prescale = ADC_PrescaleCalc(ADC_IMPOSSIBLE_CLOCK, 0); + // let the drivers compute the appropriate value for the reference clock + adcInit->timebase = ADC_TimebaseCalc(0); + +#if defined(_ADC_CTRL_ADCCLKMODE_MASK) + adcInit->em2ClockConfig = adcEm2ClockOnDemand; +#endif + + // start ADC + ADC_Init(adcDriver, adcInit); + + // set ADC initialized flag + *adcInitialized = true; + } NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -87,7 +155,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeIsChannelModeSupported___BOOLEAN__I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -96,7 +165,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -105,7 +175,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeStartContinuousConversion___BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -114,7 +185,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStoptContinuousConversion___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeStoptContinuousConversion___BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -123,7 +195,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetLastContinuousSamples___SZARRAY_I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -132,7 +205,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastScanSampleForChannel___I4__I4( CLR_RT_StackFrame &stack ) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetLastScanSampleForChannel___I4__I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h index 15895ece24..40a908ad0e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h @@ -36,4 +36,14 @@ typedef struct extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; extern const int AdcChannelCount; +#if GECKO_USE_ADC0 +extern ADC_Init_TypeDef adc0Init; +extern bool adc0Initialized; +#endif +#if GECKO_USE_ADC1 +extern ADC_Init_TypeDef adc1Init; +extern bool adc1Initialized; +#endif + + #endif // SYS_DEV_ADC_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 7ee6d6a2c6..0c7e925eef 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -13,6 +13,7 @@ #include #include +#include // #if (HAL_USE_CAN == TRUE) // #include @@ -27,6 +28,10 @@ extern void DeInitPwm(); #endif +#if (GECKO_USE_ADC0 == TRUE) || (GECKO_USE_ADC1 == TRUE) +#include +#endif + // global mutex protecting the internal state of the interpreter, including event flags // mutex_t interpreterGlobalMutex; @@ -126,6 +131,12 @@ void nanoHAL_Initialize() #endif +#if GECKO_USE_ADC0 +adc0Initialized = false; +#endif +#if GECKO_USE_ADC1 +adc1Initialized = false; +#endif // #if (HAL_USE_UART == TRUE) // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) @@ -260,6 +271,15 @@ void nanoHAL_Uninitialize() nanoSPI_Uninitialize(); #endif +#if GECKO_USE_ADC0 +ADC_Reset(ADC0); +adc0Initialized = false; +#endif +#if GECKO_USE_ADC1 +ADC_Reset(ADC1); +adc1Initialized = false; +#endif + // #if (HAL_USE_UART == TRUE) // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) From 121b1c0185054e91c7b8f42c937b7dc0bcf44679 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Sep 2022 10:57:21 +0100 Subject: [PATCH 133/572] Fix assignments in Skyworks I2C --- ...ive_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp index 94a762365c..535a8801ec 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -139,7 +139,7 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 { I2C0_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); - if (I2C1_PAL.Configuration == NULL) + if (I2C0_PAL.Configuration == NULL) { NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); } @@ -150,7 +150,7 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 ConfigPins_I2C0(); I2C0_PAL.Configuration->port = I2C0; - palI2c = I2C1_PAL; + palI2c = &I2C0_PAL; // increase device counter I2C0_DeviceCounter++; @@ -175,7 +175,7 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 ConfigPins_I2C1(); I2C1_PAL.Configuration->port = I2C1; - palI2c = I2C1_PAL; + palI2c = &I2C1_PAL; // increase device counter I2C1_DeviceCounter++; From d80020bf8240850d8a67adc5f36164e15354e1b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Sep 2022 12:13:54 +0100 Subject: [PATCH 134/572] Update declaration of Gecko ADC assembly - Update code accordingly. --- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp | 4 ++-- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h | 5 ++--- ...gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 4 ++-- ...adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 2 +- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index 6bfbb5f950..f07a0b0149 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -17,7 +17,7 @@ static const CLR_RT_MethodHandler method_lookup[] = Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4, NULL, NULL, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID, NULL, NULL, @@ -80,7 +80,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0x252EAE1B, + 0x175512A5, method_lookup, { 100, 1, 0, 0 } }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index 3b3f56e326..8240ccd4d4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -129,10 +129,9 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel static const int FIELD___disposed = 3; static const int FIELD___channelNumber = 4; static const int FIELD___adcChannelConfiguration = 5; - static const int FIELD___averageCount = 6; NANOCLR_NATIVE_DECLARE(get_LastContinuousValue___I4); - NANOCLR_NATIVE_DECLARE(NativeReadValue___I4); + NANOCLR_NATIVE_DECLARE(NativeReadValue___I4__I4); NANOCLR_NATIVE_DECLARE(NativeDisposeChannel___VOID); //--// @@ -167,7 +166,7 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController static const int FIELD___scanChannels = 2; static const int FIELD___averageCount = 3; static const int FIELD___continuousSamplingStarted = 4; - static const int FIELD___acdConfiguration = 5; + static const int FIELD___adcConfiguration = 5; NANOCLR_NATIVE_DECLARE(NativeInit___VOID); NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 6f9b180558..81c485e493 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -41,7 +41,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_ NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -99,7 +99,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati samplesCount = averageCount; // get a pointer to the channel AdcChannelConfiguration object instance - ParseAdcChannelConfig(pThis[FIELD___averageCount].Dereference(), &channelInitSingle); + ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitSingle); ADC_InitSingle(adcDriver, &channelInitSingle); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index b38abe3990..4c3949b6a6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -104,7 +104,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N ) { // get a pointer to the managed AdcConfiguration object instance - adcConfiguration = pThis[FIELD___acdConfiguration].Dereference(); + adcConfiguration = pThis[FIELD___adcConfiguration].Dereference(); // init with default values *adcInit = ADC_INIT_DEFAULT; From 7d3048fe8843a54f047cb6ddd8a59bbb2653443d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 00:14:11 +0100 Subject: [PATCH 135/572] Implementation for 1-Wire using SL stream for UART --- CMakeLists.txt | 2 + .../_common/autogen/sl_iostream_handles.c | 9 +- .../sl_iostream_init_usart_instances.c | 311 +++++---- .../sl_iostream_init_usart_instances.h | 15 +- ...noFramework_Device_OneWire_OneWireHost.cpp | 619 +++++++++++------- .../nf_dev_onewire_target.h | 63 +- .../SiliconLabs/_nanoCLR/target_platform.h.in | 2 +- 7 files changed, 641 insertions(+), 380 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 3e8d813de3..162dcc41ba 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -580,8 +580,10 @@ endif() if(API_nanoFramework.Device.OneWire) set(HAL_USE_STM32_ONEWIRE_OPTION TRUE CACHE INTERNAL "HAL STM32_ONEWIRE for nanoFramework.Device.OneWire") + set(HAL_USE_ONEWIRE_OPTION TRUE CACHE INTERNAL "HAL ONEWIRE for nanoFramework.Device.OneWire") else() set(HAL_USE_STM32_ONEWIRE_OPTION FALSE CACHE INTERNAL "HAL STM32_ONEWIRE for nanoFramework.Device.OneWire") + set(HAL_USE_ONEWIRE_OPTION FALSE CACHE INTERNAL "HAL ONEWIRE for nanoFramework.Device.OneWire") endif() ################################################################################# diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c index fee0efcc62..b89c50f299 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c @@ -1,11 +1,18 @@ #include "sl_iostream.h" #include "sl_iostream_handles.h" #include "string.h" +#include const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { +#if HAL_WP_USE_SERIAL == TRUE &sl_iostream_instance_vcom_info, - +#endif + +#if HAL_USE_ONEWIRE == TRUE + &sl_iostream_instance_onewire_info, +#endif + }; const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index cf1c75e27b..3e4f938c5e 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -8,8 +8,16 @@ #include "sl_iostream.h" #include "sl_iostream_uart.h" #include "sl_iostream_usart.h" -// Include instance config +#include + +// Include instance config +#if HAL_WP_USE_SERIAL == TRUE #include "sl_iostream_usart_vcom_config.h" +#endif +#if HAL_USE_ONEWIRE == TRUE +#include "sl_iostream_usart_onewire_config.h" +#endif + #include // need to define this here to avoid compiler warning (error) @@ -19,204 +27,265 @@ // Baudrate for the serial port // // Override default setting from board if build option is set // //////////////////////////////////////////////////////////////// -#ifdef TARGET_SERIAL_BAUDRATE +#ifdef TARGET_SERIAL_BAUDRATE #undef SL_IOSTREAM_USART_VCOM_BAUDRATE #define SL_IOSTREAM_USART_VCOM_BAUDRATE TARGET_SERIAL_BAUDRATE #endif -// MACROs for generating name and IRQ handler function -#define SL_IOSTREAM_USART_CONCAT_PASTER(first, second, third) first ## second ## third - - - +// MACROs for generating name and IRQ handler function +#define SL_IOSTREAM_USART_CONCAT_PASTER(first, second, third) first##second##third -#define SL_IOSTREAM_USART_TX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQn) -#define SL_IOSTREAM_USART_RX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQn) -#define SL_IOSTREAM_USART_TX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQHandler) -#define SL_IOSTREAM_USART_RX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQHandler) +#define SL_IOSTREAM_USART_TX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQn) +#define SL_IOSTREAM_USART_RX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQn) +#define SL_IOSTREAM_USART_TX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQHandler) +#define SL_IOSTREAM_USART_RX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQHandler) -#define SL_IOSTREAM_USART_CLOCK_REF(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(cmuClock_, USART, periph_nbr) +#define SL_IOSTREAM_USART_CLOCK_REF(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(cmuClock_, USART, periph_nbr) -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) // EM Events -#define SLEEP_EM_EVENT_MASK ( SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ - | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ - | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ - | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) +#define SLEEP_EM_EVENT_MASK \ + (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 | \ + SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) #endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) -static void events_handler(sl_power_manager_em_t from, - sl_power_manager_em_t to); -static sl_power_manager_em_transition_event_info_t events_info = -{ - .event_mask = SLEEP_EM_EVENT_MASK, - .on_event = events_handler, +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +static void events_handler(sl_power_manager_em_t from, sl_power_manager_em_t to); +static sl_power_manager_em_transition_event_info_t events_info = { + .event_mask = SLEEP_EM_EVENT_MASK, + .on_event = events_handler, }; static sl_power_manager_em_transition_event_handle_t events_handle; #endif - +#if HAL_WP_USE_SERIAL == TRUE sl_status_t sl_iostream_usart_init_vcom(void); +#endif - -// Instance(s) handle and context variable +// Instance(s) handle and context variable +#if HAL_WP_USE_SERIAL == TRUE static sl_iostream_uart_t sl_iostream_vcom; sl_iostream_t *sl_iostream_vcom_handle = &sl_iostream_vcom.stream; sl_iostream_uart_t *sl_iostream_uart_vcom_handle = &sl_iostream_vcom; -static sl_iostream_usart_context_t context_vcom; -static uint8_t rx_buffer_vcom[SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE]; +static sl_iostream_usart_context_t context_vcom; +static uint8_t rx_buffer_vcom[SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE]; sl_iostream_instance_info_t sl_iostream_instance_vcom_info = { - .handle = &sl_iostream_vcom.stream, - .name = "vcom", - .type = SL_IOSTREAM_TYPE_UART, - .periph_id = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, - .init = sl_iostream_usart_init_vcom, + .handle = &sl_iostream_vcom.stream, + .name = "vcom", + .type = SL_IOSTREAM_TYPE_UART, + .periph_id = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, + .init = sl_iostream_usart_init_vcom, }; - - sl_status_t sl_iostream_usart_init_vcom(void) { - sl_status_t status; - USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; - init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; - init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; - init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; + sl_status_t status; + USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; + init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; + init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; + init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; #if (_SILICON_LABS_32B_SERIES > 0) #if (SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE != uartFlowControlSoftware) - init_vcom.hwFlowControl = SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE; + init_vcom.hwFlowControl = SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE; #else - init_vcom.hwFlowControl = usartHwFlowControlNone; + init_vcom.hwFlowControl = usartHwFlowControlNone; #endif #endif - sl_iostream_usart_config_t config_vcom = { - .usart = SL_IOSTREAM_USART_VCOM_PERIPHERAL, - .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), - .tx_port = SL_IOSTREAM_USART_VCOM_TX_PORT, - .tx_pin = SL_IOSTREAM_USART_VCOM_TX_PIN, - .rx_port = SL_IOSTREAM_USART_VCOM_RX_PORT, - .rx_pin = SL_IOSTREAM_USART_VCOM_RX_PIN, + sl_iostream_usart_config_t config_vcom = { + .usart = SL_IOSTREAM_USART_VCOM_PERIPHERAL, + .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .tx_port = SL_IOSTREAM_USART_VCOM_TX_PORT, + .tx_pin = SL_IOSTREAM_USART_VCOM_TX_PIN, + .rx_port = SL_IOSTREAM_USART_VCOM_RX_PORT, + .rx_pin = SL_IOSTREAM_USART_VCOM_RX_PIN, #if (_SILICON_LABS_32B_SERIES > 0) #if defined(SL_IOSTREAM_USART_VCOM_CTS_PORT) - .cts_port = SL_IOSTREAM_USART_VCOM_CTS_PORT, - .cts_pin = SL_IOSTREAM_USART_VCOM_CTS_PIN, + .cts_port = SL_IOSTREAM_USART_VCOM_CTS_PORT, + .cts_pin = SL_IOSTREAM_USART_VCOM_CTS_PIN, #endif #if defined(SL_IOSTREAM_USART_VCOM_RTS_PORT) - .rts_port = SL_IOSTREAM_USART_VCOM_RTS_PORT, - .rts_pin = SL_IOSTREAM_USART_VCOM_RTS_PIN, + .rts_port = SL_IOSTREAM_USART_VCOM_RTS_PORT, + .rts_pin = SL_IOSTREAM_USART_VCOM_RTS_PIN, #endif #endif #if defined(GPIO_USART_ROUTEEN_TXPEN) - .usart_index = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, + .usart_index = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, #elif defined(USART_ROUTEPEN_RXPEN) - .usart_tx_location = SL_IOSTREAM_USART_VCOM_TX_LOC, - .usart_rx_location = SL_IOSTREAM_USART_VCOM_RX_LOC, + .usart_tx_location = SL_IOSTREAM_USART_VCOM_TX_LOC, + .usart_rx_location = SL_IOSTREAM_USART_VCOM_RX_LOC, #if defined(SL_IOSTREAM_USART_VCOM_CTS_PORT) - .usart_cts_location = SL_IOSTREAM_USART_VCOM_CTS_LOC, + .usart_cts_location = SL_IOSTREAM_USART_VCOM_CTS_LOC, #endif #if defined(SL_IOSTREAM_USART_VCOM_RTS_PORT) - .usart_rts_location = SL_IOSTREAM_USART_VCOM_RTS_LOC, + .usart_rts_location = SL_IOSTREAM_USART_VCOM_RTS_LOC, #endif #else - .usart_location = SL_IOSTREAM_USART_VCOM_ROUTE_LOC, -#endif - }; - sl_iostream_uart_config_t uart_config_vcom = { - .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), - .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), - .rx_buffer = rx_buffer_vcom, - .rx_buffer_length = SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE, - .lf_to_crlf = SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF, - .rx_when_sleeping = SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, + .usart_location = SL_IOSTREAM_USART_VCOM_ROUTE_LOC, +#endif + }; + sl_iostream_uart_config_t uart_config_vcom = { + .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .rx_buffer = rx_buffer_vcom, + .rx_buffer_length = SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE, + .lf_to_crlf = SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF, + .rx_when_sleeping = SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, #if defined(SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE) #if (SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE == uartFlowControlSoftware) - .sw_flow_control = true, + .sw_flow_control = true, #else - .sw_flow_control = false, + .sw_flow_control = false, #endif #else - .sw_flow_control = false, -#endif - }; - // Instantiate usart instance - status = sl_iostream_usart_init(&sl_iostream_vcom, - &uart_config_vcom, - &init_vcom, - &config_vcom, - &context_vcom); - EFM_ASSERT(status == SL_STATUS_OK); - - return status; + .sw_flow_control = false, +#endif + }; + // Instantiate usart instance + status = sl_iostream_usart_init(&sl_iostream_vcom, &uart_config_vcom, &init_vcom, &config_vcom, &context_vcom); + EFM_ASSERT(status == SL_STATUS_OK); + + return status; } +#endif +#if HAL_USE_ONEWIRE == TRUE +sl_status_t sl_iostream_usart_init_onewire(void) +{ + sl_status_t status; + USART_InitAsync_TypeDef init_onewire = USART_INITASYNC_DEFAULT; + init_onewire.baudrate = SL_IOSTREAM_USART_ONEWIRE_BAUDRATE; + init_onewire.parity = SL_IOSTREAM_USART_ONEWIRE_PARITY; + init_onewire.stopbits = SL_IOSTREAM_USART_ONEWIRE_STOP_BITS; +#if (_SILICON_LABS_32B_SERIES > 0) +#if (SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE != uartFlowControlSoftware) + init_onewire.hwFlowControl = SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE; +#else + init_onewire.hwFlowControl = usartHwFlowControlNone; +#endif +#endif + sl_iostream_usart_config_t config_onewire = { + .usart = SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL, + .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO), + .tx_port = SL_IOSTREAM_USART_ONEWIRE_TX_PORT, + .tx_pin = SL_IOSTREAM_USART_ONEWIRE_TX_PIN, + .rx_port = SL_IOSTREAM_USART_ONEWIRE_RX_PORT, + .rx_pin = SL_IOSTREAM_USART_ONEWIRE_RX_PIN, +#if (_SILICON_LABS_32B_SERIES > 0) +#if defined(SL_IOSTREAM_USART_ONEWIRE_CTS_PORT) + .cts_port = SL_IOSTREAM_USART_ONEWIRE_CTS_PORT, + .cts_pin = SL_IOSTREAM_USART_ONEWIRE_CTS_PIN, +#endif +#if defined(SL_IOSTREAM_USART_ONEWIRE_RTS_PORT) + .rts_port = SL_IOSTREAM_USART_ONEWIRE_RTS_PORT, + .rts_pin = SL_IOSTREAM_USART_ONEWIRE_RTS_PIN, +#endif +#endif +#if defined(GPIO_USART_ROUTEEN_TXPEN) + .usart_index = SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO, +#elif defined(USART_ROUTEPEN_RXPEN) + .usart_tx_location = SL_IOSTREAM_USART_ONEWIRE_TX_LOC, + .usart_rx_location = SL_IOSTREAM_USART_ONEWIRE_RX_LOC, +#if defined(SL_IOSTREAM_USART_ONEWIRE_CTS_PORT) + .usart_cts_location = SL_IOSTREAM_USART_ONEWIRE_CTS_LOC, +#endif +#if defined(SL_IOSTREAM_USART_ONEWIRE_RTS_PORT) + .usart_rts_location = SL_IOSTREAM_USART_ONEWIRE_RTS_LOC, +#endif +#else + .usart_location = SL_IOSTREAM_USART_ONEWIRE_ROUTE_LOC, +#endif + }; + sl_iostream_uart_config_t uart_config_onewire = { + .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO), + .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO), + .rx_buffer = rx_buffer_onewire, + .rx_buffer_length = SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE, + .lf_to_crlf = SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF, + .rx_when_sleeping = SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, +#if defined(SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE) +#if (SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE == uartFlowControlSoftware) + .sw_flow_control = true, +#else + .sw_flow_control = false, +#endif +#else + .sw_flow_control = false, +#endif + }; + // Instantiate usart instance + status = sl_iostream_usart_init( + &sl_iostream_onewire, + &uart_config_onewire, + &init_onewire, + &config_onewire, + &context_onewire); + EFM_ASSERT(status == SL_STATUS_OK); + + return status; +} + +#endif void sl_iostream_usart_init_instances(void) { -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) - // Enable power manager notifications - sl_power_manager_subscribe_em_transition_event(&events_handle, &events_info); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) + // Enable power manager notifications + sl_power_manager_subscribe_em_transition_event(&events_handle, &events_info); #endif - // Instantiate usart instance(s) - - sl_iostream_usart_init_vcom(); - +// Instantiate usart instance(s) +#if HAL_WP_USE_SERIAL == TRUE + sl_iostream_usart_init_vcom(); +#endif } - // VCOM IRQ Handler void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) { - sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); + sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); } void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) { - sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); + sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); } - - #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - + sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void) { - return sl_iostream_uart_sleep_on_isr_exit(&sl_iostream_vcom); + return sl_iostream_uart_sleep_on_isr_exit(&sl_iostream_vcom); } #endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) -static void events_handler(sl_power_manager_em_t from, - sl_power_manager_em_t to) +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +static void events_handler(sl_power_manager_em_t from, sl_power_manager_em_t to) { - uint32_t out; - if (((from == SL_POWER_MANAGER_EM2) - || (from == SL_POWER_MANAGER_EM3)) - && ((to == SL_POWER_MANAGER_EM1) - || (to == SL_POWER_MANAGER_EM0))) { - - // Wake the USART Tx pin back up - out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); - GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); - - } else if (((to == SL_POWER_MANAGER_EM2) - || (to == SL_POWER_MANAGER_EM3)) - && ((from == SL_POWER_MANAGER_EM1) - || (from == SL_POWER_MANAGER_EM0))) { - - // Sleep the USART Tx pin on series 2 devices to save energy - out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); - GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); - - } + uint32_t out; + if (((from == SL_POWER_MANAGER_EM2) || (from == SL_POWER_MANAGER_EM3)) && + ((to == SL_POWER_MANAGER_EM1) || (to == SL_POWER_MANAGER_EM0))) + { + + // Wake the USART Tx pin back up + out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); + GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); + } + else if ( + ((to == SL_POWER_MANAGER_EM2) || (to == SL_POWER_MANAGER_EM3)) && + ((from == SL_POWER_MANAGER_EM1) || (from == SL_POWER_MANAGER_EM0))) + { + + // Sleep the USART Tx pin on series 2 devices to save energy + out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); + GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); + } } #endif // implementation required (even if empty) to keep debugger happy void sli_iostream_on_uart_rx(sl_iostream_t *handle) { - (void)handle; + (void)handle; } diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h index 3c31aabb4a..713906bf87 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h @@ -8,14 +8,22 @@ #endif #include "sl_iostream.h" #include "sl_iostream_uart.h" +#include + #ifdef __cplusplus extern "C" { #endif - +#if HAL_WP_USE_SERIAL == TRUE extern sl_iostream_t *sl_iostream_vcom_handle; extern sl_iostream_uart_t *sl_iostream_uart_vcom_handle; extern sl_iostream_instance_info_t sl_iostream_instance_vcom_info; +#endif +#if HAL_USE_ONEWIRE == TRUE +extern sl_iostream_t *sl_iostream_onewire_handle; +extern sl_iostream_uart_t *sl_iostream_uart_onewire_handle; +extern sl_iostream_instance_info_t sl_iostream_instance_onewire_info; +#endif // Initialize only iostream usart instance(s) @@ -23,7 +31,12 @@ void sl_iostream_usart_init_instances(void); #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#if HAL_WP_USE_SERIAL == TRUE sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void); +#endif +#if HAL_USE_ONEWIRE == TRUE +sl_power_manager_on_isr_exit_t sl_iostream_usart_onewire_sleep_on_isr_exit(void); +#endif #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index a6ae6ff30b..ec8bd91eb9 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -5,6 +5,9 @@ #include "nf_dev_onewire_target.h" +///////////////////// +// 1-Wire API code // +///////////////////// // struct for working threads static OneWireFindStruct FindStruct; @@ -18,64 +21,21 @@ static uint8_t SerialNum[8]; // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; -// working thread to execute long running 1-Wire operations -static thread_t *OneWireWorkingThread; - - -void IRAM_ATTR oneWireStop() +void oneWireStop() { // stop UART - uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); + // TODO + // uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); // driver is stopped DriverState = ONEWIRE_STOP; } -HRESULT IRAM_ATTR oneWireInit() +HRESULT oneWireInit() { DriverState = ONEWIRE_STOP; - uart_config_t uart_config = { - .baud_rate = 115200, - .data_bits = UART_DATA_8_BITS, - .parity = UART_PARITY_DISABLE, - .stop_bits = UART_STOP_BITS_1, - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, - .rx_flow_ctrl_thresh = 0, - .use_ref_tick = false, - }; - - // get GPIO pins configured for UART assigned to 1-Wire - // need to subtract one to get the correct index of UART in mapped device pins - int txPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, NF_ONEWIRE_ESP32_UART_NUM, Esp32SerialPin_Tx); - int rxPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, NF_ONEWIRE_ESP32_UART_NUM, Esp32SerialPin_Rx); - - // check if TX, RX pins have been previously set - if (txPin == UART_PIN_NO_CHANGE || rxPin == UART_PIN_NO_CHANGE) - { - return CLR_E_PIN_UNAVAILABLE; - } - - // configure GPIO and UART - if (gpio_set_direction(gpio_num_t(txPin), GPIO_MODE_OUTPUT_OD) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } - - if (uart_param_config(NF_ONEWIRE_ESP32_UART_NUM, &uart_config) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } - - if (uart_set_pin(NF_ONEWIRE_ESP32_UART_NUM, txPin, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } - - if (uart_driver_install(NF_ONEWIRE_ESP32_UART_NUM, 256, 256, 0, NULL, ESP_INTR_FLAG_IRAM) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } + sl_iostream_usart_init_onewire(); // driver need to be deleted on soft reboot HAL_AddSoftRebootHandler(oneWireStop); @@ -85,14 +45,14 @@ HRESULT IRAM_ATTR oneWireInit() return S_OK; } - uint8_t oneWireTouchReset(void) { char reset = 0xF0; uint8_t presence; // flush DMA buffer to ensure cache coherency - uart_flush(NF_ONEWIRE_ESP32_UART_NUM); + // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 9600); @@ -106,273 +66,493 @@ uint8_t oneWireTouchReset(void) return (presence != reset); } -//////////////////////////////////////// -// struct for working threads -OneWireFindStruct FindStruct; - -// ChibiOS OneWire working thread -static THD_FUNCTION(OneWireFindFirstWorkingThread, arg) +bool oneWireTouchBit(bool sendbit) { - msg_t deviceFound; + // need to send 1-Wire write 1 or 0 according to sendbit + char write = sendbit ? IWIRE_WR1 : IWIRE_WR0; + uint8_t reply; - OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; - - deviceFound = oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly); + // flush DMA buffer to ensure cache coherency + // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - // fire event for 1-Wire operarion completed - Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&write, 1); + uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &reply, 1, 20 / portTICK_RATE_MS); - chThdExit(deviceFound); + // interpret 1-Wire reply + return (reply == IWIRE_RD); } -static THD_FUNCTION(OneWireFindNextWorkingThread, arg) +uint8_t oneWireTouchByte(uint8_t sendbyte) { - msg_t deviceFound; + uint8_t send_mask = 0x01, result = 0; + uint8_t i = 0; + char writeBuffer[8]; + uint8_t readBuffer[8]; - OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; + // send byte + while (send_mask) + { + writeBuffer[i] = (sendbyte & send_mask) ? IWIRE_WR1 : IWIRE_WR0; + i++; + // rotates the position mask transmit bit + send_mask <<= 1; + }; + + // flush DMA buffer to ensure cache coherency + // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - deviceFound = oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); + uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)writeBuffer, 8); + uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, readBuffer, 8, 20 / portTICK_RATE_MS); + + // reset send mask to interpret the reply + send_mask = 0x01; + + for (i = 0; i < 8; i++) + { + if (readBuffer[i] == IWIRE_RD) + { + result |= send_mask; + } - // fire event for 1-Wire operarion completed - Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + send_mask <<= 1; + } - chThdExit(deviceFound); + return result; } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchReset___BOOLEAN(CLR_RT_StackFrame &stack) +void oneWireAquire() { - NANOCLR_HEADER(); - - volatile bool reset = oneWireTouchReset(); - stack.SetResult_Boolean(reset); +} - NANOCLR_NOCLEANUP_NOLABEL(); +void oneWireRelease() +{ } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchBit___BOOLEAN__BOOLEAN( - CLR_RT_StackFrame &stack) +// compute CRC8 using running algorith (slower but saves FLASH) +uint8_t doCrc8(uint8_t oldCrc, uint8_t x) { - NANOCLR_HEADER(); + uint8_t crc = oldCrc; - bool value = stack.Arg1().NumericByRefConst().u1 != 0; + for (uint8_t i = 8; i; i--) + { + uint8_t mix = (crc ^ x) & 0x01; + crc >>= 1; + if (mix) + crc ^= 0x8C; + x >>= 1; + } + + return crc; +} - stack.SetResult_Boolean(oneWireTouchBit(value)); +/******************************************************************************* +** NAME: oneWireSerialNum ************************************************** +******************************************************************************** + +DESCRIPTION: + // The 'oneWireSerialNum' function either reads or sets the SerialNum buffer + // that is used in the search functions 'owFirst' and 'owNext'. + // This function contains two parameters, 'serialnum_buf' is a pointer + // to a buffer provided by the caller. 'serialnum_buf' should point to + // an array of 8 unsigned chars. The second parameter is a flag called + // 'do_read' that is TRUE (1) if the operation is to read and FALSE + // (0) if the operation is to set the internal SerialNum buffer from + // the data in the provided buffer. + // + // 'serialnum_buf' - buffer to that contains the serial number to set + // when do_read = FALSE (0) and buffer to get the serial + // number when do_read = TRUE (1). + // 'do_read' - flag to indicate reading (1) or setting (0) the current + // serial number. + // + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +void oneWireSerialNum(uint8_t *serialnum_buf, uint8_t do_read) +{ + uint8_t i; - NANOCLR_NOCLEANUP_NOLABEL(); + //-------------------------------------------------// + // read the internal buffer and place in 'serialnum_buf' + if (do_read) + { + for (i = 0; i < 8; i++) + { + serialnum_buf[i] = SerialNum[i]; + } + } + // set the internal buffer from the data in 'serialnum_buf' + else + { + for (i = 0; i < 8; i++) + { + SerialNum[i] = serialnum_buf[i]; + } + } } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchByte___U1__U1(CLR_RT_StackFrame &stack) +/******************************************************************************* +** NAME: oneWireFindNext ******************************************************* +********************************************************************************/ +// The 'oneWireFindNext' function does a general search. +// This function continues from the previos search state. The search state +// can be reset by using the 'oneWireFindFirst' function. +// This function contains one parameter 'alarmOnly'. +// When 'alarmOnly' is TRUE (1) the find alarm command +// 0xEC is sent instead of the normal search command 0xF0. +// Using the find alarm command 0xEC will limit the search to only +// 1-Wire devices that are in an 'alarm' state. +// +// 'doReset' - TRUE (1) perform reset before search, FALSE (0) do not +// perform reset before search. +// 'alarmOnly' - TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0 +// +// Returns: TRUE (1) : when a 1-Wire device was found and it's +// Serial Number placed in the global SerialNum +// FALSE (0): when no new device was found. Either the +// last search was the last device or there +// are no devices on the 1-Wire Net. +bool oneWireFindNext(bool doReset, bool alarmOnly) { - NANOCLR_HEADER(); + uint8_t romBitIndex = 1; + uint8_t romByteIndex = 0; + uint8_t bitMask = 1; + uint8_t attempt = 0; + uint8_t discrepMarker = 0; + bool outBit = 0; + bool result = FALSE; + uint8_t lastcrc8 = 0; + + // if the last call was the last one + if (LastDevice) + { + // reset the search + LastDiscrepancy = 0; + LastDevice = FALSE; + LastFamilyDiscrepancy = 0; - uint8_t value = (uint8_t)stack.Arg1().NumericByRefConst().u1; - uint8_t result = oneWireTouchByte(value); - stack.SetResult_U1(result); + return FALSE; + } - NANOCLR_NOCLEANUP_NOLABEL(); + // check if reset bus was requested + if (doReset) + { + // reset the 1-Wire bus + // if there is no presence pulse there is nothing to do here, return FALSE + if (!oneWireTouchReset()) + { + // reset the search + LastDiscrepancy = 0; + LastFamilyDiscrepancy = 0; + return FALSE; + } + } + + // send search command + if (alarmOnly) + { + // conditional search command (devices in alarm condition) + oneWireTouchByte(COND_SEARCH_ROM); + } + else + { + // ROM search command + oneWireTouchByte(SEARCH_ROM); + } + + do + { + attempt = 0; + + if (oneWireTouchBit(TRUE) == 1) + { + attempt = 2; + } + + if (oneWireTouchBit(TRUE) == 1) + { + attempt |= 1; + } + + if (attempt == 3) + { + // no devices present, done here + break; + } + else + { + if (attempt > 0) + { + // all connected devices reply with 0 or 1 + // write bit to perform search + outBit = attempt >> 1; + } + else + { + if (romBitIndex < LastDiscrepancy) + { + outBit = ((SerialNum[romByteIndex] & bitMask) > 0); + } + else + { + // set to 1 if it's the same, otherwise 0 + outBit = (romBitIndex == LastDiscrepancy); + } + + // on 0 record position on bitMask + if (outBit == 0) + { + discrepMarker = romBitIndex; + } + } + + // isolate bit in ROM[n] with bitMask + if (outBit == 1) + { + SerialNum[romByteIndex] |= bitMask; + } + else + { + SerialNum[romByteIndex] &= ~bitMask; + } + + // ROM search write + oneWireTouchBit(outBit); + + romBitIndex++; + + bitMask = bitMask << 1; + + // if the mask has reached 0 then go for a new ROM + if (bitMask == 0) + { + // reset mask and perform CRC8 + lastcrc8 = doCrc8(lastcrc8, SerialNum[romByteIndex]); + + romByteIndex++; + bitMask++; + } + } + + } while (romByteIndex < 8); // loop until we have all ROM bytes + + if ((romBitIndex < 65) || (lastcrc8 != 0)) + { + // search was unsuccessful reset the last discrepancy + LastDiscrepancy = 0; + } + else + { + // search was successful: set last discrepancy, device and result + LastDiscrepancy = discrepMarker; + LastDevice = (LastDiscrepancy == 0); + + // search isn't completed there are more devices present in the bus + result = TRUE; + } + + return result; } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::WriteByte___U1__U1(CLR_RT_StackFrame &stack) +/******************************************************************************* +** NAME: oneWireFindFirst ****************************************************** +********************************************************************************/ +// The 'oneWireFindFirst' finds the first device on the 1-Wire Net. +// This function contains one parameter 'alarmOnly'. When +// 'alarmOnly' is TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0. +// Using the find alarm command 0xEC will limit the search to only +// 1-Wire devices that are in an 'alarm' state. +// +// 'portnum' - number 0 to MAX_PORTNUM-1. This number is provided to +// indicate the symbolic port number. +// 'doReset' - TRUE (1) perform reset before search, FALSE (0) do not +// perform reset before search. +// 'alarmOnly' - TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0 +// +// Returns: TRUE (1) : when a 1-Wire device was found and it's +// Serial Number placed in the global SerialNum +// FALSE (0): There are no devices on the 1-Wire Net. +bool oneWireFindFirst(bool doReset, bool alarmOnly) { - NANOCLR_HEADER(); + // reset the search state + LastDiscrepancy = 0; + LastDevice = FALSE; + LastFamilyDiscrepancy = 0; - uint8_t cmd = (uint8_t)stack.Arg1().NumericByRefConst().u1; - uint8_t result = oneWireWriteByte(cmd); - stack.SetResult_U1(result); + // clear serial number buffer for new search + memset(SerialNum, 0, 8); - NANOCLR_NOCLEANUP_NOLABEL(); + // Call Next and return it's return value; + return oneWireFindNext(doReset, alarmOnly); } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::ReadByte___U1(CLR_RT_StackFrame &stack) +// OneWire Find First/Next working thread +static void OneWireFindWorkingThread(void *pvParameters) { - NANOCLR_HEADER(); + OneWireFindStruct *findStruct = (OneWireFindStruct *)pvParameters; - uint8_t result = oneWireReadByte(); - stack.SetResult_U1(result); + OneWireOperationResult = findStruct->FindFirst ? oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly) + : oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); - NANOCLR_NOCLEANUP_NOLABEL(); + // fire event for 1-Wire operation completed + xTaskNotifyGive(WaitingTask); + vTaskDelete(NULL); } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( - CLR_RT_StackFrame &stack) +HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) { - NANOCLR_HEADER(); - uint8_t *serialNumberPointer; - msg_t oneWireOperationResult = FALSE; - CLR_RT_HeapBlock hbTimeout; CLR_INT64 *timeout; - bool eventResult = true; + TaskHandle_t task; + HRESULT result; // set an infinite timeout to wait forever for the operation to complete // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below hbTimeout.SetInteger((CLR_INT64)-1); - NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + result = stack.SetupTimeoutFromTicks(hbTimeout, timeout); + + if (result != S_OK) + { + return result; + } // this is going to be used to check for the right event in case of simultaneous 1-Wire operations if (stack.m_customState == 1) { FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + FindStruct.FindFirst = findFirst; // because the 1-Wire bus is shared, acquire the module - oneWireAcquireModule(); + oneWireAquire(); // spawn working thread to perform the 1-Wire operations - OneWireWorkingThread = chThdCreateFromHeap( - NULL, - THD_WORKING_AREA_SIZE(256), - "OWWT", - NORMALPRIO, - OneWireFindFirstWorkingThread, - &FindStruct); + WaitingTask = xTaskGetCurrentTaskHandle(); + xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); // bump custom state stack.m_customState = 2; } - while (eventResult) - { - if (OneWireWorkingThread->state == CH_STATE_FINAL) - { - // OneWire working thread is now complete - break; - } + // wait for 1-Wire operation complete + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); - // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); - } + oneWireRelease(); - if (eventResult) + // get the result from the working thread execution + if (OneWireOperationResult) { - // event occurred - - // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the - // heap, otherwise it won't be returned - oneWireOperationResult = chThdWait(OneWireWorkingThread); - - oneWireReleaseModule(); + // update serialNumber field - // get the result from the working thread execution - if (oneWireOperationResult) + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + if (pThis == NULL) { - // if a device was found update serialNumber field in managed class - - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); + return CLR_E_NULL_REFERENCE; + } - // get a pointer to the serial number field in the OneWireController instance - CLR_RT_HeapBlock_Array *serialNumberField = pThis[FIELD___serialNumber].DereferenceArray(); + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array *serialNumberField = + pThis[Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FIELD___serialNumber] + .DereferenceArray(); - _ASSERTE(serialNumberField->m_numOfElements == 8); + _ASSERTE(serialNumberField->m_numOfElements == 8); - // get a pointer to the first element of the byte array - serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); - oneWireSerialNum(serialNumberPointer, TRUE); - } + oneWireSerialNum(serialNumberPointer, TRUE); } // pop timeout heap block from stack stack.PopValue(); // set result - stack.SetResult_Boolean(oneWireOperationResult); + stack.SetResult_Boolean(OneWireOperationResult); - NANOCLR_NOCLEANUP(); + return S_OK; } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( - CLR_RT_StackFrame &stack) +////////////////////////// +// managed library code // +////////////////////////// + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchReset___BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - uint8_t *serialNumberPointer; - msg_t oneWireOperationResult = FALSE; + stack.SetResult_Boolean(oneWireTouchReset()); - CLR_RT_HeapBlock hbTimeout; - CLR_INT64 *timeout; - bool eventResult = true; + NANOCLR_NOCLEANUP_NOLABEL(); +} - // set an infinite timeout to wait forever for the operation to complete - // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below - hbTimeout.SetInteger((CLR_INT64)-1); - NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchBit___BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // this is going to be used to check for the right event in case of simultaneous 1-Wire operations - if (stack.m_customState == 1) - { - FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; - FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + stack.SetResult_Boolean(oneWireTouchBit(stack.Arg1().NumericByRefConst().u1 != 0)); - // because the 1-Wire bus is shared, acquire the module - oneWireAcquireModule(); + NANOCLR_NOCLEANUP_NOLABEL(); +} - // spawn working thread to perform the 1-Wire operations - OneWireWorkingThread = chThdCreateFromHeap( - NULL, - THD_WORKING_AREA_SIZE(256), - "OWWT", - NORMALPRIO, - OneWireFindNextWorkingThread, - &FindStruct); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchByte___U1__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // bump custom state - stack.m_customState = 2; - } + stack.SetResult_U1(oneWireTouchByte((uint8_t)stack.Arg1().NumericByRefConst().u1)); - while (eventResult) - { - if (OneWireWorkingThread->state == CH_STATE_FINAL) - { - // OneWire working thread is now complete - break; - } + NANOCLR_NOCLEANUP_NOLABEL(); +} - // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); - } +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::WriteByte___U1__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - if (eventResult) - { - // event occurred + uint8_t sendbyte; - // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the - // heap, otherwise it won't be returned - oneWireOperationResult = chThdWait(OneWireWorkingThread); + sendbyte = (uint8_t)stack.Arg1().NumericByRefConst().u1; + stack.SetResult_U1(oneWireTouchByte(sendbyte) == sendbyte ? TRUE : FALSE); - oneWireReleaseModule(); + NANOCLR_NOCLEANUP_NOLABEL(); +} - // get the result from the working thread execution - if (oneWireOperationResult) - { - // update serialNumber field +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::ReadByte___U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); + stack.SetResult_U1(oneWireTouchByte(0xFF)); - // get a pointer to the serial number field in the OneWireController instance - CLR_RT_HeapBlock_Array *serialNumberField = pThis[FIELD___serialNumber].DereferenceArray(); + NANOCLR_NOCLEANUP_NOLABEL(); +} - _ASSERTE(serialNumberField->m_numOfElements == 8); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // get a pointer to the first element of the byte array - serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + NANOCLR_CHECK_HRESULT(FindOneDevice(stack, true)); - oneWireSerialNum(serialNumberPointer, TRUE); - } - } + NANOCLR_NOCLEANUP(); +} - // pop timeout heap block from stack - stack.PopValue(); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + (void)stack; - // set result - stack.SetResult_Boolean(oneWireOperationResult); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(FindOneDevice(stack, false)); NANOCLR_NOCLEANUP(); } @@ -390,12 +570,11 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeD HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeInit___VOID(CLR_RT_StackFrame &stack) { - (void)stack; + (void)stack; NANOCLR_HEADER(); - // startup 1-Wire driver - oneWireStart(); + NANOCLR_CHECK_HRESULT(oneWireInit()); - NANOCLR_NOCLEANUP_NOLABEL(); + NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h index dbc6185ea9..cb1843ef88 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -12,51 +12,51 @@ // set missing defines #if defined(USART0) -#ifndef GECKO_USE_USART0 -#define GECKO_USE_USART0 FALSE +#ifndef NF_ONEWIRE_USE_USART0 +#define NF_ONEWIRE_USE_USART0 FALSE #endif #else -#define GECKO_USE_USART0 FALSE +#define NF_ONEWIRE_USE_USART0 FALSE #endif #if defined(USART1) -#ifndef GECKO_USE_USART1 -#define GECKO_USE_USART1 FALSE +#ifndef NF_ONEWIRE_USE_USART1 +#define NF_ONEWIRE_USE_USART1 FALSE #endif #else -#define GECKO_USE_USART1 FALSE +#define NF_ONEWIRE_USE_USART1 FALSE #endif #if defined(USART2) -#ifndef GECKO_USE_USART2 -#define GECKO_USE_USART2 FALSE +#ifndef NF_ONEWIRE_USE_USART2 +#define NF_ONEWIRE_USE_USART2 FALSE #endif #else -#define GECKO_USE_USART2 FALSE +#define NF_ONEWIRE_USE_USART2 FALSE #endif #if defined(USART3) -#ifndef GECKO_USE_USART3 -#define GECKO_USE_USART3 FALSE +#ifndef NF_ONEWIRE_USE_USART3 +#define NF_ONEWIRE_USE_USART3 FALSE #endif #else -#define GECKO_USE_USART3 FALSE +#define NF_ONEWIRE_USE_USART3 FALSE #endif #if defined(USART4) -#ifndef GECKO_USE_USART4 -#define GECKO_USE_USART4 FALSE +#ifndef NF_ONEWIRE_USE_USART4 +#define NF_ONEWIRE_USE_USART4 FALSE #endif #else -#define GECKO_USE_USART4 FALSE +#define NF_ONEWIRE_USE_USART4 FALSE #endif #if defined(USART5) -#ifndef GECKO_USE_USART5 -#define GECKO_USE_USART5 FALSE +#ifndef NF_ONEWIRE_USE_USART5 +#define NF_ONEWIRE_USE_USART5 FALSE #endif #else -#define GECKO_USE_USART5 FALSE +#define NF_ONEWIRE_USE_USART5 FALSE #endif // struct with parameters for 1-Wire working thread @@ -80,6 +80,7 @@ typedef enum ONEWIRE_ACTIVE } oneWireState; + // character to send on the UART to mimic 1-Wire bus signals // 1-Wire write 0 time slot #define IWIRE_WR0 0x00 @@ -94,25 +95,15 @@ typedef enum // conditional search ROM #define COND_SEARCH_ROM 0xEC -#if defined(_USART_ROUTELOC0_MASK) - -// the following macro defines a function that configures the GPIO pins for an Gecko USART peripheral -// it gets called in the oneWire_lld_start function -// this is required because the USART peripherals can use multiple GPIO configuration combinations -#define INIT_ONEWIRE_CONFIG(num, usart_tx_port_location, usart_rx_location) \ - void InitSpiConfig##num(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex) \ - { \ - initSpiData.port = USART##num; \ - initSpiData.portLocationTx = mosi_port_location; \ - initSpiData.portLocationClk = sck_port_location; \ - if (!isHalfDuplex) \ - { \ - initSpiData.portLocationRx = miso_port_location; \ - } \ - } +#include "sl_iostream.h" +#ifdef __cplusplus +extern "C" { +#endif + +sl_status_t sl_iostream_usart_init_onewire(void); -#else -#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#ifdef __cplusplus +} #endif #endif // _NF_DEV_ONEWIRE_TARGET_H_ diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 25339fb6ce..219f2fb8ef 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -28,7 +28,7 @@ // #define HAL_USE_WDG @HAL_USE_WDG_OPTION@ // #define HAL_USE_CAN @HAL_USE_CAN_OPTION@ // #define HAL_NF_USE_STM32_CRC TRUE -// #define HAL_NF_USE_STM32_ONEWIRE @HAL_USE_STM32_ONEWIRE_OPTION@ +#define HAL_USE_ONEWIRE @HAL_USE_ONEWIRE_OPTION@ // #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSD_OPTION@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ #define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ From 01a1051799e3f6aed90eafe7575045a473582315 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 00:16:02 +0100 Subject: [PATCH 136/572] Add config for 1-wire in Skyworks EVB target --- CMakeUserPresets.TEMPLATE.json | 23 ++++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++++++++++++++ .../target_nf_dev_onewire_config.h | 4 +- 3 files changed, 128 insertions(+), 2 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 9aa91d2baa..ad0a8a1dd3 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -176,6 +176,29 @@ "NF_INTEROP_ASSEMBLIES": null } }, + { + "name": "SKY_EEVB_PROTO1", + "inherits": [ + "user-local-tools", + "user-prefs", + "SL_STK3701A_preset" + ], + "cacheVariables": { + "TARGET_BOARD": { + "type": "STRING", + "value": "${presetName}" + }, + "TARGET_SERIAL_BAUDRATE": "115200", + "GECKO_FEATURE_USBD_HID": "OFF", + "GECKO_FEATURE_USBD_WINUSB": "OFF", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Adc": "OFF", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_nanoFramework.Device.OneWire": "ON", + "NF_INTEROP_ASSEMBLIES": null + } + }, { "name": "ESP32_PSRAM_REV0", "inherits": [ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h index 840f02a3de..f487878cb6 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h @@ -8,5 +8,5 @@ /////////// // enable USART0 -#define NF_ONEWIRE_STM32_UART_USE_USART0 TRUE -#define GECKO_USE_USART0 TRUE +#define NF_ONEWIRE_USE_USART0 TRUE +#define GECKO_USE_USART0 TRUE From 3faa8ac5364d8442d624c14b1f3afb0f23739aaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 01:51:51 +0100 Subject: [PATCH 137/572] Various fixes in usart stream and build --- CMake/Modules/FindGecko_SDK.cmake | 3 +- .../sl_iostream_init_usart_instances.c | 45 +++++++++++++++++-- 2 files changed, 42 insertions(+), 6 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 51736ce220..434c9822cc 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -158,14 +158,13 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endif() - if(HAL_WP_USE_SERIAL) + if(HAL_WP_USE_SERIAL OR HAL_USE_ONEWIRE_OPTION) list(APPEND gecko_sdk_srcs sl_iostream_usart.c) list(APPEND gecko_sdk_srcs sl_iostream_uart.c) list(APPEND gecko_sdk_srcs sl_iostream.c) list(APPEND gecko_sdk_srcs sl_iostream_handles.c) list(APPEND gecko_sdk_srcs sl_iostream_init_usart_instances.c) - endif() diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 3e4f938c5e..24a6026eac 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -58,12 +58,9 @@ static sl_power_manager_em_transition_event_info_t events_info = { static sl_power_manager_em_transition_event_handle_t events_handle; #endif -#if HAL_WP_USE_SERIAL == TRUE -sl_status_t sl_iostream_usart_init_vcom(void); -#endif - // Instance(s) handle and context variable #if HAL_WP_USE_SERIAL == TRUE +sl_status_t sl_iostream_usart_init_vcom(void); static sl_iostream_uart_t sl_iostream_vcom; sl_iostream_t *sl_iostream_vcom_handle = &sl_iostream_vcom.stream; sl_iostream_uart_t *sl_iostream_uart_vcom_handle = &sl_iostream_vcom; @@ -150,6 +147,21 @@ sl_status_t sl_iostream_usart_init_vcom(void) #endif #if HAL_USE_ONEWIRE == TRUE + +sl_status_t sl_iostream_usart_init_onewire(void); +static sl_iostream_uart_t sl_iostream_onewire; +sl_iostream_t *sl_iostream_onewire_handle = &sl_iostream_onewire.stream; +sl_iostream_uart_t *sl_iostream_uart_onewire_handle = &sl_iostream_onewire; +static sl_iostream_usart_context_t context_onewire; +static uint8_t rx_buffer_onewire[SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE]; +sl_iostream_instance_info_t sl_iostream_instance_onewire_info = { + .handle = &sl_iostream_onewire.stream, + .name = "ONEWIRE", + .type = SL_IOSTREAM_TYPE_UART, + .periph_id = SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO, + .init = sl_iostream_usart_init_onewire, +}; + sl_status_t sl_iostream_usart_init_onewire(void) { sl_status_t status; @@ -240,6 +252,8 @@ void sl_iostream_usart_init_instances(void) #endif } +#if HAL_WP_USE_SERIAL == TRUE + // VCOM IRQ Handler void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) { @@ -251,6 +265,22 @@ void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); } +#endif // HAL_WP_USE_SERIAL + +#if HAL_USE_ONEWIRE == TRUE + +// ONEWIRE IRQ Handler +void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO)(void) +{ + sl_iostream_usart_irq_handler(sl_iostream_onewire.stream.context); +} + +void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO)(void) +{ + sl_iostream_usart_irq_handler(sl_iostream_onewire.stream.context); +} + +#endif // HAL_USE_ONEWIRE #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void) @@ -289,3 +319,10 @@ void sli_iostream_on_uart_rx(sl_iostream_t *handle) { (void)handle; } + +void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate) +{ + sl_iostream_usart_context_t *usart_context = (sl_iostream_usart_context_t *)handle->context; + + USART_BaudrateAsyncSet(usart_context->usart, 0, baudrate, 0); +} From 4b87d42dc17d23ec12e9e1def2908d6458540bd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 01:52:52 +0100 Subject: [PATCH 138/572] More work on 1-Wire implementation --- ...noFramework_Device_OneWire_OneWireHost.cpp | 42 +++++++++++-------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index ec8bd91eb9..f750491d79 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -12,12 +12,15 @@ // struct for working threads static OneWireFindStruct FindStruct; static bool OneWireOperationResult; -static TaskHandle_t WaitingTask; +// static TaskHandle_t WaitingTask; static uint8_t LastDiscrepancy; static uint8_t LastFamilyDiscrepancy; static uint8_t LastDevice; static uint8_t SerialNum[8]; +extern void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate); +extern sl_iostream_t *sl_iostream_onewire_handle; + // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; @@ -49,18 +52,19 @@ uint8_t oneWireTouchReset(void) { char reset = 0xF0; uint8_t presence; + size_t bytesRead; // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) - uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 9600); + sli_iostream_change_baudrate(sl_iostream_onewire_handle, 9600); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&reset, 1); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &presence, 1, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&reset, 1); + sl_iostream_read(sl_iostream_onewire_handle, &presence, 1, &bytesRead); // set UART baud rate to 115200bps (normal comm is performed at this baud rate) - uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 115200); + sli_iostream_change_baudrate(sl_iostream_onewire_handle, 115200); // check for presence pulse return (presence != reset); @@ -71,12 +75,13 @@ bool oneWireTouchBit(bool sendbit) // need to send 1-Wire write 1 or 0 according to sendbit char write = sendbit ? IWIRE_WR1 : IWIRE_WR0; uint8_t reply; + size_t bytesRead; // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&write, 1); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &reply, 1, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&write, 1); + sl_iostream_read(sl_iostream_onewire_handle, &reply, 1, &bytesRead); // interpret 1-Wire reply return (reply == IWIRE_RD); @@ -88,6 +93,7 @@ uint8_t oneWireTouchByte(uint8_t sendbyte) uint8_t i = 0; char writeBuffer[8]; uint8_t readBuffer[8]; + size_t bytesRead; // send byte while (send_mask) @@ -101,8 +107,8 @@ uint8_t oneWireTouchByte(uint8_t sendbyte) // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)writeBuffer, 8); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, readBuffer, 8, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&writeBuffer, 8); + sl_iostream_read(sl_iostream_onewire_handle, &readBuffer, 8, &bytesRead); // reset send mask to interpret the reply send_mask = 0x01; @@ -128,7 +134,7 @@ void oneWireRelease() { } -// compute CRC8 using running algorith (slower but saves FLASH) +// compute CRC8 using running algorithm (slower but saves FLASH) uint8_t doCrc8(uint8_t oldCrc, uint8_t x) { uint8_t crc = oldCrc; @@ -403,8 +409,9 @@ static void OneWireFindWorkingThread(void *pvParameters) : oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); // fire event for 1-Wire operation completed - xTaskNotifyGive(WaitingTask); - vTaskDelete(NULL); + // TODO + // xTaskNotifyGive(WaitingTask); + // vTaskDelete(NULL); } HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) @@ -412,7 +419,7 @@ HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) uint8_t *serialNumberPointer; CLR_RT_HeapBlock hbTimeout; CLR_INT64 *timeout; - TaskHandle_t task; + // TaskHandle_t task; HRESULT result; // set an infinite timeout to wait forever for the operation to complete @@ -436,8 +443,9 @@ HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) oneWireAquire(); // spawn working thread to perform the 1-Wire operations - WaitingTask = xTaskGetCurrentTaskHandle(); - xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); + // TODO + // WaitingTask = xTaskGetCurrentTaskHandle(); + // xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); // bump custom state stack.m_customState = 2; @@ -570,7 +578,7 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeD HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeInit___VOID(CLR_RT_StackFrame &stack) { - (void)stack; + (void)stack; NANOCLR_HEADER(); From 067238f42ecacc752d5b505d6ee6b695163349bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 01:52:52 +0100 Subject: [PATCH 139/572] More work on 1-Wire implementation --- ...noFramework_Device_OneWire_OneWireHost.cpp | 147 +++++++++++------- .../nf_dev_onewire_target.h | 2 + 2 files changed, 97 insertions(+), 52 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index ec8bd91eb9..5f6a5e0a37 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -9,15 +9,24 @@ // 1-Wire API code // ///////////////////// +#define ONEWIRE_THREAD_STACK_SIZE 256 +#define ONEWIRE_THREAD_PRIORITY 5 + // struct for working threads static OneWireFindStruct FindStruct; static bool OneWireOperationResult; -static TaskHandle_t WaitingTask; +static TX_THREAD *WaitingTask; +static uint32_t *workingThreadStack; static uint8_t LastDiscrepancy; static uint8_t LastFamilyDiscrepancy; static uint8_t LastDevice; static uint8_t SerialNum[8]; +typedef Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost OneWireHost; + +extern "C" void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate); +extern sl_iostream_t *sl_iostream_onewire_handle; + // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; @@ -37,9 +46,6 @@ HRESULT oneWireInit() sl_iostream_usart_init_onewire(); - // driver need to be deleted on soft reboot - HAL_AddSoftRebootHandler(oneWireStop); - DriverState = ONEWIRE_READY; return S_OK; @@ -49,18 +55,19 @@ uint8_t oneWireTouchReset(void) { char reset = 0xF0; uint8_t presence; + size_t bytesRead; // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) - uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 9600); + sli_iostream_change_baudrate(sl_iostream_onewire_handle, 9600); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&reset, 1); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &presence, 1, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&reset, 1); + sl_iostream_read(sl_iostream_onewire_handle, &presence, 1, &bytesRead); // set UART baud rate to 115200bps (normal comm is performed at this baud rate) - uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 115200); + sli_iostream_change_baudrate(sl_iostream_onewire_handle, 115200); // check for presence pulse return (presence != reset); @@ -71,12 +78,13 @@ bool oneWireTouchBit(bool sendbit) // need to send 1-Wire write 1 or 0 according to sendbit char write = sendbit ? IWIRE_WR1 : IWIRE_WR0; uint8_t reply; + size_t bytesRead; // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&write, 1); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &reply, 1, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&write, 1); + sl_iostream_read(sl_iostream_onewire_handle, &reply, 1, &bytesRead); // interpret 1-Wire reply return (reply == IWIRE_RD); @@ -88,6 +96,7 @@ uint8_t oneWireTouchByte(uint8_t sendbyte) uint8_t i = 0; char writeBuffer[8]; uint8_t readBuffer[8]; + size_t bytesRead; // send byte while (send_mask) @@ -101,8 +110,8 @@ uint8_t oneWireTouchByte(uint8_t sendbyte) // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)writeBuffer, 8); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, readBuffer, 8, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&writeBuffer, 8); + sl_iostream_read(sl_iostream_onewire_handle, &readBuffer, 8, &bytesRead); // reset send mask to interpret the reply send_mask = 0x01; @@ -128,7 +137,7 @@ void oneWireRelease() { } -// compute CRC8 using running algorith (slower but saves FLASH) +// compute CRC8 using running algorithm (slower but saves FLASH) uint8_t doCrc8(uint8_t oldCrc, uint8_t x) { uint8_t crc = oldCrc; @@ -395,35 +404,33 @@ bool oneWireFindFirst(bool doReset, bool alarmOnly) } // OneWire Find First/Next working thread -static void OneWireFindWorkingThread(void *pvParameters) +static void OneWireFindWorkingThread_entry(uint32_t arg) { - OneWireFindStruct *findStruct = (OneWireFindStruct *)pvParameters; + OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; OneWireOperationResult = findStruct->FindFirst ? oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly) : oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); - // fire event for 1-Wire operation completed - xTaskNotifyGive(WaitingTask); - vTaskDelete(NULL); + // fire event for 1-Wire operarion completed + Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + + // terminate this thread + tx_thread_terminate(WaitingTask); } HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) { + NANOCLR_HEADER(); + uint8_t *serialNumberPointer; CLR_RT_HeapBlock hbTimeout; CLR_INT64 *timeout; - TaskHandle_t task; - HRESULT result; + bool eventResult = true; // set an infinite timeout to wait forever for the operation to complete // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below hbTimeout.SetInteger((CLR_INT64)-1); - result = stack.SetupTimeoutFromTicks(hbTimeout, timeout); - - if (result != S_OK) - { - return result; - } + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); // this is going to be used to check for the right event in case of simultaneous 1-Wire operations if (stack.m_customState == 1) @@ -436,41 +443,79 @@ HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) oneWireAquire(); // spawn working thread to perform the 1-Wire operations - WaitingTask = xTaskGetCurrentTaskHandle(); - xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); + + // 1. allocate memory for thread stack + workingThreadStack = (uint32_t *)platform_malloc(ONEWIRE_THREAD_STACK_SIZE); + + if (workingThreadStack == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // 2. create thread + uint16_t status = tx_thread_create( + WaitingTask, +#if !defined(BUILD_RTM) + (CHAR *)"1-Wire Thread", +#else + NULL, +#endif + OneWireFindWorkingThread_entry, + (uint32_t)&FindStruct, + workingThreadStack, + ONEWIRE_THREAD_STACK_SIZE, + ONEWIRE_THREAD_PRIORITY, + ONEWIRE_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } // bump custom state stack.m_customState = 2; } - // wait for 1-Wire operation complete - ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + while (eventResult) + { + if (WaitingTask->tx_thread_state == TX_TERMINATED) + { + // ONEWIRE working thread is now complete + break; + } - oneWireRelease(); + // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); + } - // get the result from the working thread execution - if (OneWireOperationResult) + if (eventResult) { - // update serialNumber field + // event occurred + + oneWireRelease(); - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - if (pThis == NULL) + // get the result from the working thread execution + if (OneWireOperationResult) { - return CLR_E_NULL_REFERENCE; - } + // update serialNumber field + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); - // get a pointer to the serial number field in the OneWireController instance - CLR_RT_HeapBlock_Array *serialNumberField = - pThis[Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FIELD___serialNumber] - .DereferenceArray(); + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array *serialNumberField = pThis[OneWireHost::FIELD___serialNumber].DereferenceArray(); - _ASSERTE(serialNumberField->m_numOfElements == 8); + _ASSERTE(serialNumberField->m_numOfElements == 8); - // get a pointer to the first element of the byte array - serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); - oneWireSerialNum(serialNumberPointer, TRUE); + oneWireSerialNum(serialNumberPointer, TRUE); + } } // pop timeout heap block from stack @@ -479,7 +524,7 @@ HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) // set result stack.SetResult_Boolean(OneWireOperationResult); - return S_OK; + NANOCLR_NOCLEANUP(); } ////////////////////////// @@ -548,8 +593,6 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFir HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( CLR_RT_StackFrame &stack) { - (void)stack; - NANOCLR_HEADER(); NANOCLR_CHECK_HRESULT(FindOneDevice(stack, false)); @@ -570,7 +613,7 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeD HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeInit___VOID(CLR_RT_StackFrame &stack) { - (void)stack; + (void)stack; NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h index cb1843ef88..56f110502a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -10,6 +10,8 @@ #include #include +#include + // set missing defines #if defined(USART0) #ifndef NF_ONEWIRE_USE_USART0 From 3b912ba4b844a7f0db9705d4a352d6c7e6bbb922 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 10:42:27 +0100 Subject: [PATCH 140/572] Adjust 1-Wire target configuration --- .../target_nf_dev_onewire_config.cpp | 16 +++------------- .../target_nf_dev_onewire_config.h | 1 - 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp index 3a019bb807..949567e829 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp @@ -3,16 +3,6 @@ // See LICENSE file in the project root for full license information. // -#include "target_nf_dev_onewire_config.h" -#include - -/////////// -// UART0 // -/////////// - -// pin configuration for UART0 -// UART0 TX: PE10, location 1 -// UART0 TX: PE11, location 1 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -UART_CONFIG_PINS(0, 0, 0) +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h index f487878cb6..74d8b5da5b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h @@ -9,4 +9,3 @@ // enable USART0 #define NF_ONEWIRE_USE_USART0 TRUE -#define GECKO_USE_USART0 TRUE From 0b96e559dc03a47a8dbab6eb09e9f49adece92b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Sep 2022 12:13:54 +0100 Subject: [PATCH 141/572] Update declaration of Gecko ADC assembly - Update code accordingly. --- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp | 4 ++-- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h | 5 ++--- ...gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 4 ++-- ...adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 2 +- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index 6bfbb5f950..f07a0b0149 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -17,7 +17,7 @@ static const CLR_RT_MethodHandler method_lookup[] = Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4, NULL, NULL, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeDisposeChannel___VOID, NULL, NULL, @@ -80,7 +80,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0x252EAE1B, + 0x175512A5, method_lookup, { 100, 1, 0, 0 } }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index 3b3f56e326..8240ccd4d4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -129,10 +129,9 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel static const int FIELD___disposed = 3; static const int FIELD___channelNumber = 4; static const int FIELD___adcChannelConfiguration = 5; - static const int FIELD___averageCount = 6; NANOCLR_NATIVE_DECLARE(get_LastContinuousValue___I4); - NANOCLR_NATIVE_DECLARE(NativeReadValue___I4); + NANOCLR_NATIVE_DECLARE(NativeReadValue___I4__I4); NANOCLR_NATIVE_DECLARE(NativeDisposeChannel___VOID); //--// @@ -167,7 +166,7 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController static const int FIELD___scanChannels = 2; static const int FIELD___averageCount = 3; static const int FIELD___continuousSamplingStarted = 4; - static const int FIELD___acdConfiguration = 5; + static const int FIELD___adcConfiguration = 5; NANOCLR_NATIVE_DECLARE(NativeInit___VOID); NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 6f9b180558..81c485e493 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -41,7 +41,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_ NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4( +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -99,7 +99,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati samplesCount = averageCount; // get a pointer to the channel AdcChannelConfiguration object instance - ParseAdcChannelConfig(pThis[FIELD___averageCount].Dereference(), &channelInitSingle); + ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitSingle); ADC_InitSingle(adcDriver, &channelInitSingle); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index b38abe3990..4c3949b6a6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -104,7 +104,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N ) { // get a pointer to the managed AdcConfiguration object instance - adcConfiguration = pThis[FIELD___acdConfiguration].Dereference(); + adcConfiguration = pThis[FIELD___adcConfiguration].Dereference(); // init with default values *adcInit = ADC_INIT_DEFAULT; From eb284e30bb30e884741eb67ee0d6ec4f8eb57212 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 00:14:11 +0100 Subject: [PATCH 142/572] Implementation for 1-Wire using SL stream for UART --- CMakeLists.txt | 2 + .../_common/autogen/sl_iostream_handles.c | 9 +- .../sl_iostream_init_usart_instances.c | 311 +++++---- .../sl_iostream_init_usart_instances.h | 15 +- ...noFramework_Device_OneWire_OneWireHost.cpp | 619 +++++++++++------- .../nf_dev_onewire_target.h | 63 +- .../SiliconLabs/_nanoCLR/target_platform.h.in | 2 +- 7 files changed, 641 insertions(+), 380 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 3e8d813de3..162dcc41ba 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -580,8 +580,10 @@ endif() if(API_nanoFramework.Device.OneWire) set(HAL_USE_STM32_ONEWIRE_OPTION TRUE CACHE INTERNAL "HAL STM32_ONEWIRE for nanoFramework.Device.OneWire") + set(HAL_USE_ONEWIRE_OPTION TRUE CACHE INTERNAL "HAL ONEWIRE for nanoFramework.Device.OneWire") else() set(HAL_USE_STM32_ONEWIRE_OPTION FALSE CACHE INTERNAL "HAL STM32_ONEWIRE for nanoFramework.Device.OneWire") + set(HAL_USE_ONEWIRE_OPTION FALSE CACHE INTERNAL "HAL ONEWIRE for nanoFramework.Device.OneWire") endif() ################################################################################# diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c index fee0efcc62..b89c50f299 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_handles.c @@ -1,11 +1,18 @@ #include "sl_iostream.h" #include "sl_iostream_handles.h" #include "string.h" +#include const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { +#if HAL_WP_USE_SERIAL == TRUE &sl_iostream_instance_vcom_info, - +#endif + +#if HAL_USE_ONEWIRE == TRUE + &sl_iostream_instance_onewire_info, +#endif + }; const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index cf1c75e27b..3e4f938c5e 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -8,8 +8,16 @@ #include "sl_iostream.h" #include "sl_iostream_uart.h" #include "sl_iostream_usart.h" -// Include instance config +#include + +// Include instance config +#if HAL_WP_USE_SERIAL == TRUE #include "sl_iostream_usart_vcom_config.h" +#endif +#if HAL_USE_ONEWIRE == TRUE +#include "sl_iostream_usart_onewire_config.h" +#endif + #include // need to define this here to avoid compiler warning (error) @@ -19,204 +27,265 @@ // Baudrate for the serial port // // Override default setting from board if build option is set // //////////////////////////////////////////////////////////////// -#ifdef TARGET_SERIAL_BAUDRATE +#ifdef TARGET_SERIAL_BAUDRATE #undef SL_IOSTREAM_USART_VCOM_BAUDRATE #define SL_IOSTREAM_USART_VCOM_BAUDRATE TARGET_SERIAL_BAUDRATE #endif -// MACROs for generating name and IRQ handler function -#define SL_IOSTREAM_USART_CONCAT_PASTER(first, second, third) first ## second ## third - - - +// MACROs for generating name and IRQ handler function +#define SL_IOSTREAM_USART_CONCAT_PASTER(first, second, third) first##second##third -#define SL_IOSTREAM_USART_TX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQn) -#define SL_IOSTREAM_USART_RX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQn) -#define SL_IOSTREAM_USART_TX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQHandler) -#define SL_IOSTREAM_USART_RX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQHandler) +#define SL_IOSTREAM_USART_TX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQn) +#define SL_IOSTREAM_USART_RX_IRQ_NUMBER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQn) +#define SL_IOSTREAM_USART_TX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _TX_IRQHandler) +#define SL_IOSTREAM_USART_RX_IRQ_HANDLER(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(USART, periph_nbr, _RX_IRQHandler) -#define SL_IOSTREAM_USART_CLOCK_REF(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(cmuClock_, USART, periph_nbr) +#define SL_IOSTREAM_USART_CLOCK_REF(periph_nbr) SL_IOSTREAM_USART_CONCAT_PASTER(cmuClock_, USART, periph_nbr) -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) // EM Events -#define SLEEP_EM_EVENT_MASK ( SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ - | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ - | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ - | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) +#define SLEEP_EM_EVENT_MASK \ + (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 | \ + SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) #endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) -static void events_handler(sl_power_manager_em_t from, - sl_power_manager_em_t to); -static sl_power_manager_em_transition_event_info_t events_info = -{ - .event_mask = SLEEP_EM_EVENT_MASK, - .on_event = events_handler, +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +static void events_handler(sl_power_manager_em_t from, sl_power_manager_em_t to); +static sl_power_manager_em_transition_event_info_t events_info = { + .event_mask = SLEEP_EM_EVENT_MASK, + .on_event = events_handler, }; static sl_power_manager_em_transition_event_handle_t events_handle; #endif - +#if HAL_WP_USE_SERIAL == TRUE sl_status_t sl_iostream_usart_init_vcom(void); +#endif - -// Instance(s) handle and context variable +// Instance(s) handle and context variable +#if HAL_WP_USE_SERIAL == TRUE static sl_iostream_uart_t sl_iostream_vcom; sl_iostream_t *sl_iostream_vcom_handle = &sl_iostream_vcom.stream; sl_iostream_uart_t *sl_iostream_uart_vcom_handle = &sl_iostream_vcom; -static sl_iostream_usart_context_t context_vcom; -static uint8_t rx_buffer_vcom[SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE]; +static sl_iostream_usart_context_t context_vcom; +static uint8_t rx_buffer_vcom[SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE]; sl_iostream_instance_info_t sl_iostream_instance_vcom_info = { - .handle = &sl_iostream_vcom.stream, - .name = "vcom", - .type = SL_IOSTREAM_TYPE_UART, - .periph_id = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, - .init = sl_iostream_usart_init_vcom, + .handle = &sl_iostream_vcom.stream, + .name = "vcom", + .type = SL_IOSTREAM_TYPE_UART, + .periph_id = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, + .init = sl_iostream_usart_init_vcom, }; - - sl_status_t sl_iostream_usart_init_vcom(void) { - sl_status_t status; - USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; - init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; - init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; - init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; + sl_status_t status; + USART_InitAsync_TypeDef init_vcom = USART_INITASYNC_DEFAULT; + init_vcom.baudrate = SL_IOSTREAM_USART_VCOM_BAUDRATE; + init_vcom.parity = SL_IOSTREAM_USART_VCOM_PARITY; + init_vcom.stopbits = SL_IOSTREAM_USART_VCOM_STOP_BITS; #if (_SILICON_LABS_32B_SERIES > 0) #if (SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE != uartFlowControlSoftware) - init_vcom.hwFlowControl = SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE; + init_vcom.hwFlowControl = SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE; #else - init_vcom.hwFlowControl = usartHwFlowControlNone; + init_vcom.hwFlowControl = usartHwFlowControlNone; #endif #endif - sl_iostream_usart_config_t config_vcom = { - .usart = SL_IOSTREAM_USART_VCOM_PERIPHERAL, - .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), - .tx_port = SL_IOSTREAM_USART_VCOM_TX_PORT, - .tx_pin = SL_IOSTREAM_USART_VCOM_TX_PIN, - .rx_port = SL_IOSTREAM_USART_VCOM_RX_PORT, - .rx_pin = SL_IOSTREAM_USART_VCOM_RX_PIN, + sl_iostream_usart_config_t config_vcom = { + .usart = SL_IOSTREAM_USART_VCOM_PERIPHERAL, + .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .tx_port = SL_IOSTREAM_USART_VCOM_TX_PORT, + .tx_pin = SL_IOSTREAM_USART_VCOM_TX_PIN, + .rx_port = SL_IOSTREAM_USART_VCOM_RX_PORT, + .rx_pin = SL_IOSTREAM_USART_VCOM_RX_PIN, #if (_SILICON_LABS_32B_SERIES > 0) #if defined(SL_IOSTREAM_USART_VCOM_CTS_PORT) - .cts_port = SL_IOSTREAM_USART_VCOM_CTS_PORT, - .cts_pin = SL_IOSTREAM_USART_VCOM_CTS_PIN, + .cts_port = SL_IOSTREAM_USART_VCOM_CTS_PORT, + .cts_pin = SL_IOSTREAM_USART_VCOM_CTS_PIN, #endif #if defined(SL_IOSTREAM_USART_VCOM_RTS_PORT) - .rts_port = SL_IOSTREAM_USART_VCOM_RTS_PORT, - .rts_pin = SL_IOSTREAM_USART_VCOM_RTS_PIN, + .rts_port = SL_IOSTREAM_USART_VCOM_RTS_PORT, + .rts_pin = SL_IOSTREAM_USART_VCOM_RTS_PIN, #endif #endif #if defined(GPIO_USART_ROUTEEN_TXPEN) - .usart_index = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, + .usart_index = SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO, #elif defined(USART_ROUTEPEN_RXPEN) - .usart_tx_location = SL_IOSTREAM_USART_VCOM_TX_LOC, - .usart_rx_location = SL_IOSTREAM_USART_VCOM_RX_LOC, + .usart_tx_location = SL_IOSTREAM_USART_VCOM_TX_LOC, + .usart_rx_location = SL_IOSTREAM_USART_VCOM_RX_LOC, #if defined(SL_IOSTREAM_USART_VCOM_CTS_PORT) - .usart_cts_location = SL_IOSTREAM_USART_VCOM_CTS_LOC, + .usart_cts_location = SL_IOSTREAM_USART_VCOM_CTS_LOC, #endif #if defined(SL_IOSTREAM_USART_VCOM_RTS_PORT) - .usart_rts_location = SL_IOSTREAM_USART_VCOM_RTS_LOC, + .usart_rts_location = SL_IOSTREAM_USART_VCOM_RTS_LOC, #endif #else - .usart_location = SL_IOSTREAM_USART_VCOM_ROUTE_LOC, -#endif - }; - sl_iostream_uart_config_t uart_config_vcom = { - .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), - .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), - .rx_buffer = rx_buffer_vcom, - .rx_buffer_length = SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE, - .lf_to_crlf = SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF, - .rx_when_sleeping = SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, + .usart_location = SL_IOSTREAM_USART_VCOM_ROUTE_LOC, +#endif + }; + sl_iostream_uart_config_t uart_config_vcom = { + .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO), + .rx_buffer = rx_buffer_vcom, + .rx_buffer_length = SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE, + .lf_to_crlf = SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF, + .rx_when_sleeping = SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, #if defined(SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE) #if (SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE == uartFlowControlSoftware) - .sw_flow_control = true, + .sw_flow_control = true, #else - .sw_flow_control = false, + .sw_flow_control = false, #endif #else - .sw_flow_control = false, -#endif - }; - // Instantiate usart instance - status = sl_iostream_usart_init(&sl_iostream_vcom, - &uart_config_vcom, - &init_vcom, - &config_vcom, - &context_vcom); - EFM_ASSERT(status == SL_STATUS_OK); - - return status; + .sw_flow_control = false, +#endif + }; + // Instantiate usart instance + status = sl_iostream_usart_init(&sl_iostream_vcom, &uart_config_vcom, &init_vcom, &config_vcom, &context_vcom); + EFM_ASSERT(status == SL_STATUS_OK); + + return status; } +#endif +#if HAL_USE_ONEWIRE == TRUE +sl_status_t sl_iostream_usart_init_onewire(void) +{ + sl_status_t status; + USART_InitAsync_TypeDef init_onewire = USART_INITASYNC_DEFAULT; + init_onewire.baudrate = SL_IOSTREAM_USART_ONEWIRE_BAUDRATE; + init_onewire.parity = SL_IOSTREAM_USART_ONEWIRE_PARITY; + init_onewire.stopbits = SL_IOSTREAM_USART_ONEWIRE_STOP_BITS; +#if (_SILICON_LABS_32B_SERIES > 0) +#if (SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE != uartFlowControlSoftware) + init_onewire.hwFlowControl = SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE; +#else + init_onewire.hwFlowControl = usartHwFlowControlNone; +#endif +#endif + sl_iostream_usart_config_t config_onewire = { + .usart = SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL, + .clock = SL_IOSTREAM_USART_CLOCK_REF(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO), + .tx_port = SL_IOSTREAM_USART_ONEWIRE_TX_PORT, + .tx_pin = SL_IOSTREAM_USART_ONEWIRE_TX_PIN, + .rx_port = SL_IOSTREAM_USART_ONEWIRE_RX_PORT, + .rx_pin = SL_IOSTREAM_USART_ONEWIRE_RX_PIN, +#if (_SILICON_LABS_32B_SERIES > 0) +#if defined(SL_IOSTREAM_USART_ONEWIRE_CTS_PORT) + .cts_port = SL_IOSTREAM_USART_ONEWIRE_CTS_PORT, + .cts_pin = SL_IOSTREAM_USART_ONEWIRE_CTS_PIN, +#endif +#if defined(SL_IOSTREAM_USART_ONEWIRE_RTS_PORT) + .rts_port = SL_IOSTREAM_USART_ONEWIRE_RTS_PORT, + .rts_pin = SL_IOSTREAM_USART_ONEWIRE_RTS_PIN, +#endif +#endif +#if defined(GPIO_USART_ROUTEEN_TXPEN) + .usart_index = SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO, +#elif defined(USART_ROUTEPEN_RXPEN) + .usart_tx_location = SL_IOSTREAM_USART_ONEWIRE_TX_LOC, + .usart_rx_location = SL_IOSTREAM_USART_ONEWIRE_RX_LOC, +#if defined(SL_IOSTREAM_USART_ONEWIRE_CTS_PORT) + .usart_cts_location = SL_IOSTREAM_USART_ONEWIRE_CTS_LOC, +#endif +#if defined(SL_IOSTREAM_USART_ONEWIRE_RTS_PORT) + .usart_rts_location = SL_IOSTREAM_USART_ONEWIRE_RTS_LOC, +#endif +#else + .usart_location = SL_IOSTREAM_USART_ONEWIRE_ROUTE_LOC, +#endif + }; + sl_iostream_uart_config_t uart_config_onewire = { + .tx_irq_number = SL_IOSTREAM_USART_TX_IRQ_NUMBER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO), + .rx_irq_number = SL_IOSTREAM_USART_RX_IRQ_NUMBER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO), + .rx_buffer = rx_buffer_onewire, + .rx_buffer_length = SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE, + .lf_to_crlf = SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF, + .rx_when_sleeping = SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION, +#if defined(SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE) +#if (SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE == uartFlowControlSoftware) + .sw_flow_control = true, +#else + .sw_flow_control = false, +#endif +#else + .sw_flow_control = false, +#endif + }; + // Instantiate usart instance + status = sl_iostream_usart_init( + &sl_iostream_onewire, + &uart_config_onewire, + &init_onewire, + &config_onewire, + &context_onewire); + EFM_ASSERT(status == SL_STATUS_OK); + + return status; +} + +#endif void sl_iostream_usart_init_instances(void) { -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) - // Enable power manager notifications - sl_power_manager_subscribe_em_transition_event(&events_handle, &events_info); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) + // Enable power manager notifications + sl_power_manager_subscribe_em_transition_event(&events_handle, &events_info); #endif - // Instantiate usart instance(s) - - sl_iostream_usart_init_vcom(); - +// Instantiate usart instance(s) +#if HAL_WP_USE_SERIAL == TRUE + sl_iostream_usart_init_vcom(); +#endif } - // VCOM IRQ Handler void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) { - sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); + sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); } void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) { - sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); + sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); } - - #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - + sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void) { - return sl_iostream_uart_sleep_on_isr_exit(&sl_iostream_vcom); + return sl_iostream_uart_sleep_on_isr_exit(&sl_iostream_vcom); } #endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) -static void events_handler(sl_power_manager_em_t from, - sl_power_manager_em_t to) +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) +static void events_handler(sl_power_manager_em_t from, sl_power_manager_em_t to) { - uint32_t out; - if (((from == SL_POWER_MANAGER_EM2) - || (from == SL_POWER_MANAGER_EM3)) - && ((to == SL_POWER_MANAGER_EM1) - || (to == SL_POWER_MANAGER_EM0))) { - - // Wake the USART Tx pin back up - out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); - GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); - - } else if (((to == SL_POWER_MANAGER_EM2) - || (to == SL_POWER_MANAGER_EM3)) - && ((from == SL_POWER_MANAGER_EM1) - || (from == SL_POWER_MANAGER_EM0))) { - - // Sleep the USART Tx pin on series 2 devices to save energy - out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); - GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); - - } + uint32_t out; + if (((from == SL_POWER_MANAGER_EM2) || (from == SL_POWER_MANAGER_EM3)) && + ((to == SL_POWER_MANAGER_EM1) || (to == SL_POWER_MANAGER_EM0))) + { + + // Wake the USART Tx pin back up + out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); + GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); + } + else if ( + ((to == SL_POWER_MANAGER_EM2) || (to == SL_POWER_MANAGER_EM3)) && + ((from == SL_POWER_MANAGER_EM1) || (from == SL_POWER_MANAGER_EM0))) + { + + // Sleep the USART Tx pin on series 2 devices to save energy + out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); + GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); + } } #endif // implementation required (even if empty) to keep debugger happy void sli_iostream_on_uart_rx(sl_iostream_t *handle) { - (void)handle; + (void)handle; } diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h index 3c31aabb4a..713906bf87 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.h @@ -8,14 +8,22 @@ #endif #include "sl_iostream.h" #include "sl_iostream_uart.h" +#include + #ifdef __cplusplus extern "C" { #endif - +#if HAL_WP_USE_SERIAL == TRUE extern sl_iostream_t *sl_iostream_vcom_handle; extern sl_iostream_uart_t *sl_iostream_uart_vcom_handle; extern sl_iostream_instance_info_t sl_iostream_instance_vcom_info; +#endif +#if HAL_USE_ONEWIRE == TRUE +extern sl_iostream_t *sl_iostream_onewire_handle; +extern sl_iostream_uart_t *sl_iostream_uart_onewire_handle; +extern sl_iostream_instance_info_t sl_iostream_instance_onewire_info; +#endif // Initialize only iostream usart instance(s) @@ -23,7 +31,12 @@ void sl_iostream_usart_init_instances(void); #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#if HAL_WP_USE_SERIAL == TRUE sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void); +#endif +#if HAL_USE_ONEWIRE == TRUE +sl_power_manager_on_isr_exit_t sl_iostream_usart_onewire_sleep_on_isr_exit(void); +#endif #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index a6ae6ff30b..ec8bd91eb9 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -5,6 +5,9 @@ #include "nf_dev_onewire_target.h" +///////////////////// +// 1-Wire API code // +///////////////////// // struct for working threads static OneWireFindStruct FindStruct; @@ -18,64 +21,21 @@ static uint8_t SerialNum[8]; // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; -// working thread to execute long running 1-Wire operations -static thread_t *OneWireWorkingThread; - - -void IRAM_ATTR oneWireStop() +void oneWireStop() { // stop UART - uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); + // TODO + // uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); // driver is stopped DriverState = ONEWIRE_STOP; } -HRESULT IRAM_ATTR oneWireInit() +HRESULT oneWireInit() { DriverState = ONEWIRE_STOP; - uart_config_t uart_config = { - .baud_rate = 115200, - .data_bits = UART_DATA_8_BITS, - .parity = UART_PARITY_DISABLE, - .stop_bits = UART_STOP_BITS_1, - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, - .rx_flow_ctrl_thresh = 0, - .use_ref_tick = false, - }; - - // get GPIO pins configured for UART assigned to 1-Wire - // need to subtract one to get the correct index of UART in mapped device pins - int txPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, NF_ONEWIRE_ESP32_UART_NUM, Esp32SerialPin_Tx); - int rxPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, NF_ONEWIRE_ESP32_UART_NUM, Esp32SerialPin_Rx); - - // check if TX, RX pins have been previously set - if (txPin == UART_PIN_NO_CHANGE || rxPin == UART_PIN_NO_CHANGE) - { - return CLR_E_PIN_UNAVAILABLE; - } - - // configure GPIO and UART - if (gpio_set_direction(gpio_num_t(txPin), GPIO_MODE_OUTPUT_OD) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } - - if (uart_param_config(NF_ONEWIRE_ESP32_UART_NUM, &uart_config) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } - - if (uart_set_pin(NF_ONEWIRE_ESP32_UART_NUM, txPin, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } - - if (uart_driver_install(NF_ONEWIRE_ESP32_UART_NUM, 256, 256, 0, NULL, ESP_INTR_FLAG_IRAM) != ESP_OK) - { - return CLR_E_INVALID_OPERATION; - } + sl_iostream_usart_init_onewire(); // driver need to be deleted on soft reboot HAL_AddSoftRebootHandler(oneWireStop); @@ -85,14 +45,14 @@ HRESULT IRAM_ATTR oneWireInit() return S_OK; } - uint8_t oneWireTouchReset(void) { char reset = 0xF0; uint8_t presence; // flush DMA buffer to ensure cache coherency - uart_flush(NF_ONEWIRE_ESP32_UART_NUM); + // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 9600); @@ -106,273 +66,493 @@ uint8_t oneWireTouchReset(void) return (presence != reset); } -//////////////////////////////////////// -// struct for working threads -OneWireFindStruct FindStruct; - -// ChibiOS OneWire working thread -static THD_FUNCTION(OneWireFindFirstWorkingThread, arg) +bool oneWireTouchBit(bool sendbit) { - msg_t deviceFound; + // need to send 1-Wire write 1 or 0 according to sendbit + char write = sendbit ? IWIRE_WR1 : IWIRE_WR0; + uint8_t reply; - OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; - - deviceFound = oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly); + // flush DMA buffer to ensure cache coherency + // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - // fire event for 1-Wire operarion completed - Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&write, 1); + uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &reply, 1, 20 / portTICK_RATE_MS); - chThdExit(deviceFound); + // interpret 1-Wire reply + return (reply == IWIRE_RD); } -static THD_FUNCTION(OneWireFindNextWorkingThread, arg) +uint8_t oneWireTouchByte(uint8_t sendbyte) { - msg_t deviceFound; + uint8_t send_mask = 0x01, result = 0; + uint8_t i = 0; + char writeBuffer[8]; + uint8_t readBuffer[8]; - OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; + // send byte + while (send_mask) + { + writeBuffer[i] = (sendbyte & send_mask) ? IWIRE_WR1 : IWIRE_WR0; + i++; + // rotates the position mask transmit bit + send_mask <<= 1; + }; + + // flush DMA buffer to ensure cache coherency + // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - deviceFound = oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); + uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)writeBuffer, 8); + uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, readBuffer, 8, 20 / portTICK_RATE_MS); + + // reset send mask to interpret the reply + send_mask = 0x01; + + for (i = 0; i < 8; i++) + { + if (readBuffer[i] == IWIRE_RD) + { + result |= send_mask; + } - // fire event for 1-Wire operarion completed - Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + send_mask <<= 1; + } - chThdExit(deviceFound); + return result; } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchReset___BOOLEAN(CLR_RT_StackFrame &stack) +void oneWireAquire() { - NANOCLR_HEADER(); - - volatile bool reset = oneWireTouchReset(); - stack.SetResult_Boolean(reset); +} - NANOCLR_NOCLEANUP_NOLABEL(); +void oneWireRelease() +{ } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchBit___BOOLEAN__BOOLEAN( - CLR_RT_StackFrame &stack) +// compute CRC8 using running algorith (slower but saves FLASH) +uint8_t doCrc8(uint8_t oldCrc, uint8_t x) { - NANOCLR_HEADER(); + uint8_t crc = oldCrc; - bool value = stack.Arg1().NumericByRefConst().u1 != 0; + for (uint8_t i = 8; i; i--) + { + uint8_t mix = (crc ^ x) & 0x01; + crc >>= 1; + if (mix) + crc ^= 0x8C; + x >>= 1; + } + + return crc; +} - stack.SetResult_Boolean(oneWireTouchBit(value)); +/******************************************************************************* +** NAME: oneWireSerialNum ************************************************** +******************************************************************************** + +DESCRIPTION: + // The 'oneWireSerialNum' function either reads or sets the SerialNum buffer + // that is used in the search functions 'owFirst' and 'owNext'. + // This function contains two parameters, 'serialnum_buf' is a pointer + // to a buffer provided by the caller. 'serialnum_buf' should point to + // an array of 8 unsigned chars. The second parameter is a flag called + // 'do_read' that is TRUE (1) if the operation is to read and FALSE + // (0) if the operation is to set the internal SerialNum buffer from + // the data in the provided buffer. + // + // 'serialnum_buf' - buffer to that contains the serial number to set + // when do_read = FALSE (0) and buffer to get the serial + // number when do_read = TRUE (1). + // 'do_read' - flag to indicate reading (1) or setting (0) the current + // serial number. + // + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +void oneWireSerialNum(uint8_t *serialnum_buf, uint8_t do_read) +{ + uint8_t i; - NANOCLR_NOCLEANUP_NOLABEL(); + //-------------------------------------------------// + // read the internal buffer and place in 'serialnum_buf' + if (do_read) + { + for (i = 0; i < 8; i++) + { + serialnum_buf[i] = SerialNum[i]; + } + } + // set the internal buffer from the data in 'serialnum_buf' + else + { + for (i = 0; i < 8; i++) + { + SerialNum[i] = serialnum_buf[i]; + } + } } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchByte___U1__U1(CLR_RT_StackFrame &stack) +/******************************************************************************* +** NAME: oneWireFindNext ******************************************************* +********************************************************************************/ +// The 'oneWireFindNext' function does a general search. +// This function continues from the previos search state. The search state +// can be reset by using the 'oneWireFindFirst' function. +// This function contains one parameter 'alarmOnly'. +// When 'alarmOnly' is TRUE (1) the find alarm command +// 0xEC is sent instead of the normal search command 0xF0. +// Using the find alarm command 0xEC will limit the search to only +// 1-Wire devices that are in an 'alarm' state. +// +// 'doReset' - TRUE (1) perform reset before search, FALSE (0) do not +// perform reset before search. +// 'alarmOnly' - TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0 +// +// Returns: TRUE (1) : when a 1-Wire device was found and it's +// Serial Number placed in the global SerialNum +// FALSE (0): when no new device was found. Either the +// last search was the last device or there +// are no devices on the 1-Wire Net. +bool oneWireFindNext(bool doReset, bool alarmOnly) { - NANOCLR_HEADER(); + uint8_t romBitIndex = 1; + uint8_t romByteIndex = 0; + uint8_t bitMask = 1; + uint8_t attempt = 0; + uint8_t discrepMarker = 0; + bool outBit = 0; + bool result = FALSE; + uint8_t lastcrc8 = 0; + + // if the last call was the last one + if (LastDevice) + { + // reset the search + LastDiscrepancy = 0; + LastDevice = FALSE; + LastFamilyDiscrepancy = 0; - uint8_t value = (uint8_t)stack.Arg1().NumericByRefConst().u1; - uint8_t result = oneWireTouchByte(value); - stack.SetResult_U1(result); + return FALSE; + } - NANOCLR_NOCLEANUP_NOLABEL(); + // check if reset bus was requested + if (doReset) + { + // reset the 1-Wire bus + // if there is no presence pulse there is nothing to do here, return FALSE + if (!oneWireTouchReset()) + { + // reset the search + LastDiscrepancy = 0; + LastFamilyDiscrepancy = 0; + return FALSE; + } + } + + // send search command + if (alarmOnly) + { + // conditional search command (devices in alarm condition) + oneWireTouchByte(COND_SEARCH_ROM); + } + else + { + // ROM search command + oneWireTouchByte(SEARCH_ROM); + } + + do + { + attempt = 0; + + if (oneWireTouchBit(TRUE) == 1) + { + attempt = 2; + } + + if (oneWireTouchBit(TRUE) == 1) + { + attempt |= 1; + } + + if (attempt == 3) + { + // no devices present, done here + break; + } + else + { + if (attempt > 0) + { + // all connected devices reply with 0 or 1 + // write bit to perform search + outBit = attempt >> 1; + } + else + { + if (romBitIndex < LastDiscrepancy) + { + outBit = ((SerialNum[romByteIndex] & bitMask) > 0); + } + else + { + // set to 1 if it's the same, otherwise 0 + outBit = (romBitIndex == LastDiscrepancy); + } + + // on 0 record position on bitMask + if (outBit == 0) + { + discrepMarker = romBitIndex; + } + } + + // isolate bit in ROM[n] with bitMask + if (outBit == 1) + { + SerialNum[romByteIndex] |= bitMask; + } + else + { + SerialNum[romByteIndex] &= ~bitMask; + } + + // ROM search write + oneWireTouchBit(outBit); + + romBitIndex++; + + bitMask = bitMask << 1; + + // if the mask has reached 0 then go for a new ROM + if (bitMask == 0) + { + // reset mask and perform CRC8 + lastcrc8 = doCrc8(lastcrc8, SerialNum[romByteIndex]); + + romByteIndex++; + bitMask++; + } + } + + } while (romByteIndex < 8); // loop until we have all ROM bytes + + if ((romBitIndex < 65) || (lastcrc8 != 0)) + { + // search was unsuccessful reset the last discrepancy + LastDiscrepancy = 0; + } + else + { + // search was successful: set last discrepancy, device and result + LastDiscrepancy = discrepMarker; + LastDevice = (LastDiscrepancy == 0); + + // search isn't completed there are more devices present in the bus + result = TRUE; + } + + return result; } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::WriteByte___U1__U1(CLR_RT_StackFrame &stack) +/******************************************************************************* +** NAME: oneWireFindFirst ****************************************************** +********************************************************************************/ +// The 'oneWireFindFirst' finds the first device on the 1-Wire Net. +// This function contains one parameter 'alarmOnly'. When +// 'alarmOnly' is TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0. +// Using the find alarm command 0xEC will limit the search to only +// 1-Wire devices that are in an 'alarm' state. +// +// 'portnum' - number 0 to MAX_PORTNUM-1. This number is provided to +// indicate the symbolic port number. +// 'doReset' - TRUE (1) perform reset before search, FALSE (0) do not +// perform reset before search. +// 'alarmOnly' - TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0 +// +// Returns: TRUE (1) : when a 1-Wire device was found and it's +// Serial Number placed in the global SerialNum +// FALSE (0): There are no devices on the 1-Wire Net. +bool oneWireFindFirst(bool doReset, bool alarmOnly) { - NANOCLR_HEADER(); + // reset the search state + LastDiscrepancy = 0; + LastDevice = FALSE; + LastFamilyDiscrepancy = 0; - uint8_t cmd = (uint8_t)stack.Arg1().NumericByRefConst().u1; - uint8_t result = oneWireWriteByte(cmd); - stack.SetResult_U1(result); + // clear serial number buffer for new search + memset(SerialNum, 0, 8); - NANOCLR_NOCLEANUP_NOLABEL(); + // Call Next and return it's return value; + return oneWireFindNext(doReset, alarmOnly); } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::ReadByte___U1(CLR_RT_StackFrame &stack) +// OneWire Find First/Next working thread +static void OneWireFindWorkingThread(void *pvParameters) { - NANOCLR_HEADER(); + OneWireFindStruct *findStruct = (OneWireFindStruct *)pvParameters; - uint8_t result = oneWireReadByte(); - stack.SetResult_U1(result); + OneWireOperationResult = findStruct->FindFirst ? oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly) + : oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); - NANOCLR_NOCLEANUP_NOLABEL(); + // fire event for 1-Wire operation completed + xTaskNotifyGive(WaitingTask); + vTaskDelete(NULL); } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( - CLR_RT_StackFrame &stack) +HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) { - NANOCLR_HEADER(); - uint8_t *serialNumberPointer; - msg_t oneWireOperationResult = FALSE; - CLR_RT_HeapBlock hbTimeout; CLR_INT64 *timeout; - bool eventResult = true; + TaskHandle_t task; + HRESULT result; // set an infinite timeout to wait forever for the operation to complete // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below hbTimeout.SetInteger((CLR_INT64)-1); - NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); + result = stack.SetupTimeoutFromTicks(hbTimeout, timeout); + + if (result != S_OK) + { + return result; + } // this is going to be used to check for the right event in case of simultaneous 1-Wire operations if (stack.m_customState == 1) { FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + FindStruct.FindFirst = findFirst; // because the 1-Wire bus is shared, acquire the module - oneWireAcquireModule(); + oneWireAquire(); // spawn working thread to perform the 1-Wire operations - OneWireWorkingThread = chThdCreateFromHeap( - NULL, - THD_WORKING_AREA_SIZE(256), - "OWWT", - NORMALPRIO, - OneWireFindFirstWorkingThread, - &FindStruct); + WaitingTask = xTaskGetCurrentTaskHandle(); + xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); // bump custom state stack.m_customState = 2; } - while (eventResult) - { - if (OneWireWorkingThread->state == CH_STATE_FINAL) - { - // OneWire working thread is now complete - break; - } + // wait for 1-Wire operation complete + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); - // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); - } + oneWireRelease(); - if (eventResult) + // get the result from the working thread execution + if (OneWireOperationResult) { - // event occurred - - // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the - // heap, otherwise it won't be returned - oneWireOperationResult = chThdWait(OneWireWorkingThread); - - oneWireReleaseModule(); + // update serialNumber field - // get the result from the working thread execution - if (oneWireOperationResult) + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + if (pThis == NULL) { - // if a device was found update serialNumber field in managed class - - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); + return CLR_E_NULL_REFERENCE; + } - // get a pointer to the serial number field in the OneWireController instance - CLR_RT_HeapBlock_Array *serialNumberField = pThis[FIELD___serialNumber].DereferenceArray(); + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array *serialNumberField = + pThis[Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FIELD___serialNumber] + .DereferenceArray(); - _ASSERTE(serialNumberField->m_numOfElements == 8); + _ASSERTE(serialNumberField->m_numOfElements == 8); - // get a pointer to the first element of the byte array - serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); - oneWireSerialNum(serialNumberPointer, TRUE); - } + oneWireSerialNum(serialNumberPointer, TRUE); } // pop timeout heap block from stack stack.PopValue(); // set result - stack.SetResult_Boolean(oneWireOperationResult); + stack.SetResult_Boolean(OneWireOperationResult); - NANOCLR_NOCLEANUP(); + return S_OK; } -HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( - CLR_RT_StackFrame &stack) +////////////////////////// +// managed library code // +////////////////////////// + +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchReset___BOOLEAN(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - uint8_t *serialNumberPointer; - msg_t oneWireOperationResult = FALSE; + stack.SetResult_Boolean(oneWireTouchReset()); - CLR_RT_HeapBlock hbTimeout; - CLR_INT64 *timeout; - bool eventResult = true; + NANOCLR_NOCLEANUP_NOLABEL(); +} - // set an infinite timeout to wait forever for the operation to complete - // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below - hbTimeout.SetInteger((CLR_INT64)-1); - NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchBit___BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // this is going to be used to check for the right event in case of simultaneous 1-Wire operations - if (stack.m_customState == 1) - { - FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; - FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + stack.SetResult_Boolean(oneWireTouchBit(stack.Arg1().NumericByRefConst().u1 != 0)); - // because the 1-Wire bus is shared, acquire the module - oneWireAcquireModule(); + NANOCLR_NOCLEANUP_NOLABEL(); +} - // spawn working thread to perform the 1-Wire operations - OneWireWorkingThread = chThdCreateFromHeap( - NULL, - THD_WORKING_AREA_SIZE(256), - "OWWT", - NORMALPRIO, - OneWireFindNextWorkingThread, - &FindStruct); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::TouchByte___U1__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // bump custom state - stack.m_customState = 2; - } + stack.SetResult_U1(oneWireTouchByte((uint8_t)stack.Arg1().NumericByRefConst().u1)); - while (eventResult) - { - if (OneWireWorkingThread->state == CH_STATE_FINAL) - { - // OneWire working thread is now complete - break; - } + NANOCLR_NOCLEANUP_NOLABEL(); +} - // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); - } +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::WriteByte___U1__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - if (eventResult) - { - // event occurred + uint8_t sendbyte; - // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the - // heap, otherwise it won't be returned - oneWireOperationResult = chThdWait(OneWireWorkingThread); + sendbyte = (uint8_t)stack.Arg1().NumericByRefConst().u1; + stack.SetResult_U1(oneWireTouchByte(sendbyte) == sendbyte ? TRUE : FALSE); - oneWireReleaseModule(); + NANOCLR_NOCLEANUP_NOLABEL(); +} - // get the result from the working thread execution - if (oneWireOperationResult) - { - // update serialNumber field +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::ReadByte___U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); + stack.SetResult_U1(oneWireTouchByte(0xFF)); - // get a pointer to the serial number field in the OneWireController instance - CLR_RT_HeapBlock_Array *serialNumberField = pThis[FIELD___serialNumber].DereferenceArray(); + NANOCLR_NOCLEANUP_NOLABEL(); +} - _ASSERTE(serialNumberField->m_numOfElements == 8); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); - // get a pointer to the first element of the byte array - serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + NANOCLR_CHECK_HRESULT(FindOneDevice(stack, true)); - oneWireSerialNum(serialNumberPointer, TRUE); - } - } + NANOCLR_NOCLEANUP(); +} - // pop timeout heap block from stack - stack.PopValue(); +HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + (void)stack; - // set result - stack.SetResult_Boolean(oneWireOperationResult); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(FindOneDevice(stack, false)); NANOCLR_NOCLEANUP(); } @@ -390,12 +570,11 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeD HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeInit___VOID(CLR_RT_StackFrame &stack) { - (void)stack; + (void)stack; NANOCLR_HEADER(); - // startup 1-Wire driver - oneWireStart(); + NANOCLR_CHECK_HRESULT(oneWireInit()); - NANOCLR_NOCLEANUP_NOLABEL(); + NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h index dbc6185ea9..cb1843ef88 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -12,51 +12,51 @@ // set missing defines #if defined(USART0) -#ifndef GECKO_USE_USART0 -#define GECKO_USE_USART0 FALSE +#ifndef NF_ONEWIRE_USE_USART0 +#define NF_ONEWIRE_USE_USART0 FALSE #endif #else -#define GECKO_USE_USART0 FALSE +#define NF_ONEWIRE_USE_USART0 FALSE #endif #if defined(USART1) -#ifndef GECKO_USE_USART1 -#define GECKO_USE_USART1 FALSE +#ifndef NF_ONEWIRE_USE_USART1 +#define NF_ONEWIRE_USE_USART1 FALSE #endif #else -#define GECKO_USE_USART1 FALSE +#define NF_ONEWIRE_USE_USART1 FALSE #endif #if defined(USART2) -#ifndef GECKO_USE_USART2 -#define GECKO_USE_USART2 FALSE +#ifndef NF_ONEWIRE_USE_USART2 +#define NF_ONEWIRE_USE_USART2 FALSE #endif #else -#define GECKO_USE_USART2 FALSE +#define NF_ONEWIRE_USE_USART2 FALSE #endif #if defined(USART3) -#ifndef GECKO_USE_USART3 -#define GECKO_USE_USART3 FALSE +#ifndef NF_ONEWIRE_USE_USART3 +#define NF_ONEWIRE_USE_USART3 FALSE #endif #else -#define GECKO_USE_USART3 FALSE +#define NF_ONEWIRE_USE_USART3 FALSE #endif #if defined(USART4) -#ifndef GECKO_USE_USART4 -#define GECKO_USE_USART4 FALSE +#ifndef NF_ONEWIRE_USE_USART4 +#define NF_ONEWIRE_USE_USART4 FALSE #endif #else -#define GECKO_USE_USART4 FALSE +#define NF_ONEWIRE_USE_USART4 FALSE #endif #if defined(USART5) -#ifndef GECKO_USE_USART5 -#define GECKO_USE_USART5 FALSE +#ifndef NF_ONEWIRE_USE_USART5 +#define NF_ONEWIRE_USE_USART5 FALSE #endif #else -#define GECKO_USE_USART5 FALSE +#define NF_ONEWIRE_USE_USART5 FALSE #endif // struct with parameters for 1-Wire working thread @@ -80,6 +80,7 @@ typedef enum ONEWIRE_ACTIVE } oneWireState; + // character to send on the UART to mimic 1-Wire bus signals // 1-Wire write 0 time slot #define IWIRE_WR0 0x00 @@ -94,25 +95,15 @@ typedef enum // conditional search ROM #define COND_SEARCH_ROM 0xEC -#if defined(_USART_ROUTELOC0_MASK) - -// the following macro defines a function that configures the GPIO pins for an Gecko USART peripheral -// it gets called in the oneWire_lld_start function -// this is required because the USART peripherals can use multiple GPIO configuration combinations -#define INIT_ONEWIRE_CONFIG(num, usart_tx_port_location, usart_rx_location) \ - void InitSpiConfig##num(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex) \ - { \ - initSpiData.port = USART##num; \ - initSpiData.portLocationTx = mosi_port_location; \ - initSpiData.portLocationClk = sck_port_location; \ - if (!isHalfDuplex) \ - { \ - initSpiData.portLocationRx = miso_port_location; \ - } \ - } +#include "sl_iostream.h" +#ifdef __cplusplus +extern "C" { +#endif + +sl_status_t sl_iostream_usart_init_onewire(void); -#else -#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#ifdef __cplusplus +} #endif #endif // _NF_DEV_ONEWIRE_TARGET_H_ diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in index 25339fb6ce..219f2fb8ef 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/target_platform.h.in @@ -28,7 +28,7 @@ // #define HAL_USE_WDG @HAL_USE_WDG_OPTION@ // #define HAL_USE_CAN @HAL_USE_CAN_OPTION@ // #define HAL_NF_USE_STM32_CRC TRUE -// #define HAL_NF_USE_STM32_ONEWIRE @HAL_USE_STM32_ONEWIRE_OPTION@ +#define HAL_USE_ONEWIRE @HAL_USE_ONEWIRE_OPTION@ // #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSD_OPTION@ // #define USBX_FEATURE_CDC @USBX_FEATURE_CDC_OPTION@ #define USBX_FEATURE_HID @USBX_FEATURE_HID_OPTION@ From 5bb5495444c2796b4f2b9021ff7b35d617f6052e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 00:16:02 +0100 Subject: [PATCH 143/572] Add config for 1-wire in Skyworks EVB target --- CMakeUserPresets.TEMPLATE.json | 23 ++++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 3e43b6bd05..99713440e6 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -176,6 +176,29 @@ "NF_INTEROP_ASSEMBLIES": null } }, + { + "name": "SKY_EEVB_PROTO1", + "inherits": [ + "user-local-tools", + "user-prefs", + "SL_STK3701A_preset" + ], + "cacheVariables": { + "TARGET_BOARD": { + "type": "STRING", + "value": "${presetName}" + }, + "TARGET_SERIAL_BAUDRATE": "115200", + "GECKO_FEATURE_USBD_HID": "OFF", + "GECKO_FEATURE_USBD_WINUSB": "OFF", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Adc": "OFF", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_nanoFramework.Device.OneWire": "ON", + "NF_INTEROP_ASSEMBLIES": null + } + }, { "name": "ESP32_PSRAM_REV0", "inherits": [ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif From 1a2d9b8ebeb59e11c03224ead042a22e2acb8109 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 01:51:51 +0100 Subject: [PATCH 144/572] Various fixes in usart stream and build --- CMake/Modules/FindGecko_SDK.cmake | 3 +- .../sl_iostream_init_usart_instances.c | 45 +++++++++++++++++-- 2 files changed, 42 insertions(+), 6 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 51736ce220..434c9822cc 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -158,14 +158,13 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endif() - if(HAL_WP_USE_SERIAL) + if(HAL_WP_USE_SERIAL OR HAL_USE_ONEWIRE_OPTION) list(APPEND gecko_sdk_srcs sl_iostream_usart.c) list(APPEND gecko_sdk_srcs sl_iostream_uart.c) list(APPEND gecko_sdk_srcs sl_iostream.c) list(APPEND gecko_sdk_srcs sl_iostream_handles.c) list(APPEND gecko_sdk_srcs sl_iostream_init_usart_instances.c) - endif() diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 3e4f938c5e..24a6026eac 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -58,12 +58,9 @@ static sl_power_manager_em_transition_event_info_t events_info = { static sl_power_manager_em_transition_event_handle_t events_handle; #endif -#if HAL_WP_USE_SERIAL == TRUE -sl_status_t sl_iostream_usart_init_vcom(void); -#endif - // Instance(s) handle and context variable #if HAL_WP_USE_SERIAL == TRUE +sl_status_t sl_iostream_usart_init_vcom(void); static sl_iostream_uart_t sl_iostream_vcom; sl_iostream_t *sl_iostream_vcom_handle = &sl_iostream_vcom.stream; sl_iostream_uart_t *sl_iostream_uart_vcom_handle = &sl_iostream_vcom; @@ -150,6 +147,21 @@ sl_status_t sl_iostream_usart_init_vcom(void) #endif #if HAL_USE_ONEWIRE == TRUE + +sl_status_t sl_iostream_usart_init_onewire(void); +static sl_iostream_uart_t sl_iostream_onewire; +sl_iostream_t *sl_iostream_onewire_handle = &sl_iostream_onewire.stream; +sl_iostream_uart_t *sl_iostream_uart_onewire_handle = &sl_iostream_onewire; +static sl_iostream_usart_context_t context_onewire; +static uint8_t rx_buffer_onewire[SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE]; +sl_iostream_instance_info_t sl_iostream_instance_onewire_info = { + .handle = &sl_iostream_onewire.stream, + .name = "ONEWIRE", + .type = SL_IOSTREAM_TYPE_UART, + .periph_id = SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO, + .init = sl_iostream_usart_init_onewire, +}; + sl_status_t sl_iostream_usart_init_onewire(void) { sl_status_t status; @@ -240,6 +252,8 @@ void sl_iostream_usart_init_instances(void) #endif } +#if HAL_WP_USE_SERIAL == TRUE + // VCOM IRQ Handler void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void) { @@ -251,6 +265,22 @@ void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO)(void sl_iostream_usart_irq_handler(sl_iostream_vcom.stream.context); } +#endif // HAL_WP_USE_SERIAL + +#if HAL_USE_ONEWIRE == TRUE + +// ONEWIRE IRQ Handler +void SL_IOSTREAM_USART_TX_IRQ_HANDLER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO)(void) +{ + sl_iostream_usart_irq_handler(sl_iostream_onewire.stream.context); +} + +void SL_IOSTREAM_USART_RX_IRQ_HANDLER(SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO)(void) +{ + sl_iostream_usart_irq_handler(sl_iostream_onewire.stream.context); +} + +#endif // HAL_USE_ONEWIRE #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) sl_power_manager_on_isr_exit_t sl_iostream_usart_vcom_sleep_on_isr_exit(void) @@ -289,3 +319,10 @@ void sli_iostream_on_uart_rx(sl_iostream_t *handle) { (void)handle; } + +void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate) +{ + sl_iostream_usart_context_t *usart_context = (sl_iostream_usart_context_t *)handle->context; + + USART_BaudrateAsyncSet(usart_context->usart, 0, baudrate, 0); +} From 391b7c9af7f7a23a7cb17f10a91ec6023a435c5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 01:52:52 +0100 Subject: [PATCH 145/572] More work on 1-Wire implementation --- ...noFramework_Device_OneWire_OneWireHost.cpp | 147 +++++++++++------- .../nf_dev_onewire_target.h | 2 + 2 files changed, 97 insertions(+), 52 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index ec8bd91eb9..5f6a5e0a37 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -9,15 +9,24 @@ // 1-Wire API code // ///////////////////// +#define ONEWIRE_THREAD_STACK_SIZE 256 +#define ONEWIRE_THREAD_PRIORITY 5 + // struct for working threads static OneWireFindStruct FindStruct; static bool OneWireOperationResult; -static TaskHandle_t WaitingTask; +static TX_THREAD *WaitingTask; +static uint32_t *workingThreadStack; static uint8_t LastDiscrepancy; static uint8_t LastFamilyDiscrepancy; static uint8_t LastDevice; static uint8_t SerialNum[8]; +typedef Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost OneWireHost; + +extern "C" void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate); +extern sl_iostream_t *sl_iostream_onewire_handle; + // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; @@ -37,9 +46,6 @@ HRESULT oneWireInit() sl_iostream_usart_init_onewire(); - // driver need to be deleted on soft reboot - HAL_AddSoftRebootHandler(oneWireStop); - DriverState = ONEWIRE_READY; return S_OK; @@ -49,18 +55,19 @@ uint8_t oneWireTouchReset(void) { char reset = 0xF0; uint8_t presence; + size_t bytesRead; // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) - uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 9600); + sli_iostream_change_baudrate(sl_iostream_onewire_handle, 9600); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&reset, 1); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &presence, 1, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&reset, 1); + sl_iostream_read(sl_iostream_onewire_handle, &presence, 1, &bytesRead); // set UART baud rate to 115200bps (normal comm is performed at this baud rate) - uart_set_baudrate(NF_ONEWIRE_ESP32_UART_NUM, 115200); + sli_iostream_change_baudrate(sl_iostream_onewire_handle, 115200); // check for presence pulse return (presence != reset); @@ -71,12 +78,13 @@ bool oneWireTouchBit(bool sendbit) // need to send 1-Wire write 1 or 0 according to sendbit char write = sendbit ? IWIRE_WR1 : IWIRE_WR0; uint8_t reply; + size_t bytesRead; // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)&write, 1); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, &reply, 1, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&write, 1); + sl_iostream_read(sl_iostream_onewire_handle, &reply, 1, &bytesRead); // interpret 1-Wire reply return (reply == IWIRE_RD); @@ -88,6 +96,7 @@ uint8_t oneWireTouchByte(uint8_t sendbyte) uint8_t i = 0; char writeBuffer[8]; uint8_t readBuffer[8]; + size_t bytesRead; // send byte while (send_mask) @@ -101,8 +110,8 @@ uint8_t oneWireTouchByte(uint8_t sendbyte) // flush DMA buffer to ensure cache coherency // TODO uart_flush(NF_ONEWIRE_ESP32_UART_NUM); - uart_write_bytes(NF_ONEWIRE_ESP32_UART_NUM, (const char *)writeBuffer, 8); - uart_read_bytes(NF_ONEWIRE_ESP32_UART_NUM, readBuffer, 8, 20 / portTICK_RATE_MS); + sl_iostream_write(sl_iostream_onewire_handle, (uint8_t *)&writeBuffer, 8); + sl_iostream_read(sl_iostream_onewire_handle, &readBuffer, 8, &bytesRead); // reset send mask to interpret the reply send_mask = 0x01; @@ -128,7 +137,7 @@ void oneWireRelease() { } -// compute CRC8 using running algorith (slower but saves FLASH) +// compute CRC8 using running algorithm (slower but saves FLASH) uint8_t doCrc8(uint8_t oldCrc, uint8_t x) { uint8_t crc = oldCrc; @@ -395,35 +404,33 @@ bool oneWireFindFirst(bool doReset, bool alarmOnly) } // OneWire Find First/Next working thread -static void OneWireFindWorkingThread(void *pvParameters) +static void OneWireFindWorkingThread_entry(uint32_t arg) { - OneWireFindStruct *findStruct = (OneWireFindStruct *)pvParameters; + OneWireFindStruct *findStruct = (OneWireFindStruct *)arg; OneWireOperationResult = findStruct->FindFirst ? oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly) : oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); - // fire event for 1-Wire operation completed - xTaskNotifyGive(WaitingTask); - vTaskDelete(NULL); + // fire event for 1-Wire operarion completed + Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + + // terminate this thread + tx_thread_terminate(WaitingTask); } HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) { + NANOCLR_HEADER(); + uint8_t *serialNumberPointer; CLR_RT_HeapBlock hbTimeout; CLR_INT64 *timeout; - TaskHandle_t task; - HRESULT result; + bool eventResult = true; // set an infinite timeout to wait forever for the operation to complete // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below hbTimeout.SetInteger((CLR_INT64)-1); - result = stack.SetupTimeoutFromTicks(hbTimeout, timeout); - - if (result != S_OK) - { - return result; - } + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeout)); // this is going to be used to check for the right event in case of simultaneous 1-Wire operations if (stack.m_customState == 1) @@ -436,41 +443,79 @@ HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) oneWireAquire(); // spawn working thread to perform the 1-Wire operations - WaitingTask = xTaskGetCurrentTaskHandle(); - xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); + + // 1. allocate memory for thread stack + workingThreadStack = (uint32_t *)platform_malloc(ONEWIRE_THREAD_STACK_SIZE); + + if (workingThreadStack == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // 2. create thread + uint16_t status = tx_thread_create( + WaitingTask, +#if !defined(BUILD_RTM) + (CHAR *)"1-Wire Thread", +#else + NULL, +#endif + OneWireFindWorkingThread_entry, + (uint32_t)&FindStruct, + workingThreadStack, + ONEWIRE_THREAD_STACK_SIZE, + ONEWIRE_THREAD_PRIORITY, + ONEWIRE_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } // bump custom state stack.m_customState = 2; } - // wait for 1-Wire operation complete - ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + while (eventResult) + { + if (WaitingTask->tx_thread_state == TX_TERMINATED) + { + // ONEWIRE working thread is now complete + break; + } - oneWireRelease(); + // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeout, Event_OneWireHost, eventResult)); + } - // get the result from the working thread execution - if (OneWireOperationResult) + if (eventResult) { - // update serialNumber field + // event occurred + + oneWireRelease(); - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - if (pThis == NULL) + // get the result from the working thread execution + if (OneWireOperationResult) { - return CLR_E_NULL_REFERENCE; - } + // update serialNumber field + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); - // get a pointer to the serial number field in the OneWireController instance - CLR_RT_HeapBlock_Array *serialNumberField = - pThis[Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FIELD___serialNumber] - .DereferenceArray(); + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array *serialNumberField = pThis[OneWireHost::FIELD___serialNumber].DereferenceArray(); - _ASSERTE(serialNumberField->m_numOfElements == 8); + _ASSERTE(serialNumberField->m_numOfElements == 8); - // get a pointer to the first element of the byte array - serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t *)serialNumberField->GetFirstElement(); - oneWireSerialNum(serialNumberPointer, TRUE); + oneWireSerialNum(serialNumberPointer, TRUE); + } } // pop timeout heap block from stack @@ -479,7 +524,7 @@ HRESULT FindOneDevice(CLR_RT_StackFrame &stack, bool findFirst) // set result stack.SetResult_Boolean(OneWireOperationResult); - return S_OK; + NANOCLR_NOCLEANUP(); } ////////////////////////// @@ -548,8 +593,6 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindFir HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( CLR_RT_StackFrame &stack) { - (void)stack; - NANOCLR_HEADER(); NANOCLR_CHECK_HRESULT(FindOneDevice(stack, false)); @@ -570,7 +613,7 @@ HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeD HRESULT Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost::NativeInit___VOID(CLR_RT_StackFrame &stack) { - (void)stack; + (void)stack; NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h index cb1843ef88..56f110502a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -10,6 +10,8 @@ #include #include +#include + // set missing defines #if defined(USART0) #ifndef NF_ONEWIRE_USE_USART0 From 6c9f9247fd00928221570848fd3b25817961d999 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 10:44:36 +0100 Subject: [PATCH 146/572] Adjust 1-Wire target configuration --- .../target_nf_dev_onewire_config.cpp | 27 +++---------------- .../target_nf_dev_onewire_config.h | 1 - 2 files changed, 3 insertions(+), 25 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp index 6eb0d5a2a4..949567e829 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.cpp @@ -3,27 +3,6 @@ // See LICENSE file in the project root for full license information. // -#include "target_nf_dev_onewire_config.h" -#include - -/////////// -// UART0 // -/////////// - -// pin configuration for UART4 -// port for TX pin is: GPIOC -// TX pin: is GPIOC_10 -// GPIO alternate pin function is 8 -UART_CONFIG_PINS(4, GPIOC, 10, 8) - -// buffers -// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary -// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) -#if defined(__GNUC__) -__attribute__((aligned(32))) -#endif -uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; -#if defined(__GNUC__) -__attribute__((aligned(32))) -#endif -uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h index 840f02a3de..2c21c90446 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h @@ -8,5 +8,4 @@ /////////// // enable USART0 -#define NF_ONEWIRE_STM32_UART_USE_USART0 TRUE #define GECKO_USE_USART0 TRUE From 05127bc57c3389493714ea3574610cd23190ebf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 13:12:16 +0100 Subject: [PATCH 147/572] Fix 1Wire stop --- ...f_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp | 4 ++-- .../nanoFramework.Device.OneWire/nf_dev_onewire_target.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp index 5f6a5e0a37..bd0f8b73c7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost.cpp @@ -26,6 +26,7 @@ typedef Library_nf_dev_onewire_nanoFramework_Device_OneWire_OneWireHost OneWireH extern "C" void sli_iostream_change_baudrate(sl_iostream_t *handle, uint32_t baudrate); extern sl_iostream_t *sl_iostream_onewire_handle; +extern sl_iostream_uart_t *sl_iostream_uart_onewire_handle; // Driver state. static oneWireState DriverState = ONEWIRE_UNINIT; @@ -33,8 +34,7 @@ static oneWireState DriverState = ONEWIRE_UNINIT; void oneWireStop() { // stop UART - // TODO - // uart_driver_delete(NF_ONEWIRE_ESP32_UART_NUM); + sl_iostream_uart_deinit(sl_iostream_uart_onewire_handle); // driver is stopped DriverState = ONEWIRE_STOP; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h index 56f110502a..46c79b58c5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Device.OneWire/nf_dev_onewire_target.h @@ -10,6 +10,8 @@ #include #include +#include + #include // set missing defines From f7520f576bd027468d56afe5997ac6e0505cab9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 15:40:07 +0100 Subject: [PATCH 148/572] Work on AdcController for Gecko ADC --- ...ve_nanoFramework_GiantGecko_Adc_AdcController.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 4c3949b6a6..090712bf5e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -150,9 +150,10 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // Return value to the managed application + stack.SetResult_I4(AdcChannelCount); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP_NOLABEL(); } HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: @@ -160,9 +161,12 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + int mode = stack.Arg1().NumericByRef().s4; - NANOCLR_NOCLEANUP(); + // Only support Single ended mode for now + stack.SetResult_Boolean((mode == (int)AdcChannelMode_SingleEnded)); + + NANOCLR_NOCLEANUP_NOLABEL(); } HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: From ab25eacaa995e1a5c4fea57aacb93fbbbad91602 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 21 Sep 2022 15:40:07 +0100 Subject: [PATCH 149/572] Work on AdcController for Gecko ADC --- ...ve_nanoFramework_GiantGecko_Adc_AdcController.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 4c3949b6a6..090712bf5e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -150,9 +150,10 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // Return value to the managed application + stack.SetResult_I4(AdcChannelCount); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP_NOLABEL(); } HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: @@ -160,9 +161,12 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + int mode = stack.Arg1().NumericByRef().s4; - NANOCLR_NOCLEANUP(); + // Only support Single ended mode for now + stack.SetResult_Boolean((mode == (int)AdcChannelMode_SingleEnded)); + + NANOCLR_NOCLEANUP_NOLABEL(); } HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: From 077da6ee28551e4d48fafa5f641c79c3a9af00ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 22 Sep 2022 12:45:25 +0100 Subject: [PATCH 150/572] Update declaration for Gecko ADC library --- .../nano_gg_adc_native.cpp | 8 +++++--- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h | 11 +++++------ 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index f07a0b0149..b66660ec19 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -57,13 +57,15 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, + NULL, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___BOOLEAN, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStoptContinuousConversion___BOOLEAN, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___VOID__SZARRAY_I4__I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStopContinuousConversion___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastScanSampleForChannel___I4__I4, NULL, @@ -80,7 +82,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0x175512A5, + 0x8DC59CD0, method_lookup, { 100, 1, 0, 0 } }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index 8240ccd4d4..10bc6c4366 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -163,18 +163,17 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcConfiguration struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController { static const int FIELD___syncLock = 1; - static const int FIELD___scanChannels = 2; - static const int FIELD___averageCount = 3; - static const int FIELD___continuousSamplingStarted = 4; - static const int FIELD___adcConfiguration = 5; + static const int FIELD___continuousSamplingStarted = 2; + static const int FIELD___adcConfiguration = 3; + static const int FIELD___adcChannelConfiguration = 4; NANOCLR_NATIVE_DECLARE(NativeInit___VOID); NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); NANOCLR_NATIVE_DECLARE(NativeIsChannelModeSupported___BOOLEAN__I4); NANOCLR_NATIVE_DECLARE(NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution); - NANOCLR_NATIVE_DECLARE(NativeStartContinuousConversion___BOOLEAN); - NANOCLR_NATIVE_DECLARE(NativeStoptContinuousConversion___BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeStartContinuousConversion___VOID__SZARRAY_I4__I4); + NANOCLR_NATIVE_DECLARE(NativeStopContinuousConversion___VOID); NANOCLR_NATIVE_DECLARE(NativeGetLastContinuousSamples___SZARRAY_I4); NANOCLR_NATIVE_DECLARE(NativeGetLastScanSampleForChannel___I4__I4); From 9f658fb1010a48414c8f1503303eb531ad34ea5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 22 Sep 2022 19:54:08 +0100 Subject: [PATCH 151/572] Finish work on continuous scan operation implementation --- ...anoFramework_GiantGecko_Adc_AdcChannel.cpp | 12 +- ...Framework_GiantGecko_Adc_AdcController.cpp | 357 +++++++++++++++--- .../nano_gg_adc_native_target.h | 10 + 3 files changed, 325 insertions(+), 54 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 81c485e493..2482821d3f 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -31,22 +31,12 @@ void ParseAdcChannelConfig(CLR_RT_HeapBlock *channelConfiguration, void *adcInit memcpy(adcInit, &channelInitSingle, sizeof(ADC_InitSingle_TypeDef)); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - - NANOCLR_NOCLEANUP(); -} - HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - int channelNumber; + int32_t channelNumber; NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; // ADC related variables diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 090712bf5e..3c5097bad2 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -18,50 +18,31 @@ ADC_Init_TypeDef adc1Init; bool adc1Initialized = false; #endif +NF_PAL_GECKO_ADC_CONTINUOUS_SCAN *ContinuousScanOperation; + // add typedef for AdcConfiguration to ease access and improve readability typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcConfiguration AdcConfiguration; -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( - CLR_RT_StackFrame &stack) -{ - (void)stack; - - NANOCLR_HEADER(); +extern void ParseAdcChannelConfig(CLR_RT_HeapBlock *channelConfiguration, void *adcInit); - // all required initialization for ADC is handled in OpenChannel call - - NANOCLR_NOCLEANUP_NOLABEL(); -} - -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( - CLR_RT_StackFrame &stack) +// helper function to take care of init and config ADC, if not already done +HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration, ADC_TypeDef *adcDriver) { NANOCLR_HEADER(); - int channel; NF_PAL_ADC_PORT_PIN_CHANNEL adcChannelDefinition; CMU_Clock_TypeDef adcClock; - ADC_TypeDef *adcDriver = NULL; ADC_Init_TypeDef *adcInit = NULL; bool *adcInitialized = NULL; - CLR_RT_HeapBlock *adcConfiguration; - - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); - - // Get channel from argument - channel = stack.Arg1().NumericByRef().s4; - // sanity check for existing configuration - if (channel >= AdcChannelCount) + if (channelNumber >= AdcChannelCount) { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } // grab ADC channel definition - adcChannelDefinition = AdcPortPinConfig[channel]; + adcChannelDefinition = AdcPortPinConfig[channelNumber]; // we should remove from the build the ADC options that aren't implemented // plus we have to use the default to catch invalid ADC Ids @@ -103,9 +84,6 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N #endif ) { - // get a pointer to the managed AdcConfiguration object instance - adcConfiguration = pThis[FIELD___adcConfiguration].Dereference(); - // init with default values *adcInit = ADC_INIT_DEFAULT; @@ -135,7 +113,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N adcInit->em2ClockConfig = adcEm2ClockOnDemand; #endif - // start ADC + // init ADC ADC_Init(adcDriver, adcInit); // set ADC initialized flag @@ -145,6 +123,43 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID( + CLR_RT_StackFrame &stack) +{ + (void)stack; + + NANOCLR_HEADER(); + + // all required initialization for ADC is handled in OpenChannel call + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock *adcConfiguration; + int32_t channelNumber; + ADC_TypeDef *adcDriver; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get a pointer to the managed AdcConfiguration object instance + adcConfiguration = pThis[FIELD___adcConfiguration].Dereference(); + + // Get channel from argument + channelNumber = stack.Arg1().NumericByRef().s4; + + // take care of configuring ADC, if not already done + NANOCLR_CHECK_HRESULT(OpenAdcChannel(channelNumber, adcConfiguration, adcDriver)); + + NANOCLR_NOCLEANUP(); +} + HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame &stack) { @@ -174,27 +189,232 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + CLR_RT_HeapBlock *adcSampleResolution; + CLR_RT_TypeDef_Index adcSampleResolutionTypeDef; + CLR_RT_HeapBlock *hbObj; + CLR_RT_HeapBlock &top = stack.PushValue(); + + uint16_t resolutionsCount = 0; + +#if defined(_ADC_SINGLECTRL_RES_12BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_8BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_6BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_OVS) + resolutionsCount++; +#endif + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("SampleResolution", "nanoFramework.GiantGecko.Adc", adcSampleResolutionTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, resolutionsCount, adcSampleResolutionTypeDef)); + + if (resolutionsCount > 0) + { + // get a pointer to the first object in the array (which is of type ) + adcSampleResolution = (CLR_RT_HeapBlock *)top.DereferenceArray()->GetFirstElement(); + + // create an instance of + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*adcSampleResolution, adcSampleResolutionTypeDef)); + +#if defined(_ADC_SINGLECTRL_RES_12BIT) + hbObj = adcSampleResolution->Dereference(); + hbObj->SetInteger((CLR_INT32)adcRes12Bit); + hbObj->PerformBoxingIfNeeded(); + + // move pointer to the next resolution item + adcSampleResolution++; +#endif + +#if defined(_ADC_SINGLECTRL_RES_8BIT) + hbObj = adcSampleResolution->Dereference(); + hbObj->SetInteger((CLR_INT32)adcRes8Bit); + hbObj->PerformBoxingIfNeeded(); + + // move pointer to the next resolution item + adcSampleResolution++; +#endif + +#if defined(_ADC_SINGLECTRL_RES_6BIT) + hbObj = adcSampleResolution->Dereference(); + hbObj->SetInteger((CLR_INT32)adcResOVS); + hbObj->PerformBoxingIfNeeded(); + + // move pointer to the next resolution item + adcSampleResolution++; +#endif + +#if defined(_ADC_SINGLECTRL_RES_6BIT) + // dereference the object in order to reach its fields + hbObj = adcSampleResolution->Dereference(); + hbObj->SetInteger((CLR_INT32)adcRes6Bit); + hbObj->PerformBoxingIfNeeded(); +#endif + } NANOCLR_NOCLEANUP(); } HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: - NativeStartContinuousConversion___BOOLEAN(CLR_RT_StackFrame &stack) + NativeStartContinuousConversion___VOID__SZARRAY_I4__I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + uint32_t averageCount; + uint32_t channelIndex = 0; + int32_t channelNumber; + ADC_InitScan_TypeDef channelInitScan = ADC_INITSCAN_DEFAULT; + ADC_TypeDef *adcDriver = NULL; - NANOCLR_NOCLEANUP(); + NF_PAL_ADC_PORT_PIN_CHANNEL adcChannelDefinition; + + CLR_RT_HeapBlock_Array *adcChannelsToScan; + CLR_RT_HeapBlock *adcConfiguration; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get the average count + averageCount = stack.Arg2().NumericByRef().s4; + + // sanity check (need to take at least one sample) + if (averageCount < 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a pointer to the AdcChannelConfiguration object instance + ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitScan); + // enable FIFO overflow to overwrite old data + channelInitScan.fifoOverwrite = true; + + // get a pointer to the managed AdcConfiguration object instance + adcConfiguration = pThis[FIELD___adcConfiguration].Dereference(); + + // loop through all channels + adcChannelsToScan = (CLR_RT_HeapBlock_Array *)stack.Arg1().DereferenceArray(); + + // sanity check (need to have at least one channel) + if (adcChannelsToScan->m_numOfElements < 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // alloc memory for the scan operation + ContinuousScanOperation = + (NF_PAL_GECKO_ADC_CONTINUOUS_SCAN *)platform_malloc(sizeof(NF_PAL_GECKO_ADC_CONTINUOUS_SCAN)); + + // sanity check + if (ContinuousScanOperation == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // alloc memory for the data buffer + ContinuousScanOperation->dataBuffer = + (uint32_t *)platform_malloc(adcChannelsToScan->m_numOfElements * averageCount * sizeof(uint32_t)); + + // sanity check + if (ContinuousScanOperation->dataBuffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear the data buffer + memset( + ContinuousScanOperation->dataBuffer, + 0, + adcChannelsToScan->m_numOfElements * averageCount * sizeof(uint32_t)); + + // store the number of channels + ContinuousScanOperation->channelCount = adcChannelsToScan->m_numOfElements; + // store the average count + ContinuousScanOperation->averageCount = averageCount; + + while (channelIndex < ContinuousScanOperation->channelCount) + { + channelNumber = ((CLR_RT_HeapBlock *)adcChannelsToScan->GetElement(channelIndex++))->NumericByRefConst().s4; + + // take care of configuring ADC, if not already done + NANOCLR_CHECK_HRESULT(OpenAdcChannel(channelNumber, adcConfiguration, adcDriver)); + + // grab ADC channel definition + adcChannelDefinition = AdcPortPinConfig[channelNumber]; + + // select ADC input + ADC_ScanSingleEndedInputAdd(&channelInitScan, adcScanInputGroup0, adcChannelDefinition.posSel); + } + + // set scan data valid level (DVL) to 2 + adcDriver->SCANCTRLX |= (ContinuousScanOperation->channelCount - 1) << _ADC_SCANCTRLX_DVL_SHIFT; + + // clear ADC Scan FIFO + adcDriver->SCANFIFOCLEAR = ADC_SCANFIFOCLEAR_SCANFIFOCLEAR; + + // start ADC scan + ADC_InitScan(adcDriver, &channelInitScan); + + // clearn and enable Scan interrupts + ADC_IntClear(adcDriver, ADC_IEN_SCAN); + ADC_IntEnable(adcDriver, ADC_IEN_SCAN); + + // Enable ADC Interrupts + NVIC_ClearPendingIRQ(ADC0_IRQn); + NVIC_EnableIRQ(ADC0_IRQn); + + // done here: update flag + pThis[FIELD___continuousSamplingStarted].NumericByRef().u1 = (CLR_UINT8) true; + + NANOCLR_CLEANUP(); + + // clean up if needed + if (FAILED(hr)) + { + // free memory for the scan operation + if (ContinuousScanOperation != NULL) + { + if (ContinuousScanOperation->dataBuffer != NULL) + { + platform_free(ContinuousScanOperation->dataBuffer); + } + + platform_free(ContinuousScanOperation); + + ContinuousScanOperation = NULL; + } + } + + NANOCLR_CLEANUP_END(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: - NativeStoptContinuousConversion___BOOLEAN(CLR_RT_StackFrame &stack) +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStopContinuousConversion___VOID( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // disable ADC Interrupt + NVIC_DisableIRQ(ADC0_IRQn); + + // clear memory for the scan operation + platform_free(ContinuousScanOperation->dataBuffer); + platform_free(ContinuousScanOperation); + ContinuousScanOperation = NULL; + + // all good, update flag + pThis[FIELD___continuousSamplingStarted].NumericByRef().u1 = (CLR_UINT8) false; NANOCLR_NOCLEANUP(); } @@ -204,17 +424,68 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + uint64_t samplesAccumulator = 0; + + CLR_RT_HeapBlock_Array *sampleArray; + CLR_RT_HeapBlock &top = stack.PushValue(); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + top, + ContinuousScanOperation->channelCount, + g_CLR_RT_WellKnownTypes.m_Int32)); + + sampleArray = top.DereferenceArray(); + + for (uint32_t channelIndex = 0; channelIndex < ContinuousScanOperation->channelCount; channelIndex++) + { + // // Read data from ADC + // data = ADC_DataIdScanGet(ADC0, &id); + + // ContinuousScanOperation + // ->dataBuffer[i * ContinuousScanOperation->averageCount + ContinuousScanOperation->currentIndex] = data; + + // compute average + // 1. accumulate samples + for (uint32_t sampleIndex = 0; sampleIndex < ContinuousScanOperation->averageCount; sampleIndex++) + { + samplesAccumulator += + ContinuousScanOperation->dataBuffer[channelIndex * ContinuousScanOperation->averageCount + sampleIndex]; + } + + // 2. set array element with the average + ((CLR_RT_HeapBlock *)sampleArray->GetElement(channelIndex)) + ->SetInteger((CLR_INT32)(samplesAccumulator / ContinuousScanOperation->averageCount)); + } NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: - NativeGetLastScanSampleForChannel___I4__I4(CLR_RT_StackFrame &stack) +// IRQ handler for ADC0 +void ADC0_IRQHandler(void) { - NANOCLR_HEADER(); + uint32_t data, i, scanId; - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // Get ADC results + for (i = 0; i < ContinuousScanOperation->channelCount; i++) + { + // Read data from ADC + data = ADC_DataIdScanGet(ADC0, &scanId); - NANOCLR_NOCLEANUP(); + ContinuousScanOperation + ->dataBuffer[i * ContinuousScanOperation->averageCount + ContinuousScanOperation->currentIndex] = data; + } + + // increment the index + ContinuousScanOperation->currentIndex++; + + // check index + if (ContinuousScanOperation->currentIndex == ContinuousScanOperation->averageCount) + { + // reset index + ContinuousScanOperation->currentIndex = 0; + } + + // Start next ADC conversion + ADC_Start(ADC0, adcStartScan); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h index 40a908ad0e..f3392d79a1 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h @@ -33,8 +33,18 @@ typedef struct ADC_PosSel_TypeDef posSel; } NF_PAL_ADC_PORT_PIN_CHANNEL; +typedef struct +{ + uint8_t channelCount; + uint32_t *dataBuffer; + uint32_t averageCount; + uint32_t currentIndex; +} NF_PAL_GECKO_ADC_CONTINUOUS_SCAN; + + extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; extern const int AdcChannelCount; +extern NF_PAL_GECKO_ADC_CONTINUOUS_SCAN* ContinuousScanOperation; #if GECKO_USE_ADC0 extern ADC_Init_TypeDef adc0Init; From b907ab569bde1efe8dbc1dcaae4ceb1b46a80e66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 00:19:37 +0100 Subject: [PATCH 152/572] Update Gecko ADC declaration --- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp | 4 +--- .../nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h | 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index b66660ec19..c47bf51e93 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -14,7 +14,6 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::get_LastContinuousValue___I4, NULL, NULL, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::NativeReadValue___I4__I4, @@ -67,7 +66,6 @@ static const CLR_RT_MethodHandler method_lookup[] = Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___VOID__SZARRAY_I4__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStopContinuousConversion___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastScanSampleForChannel___I4__I4, NULL, NULL, NULL, @@ -82,7 +80,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0x8DC59CD0, + 0x0516D85F, method_lookup, { 100, 1, 0, 0 } }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index 10bc6c4366..de41962ad8 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -130,7 +130,6 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel static const int FIELD___channelNumber = 4; static const int FIELD___adcChannelConfiguration = 5; - NANOCLR_NATIVE_DECLARE(get_LastContinuousValue___I4); NANOCLR_NATIVE_DECLARE(NativeReadValue___I4__I4); NANOCLR_NATIVE_DECLARE(NativeDisposeChannel___VOID); @@ -175,7 +174,6 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController NANOCLR_NATIVE_DECLARE(NativeStartContinuousConversion___VOID__SZARRAY_I4__I4); NANOCLR_NATIVE_DECLARE(NativeStopContinuousConversion___VOID); NANOCLR_NATIVE_DECLARE(NativeGetLastContinuousSamples___SZARRAY_I4); - NANOCLR_NATIVE_DECLARE(NativeGetLastScanSampleForChannel___I4__I4); //--// }; From 1b2620113ab4899cbcbcc70af5b52232fa0b0949 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 01:24:35 +0100 Subject: [PATCH 153/572] Add dummy headers to allow building with/without ADC and Gecko ADC --- .../_nanoCLR/System.Device.Adc/nano_gg_adc_native_target.h | 6 ++++++ .../sys_dev_adc_native_target.h | 6 ++++++ 2 files changed, 12 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/nano_gg_adc_native_target.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/sys_dev_adc_native_target.h diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/nano_gg_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/nano_gg_adc_native_target.h new file mode 100644 index 0000000000..c032386018 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Adc/nano_gg_adc_native_target.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// need to have this here to keep the includes happy diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/sys_dev_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/sys_dev_adc_native_target.h new file mode 100644 index 0000000000..c032386018 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/sys_dev_adc_native_target.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// need to have this here to keep the includes happy From 499d2f0da743d07731b988ad26fa0ec86624c56e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 01:24:46 +0100 Subject: [PATCH 154/572] Fix guard define --- .../nano_gg_adc_native_target.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h index f3392d79a1..adba03e347 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_target.h @@ -3,8 +3,8 @@ // See LICENSE file in the project root for full license information. // -#ifndef SYS_DEV_ADC_NATIVE_TARGET_H -#define SYS_DEV_ADC_NATIVE_TARGET_H +#ifndef NANO_GG_ADC_NATIVE_TARGET_H +#define NANO_GG_ADC_NATIVE_TARGET_H #include #include @@ -56,4 +56,4 @@ extern bool adc1Initialized; #endif -#endif // SYS_DEV_ADC_NATIVE_TARGET_H +#endif // NANO_GG_ADC_NATIVE_TARGET_H From 2bc860ef14807d43c097cb7c99ddbabf3088b117 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 01:25:03 +0100 Subject: [PATCH 155/572] Fix define checks for Gecko ADC --- targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 0c7e925eef..af0f46213c 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -30,6 +30,7 @@ extern void DeInitPwm(); #if (GECKO_USE_ADC0 == TRUE) || (GECKO_USE_ADC1 == TRUE) #include +#include #endif // global mutex protecting the internal state of the interpreter, including event flags @@ -131,12 +132,13 @@ void nanoHAL_Initialize() #endif -#if GECKO_USE_ADC0 +#if (GECKO_USE_ADC0 == TRUE) && defined(NANO_GG_ADC_NATIVE_TARGET_H) adc0Initialized = false; #endif -#if GECKO_USE_ADC1 +#if (GECKO_USE_ADC1 == TRUE) && defined(NANO_GG_ADC_NATIVE_TARGET_H) adc1Initialized = false; #endif + // #if (HAL_USE_UART == TRUE) // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) @@ -271,11 +273,11 @@ void nanoHAL_Uninitialize() nanoSPI_Uninitialize(); #endif -#if GECKO_USE_ADC0 +#if (GECKO_USE_ADC0 == TRUE) && defined(NANO_GG_ADC_NATIVE_TARGET_H) ADC_Reset(ADC0); adc0Initialized = false; #endif -#if GECKO_USE_ADC1 +#if (GECKO_USE_ADC1 == TRUE) && defined(NANO_GG_ADC_NATIVE_TARGET_H) ADC_Reset(ADC1); adc1Initialized = false; #endif From 6b63ab2f276dda69a734b5bb9c886a84c0d81531 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 01:27:22 +0100 Subject: [PATCH 156/572] Enable more nano APIs for Gecko STK target --- CMakePresets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakePresets.json b/CMakePresets.json index 4fec11b28e..56bae8761e 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -304,8 +304,8 @@ "API_nanoFramework.Device.OneWire": "OFF", "API_nanoFramework.Devices.Can": "OFF", "API_nanoFramework.ResourceManager": "OFF", - "API_nanoFramework.System.Collections": "OFF", - "API_nanoFramework.System.Text": "OFF", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", "API_nanoFramework.GiantGecko.Adc": "OFF", "API_Windows.Storage": "OFF", "API_nanoFramework.Graphics": "OFF" From 73c667ea2ca237eb2dbfc3755cf4c378a0b396c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 17:51:24 +0100 Subject: [PATCH 157/572] Add ASSERT in GC code - Having this check helps debug problems in allocation. --- src/CLR/Core/CLR_RT_HeapCluster.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/CLR/Core/CLR_RT_HeapCluster.cpp b/src/CLR/Core/CLR_RT_HeapCluster.cpp index 8b87ad95f0..2fe089a673 100644 --- a/src/CLR/Core/CLR_RT_HeapCluster.cpp +++ b/src/CLR/Core/CLR_RT_HeapCluster.cpp @@ -221,6 +221,9 @@ void CLR_RT_HeapCluster::RecoverFromGC() int len = next->DataSize(); + // length of the block can not be 0, so something very wrong happened + _ASSERTE(len > 0); + next += len; lenTot += len; From 2b513ce9be3eaf0122d17780f21b2b1c48995a16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 17:56:55 +0100 Subject: [PATCH 158/572] Fix implementation of NativeGetLastContinuousSamples. --- ...noFramework_GiantGecko_Adc_AdcController.cpp | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 3c5097bad2..788a0713cc 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -424,27 +424,22 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: { NANOCLR_HEADER(); + CLR_INT32 *sample = NULL; + // assuming that, at 12 bits resolution, this will be enough to hold the average uint64_t samplesAccumulator = 0; CLR_RT_HeapBlock_Array *sampleArray; - CLR_RT_HeapBlock &top = stack.PushValue(); // create an array of NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( - top, + stack.PushValueAndClear(), ContinuousScanOperation->channelCount, g_CLR_RT_WellKnownTypes.m_Int32)); - sampleArray = top.DereferenceArray(); + sampleArray = stack.TopValue().DereferenceArray(); for (uint32_t channelIndex = 0; channelIndex < ContinuousScanOperation->channelCount; channelIndex++) { - // // Read data from ADC - // data = ADC_DataIdScanGet(ADC0, &id); - - // ContinuousScanOperation - // ->dataBuffer[i * ContinuousScanOperation->averageCount + ContinuousScanOperation->currentIndex] = data; - // compute average // 1. accumulate samples for (uint32_t sampleIndex = 0; sampleIndex < ContinuousScanOperation->averageCount; sampleIndex++) @@ -454,8 +449,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: } // 2. set array element with the average - ((CLR_RT_HeapBlock *)sampleArray->GetElement(channelIndex)) - ->SetInteger((CLR_INT32)(samplesAccumulator / ContinuousScanOperation->averageCount)); + sample = ((CLR_INT32 *)sampleArray->GetElement(channelIndex)); + *sample = (CLR_INT32)(samplesAccumulator / ContinuousScanOperation->averageCount); } NANOCLR_NOCLEANUP(); From 439bdb5f76336d1a6ba1c5d0797714806b01cb74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 18:03:50 +0100 Subject: [PATCH 159/572] Fix implementation of NativeGetSupportedResolutionsInBits. - Update declaration of GEcko ADC assembly. --- .../nano_gg_adc_native.cpp | 6 +- .../nano_gg_adc_native.h | 24 +++++--- ...Framework_GiantGecko_Adc_AdcController.cpp | 56 +++++++------------ 3 files changed, 40 insertions(+), 46 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index c47bf51e93..f773064392 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -60,12 +60,12 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___VOID__SZARRAY_I4__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStopContinuousConversion___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___STATIC__I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution, NULL, NULL, NULL, @@ -80,7 +80,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0x0516D85F, + 0x1B5683C1, method_lookup, { 100, 1, 0, 0 } }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index de41962ad8..0f9c5f91c1 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -11,6 +11,12 @@ #include #include +typedef enum __nfpack AdcChannelMode +{ + AdcChannelMode_SingleEnded = 0, + AdcChannelMode_Differential = 1, +} AdcChannelMode; + typedef enum __nfpack AquisitionTime { AquisitionTime__1Cyle = 1, @@ -74,6 +80,13 @@ typedef enum __nfpack ReferenceVoltage ReferenceVoltage_SingleEndedExternalPin6 = 4, ReferenceVoltage_DiffExternalPin6And7 = 5, ReferenceVoltage_Unbuffered2Vdd = 6, + ReferenceVoltage_InternalBandgap = 128, + ReferenceVoltage_ScaledAvdd = 129, + ReferenceVoltage_ScaledSingleEndedExternalPin6 = 130, + ReferenceVoltage_RawSingleEndedExternalPin6 = 131, + ReferenceVoltage_EntropyGeneration = 132, + ReferenceVoltage_ScaledExternalPin6And7 = 133, + ReferenceVoltage_RawExternalPin6And7 = 134, } ReferenceVoltage; typedef enum __nfpack SampleResolution @@ -117,12 +130,6 @@ typedef enum __nfpack WarmUpMode WarmUpMode_KeepAdcWarm = 3, } WarmUpMode; -typedef enum __nfpack AdcChannelMode -{ - AdcChannelMode_SingleEnded = 0, - AdcChannelMode_Differential = 1, -} AdcChannelMode; - struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel { static const int FIELD___syncLock = 2; @@ -168,12 +175,13 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController NANOCLR_NATIVE_DECLARE(NativeInit___VOID); NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); - NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); NANOCLR_NATIVE_DECLARE(NativeIsChannelModeSupported___BOOLEAN__I4); - NANOCLR_NATIVE_DECLARE(NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution); NANOCLR_NATIVE_DECLARE(NativeStartContinuousConversion___VOID__SZARRAY_I4__I4); NANOCLR_NATIVE_DECLARE(NativeStopContinuousConversion___VOID); NANOCLR_NATIVE_DECLARE(NativeGetLastContinuousSamples___SZARRAY_I4); + NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___STATIC__I4); + NANOCLR_NATIVE_DECLARE( + NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution); //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 788a0713cc..aaa1c21da5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -160,7 +160,7 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___STATIC__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -185,14 +185,13 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: } HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: - NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) + NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - CLR_RT_HeapBlock *adcSampleResolution; CLR_RT_TypeDef_Index adcSampleResolutionTypeDef; - CLR_RT_HeapBlock *hbObj; - CLR_RT_HeapBlock &top = stack.PushValue(); + CLR_RT_HeapBlock_Array *supportedResolutions; + CLR_INT32 *resolution = NULL; uint16_t resolutionsCount = 0; @@ -214,49 +213,36 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: g_CLR_RT_TypeSystem.FindTypeDef("SampleResolution", "nanoFramework.GiantGecko.Adc", adcSampleResolutionTypeDef); // create an array of - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, resolutionsCount, adcSampleResolutionTypeDef)); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + stack.PushValueAndClear(), + resolutionsCount, + adcSampleResolutionTypeDef)); + + // the code below is assigning INT32 values to the elements, which aren't exactly the same as the enum values + // but the enum values are the same as the INT32 values, so it's ok if (resolutionsCount > 0) { - // get a pointer to the first object in the array (which is of type ) - adcSampleResolution = (CLR_RT_HeapBlock *)top.DereferenceArray()->GetFirstElement(); - - // create an instance of - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*adcSampleResolution, adcSampleResolutionTypeDef)); + supportedResolutions = stack.TopValue().DereferenceArray(); #if defined(_ADC_SINGLECTRL_RES_12BIT) - hbObj = adcSampleResolution->Dereference(); - hbObj->SetInteger((CLR_INT32)adcRes12Bit); - hbObj->PerformBoxingIfNeeded(); - - // move pointer to the next resolution item - adcSampleResolution++; + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes12Bit; #endif #if defined(_ADC_SINGLECTRL_RES_8BIT) - hbObj = adcSampleResolution->Dereference(); - hbObj->SetInteger((CLR_INT32)adcRes8Bit); - hbObj->PerformBoxingIfNeeded(); - - // move pointer to the next resolution item - adcSampleResolution++; + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes8Bit; #endif #if defined(_ADC_SINGLECTRL_RES_6BIT) - hbObj = adcSampleResolution->Dereference(); - hbObj->SetInteger((CLR_INT32)adcResOVS); - hbObj->PerformBoxingIfNeeded(); - - // move pointer to the next resolution item - adcSampleResolution++; + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes6Bit; #endif -#if defined(_ADC_SINGLECTRL_RES_6BIT) - // dereference the object in order to reach its fields - hbObj = adcSampleResolution->Dereference(); - hbObj->SetInteger((CLR_INT32)adcRes6Bit); - hbObj->PerformBoxingIfNeeded(); +#if defined(_ADC_SINGLECTRL_RES_OVS) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcResOVS; #endif } From e979d74eb3193e20afaa1d0ec1670ae532f55d52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 18:59:03 +0100 Subject: [PATCH 160/572] Fix order of functions to match declaration --- ...Framework_GiantGecko_Adc_AdcController.cpp | 152 +++++++++--------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index aaa1c21da5..ef699f796a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -160,17 +160,6 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___STATIC__I4( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - // Return value to the managed application - stack.SetResult_I4(AdcChannelCount); - - NANOCLR_NOCLEANUP_NOLABEL(); -} - HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NativeIsChannelModeSupported___BOOLEAN__I4(CLR_RT_StackFrame &stack) { @@ -184,71 +173,6 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NANOCLR_NOCLEANUP_NOLABEL(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: - NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - CLR_RT_TypeDef_Index adcSampleResolutionTypeDef; - CLR_RT_HeapBlock_Array *supportedResolutions; - CLR_INT32 *resolution = NULL; - - uint16_t resolutionsCount = 0; - -#if defined(_ADC_SINGLECTRL_RES_12BIT) - resolutionsCount++; -#endif -#if defined(_ADC_SINGLECTRL_RES_8BIT) - resolutionsCount++; -#endif -#if defined(_ADC_SINGLECTRL_RES_6BIT) - resolutionsCount++; -#endif -#if defined(_ADC_SINGLECTRL_RES_OVS) - resolutionsCount++; -#endif - - // start composing the reply - // find type definition, don't bother checking the result as it exists for sure - g_CLR_RT_TypeSystem.FindTypeDef("SampleResolution", "nanoFramework.GiantGecko.Adc", adcSampleResolutionTypeDef); - - // create an array of - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( - stack.PushValueAndClear(), - resolutionsCount, - adcSampleResolutionTypeDef)); - - // the code below is assigning INT32 values to the elements, which aren't exactly the same as the enum values - // but the enum values are the same as the INT32 values, so it's ok - - if (resolutionsCount > 0) - { - supportedResolutions = stack.TopValue().DereferenceArray(); - -#if defined(_ADC_SINGLECTRL_RES_12BIT) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcRes12Bit; -#endif - -#if defined(_ADC_SINGLECTRL_RES_8BIT) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcRes8Bit; -#endif - -#if defined(_ADC_SINGLECTRL_RES_6BIT) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcRes6Bit; -#endif - -#if defined(_ADC_SINGLECTRL_RES_OVS) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcResOVS; -#endif - } - - NANOCLR_NOCLEANUP(); -} - HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NativeStartContinuousConversion___VOID__SZARRAY_I4__I4(CLR_RT_StackFrame &stack) { @@ -442,6 +366,82 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NANOCLR_NOCLEANUP(); } +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___STATIC__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // Return value to the managed application + stack.SetResult_I4(AdcChannelCount); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index adcSampleResolutionTypeDef; + CLR_RT_HeapBlock_Array *supportedResolutions; + CLR_INT32 *resolution = NULL; + + uint16_t resolutionsCount = 0; + +#if defined(_ADC_SINGLECTRL_RES_12BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_8BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_6BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_OVS) + resolutionsCount++; +#endif + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("SampleResolution", "nanoFramework.GiantGecko.Adc", adcSampleResolutionTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + stack.PushValueAndClear(), + resolutionsCount, + adcSampleResolutionTypeDef)); + + // the code below is assigning INT32 values to the elements, which aren't exactly the same as the enum values + // but the enum values are the same as the INT32 values, so it's ok + + if (resolutionsCount > 0) + { + supportedResolutions = stack.TopValue().DereferenceArray(); + +#if defined(_ADC_SINGLECTRL_RES_12BIT) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes12Bit; +#endif + +#if defined(_ADC_SINGLECTRL_RES_8BIT) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes8Bit; +#endif + +#if defined(_ADC_SINGLECTRL_RES_6BIT) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes6Bit; +#endif + +#if defined(_ADC_SINGLECTRL_RES_OVS) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcResOVS; +#endif + } + + NANOCLR_NOCLEANUP(); +} + // IRQ handler for ADC0 void ADC0_IRQHandler(void) { From fb2f4ca7f31988bc78323cd95be565f2c52a9022 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Sep 2022 19:03:59 +0100 Subject: [PATCH 161/572] Revert changes in declaration of Gecko ADC --- .../nano_gg_adc_native.cpp | 6 +- .../nano_gg_adc_native.h | 5 +- ...Framework_GiantGecko_Adc_AdcController.cpp | 152 +++++++++--------- 3 files changed, 81 insertions(+), 82 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp index f773064392..c47bf51e93 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.cpp @@ -60,12 +60,12 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeInit___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeOpenChannel___VOID__I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4, + Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStartContinuousConversion___VOID__SZARRAY_I4__I4, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeStopContinuousConversion___VOID, Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetLastContinuousSamples___SZARRAY_I4, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___STATIC__I4, - Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution, NULL, NULL, NULL, @@ -80,7 +80,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_GiantGecko_Adc = { "nanoFramework.GiantGecko.Adc", - 0x1B5683C1, + 0x0516D85F, method_lookup, { 100, 1, 0, 0 } }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h index 0f9c5f91c1..d93c33bf22 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native.h @@ -175,13 +175,12 @@ struct Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController NANOCLR_NATIVE_DECLARE(NativeInit___VOID); NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); NANOCLR_NATIVE_DECLARE(NativeIsChannelModeSupported___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution); NANOCLR_NATIVE_DECLARE(NativeStartContinuousConversion___VOID__SZARRAY_I4__I4); NANOCLR_NATIVE_DECLARE(NativeStopContinuousConversion___VOID); NANOCLR_NATIVE_DECLARE(NativeGetLastContinuousSamples___SZARRAY_I4); - NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___STATIC__I4); - NANOCLR_NATIVE_DECLARE( - NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution); //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index ef699f796a..6829205a4d 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -160,6 +160,17 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::N NANOCLR_NOCLEANUP(); } +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // Return value to the managed application + stack.SetResult_I4(AdcChannelCount); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NativeIsChannelModeSupported___BOOLEAN__I4(CLR_RT_StackFrame &stack) { @@ -173,6 +184,71 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NANOCLR_NOCLEANUP_NOLABEL(); } +HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: + NativeGetSupportedResolutionsInBits___SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index adcSampleResolutionTypeDef; + CLR_RT_HeapBlock_Array *supportedResolutions; + CLR_INT32 *resolution = NULL; + + uint16_t resolutionsCount = 0; + +#if defined(_ADC_SINGLECTRL_RES_12BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_8BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_6BIT) + resolutionsCount++; +#endif +#if defined(_ADC_SINGLECTRL_RES_OVS) + resolutionsCount++; +#endif + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("SampleResolution", "nanoFramework.GiantGecko.Adc", adcSampleResolutionTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + stack.PushValueAndClear(), + resolutionsCount, + adcSampleResolutionTypeDef)); + + // the code below is assigning INT32 values to the elements, which aren't exactly the same as the enum values + // but the enum values are the same as the INT32 values, so it's ok + + if (resolutionsCount > 0) + { + supportedResolutions = stack.TopValue().DereferenceArray(); + +#if defined(_ADC_SINGLECTRL_RES_12BIT) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes12Bit; +#endif + +#if defined(_ADC_SINGLECTRL_RES_8BIT) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes8Bit; +#endif + +#if defined(_ADC_SINGLECTRL_RES_6BIT) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcRes6Bit; +#endif + +#if defined(_ADC_SINGLECTRL_RES_OVS) + resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); + *resolution = adcResOVS; +#endif + } + + NANOCLR_NOCLEANUP(); +} + HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NativeStartContinuousConversion___VOID__SZARRAY_I4__I4(CLR_RT_StackFrame &stack) { @@ -366,82 +442,6 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: NANOCLR_NOCLEANUP(); } -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController::NativeGetChannelCount___STATIC__I4( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - // Return value to the managed application - stack.SetResult_I4(AdcChannelCount); - - NANOCLR_NOCLEANUP_NOLABEL(); -} - -HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController:: - NativeGetSupportedResolutionsInBits___STATIC__SZARRAY_nanoFrameworkGiantGeckoAdcSampleResolution(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - CLR_RT_TypeDef_Index adcSampleResolutionTypeDef; - CLR_RT_HeapBlock_Array *supportedResolutions; - CLR_INT32 *resolution = NULL; - - uint16_t resolutionsCount = 0; - -#if defined(_ADC_SINGLECTRL_RES_12BIT) - resolutionsCount++; -#endif -#if defined(_ADC_SINGLECTRL_RES_8BIT) - resolutionsCount++; -#endif -#if defined(_ADC_SINGLECTRL_RES_6BIT) - resolutionsCount++; -#endif -#if defined(_ADC_SINGLECTRL_RES_OVS) - resolutionsCount++; -#endif - - // start composing the reply - // find type definition, don't bother checking the result as it exists for sure - g_CLR_RT_TypeSystem.FindTypeDef("SampleResolution", "nanoFramework.GiantGecko.Adc", adcSampleResolutionTypeDef); - - // create an array of - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( - stack.PushValueAndClear(), - resolutionsCount, - adcSampleResolutionTypeDef)); - - // the code below is assigning INT32 values to the elements, which aren't exactly the same as the enum values - // but the enum values are the same as the INT32 values, so it's ok - - if (resolutionsCount > 0) - { - supportedResolutions = stack.TopValue().DereferenceArray(); - -#if defined(_ADC_SINGLECTRL_RES_12BIT) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcRes12Bit; -#endif - -#if defined(_ADC_SINGLECTRL_RES_8BIT) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcRes8Bit; -#endif - -#if defined(_ADC_SINGLECTRL_RES_6BIT) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcRes6Bit; -#endif - -#if defined(_ADC_SINGLECTRL_RES_OVS) - resolution = (CLR_INT32 *)supportedResolutions->GetElement(--resolutionsCount); - *resolution = adcResOVS; -#endif - } - - NANOCLR_NOCLEANUP(); -} - // IRQ handler for ADC0 void ADC0_IRQHandler(void) { From 89a5d9b68b1a0d10b3a8887423d3da7f7de251fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Sep 2022 14:25:29 +0100 Subject: [PATCH 162/572] Update mscorlib declaration --- src/CLR/CorLib/corlib_native.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/CLR/CorLib/corlib_native.h b/src/CLR/CorLib/corlib_native.h index 6522e59d77..49a030483c 100644 --- a/src/CLR/CorLib/corlib_native.h +++ b/src/CLR/CorLib/corlib_native.h @@ -441,9 +441,9 @@ struct Library_corlib_native_System_Byte struct Library_corlib_native_System_Collections_ArrayList { - static const int FIELD___items = 1; static const int FIELD___size = 2; + static const int FIELD___syncRoot = 3; NANOCLR_NATIVE_DECLARE(get_Item___OBJECT__I4); NANOCLR_NATIVE_DECLARE(set_Item___VOID__I4__OBJECT); From 3399e44b445f2628c85828554f41847ef1d7ce0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Sep 2022 15:44:54 +0100 Subject: [PATCH 163/572] More work adding support for WinUSB with Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 19 +++++++++++++++++++ .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 6 ++++++ .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 4 ++-- 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 434c9822cc..60e3c4f751 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -186,6 +186,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") if(GECKO_FEATURE_USBD_WINUSB) + list(APPEND gecko_sdk_srcs sl_usbd_class_vendor_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) @@ -269,6 +270,24 @@ else() message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") endif() +################################################################### +# change required to define the description of the USB Vendor Class +file(READ + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + SL_USBD_CLASS_VENDOR_CONTENT) + + +string(REPLACE + "\"Vendor-specific class\"" + NANO_VENDOR_SPECIFIC_DESCRIPTION + SL_USBD_CLASS_VENDOR__NEW_CONTENTS + "${SL_USBD_CLASS_VENDOR_CONTENT}") + +file(WRITE + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") +#################################################################### + include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Gecko_SDK DEFAULT_MSG Gecko_SDK_INCLUDE_DIRS Gecko_SDK_SOURCES) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8bd99ba614..b1466e9991 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,6 +37,9 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -47,6 +50,9 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 152cd22a14..9b0cea2239 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -25,6 +25,7 @@ extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +extern void sli_usbd_vendor_winusb_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -178,8 +179,7 @@ void tx_application_define(void *first_unused_memory) #endif #if GECKO_FEATURE_USBD_WINUSB == TRUE -// TODO - //usb_device_winusb_app_init(); + sli_usbd_vendor_winusb_init(); #endif #if HAL_WP_USE_USB_CDC == TRUE From 3678dfba17610aabdccc30b895f163e909e4569b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 10:52:21 +0100 Subject: [PATCH 164/572] Code style fixes --- .../autogen/sl_usbd_class_hid_instances.c | 349 ++++++++---------- .../autogen/sl_usbd_class_hid_instances.h | 23 +- .../autogen/sl_usbd_class_vendor_instances.c | 116 +++--- .../autogen/sl_usbd_class_vendor_instances.h | 3 - .../autogen/sl_usbd_configuration_instances.c | 41 +- .../autogen/sl_usbd_configuration_instances.h | 2 - .../autogen/sl_usbd_class_hid_instances.c | 349 ++++++++---------- .../autogen/sl_usbd_class_hid_instances.h | 23 +- .../autogen/sl_usbd_class_vendor_instances.c | 117 +++--- .../autogen/sl_usbd_class_vendor_instances.h | 3 - .../autogen/sl_usbd_configuration_instances.c | 41 +- .../autogen/sl_usbd_configuration_instances.h | 2 - 12 files changed, 465 insertions(+), 604 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c index f80d11f2c9..33c10907fc 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c @@ -29,282 +29,259 @@ #include - //**************************************************************************** // Function declarations. - - /* callback prototypes for hid0 instance */ void sli_usbd_hid_hid0_enable(uint8_t class_nbr); void sli_usbd_hid_hid0_disable(uint8_t class_nbr); -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len); +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len); +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, - uint8_t *p_protocol); - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, - uint8_t protocol); +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); //**************************************************************************** // Global variables. - - - /* variables for mouse0 instance */ uint8_t sl_usbd_hid_hid0_number = 0; uint8_t sl_usbd_hid_hid0_default_protocol = 0; - static const uint8_t sli_usbd_hid_hid0_default_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, 0x00, - SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, - SL_USBD_HID_LOCAL_USAGE + 1, 0x09, - SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, - SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, - SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, - SL_USBD_HID_MAIN_ENDCOLLECTION, - SL_USBD_HID_MAIN_ENDCOLLECTION -}; + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { - sli_usbd_hid_hid0_enable, - sli_usbd_hid_hid0_disable, - sli_usbd_hid_hid0_get_report_desc, - sli_usbd_hid_hid0_get_phy_desc, - sli_usbd_hid_hid0_set_output_report, - sli_usbd_hid_hid0_get_feature_report, - sli_usbd_hid_hid0_set_feature_report, - sli_usbd_hid_hid0_get_protocol, - sli_usbd_hid_hid0_set_protocol, + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, }; - - //**************************************************************************** // Callback functions. - - /* callback functions for mouse0 instance */ void sli_usbd_hid_hid0_enable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_enable_event(); + sl_usbd_hid_hid0_on_enable_event(); - return; + return; } void sli_usbd_hid_hid0_disable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_disable_event(); + sl_usbd_hid_hid0_on_disable_event(); - return; + return; } -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len) +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { - (void)&class_nbr; + (void)&class_nbr; - *p_report_ptr = sli_usbd_hid_hid0_default_desc; - *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); - sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); - return; + return; } -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len) +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { - (void)&class_nbr; + (void)&class_nbr; - *p_report_ptr = NULL; - *p_report_len = 0; + *p_report_ptr = NULL; + *p_report_len = 0; - sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); - return; + return; } -void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); - return; + return; } - -void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - memset(p_report_buf, 0, report_len); + memset(p_report_buf, 0, report_len); - sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); - return; + return; } -void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); - return; + return; } -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, - uint8_t *p_protocol) +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) { - (void)&class_nbr; + (void)&class_nbr; - *p_protocol = sl_usbd_hid_hid0_default_protocol; + *p_protocol = sl_usbd_hid_hid0_default_protocol; - sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); - return; + return; } -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, - uint8_t protocol) +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_default_protocol = protocol; + sl_usbd_hid_hid0_default_protocol = protocol; - sl_usbd_hid_hid0_on_set_protocol_event(protocol); + sl_usbd_hid_hid0_on_set_protocol_event(protocol); - return; + return; } - //**************************************************************************** // Global functions. - - /* initialize hid0 instance */ void sli_usbd_hid_hid0_init() { - sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; - - uint8_t subclass = 0; - uint8_t protocol = 0; - - uint16_t interval_in = 0; - uint16_t interval_out = 0; - bool ctrl_rd_en = true; - - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_HID_HID0_CONFIGURATIONS; - - /* read subclass, protocol, and country codes */ - subclass = SL_USBD_HID_HID0_SUBCLASS; - protocol = SL_USBD_HID_HID0_PROTOCOL; - country = SL_USBD_HID_HID0_COUNTRY_CODE; - - /* read endpoint parameters */ - interval_in = SL_USBD_HID_HID0_INTERVAL_IN; - interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; - ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; - - /* create HID instance */ - sl_usbd_hid_create_instance(subclass, - protocol, - country, - interval_in, - interval_out, - ctrl_rd_en, - &sli_usbd_hid_hid0_callbacks, - &class_number); - - /* store class number globally */ - sl_usbd_hid_hid0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_hid_add_to_configuration(class_number, config_number); + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); } - - - /* next token */ - token = strtok(NULL, ", "); - } } - diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h index 1243386c7e..fa9e5b853a 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h @@ -13,31 +13,20 @@ extern uint8_t sl_usbd_hid_hid0_number; - /* event handlers for all HID instances */ __WEAK void sl_usbd_hid_hid0_on_enable_event(void); __WEAK void sl_usbd_hid_hid0_on_disable_event(void); -__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, - uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, - uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); __WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); -__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); - +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); /* init functions for all HID instances */ void sli_usbd_hid_hid0_init(void); - #endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c index 4a5482daad..574a69a1cf 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c @@ -9,7 +9,6 @@ #include "sl_status.h" - #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wundef" @@ -32,142 +31,117 @@ #include "sl_usbd_class_winusb_config.h" - //**************************************************************************** // Function declarations. - - - /* callback prototypes for winusb instance */ void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, - const sl_usbd_setup_req_t *p_setup_req); - - - +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); //**************************************************************************** // Global variables. - - - /* variables for winusb instance */ uint8_t sl_usbd_vendor_winusb_number = 0; sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { - sli_usbd_vendor_winusb_enable, - sli_usbd_vendor_winusb_disable, - sli_usbd_vendor_winusb_setup_req, + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, }; - - //**************************************************************************** // Callback functions. - - - void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_enable_event(); + sl_usbd_vendor_winusb_on_enable_event(); - return; + return; } void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_disable_event(); + sl_usbd_vendor_winusb_on_disable_event(); - return; + return; } -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, - const sl_usbd_setup_req_t *p_setup_req) +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); - return; + return; } - //**************************************************************************** // Global functions. - - /* initialize winusb instance */ void sli_usbd_vendor_winusb_init() { - bool intr_en = true; - uint16_t interval = 0; + bool intr_en = true; + uint16_t interval = 0; - uint8_t class_number = 0; - uint8_t config_number = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; + char *configs = NULL; + char *token = NULL; - /* configs to attach the class instance to */ - configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; - /* read interrupt enable flag */ - intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; - /* read interval */ - interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; - /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, - interval, - &sli_usbd_vendor_winusb_callbacks, - &class_number); + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); - /* store class number globally */ - sl_usbd_vendor_winusb_number = class_number; + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); - /* loop over tokens */ - while (token != NULL) { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); - } - + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } - /* next token */ - token = strtok(NULL, ", "); - } + /* next token */ + token = strtok(NULL, ", "); + } } void sl_usbd_vendor_winusb_on_enable_event(void) { - } void sl_usbd_vendor_winusb_on_disable_event(void) { - } void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) { - } diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h index 1cc98931e6..0d411ca785 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h @@ -13,17 +13,14 @@ extern uint8_t sl_usbd_vendor_winusb_number; - /* event handlers for all vendor instances */ __WEAK void sl_usbd_vendor_winusb_on_enable_event(void); __WEAK void sl_usbd_vendor_winusb_on_disable_event(void); __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); - /* init functions for all vendor instances */ void sli_usbd_vendor_winusb_init(void); - #endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c index 7427de8c50..18f8c70f9d 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c @@ -27,7 +27,6 @@ #include - //**************************************************************************** // Global variables. @@ -35,42 +34,38 @@ uint8_t sl_usbd_configuration_config0_number = 0; - //**************************************************************************** // Global functions. - - /* initialize config0 instance */ void sli_usbd_configuration_config0_init() { - uint8_t attrib = 0; - uint16_t power = 0; - sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; - const char *name = NULL; - uint8_t number = 0; + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; - /* configuration attributes */ + /* configuration attributes */ #if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 - attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; #endif #if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 - attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; #endif - /* configuration maximum power (mA) */ - power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; - /* configuration speed */ - speed = SL_USBD_DEVICE_SPEED_FULL; + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; - /* configuration name */ - name = SL_USB_CONFIGURATION_CONFIG0_NAME; + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; - /* create the configuration descriptor */ - sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); - /* store the configuration number globally */ - sl_usbd_configuration_config0_number = number; + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; } - diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h index 500dd508c3..07726e93fe 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h @@ -11,10 +11,8 @@ extern uint8_t sl_usbd_configuration_config0_number; - /* init functions for all configuration instances */ void sli_usbd_configuration_config0_init(void); - #endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c index f80d11f2c9..33c10907fc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -29,282 +29,259 @@ #include - //**************************************************************************** // Function declarations. - - /* callback prototypes for hid0 instance */ void sli_usbd_hid_hid0_enable(uint8_t class_nbr); void sli_usbd_hid_hid0_disable(uint8_t class_nbr); -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len); +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len); +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, - uint8_t *p_protocol); - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, - uint8_t protocol); +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); //**************************************************************************** // Global variables. - - - /* variables for mouse0 instance */ uint8_t sl_usbd_hid_hid0_number = 0; uint8_t sl_usbd_hid_hid0_default_protocol = 0; - static const uint8_t sli_usbd_hid_hid0_default_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, 0x00, - SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, - SL_USBD_HID_LOCAL_USAGE + 1, 0x09, - SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, - SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, - SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, - SL_USBD_HID_MAIN_ENDCOLLECTION, - SL_USBD_HID_MAIN_ENDCOLLECTION -}; + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { - sli_usbd_hid_hid0_enable, - sli_usbd_hid_hid0_disable, - sli_usbd_hid_hid0_get_report_desc, - sli_usbd_hid_hid0_get_phy_desc, - sli_usbd_hid_hid0_set_output_report, - sli_usbd_hid_hid0_get_feature_report, - sli_usbd_hid_hid0_set_feature_report, - sli_usbd_hid_hid0_get_protocol, - sli_usbd_hid_hid0_set_protocol, + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, }; - - //**************************************************************************** // Callback functions. - - /* callback functions for mouse0 instance */ void sli_usbd_hid_hid0_enable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_enable_event(); + sl_usbd_hid_hid0_on_enable_event(); - return; + return; } void sli_usbd_hid_hid0_disable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_disable_event(); + sl_usbd_hid_hid0_on_disable_event(); - return; + return; } -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len) +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { - (void)&class_nbr; + (void)&class_nbr; - *p_report_ptr = sli_usbd_hid_hid0_default_desc; - *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); - sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); - return; + return; } -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len) +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { - (void)&class_nbr; + (void)&class_nbr; - *p_report_ptr = NULL; - *p_report_len = 0; + *p_report_ptr = NULL; + *p_report_len = 0; - sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); - return; + return; } -void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); - return; + return; } - -void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - memset(p_report_buf, 0, report_len); + memset(p_report_buf, 0, report_len); - sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); - return; + return; } -void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); - return; + return; } -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, - uint8_t *p_protocol) +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) { - (void)&class_nbr; + (void)&class_nbr; - *p_protocol = sl_usbd_hid_hid0_default_protocol; + *p_protocol = sl_usbd_hid_hid0_default_protocol; - sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); - return; + return; } -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, - uint8_t protocol) +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_default_protocol = protocol; + sl_usbd_hid_hid0_default_protocol = protocol; - sl_usbd_hid_hid0_on_set_protocol_event(protocol); + sl_usbd_hid_hid0_on_set_protocol_event(protocol); - return; + return; } - //**************************************************************************** // Global functions. - - /* initialize hid0 instance */ void sli_usbd_hid_hid0_init() { - sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; - - uint8_t subclass = 0; - uint8_t protocol = 0; - - uint16_t interval_in = 0; - uint16_t interval_out = 0; - bool ctrl_rd_en = true; - - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_HID_HID0_CONFIGURATIONS; - - /* read subclass, protocol, and country codes */ - subclass = SL_USBD_HID_HID0_SUBCLASS; - protocol = SL_USBD_HID_HID0_PROTOCOL; - country = SL_USBD_HID_HID0_COUNTRY_CODE; - - /* read endpoint parameters */ - interval_in = SL_USBD_HID_HID0_INTERVAL_IN; - interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; - ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; - - /* create HID instance */ - sl_usbd_hid_create_instance(subclass, - protocol, - country, - interval_in, - interval_out, - ctrl_rd_en, - &sli_usbd_hid_hid0_callbacks, - &class_number); - - /* store class number globally */ - sl_usbd_hid_hid0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_hid_add_to_configuration(class_number, config_number); + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); } - - - /* next token */ - token = strtok(NULL, ", "); - } } - diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h index 1243386c7e..fa9e5b853a 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h @@ -13,31 +13,20 @@ extern uint8_t sl_usbd_hid_hid0_number; - /* event handlers for all HID instances */ __WEAK void sl_usbd_hid_hid0_on_enable_event(void); __WEAK void sl_usbd_hid_hid0_on_disable_event(void); -__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, - uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, - uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); __WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); -__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); - +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); /* init functions for all HID instances */ void sli_usbd_hid_hid0_init(void); - #endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c index 4a5482daad..f4a864b429 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -9,7 +9,6 @@ #include "sl_status.h" - #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wundef" @@ -32,142 +31,118 @@ #include "sl_usbd_class_winusb_config.h" - //**************************************************************************** // Function declarations. - - - /* callback prototypes for winusb instance */ void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, - const sl_usbd_setup_req_t *p_setup_req); - - - +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); //**************************************************************************** // Global variables. - - - /* variables for winusb instance */ uint8_t sl_usbd_vendor_winusb_number = 0; sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { - sli_usbd_vendor_winusb_enable, - sli_usbd_vendor_winusb_disable, - sli_usbd_vendor_winusb_setup_req, + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, }; - - //**************************************************************************** // Callback functions. - - - void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_enable_event(); + sl_usbd_vendor_winusb_on_enable_event(); - return; + return; } void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_disable_event(); + sl_usbd_vendor_winusb_on_disable_event(); - return; + return; } -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, - const sl_usbd_setup_req_t *p_setup_req) +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); - return; + return; } - //**************************************************************************** // Global functions. - - /* initialize winusb instance */ void sli_usbd_vendor_winusb_init() { - bool intr_en = true; - uint16_t interval = 0; + bool intr_en = true; + uint16_t interval = 0; - uint8_t class_number = 0; - uint8_t config_number = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; + char *configs = NULL; + char *token = NULL; - /* configs to attach the class instance to */ - configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; - /* read interrupt enable flag */ - intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; - /* read interval */ - interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; - /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, - interval, - &sli_usbd_vendor_winusb_callbacks, - &class_number); + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); - /* store class number globally */ - sl_usbd_vendor_winusb_number = class_number; + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); - /* loop over tokens */ - while (token != NULL) { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); - } - + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } - /* next token */ - token = strtok(NULL, ", "); - } + /* next token */ + token = strtok(NULL, ", "); + } } void sl_usbd_vendor_winusb_on_enable_event(void) { - } void sl_usbd_vendor_winusb_on_disable_event(void) { - } void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) { - + (void)&p_setup_req; } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h index 1cc98931e6..0d411ca785 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h @@ -13,17 +13,14 @@ extern uint8_t sl_usbd_vendor_winusb_number; - /* event handlers for all vendor instances */ __WEAK void sl_usbd_vendor_winusb_on_enable_event(void); __WEAK void sl_usbd_vendor_winusb_on_disable_event(void); __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); - /* init functions for all vendor instances */ void sli_usbd_vendor_winusb_init(void); - #endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c index 7427de8c50..18f8c70f9d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c @@ -27,7 +27,6 @@ #include - //**************************************************************************** // Global variables. @@ -35,42 +34,38 @@ uint8_t sl_usbd_configuration_config0_number = 0; - //**************************************************************************** // Global functions. - - /* initialize config0 instance */ void sli_usbd_configuration_config0_init() { - uint8_t attrib = 0; - uint16_t power = 0; - sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; - const char *name = NULL; - uint8_t number = 0; + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; - /* configuration attributes */ + /* configuration attributes */ #if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 - attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; #endif #if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 - attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; #endif - /* configuration maximum power (mA) */ - power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; - /* configuration speed */ - speed = SL_USBD_DEVICE_SPEED_FULL; + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; - /* configuration name */ - name = SL_USB_CONFIGURATION_CONFIG0_NAME; + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; - /* create the configuration descriptor */ - sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); - /* store the configuration number globally */ - sl_usbd_configuration_config0_number = number; + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; } - diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h index 500dd508c3..07726e93fe 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h @@ -11,10 +11,8 @@ extern uint8_t sl_usbd_configuration_config0_number; - /* init functions for all configuration instances */ void sli_usbd_configuration_config0_init(void); - #endif From 76b13008b3f32b152283b6cb36e4ea433afeb9a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 10:54:49 +0100 Subject: [PATCH 165/572] Enable WinUSB config for Skyworks EVB target --- .../AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt index 090d3d7cf6..339247eca3 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -34,6 +34,9 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GQ100=1 @@ -43,6 +46,9 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From df812c1d36088ad1b21d7d0bbcb37681f5b9a09a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:11:28 +0100 Subject: [PATCH 166/572] Remove WinUSB config from SL_STK3701A target --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 6 ------ 1 file changed, 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index b1466e9991..8bd99ba614 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,9 +37,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - USBD_CFG_MS_OS_DESC_EN=1 - SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 - NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -50,9 +47,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - USBD_CFG_MS_OS_DESC_EN=1 - SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 - NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From 0d2dcceff638f144b46008d48592bf999c91bd48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:22:34 +0100 Subject: [PATCH 167/572] Improvements in build system to add/config WinUSB in Gecko SDK - Add README for Silabs Gecko with details about adding WinUSB support to a target. --- CMake/Modules/FindGecko_SDK.cmake | 14 ++++++++++++++ targets/AzureRTOS/SiliconLabs/README.md | 17 +++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/README.md diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 60e3c4f751..f7b28baf46 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -323,6 +323,20 @@ macro(nf_add_gecko_sdk) nf_set_compile_options(TARGET ${LIB_NAME} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS ${NFGCKSDK_EXTRA_COMPILE_DEFINITIONS} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + + # add compile definitions required for WinUSB + if(GECKO_FEATURE_USBD_WINUSB) + nf_set_compile_definitions( + TARGET ${LIB_NAME} + + EXTRA_COMPILE_DEFINITIONS + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + + BUILD_TARGET ${NFGCKSDK_BUILD_TARGET} + ) + endif() + nf_set_link_options(TARGET ${LIB_NAME}) # add alias diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md new file mode 100644 index 0000000000..bc81474119 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -0,0 +1,17 @@ +# Silabs Gecko SDK + +## Configuration for USB devices and classes + +### WinUSB devices + +In order to add a WinUSB device configuration, the follow is required: + +1. Set build option `GECKO_FEATURE_USBD_WINUSB` to `ON`. +1. Add the following files to the target folder (mind the location) + [sl_usbd_class_vendor_instances.c](SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c) + + [sl_usbd_class_vendor_instances.h](SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h) + + [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h) + +1. Add the following compiler definition to the target CMakelists.txt `NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). From 1a2f165d862b429d28a9810a65aab9347d1b9e95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:23:26 +0100 Subject: [PATCH 168/572] Remove unnecessary compiler defs --- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt index 339247eca3..57ad23f7fb 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -34,8 +34,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - USBD_CFG_MS_OS_DESC_EN=1 - SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS @@ -46,8 +44,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - USBD_CFG_MS_OS_DESC_EN=1 - SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES From 973f0fab04f9673b9833719a92cbe0351530ade5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:24:59 +0100 Subject: [PATCH 169/572] Rename compiler define for clarity --- CMake/Modules/FindGecko_SDK.cmake | 2 +- targets/AzureRTOS/SiliconLabs/README.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index f7b28baf46..4d235394ba 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -279,7 +279,7 @@ file(READ string(REPLACE "\"Vendor-specific class\"" - NANO_VENDOR_SPECIFIC_DESCRIPTION + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION SL_USBD_CLASS_VENDOR__NEW_CONTENTS "${SL_USBD_CLASS_VENDOR_CONTENT}") diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index bc81474119..de98a92611 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -14,4 +14,4 @@ In order to add a WinUSB device configuration, the follow is required: [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h) -1. Add the following compiler definition to the target CMakelists.txt `NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). +1. Add the following compiler definition to the target CMakelists.txt `NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). From d9dd6288cf2714b2e3a228394f42faeab4a7dd0e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:25:31 +0100 Subject: [PATCH 170/572] Rename compiler define following changes in build system --- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt | 4 ++-- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt index 57ad23f7fb..0eeba5b2b4 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -34,7 +34,7 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GQ100=1 @@ -44,7 +44,7 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8bd99ba614..8c39c9c4d2 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,6 +37,7 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -47,6 +48,7 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From 4e6ac1d0f4d533285d01cea988a2e4fbbac2e56c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 12:37:05 +0100 Subject: [PATCH 171/572] Wrap tweaking of USB core code depending on build option --- CMake/Modules/FindGecko_SDK.cmake | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 4d235394ba..94cea3f016 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -272,21 +272,23 @@ endif() ################################################################### # change required to define the description of the USB Vendor Class -file(READ - ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - SL_USBD_CLASS_VENDOR_CONTENT) +if(GECKO_FEATURE_USBD_WINUSB) + file(READ + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + SL_USBD_CLASS_VENDOR_CONTENT) -string(REPLACE - "\"Vendor-specific class\"" - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION - SL_USBD_CLASS_VENDOR__NEW_CONTENTS - "${SL_USBD_CLASS_VENDOR_CONTENT}") + string(REPLACE + "\"Vendor-specific class\"" + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION + SL_USBD_CLASS_VENDOR__NEW_CONTENTS + "${SL_USBD_CLASS_VENDOR_CONTENT}") -file(WRITE - ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") -#################################################################### + file(WRITE + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") + +endif() include(FindPackageHandleStandardArgs) From a170e39f258e2edbe7ad780f842b121909f58553 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 12:44:17 +0100 Subject: [PATCH 172/572] Implement building of serial number string from device unique ID - Add explanation on README. - Update definition for SL_STK3701A. --- targets/AzureRTOS/SiliconLabs/README.md | 6 ++++ .../config/sl_usbd_device_config.h | 4 ++- .../_common/autogen/sl_usbd_init.c | 36 ++++++++++++++++++- 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index de98a92611..b87276e6a8 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -2,6 +2,12 @@ ## Configuration for USB devices and classes +### USB serial number + +The USB serial number string is defined with `SL_USBD_DEVICE_SERIAL_NUMBER_STRING` in sl_usbd_device_config.h. +It can be hardcoded by setting it to a string like `"1234567890ABCDEF"`. +As an alternative it can be generated from the device unique ID. For this the define has to be set to `(const char *)&UsbSerialNumber` and the following declaration has to be added `extern char *UsbSerialNumber[];`. Please check the example [here](SL_STK3701A/config/sl_usbd_device_config.h). + ### WinUSB devices In order to add a WinUSB device configuration, the follow is required: diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h index 4a3d86766f..8a31e51491 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h @@ -7,6 +7,8 @@ #ifndef SL_USBD_DEVICE_CONFIG_H #define SL_USBD_DEVICE_CONFIG_H +extern char *UsbSerialNumber[]; + // <<< Use Configuration Wizard in Context Menu >>> // USB Device Configuration @@ -37,7 +39,7 @@ // Device Serial Number // Default: "1234567890ABCDEF" // Device serial number string. -#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING "1234567890ABCDEF" +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber // Device Language ID // Arabic diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index 4f418ed9cf..fb3759f4a8 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -29,12 +29,47 @@ #include "sl_usbd_class_cdc_acm.h" #endif +// need to fit 64bits as hex string +// Can be referenced from sl_usbd_device_config.h in the define SL_USBD_DEVICE_SERIAL_NUMBER_STRING +#define USB_SERIAL_NUMBER_LENGTH (8 * 2 + 1) +char UsbSerialNumber[USB_SERIAL_NUMBER_LENGTH]; + //**************************************************************************** // Global functions. +// this function composes a string with the device Unique ID +void ComposeDeviceUID() +{ + // device Unique ID is 64 bits long + uint8_t deviceUID[8]; + + deviceUID[0] = DEVINFO->UNIQUEH >> 24; + deviceUID[1] = DEVINFO->UNIQUEH >> 16; + deviceUID[2] = DEVINFO->UNIQUEH >> 8; + deviceUID[3] = DEVINFO->UNIQUEH; + deviceUID[4] = DEVINFO->UNIQUEL >> 24; + deviceUID[5] = DEVINFO->UNIQUEL >> 16; + deviceUID[6] = DEVINFO->UNIQUEL >> 8; + deviceUID[7] = DEVINFO->UNIQUEL; + + snprintf( + UsbSerialNumber, + sizeof(UsbSerialNumber), + "%02X%02X%02X%02X%02X%02X%02X%02X", + deviceUID[0], + deviceUID[1], + deviceUID[2], + deviceUID[3], + deviceUID[4], + deviceUID[5], + deviceUID[6], + deviceUID[7]); +} + /* USB initialization function */ void sli_usbd_init(void) { + ComposeDeviceUID(); sl_usbd_core_init(); @@ -50,5 +85,4 @@ void sli_usbd_init(void) #if GECKO_FEATURE_USBD_WINUSB == TRUE sl_usbd_vendor_init(); #endif - } From 03c98fb1a3fa57eb570a3c492a2b26e4dc3e0002 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 12:47:37 +0100 Subject: [PATCH 173/572] USB serial number is now coming from device unique ID --- .../SKY_EEVB_PROTO1/config/sl_usbd_device_config.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h index 4a3d86766f..8a31e51491 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h @@ -7,6 +7,8 @@ #ifndef SL_USBD_DEVICE_CONFIG_H #define SL_USBD_DEVICE_CONFIG_H +extern char *UsbSerialNumber[]; + // <<< Use Configuration Wizard in Context Menu >>> // USB Device Configuration @@ -37,7 +39,7 @@ // Device Serial Number // Default: "1234567890ABCDEF" // Device serial number string. -#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING "1234567890ABCDEF" +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber // Device Language ID // Arabic From 6f9c9177032d8fd6022fff2e5a1cbf695e5c5e6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 13:16:35 +0100 Subject: [PATCH 174/572] Fix build for SKY_EEVB_PROTO1 --- .../autogen/sl_usbd_class_vendor_instances.c | 1 + .../AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h | 9 +++++++++ 2 files changed, 10 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c index 574a69a1cf..b8e5a63004 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c @@ -144,4 +144,5 @@ void sl_usbd_vendor_winusb_on_disable_event(void) void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) { + (void)p_setup_req; } diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// From 3ad831fec088b0aac9cbd36ed8e093e553c0b657 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 13:17:02 +0100 Subject: [PATCH 175/572] Increase block storage size for SKY_EEVB_PROTO1 booter --- .../AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt | 4 ++-- .../SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c | 6 +++--- .../SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld | 4 ++-- .../SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt index 0eeba5b2b4..9fedae80e7 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -65,13 +65,13 @@ if(SRECORD_TOOL_AVAILABLE) nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 12000 + 13000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) else() nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 12000 + 13000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) endif() diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c index 71c9310708..5ae69920e9 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c @@ -10,10 +10,10 @@ const BlockRange BlockRange1[] = { // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 17}, + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, - // 00012000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 18, 237}, + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, // 000EE000 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld index 74c3541c99..8941c58e5c 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00000000, len = 72k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00012000, len = 0 /* space reserved for application deployment */ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld index bbd167197f..58e8ea7a09 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,7 +32,7 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00012000, len = 2M - 72k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ deployment (rx) : org = 0x000EE000, len = 904k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ From 09a3bfe53117dcb3f503fe85186795c4283dc132 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 13:18:35 +0100 Subject: [PATCH 176/572] Fix USB PID for Skyworks EVB --- .../SKY_EEVB_PROTO1/config/sl_usbd_device_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h index 8a31e51491..f9f5a0158d 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h @@ -18,8 +18,8 @@ extern char *UsbSerialNumber[]; #define SL_USBD_DEVICE_VENDOR_ID 0x10C4 // Device Product ID -// Device product ID. PID assigned to .NET nanoFramework -#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAD +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC // Device Release Number // Default: 0x0100 From a8f196094cd7b7574dee573ec1d5b3df496f70aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 13:24:04 +0100 Subject: [PATCH 177/572] Fix startup of winUSB for SKY_EEVB_PROTO1 --- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c index d81f479cd5..a40ab0cbdc 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -24,6 +24,7 @@ extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +extern void sli_usbd_vendor_winusb_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -177,8 +178,7 @@ void tx_application_define(void *first_unused_memory) #endif #if GECKO_FEATURE_USBD_WINUSB == TRUE -// TODO - //usb_device_winusb_app_init(); + sli_usbd_vendor_winusb_init(); #endif #if HAL_WP_USE_USB_CDC == TRUE From 7b9a930642cedcd6a8b5cebe4cf841e886e43396 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Sep 2022 15:44:54 +0100 Subject: [PATCH 178/572] More work adding support for WinUSB with Gecko SDK --- CMake/Modules/FindGecko_SDK.cmake | 19 +++++++++++++++++++ .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 6 ++++++ .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 4 ++-- 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 434c9822cc..60e3c4f751 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -186,6 +186,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") if(GECKO_FEATURE_USBD_WINUSB) + list(APPEND gecko_sdk_srcs sl_usbd_class_vendor_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) @@ -269,6 +270,24 @@ else() message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") endif() +################################################################### +# change required to define the description of the USB Vendor Class +file(READ + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + SL_USBD_CLASS_VENDOR_CONTENT) + + +string(REPLACE + "\"Vendor-specific class\"" + NANO_VENDOR_SPECIFIC_DESCRIPTION + SL_USBD_CLASS_VENDOR__NEW_CONTENTS + "${SL_USBD_CLASS_VENDOR_CONTENT}") + +file(WRITE + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") +#################################################################### + include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Gecko_SDK DEFAULT_MSG Gecko_SDK_INCLUDE_DIRS Gecko_SDK_SOURCES) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8bd99ba614..b1466e9991 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,6 +37,9 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -47,6 +50,9 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 152cd22a14..9b0cea2239 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -25,6 +25,7 @@ extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +extern void sli_usbd_vendor_winusb_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -178,8 +179,7 @@ void tx_application_define(void *first_unused_memory) #endif #if GECKO_FEATURE_USBD_WINUSB == TRUE -// TODO - //usb_device_winusb_app_init(); + sli_usbd_vendor_winusb_init(); #endif #if HAL_WP_USE_USB_CDC == TRUE From 2eb94923e62d021663ed6b3b142ba862c7333513 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 10:52:21 +0100 Subject: [PATCH 179/572] Code style fixes --- .../autogen/sl_usbd_class_hid_instances.c | 349 ++++++++---------- .../autogen/sl_usbd_class_hid_instances.h | 23 +- .../autogen/sl_usbd_class_vendor_instances.c | 117 +++--- .../autogen/sl_usbd_configuration_instances.c | 41 +- .../autogen/sl_usbd_configuration_instances.h | 2 - 5 files changed, 233 insertions(+), 299 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c index f80d11f2c9..33c10907fc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -29,282 +29,259 @@ #include - //**************************************************************************** // Function declarations. - - /* callback prototypes for hid0 instance */ void sli_usbd_hid_hid0_enable(uint8_t class_nbr); void sli_usbd_hid_hid0_disable(uint8_t class_nbr); -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len); +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len); +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); -void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, - uint8_t *p_protocol); - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, - uint8_t protocol); +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); //**************************************************************************** // Global variables. - - - /* variables for mouse0 instance */ uint8_t sl_usbd_hid_hid0_number = 0; uint8_t sl_usbd_hid_hid0_default_protocol = 0; - static const uint8_t sli_usbd_hid_hid0_default_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, 0x00, - SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, - SL_USBD_HID_LOCAL_USAGE + 1, 0x09, - SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, - SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, - SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, - SL_USBD_HID_MAIN_ENDCOLLECTION, - SL_USBD_HID_MAIN_ENDCOLLECTION -}; + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { - sli_usbd_hid_hid0_enable, - sli_usbd_hid_hid0_disable, - sli_usbd_hid_hid0_get_report_desc, - sli_usbd_hid_hid0_get_phy_desc, - sli_usbd_hid_hid0_set_output_report, - sli_usbd_hid_hid0_get_feature_report, - sli_usbd_hid_hid0_set_feature_report, - sli_usbd_hid_hid0_get_protocol, - sli_usbd_hid_hid0_set_protocol, + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, }; - - //**************************************************************************** // Callback functions. - - /* callback functions for mouse0 instance */ void sli_usbd_hid_hid0_enable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_enable_event(); + sl_usbd_hid_hid0_on_enable_event(); - return; + return; } void sli_usbd_hid_hid0_disable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_disable_event(); + sl_usbd_hid_hid0_on_disable_event(); - return; + return; } -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len) +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { - (void)&class_nbr; + (void)&class_nbr; - *p_report_ptr = sli_usbd_hid_hid0_default_desc; - *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); - sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); - return; + return; } -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, - const uint8_t **p_report_ptr, - uint16_t *p_report_len) +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) { - (void)&class_nbr; + (void)&class_nbr; - *p_report_ptr = NULL; - *p_report_len = 0; + *p_report_ptr = NULL; + *p_report_len = 0; - sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); - return; + return; } -void sli_usbd_hid_hid0_set_output_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); - return; + return; } - -void sli_usbd_hid_hid0_get_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - memset(p_report_buf, 0, report_len); + memset(p_report_buf, 0, report_len); - sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); - return; + return; } -void sli_usbd_hid_hid0_set_feature_report(uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); - return; + return; } -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, - uint8_t *p_protocol) +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) { - (void)&class_nbr; + (void)&class_nbr; - *p_protocol = sl_usbd_hid_hid0_default_protocol; + *p_protocol = sl_usbd_hid_hid0_default_protocol; - sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); - return; + return; } -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, - uint8_t protocol) +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_hid_hid0_default_protocol = protocol; + sl_usbd_hid_hid0_default_protocol = protocol; - sl_usbd_hid_hid0_on_set_protocol_event(protocol); + sl_usbd_hid_hid0_on_set_protocol_event(protocol); - return; + return; } - //**************************************************************************** // Global functions. - - /* initialize hid0 instance */ void sli_usbd_hid_hid0_init() { - sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; - - uint8_t subclass = 0; - uint8_t protocol = 0; - - uint16_t interval_in = 0; - uint16_t interval_out = 0; - bool ctrl_rd_en = true; - - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_HID_HID0_CONFIGURATIONS; - - /* read subclass, protocol, and country codes */ - subclass = SL_USBD_HID_HID0_SUBCLASS; - protocol = SL_USBD_HID_HID0_PROTOCOL; - country = SL_USBD_HID_HID0_COUNTRY_CODE; - - /* read endpoint parameters */ - interval_in = SL_USBD_HID_HID0_INTERVAL_IN; - interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; - ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; - - /* create HID instance */ - sl_usbd_hid_create_instance(subclass, - protocol, - country, - interval_in, - interval_out, - ctrl_rd_en, - &sli_usbd_hid_hid0_callbacks, - &class_number); - - /* store class number globally */ - sl_usbd_hid_hid0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_hid_add_to_configuration(class_number, config_number); + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); } - - - /* next token */ - token = strtok(NULL, ", "); - } } - diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h index 1243386c7e..fa9e5b853a 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.h @@ -13,31 +13,20 @@ extern uint8_t sl_usbd_hid_hid0_number; - /* event handlers for all HID instances */ __WEAK void sl_usbd_hid_hid0_on_enable_event(void); __WEAK void sl_usbd_hid_hid0_on_disable_event(void); -__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, - uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, - uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); __WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); -__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); - +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); /* init functions for all HID instances */ void sli_usbd_hid_hid0_init(void); - #endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c index 4a5482daad..f4a864b429 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -9,7 +9,6 @@ #include "sl_status.h" - #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wundef" @@ -32,142 +31,118 @@ #include "sl_usbd_class_winusb_config.h" - //**************************************************************************** // Function declarations. - - - /* callback prototypes for winusb instance */ void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, - const sl_usbd_setup_req_t *p_setup_req); - - - +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); //**************************************************************************** // Global variables. - - - /* variables for winusb instance */ uint8_t sl_usbd_vendor_winusb_number = 0; sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { - sli_usbd_vendor_winusb_enable, - sli_usbd_vendor_winusb_disable, - sli_usbd_vendor_winusb_setup_req, + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, }; - - //**************************************************************************** // Callback functions. - - - void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_enable_event(); + sl_usbd_vendor_winusb_on_enable_event(); - return; + return; } void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_disable_event(); + sl_usbd_vendor_winusb_on_disable_event(); - return; + return; } -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, - const sl_usbd_setup_req_t *p_setup_req) +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) { - (void)&class_nbr; + (void)&class_nbr; - sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); - return; + return; } - //**************************************************************************** // Global functions. - - /* initialize winusb instance */ void sli_usbd_vendor_winusb_init() { - bool intr_en = true; - uint16_t interval = 0; + bool intr_en = true; + uint16_t interval = 0; - uint8_t class_number = 0; - uint8_t config_number = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; + char *configs = NULL; + char *token = NULL; - /* configs to attach the class instance to */ - configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; - /* read interrupt enable flag */ - intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; - /* read interval */ - interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; - /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, - interval, - &sli_usbd_vendor_winusb_callbacks, - &class_number); + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); - /* store class number globally */ - sl_usbd_vendor_winusb_number = class_number; + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); - /* loop over tokens */ - while (token != NULL) { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); - } - + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } - /* next token */ - token = strtok(NULL, ", "); - } + /* next token */ + token = strtok(NULL, ", "); + } } void sl_usbd_vendor_winusb_on_enable_event(void) { - } void sl_usbd_vendor_winusb_on_disable_event(void) { - } void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) { - + (void)&p_setup_req; } diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c index 7427de8c50..18f8c70f9d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c @@ -27,7 +27,6 @@ #include - //**************************************************************************** // Global variables. @@ -35,42 +34,38 @@ uint8_t sl_usbd_configuration_config0_number = 0; - //**************************************************************************** // Global functions. - - /* initialize config0 instance */ void sli_usbd_configuration_config0_init() { - uint8_t attrib = 0; - uint16_t power = 0; - sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; - const char *name = NULL; - uint8_t number = 0; + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; - /* configuration attributes */ + /* configuration attributes */ #if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 - attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; #endif #if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 - attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; #endif - /* configuration maximum power (mA) */ - power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; - /* configuration speed */ - speed = SL_USBD_DEVICE_SPEED_FULL; + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; - /* configuration name */ - name = SL_USB_CONFIGURATION_CONFIG0_NAME; + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; - /* create the configuration descriptor */ - sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); - /* store the configuration number globally */ - sl_usbd_configuration_config0_number = number; + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; } - diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h index 500dd508c3..07726e93fe 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.h @@ -11,10 +11,8 @@ extern uint8_t sl_usbd_configuration_config0_number; - /* init functions for all configuration instances */ void sli_usbd_configuration_config0_init(void); - #endif From 37ef4ed98ec41317ed47e6611fba05834f7c1b45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:11:28 +0100 Subject: [PATCH 180/572] Remove WinUSB config from SL_STK3701A target --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 6 ------ 1 file changed, 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index b1466e9991..8bd99ba614 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,9 +37,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - USBD_CFG_MS_OS_DESC_EN=1 - SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 - NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -50,9 +47,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - USBD_CFG_MS_OS_DESC_EN=1 - SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 - NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From 9a66f4cf7a854121968cabe6068596439beaecd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:22:34 +0100 Subject: [PATCH 181/572] Improvements in build system to add/config WinUSB in Gecko SDK - Add README for Silabs Gecko with details about adding WinUSB support to a target. --- CMake/Modules/FindGecko_SDK.cmake | 14 ++++++++++++++ targets/AzureRTOS/SiliconLabs/README.md | 17 +++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/README.md diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 60e3c4f751..f7b28baf46 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -323,6 +323,20 @@ macro(nf_add_gecko_sdk) nf_set_compile_options(TARGET ${LIB_NAME} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS ${NFGCKSDK_EXTRA_COMPILE_DEFINITIONS} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + + # add compile definitions required for WinUSB + if(GECKO_FEATURE_USBD_WINUSB) + nf_set_compile_definitions( + TARGET ${LIB_NAME} + + EXTRA_COMPILE_DEFINITIONS + USBD_CFG_MS_OS_DESC_EN=1 + SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY=1 + + BUILD_TARGET ${NFGCKSDK_BUILD_TARGET} + ) + endif() + nf_set_link_options(TARGET ${LIB_NAME}) # add alias diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md new file mode 100644 index 0000000000..bc81474119 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -0,0 +1,17 @@ +# Silabs Gecko SDK + +## Configuration for USB devices and classes + +### WinUSB devices + +In order to add a WinUSB device configuration, the follow is required: + +1. Set build option `GECKO_FEATURE_USBD_WINUSB` to `ON`. +1. Add the following files to the target folder (mind the location) + [sl_usbd_class_vendor_instances.c](SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c) + + [sl_usbd_class_vendor_instances.h](SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h) + + [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h) + +1. Add the following compiler definition to the target CMakelists.txt `NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). From 57753c1a519f279e362da71f71c67157e0e5ef07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:24:59 +0100 Subject: [PATCH 182/572] Rename compiler define for clarity --- CMake/Modules/FindGecko_SDK.cmake | 2 +- targets/AzureRTOS/SiliconLabs/README.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index f7b28baf46..4d235394ba 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -279,7 +279,7 @@ file(READ string(REPLACE "\"Vendor-specific class\"" - NANO_VENDOR_SPECIFIC_DESCRIPTION + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION SL_USBD_CLASS_VENDOR__NEW_CONTENTS "${SL_USBD_CLASS_VENDOR_CONTENT}") diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index bc81474119..de98a92611 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -14,4 +14,4 @@ In order to add a WinUSB device configuration, the follow is required: [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h) -1. Add the following compiler definition to the target CMakelists.txt `NANO_VENDOR_SPECIFIC_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). +1. Add the following compiler definition to the target CMakelists.txt `NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). From 3ddfe36544f393cdd651757bd0f351ce4e5fcd17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 12:37:05 +0100 Subject: [PATCH 183/572] Wrap tweaking of USB core code depending on build option --- CMake/Modules/FindGecko_SDK.cmake | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 4d235394ba..94cea3f016 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -272,21 +272,23 @@ endif() ################################################################### # change required to define the description of the USB Vendor Class -file(READ - ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - SL_USBD_CLASS_VENDOR_CONTENT) +if(GECKO_FEATURE_USBD_WINUSB) + file(READ + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + SL_USBD_CLASS_VENDOR_CONTENT) -string(REPLACE - "\"Vendor-specific class\"" - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION - SL_USBD_CLASS_VENDOR__NEW_CONTENTS - "${SL_USBD_CLASS_VENDOR_CONTENT}") + string(REPLACE + "\"Vendor-specific class\"" + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION + SL_USBD_CLASS_VENDOR__NEW_CONTENTS + "${SL_USBD_CLASS_VENDOR_CONTENT}") -file(WRITE - ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") -#################################################################### + file(WRITE + ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c + "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") + +endif() include(FindPackageHandleStandardArgs) From 00c25b4ccc359d71602a2e0ba8fa3c8c6001d26d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 12:44:17 +0100 Subject: [PATCH 184/572] Implement building of serial number string from device unique ID - Add explanation on README. - Update definition for SL_STK3701A. --- targets/AzureRTOS/SiliconLabs/README.md | 6 ++++ .../config/sl_usbd_device_config.h | 4 ++- .../_common/autogen/sl_usbd_init.c | 36 ++++++++++++++++++- 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index de98a92611..b87276e6a8 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -2,6 +2,12 @@ ## Configuration for USB devices and classes +### USB serial number + +The USB serial number string is defined with `SL_USBD_DEVICE_SERIAL_NUMBER_STRING` in sl_usbd_device_config.h. +It can be hardcoded by setting it to a string like `"1234567890ABCDEF"`. +As an alternative it can be generated from the device unique ID. For this the define has to be set to `(const char *)&UsbSerialNumber` and the following declaration has to be added `extern char *UsbSerialNumber[];`. Please check the example [here](SL_STK3701A/config/sl_usbd_device_config.h). + ### WinUSB devices In order to add a WinUSB device configuration, the follow is required: diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h index 4a3d86766f..8a31e51491 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h @@ -7,6 +7,8 @@ #ifndef SL_USBD_DEVICE_CONFIG_H #define SL_USBD_DEVICE_CONFIG_H +extern char *UsbSerialNumber[]; + // <<< Use Configuration Wizard in Context Menu >>> // USB Device Configuration @@ -37,7 +39,7 @@ // Device Serial Number // Default: "1234567890ABCDEF" // Device serial number string. -#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING "1234567890ABCDEF" +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber // Device Language ID // Arabic diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index 4f418ed9cf..fb3759f4a8 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -29,12 +29,47 @@ #include "sl_usbd_class_cdc_acm.h" #endif +// need to fit 64bits as hex string +// Can be referenced from sl_usbd_device_config.h in the define SL_USBD_DEVICE_SERIAL_NUMBER_STRING +#define USB_SERIAL_NUMBER_LENGTH (8 * 2 + 1) +char UsbSerialNumber[USB_SERIAL_NUMBER_LENGTH]; + //**************************************************************************** // Global functions. +// this function composes a string with the device Unique ID +void ComposeDeviceUID() +{ + // device Unique ID is 64 bits long + uint8_t deviceUID[8]; + + deviceUID[0] = DEVINFO->UNIQUEH >> 24; + deviceUID[1] = DEVINFO->UNIQUEH >> 16; + deviceUID[2] = DEVINFO->UNIQUEH >> 8; + deviceUID[3] = DEVINFO->UNIQUEH; + deviceUID[4] = DEVINFO->UNIQUEL >> 24; + deviceUID[5] = DEVINFO->UNIQUEL >> 16; + deviceUID[6] = DEVINFO->UNIQUEL >> 8; + deviceUID[7] = DEVINFO->UNIQUEL; + + snprintf( + UsbSerialNumber, + sizeof(UsbSerialNumber), + "%02X%02X%02X%02X%02X%02X%02X%02X", + deviceUID[0], + deviceUID[1], + deviceUID[2], + deviceUID[3], + deviceUID[4], + deviceUID[5], + deviceUID[6], + deviceUID[7]); +} + /* USB initialization function */ void sli_usbd_init(void) { + ComposeDeviceUID(); sl_usbd_core_init(); @@ -50,5 +85,4 @@ void sli_usbd_init(void) #if GECKO_FEATURE_USBD_WINUSB == TRUE sl_usbd_vendor_init(); #endif - } From 0acb81ab5e5d4fe39715a02945b9617a1a0d49e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Sep 2022 11:25:31 +0100 Subject: [PATCH 185/572] Rename compiler define following changes in build system --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8bd99ba614..8c39c9c4d2 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,6 +37,7 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -47,6 +48,7 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" From e32da0e2635339ee63ceb04535bc9909a775dfe3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:48:55 +0100 Subject: [PATCH 186/572] Fix several USB properties --- .../SKY_EEVB_PROTO1/config/sl_usbd_device_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h index f9f5a0158d..d637b5e987 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h @@ -29,12 +29,12 @@ extern char *UsbSerialNumber[]; // Device Manufacturer Name // Default: "Silicon Labs" // Device manufacturer string. -#define SL_USBD_DEVICE_MANUFACTURER_STRING "Silicon Labs" +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" // Device Product Name // Default: "Product" // Device product string. -#define SL_USBD_DEVICE_PRODUCT_STRING "nanodevice" +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EEVB" // Device Serial Number // Default: "1234567890ABCDEF" From c5125880dedf732900bf82b0f0474a90e406913f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:49:46 +0100 Subject: [PATCH 187/572] Add USB event handlers to class vendor instances - Required when no other USB classes are added. --- .../autogen/sl_usbd_class_vendor_instances.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c index b8e5a63004..c954f68c8f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c @@ -146,3 +146,53 @@ void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_s { (void)p_setup_req; } + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} From 86e606fc075e92e7f98b9ef642401b46b8f4e907 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:51:07 +0100 Subject: [PATCH 188/572] Add missing Microsoft extended property - Enumeration requires DeviceInterfaceGUID to have device properly accessible. - Add configs and setting the property. --- .../_common/autogen/sl_usbd_class_winusb.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h new file mode 100644 index 0000000000..59a640a77e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_WINUSB_H +#define SL_USBD_CLASS_WINUSB_H + +#define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" + +/// Length of GUID Property Name +#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) + +#endif // SL_USBD_CLASS_WINUSB_H From 021b05a4612f78eabbc2b1757b349fc375362563 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:51:33 +0100 Subject: [PATCH 189/572] Add DeviceInterfaceGUID config to SKY_EEVB_PROTO1 --- .../autogen/sl_usbd_class_vendor_instances.c | 9 +++++++++ .../SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c index c954f68c8f..51e9e896a5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c @@ -132,6 +132,15 @@ void sli_usbd_vendor_winusb_init() /* next token */ token = strtok(NULL, ", "); } + + // add device class GUID to WinUSB properties + sl_usbd_vendor_add_microsoft_ext_property( + config_number, + SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, + (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, + DEVICEINTERFACE_GUID_PROP_NAME_LEN, + (const uint8_t *)DEVICE_CLASS_GUID_PROPERTY, + sizeof(DEVICE_CLASS_GUID_PROPERTY)); } void sl_usbd_vendor_winusb_on_enable_event(void) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h index 4da7f4409b..57d9f807a8 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h @@ -7,6 +7,11 @@ #ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H #define SL_USBD_VENDOR_WINUSB_CONFIG_H +#include + +/// device class GUID for WinUSB (going into DeviceInterfaceGUID extended property) +#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + // <<< Use Configuration Wizard in Context Menu >>> // Class Configuration From 55b17df92c87d2dea5df48b505dc67dc1e1bc981 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:51:07 +0100 Subject: [PATCH 190/572] Add missing Microsoft extended property - Enumeration requires DeviceInterfaceGUID to have device properly accessible. - Add configs and setting the property. --- .../_common/autogen/sl_usbd_class_winusb.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h new file mode 100644 index 0000000000..59a640a77e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h @@ -0,0 +1,15 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_WINUSB_H +#define SL_USBD_CLASS_WINUSB_H + +#define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" + +/// Length of GUID Property Name +#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) + +#endif // SL_USBD_CLASS_WINUSB_H From de18efc3e0602de3ffa7ef2c7edcb9d387358804 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:54:22 +0100 Subject: [PATCH 191/572] Add DeviceInterfaceGUID config to SL_STK3701A --- .../autogen/sl_usbd_class_vendor_instances.c | 9 +++ .../config/sl_usbd_class_winusb_config.h | 57 +++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c index f4a864b429..f5d6c2e89c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -132,6 +132,15 @@ void sli_usbd_vendor_winusb_init() /* next token */ token = strtok(NULL, ", "); } + + // add device class GUID to WinUSB properties + sl_usbd_vendor_add_microsoft_ext_property( + config_number, + SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, + (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, + DEVICEINTERFACE_GUID_PROP_NAME_LEN, + (const uint8_t *)DEVICE_CLASS_GUID_PROPERTY, + sizeof(DEVICE_CLASS_GUID_PROPERTY)); } void sl_usbd_vendor_winusb_on_enable_event(void) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..4da7f4409b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,57 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H From 2f66b4449a16c523ca73f8e961c2175605bef1e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:55:57 +0100 Subject: [PATCH 192/572] Add USB event handlers to class vendor instances - Required when no other USB classes are added. --- .../autogen/sl_usbd_class_vendor_instances.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c index f5d6c2e89c..8421c3fa75 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c @@ -155,3 +155,53 @@ void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_s { (void)&p_setup_req; } + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} From 28bff75bbfc25afd731baed61d7f08d6713aa648 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 17:58:05 +0100 Subject: [PATCH 193/572] Add missing GUID for device class --- .../SL_STK3701A/config/sl_usbd_class_winusb_config.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h index 4da7f4409b..cdaa68dac3 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -7,6 +7,11 @@ #ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H #define SL_USBD_VENDOR_WINUSB_CONFIG_H +#include + +/// device class GUID for WinUSB (going into DeviceInterfaceGUID extended property) +#define DEVICE_CLASS_GUID_PROPERTY L"{9e48651c-fa68-4b39-8731-1ee84659aac5}" + // <<< Use Configuration Wizard in Context Menu >>> // Class Configuration From ca95ace6e8eb8d7067aea00080262a3ddac8eba5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 30 Sep 2022 18:01:34 +0100 Subject: [PATCH 194/572] Update docs about WinUSB --- targets/AzureRTOS/SiliconLabs/README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index b87276e6a8..284b48f3dc 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -13,6 +13,7 @@ As an alternative it can be generated from the device unique ID. For this the de In order to add a WinUSB device configuration, the follow is required: 1. Set build option `GECKO_FEATURE_USBD_WINUSB` to `ON`. + 1. Add the following files to the target folder (mind the location) [sl_usbd_class_vendor_instances.c](SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c) @@ -21,3 +22,6 @@ In order to add a WinUSB device configuration, the follow is required: [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h) 1. Add the following compiler definition to the target CMakelists.txt `NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). + +1. Define a GUID for the device class and set define `DEVICE_CLASS_GUID_PROPERTY` with it. Check [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h). +For details check [Microsoft documentation](https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/automatic-installation-of-winusb#registering-a-device-interface-guid) about setting a WinUSB device that does not require an INF file to install. From 5fd1059edd163a2f7704dd3221755b86d81ab274 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 3 Oct 2022 10:02:47 +0100 Subject: [PATCH 195/572] Improve comment about device class GUID --- .../SL_STK3701A/config/sl_usbd_class_winusb_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h index cdaa68dac3..24bc732064 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -9,7 +9,7 @@ #include -/// device class GUID for WinUSB (going into DeviceInterfaceGUID extended property) +// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) #define DEVICE_CLASS_GUID_PROPERTY L"{9e48651c-fa68-4b39-8731-1ee84659aac5}" // <<< Use Configuration Wizard in Context Menu >>> From e59f9df65485831b163e49b9e922a8e00f1f635b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 3 Oct 2022 10:03:15 +0100 Subject: [PATCH 196/572] Improve comment about device class GUID --- .../SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h index 57d9f807a8..50f40785bb 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h @@ -9,7 +9,7 @@ #include -/// device class GUID for WinUSB (going into DeviceInterfaceGUID extended property) +// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) #define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" // <<< Use Configuration Wizard in Context Menu >>> From 27d15bab9d217bc2957513ee912379e414c9e9b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 6 Oct 2022 19:08:41 +0100 Subject: [PATCH 197/572] Initial work adding native implementation for UsbDevice --- CMake/Modules/FindGecko_SDK.cmake | 6 +- CMake/Modules/FindNF_NativeAssemblies.cmake | 7 + .../Modules/FindSystem.Device.UsbStream.cmake | 51 ++++ .../System.Device.UsbStream.filters | 30 +++ .../System.Device.UsbStream.vcxproj | 162 +++++++++++ .../sys_dev_usbstream_native.cpp | 43 +++ .../sys_dev_usbstream_native.h | 30 +++ ...ystem_Device_UsbClient_UsbStream_stubs.cpp | 54 ++++ targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 7 +- .../autogen/sl_usbd_class_vendor_instances.c | 211 +++++++++++++++ .../autogen/sl_usbd_class_vendor_instances.h | 36 +++ .../_common/autogen/sl_usbd_class_winusb.h | 15 -- ...tive_System_Device_UsbClient_UsbStream.cpp | 253 ++++++++++++++++++ 13 files changed, 884 insertions(+), 21 deletions(-) create mode 100644 CMake/Modules/FindSystem.Device.UsbStream.cmake create mode 100644 src/System.Device.UsbStream/System.Device.UsbStream.filters create mode 100644 src/System.Device.UsbStream/System.Device.UsbStream.vcxproj create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native.cpp create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native.h create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h delete mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 94cea3f016..2555bc9fb6 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -281,12 +281,12 @@ if(GECKO_FEATURE_USBD_WINUSB) string(REPLACE "\"Vendor-specific class\"" NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION - SL_USBD_CLASS_VENDOR__NEW_CONTENTS + SL_USBD_CLASS_VENDOR_NEW_CONTENTS "${SL_USBD_CLASS_VENDOR_CONTENT}") file(WRITE ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") + "${SL_USBD_CLASS_VENDOR_NEW_CONTENTS}") endif() @@ -310,7 +310,7 @@ macro(nf_add_gecko_sdk) # add THESE has a library set(LIB_NAME gecko_sdk_${NFGCKSDK_BUILD_TARGET}) - + add_library( ${LIB_NAME} STATIC ${Gecko_SDK_SOURCES} diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index b8a4c2580c..1154c9e3b1 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -31,6 +31,7 @@ option(API_Com.SkyworksInc.NanoFramework.Devices.Spi "option f option(API_Windows.Storage "option for Windows.Storage") option(API_nanoFramework.Graphics "option for nanoFramework.Graphics") option(API_nanoFramework.Device.Bluetooth "option for nanoFramework.Device.Bluetooth") +option(API_System.Device.UsbStream "option for System.Device.UsbStream API") # Esp32 only option(API_Hardware.Esp32 "option for Hardware.Esp32") @@ -340,6 +341,12 @@ if(API_System.Device.Wifi) PerformSettingsForApiEntry("System.Device.Wifi") endif() +# System.Device.UsbStream +if(API_System.Device.UsbStream) + ##### API name here (doted name) + PerformSettingsForApiEntry("System.Device.UsbStream") +endif() + # Windows.Storage if(API_Windows.Storage) ##### API name here (doted name) diff --git a/CMake/Modules/FindSystem.Device.UsbStream.cmake b/CMake/Modules/FindSystem.Device.UsbStream.cmake new file mode 100644 index 0000000000..8579a6e592 --- /dev/null +++ b/CMake/Modules/FindSystem.Device.UsbStream.cmake @@ -0,0 +1,51 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Device.UsbStream) + + +# set include directories +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/System.Device.UsbStream) + +# source files +set(System.Device.UsbStream_SRCS + + sys_dev_usbstream_native.cpp + + + sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp + +) + +foreach(SRC_FILE ${System.Device.UsbStream_SRCS}) + + set(System.Device.UsbStream_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(System.Device.UsbStream_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/System.Device.UsbStream + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${System.Device.UsbStream_SRC_FILE}") + endif() + + list(APPEND System.Device.UsbStream_SOURCES ${System.Device.UsbStream_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(System.Device.UsbStream DEFAULT_MSG System.Device.UsbStream_INCLUDE_DIRS System.Device.UsbStream_SOURCES) diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.filters b/src/System.Device.UsbStream/System.Device.UsbStream.filters new file mode 100644 index 0000000000..7f41043a0f --- /dev/null +++ b/src/System.Device.UsbStream/System.Device.UsbStream.filters @@ -0,0 +1,30 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + + + Header Files + + + \ No newline at end of file diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj new file mode 100644 index 0000000000..59b2a20d17 --- /dev/null +++ b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj @@ -0,0 +1,162 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + {71fbf8bd-5386-4ea9-9e6b-ec36470fc021} + Win32Proj + System.Device.UsbStream + 10.0.19041.0 + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;NANOCLR_SYSTEM_COLLECTIONS=TRUE;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;NANOCLR_SYSTEM_COLLECTIONS=TRUE;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp new file mode 100644 index 0000000000..933e866f0a --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -0,0 +1,43 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_usbstream_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = +{ + "System.Device.UsbStream", + 0x79416300, + method_lookup, + { 1, 0, 0, 0 } +}; + +// clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h new file mode 100644 index 0000000000..246c9c9c20 --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -0,0 +1,30 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_USBSTREAM_NATIVE_H +#define SYS_DEV_USBSTREAM_NATIVE_H + +#include +#include +#include +#include + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream +{ + static const int FIELD___streamIndex = 2; + static const int FIELD___disposed = 3; + + NANOCLR_NATIVE_DECLARE(Flush___VOID); + NANOCLR_NATIVE_DECLARE(NativeClose___VOID); + NANOCLR_NATIVE_DECLARE(NativeOpen___I4__STRING__STRING); + NANOCLR_NATIVE_DECLARE(NativeWrite___VOID__SZARRAY_U1__I4__I4); + NANOCLR_NATIVE_DECLARE(NativeRead___I4__SZARRAY_U1__I4__I4); + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream; + +#endif // SYS_DEV_USBSTREAM_NATIVE_H diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp new file mode 100644 index 0000000000..beaba35c7b --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp @@ -0,0 +1,54 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index e274b4bb46..901408d261 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -38,12 +38,13 @@ else() set(GECKO_FEATURE_USBD_HID_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_HID for USBD HID") endif() -if(GECKO_FEATURE_USBD_WINUSB) +if(API_System.Device.UsbStream) - set(GECKO_FEATURE_USBD_WINUSB_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") + set(GECKO_FEATURE_USBD_WINUSB_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for WinUSB") + set(GECKO_FEATURE_USBD_WINUSB ON PARENT_SCOPE) else() - set(GECKO_FEATURE_USBD_WINUSB_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") + set(GECKO_FEATURE_USBD_WINUSB_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for WinUSB") endif() diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c new file mode 100644 index 0000000000..0b85bfd1e1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -0,0 +1,211 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_vendor.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_vendor_instances.h" + +/* include config file for the instances */ + +#include + +// storage for USB class vendor description +char UsbClassVendorDescription[32 + 1]; +char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for winusb instance */ + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); + +//**************************************************************************** +// Global variables. + +/* variables for winusb instance */ + +uint8_t sl_usbd_vendor_winusb_number = 0; + +sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, +}; + +//**************************************************************************** +// Callback functions. + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_enable_event(); + + return; +} + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_disable_event(); + + return; +} + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize winusb instance */ +void sli_usbd_vendor_winusb_init() +{ + bool intr_en = true; + uint16_t interval = 0; + + uint8_t class_number = 0; + uint8_t config_number = 0; + + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } + + // add device class GUID to WinUSB properties + sl_usbd_vendor_add_microsoft_ext_property( + config_number, + SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, + (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, + DEVICEINTERFACE_GUID_PROP_NAME_LEN, + (const uint8_t *)UsbClassVendorDeviceInterfaceGuid, + sizeof(UsbClassVendorDeviceInterfaceGuid)); +} + +void sl_usbd_vendor_winusb_on_enable_event(void) +{ +} + +void sl_usbd_vendor_winusb_on_disable_event(void) +{ +} + +void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) +{ + (void)p_setup_req; +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h new file mode 100644 index 0000000000..23e4b3a410 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -0,0 +1,36 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_VENDOR_INSTANCES_INIT +#define SL_USBD_CLASS_VENDOR_INSTANCES_INIT + +#include + +#define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" + +/// Length of GUID Property Name +#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) + +// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) +#define DEVICE_CLASS_GUID_PROPERTY L"{00000000-0000-0000-0000-000000000000}" +#define DEVICE_CLASS_GUID_PROPERTY_LEN sizeof(DEVICE_CLASS_GUID_PROPERTY) + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_vendor_winusb_number; +extern char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; + +/* event handlers for all vendor instances */ + +__WEAK void sl_usbd_vendor_winusb_on_enable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_disable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); + +/* init functions for all vendor instances */ + +void sli_usbd_vendor_winusb_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h deleted file mode 100644 index 59a640a77e..0000000000 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h +++ /dev/null @@ -1,15 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_WINUSB_H -#define SL_USBD_CLASS_WINUSB_H - -#define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" - -/// Length of GUID Property Name -#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) - -#endif // SL_USBD_CLASS_WINUSB_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp new file mode 100644 index 0000000000..a5ea1d3705 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp @@ -0,0 +1,253 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////////////////////////////////////////////////////////////////////////////////////////////////// +// Need to add these here, until Silabs fixes the include files. +// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // +// It's reportedly fixed and will be available in GCC 13. +////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USBD_CFG_HS_EN 0 +#define USBD_CFG_EP_ISOC_EN 0 +////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; +extern uint8_t sl_usbd_vendor_winusb_number; +extern "C" void sli_usbd_vendor_winusb_init(void); + +// -- // + +static void UsbAsyncWriteCompleted( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_callback_arg, + sl_status_t status) +{ + (void)class_nbr; + (void)p_buf; + (void)buf_len; + (void)xfer_len; + (void)p_callback_arg; + (void)status; +} + +// -- // + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + const char *deviceDescription; + const char *deviceClassGuid; + + // get device class GUID + deviceClassGuid = stack.Arg1().RecoverString(); + ; + + // clear destination + memset(UsbClassVendorDeviceInterfaceGuid, 0, sizeof(UsbClassVendorDeviceInterfaceGuid)); + + for (uint16_t i = 0; i < sizeof(UsbClassVendorDeviceInterfaceGuid); i += 2) + { + UsbClassVendorDeviceInterfaceGuid[i] = *deviceClassGuid++; + } + + // get description + deviceDescription = stack.Arg2().RecoverString(); + FAULT_ON_NULL(deviceDescription); + + // store device description + hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); + + sli_usbd_vendor_winusb_init(); + + stack.SetResult_I4(sl_usbd_vendor_winusb_number); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array *dataBuffer; + CLR_RT_HeapBlock hbTimeout; + int64_t *timeoutTicks; + bool eventResult = true; + bool isLongRunningOperation = false; + uint32_t estimatedDurationMiliseconds; + + uint8_t *data; + uint32_t length = 0; + uint32_t count = 0; + uint32_t offset = 0; + sl_status_t reqStatus; + bool conn; + uint32_t bytesTransfered; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // perform parameter validation and setup TX operation + + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + offset = stack.Arg2().NumericByRef().s4; + count = stack.Arg3().NumericByRef().s4; + + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // check parameters + FAULT_ON_NULL_ARG(dataBuffer); + + if ((offset > length) || (count > length)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (offset + count > length) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // check for long runnign operation: over 10 blocks of 64 bytes (USB payload) + if (count > 64 * 10) + { + isLongRunningOperation = true; + + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + } + + if (isLongRunningOperation) + { + // setup timeout + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + } + + // check if device is connected (enabled) + sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); + + if (!conn) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (isLongRunningOperation) + { + // this is a long running operation... + if (stack.m_customState == 1) + { + // ... and hasn't started yet + // push onto the eval stack how many bytes are being pushed to the USB + stack.PushValueI4(count); + + // bump custom state + stack.m_customState = 2; + + // start write operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_write_bulk_async( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + UsbAsyncWriteCompleted, + NULL, + true); + + _ASSERTE(reqStatus == SL_STATUS_OK); + } + } + else + { + // this is NOT a long running operation + // perform write operation with sync API + reqStatus = sl_usbd_vendor_write_bulk_sync( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + 0, + true, + &bytesTransfered); + + _ASSERTE(reqStatus == SL_STATUS_OK); + + // check bytes transfered + if (bytesTransfered != count) + { + // something went wrong + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_I2cMaster, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} From 3059a2131cdba43d642c1fa09e9633ed03217a63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 6 Oct 2022 19:09:22 +0100 Subject: [PATCH 198/572] Move and remove unnecessary config files for WinUSB in SKY_EEVB_PROTO1 --- .../SKY_EEVB_PROTO1/CMakeLists.txt | 2 - .../autogen/sl_usbd_class_vendor_instances.c | 207 ------------------ .../autogen/sl_usbd_class_vendor_instances.h | 26 --- .../config/sl_usbd_class_winusb_config.h | 5 +- .../config/sl_usbd_core_config.h | 7 + .../SKY_EEVB_PROTO1/nanoCLR/main.c | 37 +++- 6 files changed, 43 insertions(+), 241 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c delete mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt index 9fedae80e7..a240dd3202 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -34,7 +34,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Skyworks\ EEVB\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GQ100=1 @@ -44,7 +43,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Skyworks\ EEVB\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c deleted file mode 100644 index 51e9e896a5..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.c +++ /dev/null @@ -1,207 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include "sl_status.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - -#include -#include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "sl_usbd_class_vendor.h" - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_vendor_instances.h" - -/* include config file for the instances */ - -#include "sl_usbd_class_winusb_config.h" - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for winusb instance */ - -void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); - -void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); - -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); - -//**************************************************************************** -// Global variables. - -/* variables for winusb instance */ - -uint8_t sl_usbd_vendor_winusb_number = 0; - -sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { - sli_usbd_vendor_winusb_enable, - sli_usbd_vendor_winusb_disable, - sli_usbd_vendor_winusb_setup_req, -}; - -//**************************************************************************** -// Callback functions. - -void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_enable_event(); - - return; -} - -void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_disable_event(); - - return; -} - -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); - - return; -} - -//**************************************************************************** -// Global functions. - -/* initialize winusb instance */ -void sli_usbd_vendor_winusb_init() -{ - bool intr_en = true; - uint16_t interval = 0; - - uint8_t class_number = 0; - uint8_t config_number = 0; - - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; - - /* read interrupt enable flag */ - intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; - - /* read interval */ - interval = SL_USBD_VENDOR_WINUSB_INTERVAL; - - /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); - - /* store class number globally */ - sl_usbd_vendor_winusb_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } - - // add device class GUID to WinUSB properties - sl_usbd_vendor_add_microsoft_ext_property( - config_number, - SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, - (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, - DEVICEINTERFACE_GUID_PROP_NAME_LEN, - (const uint8_t *)DEVICE_CLASS_GUID_PROPERTY, - sizeof(DEVICE_CLASS_GUID_PROPERTY)); -} - -void sl_usbd_vendor_winusb_on_enable_event(void) -{ -} - -void sl_usbd_vendor_winusb_on_disable_event(void) -{ -} - -void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) -{ - (void)p_setup_req; -} - -// USB bus events. -void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) -{ - switch (event) - { - case SL_USBD_EVENT_BUS_CONNECT: - // called when usb cable is inserted in a host controller - break; - - case SL_USBD_EVENT_BUS_DISCONNECT: - // called when usb cable is removed from a host controller - break; - - case SL_USBD_EVENT_BUS_RESET: - // called when the host sends reset command - break; - - case SL_USBD_EVENT_BUS_SUSPEND: - // called when the host sends suspend command - break; - - case SL_USBD_EVENT_BUS_RESUME: - // called when the host sends wake up command - break; - - default: - break; - } -} - -// USB configuration events. -void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) -{ - (void)config_nbr; - - switch (event) - { - case SL_USBD_EVENT_CONFIG_SET: - // called when the host sets a configuration after reset - break; - - case SL_USBD_EVENT_CONFIG_UNSET: - // called when a configuration is unset due to reset command - break; - - default: - break; - } -} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h deleted file mode 100644 index 0d411ca785..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_vendor_instances.h +++ /dev/null @@ -1,26 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_VENDOR_INSTANCES_INIT -#define SL_USBD_CLASS_VENDOR_INSTANCES_INIT - -#include - -/* class numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_vendor_winusb_number; - -/* event handlers for all vendor instances */ - -__WEAK void sl_usbd_vendor_winusb_on_enable_event(void); -__WEAK void sl_usbd_vendor_winusb_on_disable_event(void); -__WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); - -/* init functions for all vendor instances */ - -void sli_usbd_vendor_winusb_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h index 50f40785bb..53ccff0cd9 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h @@ -7,10 +7,7 @@ #ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H #define SL_USBD_VENDOR_WINUSB_CONFIG_H -#include - -// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) -#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" // <<< Use Configuration Wizard in Context Menu >>> diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h index 24ec038d55..b1c68ffeeb 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h @@ -7,6 +7,8 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H +extern char UsbClassVendorDescription[32 + 1]; + // <<< Use Configuration Wizard in Context Menu >>> // USB Configuration @@ -188,6 +190,11 @@ // Number of configurations. #define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 +// Device Serial Number +// Default: "1234567890ABCDEF" +// Device serial number string. +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + // // diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c index a40ab0cbdc..2c2caa70e4 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -11,6 +11,7 @@ #include #include #include +#include #include @@ -24,7 +25,6 @@ extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); -extern void sli_usbd_vendor_winusb_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -59,14 +59,47 @@ TX_THREAD clrStartupThread; uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; extern void ClrStartupThread_entry(uint32_t parameter); +extern sl_status_t sl_usbd_vendor_read_bulk_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, + bool *p_enabled); + void BlinkThread_entry(uint32_t parameter) { (void)parameter; +// uint8_t buffer[10]; +// uint32_t p_xfer_len; +// sl_status_t reqStatus; +// bool conn; while (1) { //GPIO_PinOutToggle(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1); tx_thread_sleep(TX_TICKS_PER_MILLISEC(250)); + + // // Wait for device connection. + // reqStatus = sl_usbd_vendor_is_enabled(1, &conn); + // _ASSERTE(reqStatus == SL_STATUS_OK); + + // while (conn != true) + // { + // tx_thread_sleep(TX_TICKS_PER_MILLISEC(250)); + + // reqStatus = sl_usbd_vendor_is_enabled(1, &conn); + + // _ASSERTE(reqStatus == SL_STATUS_OK); + // } + + // reqStatus = sl_usbd_vendor_read_bulk_sync(1, + // (void *)buffer, + // 3, + // 0, + // &p_xfer_len); + + // _ASSERTE(reqStatus == SL_STATUS_OK); } } @@ -178,7 +211,7 @@ void tx_application_define(void *first_unused_memory) #endif #if GECKO_FEATURE_USBD_WINUSB == TRUE - sli_usbd_vendor_winusb_init(); + //sli_usbd_vendor_winusb_init(); #endif #if HAL_WP_USE_USB_CDC == TRUE From e7ca36eb30a9a68917b6151f15b719ff951d3d11 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 6 Oct 2022 19:12:18 +0100 Subject: [PATCH 199/572] Move and remove unnecessary config files for WinUSB in SL_STK3701A --- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 - .../autogen/sl_usbd_class_vendor_instances.c | 207 ------------------ .../autogen/sl_usbd_class_vendor_instances.h | 26 --- .../config/sl_usbd_class_winusb_config.h | 5 - .../SL_STK3701A/config/sl_usbd_core_config.h | 2 + .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 5 - 6 files changed, 2 insertions(+), 245 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8c39c9c4d2..8bd99ba614 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,7 +37,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -48,7 +47,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c deleted file mode 100644 index 8421c3fa75..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ /dev/null @@ -1,207 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include "sl_status.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - -#include -#include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "sl_usbd_class_vendor.h" - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_vendor_instances.h" - -/* include config file for the instances */ - -#include "sl_usbd_class_winusb_config.h" - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for winusb instance */ - -void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); - -void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); - -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); - -//**************************************************************************** -// Global variables. - -/* variables for winusb instance */ - -uint8_t sl_usbd_vendor_winusb_number = 0; - -sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { - sli_usbd_vendor_winusb_enable, - sli_usbd_vendor_winusb_disable, - sli_usbd_vendor_winusb_setup_req, -}; - -//**************************************************************************** -// Callback functions. - -void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_enable_event(); - - return; -} - -void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_disable_event(); - - return; -} - -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); - - return; -} - -//**************************************************************************** -// Global functions. - -/* initialize winusb instance */ -void sli_usbd_vendor_winusb_init() -{ - bool intr_en = true; - uint16_t interval = 0; - - uint8_t class_number = 0; - uint8_t config_number = 0; - - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; - - /* read interrupt enable flag */ - intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; - - /* read interval */ - interval = SL_USBD_VENDOR_WINUSB_INTERVAL; - - /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); - - /* store class number globally */ - sl_usbd_vendor_winusb_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } - - // add device class GUID to WinUSB properties - sl_usbd_vendor_add_microsoft_ext_property( - config_number, - SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, - (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, - DEVICEINTERFACE_GUID_PROP_NAME_LEN, - (const uint8_t *)DEVICE_CLASS_GUID_PROPERTY, - sizeof(DEVICE_CLASS_GUID_PROPERTY)); -} - -void sl_usbd_vendor_winusb_on_enable_event(void) -{ -} - -void sl_usbd_vendor_winusb_on_disable_event(void) -{ -} - -void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) -{ - (void)&p_setup_req; -} - -// USB bus events. -void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) -{ - switch (event) - { - case SL_USBD_EVENT_BUS_CONNECT: - // called when usb cable is inserted in a host controller - break; - - case SL_USBD_EVENT_BUS_DISCONNECT: - // called when usb cable is removed from a host controller - break; - - case SL_USBD_EVENT_BUS_RESET: - // called when the host sends reset command - break; - - case SL_USBD_EVENT_BUS_SUSPEND: - // called when the host sends suspend command - break; - - case SL_USBD_EVENT_BUS_RESUME: - // called when the host sends wake up command - break; - - default: - break; - } -} - -// USB configuration events. -void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) -{ - (void)config_nbr; - - switch (event) - { - case SL_USBD_EVENT_CONFIG_SET: - // called when the host sets a configuration after reset - break; - - case SL_USBD_EVENT_CONFIG_UNSET: - // called when a configuration is unset due to reset command - break; - - default: - break; - } -} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h deleted file mode 100644 index 0d411ca785..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.h +++ /dev/null @@ -1,26 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_VENDOR_INSTANCES_INIT -#define SL_USBD_CLASS_VENDOR_INSTANCES_INIT - -#include - -/* class numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_vendor_winusb_number; - -/* event handlers for all vendor instances */ - -__WEAK void sl_usbd_vendor_winusb_on_enable_event(void); -__WEAK void sl_usbd_vendor_winusb_on_disable_event(void); -__WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); - -/* init functions for all vendor instances */ - -void sli_usbd_vendor_winusb_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h index 24bc732064..4da7f4409b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -7,11 +7,6 @@ #ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H #define SL_USBD_VENDOR_WINUSB_CONFIG_H -#include - -// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) -#define DEVICE_CLASS_GUID_PROPERTY L"{9e48651c-fa68-4b39-8731-1ee84659aac5}" - // <<< Use Configuration Wizard in Context Menu >>> // Class Configuration diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h index 24ec038d55..f822724cd4 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -7,6 +7,8 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H +extern char UsbClassVendorDescription[32 + 1]; + // <<< Use Configuration Wizard in Context Menu >>> // USB Configuration diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 9b0cea2239..e18c993d26 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -25,7 +25,6 @@ extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); -extern void sli_usbd_vendor_winusb_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -178,10 +177,6 @@ void tx_application_define(void *first_unused_memory) usb_device_hid_app_init(); #endif -#if GECKO_FEATURE_USBD_WINUSB == TRUE - sli_usbd_vendor_winusb_init(); -#endif - #if HAL_WP_USE_USB_CDC == TRUE sli_usbd_cdc_acm_acm0_init(); usb_device_cdc_acm_app_init(); From caa658df20b85f9dc2c997af3c46bc26e16ccab9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 12:38:18 +0100 Subject: [PATCH 200/572] Add events for USB Device --- src/CLR/Include/nanoCLR_Runtime.h | 2 ++ src/HAL/Include/nanoHAL_v2.h | 8 +++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/CLR/Include/nanoCLR_Runtime.h b/src/CLR/Include/nanoCLR_Runtime.h index 21d608d9b9..92c646bcdc 100644 --- a/src/CLR/Include/nanoCLR_Runtime.h +++ b/src/CLR/Include/nanoCLR_Runtime.h @@ -3392,6 +3392,8 @@ typedef enum Events Event_Radio = 0x00000400, Event_Wifi_Station = 0x00000800, Event_Bluetooth = 0x00001000, + Event_UsbIn = 0x00002000, + Event_UsbOut = 0x00004000, Event_AppDomain = 0x02000000, Event_Socket = 0x20000000, Event_IdleCPU = 0x40000000, diff --git a/src/HAL/Include/nanoHAL_v2.h b/src/HAL/Include/nanoHAL_v2.h index 3bd5acc3a8..ce59095fe7 100644 --- a/src/HAL/Include/nanoHAL_v2.h +++ b/src/HAL/Include/nanoHAL_v2.h @@ -61,6 +61,8 @@ typedef enum SLEEP_LEVEL #define SYSTEM_EVENT_FLAG_COM_OUT 0x00000002 #define SYSTEM_EVENT_FLAG_STORAGE_IO 0x00000004 #define SYSTEM_EVENT_FLAG_SYSTEM_TIMER 0x00000010 +#define SYSTEM_EVENT_FLAG_USB_IN 0x00000020 +#define SYSTEM_EVENT_FLAG_USB_OUT 0x00000040 //#define SYSTEM_EVENT_FLAG_TIMER1 0x00000020 //#define SYSTEM_EVENT_FLAG_TIMER2 0x00000040 //#define SYSTEM_EVENT_FLAG_BUTTON 0x00000080 @@ -108,9 +110,9 @@ typedef enum SLEEP_LEVEL #define EVENT_RADIO 80 #define EVENT_HIGH_RESOLUTION_TIMER 90 #define EVENT_BLUETOOTH 100 - -#define EVENT_TOUCH 120 -#define EVENT_GESTURE 130 +#define EVENT_USB 110 +#define EVENT_TOUCH 120 +#define EVENT_GESTURE 130 #define PAL_EVENT_TOUCH 0x1 #define PAL_EVENT_KEY 0x2 From b24661afee49868b078cc74ca8fea1781f1f7ba3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 15:05:07 +0100 Subject: [PATCH 201/572] Improvements in UsbCLient - Following nanoframework/System.Device.UsbClient#3. --- .../Modules/FindSystem.Device.UsbStream.cmake | 1 + .../System.Device.UsbStream.filters | 3 + .../System.Device.UsbStream.vcxproj | 3 +- .../sys_dev_usbstream_native.cpp | 24 ++- .../sys_dev_usbstream_native.h | 35 ++++ ...ystem_Device_UsbClient_UsbClient_stubs.cpp | 16 ++ .../autogen/sl_usbd_class_vendor_instances.c | 13 ++ ...tive_System_Device_UsbClient_UsbClient.cpp | 23 +++ ...tive_System_Device_UsbClient_UsbStream.cpp | 161 +++++++++++++++++- 9 files changed, 274 insertions(+), 5 deletions(-) create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp diff --git a/CMake/Modules/FindSystem.Device.UsbStream.cmake b/CMake/Modules/FindSystem.Device.UsbStream.cmake index 8579a6e592..c82b1102b1 100644 --- a/CMake/Modules/FindSystem.Device.UsbStream.cmake +++ b/CMake/Modules/FindSystem.Device.UsbStream.cmake @@ -21,6 +21,7 @@ set(System.Device.UsbStream_SRCS sys_dev_usbstream_native.cpp + sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp ) diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.filters b/src/System.Device.UsbStream/System.Device.UsbStream.filters index 7f41043a0f..c5ff73772c 100644 --- a/src/System.Device.UsbStream/System.Device.UsbStream.filters +++ b/src/System.Device.UsbStream/System.Device.UsbStream.filters @@ -15,6 +15,9 @@ + + Source Files + Source Files diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj index 59b2a20d17..56503ccdf8 100644 --- a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj +++ b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj @@ -19,8 +19,9 @@ + - + diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 933e866f0a..25a8acabf4 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -9,6 +9,27 @@ static const CLR_RT_MethodHandler method_lookup[] = { + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, NULL, NULL, NULL, @@ -35,9 +56,10 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x79416300, + 0x6E619AF7, method_lookup, { 1, 0, 0, 0 } }; + // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 246c9c9c20..23a6133507 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -11,6 +11,41 @@ #include #include +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +// moved to targets\AzureRTOS\SiliconLabs\_common\autogen\sl_usbd_class_vendor_instances.c for convenience // +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +// typedef enum __nfpack UsbEventType +// { +// UsbEventType_Invalid = 0, +// UsbEventType_DeviceConnected = 1, +// UsbEventType_DeviceDisconnected = 2, +// } UsbEventType; + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_DeviceConnectionEventArgs +{ + static const int FIELD___isConnected = 1; + + //--// +}; + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient +{ + static const int FIELD_STATIC__UsbDeviceConnectionChanged = 0; + + NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); + + //--// +}; + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbDeviceEvent +{ + static const int FIELD___eventType = 3; + static const int FIELD___eventData = 4; + static const int FIELD___interfaceIndex = 5; + + //--// +}; + struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream { static const int FIELD___streamIndex = 2; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp new file mode 100644 index 0000000000..70aa7f8645 --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp @@ -0,0 +1,16 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_usbstream_native.h" + + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 0b85bfd1e1..1943c27e02 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -8,6 +8,7 @@ // Includes. #include "sl_status.h" +#include #ifdef __GNUC__ #pragma GCC diagnostic push @@ -31,10 +32,20 @@ #include +// need to declare this here as extern +extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2); + // storage for USB class vendor description char UsbClassVendorDescription[32 + 1]; char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; +typedef enum __nfpack UsbEventType +{ + UsbEventType_Invalid = 0, + UsbEventType_DeviceConnected = 1, + UsbEventType_DeviceDisconnected = 2, +} UsbEventType; + //**************************************************************************** // Function declarations. @@ -167,10 +178,12 @@ void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) { case SL_USBD_EVENT_BUS_CONNECT: // called when usb cable is inserted in a host controller + PostManagedEvent(EVENT_USB, 0, UsbEventType_DeviceConnected, 0); break; case SL_USBD_EVENT_BUS_DISCONNECT: // called when usb cable is removed from a host controller + PostManagedEvent(EVENT_USB, 0, UsbEventType_DeviceDisconnected, 0); break; case SL_USBD_EVENT_BUS_RESET: diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp new file mode 100644 index 0000000000..ecb7504c00 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp @@ -0,0 +1,23 @@ +//----------------------------------------------------------------------------- +// +// ** WARNING! ** +// This file was generated automatically by a tool. +// Re-running the tool will overwrite this file. +// You should copy this file to a custom location +// before adding any customization in the copy to +// prevent loss of your changes when the tool is +// re-run. +// +//----------------------------------------------------------------------------- + +#include "sys_dev_usbstream_native.h" + + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp index a5ea1d3705..a7528506f9 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp @@ -37,6 +37,26 @@ static void UsbAsyncWriteCompleted( (void)xfer_len; (void)p_callback_arg; (void)status; + + Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); +} + +static void UsbAsyncReadCompleted( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_callback_arg, + sl_status_t status) +{ + (void)class_nbr; + (void)p_buf; + (void)buf_len; + (void)xfer_len; + (void)p_callback_arg; + (void)status; + + Events_Set(SYSTEM_EVENT_FLAG_USB_IN); } // -- // @@ -228,9 +248,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati break; } - // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_I2cMaster, eventResult)); + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } if (isLongRunningOperation) @@ -247,7 +267,142 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + CLR_RT_HeapBlock_Array *dataBuffer; + CLR_RT_HeapBlock hbTimeout; + int64_t *timeoutTicks; + bool eventResult = true; + bool isLongRunningOperation = false; + uint32_t estimatedDurationMiliseconds; + + uint8_t *data; + uint32_t length = 0; + uint32_t count = 0; + uint32_t offset = 0; + sl_status_t reqStatus; + bool conn; + uint32_t bytesTransfered; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // perform parameter validation and setup TX operation + + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + offset = stack.Arg2().NumericByRef().s4; + count = stack.Arg3().NumericByRef().s4; + + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // check parameters + FAULT_ON_NULL_ARG(dataBuffer); + + if ((offset > length) || (count > length)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (offset + count > length) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // check for long runnign operation: over 10 blocks of 64 bytes (USB payload) + if (count > 64 * 10) + { + isLongRunningOperation = true; + + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + } + + if (isLongRunningOperation) + { + // setup timeout + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + } + + // check if device is connected (enabled) + sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); + + if (!conn) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (isLongRunningOperation) + { + // this is a long running operation... + if (stack.m_customState == 1) + { + // ... and hasn't started yet + // push onto the eval stack how many bytes are being pushed to the USB + stack.PushValueI4(count); + + // bump custom state + stack.m_customState = 2; + + // start read operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_read_bulk_async( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + UsbAsyncReadCompleted, + NULL); + + _ASSERTE(reqStatus == SL_STATUS_OK); + } + } + else + { + // this is NOT a long running operation + // perform read operation with sync API + reqStatus = + sl_usbd_vendor_read_bulk_sync(sl_usbd_vendor_winusb_number, (void *)data, count, 0, &bytesTransfered); + + _ASSERTE(reqStatus == SL_STATUS_OK); + + // check bytes transfered + if (bytesTransfered != count) + { + // something went wrong + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + // non-blocking wait allowing other threads to run while we wait for the USB operation to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + stack.SetResult_I4(bytesTransfered); NANOCLR_NOCLEANUP(); } From ffa935137640cbee2c0a0ea10af5c7717e25328d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 16:29:49 +0100 Subject: [PATCH 202/572] Add native implementation for UsbClient --- ...tive_System_Device_UsbClient_UsbClient.cpp | 24 ++++++++++--------- ...tive_System_Device_UsbClient_UsbStream.cpp | 19 +-------------- .../sys_dev_usbstream_native_target.h | 20 ++++++++++++++++ 3 files changed, 34 insertions(+), 29 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp index ecb7504c00..ff68957217 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp @@ -1,23 +1,25 @@ -//----------------------------------------------------------------------------- // -// ** WARNING! ** -// This file was generated automatically by a tool. -// Re-running the tool will overwrite this file. -// You should copy this file to a custom location -// before adding any customization in the copy to -// prevent loss of your changes when the tool is -// re-run. +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. // -//----------------------------------------------------------------------------- #include "sys_dev_usbstream_native.h" - +#include "sys_dev_usbstream_native_target.h" HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + bool conn; + + if(sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) + { + stack.SetResult_Boolean(conn); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp index a7528506f9..b039ec3ac0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp @@ -4,24 +4,7 @@ // #include - -////////////////////////////////////////////////////////////////////////////////////////////////////// -// Need to add these here, until Silabs fixes the include files. -// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // -// It's reportedly fixed and will be available in GCC 13. -////////////////////////////////////////////////////////////////////////////////////////////////////// -#define USBD_CFG_HS_EN 0 -#define USBD_CFG_EP_ISOC_EN 0 -////////////////////////////////////////////////////////////////////////////////////////////////////// - -#include - -extern char UsbClassVendorDescription[32 + 1]; -extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; -extern uint8_t sl_usbd_vendor_winusb_number; -extern "C" void sli_usbd_vendor_winusb_init(void); - -// -- // +#include "sys_dev_usbstream_native_target.h" static void UsbAsyncWriteCompleted( uint8_t class_nbr, diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h new file mode 100644 index 0000000000..e39323f203 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////////////////// +// Need to add these here, until Silabs fixes the include files. +// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // +// It's reportedly fixed and will be available in GCC 13. +////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USBD_CFG_HS_EN 0 +#define USBD_CFG_EP_ISOC_EN 0 +////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; +extern uint8_t sl_usbd_vendor_winusb_number; +extern "C" void sli_usbd_vendor_winusb_init(void); From 5cb2fe8f5504e7605145a8210f354c250974b968 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 16:52:08 +0100 Subject: [PATCH 203/572] Update cmake user template --- CMakeUserPresets.TEMPLATE.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 25273dcc17..9a05f38d10 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -168,11 +168,11 @@ }, "TARGET_SERIAL_BAUDRATE": "115200", "GECKO_FEATURE_USBD_HID": "OFF", - "GECKO_FEATURE_USBD_WINUSB": "OFF", "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_System.Device.Adc": "OFF", "API_nanoFramework.GiantGecko.Adc": "ON", + "API_System.Device.UsbStream": "OFF", "NF_INTEROP_ASSEMBLIES": null } }, From 49a2055f1b08807c12b9dfcdcb2be71d345bf5ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 16:55:46 +0100 Subject: [PATCH 204/572] Fix comment on USB config define --- .../SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h index b1c68ffeeb..a604eb6826 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h @@ -190,9 +190,7 @@ extern char UsbClassVendorDescription[32 + 1]; // Number of configurations. #define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 -// Device Serial Number -// Default: "1234567890ABCDEF" -// Device serial number string. +// pointer to USB Class Vendor description #define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription // From fb30e2b2dc3abd30fae206b1cd127911efe69109 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 16:56:40 +0100 Subject: [PATCH 205/572] Fix comment on USB config define for SL_STK3701A --- .../SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h index f822724cd4..a604eb6826 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -190,6 +190,9 @@ extern char UsbClassVendorDescription[32 + 1]; // Number of configurations. #define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + // // From d77c24515192ff18066877f416ad600ad0df1334 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 3 Oct 2022 10:02:47 +0100 Subject: [PATCH 206/572] Improve comment about device class GUID --- .../SL_STK3701A/config/sl_usbd_class_winusb_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h index cdaa68dac3..24bc732064 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -9,7 +9,7 @@ #include -/// device class GUID for WinUSB (going into DeviceInterfaceGUID extended property) +// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) #define DEVICE_CLASS_GUID_PROPERTY L"{9e48651c-fa68-4b39-8731-1ee84659aac5}" // <<< Use Configuration Wizard in Context Menu >>> From a79a905a49cae856819d932518e3ede156ac6473 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 6 Oct 2022 19:08:41 +0100 Subject: [PATCH 207/572] Initial work adding native implementation for UsbDevice --- CMake/Modules/FindGecko_SDK.cmake | 6 +- CMake/Modules/FindNF_NativeAssemblies.cmake | 7 + .../Modules/FindSystem.Device.UsbStream.cmake | 51 ++++ .../System.Device.UsbStream.filters | 30 +++ .../System.Device.UsbStream.vcxproj | 162 +++++++++++ .../sys_dev_usbstream_native.cpp | 43 +++ .../sys_dev_usbstream_native.h | 30 +++ ...ystem_Device_UsbClient_UsbStream_stubs.cpp | 54 ++++ targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 7 +- .../autogen/sl_usbd_class_vendor_instances.c | 211 +++++++++++++++ .../autogen/sl_usbd_class_vendor_instances.h | 36 +++ .../_common/autogen/sl_usbd_class_winusb.h | 15 -- ...tive_System_Device_UsbClient_UsbStream.cpp | 253 ++++++++++++++++++ 13 files changed, 884 insertions(+), 21 deletions(-) create mode 100644 CMake/Modules/FindSystem.Device.UsbStream.cmake create mode 100644 src/System.Device.UsbStream/System.Device.UsbStream.filters create mode 100644 src/System.Device.UsbStream/System.Device.UsbStream.vcxproj create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native.cpp create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native.h create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h delete mode 100644 targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 94cea3f016..2555bc9fb6 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -281,12 +281,12 @@ if(GECKO_FEATURE_USBD_WINUSB) string(REPLACE "\"Vendor-specific class\"" NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION - SL_USBD_CLASS_VENDOR__NEW_CONTENTS + SL_USBD_CLASS_VENDOR_NEW_CONTENTS "${SL_USBD_CLASS_VENDOR_CONTENT}") file(WRITE ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - "${SL_USBD_CLASS_VENDOR__NEW_CONTENTS}") + "${SL_USBD_CLASS_VENDOR_NEW_CONTENTS}") endif() @@ -310,7 +310,7 @@ macro(nf_add_gecko_sdk) # add THESE has a library set(LIB_NAME gecko_sdk_${NFGCKSDK_BUILD_TARGET}) - + add_library( ${LIB_NAME} STATIC ${Gecko_SDK_SOURCES} diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index 13785b75d2..8f6b77f949 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -29,6 +29,7 @@ option(API_System.Device.Spi "option for System.Device.Spi AP option(API_Windows.Storage "option for Windows.Storage") option(API_nanoFramework.Graphics "option for nanoFramework.Graphics") option(API_nanoFramework.Device.Bluetooth "option for nanoFramework.Device.Bluetooth") +option(API_System.Device.UsbStream "option for System.Device.UsbStream API") # Esp32 only option(API_Hardware.Esp32 "option for Hardware.Esp32") @@ -326,6 +327,12 @@ if(API_System.Device.Wifi) PerformSettingsForApiEntry("System.Device.Wifi") endif() +# System.Device.UsbStream +if(API_System.Device.UsbStream) + ##### API name here (doted name) + PerformSettingsForApiEntry("System.Device.UsbStream") +endif() + # Windows.Storage if(API_Windows.Storage) ##### API name here (doted name) diff --git a/CMake/Modules/FindSystem.Device.UsbStream.cmake b/CMake/Modules/FindSystem.Device.UsbStream.cmake new file mode 100644 index 0000000000..8579a6e592 --- /dev/null +++ b/CMake/Modules/FindSystem.Device.UsbStream.cmake @@ -0,0 +1,51 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Device.UsbStream) + + +# set include directories +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND System.Device.UsbStream_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/System.Device.UsbStream) + +# source files +set(System.Device.UsbStream_SRCS + + sys_dev_usbstream_native.cpp + + + sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp + +) + +foreach(SRC_FILE ${System.Device.UsbStream_SRCS}) + + set(System.Device.UsbStream_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(System.Device.UsbStream_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/System.Device.UsbStream + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${System.Device.UsbStream_SRC_FILE}") + endif() + + list(APPEND System.Device.UsbStream_SOURCES ${System.Device.UsbStream_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(System.Device.UsbStream DEFAULT_MSG System.Device.UsbStream_INCLUDE_DIRS System.Device.UsbStream_SOURCES) diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.filters b/src/System.Device.UsbStream/System.Device.UsbStream.filters new file mode 100644 index 0000000000..7f41043a0f --- /dev/null +++ b/src/System.Device.UsbStream/System.Device.UsbStream.filters @@ -0,0 +1,30 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + + + Header Files + + + \ No newline at end of file diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj new file mode 100644 index 0000000000..59b2a20d17 --- /dev/null +++ b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj @@ -0,0 +1,162 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + {71fbf8bd-5386-4ea9-9e6b-ec36470fc021} + Win32Proj + System.Device.UsbStream + 10.0.19041.0 + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;NANOCLR_SYSTEM_COLLECTIONS=TRUE;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;NANOCLR_SYSTEM_COLLECTIONS=TRUE;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp new file mode 100644 index 0000000000..933e866f0a --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -0,0 +1,43 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_usbstream_native.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = +{ + "System.Device.UsbStream", + 0x79416300, + method_lookup, + { 1, 0, 0, 0 } +}; + +// clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h new file mode 100644 index 0000000000..246c9c9c20 --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -0,0 +1,30 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_DEV_USBSTREAM_NATIVE_H +#define SYS_DEV_USBSTREAM_NATIVE_H + +#include +#include +#include +#include + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream +{ + static const int FIELD___streamIndex = 2; + static const int FIELD___disposed = 3; + + NANOCLR_NATIVE_DECLARE(Flush___VOID); + NANOCLR_NATIVE_DECLARE(NativeClose___VOID); + NANOCLR_NATIVE_DECLARE(NativeOpen___I4__STRING__STRING); + NANOCLR_NATIVE_DECLARE(NativeWrite___VOID__SZARRAY_U1__I4__I4); + NANOCLR_NATIVE_DECLARE(NativeRead___I4__SZARRAY_U1__I4__I4); + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream; + +#endif // SYS_DEV_USBSTREAM_NATIVE_H diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp new file mode 100644 index 0000000000..beaba35c7b --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp @@ -0,0 +1,54 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index e274b4bb46..901408d261 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -38,12 +38,13 @@ else() set(GECKO_FEATURE_USBD_HID_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_HID for USBD HID") endif() -if(GECKO_FEATURE_USBD_WINUSB) +if(API_System.Device.UsbStream) - set(GECKO_FEATURE_USBD_WINUSB_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") + set(GECKO_FEATURE_USBD_WINUSB_OPTION TRUE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for WinUSB") + set(GECKO_FEATURE_USBD_WINUSB ON PARENT_SCOPE) else() - set(GECKO_FEATURE_USBD_WINUSB_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for USBD HID") + set(GECKO_FEATURE_USBD_WINUSB_OPTION FALSE CACHE INTERNAL "GECKO_FEATURE_USBD_WINUSB for WinUSB") endif() diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c new file mode 100644 index 0000000000..0b85bfd1e1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -0,0 +1,211 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include "sl_status.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wundef" +#endif + +#include +#include "sl_usbd_class_hid.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "sl_usbd_class_vendor.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_vendor_instances.h" + +/* include config file for the instances */ + +#include + +// storage for USB class vendor description +char UsbClassVendorDescription[32 + 1]; +char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for winusb instance */ + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); + +//**************************************************************************** +// Global variables. + +/* variables for winusb instance */ + +uint8_t sl_usbd_vendor_winusb_number = 0; + +sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { + sli_usbd_vendor_winusb_enable, + sli_usbd_vendor_winusb_disable, + sli_usbd_vendor_winusb_setup_req, +}; + +//**************************************************************************** +// Callback functions. + +void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_enable_event(); + + return; +} + +void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_disable_event(); + + return; +} + +void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) +{ + (void)&class_nbr; + + sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize winusb instance */ +void sli_usbd_vendor_winusb_init() +{ + bool intr_en = true; + uint16_t interval = 0; + + uint8_t class_number = 0; + uint8_t config_number = 0; + + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; + + /* read interrupt enable flag */ + intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; + + /* read interval */ + interval = SL_USBD_VENDOR_WINUSB_INTERVAL; + + /* create vendor instance */ + sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_vendor_winusb_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_vendor_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } + + // add device class GUID to WinUSB properties + sl_usbd_vendor_add_microsoft_ext_property( + config_number, + SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, + (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, + DEVICEINTERFACE_GUID_PROP_NAME_LEN, + (const uint8_t *)UsbClassVendorDeviceInterfaceGuid, + sizeof(UsbClassVendorDeviceInterfaceGuid)); +} + +void sl_usbd_vendor_winusb_on_enable_event(void) +{ +} + +void sl_usbd_vendor_winusb_on_disable_event(void) +{ +} + +void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) +{ + (void)p_setup_req; +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h new file mode 100644 index 0000000000..23e4b3a410 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -0,0 +1,36 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_VENDOR_INSTANCES_INIT +#define SL_USBD_CLASS_VENDOR_INSTANCES_INIT + +#include + +#define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" + +/// Length of GUID Property Name +#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) + +// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) +#define DEVICE_CLASS_GUID_PROPERTY L"{00000000-0000-0000-0000-000000000000}" +#define DEVICE_CLASS_GUID_PROPERTY_LEN sizeof(DEVICE_CLASS_GUID_PROPERTY) + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_vendor_winusb_number; +extern char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; + +/* event handlers for all vendor instances */ + +__WEAK void sl_usbd_vendor_winusb_on_enable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_disable_event(void); +__WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req); + +/* init functions for all vendor instances */ + +void sli_usbd_vendor_winusb_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h deleted file mode 100644 index 59a640a77e..0000000000 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_winusb.h +++ /dev/null @@ -1,15 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_WINUSB_H -#define SL_USBD_CLASS_WINUSB_H - -#define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" - -/// Length of GUID Property Name -#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) - -#endif // SL_USBD_CLASS_WINUSB_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp new file mode 100644 index 0000000000..a5ea1d3705 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp @@ -0,0 +1,253 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////////////////////////////////////////////////////////////////////////////////////////////////// +// Need to add these here, until Silabs fixes the include files. +// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // +// It's reportedly fixed and will be available in GCC 13. +////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USBD_CFG_HS_EN 0 +#define USBD_CFG_EP_ISOC_EN 0 +////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; +extern uint8_t sl_usbd_vendor_winusb_number; +extern "C" void sli_usbd_vendor_winusb_init(void); + +// -- // + +static void UsbAsyncWriteCompleted( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_callback_arg, + sl_status_t status) +{ + (void)class_nbr; + (void)p_buf; + (void)buf_len; + (void)xfer_len; + (void)p_callback_arg; + (void)status; +} + +// -- // + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + const char *deviceDescription; + const char *deviceClassGuid; + + // get device class GUID + deviceClassGuid = stack.Arg1().RecoverString(); + ; + + // clear destination + memset(UsbClassVendorDeviceInterfaceGuid, 0, sizeof(UsbClassVendorDeviceInterfaceGuid)); + + for (uint16_t i = 0; i < sizeof(UsbClassVendorDeviceInterfaceGuid); i += 2) + { + UsbClassVendorDeviceInterfaceGuid[i] = *deviceClassGuid++; + } + + // get description + deviceDescription = stack.Arg2().RecoverString(); + FAULT_ON_NULL(deviceDescription); + + // store device description + hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); + + sli_usbd_vendor_winusb_init(); + + stack.SetResult_I4(sl_usbd_vendor_winusb_number); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array *dataBuffer; + CLR_RT_HeapBlock hbTimeout; + int64_t *timeoutTicks; + bool eventResult = true; + bool isLongRunningOperation = false; + uint32_t estimatedDurationMiliseconds; + + uint8_t *data; + uint32_t length = 0; + uint32_t count = 0; + uint32_t offset = 0; + sl_status_t reqStatus; + bool conn; + uint32_t bytesTransfered; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // perform parameter validation and setup TX operation + + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + offset = stack.Arg2().NumericByRef().s4; + count = stack.Arg3().NumericByRef().s4; + + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // check parameters + FAULT_ON_NULL_ARG(dataBuffer); + + if ((offset > length) || (count > length)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (offset + count > length) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // check for long runnign operation: over 10 blocks of 64 bytes (USB payload) + if (count > 64 * 10) + { + isLongRunningOperation = true; + + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + } + + if (isLongRunningOperation) + { + // setup timeout + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + } + + // check if device is connected (enabled) + sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); + + if (!conn) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (isLongRunningOperation) + { + // this is a long running operation... + if (stack.m_customState == 1) + { + // ... and hasn't started yet + // push onto the eval stack how many bytes are being pushed to the USB + stack.PushValueI4(count); + + // bump custom state + stack.m_customState = 2; + + // start write operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_write_bulk_async( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + UsbAsyncWriteCompleted, + NULL, + true); + + _ASSERTE(reqStatus == SL_STATUS_OK); + } + } + else + { + // this is NOT a long running operation + // perform write operation with sync API + reqStatus = sl_usbd_vendor_write_bulk_sync( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + 0, + true, + &bytesTransfered); + + _ASSERTE(reqStatus == SL_STATUS_OK); + + // check bytes transfered + if (bytesTransfered != count) + { + // something went wrong + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_I2cMaster, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} From fa4fa433987e1cbc16b8d5c85d3de0f819942449 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 6 Oct 2022 19:12:18 +0100 Subject: [PATCH 208/572] Move and remove unnecessary config files for WinUSB in SL_STK3701A --- .../SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 - .../autogen/sl_usbd_class_vendor_instances.c | 207 ------------------ .../config/sl_usbd_class_winusb_config.h | 5 - .../SL_STK3701A/config/sl_usbd_core_config.h | 2 + .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 5 - 5 files changed, 2 insertions(+), 219 deletions(-) delete mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8c39c9c4d2..8bd99ba614 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -37,7 +37,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x2000 SL_HEAP_SIZE=0x2000 - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" CLR_EXTRA_COMPILE_DEFINITIONS EFM32GG11B820F2048GL192=1 @@ -48,7 +47,6 @@ nf_setup_target_build( I2CSPM_TRANSFER_TIMEOUT=3000 SL_STACK_SIZE=0x7000 SL_HEAP_SIZE=0x10000 - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Silabs\ STK3701A\" BOOTER_EXTRA_LINKMAP_PROPERTIES ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c deleted file mode 100644 index 8421c3fa75..0000000000 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c +++ /dev/null @@ -1,207 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include "sl_status.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - -#include -#include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "sl_usbd_class_vendor.h" - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_vendor_instances.h" - -/* include config file for the instances */ - -#include "sl_usbd_class_winusb_config.h" - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for winusb instance */ - -void sli_usbd_vendor_winusb_enable(uint8_t class_nbr); - -void sli_usbd_vendor_winusb_disable(uint8_t class_nbr); - -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req); - -//**************************************************************************** -// Global variables. - -/* variables for winusb instance */ - -uint8_t sl_usbd_vendor_winusb_number = 0; - -sl_usbd_vendor_callbacks_t sli_usbd_vendor_winusb_callbacks = { - sli_usbd_vendor_winusb_enable, - sli_usbd_vendor_winusb_disable, - sli_usbd_vendor_winusb_setup_req, -}; - -//**************************************************************************** -// Callback functions. - -void sli_usbd_vendor_winusb_enable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_enable_event(); - - return; -} - -void sli_usbd_vendor_winusb_disable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_disable_event(); - - return; -} - -void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req_t *p_setup_req) -{ - (void)&class_nbr; - - sl_usbd_vendor_winusb_on_setup_request_event(p_setup_req); - - return; -} - -//**************************************************************************** -// Global functions. - -/* initialize winusb instance */ -void sli_usbd_vendor_winusb_init() -{ - bool intr_en = true; - uint16_t interval = 0; - - uint8_t class_number = 0; - uint8_t config_number = 0; - - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; - - /* read interrupt enable flag */ - intr_en = SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS; - - /* read interval */ - interval = SL_USBD_VENDOR_WINUSB_INTERVAL; - - /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); - - /* store class number globally */ - sl_usbd_vendor_winusb_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } - - // add device class GUID to WinUSB properties - sl_usbd_vendor_add_microsoft_ext_property( - config_number, - SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, - (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, - DEVICEINTERFACE_GUID_PROP_NAME_LEN, - (const uint8_t *)DEVICE_CLASS_GUID_PROPERTY, - sizeof(DEVICE_CLASS_GUID_PROPERTY)); -} - -void sl_usbd_vendor_winusb_on_enable_event(void) -{ -} - -void sl_usbd_vendor_winusb_on_disable_event(void) -{ -} - -void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req_t *p_setup_req) -{ - (void)&p_setup_req; -} - -// USB bus events. -void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) -{ - switch (event) - { - case SL_USBD_EVENT_BUS_CONNECT: - // called when usb cable is inserted in a host controller - break; - - case SL_USBD_EVENT_BUS_DISCONNECT: - // called when usb cable is removed from a host controller - break; - - case SL_USBD_EVENT_BUS_RESET: - // called when the host sends reset command - break; - - case SL_USBD_EVENT_BUS_SUSPEND: - // called when the host sends suspend command - break; - - case SL_USBD_EVENT_BUS_RESUME: - // called when the host sends wake up command - break; - - default: - break; - } -} - -// USB configuration events. -void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) -{ - (void)config_nbr; - - switch (event) - { - case SL_USBD_EVENT_CONFIG_SET: - // called when the host sets a configuration after reset - break; - - case SL_USBD_EVENT_CONFIG_UNSET: - // called when a configuration is unset due to reset command - break; - - default: - break; - } -} diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h index 24bc732064..4da7f4409b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_class_winusb_config.h @@ -7,11 +7,6 @@ #ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H #define SL_USBD_VENDOR_WINUSB_CONFIG_H -#include - -// GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) -#define DEVICE_CLASS_GUID_PROPERTY L"{9e48651c-fa68-4b39-8731-1ee84659aac5}" - // <<< Use Configuration Wizard in Context Menu >>> // Class Configuration diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h index 24ec038d55..f822724cd4 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -7,6 +7,8 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H +extern char UsbClassVendorDescription[32 + 1]; + // <<< Use Configuration Wizard in Context Menu >>> // USB Configuration diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index 9b0cea2239..e18c993d26 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -25,7 +25,6 @@ extern void sli_usbd_init(void); extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); -extern void sli_usbd_vendor_winusb_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -178,10 +177,6 @@ void tx_application_define(void *first_unused_memory) usb_device_hid_app_init(); #endif -#if GECKO_FEATURE_USBD_WINUSB == TRUE - sli_usbd_vendor_winusb_init(); -#endif - #if HAL_WP_USE_USB_CDC == TRUE sli_usbd_cdc_acm_acm0_init(); usb_device_cdc_acm_app_init(); From cd2feb8a2ace18b3a2a15e6ca63a5ca6b72ba162 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 15:05:07 +0100 Subject: [PATCH 209/572] Improvements in UsbCLient - Following nanoframework/System.Device.UsbClient#3. --- .../Modules/FindSystem.Device.UsbStream.cmake | 1 + .../System.Device.UsbStream.filters | 3 + .../System.Device.UsbStream.vcxproj | 3 +- .../sys_dev_usbstream_native.cpp | 24 ++- .../sys_dev_usbstream_native.h | 35 ++++ ...ystem_Device_UsbClient_UsbClient_stubs.cpp | 16 ++ .../autogen/sl_usbd_class_vendor_instances.c | 13 ++ ...tive_System_Device_UsbClient_UsbClient.cpp | 23 +++ ...tive_System_Device_UsbClient_UsbStream.cpp | 161 +++++++++++++++++- 9 files changed, 274 insertions(+), 5 deletions(-) create mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp diff --git a/CMake/Modules/FindSystem.Device.UsbStream.cmake b/CMake/Modules/FindSystem.Device.UsbStream.cmake index 8579a6e592..c82b1102b1 100644 --- a/CMake/Modules/FindSystem.Device.UsbStream.cmake +++ b/CMake/Modules/FindSystem.Device.UsbStream.cmake @@ -21,6 +21,7 @@ set(System.Device.UsbStream_SRCS sys_dev_usbstream_native.cpp + sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp ) diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.filters b/src/System.Device.UsbStream/System.Device.UsbStream.filters index 7f41043a0f..c5ff73772c 100644 --- a/src/System.Device.UsbStream/System.Device.UsbStream.filters +++ b/src/System.Device.UsbStream/System.Device.UsbStream.filters @@ -15,6 +15,9 @@ + + Source Files + Source Files diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj index 59b2a20d17..56503ccdf8 100644 --- a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj +++ b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj @@ -19,8 +19,9 @@ + - + diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 933e866f0a..25a8acabf4 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -9,6 +9,27 @@ static const CLR_RT_MethodHandler method_lookup[] = { + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, NULL, NULL, NULL, @@ -35,9 +56,10 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x79416300, + 0x6E619AF7, method_lookup, { 1, 0, 0, 0 } }; + // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 246c9c9c20..23a6133507 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -11,6 +11,41 @@ #include #include +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +// moved to targets\AzureRTOS\SiliconLabs\_common\autogen\sl_usbd_class_vendor_instances.c for convenience // +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +// typedef enum __nfpack UsbEventType +// { +// UsbEventType_Invalid = 0, +// UsbEventType_DeviceConnected = 1, +// UsbEventType_DeviceDisconnected = 2, +// } UsbEventType; + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_DeviceConnectionEventArgs +{ + static const int FIELD___isConnected = 1; + + //--// +}; + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient +{ + static const int FIELD_STATIC__UsbDeviceConnectionChanged = 0; + + NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); + + //--// +}; + +struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbDeviceEvent +{ + static const int FIELD___eventType = 3; + static const int FIELD___eventData = 4; + static const int FIELD___interfaceIndex = 5; + + //--// +}; + struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream { static const int FIELD___streamIndex = 2; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp new file mode 100644 index 0000000000..70aa7f8645 --- /dev/null +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp @@ -0,0 +1,16 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_usbstream_native.h" + + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 0b85bfd1e1..1943c27e02 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -8,6 +8,7 @@ // Includes. #include "sl_status.h" +#include #ifdef __GNUC__ #pragma GCC diagnostic push @@ -31,10 +32,20 @@ #include +// need to declare this here as extern +extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2); + // storage for USB class vendor description char UsbClassVendorDescription[32 + 1]; char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; +typedef enum __nfpack UsbEventType +{ + UsbEventType_Invalid = 0, + UsbEventType_DeviceConnected = 1, + UsbEventType_DeviceDisconnected = 2, +} UsbEventType; + //**************************************************************************** // Function declarations. @@ -167,10 +178,12 @@ void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) { case SL_USBD_EVENT_BUS_CONNECT: // called when usb cable is inserted in a host controller + PostManagedEvent(EVENT_USB, 0, UsbEventType_DeviceConnected, 0); break; case SL_USBD_EVENT_BUS_DISCONNECT: // called when usb cable is removed from a host controller + PostManagedEvent(EVENT_USB, 0, UsbEventType_DeviceDisconnected, 0); break; case SL_USBD_EVENT_BUS_RESET: diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp new file mode 100644 index 0000000000..ecb7504c00 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp @@ -0,0 +1,23 @@ +//----------------------------------------------------------------------------- +// +// ** WARNING! ** +// This file was generated automatically by a tool. +// Re-running the tool will overwrite this file. +// You should copy this file to a custom location +// before adding any customization in the copy to +// prevent loss of your changes when the tool is +// re-run. +// +//----------------------------------------------------------------------------- + +#include "sys_dev_usbstream_native.h" + + +HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp index a5ea1d3705..a7528506f9 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp @@ -37,6 +37,26 @@ static void UsbAsyncWriteCompleted( (void)xfer_len; (void)p_callback_arg; (void)status; + + Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); +} + +static void UsbAsyncReadCompleted( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_callback_arg, + sl_status_t status) +{ + (void)class_nbr; + (void)p_buf; + (void)buf_len; + (void)xfer_len; + (void)p_callback_arg; + (void)status; + + Events_Set(SYSTEM_EVENT_FLAG_USB_IN); } // -- // @@ -228,9 +248,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati break; } - // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_I2cMaster, eventResult)); + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } if (isLongRunningOperation) @@ -247,7 +267,142 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + CLR_RT_HeapBlock_Array *dataBuffer; + CLR_RT_HeapBlock hbTimeout; + int64_t *timeoutTicks; + bool eventResult = true; + bool isLongRunningOperation = false; + uint32_t estimatedDurationMiliseconds; + + uint8_t *data; + uint32_t length = 0; + uint32_t count = 0; + uint32_t offset = 0; + sl_status_t reqStatus; + bool conn; + uint32_t bytesTransfered; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // perform parameter validation and setup TX operation + + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + offset = stack.Arg2().NumericByRef().s4; + count = stack.Arg3().NumericByRef().s4; + + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // check parameters + FAULT_ON_NULL_ARG(dataBuffer); + + if ((offset > length) || (count > length)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (offset + count > length) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // check for long runnign operation: over 10 blocks of 64 bytes (USB payload) + if (count > 64 * 10) + { + isLongRunningOperation = true; + + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + } + + if (isLongRunningOperation) + { + // setup timeout + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + } + + // check if device is connected (enabled) + sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); + + if (!conn) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (isLongRunningOperation) + { + // this is a long running operation... + if (stack.m_customState == 1) + { + // ... and hasn't started yet + // push onto the eval stack how many bytes are being pushed to the USB + stack.PushValueI4(count); + + // bump custom state + stack.m_customState = 2; + + // start read operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_read_bulk_async( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + UsbAsyncReadCompleted, + NULL); + + _ASSERTE(reqStatus == SL_STATUS_OK); + } + } + else + { + // this is NOT a long running operation + // perform read operation with sync API + reqStatus = + sl_usbd_vendor_read_bulk_sync(sl_usbd_vendor_winusb_number, (void *)data, count, 0, &bytesTransfered); + + _ASSERTE(reqStatus == SL_STATUS_OK); + + // check bytes transfered + if (bytesTransfered != count) + { + // something went wrong + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + + while (eventResult) + { + if (!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + // non-blocking wait allowing other threads to run while we wait for the USB operation to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); + } + + if (isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + stack.SetResult_I4(bytesTransfered); NANOCLR_NOCLEANUP(); } From b2666ba36c5935b0e851478c29f211b449ca5f43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 16:29:49 +0100 Subject: [PATCH 210/572] Add native implementation for UsbClient --- ...tive_System_Device_UsbClient_UsbClient.cpp | 24 ++++++++++--------- ...tive_System_Device_UsbClient_UsbStream.cpp | 19 +-------------- .../sys_dev_usbstream_native_target.h | 20 ++++++++++++++++ 3 files changed, 34 insertions(+), 29 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp index ecb7504c00..ff68957217 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp @@ -1,23 +1,25 @@ -//----------------------------------------------------------------------------- // -// ** WARNING! ** -// This file was generated automatically by a tool. -// Re-running the tool will overwrite this file. -// You should copy this file to a custom location -// before adding any customization in the copy to -// prevent loss of your changes when the tool is -// re-run. +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. // -//----------------------------------------------------------------------------- #include "sys_dev_usbstream_native.h" - +#include "sys_dev_usbstream_native_target.h" HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + bool conn; + + if(sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) + { + stack.SetResult_Boolean(conn); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp index a7528506f9..b039ec3ac0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp @@ -4,24 +4,7 @@ // #include - -////////////////////////////////////////////////////////////////////////////////////////////////////// -// Need to add these here, until Silabs fixes the include files. -// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // -// It's reportedly fixed and will be available in GCC 13. -////////////////////////////////////////////////////////////////////////////////////////////////////// -#define USBD_CFG_HS_EN 0 -#define USBD_CFG_EP_ISOC_EN 0 -////////////////////////////////////////////////////////////////////////////////////////////////////// - -#include - -extern char UsbClassVendorDescription[32 + 1]; -extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; -extern uint8_t sl_usbd_vendor_winusb_number; -extern "C" void sli_usbd_vendor_winusb_init(void); - -// -- // +#include "sys_dev_usbstream_native_target.h" static void UsbAsyncWriteCompleted( uint8_t class_nbr, diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h new file mode 100644 index 0000000000..e39323f203 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////////////////// +// Need to add these here, until Silabs fixes the include files. +// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // +// It's reportedly fixed and will be available in GCC 13. +////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USBD_CFG_HS_EN 0 +#define USBD_CFG_EP_ISOC_EN 0 +////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; +extern uint8_t sl_usbd_vendor_winusb_number; +extern "C" void sli_usbd_vendor_winusb_init(void); From edbd8a2912219813f80cfc3f525a68a187419b89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 7 Oct 2022 16:56:40 +0100 Subject: [PATCH 211/572] Fix comment on USB config define for SL_STK3701A --- .../SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h index f822724cd4..a604eb6826 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -190,6 +190,9 @@ extern char UsbClassVendorDescription[32 + 1]; // Number of configurations. #define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + // // From 3ee3024304c7d9ac2a34b409c19223103fe87518 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:11:52 +0100 Subject: [PATCH 212/572] SPI CS control can now be defined to be driver controlled - Required for Skyworks SPI library. --- .../SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index d9c6f71633..d4e1cf9805 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -218,7 +218,11 @@ void GetSpiConfig(const SPI_DEVICE_CONFIGURATION &config, NF_SpiDriver_Init_t &i break; } +#if defined(SPI_CS_CONTROL) + initSpiData.csControl = SPI_CS_CONTROL; +#else initSpiData.csControl = spidrvCsControlApplication; +#endif initSpiData.dummyTxValue = 0; // Sets the order of bytes transmission : MSB first or LSB first initSpiData.bitOrder = config.DataOrder16 == DataBitOrder_MSB ? spidrvBitOrderMsbFirst : spidrvBitOrderLsbFirst; From fe4cc8da1bec095d48413b1704fed3f28db4872a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:24:01 +0100 Subject: [PATCH 213/572] Work Skyworks SPI implementation - Update assembly declaration. - Rework code to have CS configured at build time. - Rework code to have CS controlled by SPI driver. - Update Skyworks SPI config on both targets. - Closes Skyworks-Timing-Software/MCU#9. --- .../com_sky_nf_dev_spi_native.cpp | 5 +-- .../com_sky_nf_dev_spi_native.h | 13 ++++--- .../target_com_sky_nf_dev_spi_config.cpp | 6 ++-- .../target_com_sky_nf_dev_spi_config.cpp | 8 ++--- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 30 ---------------- .../com_sky_nf_dev_spi_native_target.h | 34 +++++++++++++++++++ .../sys_dev_spi_native_target.h | 4 +++ 7 files changed, 52 insertions(+), 48 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index 0c74bd5f4b..708b7becf5 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -25,9 +25,6 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - NULL, - NULL, - NULL, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN, NULL, @@ -44,7 +41,7 @@ const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramewo "Com.SkyworksInc.NanoFramework.Devices.Spi", 0x6E9C1C37, method_lookup, - { 1, 0, 0, 0 } + { 1, 0, 0, 1 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index b82d3ad68c..531d1e71c4 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -35,12 +35,11 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration { - static const int FIELD___csLine = 1; - static const int FIELD___clockFrequency = 2; - static const int FIELD___databitLength = 3; - static const int FIELD___spiMode = 4; - static const int FIELD___dataFlow = 5; - static const int FIELD___busConfiguration = 6; + static const int FIELD___clockFrequency = 1; + static const int FIELD___databitLength = 2; + static const int FIELD___spiMode = 3; + static const int FIELD___dataFlow = 4; + static const int FIELD___busConfiguration = 5; //--// }; @@ -61,7 +60,7 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S struct Library_com_sky_nf_dev_spi_native_ThisAssembly { - static const int FIELD_STATIC__GitCommitDate = 1; + static const int FIELD_STATIC__GitCommitDate = 2; //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp index 5eeab9653f..ea3cba003b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp @@ -9,11 +9,11 @@ // SPI1 // ////////// -// pin configuration for SPI1 +// pin configuration for SPI1 (mapped to USART1 on this device) // SPI1_SCK: PD2, location 1 // SPI1_MOSI: PD0, location 1 // SPI1_MISO: PD1, location 1 -// CS: PD3 (not used in SPI configuration) +// SPI1_CS: PD3, location 1 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(1, 1, 1, 1) +INIT_SPI_CONFIG(1, 1, 1, 1, 1) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp index 6dbea05b69..51613d0c77 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_spi_config.cpp @@ -15,9 +15,9 @@ // SPI0_SCK: PE12, location 0, EXP Header Pin 8 // SPI0_MOSI: PE10, location 0, EXP Header Pin 4 // SPI0_MISO: PE11, location 0, EXP Header Pin 6 -// CS: PE13, EXP Header Pin 10 +// SPI0_CS: PE13, location 0, EXP Header Pin 10 -INIT_SPI_CONFIG(0, 0, 0, 0) +INIT_SPI_CONFIG(0, 0, 0, 0, 0) ////////// // SPI1 // @@ -29,6 +29,6 @@ INIT_SPI_CONFIG(0, 0, 0, 0) // SPI1_SCK: PC15, location 3 // SPI1_MOSI: PA14, location 6 // SPI1_MISO: (not used for LCD) -// CS: PC14 (not used in SPI configuration) +// SPI1_CS: PC14, location 3 -INIT_SPI_CONFIG(1, 3, 6, 0) +INIT_SPI_CONFIG(1, 3, 6, 0, 3) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index a11ba8a07b..20c27782a7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -118,17 +118,8 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // always bus master SpiConfigs[busIndex].BusMode = SpiBusMode_master; - // internally SPI bus ID is zero based, so better take care of that here SpiConfigs[busIndex].Spi_Bus = busIndex; - SpiConfigs[busIndex].DeviceChipSelect = config[SpiBaseConfiguration::FIELD___csLine].NumericByRef().s4; - - // sanity check chip select line - if (SpiConfigs[busIndex].DeviceChipSelect < -1) - { - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); - } - SpiConfigs[busIndex].Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiMode].NumericByRef().s4; SpiConfigs[busIndex].DataOrder16 = (DataBitOrder)config[SpiBaseConfiguration::FIELD___dataFlow].NumericByRef().s4; @@ -370,13 +361,6 @@ static HRESULT SPI_nWrite_nRead( } } - // if CS is to be controlled by the driver, set the GPIO - if (palSpi->ChipSelect >= 0) - { - // assert pin based on CS active level - CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); - } - if (sync) { // Sync operation @@ -441,13 +425,6 @@ static HRESULT SPI_nWrite_nRead( NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); } } - - // if CS is to be controlled by the driver, set the GPIO - if (palSpi->ChipSelect >= 0) - { - // de-assert pin based on CS active level - CPU_GPIO_TogglePinState(palSpi->ChipSelect); - } } else { @@ -455,13 +432,6 @@ static HRESULT SPI_nWrite_nRead( // perform SPI operation using driver's ASYNC API // Completed on calling SPI Callback - // if CS is to be controlled by the driver, set the GPIO - if (palSpi->ChipSelect >= 0) - { - // assert pin based on CS active level - CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); - } - // this is a Async operation // perform SPI operation using driver's ASYNC API if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h index 46eefca216..bb2190fc6b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_target.h @@ -14,4 +14,38 @@ // all PAL declarations are coming from CPU SPI +/////////////////////////////////////////////////// +// for Skyworks SPI CS is controlled by SPI driver +#define SPI_CS_CONTROL spidrvCsControlAuto +/////////////////////////////////////////////////// + +#if defined(_USART_ROUTELOC0_MASK) + +//////////////////////////////////////////////////////// +// INIT_SPI_CONFIG from System.Device.Spi redefined here +#if defined(INIT_SPI_CONFIG) +#undef INIT_SPI_CONFIG +#endif +//////////////////////////////////////////////////////// + +// the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral +// it gets called in the System_Device_SPi_SPiDevice::NativeInit function +// this is required because the SPI peripherals can use multiple GPIO configuration combinations +#define INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) \ + void InitSpiConfig##num(NF_SpiDriver_Init_t &initSpiData, bool isHalfDuplex) \ + { \ + initSpiData.port = USART##num; \ + initSpiData.portLocationTx = mosi_port_location; \ + initSpiData.portLocationClk = sck_port_location; \ + initSpiData.portLocationCs = cs_port_location; \ + if (!isHalfDuplex) \ + { \ + initSpiData.portLocationRx = miso_port_location; \ + } \ + } + +#else +#error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." +#endif + #endif // SYS_DEV_SPI_NATIVE_TARGET_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 74b69316c0..5c9e918a34 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -110,6 +110,8 @@ extern NF_PAL_SPI SPI5_PAL; #if defined(_USART_ROUTELOC0_MASK) +#if !defined(INIT_SPI_CONFIG) + // the following macro defines a function that configures the GPIO pins for an Gecko SPI peripheral // it gets called in the System_Device_SPi_SPiDevice::NativeInit function // this is required because the SPI peripherals can use multiple GPIO configuration combinations @@ -125,6 +127,8 @@ extern NF_PAL_SPI SPI5_PAL; } \ } +#endif // INIT_SPI_CONFIG + #else #error "This routing configuration is not supported. Need to have _USART_ROUTELOC0_MASK." #endif From 9f99979afbf655f472945f56e7ba0ac72bfeb99d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:26:45 +0100 Subject: [PATCH 214/572] Fix index for SPI bus in Gecko SPI driver --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 27 ++++++++++--------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index d4e1cf9805..43ae88220b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -144,39 +144,42 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) // get the PAL struct for the SPI bus switch (busIndex) { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// #if GECKO_USE_SPI0 == TRUE - case 0: + case 1: palSpi = &SPI0_PAL; break; #endif #if GECKO_USE_SPI1 == TRUE - case 1: + case 2: palSpi = &SPI1_PAL; break; #endif #if GECKO_USE_SPI2 == TRUE - case 2: + case 3: palSpi = &SPI2_PAL; break; #endif #if GECKO_USE_SPI3 == TRUE - case 3: + case 4: palSpi = &SPI3_PAL; break; #endif #if GECKO_USE_SPI4 == TRUE - case 4: + case 5: palSpi = &SPI4_PAL; break; #endif #if GECKO_USE_SPI5 == TRUE - case 5: + case 6: palSpi = &SPI5_PAL; break; #endif @@ -497,21 +500,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon ////////////////////////////////// #if GECKO_USE_SPI0 == TRUE - case 0: + case 1: palSpi = &SPI0_PAL; initSpiConfig = &InitSpiConfig0; break; #endif #if GECKO_USE_SPI1 == TRUE - case 1: + case 2: palSpi = &SPI1_PAL; initSpiConfig = &InitSpiConfig1; break; #endif #if GECKO_USE_SPI2 == TRUE - case 2: + case 3: palSpi = &SPI2_PAL; initSpiConfig = &InitSpiConfig2; @@ -519,21 +522,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #endif #if GECKO_USE_SPI3 == TRUE - case 3: + case 4: palSpi = &SPI3_PAL; initSpiConfig = &InitSpiConfig3; break; #endif #if GECKO_USE_SPI4 == TRUE - case 4: + case 5: palSpi = &SPI4_PAL; initSpiConfig = &InitSpiConfig4; break; #endif #if GECKO_USE_SPI5 == TRUE - case 5: + case 6: palSpi = &SPI5_PAL; initSpiConfig = &InitSpiConfig5; break; From 4f33b6724c029af55da4d2734a11acfdb1c2cdce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:44:39 +0100 Subject: [PATCH 215/572] Fix SPI index access --- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 29 +++++++++++-------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 20c27782a7..f6a8e38160 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -93,6 +93,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) int8_t busIndex; SPI_WRITE_READ_SETTINGS rws; NF_PAL_SPI *palSpi = NULL; + SPI_DEVICE_CONFIGURATION* spiDeviceConfig = NULL; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -101,10 +102,14 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // get bus index busIndex = (int8_t)stack.Arg1().NumericByRef().s4; + // SPI bux index is 1 based, but the array is 0 based + spiDeviceConfig = &SpiConfigs[busIndex - 1]; + if (stack.m_customState == 0) { // check if this SPI has been initialized palSpi = GetNfPalfromBusIndex(busIndex); + if (palSpi->Handle == NULL) { // compose SPI_DEVICE_CONFIGURATION @@ -114,25 +119,25 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) ->GetElement(busIndex); // CS is always active low - SpiConfigs[busIndex].ChipSelectActive = false; + spiDeviceConfig->ChipSelectActive = false; // always bus master - SpiConfigs[busIndex].BusMode = SpiBusMode_master; + spiDeviceConfig->BusMode = SpiBusMode_master; - SpiConfigs[busIndex].Spi_Bus = busIndex; + spiDeviceConfig->Spi_Bus = busIndex; - SpiConfigs[busIndex].Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiMode].NumericByRef().s4; - SpiConfigs[busIndex].DataOrder16 = + spiDeviceConfig->Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiMode].NumericByRef().s4; + spiDeviceConfig->DataOrder16 = (DataBitOrder)config[SpiBaseConfiguration::FIELD___dataFlow].NumericByRef().s4; - SpiConfigs[busIndex].Clock_RateHz = config[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRef().s4; - SpiConfigs[busIndex].ByteTime = (1.0 / SpiConfigs[busIndex].Clock_RateHz) * 1000 * 8; - SpiConfigs[busIndex].BusConfiguration = + spiDeviceConfig->Clock_RateHz = config[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRef().s4; + spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; + spiDeviceConfig->BusConfiguration = (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___busConfiguration].NumericByRef().s4; - SpiConfigs[busIndex].MD16bits = + spiDeviceConfig->MD16bits = config[SpiBaseConfiguration::FIELD___databitLength].NumericByRef().s4 == 16 ? true : false; // store this here too - palSpi->BufferIs16bits = SpiConfigs[busIndex].MD16bits; + palSpi->BufferIs16bits = spiDeviceConfig->MD16bits; - CPU_SPI_Initialize(busIndex, SpiConfigs[busIndex]); + CPU_SPI_Initialize(busIndex, *spiDeviceConfig); } // Buffers used either for the SpanBye either for the Byte array @@ -226,7 +231,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) readSize, fullDuplex, palSpi->BufferIs16bits, - SpiConfigs[busIndex].ByteTime, + spiDeviceConfig->ByteTime, (uint32_t &)estimatedDurationMiliseconds); if (isLongRunningOperation) From 1195396db8fc347cf1b56cc89c304bafe4be15d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:56:00 +0100 Subject: [PATCH 216/572] Improve readme for SKY_EEVB_PROTO1 with I2C and SPI indexes --- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md index 30269171db..30d3335c40 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md @@ -14,17 +14,17 @@ ADC has enabled the following channels: ## I2C -I2C0 +I2C0 (this is referenced as I2C1 in C#) SCL is: PA1 SDA is: PA0 -I2C1 +I2C1 (this is referenced as I2C2 in C#) SCL is: PC5 SDA is: PC4 ## SPI -SPI1 +US1 (this is referenced as SPI2 in C#) SCK: PD2 MOSI: PD0 MISO: PD1 From f6390f1ed6dab58c3b4e7d259789ebb0b53a9625 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:11:52 +0100 Subject: [PATCH 217/572] SPI CS control can now be defined to be driver controlled - Required for Skyworks SPI library. --- .../SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 1e848afa5e..b593524a89 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -218,7 +218,11 @@ void GetSpiConfig(const SPI_DEVICE_CONFIGURATION &config, NF_SpiDriver_Init_t &i break; } +#if defined(SPI_CS_CONTROL) + initSpiData.csControl = SPI_CS_CONTROL; +#else initSpiData.csControl = spidrvCsControlApplication; +#endif initSpiData.dummyTxValue = 0; // Sets the order of bytes transmission : MSB first or LSB first initSpiData.bitOrder = config.DataOrder16 == DataBitOrder_MSB ? spidrvBitOrderMsbFirst : spidrvBitOrderLsbFirst; From fd2d5de3e029ff1a4b4f586277b9844f151e5cef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 16:26:45 +0100 Subject: [PATCH 218/572] Fix index for SPI bus in Gecko SPI driver --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 27 ++++++++++--------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index b593524a89..575b048925 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -144,39 +144,42 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) // get the PAL struct for the SPI bus switch (busIndex) { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// #if GECKO_USE_SPI0 == TRUE - case 0: + case 1: palSpi = &SPI0_PAL; break; #endif #if GECKO_USE_SPI1 == TRUE - case 1: + case 2: palSpi = &SPI1_PAL; break; #endif #if GECKO_USE_SPI2 == TRUE - case 2: + case 3: palSpi = &SPI2_PAL; break; #endif #if GECKO_USE_SPI3 == TRUE - case 3: + case 4: palSpi = &SPI3_PAL; break; #endif #if GECKO_USE_SPI4 == TRUE - case 4: + case 5: palSpi = &SPI4_PAL; break; #endif #if GECKO_USE_SPI5 == TRUE - case 5: + case 6: palSpi = &SPI5_PAL; break; #endif @@ -497,21 +500,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon ////////////////////////////////// #if GECKO_USE_SPI0 == TRUE - case 0: + case 1: palSpi = &SPI0_PAL; initSpiConfig = &InitSpiConfig0; break; #endif #if GECKO_USE_SPI1 == TRUE - case 1: + case 2: palSpi = &SPI1_PAL; initSpiConfig = &InitSpiConfig1; break; #endif #if GECKO_USE_SPI2 == TRUE - case 2: + case 3: palSpi = &SPI2_PAL; initSpiConfig = &InitSpiConfig2; @@ -519,21 +522,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #endif #if GECKO_USE_SPI3 == TRUE - case 3: + case 4: palSpi = &SPI3_PAL; initSpiConfig = &InitSpiConfig3; break; #endif #if GECKO_USE_SPI4 == TRUE - case 4: + case 5: palSpi = &SPI4_PAL; initSpiConfig = &InitSpiConfig4; break; #endif #if GECKO_USE_SPI5 == TRUE - case 5: + case 6: palSpi = &SPI5_PAL; initSpiConfig = &InitSpiConfig5; break; From e063a96a396ed32d8844ebb9b950996f68a5234d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 10 Oct 2022 17:15:36 +0100 Subject: [PATCH 219/572] Improve readme with pin map details for SL_STK3701A target --- .../SiliconLabs/SL_STK3701A/README.md | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index 2ec34ed193..87239e5f29 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -25,3 +25,30 @@ Vref is 2.5V for all channels, except for VCC which is 5V. PWM has enabled the following GPIOs: 0 - PC1 (pin 15 on the expansion header) 1 - PI1 (through hole connector at bottom side) + +## I2C + +I2C2 (this is referenced as I2C3 in C#) +Connected to the following devices on the GG11 board: +Si7021: Relative Humidity and Temperature Sensor +Si7210: Hall-Effect Sensor + +I2C2_SCL is: PI5 +I2C2_SDA is: PI4 + +## SPI + +SPI0 (this is referenced as SPI1 in C#) +Available in EXP header + +SPI0_SCK: PE12, EXP Header Pin 8 +SPI0_MOSI: PE10, EXP Header Pin 4 +SPI0_MISO: PE11, EXP Header Pin 6 +SPI0_CS: PE13, EXP Header Pin 10 + +SPI0 (this is referenced as SPI2 in C#) +Connected to board LCD module + +SPI1_SCK: PC15 +SPI1_MOSI: PA14 +SPI1_CS: PC14 From 1a39adee220aa4f0a4b0e433d047bed8257ddf3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 11 Oct 2022 17:56:05 +0100 Subject: [PATCH 220/572] Update declaration and implementation of UsbClient assembly - Following nanoframework/System.Device.UsbClient#6. --- .../Modules/FindSystem.Device.UsbStream.cmake | 4 ++-- .../sys_dev_usbstream_native.cpp | 20 +++++++++++-------- .../sys_dev_usbstream_native.h | 14 +++++++------ ...ive_System_Device_Usb_UsbClient_stubs.cpp} | 2 +- ...ive_System_Device_Usb_UsbStream_stubs.cpp} | 10 +++++----- ...am_native_System_Device_Usb_UsbClient.cpp} | 2 +- ...am_native_System_Device_Usb_UsbStream.cpp} | 10 +++++----- 7 files changed, 34 insertions(+), 28 deletions(-) rename src/System.Device.UsbStream/{sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp => sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp} (67%) rename src/System.Device.UsbStream/{sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp => sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp} (58%) rename targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/{sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp => sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp} (78%) rename targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/{sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp => sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp} (94%) diff --git a/CMake/Modules/FindSystem.Device.UsbStream.cmake b/CMake/Modules/FindSystem.Device.UsbStream.cmake index c82b1102b1..015e70c968 100644 --- a/CMake/Modules/FindSystem.Device.UsbStream.cmake +++ b/CMake/Modules/FindSystem.Device.UsbStream.cmake @@ -21,8 +21,8 @@ set(System.Device.UsbStream_SRCS sys_dev_usbstream_native.cpp - sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp - sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp + sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp + sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp ) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 25a8acabf4..16939392e3 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -11,7 +11,7 @@ static const CLR_RT_MethodHandler method_lookup[] = { NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN, NULL, NULL, NULL, @@ -40,26 +40,30 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID, NULL, NULL, NULL, NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID, NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID, - Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING, - Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, - Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, + NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x6E619AF7, + 0x0024FE8B, method_lookup, { 1, 0, 0, 0 } }; - // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 23a6133507..72360955de 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -21,14 +21,14 @@ // UsbEventType_DeviceDisconnected = 2, // } UsbEventType; -struct Library_sys_dev_usbstream_native_System_Device_UsbClient_DeviceConnectionEventArgs +struct Library_sys_dev_usbstream_native_System_Device_Usb_DeviceConnectionEventArgs { static const int FIELD___isConnected = 1; //--// }; -struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient +struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient { static const int FIELD_STATIC__UsbDeviceConnectionChanged = 0; @@ -37,7 +37,7 @@ struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient //--// }; -struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbDeviceEvent +struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbDeviceEvent { static const int FIELD___eventType = 3; static const int FIELD___eventData = 4; @@ -46,10 +46,12 @@ struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbDeviceEvent //--// }; -struct Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream +struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream { - static const int FIELD___streamIndex = 2; - static const int FIELD___disposed = 3; + static const int FIELD___streamIndex = 1; + static const int FIELD___disposed = 2; + static const int FIELD___writeTimeout = 3; + static const int FIELD___readTimeout = 4; NANOCLR_NATIVE_DECLARE(Flush___VOID); NANOCLR_NATIVE_DECLARE(NativeClose___VOID); diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp similarity index 67% rename from src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp rename to src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp index 70aa7f8645..3b9d3c0133 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp @@ -6,7 +6,7 @@ #include "sys_dev_usbstream_native.h" -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp similarity index 58% rename from src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp rename to src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp index beaba35c7b..10c3c1197e 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp @@ -5,7 +5,7 @@ #include -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -14,7 +14,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flus NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -23,7 +23,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -33,7 +33,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -43,7 +43,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp similarity index 78% rename from targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp rename to targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp index ff68957217..d7d610ee55 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbClient.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp @@ -6,7 +6,7 @@ #include "sys_dev_usbstream_native.h" #include "sys_dev_usbstream_native_target.h" -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp similarity index 94% rename from targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp rename to targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index b039ec3ac0..6a60adc8d6 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_UsbClient_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -44,7 +44,7 @@ static void UsbAsyncReadCompleted( // -- // -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -53,7 +53,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Flus NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -62,7 +62,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeOpen___I4__STRING__STRING( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -96,7 +96,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -245,7 +245,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::Nati NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_UsbClient_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); From a1bf2ba05d7cc8f5dad1136a6f62a8d2b6b971b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 11 Oct 2022 17:57:08 +0100 Subject: [PATCH 221/572] Simplification of condition for disposed object --- .../sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 6a60adc8d6..f0e4d95f1e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -120,7 +120,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit CLR_RT_HeapBlock *pThis = stack.This(); FAULT_ON_NULL(pThis); - if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + if ((bool)pThis[FIELD___disposed].NumericByRef().u1) { NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); } @@ -269,7 +269,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead CLR_RT_HeapBlock *pThis = stack.This(); FAULT_ON_NULL(pThis); - if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + if ((bool)pThis[FIELD___disposed].NumericByRef().u1) { NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); } From f90873c7f84fdbfd42cd08e255a610b69010fc4a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 11 Oct 2022 18:01:23 +0100 Subject: [PATCH 222/572] Rework implementation of USB read and write operations - Always using Gecko async API now so thread execution is not blocked. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 195 +++++------------- 1 file changed, 56 insertions(+), 139 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index f0e4d95f1e..6139130642 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -105,8 +105,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit CLR_RT_HeapBlock hbTimeout; int64_t *timeoutTicks; bool eventResult = true; - bool isLongRunningOperation = false; - uint32_t estimatedDurationMiliseconds; uint8_t *data; uint32_t length = 0; @@ -148,25 +146,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // get a the pointer to the array by using the offset - data = dataBuffer->GetElement(offset); - - // check for long runnign operation: over 10 blocks of 64 bytes (USB payload) - if (count > 64 * 10) - { - isLongRunningOperation = true; - - // rough estimation!! - estimatedDurationMiliseconds = count / 64; - } - - if (isLongRunningOperation) - { - // setup timeout - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); - NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); - } - // check if device is connected (enabled) sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); @@ -176,71 +155,48 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); } - if (isLongRunningOperation) - { - // this is a long running operation... - if (stack.m_customState == 1) - { - // ... and hasn't started yet - // push onto the eval stack how many bytes are being pushed to the USB - stack.PushValueI4(count); - - // bump custom state - stack.m_customState = 2; - - // start write operation with async API - // requesting handling of "End-of-transfer" - reqStatus = sl_usbd_vendor_write_bulk_async( - sl_usbd_vendor_winusb_number, - (void *)data, - count, - UsbAsyncWriteCompleted, - NULL, - true); - - _ASSERTE(reqStatus == SL_STATUS_OK); - } - } - else + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // setup timeout + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + + // this is a long running operation... + if (stack.m_customState == 1) { - // this is NOT a long running operation - // perform write operation with sync API - reqStatus = sl_usbd_vendor_write_bulk_sync( + // ... and hasn't started yet + // push onto the eval stack how many bytes are being pushed to the USB + stack.PushValueI4(count); + + // bump custom state + stack.m_customState = 2; + + // start write operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_write_bulk_async( sl_usbd_vendor_winusb_number, (void *)data, count, - 0, - true, - &bytesTransfered); + UsbAsyncWriteCompleted, + NULL, + true); _ASSERTE(reqStatus == SL_STATUS_OK); - - // check bytes transfered - if (bytesTransfered != count) - { - // something went wrong - NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); - } } while (eventResult) { - if (!isLongRunningOperation) - { - // this is not a long running operation so nothing to do here - break; - } - // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } - if (isLongRunningOperation) - { - // pop timeout heap block from stack - stack.PopValue(); - } + // pop "count" heap block from stack + stack.PopValue(); + + // pop timeout heap block from stack + stack.PopValue(); NANOCLR_NOCLEANUP(); } @@ -254,8 +210,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead CLR_RT_HeapBlock hbTimeout; int64_t *timeoutTicks; bool eventResult = true; - bool isLongRunningOperation = false; - uint32_t estimatedDurationMiliseconds; uint8_t *data; uint32_t length = 0; @@ -297,25 +251,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // get a the pointer to the array by using the offset - data = dataBuffer->GetElement(offset); - - // check for long runnign operation: over 10 blocks of 64 bytes (USB payload) - if (count > 64 * 10) - { - isLongRunningOperation = true; - - // rough estimation!! - estimatedDurationMiliseconds = count / 64; - } - - if (isLongRunningOperation) - { - // setup timeout - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); - NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); - } - // check if device is connected (enabled) sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); @@ -325,65 +260,47 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); } - if (isLongRunningOperation) - { - // this is a long running operation... - if (stack.m_customState == 1) - { - // ... and hasn't started yet - // push onto the eval stack how many bytes are being pushed to the USB - stack.PushValueI4(count); - - // bump custom state - stack.m_customState = 2; - - // start read operation with async API - // requesting handling of "End-of-transfer" - reqStatus = sl_usbd_vendor_read_bulk_async( - sl_usbd_vendor_winusb_number, - (void *)data, - count, - UsbAsyncReadCompleted, - NULL); - - _ASSERTE(reqStatus == SL_STATUS_OK); - } - } - else + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // setup timeout + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + + // this is a long running operation... + if (stack.m_customState == 1) { - // this is NOT a long running operation - // perform read operation with sync API - reqStatus = - sl_usbd_vendor_read_bulk_sync(sl_usbd_vendor_winusb_number, (void *)data, count, 0, &bytesTransfered); + // ... and hasn't started yet + // push onto the eval stack how many bytes are being pushed to the USB + stack.PushValueI4(count); - _ASSERTE(reqStatus == SL_STATUS_OK); + // bump custom state + stack.m_customState = 2; + + // start read operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_read_bulk_async( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + UsbAsyncReadCompleted, + NULL); - // check bytes transfered - if (bytesTransfered != count) - { - // something went wrong - NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); - } + _ASSERTE(reqStatus == SL_STATUS_OK); } while (eventResult) { - if (!isLongRunningOperation) - { - // this is not a long running operation so nothing to do here - break; - } - // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); } - if (isLongRunningOperation) - { - // pop timeout heap block from stack - stack.PopValue(); - } + // pop "count" heap block from stack + stack.PopValue(); + + // pop timeout heap block from stack + stack.PopValue(); stack.SetResult_I4(bytesTransfered); From d010a281598a451b694148a81a484dd341dac9a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 11 Oct 2022 22:38:09 +0100 Subject: [PATCH 223/572] More work to improve UsbStream --- ..._usbstream_native_System_Device_Usb_UsbStream.cpp | 9 ++++++++- .../sys_dev_usbstream_native_target.h | 12 ++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 6139130642..91e6e8084a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -112,7 +112,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit uint32_t offset = 0; sl_status_t reqStatus; bool conn; - uint32_t bytesTransfered; + uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -158,6 +158,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); @@ -218,6 +221,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead sl_status_t reqStatus; bool conn; uint32_t bytesTransfered; + uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -263,6 +267,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index e39323f203..b90868a5e0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -14,7 +14,19 @@ #include +// need these declared here as they are scattered throughout Gecko SDK and config files extern char UsbClassVendorDescription[32 + 1]; extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; extern uint8_t sl_usbd_vendor_winusb_number; extern "C" void sli_usbd_vendor_winusb_init(void); + +// struct representing the UART +typedef struct +{ + HAL_RingBuffer RxRingBuffer; + uint8_t *RxBuffer; + uint16_t RxBytesToRead; + + uint32_t ReceivedBytesThreshold; + +} NF_PAL_USB; From 164e73cd7f029ef11cf317bbc20ef95901c60d16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 12:23:00 +0100 Subject: [PATCH 224/572] Update declaration of UsbStream assembly - Following nanoframework/System.Device.UsbClient#7. --- src/System.Device.UsbStream/sys_dev_usbstream_native.cpp | 4 ++-- src/System.Device.UsbStream/sys_dev_usbstream_native.h | 2 +- ...dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp | 2 +- .../sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 16939392e3..2c71e3899b 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -11,8 +11,8 @@ static const CLR_RT_MethodHandler method_lookup[] = { NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN, NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN, NULL, NULL, NULL, @@ -61,7 +61,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x0024FE8B, + 0x74531012, method_lookup, { 1, 0, 0, 0 } }; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 72360955de..ef710e5250 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -32,7 +32,7 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient { static const int FIELD_STATIC__UsbDeviceConnectionChanged = 0; - NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsConnected___STATIC__BOOLEAN); //--// }; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp index 3b9d3c0133..94e2cd5b43 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp @@ -6,7 +6,7 @@ #include "sys_dev_usbstream_native.h" -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp index d7d610ee55..57f10f13a4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp @@ -6,7 +6,7 @@ #include "sys_dev_usbstream_native.h" #include "sys_dev_usbstream_native_target.h" -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); From 2a2a77019f0e0c57d69ae6a82d5de6ed5855f7f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 12:23:45 +0100 Subject: [PATCH 225/572] Fix adding WinUSB device interface class property --- .../_common/autogen/sl_usbd_class_vendor_instances.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 1943c27e02..ce1d10cdbe 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -150,7 +150,7 @@ void sli_usbd_vendor_winusb_init() // add device class GUID to WinUSB properties sl_usbd_vendor_add_microsoft_ext_property( - config_number, + class_number, SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, DEVICEINTERFACE_GUID_PROP_NAME_LEN, From b9c9a7f2ae1475926c9a81272b1bd29145ce10ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:42:46 +0100 Subject: [PATCH 226/572] Revert "Fix adding WinUSB device interface class property" This reverts commit 2a2a77019f0e0c57d69ae6a82d5de6ed5855f7f5. --- .../_common/autogen/sl_usbd_class_vendor_instances.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index ce1d10cdbe..1943c27e02 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -150,7 +150,7 @@ void sli_usbd_vendor_winusb_init() // add device class GUID to WinUSB properties sl_usbd_vendor_add_microsoft_ext_property( - class_number, + config_number, SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, DEVICEINTERFACE_GUID_PROP_NAME_LEN, From 149289ae99f238d77dfae113b1a68cf9e22db0ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:44:52 +0100 Subject: [PATCH 227/572] Remove call to check for device connected - This is already performed in the Gecko API so no need to do it here. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 91e6e8084a..d7cb032458 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -111,7 +111,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - bool conn; uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL @@ -146,15 +145,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // check if device is connected (enabled) - sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); - - if (!conn) - { - // device is not connected, return exception - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); - } - // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); @@ -219,7 +209,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - bool conn; uint32_t bytesTransfered; uint32_t estimatedDurationMiliseconds; @@ -255,15 +244,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // check if device is connected (enabled) - sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); - - if (!conn) - { - // device is not connected, return exception - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); - } - // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); From 1a37d1ac51ba001b60592c662d1fd3927f92c5b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:47:40 +0100 Subject: [PATCH 228/572] Rework sli_usbd_vendor_winusb_init - Function now returns SL status. - Add check for successful call to add configuration. - Add global flag so WinUSB init is not performed repeatedly on CLR reboot. --- .../autogen/sl_usbd_class_vendor_instances.c | 22 +++++++++++++++++-- .../autogen/sl_usbd_class_vendor_instances.h | 2 +- ...eam_native_System_Device_Usb_UsbStream.cpp | 5 ++++- .../sys_dev_usbstream_native_target.h | 2 +- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 1943c27e02..1ae094c2a6 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -39,6 +39,9 @@ extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t dat char UsbClassVendorDescription[32 + 1]; char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; +// flag for USB WinUSB intialized +static bool usbdVendorWinusbInited = false; + typedef enum __nfpack UsbEventType { UsbEventType_Invalid = 0, @@ -104,7 +107,7 @@ void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req // Global functions. /* initialize winusb instance */ -void sli_usbd_vendor_winusb_init() +sl_status_t sli_usbd_vendor_winusb_init() { bool intr_en = true; uint16_t interval = 0; @@ -115,6 +118,12 @@ void sli_usbd_vendor_winusb_init() char *configs = NULL; char *token = NULL; + // check if already initialized + if (usbdVendorWinusbInited) + { + return SL_STATUS_OK; + } + /* configs to attach the class instance to */ configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; @@ -141,7 +150,11 @@ void sli_usbd_vendor_winusb_init() if (!strcmp(token, "config0") || !strcmp(token, "all")) { config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); + if(sl_usbd_vendor_add_to_configuration(class_number, config_number) != SL_STATUS_OK) + { + // error adding class to configuration + return SL_STATUS_FAIL; + } } /* next token */ @@ -156,6 +169,11 @@ void sli_usbd_vendor_winusb_init() DEVICEINTERFACE_GUID_PROP_NAME_LEN, (const uint8_t *)UsbClassVendorDeviceInterfaceGuid, sizeof(UsbClassVendorDeviceInterfaceGuid)); + + // all good here, update flag + usbdVendorWinusbInited = true; + + return SL_STATUS_OK; } void sl_usbd_vendor_winusb_on_enable_event(void) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h index 23e4b3a410..72776bcc84 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -31,6 +31,6 @@ __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req /* init functions for all vendor instances */ -void sli_usbd_vendor_winusb_init(void); +sl_status_t sli_usbd_vendor_winusb_init(void); #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d7cb032458..2e1057d7bd 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -89,7 +89,10 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen // store device description hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); - sli_usbd_vendor_winusb_init(); + if (sli_usbd_vendor_winusb_init() != SL_STATUS_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } stack.SetResult_I4(sl_usbd_vendor_winusb_number); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index b90868a5e0..148c378f94 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -18,7 +18,7 @@ extern char UsbClassVendorDescription[32 + 1]; extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; extern uint8_t sl_usbd_vendor_winusb_number; -extern "C" void sli_usbd_vendor_winusb_init(void); +extern "C" sl_status_t sli_usbd_vendor_winusb_init(void); // struct representing the UART typedef struct From f6f49f5166e24a7538441f04d27c6248343309d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:53:15 +0100 Subject: [PATCH 229/572] Rework async execution of Write and Read operations - Replace assert with check for various possible outcomes and throw exceptions accordingly. - Add clean-up section to pop values from stack and add return value for read - Minor fixes in code style. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 64 ++++++++++++++----- 1 file changed, 47 insertions(+), 17 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 2e1057d7bd..d7098fa9ea 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -72,7 +72,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen // get device class GUID deviceClassGuid = stack.Arg1().RecoverString(); - ; // clear destination memset(UsbClassVendorDeviceInterfaceGuid, 0, sizeof(UsbClassVendorDeviceInterfaceGuid)); @@ -152,7 +151,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit data = dataBuffer->GetElement(offset); // rough estimation!! - estimatedDurationMiliseconds = count / 64; + estimatedDurationMiliseconds = count / 10; // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); @@ -178,7 +177,16 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NULL, true); - _ASSERTE(reqStatus == SL_STATUS_OK); + if (reqStatus == SL_STATUS_INVALID_STATE) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + else if (reqStatus == SL_STATUS_NOT_READY) + { + // transfer already in progress, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } } while (eventResult) @@ -188,13 +196,18 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } - // pop "count" heap block from stack - stack.PopValue(); + NANOCLR_CLEANUP(); - // pop timeout heap block from stack - stack.PopValue(); + if (stack.m_customState > 1) + { + // pop "count" heap block from stack + stack.PopValue(); - NANOCLR_NOCLEANUP(); + // pop timeout heap block from stack + stack.PopValue(); + } + + NANOCLR_CLEANUP_END(); } HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( @@ -212,7 +225,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t bytesTransfered; + uint32_t bytesTransfered = 0; uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL @@ -251,7 +264,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead data = dataBuffer->GetElement(offset); // rough estimation!! - estimatedDurationMiliseconds = count / 64; + estimatedDurationMiliseconds = count / 10; // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); @@ -276,7 +289,16 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead UsbAsyncReadCompleted, NULL); - _ASSERTE(reqStatus == SL_STATUS_OK); + if (reqStatus == SL_STATUS_INVALID_STATE) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + else if (reqStatus == SL_STATUS_NOT_READY) + { + // transfer already in progress, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } } while (eventResult) @@ -286,13 +308,21 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); } - // pop "count" heap block from stack - stack.PopValue(); + NANOCLR_CLEANUP(); + + if (stack.m_customState > 1) + { + // pop "count" heap block from stack + stack.PopValue(); - // pop timeout heap block from stack - stack.PopValue(); + // pop timeout heap block from stack + stack.PopValue(); + } - stack.SetResult_I4(bytesTransfered); + if (SUCCEEDED(hr)) + { + stack.SetResult_I4(bytesTransfered); + } - NANOCLR_NOCLEANUP(); + NANOCLR_CLEANUP_END(); } From 58a5c3538d79285997338b80e084c05b711d2675 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 18:49:31 +0100 Subject: [PATCH 230/572] Improve timeout setting for W/R operations - Now coming from timeout fields. - Add implementation to event handlers. - Improve post processing of events. - Add processing for timeout event. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 62 +++++++++++++------ .../sys_dev_usbstream_native_target.h | 6 +- 2 files changed, 47 insertions(+), 21 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d7098fa9ea..63e8a37d1b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -6,6 +6,8 @@ #include #include "sys_dev_usbstream_native_target.h" +NF_PAL_USB UsbStream_PAL; + static void UsbAsyncWriteCompleted( uint8_t class_nbr, void *p_buf, @@ -17,10 +19,13 @@ static void UsbAsyncWriteCompleted( (void)class_nbr; (void)p_buf; (void)buf_len; - (void)xfer_len; - (void)p_callback_arg; (void)status; + NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; + + // store TX count + usbPal->TxBytesSent = xfer_len; + Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); } @@ -35,10 +40,13 @@ static void UsbAsyncReadCompleted( (void)class_nbr; (void)p_buf; (void)buf_len; - (void)xfer_len; - (void)p_callback_arg; (void)status; + NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; + + // store RX count + usbPal->RxBytesReceived = xfer_len; + Events_Set(SYSTEM_EVENT_FLAG_USB_IN); } @@ -70,6 +78,12 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen const char *deviceDescription; const char *deviceClassGuid; + // int32_t bufferSize; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + // get device class GUID deviceClassGuid = stack.Arg1().RecoverString(); @@ -113,7 +127,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -150,11 +163,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); - // rough estimation!! - estimatedDurationMiliseconds = count / 10; - - // setup timeout - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + // setup timeout from managed property + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); // this is a long running operation... @@ -174,7 +184,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit (void *)data, count, UsbAsyncWriteCompleted, - NULL, + &UsbStream_PAL, true); if (reqStatus == SL_STATUS_INVALID_STATE) @@ -196,6 +206,13 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } + // timeout expired + if (!eventResult) + { + // timeout has expired, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + NANOCLR_CLEANUP(); if (stack.m_customState > 1) @@ -225,8 +242,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t bytesTransfered = 0; - uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -263,11 +278,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); - // rough estimation!! - estimatedDurationMiliseconds = count / 10; - - // setup timeout - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + // setup timeout from managed property + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___readTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); // this is a long running operation... @@ -280,6 +292,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // bump custom state stack.m_customState = 2; + // clear RX counter + UsbStream_PAL.RxBytesReceived = 0; + // start read operation with async API // requesting handling of "End-of-transfer" reqStatus = sl_usbd_vendor_read_bulk_async( @@ -287,7 +302,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead (void *)data, count, UsbAsyncReadCompleted, - NULL); + &UsbStream_PAL); if (reqStatus == SL_STATUS_INVALID_STATE) { @@ -308,6 +323,13 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); } + // timeout expired + if (!eventResult) + { + // timeout has expired, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + NANOCLR_CLEANUP(); if (stack.m_customState > 1) @@ -321,7 +343,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead if (SUCCEEDED(hr)) { - stack.SetResult_I4(bytesTransfered); + stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); } NANOCLR_CLEANUP_END(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index 148c378f94..ef5a05d683 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -26,7 +26,11 @@ typedef struct HAL_RingBuffer RxRingBuffer; uint8_t *RxBuffer; uint16_t RxBytesToRead; - + uint16_t RxBytesReceived; uint32_t ReceivedBytesThreshold; + uint16_t TxBytesSent; + } NF_PAL_USB; + +extern NF_PAL_USB UsbStream_PAL; From de666c209762995ab3e74b96db09fc86a89ab026 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 15:23:41 +0100 Subject: [PATCH 231/572] Fix I2C bus parameter --- ..._native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp index 535a8801ec..e89a3a31c3 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -663,7 +663,7 @@ HRESULT Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_ FAULT_ON_NULL(pThis); // get bus index - busIndex = (uint8_t)stack.Arg2().NumericByRef().s4; + busIndex = (uint8_t)stack.Arg1().NumericByRef().s4; // get a pointer to the managed I2C connectionSettings object instance busSpeedCollection = (CLR_RT_HeapBlock_Array *)pThis[FIELD_STATIC___busSpeed].DereferenceArray(); From 6894118a4bccd21b00d99badff6583b2db577c77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 15:25:02 +0100 Subject: [PATCH 232/572] Move Skyworks I2C library to src folder - No reason for being inside the PAL folder. --- .../FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake | 4 ++-- .../com_sky_nf_dev_i2c_native.cpp | 0 .../com_sky_nf_dev_i2c_native.h | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename src/{PAL => }/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp (100%) rename src/{PAL => }/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h (100%) diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake index 938c7800db..b3999bac6c 100644 --- a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake @@ -13,7 +13,7 @@ list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURC list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/HAL/Include) list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Include) list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) -list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c) +list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.I2c) # source files set(Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS @@ -34,7 +34,7 @@ foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS}) PATHS ${BASE_PATH_FOR_THIS_MODULE} ${TARGET_BASE_LOCATION} - ${PROJECT_SOURCE_DIR}/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c + ${PROJECT_SOURCE_DIR}/src/Com.SkyworksInc.NanoFramework.Devices.I2c CMAKE_FIND_ROOT_PATH_BOTH ) diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp similarity index 100% rename from src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp rename to src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp diff --git a/src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h similarity index 100% rename from src/PAL/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h rename to src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h From 574e0f01d80e0c2fc544b12465312739d6bb94cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 16:26:22 +0100 Subject: [PATCH 233/572] Various fixes in SPI operations --- ...yworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index f6a8e38160..0cc11548c8 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -102,7 +102,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // get bus index busIndex = (int8_t)stack.Arg1().NumericByRef().s4; - // SPI bux index is 1 based, but the array is 0 based + // SPI bus index is 1 based, but the array is 0 based spiDeviceConfig = &SpiConfigs[busIndex - 1]; if (stack.m_customState == 0) @@ -114,12 +114,15 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) { // compose SPI_DEVICE_CONFIGURATION // get ref to SpiBaseConfiguration from static _busConnectionSettings array, access it by index + // which is 0 based config = (CLR_RT_HeapBlock *)pThis[Devices_Spi_SpiBus::FIELD_STATIC___busConnectionSettings] .DereferenceArray() - ->GetElement(busIndex); + ->GetElement(busIndex - 1); // CS is always active low spiDeviceConfig->ChipSelectActive = false; + // CS is controled by the Gecko SDK driver + spiDeviceConfig->DeviceChipSelect = -1; // always bus master spiDeviceConfig->BusMode = SpiBusMode_master; @@ -145,7 +148,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) if (isSpanByte) { // dereference the write and read SpanByte from the arguments - writeSpanByte = stack.Arg1().Dereference(); + writeSpanByte = stack.Arg2().Dereference(); if (writeSpanByte != NULL) { @@ -170,7 +173,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) writeSize = 0; } - readSpanByte = stack.Arg2().Dereference(); + readSpanByte = stack.Arg3().Dereference(); if (readSpanByte != NULL) { @@ -196,7 +199,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) } else { - writeBuffer = stack.Arg1().DereferenceArray(); + writeBuffer = stack.Arg2().DereferenceArray(); if (writeBuffer != NULL) { @@ -207,7 +210,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) writeSize = writeBuffer->m_numOfElements; } - readBuffer = stack.Arg2().DereferenceArray(); + readBuffer = stack.Arg3().DereferenceArray(); if (readBuffer != NULL) { From e21e00994253a30411576390bac698e0ac51e96a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 17:30:34 +0100 Subject: [PATCH 234/572] Fix formating --- .../com_sky_nf_dev_spi_native.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 531d1e71c4..90842a4a8b 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -8,7 +8,6 @@ #include #include - // defined src\System.Device.Spi\sys_dev_spi_native.h // typedef enum __nfpack DataFlow // { From 79859d67192497d83fcf2cf05dbb7cc72337eb39 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 17:31:11 +0100 Subject: [PATCH 235/572] Fix access to static field --- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 0cc11548c8..27386c0ae3 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -72,7 +72,10 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) { NANOCLR_HEADER(); + CLR_IDX assemblyIdx; + CLR_RT_Assembly *thisAssembly = NULL; CLR_RT_HeapBlock *config = NULL; + CLR_RT_HeapBlock_Array *busConnectionSettings; CLR_RT_HeapBlock_Array *writeBuffer; CLR_RT_HeapBlock_Array *readBuffer; CLR_RT_HeapBlock *writeSpanByte; @@ -93,7 +96,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) int8_t busIndex; SPI_WRITE_READ_SETTINGS rws; NF_PAL_SPI *palSpi = NULL; - SPI_DEVICE_CONFIGURATION* spiDeviceConfig = NULL; + SPI_DEVICE_CONFIGURATION *spiDeviceConfig = NULL; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -113,11 +116,15 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) if (palSpi->Handle == NULL) { // compose SPI_DEVICE_CONFIGURATION - // get ref to SpiBaseConfiguration from static _busConnectionSettings array, access it by index - // which is 0 based - config = (CLR_RT_HeapBlock *)pThis[Devices_Spi_SpiBus::FIELD_STATIC___busConnectionSettings] - .DereferenceArray() - ->GetElement(busIndex - 1); + // get ref to SpiBaseConfiguration from static _busConnectionSettings array... + // need to access it through the assembly + assemblyIdx = pThis->ObjectCls().Assembly(); + thisAssembly = g_CLR_RT_TypeSystem.m_assemblies[assemblyIdx - 1]; + busConnectionSettings = + thisAssembly->GetStaticField(Devices_Spi_SpiBus::FIELD_STATIC___busConnectionSettings) + ->DereferenceArray(); + // ...access it by index, which is 0 based + config = ((CLR_RT_HeapBlock *)busConnectionSettings->GetElement(busIndex - 1))->Dereference(); // CS is always active low spiDeviceConfig->ChipSelectActive = false; From a5879f168d550cafc4e476baf812a3542be5bc9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 18:31:58 +0100 Subject: [PATCH 236/572] Improvements in Skyworks SPI - Add array of flags to signal pending spi config changes. - Rework CPU SPI config code to handle this procedure of reconfigure SPI. - Update code accordingly. - Update Skyworks SPI assembly declaration following Skyworks-Timing-Software/MCU#16. --- .../com_sky_nf_dev_spi_native.cpp | 5 ++- .../com_sky_nf_dev_spi_native.h | 4 +- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 36 +++++++++++++++++- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 37 ++++++++++++++----- .../sys_dev_spi_native_target.h | 1 + 5 files changed, 68 insertions(+), 15 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index 708b7becf5..fdf34247cb 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -27,6 +27,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, NULL, NULL, NULL, @@ -39,9 +40,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = { "Com.SkyworksInc.NanoFramework.Devices.Spi", - 0x6E9C1C37, + 0xCFFC5E97, method_lookup, - { 1, 0, 0, 1 } + { 100, 0, 0, 2 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 90842a4a8b..03a7f3002c 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -46,20 +46,20 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus { static const int FIELD_STATIC___busConnectionSettings = 0; - static const int FIELD_STATIC___busSettingsChanged = 1; static const int FIELD___syncLock = 1; static const int FIELD___bufferSingleOperation = 2; NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN); NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeReportBusSettingsChanged___VOID__I4); //--// }; struct Library_com_sky_nf_dev_spi_native_ThisAssembly { - static const int FIELD_STATIC__GitCommitDate = 2; + static const int FIELD_STATIC__GitCommitDate = 1; //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 27386c0ae3..b35f4c36ea 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -4,6 +4,10 @@ extern NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex); extern void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred); +extern bool CPU_SPI_Initialize_Extended( + uint8_t busIndex, + const SPI_DEVICE_CONFIGURATION &busConfiguration, + bool reconfigure); typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus Devices_Spi_SpiBus; typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration @@ -22,6 +26,9 @@ static HRESULT SPI_nWrite_nRead( // Saved config for each available SPI bus SPI_DEVICE_CONFIGURATION SpiConfigs[NUM_SPI_BUSES]; +// flags for bus config changes pending +bool BusConfigChangesPending[NUM_SPI_BUSES]; + void Com_Sky_Spi_Callback(int busIndex) { (void)busIndex; @@ -113,8 +120,10 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // check if this SPI has been initialized palSpi = GetNfPalfromBusIndex(busIndex); - if (palSpi->Handle == NULL) + if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex - 1]) { + // SPI bus not initialized or config changes pending + // compose SPI_DEVICE_CONFIGURATION // get ref to SpiBaseConfiguration from static _busConnectionSettings array... // need to access it through the assembly @@ -147,7 +156,10 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // store this here too palSpi->BufferIs16bits = spiDeviceConfig->MD16bits; - CPU_SPI_Initialize(busIndex, *spiDeviceConfig); + CPU_SPI_Initialize_Extended(busIndex, *spiDeviceConfig, true); + + // lower changes pending flag + BusConfigChangesPending[busIndex - 1] = false; } // Buffers used either for the SpanBye either for the Byte array @@ -537,3 +549,23 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ NANOCLR_NOCLEANUP(); } + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeReportBusSettingsChanged___VOID__I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + int8_t busIndex; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + busIndex = (int8_t)stack.Arg1().NumericByRef().s4; + + // SPI bus index is 1 based, but the array is 0 based + BusConfigChangesPending[busIndex - 1] = true; + + NANOCLR_NOCLEANUP(); +} \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 43ae88220b..623e62e438 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -481,10 +481,10 @@ HRESULT CPU_SPI_nWrite_nRead( NANOCLR_NOCLEANUP(); } -bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) +// this is exposing the extended call that allow for re-configuration of SPI +bool CPU_SPI_Initialize_Extended(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration, bool reconfigure) { NF_PAL_SPI *palSpi = NULL; - NF_SpiDriver_Init_t *initSpiData = NULL; Ecode_t configResult; GPIO_Port_TypeDef port; uint32_t portPin; @@ -549,7 +549,6 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon if (palSpi->Handle == NULL) { - // allocate memory for the USART_InitSync_TypeDef palSpi->Handle = (NF_SpiDriver_Handle_t)platform_malloc(sizeof(NF_SpiDriver_HandleData_t)); @@ -562,25 +561,27 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon memset(palSpi->Handle, 0, sizeof(NF_SpiDriver_HandleData_t)); // allocate memory for the NF_SpiDriver_Init_t - initSpiData = (NF_SpiDriver_Init_t *)platform_malloc(sizeof(NF_SpiDriver_Init_t)); + palSpi->InitSpiData = (NF_SpiDriver_Init_t *)platform_malloc(sizeof(NF_SpiDriver_Init_t)); // sanity check allocation - if (initSpiData == NULL) + if (palSpi->InitSpiData == NULL) { platform_free(palSpi->Handle); return false; } - memset(initSpiData, 0, sizeof(NF_SpiDriver_Init_t)); + memset(palSpi->InitSpiData, 0, sizeof(NF_SpiDriver_Init_t)); // call handler to configure pins - initSpiConfig(*initSpiData, busConfiguration.BusConfiguration == SpiBusConfiguration_HalfDuplex); + initSpiConfig(*palSpi->InitSpiData, busConfiguration.BusConfiguration == SpiBusConfiguration_HalfDuplex); + +jump_to_init: // get the SPI configuration - GetSpiConfig(busConfiguration, *initSpiData); + GetSpiConfig(busConfiguration, *palSpi->InitSpiData); - configResult = NF_SpiDriver_Init(palSpi->Handle, initSpiData); + configResult = NF_SpiDriver_Init(palSpi->Handle, palSpi->InitSpiData); _ASSERTE(configResult == ECODE_OK); palSpi->ChipSelect = busConfiguration.DeviceChipSelect; @@ -592,10 +593,28 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon GPIO_PinModeSet(port, portPin, gpioModePushPull, busConfiguration.ChipSelectActive ? 0 : 1); } } + else + { + // there's already a handle, check if we need to re-configure the SPI bus + if(reconfigure) + { + // deinitalize the SPI bus + NF_SpiDriver_DeInit(palSpi->Handle); + + // jump straight to init + goto jump_to_init; + } + } return true; } +// this is exposing the "standard" call +bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) +{ + return CPU_SPI_Initialize_Extended(busIndex, busConfiguration, false); +} + bool CPU_SPI_Uninitialize(uint8_t busIndex) { NF_PAL_SPI *palSpi = NULL; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 5c9e918a34..77c15b72d8 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -84,6 +84,7 @@ struct NF_PAL_SPI int32_t ChipSelect; NF_SpiDriver_Handle_t Handle; + NF_SpiDriver_Init_t *InitSpiData; }; //////////////////////////////////////////// From d4cb9abaac2822e81f03a8b6c0d9f983496e3b65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 18:38:44 +0100 Subject: [PATCH 237/572] Update Slyworks I2C and SPI assemblies declaration - Following Skyworks-Timing-Software/MCU#17. --- .../com_sky_nf_dev_i2c_native.cpp | 5 ++--- .../com_sky_nf_dev_i2c_native.h | 7 ------- .../com_sky_nf_dev_spi_native.cpp | 5 ++--- .../com_sky_nf_dev_spi_native.h | 7 ------- 4 files changed, 4 insertions(+), 20 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp index 6eadd9f0c5..b67bab15d6 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp @@ -20,15 +20,14 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_I2c = { "Com.SkyworksInc.NanoFramework.Devices.I2c", - 0xF6A356D7, + 0x913E3D1E, method_lookup, - { 1, 0, 0, 0 } + { 100, 0, 0, 1 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h index aa55925633..d0e114bab7 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.h @@ -42,13 +42,6 @@ struct Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I //--// }; -struct Library_com_sky_nf_dev_i2c_native_ThisAssembly -{ - static const int FIELD_STATIC__GitCommitDate = 1; - - //--// -}; - extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_I2c; #endif //_COM_SKY_NF_DEV_I2C_NATIVE_H_ diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index fdf34247cb..4a6b82f253 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -34,15 +34,14 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = { "Com.SkyworksInc.NanoFramework.Devices.Spi", - 0xCFFC5E97, + 0x294C1D50, method_lookup, - { 100, 0, 0, 2 } + { 100, 0, 0, 3 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 03a7f3002c..aebf5f005f 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -57,13 +57,6 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S //--// }; -struct Library_com_sky_nf_dev_spi_native_ThisAssembly -{ - static const int FIELD_STATIC__GitCommitDate = 1; - - //--// -}; - extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi; #endif //_COM_SKY_NF_DEV_SPI_NATIVE_H_ From 7d20262b383a9ad73839f1479a70861529852f27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:02:46 +0100 Subject: [PATCH 238/572] Fix parsing ADC channel init --- ...ative_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 2482821d3f..19ae528bde 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -13,15 +13,21 @@ typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannelConfig void ParseAdcChannelConfig(CLR_RT_HeapBlock *channelConfiguration, void *adcInit) { ADC_InitSingle_TypeDef channelInitSingle = ADC_INITSINGLE_DEFAULT; - //ADC_InitScan_TypeDef channelInitScan = ADC_INITSCAN_DEFAULT; + // ADC_InitScan_TypeDef channelInitScan = ADC_INITSCAN_DEFAULT; // now map the AdcChannelConfiguration object to the native structure - channelInitSingle.prsSel = - (ADC_PRSSEL_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___prsSampleTrigger].NumericByRef().s4; + + // handle PRS differently because it's a C# enum and -1 is the disabled value + // if PRS is disabled, use the default value + int32_t prsSel = channelConfiguration[AdcChannelConfiguration::FIELD___prsSampleTrigger].NumericByRef().s4; + channelInitSingle.prsSel = prsSel == -1 ? adcPRSSELCh0 : (ADC_PRSSEL_TypeDef)prsSel; + channelInitSingle.acqTime = (ADC_AcqTime_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___aquisitionTime].NumericByRef().s4; channelInitSingle.reference = (ADC_Ref_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___referenceVoltage].NumericByRef().s4; + channelInitSingle.resolution = + (ADC_Res_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___sampleResolution].NumericByRef().s4; channelInitSingle.diff = (AdcChannelMode)channelConfiguration[AdcChannelConfiguration::FIELD___channelMode].NumericByRef().s4 == AdcChannelMode_Differential From fab3c74bda15b2cab262371e22ce15eed4a5e0bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:03:18 +0100 Subject: [PATCH 239/572] Add missing setting for ADC pos selection --- ..._gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 19ae528bde..5988d80c0c 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -97,6 +97,10 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati // get a pointer to the channel AdcChannelConfiguration object instance ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitSingle); + + // select positive input + channelInitSingle.posSel = (ADC_PosSel_TypeDef)adcDefinition.posSel; + ADC_InitSingle(adcDriver, &channelInitSingle); while (samplesCount--) From a27a275963a5e365adff1b89978d354230799fca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:03:54 +0100 Subject: [PATCH 240/572] Add check for diff mode in ADC channel config - Not supported at this time. --- ...gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 5988d80c0c..9d68712566 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -97,6 +97,11 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati // get a pointer to the channel AdcChannelConfiguration object instance ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitSingle); + // sanity check (only support single ended mode at this time) + if (channelInitSingle.diff) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOTIMPL); + } // select positive input channelInitSingle.posSel = (ADC_PosSel_TypeDef)adcDefinition.posSel; From d80355f7ae03d9f261195bf894cd86507a6d8942 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:04:13 +0100 Subject: [PATCH 241/572] Fix handling of auto averaging --- ..._gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 9d68712566..feaf0eab9a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -49,8 +49,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati ADC_TypeDef *adcDriver = NULL; ADC_InitSingle_TypeDef channelInitSingle; uint64_t samplesAccumulator = 0; - uint32_t averageCount; - uint32_t samplesCount; + int32_t averageCount; + int32_t samplesCount; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); From 2d9496fb16f9c44e28a6b4b839b415e08c703a94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:04:33 +0100 Subject: [PATCH 242/572] Fix checks for ADC init conditions --- ..._native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 6829205a4d..ed408d1168 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -73,14 +73,14 @@ HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration // is this ADC already initialized? if ( -#if GECKO_USE_ADC0 - (adcDriver == ADC0 && !adcInitialized) +#if GECKO_USE_ADC0 && !GECKO_USE_ADC1 + (adcDriver == ADC0 && !*adcInitialized) #endif #if GECKO_USE_ADC0 && GECKO_USE_ADC1 || #endif -#if GECKO_USE_ADC1 - (adcDriver == ADC1 && !adcInitialized) +#if !GECKO_USE_ADC0 && GECKO_USE_ADC1 + (adcDriver == ADC1 && !*adcInitialized) #endif ) { From c40cfe102a807c6c475bf5eac9797dc7da7ac6c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:04:56 +0100 Subject: [PATCH 243/572] Remove unnecessary init of HPFER clock when config ADC --- ..._gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index ed408d1168..2dbbdd0ad7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -101,7 +101,6 @@ HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration adcInit->tailgate = (bool)adcConfiguration[AdcConfiguration::FIELD___tailgating].NumericByRef().u1; // Enable ADC clock - CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(adcClock, true); // init to max possible ADC clock From 8b2da7b9686241eb9469f036aefce1df09f9aab8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 11 Oct 2022 22:38:09 +0100 Subject: [PATCH 244/572] More work to improve UsbStream --- ..._usbstream_native_System_Device_Usb_UsbStream.cpp | 9 ++++++++- .../sys_dev_usbstream_native_target.h | 12 ++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 6139130642..91e6e8084a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -112,7 +112,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit uint32_t offset = 0; sl_status_t reqStatus; bool conn; - uint32_t bytesTransfered; + uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -158,6 +158,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); @@ -218,6 +221,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead sl_status_t reqStatus; bool conn; uint32_t bytesTransfered; + uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -263,6 +267,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); + // rough estimation!! + estimatedDurationMiliseconds = count / 64; + // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index e39323f203..b90868a5e0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -14,7 +14,19 @@ #include +// need these declared here as they are scattered throughout Gecko SDK and config files extern char UsbClassVendorDescription[32 + 1]; extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; extern uint8_t sl_usbd_vendor_winusb_number; extern "C" void sli_usbd_vendor_winusb_init(void); + +// struct representing the UART +typedef struct +{ + HAL_RingBuffer RxRingBuffer; + uint8_t *RxBuffer; + uint16_t RxBytesToRead; + + uint32_t ReceivedBytesThreshold; + +} NF_PAL_USB; From 085b391a3fca6bed47b7b0aa2ffab14e09bddcba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 12:23:00 +0100 Subject: [PATCH 245/572] Update declaration of UsbStream assembly - Following nanoframework/System.Device.UsbClient#7. --- src/System.Device.UsbStream/sys_dev_usbstream_native.cpp | 4 ++-- src/System.Device.UsbStream/sys_dev_usbstream_native.h | 2 +- ...dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp | 2 +- .../sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 16939392e3..2c71e3899b 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -11,8 +11,8 @@ static const CLR_RT_MethodHandler method_lookup[] = { NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN, NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN, NULL, NULL, NULL, @@ -61,7 +61,7 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x0024FE8B, + 0x74531012, method_lookup, { 1, 0, 0, 0 } }; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 72360955de..ef710e5250 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -32,7 +32,7 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient { static const int FIELD_STATIC__UsbDeviceConnectionChanged = 0; - NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsConnected___STATIC__BOOLEAN); //--// }; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp index 3b9d3c0133..94e2cd5b43 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp @@ -6,7 +6,7 @@ #include "sys_dev_usbstream_native.h" -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp index d7d610ee55..57f10f13a4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp @@ -6,7 +6,7 @@ #include "sys_dev_usbstream_native.h" #include "sys_dev_usbstream_native_target.h" -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); From d6a314309388e6734998cf4264d6adf4c2a4bb9f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 12:23:45 +0100 Subject: [PATCH 246/572] Fix adding WinUSB device interface class property --- .../_common/autogen/sl_usbd_class_vendor_instances.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 1943c27e02..ce1d10cdbe 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -150,7 +150,7 @@ void sli_usbd_vendor_winusb_init() // add device class GUID to WinUSB properties sl_usbd_vendor_add_microsoft_ext_property( - config_number, + class_number, SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, DEVICEINTERFACE_GUID_PROP_NAME_LEN, From 5f6b40b0d06b1c6de20af933635624b6b4a68ea7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:42:46 +0100 Subject: [PATCH 247/572] Revert "Fix adding WinUSB device interface class property" This reverts commit 2a2a77019f0e0c57d69ae6a82d5de6ed5855f7f5. --- .../_common/autogen/sl_usbd_class_vendor_instances.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index ce1d10cdbe..1943c27e02 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -150,7 +150,7 @@ void sli_usbd_vendor_winusb_init() // add device class GUID to WinUSB properties sl_usbd_vendor_add_microsoft_ext_property( - class_number, + config_number, SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, DEVICEINTERFACE_GUID_PROP_NAME_LEN, From 45bcac18e0f952afbaface9a4cf5f70bae9de8b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:44:52 +0100 Subject: [PATCH 248/572] Remove call to check for device connected - This is already performed in the Gecko API so no need to do it here. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 91e6e8084a..d7cb032458 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -111,7 +111,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - bool conn; uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL @@ -146,15 +145,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // check if device is connected (enabled) - sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); - - if (!conn) - { - // device is not connected, return exception - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); - } - // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); @@ -219,7 +209,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - bool conn; uint32_t bytesTransfered; uint32_t estimatedDurationMiliseconds; @@ -255,15 +244,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // check if device is connected (enabled) - sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); - - if (!conn) - { - // device is not connected, return exception - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); - } - // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); From d35c7896b5b5cf9bf2b82e8b776f25fdf35f3b8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:47:40 +0100 Subject: [PATCH 249/572] Rework sli_usbd_vendor_winusb_init - Function now returns SL status. - Add check for successful call to add configuration. - Add global flag so WinUSB init is not performed repeatedly on CLR reboot. --- .../autogen/sl_usbd_class_vendor_instances.c | 22 +++++++++++++++++-- .../autogen/sl_usbd_class_vendor_instances.h | 2 +- ...eam_native_System_Device_Usb_UsbStream.cpp | 5 ++++- .../sys_dev_usbstream_native_target.h | 2 +- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 1943c27e02..1ae094c2a6 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -39,6 +39,9 @@ extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t dat char UsbClassVendorDescription[32 + 1]; char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; +// flag for USB WinUSB intialized +static bool usbdVendorWinusbInited = false; + typedef enum __nfpack UsbEventType { UsbEventType_Invalid = 0, @@ -104,7 +107,7 @@ void sli_usbd_vendor_winusb_setup_req(uint8_t class_nbr, const sl_usbd_setup_req // Global functions. /* initialize winusb instance */ -void sli_usbd_vendor_winusb_init() +sl_status_t sli_usbd_vendor_winusb_init() { bool intr_en = true; uint16_t interval = 0; @@ -115,6 +118,12 @@ void sli_usbd_vendor_winusb_init() char *configs = NULL; char *token = NULL; + // check if already initialized + if (usbdVendorWinusbInited) + { + return SL_STATUS_OK; + } + /* configs to attach the class instance to */ configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; @@ -141,7 +150,11 @@ void sli_usbd_vendor_winusb_init() if (!strcmp(token, "config0") || !strcmp(token, "all")) { config_number = sl_usbd_configuration_config0_number; - sl_usbd_vendor_add_to_configuration(class_number, config_number); + if(sl_usbd_vendor_add_to_configuration(class_number, config_number) != SL_STATUS_OK) + { + // error adding class to configuration + return SL_STATUS_FAIL; + } } /* next token */ @@ -156,6 +169,11 @@ void sli_usbd_vendor_winusb_init() DEVICEINTERFACE_GUID_PROP_NAME_LEN, (const uint8_t *)UsbClassVendorDeviceInterfaceGuid, sizeof(UsbClassVendorDeviceInterfaceGuid)); + + // all good here, update flag + usbdVendorWinusbInited = true; + + return SL_STATUS_OK; } void sl_usbd_vendor_winusb_on_enable_event(void) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h index 23e4b3a410..72776bcc84 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -31,6 +31,6 @@ __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req /* init functions for all vendor instances */ -void sli_usbd_vendor_winusb_init(void); +sl_status_t sli_usbd_vendor_winusb_init(void); #endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d7cb032458..2e1057d7bd 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -89,7 +89,10 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen // store device description hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); - sli_usbd_vendor_winusb_init(); + if (sli_usbd_vendor_winusb_init() != SL_STATUS_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } stack.SetResult_I4(sl_usbd_vendor_winusb_number); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index b90868a5e0..148c378f94 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -18,7 +18,7 @@ extern char UsbClassVendorDescription[32 + 1]; extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; extern uint8_t sl_usbd_vendor_winusb_number; -extern "C" void sli_usbd_vendor_winusb_init(void); +extern "C" sl_status_t sli_usbd_vendor_winusb_init(void); // struct representing the UART typedef struct From 3862a1a0ff9b374f14a3c235828f2c09e3fcd667 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 13:53:15 +0100 Subject: [PATCH 250/572] Rework async execution of Write and Read operations - Replace assert with check for various possible outcomes and throw exceptions accordingly. - Add clean-up section to pop values from stack and add return value for read - Minor fixes in code style. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 64 ++++++++++++++----- 1 file changed, 47 insertions(+), 17 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 2e1057d7bd..d7098fa9ea 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -72,7 +72,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen // get device class GUID deviceClassGuid = stack.Arg1().RecoverString(); - ; // clear destination memset(UsbClassVendorDeviceInterfaceGuid, 0, sizeof(UsbClassVendorDeviceInterfaceGuid)); @@ -152,7 +151,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit data = dataBuffer->GetElement(offset); // rough estimation!! - estimatedDurationMiliseconds = count / 64; + estimatedDurationMiliseconds = count / 10; // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); @@ -178,7 +177,16 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NULL, true); - _ASSERTE(reqStatus == SL_STATUS_OK); + if (reqStatus == SL_STATUS_INVALID_STATE) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + else if (reqStatus == SL_STATUS_NOT_READY) + { + // transfer already in progress, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } } while (eventResult) @@ -188,13 +196,18 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } - // pop "count" heap block from stack - stack.PopValue(); + NANOCLR_CLEANUP(); - // pop timeout heap block from stack - stack.PopValue(); + if (stack.m_customState > 1) + { + // pop "count" heap block from stack + stack.PopValue(); - NANOCLR_NOCLEANUP(); + // pop timeout heap block from stack + stack.PopValue(); + } + + NANOCLR_CLEANUP_END(); } HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( @@ -212,7 +225,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t bytesTransfered; + uint32_t bytesTransfered = 0; uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL @@ -251,7 +264,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead data = dataBuffer->GetElement(offset); // rough estimation!! - estimatedDurationMiliseconds = count / 64; + estimatedDurationMiliseconds = count / 10; // setup timeout hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); @@ -276,7 +289,16 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead UsbAsyncReadCompleted, NULL); - _ASSERTE(reqStatus == SL_STATUS_OK); + if (reqStatus == SL_STATUS_INVALID_STATE) + { + // device is not connected, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + else if (reqStatus == SL_STATUS_NOT_READY) + { + // transfer already in progress, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } } while (eventResult) @@ -286,13 +308,21 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); } - // pop "count" heap block from stack - stack.PopValue(); + NANOCLR_CLEANUP(); + + if (stack.m_customState > 1) + { + // pop "count" heap block from stack + stack.PopValue(); - // pop timeout heap block from stack - stack.PopValue(); + // pop timeout heap block from stack + stack.PopValue(); + } - stack.SetResult_I4(bytesTransfered); + if (SUCCEEDED(hr)) + { + stack.SetResult_I4(bytesTransfered); + } - NANOCLR_NOCLEANUP(); + NANOCLR_CLEANUP_END(); } From 0ebdc417c14065267f30e0b484a16188d81bebd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 12 Oct 2022 18:49:31 +0100 Subject: [PATCH 251/572] Improve timeout setting for W/R operations - Now coming from timeout fields. - Add implementation to event handlers. - Improve post processing of events. - Add processing for timeout event. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 62 +++++++++++++------ .../sys_dev_usbstream_native_target.h | 6 +- 2 files changed, 47 insertions(+), 21 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d7098fa9ea..63e8a37d1b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -6,6 +6,8 @@ #include #include "sys_dev_usbstream_native_target.h" +NF_PAL_USB UsbStream_PAL; + static void UsbAsyncWriteCompleted( uint8_t class_nbr, void *p_buf, @@ -17,10 +19,13 @@ static void UsbAsyncWriteCompleted( (void)class_nbr; (void)p_buf; (void)buf_len; - (void)xfer_len; - (void)p_callback_arg; (void)status; + NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; + + // store TX count + usbPal->TxBytesSent = xfer_len; + Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); } @@ -35,10 +40,13 @@ static void UsbAsyncReadCompleted( (void)class_nbr; (void)p_buf; (void)buf_len; - (void)xfer_len; - (void)p_callback_arg; (void)status; + NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; + + // store RX count + usbPal->RxBytesReceived = xfer_len; + Events_Set(SYSTEM_EVENT_FLAG_USB_IN); } @@ -70,6 +78,12 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen const char *deviceDescription; const char *deviceClassGuid; + // int32_t bufferSize; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + // get device class GUID deviceClassGuid = stack.Arg1().RecoverString(); @@ -113,7 +127,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -150,11 +163,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); - // rough estimation!! - estimatedDurationMiliseconds = count / 10; - - // setup timeout - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + // setup timeout from managed property + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); // this is a long running operation... @@ -174,7 +184,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit (void *)data, count, UsbAsyncWriteCompleted, - NULL, + &UsbStream_PAL, true); if (reqStatus == SL_STATUS_INVALID_STATE) @@ -196,6 +206,13 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); } + // timeout expired + if (!eventResult) + { + // timeout has expired, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + NANOCLR_CLEANUP(); if (stack.m_customState > 1) @@ -225,8 +242,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t bytesTransfered = 0; - uint32_t estimatedDurationMiliseconds; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -263,11 +278,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // get a the pointer to the array by using the offset data = dataBuffer->GetElement(offset); - // rough estimation!! - estimatedDurationMiliseconds = count / 10; - - // setup timeout - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + // setup timeout from managed property + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___readTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); // this is a long running operation... @@ -280,6 +292,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // bump custom state stack.m_customState = 2; + // clear RX counter + UsbStream_PAL.RxBytesReceived = 0; + // start read operation with async API // requesting handling of "End-of-transfer" reqStatus = sl_usbd_vendor_read_bulk_async( @@ -287,7 +302,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead (void *)data, count, UsbAsyncReadCompleted, - NULL); + &UsbStream_PAL); if (reqStatus == SL_STATUS_INVALID_STATE) { @@ -308,6 +323,13 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); } + // timeout expired + if (!eventResult) + { + // timeout has expired, return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + NANOCLR_CLEANUP(); if (stack.m_customState > 1) @@ -321,7 +343,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead if (SUCCEEDED(hr)) { - stack.SetResult_I4(bytesTransfered); + stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); } NANOCLR_CLEANUP_END(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index 148c378f94..ef5a05d683 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -26,7 +26,11 @@ typedef struct HAL_RingBuffer RxRingBuffer; uint8_t *RxBuffer; uint16_t RxBytesToRead; - + uint16_t RxBytesReceived; uint32_t ReceivedBytesThreshold; + uint16_t TxBytesSent; + } NF_PAL_USB; + +extern NF_PAL_USB UsbStream_PAL; From 2fa6a9402e98e762264709d09148d15ae3377e42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 15:23:41 +0100 Subject: [PATCH 252/572] Fix I2C bus parameter From 181d897c651f91d93538465798692db48a20d49e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Oct 2022 15:25:02 +0100 Subject: [PATCH 253/572] Move Skyworks I2C library to src folder - No reason for being inside the PAL folder. From c6074aa2bdf62e18f7c2eb12d0785f2cd6180ec7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:02:46 +0100 Subject: [PATCH 254/572] Fix parsing ADC channel init --- ...ative_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 2482821d3f..19ae528bde 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -13,15 +13,21 @@ typedef Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannelConfig void ParseAdcChannelConfig(CLR_RT_HeapBlock *channelConfiguration, void *adcInit) { ADC_InitSingle_TypeDef channelInitSingle = ADC_INITSINGLE_DEFAULT; - //ADC_InitScan_TypeDef channelInitScan = ADC_INITSCAN_DEFAULT; + // ADC_InitScan_TypeDef channelInitScan = ADC_INITSCAN_DEFAULT; // now map the AdcChannelConfiguration object to the native structure - channelInitSingle.prsSel = - (ADC_PRSSEL_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___prsSampleTrigger].NumericByRef().s4; + + // handle PRS differently because it's a C# enum and -1 is the disabled value + // if PRS is disabled, use the default value + int32_t prsSel = channelConfiguration[AdcChannelConfiguration::FIELD___prsSampleTrigger].NumericByRef().s4; + channelInitSingle.prsSel = prsSel == -1 ? adcPRSSELCh0 : (ADC_PRSSEL_TypeDef)prsSel; + channelInitSingle.acqTime = (ADC_AcqTime_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___aquisitionTime].NumericByRef().s4; channelInitSingle.reference = (ADC_Ref_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___referenceVoltage].NumericByRef().s4; + channelInitSingle.resolution = + (ADC_Res_TypeDef)channelConfiguration[AdcChannelConfiguration::FIELD___sampleResolution].NumericByRef().s4; channelInitSingle.diff = (AdcChannelMode)channelConfiguration[AdcChannelConfiguration::FIELD___channelMode].NumericByRef().s4 == AdcChannelMode_Differential From e2a71fbf1217434e947deec49f3545fa70e95a59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:03:18 +0100 Subject: [PATCH 255/572] Add missing setting for ADC pos selection --- ..._gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 19ae528bde..5988d80c0c 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -97,6 +97,10 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati // get a pointer to the channel AdcChannelConfiguration object instance ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitSingle); + + // select positive input + channelInitSingle.posSel = (ADC_PosSel_TypeDef)adcDefinition.posSel; + ADC_InitSingle(adcDriver, &channelInitSingle); while (samplesCount--) From 69d510ae08894399c50c6b1501542b49f183b944 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:03:54 +0100 Subject: [PATCH 256/572] Add check for diff mode in ADC channel config - Not supported at this time. --- ...gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 5988d80c0c..9d68712566 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -97,6 +97,11 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati // get a pointer to the channel AdcChannelConfiguration object instance ParseAdcChannelConfig(pThis[FIELD___adcChannelConfiguration].Dereference(), &channelInitSingle); + // sanity check (only support single ended mode at this time) + if (channelInitSingle.diff) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOTIMPL); + } // select positive input channelInitSingle.posSel = (ADC_PosSel_TypeDef)adcDefinition.posSel; From 9803c44ac3d2484d0ab363ba79d531ce862e84d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:04:13 +0100 Subject: [PATCH 257/572] Fix handling of auto averaging --- ..._gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp index 9d68712566..feaf0eab9a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel.cpp @@ -49,8 +49,8 @@ HRESULT Library_nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcChannel::Nati ADC_TypeDef *adcDriver = NULL; ADC_InitSingle_TypeDef channelInitSingle; uint64_t samplesAccumulator = 0; - uint32_t averageCount; - uint32_t samplesCount; + int32_t averageCount; + int32_t samplesCount; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); From fa22961d81ec14492880beccb9e8a8961e2a0e15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:04:33 +0100 Subject: [PATCH 258/572] Fix checks for ADC init conditions --- ..._native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 6829205a4d..ed408d1168 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -73,14 +73,14 @@ HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration // is this ADC already initialized? if ( -#if GECKO_USE_ADC0 - (adcDriver == ADC0 && !adcInitialized) +#if GECKO_USE_ADC0 && !GECKO_USE_ADC1 + (adcDriver == ADC0 && !*adcInitialized) #endif #if GECKO_USE_ADC0 && GECKO_USE_ADC1 || #endif -#if GECKO_USE_ADC1 - (adcDriver == ADC1 && !adcInitialized) +#if !GECKO_USE_ADC0 && GECKO_USE_ADC1 + (adcDriver == ADC1 && !*adcInitialized) #endif ) { From f13b505bcfbe204eea85b20475517a604b8c7193 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 14:04:56 +0100 Subject: [PATCH 259/572] Remove unnecessary init of HPFER clock when config ADC --- ..._gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index ed408d1168..2dbbdd0ad7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -101,7 +101,6 @@ HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration adcInit->tailgate = (bool)adcConfiguration[AdcConfiguration::FIELD___tailgating].NumericByRef().u1; // Enable ADC clock - CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(adcClock, true); // init to max possible ADC clock From 053a1162fe261a8101eeb3de7943c1fc59a1c83f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 15:13:20 +0100 Subject: [PATCH 260/572] Skyworks EVB config upated to use a single USB Class Vendor instance --- .../SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h index a604eb6826..f5e936cd19 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h @@ -181,12 +181,10 @@ extern char UsbClassVendorDescription[32 + 1]; // Vendor Pools // Number of class instances <1-255> -// Default: 2 // Number of class instances. -#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 1 // Number of configurations <1-255> -// Default: 1 // Number of configurations. #define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 From 0fb3fdd494476740fbaf9e9e261d34fa34a02b39 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 15:30:30 +0100 Subject: [PATCH 261/572] Update declaration for UsbStream - Following nanoframework/System.Device.UsbClient#8. --- .../Modules/FindSystem.Device.UsbStream.cmake | 2 - .../System.Device.UsbStream.filters | 3 -- .../System.Device.UsbStream.vcxproj | 1 - .../sys_dev_usbstream_native.cpp | 22 ++++++-- .../sys_dev_usbstream_native.h | 30 +++++++---- ...tive_System_Device_Usb_UsbClient_stubs.cpp | 16 ------ ...tive_System_Device_Usb_UsbStream_stubs.cpp | 29 ++++++++++ ...eam_native_System_Device_Usb_UsbClient.cpp | 25 --------- ...eam_native_System_Device_Usb_UsbStream.cpp | 53 +++++++++++++++++++ .../SiliconLabs/_nanoCLR/targetHAL.cpp | 9 ++++ 10 files changed, 128 insertions(+), 62 deletions(-) delete mode 100644 src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp delete mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp diff --git a/CMake/Modules/FindSystem.Device.UsbStream.cmake b/CMake/Modules/FindSystem.Device.UsbStream.cmake index 015e70c968..c55694f60c 100644 --- a/CMake/Modules/FindSystem.Device.UsbStream.cmake +++ b/CMake/Modules/FindSystem.Device.UsbStream.cmake @@ -20,8 +20,6 @@ set(System.Device.UsbStream_SRCS sys_dev_usbstream_native.cpp - - sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp ) diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.filters b/src/System.Device.UsbStream/System.Device.UsbStream.filters index c5ff73772c..7f41043a0f 100644 --- a/src/System.Device.UsbStream/System.Device.UsbStream.filters +++ b/src/System.Device.UsbStream/System.Device.UsbStream.filters @@ -15,9 +15,6 @@ - - Source Files - Source Files diff --git a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj index 56503ccdf8..90228ee520 100644 --- a/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj +++ b/src/System.Device.UsbStream/System.Device.UsbStream.vcxproj @@ -19,7 +19,6 @@ - diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 2c71e3899b..ed5324dfe0 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -12,7 +12,6 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN, NULL, NULL, NULL, @@ -42,9 +41,18 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4, + NULL, NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID, NULL, NULL, NULL, @@ -55,15 +63,21 @@ static const CLR_RT_MethodHandler method_lookup[] = Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___STATIC__BOOLEAN, + NULL, + NULL, + NULL, + NULL, NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x74531012, + 0x9B726093, method_lookup, - { 1, 0, 0, 0 } + { 100, 0, 0, 1 } }; // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index ef710e5250..99f78fa256 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -28,36 +28,44 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_DeviceConnectionEventA //--// }; -struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient +struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbDeviceEvent { - static const int FIELD_STATIC__UsbDeviceConnectionChanged = 0; - - NANOCLR_NATIVE_DECLARE(get_IsConnected___STATIC__BOOLEAN); + static const int FIELD___eventType = 3; + static const int FIELD___eventData = 4; + static const int FIELD___interfaceIndex = 5; //--// }; -struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbDeviceEvent +struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbDeviceEventListener { - static const int FIELD___eventType = 3; - static const int FIELD___eventData = 4; - static const int FIELD___interfaceIndex = 5; + static const int FIELD___usbStream = 1; //--// }; struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream { + static const int FIELD_STATIC___streamCreated = 0; + static const int FIELD___streamIndex = 1; - static const int FIELD___disposed = 2; - static const int FIELD___writeTimeout = 3; - static const int FIELD___readTimeout = 4; + static const int FIELD___useDeviceEventListener = 2; + static const int FIELD___disposed = 3; + static const int FIELD___writeTimeout = 4; + static const int FIELD___readTimeout = 5; + static const int FIELD___receivedBytesThreshold = 6; + static const int FIELD___bufferSize = 7; + static const int FIELD__UsbDeviceConnectionChanged = 8; + static const int FIELD__DataReceived = 9; NANOCLR_NATIVE_DECLARE(Flush___VOID); + NANOCLR_NATIVE_DECLARE(get_BytesToRead___I4); NANOCLR_NATIVE_DECLARE(NativeClose___VOID); NANOCLR_NATIVE_DECLARE(NativeOpen___I4__STRING__STRING); NANOCLR_NATIVE_DECLARE(NativeWrite___VOID__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(NativeRead___I4__SZARRAY_U1__I4__I4); + NANOCLR_NATIVE_DECLARE(NativeReceivedBytesThreshold___VOID__I4); + NANOCLR_NATIVE_DECLARE(get_IsConnected___STATIC__BOOLEAN); //--// }; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp deleted file mode 100644 index 94e2cd5b43..0000000000 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient_stubs.cpp +++ /dev/null @@ -1,16 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include "sys_dev_usbstream_native.h" - - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN( CLR_RT_StackFrame &stack ) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - - NANOCLR_NOCLEANUP(); -} diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp index 10c3c1197e..e605211e02 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp @@ -14,6 +14,15 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VO NANOCLR_NOCLEANUP(); } +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -52,3 +61,23 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_NOCLEANUP(); } + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___STATIC__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp deleted file mode 100644 index 57f10f13a4..0000000000 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbClient.cpp +++ /dev/null @@ -1,25 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include "sys_dev_usbstream_native.h" -#include "sys_dev_usbstream_native_target.h" - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbClient::get_IsConnected___STATIC__BOOLEAN( CLR_RT_StackFrame &stack ) -{ - NANOCLR_HEADER(); - - bool conn; - - if(sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) - { - stack.SetResult_Boolean(conn); - } - else - { - NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); - } - - NANOCLR_NOCLEANUP(); -} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 63e8a37d1b..1b4348708b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -61,11 +61,22 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VO NANOCLR_NOCLEANUP(); } +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + // platform_free(UsbStream_PAL.RxBuffer); + // UsbStream_PAL.RxBuffer = NULL; NANOCLR_NOCLEANUP(); } @@ -107,6 +118,19 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); } + // // alloc buffer memory + // bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; + // UsbStream_PAL.RxBuffer = (uint8_t *)platform_malloc(bufferSize); + + // // sanity check + // if (UsbStream_PAL.RxBuffer == NULL) + // { + // NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + // } + + // // init buffer + // UsbStream_PAL.RxRingBuffer.Initialize(UsbStream_PAL.RxBuffer, bufferSize); + stack.SetResult_I4(sl_usbd_vendor_winusb_number); NANOCLR_NOCLEANUP(); @@ -348,3 +372,32 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_CLEANUP_END(); } + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___STATIC__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + bool conn; + + if (sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) + { + stack.SetResult_Boolean(conn); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index af0f46213c..2bb21ca669 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -33,6 +33,11 @@ extern void DeInitPwm(); #include #endif +#if GECKO_FEATURE_USBD_WINUSB == TRUE +#include +#endif + + // global mutex protecting the internal state of the interpreter, including event flags // mutex_t interpreterGlobalMutex; @@ -139,6 +144,10 @@ adc0Initialized = false; adc1Initialized = false; #endif +#if GECKO_FEATURE_USBD_WINUSB == TRUE + memset(&UsbStream_PAL, 0, sizeof(UsbStream_PAL)); +#endif + // #if (HAL_USE_UART == TRUE) // #if defined(NF_SERIAL_COMM_STM32_UART_USE_USART1) && (NF_SERIAL_COMM_STM32_UART_USE_USART1 == TRUE) From 1f5671c3a21d51d43011124df24eedb4d46ceb31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 14 Oct 2022 19:24:16 +0100 Subject: [PATCH 262/572] Update UsbStream assembly declaration - Following nanoframework/System.Device.UsbClient#9. --- .../sys_dev_usbstream_native.cpp | 6 +- .../sys_dev_usbstream_native.h | 3 +- ...tive_System_Device_Usb_UsbStream_stubs.cpp | 16 ++-- ...eam_native_System_Device_Usb_UsbStream.cpp | 84 ++++++++++++------- 4 files changed, 69 insertions(+), 40 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index ed5324dfe0..e465544e00 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -49,6 +49,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4, NULL, NULL, @@ -64,7 +65,6 @@ static const CLR_RT_MethodHandler method_lookup[] = Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___STATIC__BOOLEAN, NULL, NULL, NULL, @@ -75,9 +75,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x9B726093, + 0x19581C1B, method_lookup, - { 100, 0, 0, 1 } + { 100, 0, 0, 2 } }; // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 99f78fa256..4e6d3af44f 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -59,17 +59,18 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream static const int FIELD__DataReceived = 9; NANOCLR_NATIVE_DECLARE(Flush___VOID); + NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); NANOCLR_NATIVE_DECLARE(get_BytesToRead___I4); NANOCLR_NATIVE_DECLARE(NativeClose___VOID); NANOCLR_NATIVE_DECLARE(NativeOpen___I4__STRING__STRING); NANOCLR_NATIVE_DECLARE(NativeWrite___VOID__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(NativeRead___I4__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(NativeReceivedBytesThreshold___VOID__I4); - NANOCLR_NATIVE_DECLARE(get_IsConnected___STATIC__BOOLEAN); //--// }; + extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream; #endif // SYS_DEV_USBSTREAM_NATIVE_H diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp index e605211e02..8df842110f 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp @@ -14,7 +14,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VO NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -23,7 +24,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesT NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -32,8 +33,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClos NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -42,7 +42,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -52,7 +52,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -62,7 +62,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -72,7 +72,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRece NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___STATIC__BOOLEAN( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 1b4348708b..efa90bda49 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -61,22 +61,43 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VO NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + bool conn; + + if (sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) + { + stack.SetResult_Boolean(conn); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } NANOCLR_NOCLEANUP(); } +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // get length of Rx ring buffer + stack.SetResult_U4(UsbStream_PAL.RxRingBuffer.Length()); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - // platform_free(UsbStream_PAL.RxBuffer); - // UsbStream_PAL.RxBuffer = NULL; + (void)stack; + + platform_free(UsbStream_PAL.RxBuffer); + UsbStream_PAL.RxBuffer = NULL; NANOCLR_NOCLEANUP(); } @@ -88,6 +109,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen const char *deviceDescription; const char *deviceClassGuid; + int32_t bufferSize; // int32_t bufferSize; @@ -118,18 +140,18 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); } - // // alloc buffer memory - // bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; - // UsbStream_PAL.RxBuffer = (uint8_t *)platform_malloc(bufferSize); + // alloc buffer memory + bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; + UsbStream_PAL.RxBuffer = (uint8_t *)platform_malloc(bufferSize); - // // sanity check - // if (UsbStream_PAL.RxBuffer == NULL) - // { - // NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); - // } + // sanity check + if (UsbStream_PAL.RxBuffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } - // // init buffer - // UsbStream_PAL.RxRingBuffer.Initialize(UsbStream_PAL.RxBuffer, bufferSize); + // init buffer + UsbStream_PAL.RxRingBuffer.Initialize(UsbStream_PAL.RxBuffer, bufferSize); stack.SetResult_I4(sl_usbd_vendor_winusb_number); @@ -378,25 +400,31 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRece { NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + int32_t threshold; - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___STATIC__BOOLEAN( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); - bool conn; + // check if threshold is valid + threshold = (int32_t)stack.Arg1().NumericByRef().s4; - if (sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) + if (threshold <= 0) { - stack.SetResult_Boolean(conn); + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); } - else + + // update field + pThis[FIELD___receivedBytesThreshold].NumericByRef().s4 = threshold; + + // update threshold value + UsbStream_PAL.ReceivedBytesThreshold = threshold; + + // fake call to event handler in case the new threshold was set + // to a value lower than the bytes that are already available + if ((uint32_t)threshold <= UsbStream_PAL.RxRingBuffer.Length()) { - NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + // PostManagedEvent(EVENT_SERIAL, 0, portIndex, SerialData_Chars); } NANOCLR_NOCLEANUP(); From 4a9a3a0adf68218d6115916f7a7ce6c6309ac858 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 17 Oct 2022 16:15:52 +0100 Subject: [PATCH 263/572] Fix build issue with USB stream --- .../sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index efa90bda49..7b5e62b733 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -99,7 +99,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClos platform_free(UsbStream_PAL.RxBuffer); UsbStream_PAL.RxBuffer = NULL; - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP_NOLABEL(); } HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( From ff2c906f12de11a36bf4a7cf0c8ec792f53a303f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 17 Oct 2022 18:33:53 +0100 Subject: [PATCH 264/572] Add nanoFramework.Hardware.GiantGecko assembly - Add declaration and build options. - Add implementation. - Following nanoframework/nanoFramework.Hardware.GiantGecko#1. --- CMake/Modules/FindNF_NativeAssemblies.cmake | 7 ++ ...indnanoFramework.Hardware.GiantGecko.cmake | 46 ++++++++++ CMakePresets.json | 2 +- .../nf_hardware_giantgecko.cpp | 38 +++++++++ .../nf_hardware_giantgecko.h | 47 +++++++++++ ...anoFramework_Hardware_GiantGecko_Power.cpp | 25 ++++++ ..._nanoFramework_Hardware_GiantGecko_RTC.cpp | 25 ++++++ ...ramework_Hardware_GiantGecko_Utilities.cpp | 83 +++++++++++++++++++ 8 files changed, 272 insertions(+), 1 deletion(-) create mode 100644 CMake/Modules/FindnanoFramework.Hardware.GiantGecko.cmake create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_RTC.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities.cpp diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index 8f6b77f949..6a9e3aa280 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -45,6 +45,7 @@ option(API_nanoFramework.Hardware.TI "option for nanoFramework.Hardwa # Silabs Giant Gecko only option(API_nanoFramework.GiantGecko.Adc "option for nanoFramework.GiantGecko.Adc") +option(API_Hardware.GiantGecko "option for Hardware.GiantGecko") ################################################################# # macro to perform individual settings to add an API to the build @@ -247,6 +248,12 @@ if(API_nanoFramework.GiantGecko.Adc) PerformSettingsForApiEntry("nanoFramework.GiantGecko.Adc") endif() +# nanoFramework.Hardware.GiantGecko +if(API_Hardware.GiantGecko) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Hardware.GiantGecko") +endif() + # nanoFramework.Runtime.Events if(API_nanoFramework.Runtime.Events) ##### API name here (doted name) diff --git a/CMake/Modules/FindnanoFramework.Hardware.GiantGecko.cmake b/CMake/Modules/FindnanoFramework.Hardware.GiantGecko.cmake new file mode 100644 index 0000000000..c321586b17 --- /dev/null +++ b/CMake/Modules/FindnanoFramework.Hardware.GiantGecko.cmake @@ -0,0 +1,46 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.Hardware.GiantGecko) + + +# set include directories +list(APPEND nanoFramework.Hardware.GiantGecko_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) + +# source files +set(nanoFramework.Hardware.GiantGecko_SRCS + + nf_hardware_giantgecko.cpp + + + nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power.cpp + nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Rtc.cpp + nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities.cpp + +) + +foreach(SRC_FILE ${nanoFramework.Hardware.GiantGecko_SRCS}) + + set(nanoFramework.Hardware.GiantGecko_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(nanoFramework.Hardware.GiantGecko_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${nanoFramework.Hardware.GiantGecko_SRC_FILE}") + endif() + + list(APPEND nanoFramework.Hardware.GiantGecko_SOURCES ${nanoFramework.Hardware.GiantGecko_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Hardware.GiantGecko DEFAULT_MSG nanoFramework.Hardware.GiantGecko_INCLUDE_DIRS nanoFramework.Hardware.GiantGecko_SOURCES) diff --git a/CMakePresets.json b/CMakePresets.json index a6f6a11c9f..6e1a819391 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -292,7 +292,7 @@ "SWO_OUTPUT": "OFF", "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", - "API_Hardware.Stm32": "OFF", + "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", "API_System.Device.Spi": "ON", "API_System.Device.I2c": "ON", diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.cpp new file mode 100644 index 0000000000..e1bb837955 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.cpp @@ -0,0 +1,38 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_giantgecko.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power::NativeEnterHibernateMode___STATIC__VOID, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power::NativeEnterShutoffMode___STATIC__VOID, + NULL, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Rtc::GetAlarm___STATIC__SystemDateTime, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Rtc::NativeRtcSetAlarm___STATIC__VOID__I4__U1__U1__U1__U1__U1, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities::NativeGetDeviceUniqueId___STATIC__VOID__SZARRAY_U1, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities::NativeGetProductionRevision___STATIC__U1, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities::NativeGetDeviceFamily___STATIC__U1, + Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities::NativeGetDeviceNumber___STATIC__U1, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Hardware_GiantGecko = +{ + "nanoFramework.Hardware.GiantGecko", + 0x01AA4021, + method_lookup, + { 100, 0, 0, 1 } +}; + +// clang-format on diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.h new file mode 100644 index 0000000000..84e342ef3e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko.h @@ -0,0 +1,47 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef NF_HARDWARE_GIANTGECKO_H +#define NF_HARDWARE_GIANTGECKO_H + +#include +#include +#include +#include + +struct Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power +{ + NANOCLR_NATIVE_DECLARE(NativeEnterHibernateMode___STATIC__VOID); + NANOCLR_NATIVE_DECLARE(NativeEnterShutoffMode___STATIC__VOID); + + //--// +}; + +struct Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Rtc +{ + NANOCLR_NATIVE_DECLARE(GetAlarm___STATIC__SystemDateTime); + NANOCLR_NATIVE_DECLARE(NativeRtcSetAlarm___STATIC__VOID__I4__U1__U1__U1__U1__U1); + + //--// +}; + +struct Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities +{ + static const int FIELD_STATIC___deviceUniqueId = 0; + static const int FIELD_STATIC___productionRevision = 1; + static const int FIELD_STATIC___deviceFamily = 2; + static const int FIELD_STATIC___deviceNumber = 3; + + NANOCLR_NATIVE_DECLARE(NativeGetDeviceUniqueId___STATIC__VOID__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(NativeGetProductionRevision___STATIC__U1); + NANOCLR_NATIVE_DECLARE(NativeGetDeviceFamily___STATIC__U1); + NANOCLR_NATIVE_DECLARE(NativeGetDeviceNumber___STATIC__U1); + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Hardware_GiantGecko; + +#endif // NF_HARDWARE_GIANTGECKO_H diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power.cpp new file mode 100644 index 0000000000..9ac69f5a51 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_giantgecko.h" + + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power::NativeEnterHibernateMode___STATIC__VOID( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Power::NativeEnterShutoffMode___STATIC__VOID( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_RTC.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_RTC.cpp new file mode 100644 index 0000000000..86509d49e1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_RTC.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_giantgecko.h" + + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Rtc::GetAlarm___STATIC__SystemDateTime( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Rtc::NativeRtcSetAlarm___STATIC__VOID__I4__U1__U1__U1__U1__U1( CLR_RT_StackFrame &stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities.cpp new file mode 100644 index 0000000000..117a661441 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.Hardware.GiantGecko/nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities.cpp @@ -0,0 +1,83 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_giantgecko.h" +#include + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities:: + NativeGetDeviceUniqueId___STATIC__VOID__SZARRAY_U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // device Unique ID is 64 bits long + uint8_t deviceUID[8]; + + // high 32 bits + uint32_t rawId = DEVINFO->UNIQUEH; + + deviceUID[3] = rawId; + rawId >>= 8; + deviceUID[2] = rawId; + rawId >>= 8; + deviceUID[1] = rawId; + rawId >>= 8; + deviceUID[0] = rawId; + + // low 32 bits + rawId = DEVINFO->UNIQUEL; + + deviceUID[7] = rawId; + rawId >>= 8; + deviceUID[6] = rawId; + rawId >>= 8; + deviceUID[5] = rawId; + rawId >>= 8; + deviceUID[4] = rawId; + + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array *buffer = stack.Arg0().DereferenceArray(); + + // get a the pointer to the byffer by using the first element of the array + uint8_t *data = buffer->GetFirstElement(); + + // 64 bit unique device ID => 16 bytes + // memory copy from the address pointed by deviceUID + memcpy(data, deviceUID, 8); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities:: + NativeGetProductionRevision___STATIC__U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // read PROD_REV from 31:24 bits + stack.SetResult_U1(DEVINFO->PART >> 24); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities::NativeGetDeviceFamily___STATIC__U1( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // read DEVICE_FAMILY from 23:16 bits + stack.SetResult_U1(DEVINFO->PART >> 16); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_hardware_giantgecko_nanoFramework_Hardware_GiantGecko_Utilities::NativeGetDeviceNumber___STATIC__U1( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // read DEVICE_NUMBER from 15:0 bits + stack.SetResult_U4((uint16_t)DEVINFO->PART); + + NANOCLR_NOCLEANUP_NOLABEL(); +} From 047fb12a62ebc94886ae9f44eed1040f05f495c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 26 Oct 2022 18:06:43 +0100 Subject: [PATCH 265/572] Add implementation for Serial Ports --- .../target_system_io_ports_config.cpp | 24 + .../target_system_io_ports_config.h | 11 + ..._ser_native_System_IO_Ports_SerialPort.cpp | 1185 +++++++++++++++++ .../sys_io_ser_native_target.h | 169 +++ 4 files changed, 1389 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..7bf6f18758 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.cpp @@ -0,0 +1,24 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_system_io_ports_config.h" +#include + +//////////// +// USART2 // +//////////// + +// GPIOs for USART2 are exposed in the J102 connector. + +// pin configuration for USART2 +// port for TX pin is: GPIOA +// port for RX pin is: GPIOA +// TX pin: is PF0 +// RX pin: is PF1 +// GPIO location is 5 +UART_INIT_CONFIG(2, gpioPortF, 0, 5, gpioPortF, 1, 5) + +// un-initialization for UART2 +UART_UNINIT(2, gpioPortF, 0, 5, gpioPortF, 1, 5) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.h new file mode 100644 index 0000000000..782ecfe749 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_io_ports_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +//////////// +// USART2 // +//////////// + +// enable USART2 +#define GECKO_USE_USART2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp new file mode 100644 index 0000000000..1f8e30116f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp @@ -0,0 +1,1185 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_io_ser_native_target.h" +#include + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) +NF_PAL_UART Uart0_PAL; +#endif +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) +NF_PAL_UART Uart1_PAL; +#endif +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) +NF_PAL_UART Uart2_PAL; +#endif +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) +NF_PAL_UART Uart3_PAL; +#endif +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) +NF_PAL_UART Uart4_PAL; +#endif +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) +NF_PAL_UART Uart5_PAL; +#endif + +static NF_PAL_UART *GetUartPAL(uint8_t index) +{ + // Choose the driver for this SerialDevice + switch (index) + { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) + case 1: + return &Uart0_PAL; +#endif + +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) + case 2: + return &Uart1_PAL; +#endif + +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) + case 3: + return &Uart2_PAL; +#endif + +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) + case 4: + return &Uart3_PAL; +#endif + +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) + case 5: + return &Uart4_PAL; +#endif + +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) + case 6: + return &Uart5_PAL; +#endif + + default: + return NULL; + } +} + +// This handler is invoked when a byte has been transmitted by the USART. +static void UsartTxHandler(uint8_t index) +{ + NATIVE_INTERRUPT_START + + NF_PAL_UART *palUart = GetUartPAL(index); + + if (palUart->TxOngoingCount > 0) + { + // load the next byte + palUart->Usart->TXDATA = *palUart->TxBuffer; + + // update pointer + palUart->TxBuffer++; + + // update counter + palUart->TxOngoingCount--; + } + else + { + // no more bytes to send + Events_Set(SYSTEM_EVENT_FLAG_COM_OUT); + } + + NATIVE_INTERRUPT_END +} + +// This callback is invoked when a character is received +static void UsartRxHandler(uint8_t index) +{ + NATIVE_INTERRUPT_START + + NF_PAL_UART *palUart = GetUartPAL(index); + + uint8_t newChar = (uint8_t)palUart->Usart->RXDATA; + + // store this into the UART Rx buffer + // don't care about the success of the operation, if it's full we are droping the char anyway + palUart->RxRingBuffer.Push(newChar); + + // is there a read operation going on? + if (palUart->RxBytesToRead > 0) + { + // yes + // check if the requested bytes are available in the buffer... + //... or if the watch char was received + if ((palUart->RxRingBuffer.Length() >= palUart->RxBytesToRead) || (newChar == palUart->WatchChar)) + { + // reset Rx bytes to read count + palUart->RxBytesToRead = 0; + + // fire event for Rx buffer complete + Events_Set(SYSTEM_EVENT_FLAG_COM_IN); + } + } + else if (palUart->NewLineChar > 0 && newChar == palUart->NewLineChar) + { + // fire event for new line char found + Events_Set(SYSTEM_EVENT_FLAG_COM_IN); + } + else + { + // no read operation ongoing, so fire an event, if the available bytes are above the threshold + if (palUart->RxRingBuffer.Length() >= palUart->ReceivedBytesThreshold) + { + // post a managed event with the port index and event code (check if this is the watch char or just another + // char) + // TODO: check if callbacks are registered so this is called only if there is anyone listening otherwise + PostManagedEvent( + EVENT_SERIAL, + 0, + index, + (newChar == palUart->WatchChar) ? SerialData_WatchChar : SerialData_Chars); + } + } + + NATIVE_INTERRUPT_END +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get length of Rx ring buffer + stack.SetResult_U4(palUart->RxRingBuffer.Length()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::get_InvertSignalLevels___BOOLEAN(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + (void)stack; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::set_InvertSignalLevels___VOID__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + (void)stack; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::Read___I4__SZARRAY_U1__I4__I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock hbTimeout; + CLR_RT_HeapBlock_Array *dataBuffer; + NF_PAL_UART *palUart = NULL; + + uint8_t *data; + + uint32_t length; + uint32_t count = 0; + uint32_t bytesRead = 0; + uint32_t offset = 0; + uint32_t bytesToRead = 0; + + int64_t *timeoutTicks; + bool eventResult = true; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // setup timeout + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___readTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + offset = stack.Arg2().NumericByRef().s4; + count = stack.Arg3().NumericByRef().s4; + + // perform parameter validation (only on initial call) + if (stack.m_customState == 1) + { + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // check parameters + FAULT_ON_NULL_ARG(dataBuffer); + + if ((offset > length) || (count > length)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (offset + count > length) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // figure out what's available in the Rx ring buffer + if (palUart->RxRingBuffer.Length() >= count) + { + // read from Rx ring buffer + bytesToRead = count; + + // we have enough bytes, skip wait for event + eventResult = false; + + // clear event by getting it + Events_Get(SYSTEM_EVENT_FLAG_COM_IN); + } + else + { + if (stack.m_customState == 1) + { + // not enough bytes available, have to read from UART + palUart->RxBytesToRead = count; + + // clear event by getting it + Events_Get(SYSTEM_EVENT_FLAG_COM_IN); + + // don't read anything from the buffer yet + bytesToRead = 0; + } + } + + while (eventResult) + { + if (stack.m_customState == 1) + { + if (bytesToRead > 0) + { + // enough bytes available + eventResult = false; + } + else + { + // need to read from the UART + // update custom state + stack.m_customState = 2; + } + } + else + { + // wait for event + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine + .WaitEvents(stack.m_owningThread, *timeoutTicks, Event_SerialPortIn, eventResult)); + + if (!eventResult) + { + // event timeout + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + } + + if (bytesToRead > 0) + { + // pop the requested bytes from the ring buffer + bytesRead = palUart->RxRingBuffer.Pop(data, bytesToRead); + } + + // pop "hbTimeout" heap block from stack + stack.PopValue(); + + // return how many bytes were read + stack.SetResult_U4(bytesRead); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::ReadExisting___STRING(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart = NULL; + + uint8_t *buffer = NULL; + uint32_t bufferLength; + + CLR_RT_HeapBlock &top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + bufferLength = palUart->RxRingBuffer.Length(); + + if (bufferLength) + { + // there are bytes available in the Rx buffer + // setup read buffer + buffer = (uint8_t *)platform_malloc(bufferLength); + + // sanity check + if (buffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // fill data buffer from Rx buffer + palUart->RxRingBuffer.Pop(buffer, bufferLength); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(top, (const char *)buffer, bufferLength)); + } + else + { + // create an empty + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(top, (const char *)NULL)); + } + + NANOCLR_CLEANUP(); + + if (buffer != NULL) + { + platform_free(buffer); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::ReadLine___STRING(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock hbTimeout; + NF_PAL_UART *palUart = NULL; + + uint8_t *line = NULL; + const char *newLine; + uint32_t newLineLength; + + int64_t *timeoutTicks; + bool eventResult = true; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // setup timeout + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___readTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if (stack.m_customState == 1) + { + // check if there is a full line available to read + if (GetLineFromRxBuffer(pThis, &(palUart->RxRingBuffer), line)) + { + // got one! + eventResult = false; + } + else + { + // get new line from field + newLine = pThis[FIELD___newLine].RecoverString(); + newLineLength = hal_strlen_s(newLine); + // need to subtract one because we are 0 indexed + newLineLength--; + + // set new line char as the last one in the string + // only if this one is found it will have a chance of the others being there + palUart->NewLineChar = newLine[newLineLength]; + + stack.m_customState = 2; + } + } + + while (eventResult) + { + // wait for event + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_SerialPortIn, eventResult)); + + // clear the new line watch char + palUart->NewLineChar = 0; + + if (eventResult) + { + GetLineFromRxBuffer(pThis, &(palUart->RxRingBuffer), line); + + // done here + break; + } + else + { + // event timeout + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop "hbTimeout" heap block from stack + stack.PopValue(); + + // return how many bytes were read + stack.SetResult_String((const char *)line); + + // free memory, if needed + if (line != NULL) + { + platform_free(line); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::Write___VOID__SZARRAY_U1__I4__I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart = NULL; + + CLR_RT_HeapBlock_Array *dataBuffer; + CLR_RT_HeapBlock hbTimeout; + int64_t *timeoutTicks; + bool eventResult = true; + + uint8_t *data; + int32_t length = 0; + int32_t count = 0; + int32_t offset = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // setup timeout + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + + // perform parameter validation and setup TX operation + if (stack.m_customState == 1) + { + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + offset = stack.Arg2().NumericByRef().s4; + count = stack.Arg3().NumericByRef().s4; + + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // check parameters + FAULT_ON_NULL_ARG(dataBuffer); + + if ((offset > length) || (count > length)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + if (offset + count > length) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a the pointer to the array by using the offset + data = dataBuffer->GetElement(offset); + + // push onto the eval stack how many bytes are being pushed to the UART + stack.PushValueI4(count); + + // store pointer + palUart->TxBuffer = data; + + // set TX ongoing count + palUart->TxOngoingCount = count; + + // decrease count for the char we're about to send + palUart->TxOngoingCount--; + + // start sending data + // this will trigger the TX interrupt + palUart->Usart->TXDATA = *palUart->TxBuffer; + + // update buffer pointer + palUart->TxBuffer++; + + // bump custom state + stack.m_customState = 2; + } + + while (eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Tx operation to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_SerialPortOut, eventResult)); + + if (eventResult) + { + // event occurred + // get from the eval stack how many bytes were buffered to Tx + count = stack.m_evalStack[1].NumericByRef().s4; + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop "count" heap block from stack + stack.PopValue(); + + // pop "hbTimeout" heap block from stack + stack.PopValue(); + + stack.SetResult_U4(count); + + // null pointers and vars + pThis = NULL; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeDispose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[FIELD___portIndex].NumericByRef().s4) + { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) + case 1: + UnInit_UART0(); + break; +#endif + +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) + case 2: + UnInit_UART1(); + break; +#endif + +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) + case 3: + UnInit_UART2(); + break; +#endif + +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) + case 4: + UnInit_UART3(); + break; +#endif + +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) + case 5: + UnInit_UART4(); + break; +#endif + +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) + case 6: + UnInit_UART5(); + break; +#endif + + default: + // this COM port is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeInit___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart; + int32_t bufferSize; + uint8_t watchChar; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[FIELD___portIndex].NumericByRef().s4) + { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) + case 1: + palUart = &Uart0_PAL; + break; +#endif +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) + case 2: + InitConfig_USART1(); + palUart = &Uart1_PAL; + break; +#endif +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) + case 3: + palUart = &Uart2_PAL; + break; +#endif +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) + case 4: + palUart = &Uart3_PAL; + break; +#endif +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) + case 5: + palUart = &Uart4_PAL; + break; +#endif +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) + case 6: + palUart = &Uart5_PAL; + break; +#endif + default: + // this COM port is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // alloc buffer memory + bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; + palUart->RxBuffer = (uint8_t *)platform_malloc(bufferSize); + + // sanity check + if (palUart->RxBuffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // init buffer + palUart->RxRingBuffer.Initialize(palUart->RxBuffer, bufferSize); + + // get watch character + watchChar = pThis[FIELD___watchChar].NumericByRef().u1; + + // set watch char, if set + if (watchChar != 0) + { + palUart->WatchChar = watchChar; + } + + // call the configure + return NativeConfig___VOID(stack); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeConfig___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // setup configuration + palUart->UsartInit = USART_INITASYNC_DEFAULT; + + // data bits + // TODO + + // parity + // TODO + + // Check RS485 mode is not selected as currently not supported + if ((SerialMode)pThis[FIELD___mode].NumericByRef().s4 != SerialMode_Normal) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOTIMPL); + } + + // stop bits + + switch ((StopBits)pThis[FIELD___stopBits].NumericByRef().s4) + { + case StopBits_One: + // already set with the above + break; + case StopBits_OnePointFive: + palUart->UsartInit.stopbits = usartStopbits1p5; + break; + case StopBits_Two: + palUart->UsartInit.stopbits = usartStopbits2; + break; + } + + // configure TX, RX signal levels + if (palUart->SignalLevelsInverted) + { + // this driver doesn't support inverted signal levels + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + // baud rate + palUart->UsartInit.baudrate = (int)pThis[FIELD___baudRate].NumericByRef().s4; + + // stop UART, better do this before changing configuration + USART_Reset(palUart->Usart); + + // get pointer to PAL UART + switch ((int)pThis[FIELD___portIndex].NumericByRef().s4) + { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) + case 1: + InitConfig_USART0(); + break; +#endif +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) + case 2: + InitConfig_USART1(); + break; +#endif +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) + case 3: + InitConfig_USART2(); + + break; +#endif +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) + case 4: + InitConfig_USART3(); + + break; +#endif +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) + case 5: + InitConfig_USART4(); + break; +#endif +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) + case 6: + InitConfig_USART5(); + break; +#endif + } + + // null pointers and vars + pThis = NULL; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeSetWatchChar___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // set watch char + palUart->WatchChar = (uint8_t)pThis[FIELD___watchChar].NumericByRef().u1; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeWriteString___VOID__STRING__BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart = NULL; + + CLR_RT_HeapBlock hbTimeout; + int64_t *timeoutTicks; + bool eventResult = true; + + bool isNewAllocation = false; + char *buffer = NULL; + uint32_t bufferLength; + int32_t length = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + if (pThis[FIELD___disposed].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + if (stack.Arg1().RecoverString() == NULL) + { + // text string it's empty so there is noting to do here + stack.SetResult_U4(0); + NANOCLR_SET_AND_LEAVE(S_OK); + } + + // Choose the driver for this SerialDevice + palUart = GetUartPAL((int)pThis[FIELD___portIndex].NumericByRef().s4); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // setup timeout + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + + // perform parameter validation and setup TX operation + if (stack.m_customState == 1) + { + // get buffer to output + NANOCLR_CHECK_HRESULT(SetupWriteLine(stack, &buffer, &bufferLength, &isNewAllocation)); + + // push onto the eval stack how many bytes are being pushed to the UART + stack.PushValueI4(bufferLength); + + // store pointer + palUart->TxBuffer = (uint8_t *)buffer; + + // set TX ongoing count + palUart->TxOngoingCount = bufferLength; + + // decrease count for the char we're about to send + palUart->TxOngoingCount--; + + // start sending data + // this will trigger the TX interrupt + palUart->Usart->TXDATA = *palUart->TxBuffer; + + // update buffer pointer + palUart->TxBuffer++; + + // bump custom state + stack.m_customState = 2; + } + + while (eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Tx operation to complete + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_SerialPortOut, eventResult)); + + if (eventResult) + { + // event occurred + // get from the eval stack how many bytes were buffered to Tx + length = stack.m_evalStack[1].NumericByRef().s4; + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop "length" heap block from stack + stack.PopValue(); + + // pop "hbTimeout" heap block from stack + stack.PopValue(); + + stack.SetResult_U4(length); + + // free memory, if it was allocated + if (isNewAllocation && buffer) + { + platform_free(buffer); + } + + // null pointers and vars + pThis = NULL; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeReceivedBytesThreshold___VOID__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_UART *palUart; + int32_t threshold; + uint8_t portIndex; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // check if threshold is valid + threshold = (int32_t)stack.Arg1().NumericByRef().s4; + + if (threshold <= 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + portIndex = (int)pThis[FIELD___portIndex].NumericByRef().s4; + + // Choose the driver for this SerialDevice + palUart = GetUartPAL(portIndex); + if (palUart == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // update field + pThis[FIELD___receivedBytesThreshold].NumericByRef().s4 = threshold; + + // update threshold value + palUart->ReceivedBytesThreshold = threshold; + + // fake call to event handler in case port is open and the new threshold was set + // to a value lower than the bytes that are already available + if (pThis[FIELD___opened].NumericByRef().u1 && (uint32_t)threshold <= palUart->RxRingBuffer.Length()) + { + ////////////////////////////////// + // Gecko USART index is 0 based // + ////////////////////////////////// + PostManagedEvent(EVENT_SERIAL, 0, portIndex + 1, SerialData_Chars); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::GetDeviceSelector___STATIC__STRING( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // declare the device selector string whose max size is "COM1,COM2,COM3,COM4,COM5,COM6,COM7,COM8," + terminator + // and init with the terminator + static char deviceSelectorString[] = + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) + "COM1," +#endif +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) + "COM2," +#endif +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) + "COM3," +#endif +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) + "COM4," +#endif + +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) + "COM5," +#endif + +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) + "COM6," +#endif + ; + + // replace the last comma with a terminator + if (deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] == ',') + { + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + } + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable + // type (a string here) + stack.SetResult_String(deviceSelectorString); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) +void USART0_RX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartRxHandler(1); +} +void USART0_TX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartTxHandler(1); +} +#endif + +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) +void USART1_RX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartRxHandler(2); +} +void USART1_TX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartTxHandler(2); +} +#endif + +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) +void USART2_RX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartRxHandler(3); +} +void USART2_TX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartTxHandler(3); +} +#endif + +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) +void USART3_RX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartRxHandler(4); +} +void USART3_TX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartTxHandler(4); +} +#endif + +#if (HAL_WP_USE_SERIAL == FALSE) && defined(GECKO_USE_USART4) && (GECKO_USE_USART4 == TRUE) +void USART4_RX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartRxHandler(5); +} +void USART4_TX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartTxHandler(5); +} +#endif + +#if defined(GECKO_USE_USART5) && (GECKO_USE_USART5 == TRUE) +void USART5_RX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartRxHandler(6); +} +void USART5_TX_IRQHandler(void) +{ + // Gecko USART index is 0 based + // need to follow the same index as in the PAL struct + UsartTxHandler(6); +} +#endif diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h new file mode 100644 index 0000000000..af19a935ea --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h @@ -0,0 +1,169 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SYS_IO_SER_NATIVE_TARGET_H +#define SYS_IO_SER_NATIVE_TARGET_H + +#include +#include + +#include +#include +#include + +// set missing defines +#if defined(USART0) +#ifndef GECKO_USE_USART0 +#define GECKO_USE_USART0 FALSE +#endif +#else +#define GECKO_USE_USART0 FALSE +#endif + +#if defined(USART1) +#ifndef GECKO_USE_USART1 +#define GECKO_USE_USART1 FALSE +#endif +#else +#define GECKO_USE_USART1 FALSE +#endif + +#if defined(USART2) +#ifndef GECKO_USE_USART2 +#define GECKO_USE_USART2 FALSE +#endif +#else +#define GECKO_USE_USART2 FALSE +#endif + +#if defined(USART3) +#ifndef GECKO_USE_USART3 +#define GECKO_USE_USART3 FALSE +#endif +#else +#define GECKO_USE_USART3 FALSE +#endif + +#if defined(USART4) +#ifndef GECKO_USE_USART4 +#define GECKO_USE_USART4 FALSE +#endif +#else +#define GECKO_USE_USART4 FALSE +#endif + +#if defined(USART5) +#ifndef GECKO_USE_USART5 +#define GECKO_USE_USART5 FALSE +#endif +#else +#define GECKO_USE_USART5 FALSE +#endif + +// struct representing the UART +typedef struct +{ + USART_TypeDef *Usart; + USART_InitAsync_TypeDef UsartInit; + + uint8_t *TxBuffer; + uint16_t TxOngoingCount; + + HAL_RingBuffer RxRingBuffer; + uint8_t *RxBuffer; + uint16_t RxBytesToRead; + + uint8_t WatchChar; + uint8_t NewLineChar; + uint32_t ReceivedBytesThreshold; + + bool SignalLevelsInverted; + +} NF_PAL_UART; + +//////////////////////////////////////////// +// declaration of the the UART PAL strucs // +//////////////////////////////////////////// +#if defined(GECKO_USE_USART0) && (GECKO_USE_USART0 == TRUE) +extern NF_PAL_UART Uart0_PAL; +#endif +#if defined(GECKO_USE_USART1) && (GECKO_USE_USART1 == TRUE) +extern NF_PAL_UART Uart1_PAL; +#endif +#if defined(GECKO_USE_USART2) && (GECKO_USE_USART2 == TRUE) +extern NF_PAL_UART Uart2_PAL; +#endif +#if defined(GECKO_USE_USART3) && (GECKO_USE_USART3 == TRUE) +extern NF_PAL_UART Uart3_PAL; +#endif +#if defined(GECKO_USE_USART_UART4) && (GECKO_USE_USART_UART4 == TRUE) +extern NF_PAL_UART Uart4_PAL; +#endif +#if defined(GECKO_USE_USART_UART5) && (GECKO_USE_USART_UART5 == TRUE) +extern NF_PAL_UART Uart5_PAL; +#endif + +// the following macro defines a function that configures the GPIO pins for a Gecko USART +// it gets called in the System_IO_Ports_SerialPort::NativeConfig function +// this is required because the UART/USART peripherals can use multiple GPIO configuration combinations +#define UART_INIT_CONFIG(num, gpio_port_tx, tx_pin, tx_location, gpio_port_rx, rx_pin, rx_location) \ + void InitConfig_USART##num() \ + { \ + CMU_ClockEnable(cmuClock_USART##num, true); \ + GPIO_PinModeSet(gpio_port_rx, rx_pin, gpioModeInput, 0); \ + GPIO_PinModeSet(gpio_port_tx, tx_pin, gpioModePushPull, 1); \ + USART_InitAsync(USART##num, &Uart##num##_PAL.UsartInit); \ + NVIC_ClearPendingIRQ(USART##num##_RX_IRQn); \ + NVIC_EnableIRQ(USART##num##_RX_IRQn); \ + NVIC_ClearPendingIRQ(USART##num##_TX_IRQn); \ + NVIC_EnableIRQ(USART##num##_TX_IRQn); \ + Uart##num##_PAL.Usart = USART##num; \ + USART##num->ROUTELOC0 = rx_location | tx_location; \ + USART##num->ROUTEPEN |= USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN; \ + Uart##num##_PAL.TxBuffer = NULL; \ + Uart##num##_PAL.TxOngoingCount = 0; \ + Uart##num##_PAL.RxBuffer = NULL; \ + Uart##num##_PAL.WatchChar = 0; \ + Uart##num##_PAL.NewLineChar = 0; \ + Uart##num##_PAL.SignalLevelsInverted = false; \ + } + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// when a UART/USART is defined the declarations below will have the real function/configuration +// in the target folder @ target_system_io_ports_config.cpp +/////////////////////////////////////////////////////////////////////////////////////////////////// +void InitConfig_USART0(); +void InitConfig_USART1(); +void InitConfig_USART2(); +void InitConfig_USART3(); +void InitConfig_USART4(); +void InitConfig_USART5(); + +// the following macro defines a function that un initializes an UART struct +// it gets called in the System_IO_Ports_SerialPort::NativeDispose function +#define UART_UNINIT(num, gpio_port_tx, tx_pin, tx_location, gpio_port_rx, rx_pin, rx_location) \ + void UnInit_UART##num() \ + { \ + USART_Reset(USART##num); \ + GPIO_PinModeSet(gpio_port_rx, rx_pin, gpioModeDisabled, 0); \ + GPIO_PinModeSet(gpio_port_tx, tx_pin, gpioModeDisabled, 0); \ + CMU_ClockEnable(cmuClock_USART##num, false); \ + platform_free(Uart##num##_PAL.RxBuffer); \ + Uart##num##_PAL.TxBuffer = NULL; \ + Uart##num##_PAL.RxBuffer = NULL; \ + Uart##num##_PAL.Usart = NULL; \ + return; \ + } + +// when a UART/USART is defined the declarations below will have the real function/configuration +// in the target folder @ target_system_io_ports_config.cpp +void UnInit_UART0(); +void UnInit_UART1(); +void UnInit_UART2(); +void UnInit_UART3(); +void UnInit_UART4(); +void UnInit_UART5(); + +#endif // SYS_IO_SER_NATIVE_TARGET_H From 9e073ed850044546c8abeba3b32ab64c686c534c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 27 Oct 2022 14:35:29 +0100 Subject: [PATCH 266/572] Add empty Sys.IO.Ports config --- .../SKY_EEVB_PROTO1/target_system_io_ports_config.cpp | 4 ++++ .../SKY_EEVB_PROTO1/target_system_io_ports_config.h | 5 +++++ 2 files changed, 9 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + From 30c11a56fe474f31283220684f4e7dd46ecdbd74 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 27 Oct 2022 14:35:57 +0100 Subject: [PATCH 267/572] Fix includes for sys.io.ports native --- .../_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h index af19a935ea..e6952c319c 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_target.h @@ -10,8 +10,8 @@ #include #include -#include -#include +#include +#include // set missing defines #if defined(USART0) From da999a72fa360f60dc15e1d2fac0991d481c3fbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 28 Oct 2022 17:54:35 +0100 Subject: [PATCH 268/572] Revert changes in USDB config --- .../SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h index f5e936cd19..debd4df8ef 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h @@ -182,11 +182,11 @@ extern char UsbClassVendorDescription[32 + 1]; // Number of class instances <1-255> // Number of class instances. -#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 1 +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 // Number of configurations <1-255> // Number of configurations. -#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 // pointer to USB Class Vendor description #define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription From 616722893fc6ebbdde698960431b5bf808fae54c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 28 Oct 2022 17:55:22 +0100 Subject: [PATCH 269/572] Add nano implementation of Gecko USB Class Vendor --- CMake/Modules/FindGecko_SDK.cmake | 25 +- .../_common/nano_sl_usbd_class_vendor.c | 1379 +++++++++++++++++ .../_include/nano_sl_usbd_class_vendor.h | 428 +++++ 3 files changed, 1810 insertions(+), 22 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c create mode 100644 targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 2555bc9fb6..8ecb3ca2cc 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -193,7 +193,8 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) list(APPEND gecko_sdk_srcs sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) - list(APPEND gecko_sdk_srcs sl_usbd_class_vendor.c) + # this one is our own implementation + list(APPEND gecko_sdk_srcs nano_sl_usbd_class_vendor.c) list(APPEND gecko_sdk_srcs sl_usbd_init.c) list(APPEND gecko_sdk_srcs sl_malloc.c) @@ -259,7 +260,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_hid_report.c PROPERTIES COMPILE_FLAGS -Wno-undef) - SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c PROPERTIES COMPILE_FLAGS -Wno-undef) + SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_driver_dwc_otg_fs.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_init.c PROPERTIES COMPILE_FLAGS -Wno-undef) @@ -270,26 +271,6 @@ else() message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") endif() -################################################################### -# change required to define the description of the USB Vendor Class -if(GECKO_FEATURE_USBD_WINUSB) - file(READ - ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - SL_USBD_CLASS_VENDOR_CONTENT) - - - string(REPLACE - "\"Vendor-specific class\"" - NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION - SL_USBD_CLASS_VENDOR_NEW_CONTENTS - "${SL_USBD_CLASS_VENDOR_CONTENT}") - - file(WRITE - ${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_vendor.c - "${SL_USBD_CLASS_VENDOR_NEW_CONTENTS}") - -endif() - include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Gecko_SDK DEFAULT_MSG Gecko_SDK_INCLUDE_DIRS Gecko_SDK_SOURCES) diff --git a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c new file mode 100644 index 0000000000..ce1a3b4955 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c @@ -0,0 +1,1379 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// This is an extension to the original file from Gecko SDK v4.1.1 +// Following Support Case #00293097 with Silabs, we where advised to add the missing +// APIs to our own implementation. In case these are ever made available in the +// official SDK, this file should be removed and the original one should be used. +// There is also a change to allow changing the USB Vendor Class description, by replacing +// the hardcoded "Vendor-specific class" with a custom one. Suggestion to improve this has +// been made to Silabs (Support Case #00292362). + +/******************************************************************************************************** + ******************************************************************************************************** + * INCLUDE FILES + ******************************************************************************************************** + *******************************************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include + +// clang-format off + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL DEFINES + ******************************************************************************************************** + *******************************************************************************************************/ + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL DATA TYPES + ******************************************************************************************************** + *******************************************************************************************************/ + +/******************************************************************************************************** + * FORWARD DECLARATIONS + *******************************************************************************************************/ + +typedef struct sli_usbd_vendor_ctrl sli_usbd_vendor_ctrl_t; + +/******************************************************************************************************** + * VENDOR CLASS STATES + *******************************************************************************************************/ + +SL_ENUM(sli_usbd_vendor_state_t) { + SLI_USBD_VENDOR_STATE_NONE = 0, + SLI_USBD_VENDOR_STATE_INIT, + SLI_USBD_VENDOR_STATE_CONFIG +}; + +/******************************************************************************************************** + * VENDOR CLASS EP REQUIREMENTS DATA TYPE + *******************************************************************************************************/ + +// Vendor class comm info +typedef struct { + // Ptr to ctrl info. + sli_usbd_vendor_ctrl_t *ctrl_ptr; + // Avail EP for comm: Bulk (and Intr) + uint8_t data_bulk_in_endpoint_address; + uint8_t data_bulk_out_endpoint_address; + uint8_t interrupt_in_endpoint_address; + uint8_t interrupt_out_endpoint_address; + + bool data_bulk_in_active_transfer; + bool data_bulk_out_active_transfer; + bool interrupt_in_active_transfer; + bool interrupt_out_active_transfer; +} sli_usbd_vendor_comm_t; + +// Vendor Class Ctrl Info +struct sli_usbd_vendor_ctrl { + sli_usbd_vendor_state_t state; ///< Vendor class state. + uint8_t class_nbr; ///< Vendor class instance nbr. + sli_usbd_vendor_comm_t *comm_ptr; ///< Vendor class comm info ptr. + bool interrupt_enable; ///< Intr IN & OUT EPs en/dis flag. + uint16_t interrupt_interval; ///< Polling interval for intr IN & OUT EPs. + sl_usbd_vendor_callbacks_t *callback_ptr; ///< Ptr to app callback for vendor-specific req. + sl_usbd_vendor_async_function_t bulk_read_async_function; ///< Ptr to callback used for async comm. + void *bulk_read_async_arg_ptr; ///< Ptr to extra arg used for async comm. + sl_usbd_vendor_async_function_t bulk_write_async_function; ///< Ptr to callback used for async comm. + void *bulk_write_async_arg_ptr; ///< Ptr to extra arg used for async comm. + sl_usbd_vendor_async_function_t interrupt_read_async_function; ///< Ptr to callback used for async comm. + void *interrupt_read_async_arg_ptr; ///< Ptr to extra arg used for async comm. + sl_usbd_vendor_async_function_t interrupt_write_async_function; ///< Ptr to callback used for async comm. + void *interrupt_write_async_arg_ptr; ///< Ptr to extra arg used for async comm. +#if (USBD_CFG_MS_OS_DESC_EN == 1) // Microsoft ext properties. + sl_usbd_microsoft_ext_property_t microsoft_ext_property_table[SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY]; + uint8_t interface_number; // Interface number associated with class instance + uint8_t microsoft_ext_property_next; +#endif +}; + +// Vendor Class Root Struct +typedef struct { + sli_usbd_vendor_ctrl_t ctrl_table[SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY]; ///< Vendor class ctrl array. + uint8_t ctrl_nbr_next; + sli_usbd_vendor_comm_t comm_tbl[SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY * SL_USBD_VENDOR_CONFIGURATION_QUANTITY]; ///< Vendor class comm array. + uint8_t comm_nbr_next; +} sli_usbd_vendor_t; + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL CONSTANTS + ******************************************************************************************************** + *******************************************************************************************************/ + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL GLOBAL VARIABLES + ******************************************************************************************************** + *******************************************************************************************************/ + +static sli_usbd_vendor_t usbd_vendor; + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL FUNCTION PROTOTYPES + ******************************************************************************************************** + *******************************************************************************************************/ + +static void usbd_vendor_enable(uint8_t config_nbr, + void *p_if_class_arg); + +static void usbd_vendor_disable(uint8_t config_nbr, + void *p_if_class_arg); + +static bool usbd_vendor_request_handler(const sl_usbd_setup_req_t *p_setup_req, + void *p_if_class_arg); + +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static uint8_t usbd_vendor_get_microsoft_compat_id(uint8_t *p_sub_compat_id_ix); + +static uint8_t usbd_vendor_get_microsoft_ext_property_table(sl_usbd_microsoft_ext_property_t **pp_ext_property_tbl, uint8_t if_no); +#endif + +static void usbd_vendor_read_bulk_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status); + +static void usbd_vendor_write_bulk_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status); + +static void usbd_vendor_read_interrupt_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status); + +static void usbd_vendor_write_interrupt_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status); + +/******************************************************************************************************** + * VENDOR CLASS DRIVER + *******************************************************************************************************/ + +static sl_usbd_class_driver_t usbd_vendor_driver = { + usbd_vendor_enable, + usbd_vendor_disable, + NULL, // Vendor does NOT use alternate interface(s). + NULL, + NULL, // Vendor does NOT use functional EP desc. + NULL, + NULL, // Vendor does NOT use functional IF desc. + NULL, + NULL, // Vendor does NOT handle std req with IF recipient. + NULL, // Vendor does NOT define class-specific req. + usbd_vendor_request_handler, + +#if (USBD_CFG_MS_OS_DESC_EN == 1) + usbd_vendor_get_microsoft_compat_id, + usbd_vendor_get_microsoft_ext_property_table, +#endif +}; + +/******************************************************************************************************** + ******************************************************************************************************** + * GLOBAL FUNCTIONS + ******************************************************************************************************** + *******************************************************************************************************/ + +/****************************************************************************************************//** + * Initializes the internal structures and variables used by the Vendor class + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_init(void) +{ + uint8_t ix; + sli_usbd_vendor_ctrl_t *p_ctrl; + sli_usbd_vendor_comm_t *p_comm; + + usbd_vendor.ctrl_nbr_next = SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY; + usbd_vendor.comm_nbr_next = SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY * SL_USBD_VENDOR_CONFIGURATION_QUANTITY; + + // Init vendor class struct. + for (ix = 0u; ix < usbd_vendor.ctrl_nbr_next; ix++) { + p_ctrl = &usbd_vendor.ctrl_table[ix]; + p_ctrl->state = SLI_USBD_VENDOR_STATE_NONE; + p_ctrl->class_nbr = SL_USBD_CLASS_NBR_NONE; + p_ctrl->comm_ptr = NULL; + p_ctrl->interrupt_enable = false; + p_ctrl->interrupt_interval = 0u; + p_ctrl->callback_ptr = NULL; + p_ctrl->bulk_read_async_function = NULL; + p_ctrl->bulk_read_async_arg_ptr = NULL; + p_ctrl->bulk_write_async_function = NULL; + p_ctrl->bulk_write_async_arg_ptr = NULL; + p_ctrl->interrupt_read_async_function = NULL; + p_ctrl->interrupt_read_async_arg_ptr = NULL; + p_ctrl->interrupt_write_async_function = NULL; + p_ctrl->interrupt_write_async_arg_ptr = NULL; + +#if (USBD_CFG_MS_OS_DESC_EN == 1) + p_ctrl->microsoft_ext_property_next = 0u; + + memset(p_ctrl->microsoft_ext_property_table, 0, sizeof(sl_usbd_microsoft_ext_property_t) * SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY); +#endif + } + + // Init vendor EP tbl. + for (ix = 0u; ix < usbd_vendor.comm_nbr_next; ix++) { + p_comm = &usbd_vendor.comm_tbl[ix]; + p_comm->ctrl_ptr = NULL; + p_comm->data_bulk_in_endpoint_address = SL_USBD_ENDPOINT_ADDR_NONE; + p_comm->data_bulk_out_endpoint_address = SL_USBD_ENDPOINT_ADDR_NONE; + p_comm->interrupt_in_endpoint_address = SL_USBD_ENDPOINT_ADDR_NONE; + p_comm->interrupt_out_endpoint_address = SL_USBD_ENDPOINT_ADDR_NONE; + + p_comm->data_bulk_in_active_transfer = false; + p_comm->data_bulk_out_active_transfer = false; + p_comm->interrupt_in_active_transfer = false; + p_comm->interrupt_out_active_transfer = false; + } + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Adds a new instance of the Vendor class + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_create_instance(bool intr_en, + uint16_t interval, + sl_usbd_vendor_callbacks_t *p_vendor_callbacks, + uint8_t *p_class_nbr) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + uint8_t vendor_class_nbr; + CORE_DECLARE_IRQ_STATE; + + if (p_class_nbr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (intr_en == true) { + // interval must be a power of 2. + if (SLI_USBD_IS_PWR2(interval) != true) { + *p_class_nbr = SL_USBD_CLASS_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + } + + CORE_ENTER_ATOMIC(); + // Chk if max nbr of instances reached. + if (usbd_vendor.ctrl_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_class_nbr = SL_USBD_CLASS_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + + // Next avail vendor class instance nbr. + usbd_vendor.ctrl_nbr_next--; + // Alloc new vendor class instance nbr. + vendor_class_nbr = usbd_vendor.ctrl_nbr_next; + CORE_EXIT_ATOMIC(); + + p_ctrl = &usbd_vendor.ctrl_table[vendor_class_nbr]; // Get vendor class instance. + // Store vendor class instance info. + p_ctrl->interrupt_enable = intr_en; // Intr EPs en/dis. + p_ctrl->interrupt_interval = interval; // Polling interval for intr EPs. + p_ctrl->callback_ptr = p_vendor_callbacks; // App callback for vendor-specific req. + + *p_class_nbr = vendor_class_nbr; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Creates a new instance of the Vendor class + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_add_to_configuration(uint8_t class_nbr, + uint8_t config_nbr) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + sli_usbd_vendor_comm_t *p_comm; + uint8_t if_nbr; + uint8_t ep_addr; + uint16_t comm_nbr; + uint16_t intr_interval; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get vendor class instance. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + CORE_ENTER_ATOMIC(); + + if (usbd_vendor.comm_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_ALLOCATION_FAILED; + } + + // Alloc new vendor class comm info nbr. + comm_nbr = usbd_vendor.comm_nbr_next - 1u; + // Next avail vendor class comm info nbr. + usbd_vendor.comm_nbr_next--; + CORE_EXIT_ATOMIC(); + + // Get vendor class comm info. + p_comm = &usbd_vendor.comm_tbl[comm_nbr]; + + // Config Desc Construction + // See Note #2. + // Add vendor IF desc to config desc. + // .NET nanoFramework change: replace hardcoded USB Vendor Class description with one from the configuration + status = sl_usbd_core_add_interface(config_nbr, + &usbd_vendor_driver, + (void *)p_comm, + NULL, + SL_USBD_CLASS_CODE_VENDOR_SPECIFIC, + SL_USBD_SUBCLASS_CODE_VENDOR_SPECIFIC, + SL_USBD_PROTOCOL_CODE_VENDOR_SPECIFIC, + // [NF_CHANGE] + NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION, + // [END_NF_CHANGE] + &if_nbr); + if (status != SL_STATUS_OK) { + return status; + } + + // Microsoft ext properties. +#if (USBD_CFG_MS_OS_DESC_EN == 1) + p_ctrl->interface_number = if_nbr; +#endif + + // Add bulk IN EP desc. + status = sl_usbd_core_add_bulk_endpoint(config_nbr, + if_nbr, + 0u, + true, + 0u, + &ep_addr); + if (status != SL_STATUS_OK) { + return status; + } + + // Store bulk IN EP addr. + p_comm->data_bulk_in_endpoint_address = ep_addr; + + // Add bulk OUT EP desc. + status = sl_usbd_core_add_bulk_endpoint(config_nbr, + if_nbr, + 0u, + false, + 0u, + &ep_addr); + if (status != SL_STATUS_OK) { + return status; + } + + // Store bulk OUT EP addr. + p_comm->data_bulk_out_endpoint_address = ep_addr; + + if (p_ctrl->interrupt_enable == true) { + if (SL_IS_BIT_CLEAR(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT) == true) { + // In FS, bInterval in frames. + intr_interval = p_ctrl->interrupt_interval; + } else { + // In HS, bInterval in microframes. + intr_interval = p_ctrl->interrupt_interval * 8u; + } + + // Add intr IN EP desc. + status = sl_usbd_core_add_interrupt_endpoint(config_nbr, + if_nbr, + 0u, + true, + 0u, + intr_interval, + &ep_addr); + if (status != SL_STATUS_OK) { + return status; + } + + // Store intr IN EP addr. + p_comm->interrupt_in_endpoint_address = ep_addr; + + // Add intr OUT EP desc. + status = sl_usbd_core_add_interrupt_endpoint(config_nbr, + if_nbr, + 0u, + false, + 0u, + intr_interval, + &ep_addr); + if (status != SL_STATUS_OK) { + return status; + } + + // Store intr OUT EP addr. + p_comm->interrupt_out_endpoint_address = ep_addr; + } + // Store vendor class instance info. + CORE_ENTER_ATOMIC(); + // Set class instance to init state. + p_ctrl->state = SLI_USBD_VENDOR_STATE_INIT; + p_ctrl->class_nbr = class_nbr; + p_ctrl->comm_ptr = NULL; + CORE_EXIT_ATOMIC(); + + // Save ref to vendor class instance ctrl struct. + p_comm->ctrl_ptr = p_ctrl; + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Gets the vendor class enable state + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, + bool *p_enabled) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + sl_usbd_device_state_t state; + sl_status_t status; + + // TODO validate class_nbr + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + // Get dev state. + status = sl_usbd_core_get_device_state(&state); + + if ((status == SL_STATUS_OK) + && (state == SL_USBD_DEVICE_STATE_CONFIGURED) + && (p_ctrl->state == SLI_USBD_VENDOR_STATE_CONFIG)) { + *p_enabled = true; + } else { + *p_enabled = false; + } + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Adds a Microsoft OS extended property to this vendor class instance + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +sl_status_t sl_usbd_vendor_add_microsoft_ext_property(uint8_t class_nbr, + uint8_t property_type, + const uint8_t *p_property_name, + uint16_t property_name_len, + const uint8_t *p_property, + uint32_t property_len) +{ + uint8_t ext_property_nbr; + sli_usbd_vendor_ctrl_t *p_ctrl; + sl_usbd_microsoft_ext_property_t *p_ext_property; + CORE_DECLARE_IRQ_STATE; + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (!((property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ) + || (property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_EXPAND_SZ) + || (property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_BINARY) + || (property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_DWORD_LITTLE_ENDIAN) + || (property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_DWORD_BIG_ENDIAN) + || (property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_LINK) + || (property_type == SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_MULTI_SZ))) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((p_property_name == NULL) && (property_name_len != 0u)) { + return SL_STATUS_NULL_POINTER; + } + + if ((p_property == NULL) && (property_len != 0u)) { + return SL_STATUS_NULL_POINTER; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + CORE_ENTER_ATOMIC(); + ext_property_nbr = p_ctrl->microsoft_ext_property_next; + +#if (RTOS_ARG_CHK_EXT_EN == 1) + if (ext_property_nbr >= SL_USBD_VENDOR_MS_EXTENDED_PROPERTIES_QUANTITY) { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_ALLOCATION_FAILED; + } +#endif + p_ctrl->microsoft_ext_property_next++; + + p_ext_property = &p_ctrl->microsoft_ext_property_table[ext_property_nbr]; + + p_ext_property->property_type = property_type; + p_ext_property->property_name_ptr = p_property_name; + p_ext_property->property_name_len = property_name_len; + p_ext_property->property_ptr = p_property; + p_ext_property->property_len = property_len; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * Receive the data from the host through the Bulk OUT endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_bulk_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + uint32_t xfer_len; + bool conn; + sl_status_t status; + + if (p_xfer_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if ((p_buf == NULL) && (buf_len != 0u)) { + *p_xfer_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + status = sl_usbd_core_read_bulk_sync(p_ctrl->comm_ptr->data_bulk_out_endpoint_address, + p_buf, + buf_len, + timeout, + &xfer_len); + + if (status != SL_STATUS_OK) { + *p_xfer_len = 0; + return status; + } + + *p_xfer_len = xfer_len; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Sends the data to host through Bulk IN endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_bulk_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + bool end, + uint32_t *p_xfer_len) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + uint32_t xfer_len; + bool conn; + sl_status_t status; + + if (p_xfer_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if ((p_buf == NULL) && (buf_len != 0u)) { + *p_xfer_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + status = sl_usbd_core_write_bulk_sync(p_ctrl->comm_ptr->data_bulk_in_endpoint_address, + p_buf, + buf_len, + timeout, + end, + &xfer_len); + + if (status != SL_STATUS_OK) { + *p_xfer_len = 0; + return status; + } + + *p_xfer_len = xfer_len; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Receive the data from the host through the Bulk OUT endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_bulk_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + bool conn; + sl_status_t status; + + if ((p_buf == NULL) && (buf_len != 0u)) { + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + p_ctrl->bulk_read_async_function = async_fnct; + p_ctrl->bulk_read_async_arg_ptr = p_async_arg; + + // Check if another xfer is already in progress. + if (p_ctrl->comm_ptr->data_bulk_out_active_transfer == false) { + // Indicate that a xfer is in progress. + p_ctrl->comm_ptr->data_bulk_out_active_transfer = true; + status = sl_usbd_core_read_bulk_async(p_ctrl->comm_ptr->data_bulk_out_endpoint_address, + p_buf, + buf_len, + usbd_vendor_read_bulk_async_complete, + (void *)p_ctrl); + if (status != SL_STATUS_OK) { + p_ctrl->comm_ptr->data_bulk_out_active_transfer = false; + } + } else { + status = SL_STATUS_NOT_READY; + } + + return status; +} + +/****************************************************************************************************//** + * Sends the data to host through the Bulk IN endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_bulk_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg, + bool end) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + bool conn; + sl_status_t status; + + if ((p_buf == NULL) && (buf_len != 0u)) { + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + p_ctrl->bulk_write_async_function = async_fnct; + p_ctrl->bulk_write_async_arg_ptr = p_async_arg; + + // Check if another xfer is already in progress. + if (p_ctrl->comm_ptr->data_bulk_in_active_transfer == false) { + // Indicate that a xfer is in progress. + p_ctrl->comm_ptr->data_bulk_in_active_transfer = true; + status = sl_usbd_core_write_bulk_async(p_ctrl->comm_ptr->data_bulk_in_endpoint_address, + p_buf, + buf_len, + usbd_vendor_write_bulk_async_complete, + (void *)p_ctrl, + end); + if (status != SL_STATUS_OK) { + p_ctrl->comm_ptr->data_bulk_in_active_transfer = false; + } + } else { + status = SL_STATUS_NOT_READY; + } + + return status; +} + +/****************************************************************************************************//** + * Receives the data from the host through the Interrupt OUT endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_interrupt_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + uint32_t xfer_len; + bool conn; + sl_status_t status; + + if (p_xfer_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if ((p_buf == NULL) && (buf_len != 0u)) { + *p_xfer_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + status = sl_usbd_core_read_interrupt_sync(p_ctrl->comm_ptr->interrupt_out_endpoint_address, + p_buf, + buf_len, + timeout, + &xfer_len); + + if (status != SL_STATUS_OK) { + *p_xfer_len = 0; + return status; + } + + *p_xfer_len = xfer_len; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Sends data to the host through the Interrupt IN endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_interrupt_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + bool end, + uint32_t *p_xfer_len) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + uint32_t xfer_len; + bool conn; + sl_status_t status; + + if (p_xfer_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if ((p_buf == NULL) && (buf_len != 0u)) { + *p_xfer_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + *p_xfer_len = 0; + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + status = sl_usbd_core_write_interrupt_sync(p_ctrl->comm_ptr->interrupt_in_endpoint_address, + p_buf, + buf_len, + timeout, + end, + &xfer_len); + + if (status != SL_STATUS_OK) { + *p_xfer_len = 0; + return status; + } + + *p_xfer_len = xfer_len; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Receives the data from the host through Interrupt OUT endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_interrupt_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + bool conn; + sl_status_t status; + + if ((p_buf == NULL) && (buf_len != 0u)) { + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + p_ctrl->interrupt_read_async_function = async_fnct; + p_ctrl->interrupt_read_async_arg_ptr = p_async_arg; + + // Check if another xfer is already in progress. + if (p_ctrl->comm_ptr->interrupt_out_active_transfer == false) { + // Indicate that a xfer is in progres. + p_ctrl->comm_ptr->interrupt_out_active_transfer = true; + status = sl_usbd_core_read_interrupt_async(p_ctrl->comm_ptr->interrupt_out_endpoint_address, + p_buf, + buf_len, + usbd_vendor_read_interrupt_async_complete, + (void *)p_ctrl); + if (status != SL_STATUS_OK) { + p_ctrl->comm_ptr->interrupt_out_active_transfer = false; + } + } else { + status = SL_STATUS_NOT_READY; + } + + return status; +} + +/****************************************************************************************************//** + * Sends the data to the host through the Interrupt IN endpoint + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_interrupt_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg, + bool end) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + bool conn; + sl_status_t status; + + if ((p_buf == NULL) && (buf_len != 0u)) { + return SL_STATUS_NULL_POINTER; + } + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_usbd_vendor_is_enabled(class_nbr, &conn); + + // Chk class state. + if (conn != true) { + return SL_STATUS_INVALID_STATE; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + p_ctrl->interrupt_write_async_function = async_fnct; + p_ctrl->interrupt_write_async_arg_ptr = p_async_arg; + + // Check if another xfer is already in progress. + if (p_ctrl->comm_ptr->interrupt_in_active_transfer == false) { + // Indicate that a xfer is in progress. + p_ctrl->comm_ptr->interrupt_in_active_transfer = true; + status = sl_usbd_core_write_interrupt_async(p_ctrl->comm_ptr->interrupt_in_endpoint_address, + p_buf, + buf_len, + usbd_vendor_write_interrupt_async_complete, + (void *)p_ctrl, + end); + if (status != SL_STATUS_OK) { + p_ctrl->comm_ptr->interrupt_in_active_transfer = false; + } + } else { + status = SL_STATUS_NOT_READY; + } + + return status; +} + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL FUNCTIONS + ******************************************************************************************************** + *******************************************************************************************************/ + +/****************************************************************************************************//** + * usbd_vendor_enable() + * + * @brief Notify class that configuration is active. + * + * @param config_nbr Configuration index to add the interface to. + * + * @param p_if_class_arg Pointer to class argument. + *******************************************************************************************************/ +static void usbd_vendor_enable(uint8_t config_nbr, + void *p_if_class_arg) +{ + sli_usbd_vendor_comm_t *p_comm; + sli_usbd_vendor_ctrl_t *p_ctrl; + CORE_DECLARE_IRQ_STATE; + + (void)&config_nbr; + + p_comm = (sli_usbd_vendor_comm_t *)p_if_class_arg; + p_ctrl = p_comm->ctrl_ptr; + + CORE_ENTER_ATOMIC(); + p_ctrl->comm_ptr = p_comm; + p_ctrl->state = SLI_USBD_VENDOR_STATE_CONFIG; + CORE_EXIT_ATOMIC(); + + if (p_ctrl->callback_ptr != NULL && p_ctrl->callback_ptr->enable != NULL) { + p_ctrl->callback_ptr->enable(p_ctrl->class_nbr); + } +} + +/****************************************************************************************************//** + * usbd_vendor_disable() + * + * @brief Notify class that configuration is not active. + * + * @param config_nbr Configuration index to add the interface. + * + * @param p_if_class_arg Pointer to class argument. + *******************************************************************************************************/ +static void usbd_vendor_disable(uint8_t config_nbr, + void *p_if_class_arg) +{ + sli_usbd_vendor_comm_t *p_comm; + sli_usbd_vendor_ctrl_t *p_ctrl; + CORE_DECLARE_IRQ_STATE; + + (void)&config_nbr; + + p_comm = (sli_usbd_vendor_comm_t *)p_if_class_arg; + p_ctrl = p_comm->ctrl_ptr; + + CORE_ENTER_ATOMIC(); + p_comm->ctrl_ptr->state = SLI_USBD_VENDOR_STATE_INIT; + CORE_EXIT_ATOMIC(); + + if (p_ctrl->callback_ptr != NULL && p_ctrl->callback_ptr->disable != NULL) { + p_ctrl->callback_ptr->disable(p_ctrl->class_nbr); + } +} + +/****************************************************************************************************//** + * usbd_vendor_request_handler() + * + * @brief Process vendor-specific request. + * + * @param p_setup_req Pointer to setup request structure. + * + * @param p_if_class_arg Pointer to class argument passed to sl_usbd_core_add_interface(). + * + * @return true, if vendor-specific request successfully processed. + * + * false, otherwise. + *******************************************************************************************************/ +static bool usbd_vendor_request_handler(const sl_usbd_setup_req_t *p_setup_req, + void *p_if_class_arg) +{ + sli_usbd_vendor_comm_t *p_comm; + sli_usbd_vendor_ctrl_t *p_ctrl; + bool valid; + + p_comm = (sli_usbd_vendor_comm_t *)p_if_class_arg; + p_ctrl = p_comm->ctrl_ptr; + + if (p_ctrl->callback_ptr != NULL && p_ctrl->callback_ptr->setup_req != NULL) { + p_ctrl->callback_ptr->setup_req(p_ctrl->class_nbr, p_setup_req); + valid = true; + } else { + valid = false; + } + + return (valid); +} + +/****************************************************************************************************//** + * usbd_vendor_get_microsoft_compat_id() + * + * @brief Returns Microsoft descriptor compatible id. + * + * @param p_sub_compat_id_ix Pointer to the variable that will receive subcompatible id. + * + * @return Compatible id. + * + * false, otherwise. + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static uint8_t usbd_vendor_get_microsoft_compat_id(uint8_t *p_sub_compat_id_ix) +{ + *p_sub_compat_id_ix = SL_USBD_MICROSOFT_SUBCOMPAT_ID_NULL; + + return (SL_USBD_MICROSOFT_COMPAT_ID_WINUSB); +} +#endif + +/****************************************************************************************************//** + * usbd_vendor_get_microsoft_ext_property_table() + * + * @brief Returns Microsoft descriptor extended properties table. + * + * @param pp_ext_property_tbl Pointer to the variable that will receive the Microsoft extended + * properties table. + * + * @param interface_number Interface number + * + * @return Number of Microsoft extended properties in table. + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static uint8_t usbd_vendor_get_microsoft_ext_property_table(sl_usbd_microsoft_ext_property_t **pp_ext_property_tbl, + uint8_t interface_number) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + + for (int i = 0; i < SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY; i++) { + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[i]; + if (p_ctrl->interface_number == interface_number) { + *pp_ext_property_tbl = p_ctrl->microsoft_ext_property_table; + // Only one extended property (GUID) supported. + return (p_ctrl->microsoft_ext_property_next); + } + } + // no extended properties table has been set + return 0; +} +#endif + +/****************************************************************************************************//** + * usbd_vendor_read_bulk_async_complete() + * + * @brief Inform the application about the Bulk OUT transfer completion. + * + * @param ep_addr Endpoint address. + * + * @param p_buf Pointer to the receive buffer. + * + * @param buf_len Receive buffer length. + * + * @param xfer_len Number of octets received. + * + * @param p_arg Additional argument provided by application. + * + * @param status Transfer status: success or error. + *******************************************************************************************************/ +static void usbd_vendor_read_bulk_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + void *p_callback_arg; + + (void)&ep_addr; + + // Get Vendor class instance ctrl struct. + p_ctrl = (sli_usbd_vendor_ctrl_t *)p_arg; + p_callback_arg = p_ctrl->bulk_read_async_arg_ptr; + + // Xfer finished, no more active xfer. + p_ctrl->comm_ptr->data_bulk_out_active_transfer = false; + // Call app callback to inform about xfer completion. + p_ctrl->bulk_read_async_function(p_ctrl->class_nbr, + p_buf, + buf_len, + xfer_len, + p_callback_arg, + status); +} + +/****************************************************************************************************//** + * usbd_vendor_write_bulk_async_complete() + * + * @brief Inform the application about the Bulk IN transfer completion. + * + * @param ep_addr Endpoint address. + * + * @param p_buf Pointer to the transmit buffer. + * + * @param buf_len Transmit buffer length. + * + * @param xfer_len Number of octets sent. + * + * @param p_arg Additional argument provided by application. + * + * @param status Transfer status: success or error. + *******************************************************************************************************/ +static void usbd_vendor_write_bulk_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + void *p_callback_arg; + + (void)&ep_addr; + + // Get Vendor class instance ctrl struct. + p_ctrl = (sli_usbd_vendor_ctrl_t *)p_arg; + p_callback_arg = p_ctrl->bulk_write_async_arg_ptr; + + // Xfer finished, no more active xfer. + p_ctrl->comm_ptr->data_bulk_in_active_transfer = false; + // Call app callback to inform about xfer completion. + p_ctrl->bulk_write_async_function(p_ctrl->class_nbr, + p_buf, + buf_len, + xfer_len, + p_callback_arg, + status); +} + +/****************************************************************************************************//** + * usbd_vendor_read_interrupt_async_complete() + * + * @brief Inform the application about the Interrupt OUT transfer completion. + * + * @param ep_addr Endpoint address. + * + * @param p_buf Pointer to the receive buffer. + * + * @param buf_len Receive buffer length. + * + * @param xfer_len Number of octets received. + * + * @param p_arg Additional argument provided by application. + * + * @param status Transfer status: success or error. + *******************************************************************************************************/ +static void usbd_vendor_read_interrupt_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + void *p_callback_arg; + + (void)&ep_addr; + + // Get Vendor class instance ctrl struct. + p_ctrl = (sli_usbd_vendor_ctrl_t *)p_arg; + p_callback_arg = p_ctrl->interrupt_read_async_arg_ptr; + + // Xfer finished, no more active xfer. + p_ctrl->comm_ptr->interrupt_out_active_transfer = false; + // Call app callback to inform about xfer completion. + p_ctrl->interrupt_read_async_function(p_ctrl->class_nbr, + p_buf, + buf_len, + xfer_len, + p_callback_arg, + status); +} + +/****************************************************************************************************//** + * usbd_vendor_write_interrupt_async_complete() + * + * @brief Inform the application about the Interrupt IN transfer completion. + * + * @param ep_addr Endpoint address. + * + * @param p_buf Pointer to the transmit buffer. + * + * @param buf_len Transmit buffer length. + * + * @param xfer_len Number of octets sent. + * + * @param p_arg Additional argument provided by application. + * + * @param status Transfer status: success or error. + *******************************************************************************************************/ +static void usbd_vendor_write_interrupt_async_complete(uint8_t ep_addr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_arg, + sl_status_t status) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + void *p_callback_arg; + + (void)&ep_addr; + + // Get Vendor class instance ctrl struct. + p_ctrl = (sli_usbd_vendor_ctrl_t *)p_arg; + p_callback_arg = p_ctrl->interrupt_write_async_arg_ptr; + + // Xfer finished, no more active xfer. + p_ctrl->comm_ptr->interrupt_in_active_transfer = false; + // Call app callback to inform about xfer completion. + p_ctrl->interrupt_write_async_function(p_ctrl->class_nbr, + p_buf, + buf_len, + xfer_len, + p_callback_arg, + status); +} + +// clang-format on + +// [NF_CHANGE] +sl_status_t sl_usbd_vendor_abort_read_bulk(uint8_t class_nbr) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + sl_status_t status; + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) + { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + // Check if a xfer is already in progress. + if (p_ctrl->comm_ptr->data_bulk_out_active_transfer) + { + status = sl_usbd_core_abort_endpoint(p_ctrl->comm_ptr->data_bulk_out_endpoint_address); + + if (status == SL_STATUS_OK) + { + p_ctrl->comm_ptr->data_bulk_out_active_transfer = false; + } + } + else + { + // No xfer in progress + status = SL_STATUS_NONE_WAITING; + } + + return status; +} + +sl_status_t sl_usbd_vendor_abort_write_bulk(uint8_t class_nbr) +{ + sli_usbd_vendor_ctrl_t *p_ctrl; + sl_status_t status; + + if (class_nbr >= SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY) + { + return SL_STATUS_INVALID_PARAMETER; + } + // Get Vendor class instance ctrl struct. + p_ctrl = &usbd_vendor.ctrl_table[class_nbr]; + + // Check if another xfer is already in progress. + if (p_ctrl->comm_ptr->data_bulk_in_active_transfer) + { + status = sl_usbd_core_abort_endpoint(p_ctrl->comm_ptr->data_bulk_in_endpoint_address); + + if (status == SL_STATUS_OK) + { + p_ctrl->comm_ptr->data_bulk_in_active_transfer = false; + } + } + else + { + // No xfer in progress + status = SL_STATUS_NONE_WAITING; + } + + return status; +} + +// [END_NF_CHANGE] diff --git a/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h b/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h new file mode 100644 index 0000000000..474f50a20f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h @@ -0,0 +1,428 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// This is an extension to the original file from Gecko SDK v4.1.1 +// Following Support Case #00293097 with Silabs, we where advised to add the missing +// APIs to our own implementation. In case these are ever made available in the +// official SDK, this file should be removed and the original one should be used. + +// clang-format off + +#ifndef SL_USBD_CLASS_VENDOR_H +#define SL_USBD_CLASS_VENDOR_H + +/******************************************************************************************************** + ******************************************************************************************************** + * INCLUDE FILES + ******************************************************************************************************** + *******************************************************************************************************/ + +#include +#include + +#include + +/******************************************************************************************************** + ******************************************************************************************************** + * DATA TYPES + ******************************************************************************************************** + *******************************************************************************************************/ +/// Vendor callbacks +typedef const struct { + void (*enable)(uint8_t class_nbr); ///< Callback for enable event + + void (*disable)(uint8_t class_nbr); ///< Callback for disable event + + void (*setup_req)(uint8_t class_nbr, + const sl_usbd_setup_req_t *p_setup_req); ///< Callback for setup req event +} sl_usbd_vendor_callbacks_t; + +/// App callback used for async comm. +typedef void (*sl_usbd_vendor_async_function_t)(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint32_t xfer_len, + void *p_callback_arg, + sl_status_t status); + +/******************************************************************************************************** + ******************************************************************************************************** + * FUNCTION PROTOTYPES + ******************************************************************************************************** + *******************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************************************** + * VENDOR FUNCTIONS + *******************************************************************************************************/ + +/****************************************************************************************************//** + * @brief Initialize the internal structures and variables used by the Vendor class. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_init(void); + +/****************************************************************************************************//** + * @brief Add a new instance of the Vendor class. + * + * @param intr_en Interrupt endpoints IN and OUT flag: + * - true Pair of interrupt endpoints added to interface. + * - false Pair of interrupt endpoints not added to interface. + * + * @param interval Endpoint interval in milliseconds (must be a power of 2). + * + * @param p_vendor_callbacks Pointer to vendor callback structure. + * [Content MUST be persistent] + * + * @param p_class_nbr Pointer to a variable that will receive class instance number, if no + * errors are returned, or SL_USBD_CLASS_NBR_NONE otherwise. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_create_instance(bool intr_en, + uint16_t interval, + sl_usbd_vendor_callbacks_t *p_vendor_callbacks, + uint8_t *p_class_nbr); + +/****************************************************************************************************//** + * @brief Add the Vendor class instance into the specified configuration (see Note #1). + * + * @param class_nbr Class instance number. + * + * @param config_nbr Configuration index to which to add the Vendor class instance. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) Called several times, it creates multiple instances and configurations. + * For instance, the following architecture could be created : + * @verbatim + * FS + * |-- Configuration 0 + * |-- Interface 0 (Vendor 0) + * |-- Configuration 1 + * |-- Interface 0 (Vendor 0) + * |-- Interface 1 (Vendor 1) + * @endverbatim + * In that example, there are two instances of Vendor class: 'Vendor 0' and '1', and two + * possible configurations: 'Configuration 0' and '1'. 'Configuration 1' is composed + * of two interfaces. Each class instance has an association with one of the interfaces. + * If 'Configuration 1' is activated by the host, it allows the host to access two + * different functionalities offered by the device. + * + * @note (2) Configuration Descriptor corresponding to a Vendor-specific device has the following + * format : + * @verbatim + * Configuration Descriptor + * |-- Interface Descriptor (Vendor class) + * |-- Endpoint Descriptor (Bulk OUT) + * |-- Endpoint Descriptor (Bulk IN) + * |-- Endpoint Descriptor (Interrupt OUT) - optional + * |-- Endpoint Descriptor (Interrupt IN) - optional + * @endverbatim + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_add_to_configuration(uint8_t class_nbr, + uint8_t config_nbr); + +/****************************************************************************************************//** + * @brief Get the vendor class enable state. + * + * @param class_nbr Class instance number. + * + * @param p_enabled Pointer to a variable that will receive the enable state. + * The variable is set to true, if the Vendor class is enabled, + * and is set to false if the Vendor class is NOT enabled. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, + bool *p_enabled); + +/****************************************************************************************************//** + * @brief Add a Microsoft OS extended property to this vendor class instance. + * + * @param class_nbr Class instance number. + * + * @param property_type Property type (see Note #2). + * - OS_PROPERTY_TYPE_REG_SZ + * - OS_PROPERTY_TYPE_REG_EXPAND_SZ + * - OS_PROPERTY_TYPE_REG_BINARY + * - OS_PROPERTY_TYPE_REG_DWORD_LITTLE_ENDIAN + * - OS_PROPERTY_TYPE_REG_DWORD_BIG_ENDIAN + * - OS_PROPERTY_TYPE_REG_LINK + * - OS_PROPERTY_TYPE_REG_MULTI_SZ + * + * @param p_property_name Pointer to the buffer that contains the property name. + * ---- Buffer assumed to be persistent ---- + * + * @param property_name_len Length of the property name in octets. + * + * @param p_property Pointer to the buffer that contains the property name. + * ---- Buffer assumed to be persistent ---- + * + * @param property_len Length of the property in octets. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) For more information on Microsoft OS descriptors, see + * 'http://msdn.microsoft.com/en-us/library/windows/hardware/gg463179.aspx'. + * + * @note (2) For more information on property types, refer to "Table 3. Property Data Types" of + * "Extended Properties OS Feature Descriptor Specification" document provided by + * Microsoft available at + * 'http://msdn.microsoft.com/en-us/library/windows/hardware/gg463179.aspx'. + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +sl_status_t sl_usbd_vendor_add_microsoft_ext_property(uint8_t class_nbr, + uint8_t property_type, + const uint8_t *p_property_name, + uint16_t property_name_len, + const uint8_t *p_property, + uint32_t property_len); +#endif + +/****************************************************************************************************//** + * @brief Receive the data from the host through the Bulk OUT endpoint. This function is blocking. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the receive buffer. + * + * @param buf_len Receive the buffer length in octets. + * + * @param timeout Timeout in milliseconds. + * + * @param p_xfer_len Pointer to a variable that will receive transfer length. + * The variable is set to number of octets received, if no errors are returned, + * or is set to 0 if any errors are returned. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_bulk_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); + +/****************************************************************************************************//** + * @brief Send data to the host through Bulk IN endpoint. This function is blocking. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the transmit buffer. + * + * @param buf_len Transmit the buffer length in octets. + * + * @param timeout Timeout in milliseconds. + * + * @param end End-of-transfer flag (see Note #1). + * + * @param p_xfer_len Pointer to a variable that will receive transfer length. + * The variable is set to number of octets received, if no errors are returned, + * or is set to 0 if any errors are returned. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) If the end-of-transfer is set and the transfer length is a multiple of the maximum + * packet size, a zero-length packet is transferred to signal the end of transfer to the host. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_bulk_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + bool end, + uint32_t *p_xfer_len); + +/****************************************************************************************************//** + * @brief Receive data from the host through the Bulk OUT endpoint. This function is non-blocking + * are returns immediately after transfer preparation. Upon transfer completion, a callback + * provided by the application will be called to finalize the transfer. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the receive buffer. + * + * @param buf_len Receive buffer length in octets. + * + * @param async_fnct Receive the the callback. + * + * @param p_async_arg Additional argument provided by the application for the receive callback. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_bulk_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg); + +/****************************************************************************************************//** + * @brief Send data to the host through the Bulk IN endpoint. This function is non-blocking + * and returns immediately after transfer preparation. Upon transfer completion, a + * callback provided by the application will be called to finalize the transfer. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the transmit buffer. + * + * @param buf_len Transmit buffer length in octets. + * + * @param async_fnct Transmit the callback. + * + * @param p_async_arg Additional argument provided by the application for the transmit callback. + * + * @param end End-of-transfer flag (see Note #1). + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) If the end-of-transfer is set and the transfer length is a multiple of the maximum + * packet size, a zero-length packet is transferred to signal the end of transfer to the host. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_bulk_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg, + bool end); + +/****************************************************************************************************//** + * @brief Receive data from the the host through the Interrupt OUT endpoint. This function is blocking. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the receive buffer. + * + * @param buf_len Receive buffer length in octets. + * + * @param timeout Timeout in milliseconds. + * + * @param p_xfer_len Pointer to a variable that will receive transfer length. + * The variable is set to number of octets received, if no errors are returned, + * or is set to 0 if any errors are returned. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_interrupt_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); + +/****************************************************************************************************//** + * @brief Send data to the host through the Interrupt IN endpoint. This function is blocking. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the transmit buffer. + * + * @param buf_len Transmit buffer length in octets. + * + * @param timeout Timeout in milliseconds. + * + * @param end End-of-transfer flag (see Note #1). + * + * @param p_xfer_len Pointer to a variable that will receive transfer length. + * The variable is set to number of octets received, if no errors are returned, + * or is set to 0 if any errors are returned. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) If the end-of-transfer is set and the transfer length is a multiple of the maximum + * packet size, a zero-length packet is transferred to signal the end of transfer to the host. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_interrupt_sync(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + bool end, + uint32_t *p_xfer_len); + +/****************************************************************************************************//** + * @brief Receive data from the host through Interrupt OUT endpoint. This function is non-blocking + * and returns immediately after transfer preparation. Upon transfer completion, a callback + * provided by the application will be called to finalize the transfer. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the receive buffer. + * + * @param buf_len Receive buffer length in octets. + * + * @param async_fnct Receive callback. + * + * @param p_async_arg Additional argument provided by application for the receive callback. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_read_interrupt_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg); + +/****************************************************************************************************//** + * @brief Send data to the host through the Interrupt IN endpoint. This function is non-blocking + * and returns immediately after transfer preparation. Upon transfer completion, a callback + * provided by the application will be called to finalize the transfer. + * + * @param class_nbr Class instance number. + * + * @param p_buf Pointer to the transmit buffer. + * + * @param buf_len Transmit buffer length in octets. + * + * @param async_fnct Transmit callback. + * + * @param p_async_arg Additional argument provided by the application for the transmit callback. + * + * @param end End-of-transfer flag (see Note #1). + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) If the end-of-transfer is set and the transfer length is a multiple of the maximum + * packet size, a zero-length packet is transferred to signal the end of transfer to the host. + *******************************************************************************************************/ +sl_status_t sl_usbd_vendor_write_interrupt_async(uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + sl_usbd_vendor_async_function_t async_fnct, + void *p_async_arg, + bool end); + +// clang-format on + +// [NF_CHANGE] + +// Abort an ongoing async I/O transfer on the Bulk OUT endpoint. +// class_nbr Class instance number. +// Returns SL_STATUS_OK on success or another SL_STATUS code on failure. +sl_status_t sl_usbd_vendor_abort_read_bulk(uint8_t class_nbr); + +// Abort an ongoing async I/O transfer on the Bulk IN endpoint. +// param class_nbr Class instance number. +// Returns SL_STATUS_OK on success or another SL_STATUS code on failure. +sl_status_t sl_usbd_vendor_abort_write_bulk(uint8_t class_nbr); + +// [END_NF_CHANGE] + +#ifdef __cplusplus +} +#endif + +// clang-format off + +/****************************************************************************************************//** + ******************************************************************************************************** + * @} MODULE END + ******************************************************************************************************** + *******************************************************************************************************/ + +#endif + +// clang-format on From 02d30e2c3c395c1b8a9216391f4829fbdc2c8912 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 28 Oct 2022 17:55:44 +0100 Subject: [PATCH 270/572] Add more checks to init class vendor code --- .../_common/autogen/sl_usbd_class_vendor_instances.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 1ae094c2a6..f2477f527e 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -134,7 +134,12 @@ sl_status_t sli_usbd_vendor_winusb_init() interval = SL_USBD_VENDOR_WINUSB_INTERVAL; /* create vendor instance */ - sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number); + if (sl_usbd_vendor_create_instance(intr_en, interval, &sli_usbd_vendor_winusb_callbacks, &class_number) != + SL_STATUS_OK) + { + // error creating instance + return SL_STATUS_FAIL; + } /* store class number globally */ sl_usbd_vendor_winusb_number = class_number; @@ -150,7 +155,7 @@ sl_status_t sli_usbd_vendor_winusb_init() if (!strcmp(token, "config0") || !strcmp(token, "all")) { config_number = sl_usbd_configuration_config0_number; - if(sl_usbd_vendor_add_to_configuration(class_number, config_number) != SL_STATUS_OK) + if (sl_usbd_vendor_add_to_configuration(class_number, config_number) != SL_STATUS_OK) { // error adding class to configuration return SL_STATUS_FAIL; From 84b85f3f6919692794677a28bb2c97c1c043d3cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 28 Oct 2022 17:56:06 +0100 Subject: [PATCH 271/572] Improvements in UsbStream following updated USB API --- ...eam_native_System_Device_Usb_UsbStream.cpp | 51 +++++++------------ .../sys_dev_usbstream_native_target.h | 2 +- 2 files changed, 19 insertions(+), 34 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 7b5e62b733..d4947c7e17 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -217,8 +217,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit if (stack.m_customState == 1) { // ... and hasn't started yet - // push onto the eval stack how many bytes are being pushed to the USB - stack.PushValueI4(count); // bump custom state stack.m_customState = 2; @@ -255,22 +253,18 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // timeout expired if (!eventResult) { - // timeout has expired, return exception + // timeout has expired + // cancel the async operation... + sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); + + // ... return exception NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); } - NANOCLR_CLEANUP(); - - if (stack.m_customState > 1) - { - // pop "count" heap block from stack - stack.PopValue(); - - // pop timeout heap block from stack - stack.PopValue(); - } + // pop timeout heap block from stack + stack.PopValue(); - NANOCLR_CLEANUP_END(); + NANOCLR_NOCLEANUP(); } HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( @@ -332,8 +326,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead if (stack.m_customState == 1) { // ... and hasn't started yet - // push onto the eval stack how many bytes are being pushed to the USB - stack.PushValueI4(count); // bump custom state stack.m_customState = 2; @@ -372,27 +364,20 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // timeout expired if (!eventResult) { - // timeout has expired, return exception - NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); - } + // timeout has expired + // cancel the async operation... + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - NANOCLR_CLEANUP(); - - if (stack.m_customState > 1) - { - // pop "count" heap block from stack - stack.PopValue(); - - // pop timeout heap block from stack - stack.PopValue(); + // ... return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); } - if (SUCCEEDED(hr)) - { - stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); - } + // pop timeout heap block from stack + stack.PopValue(); + // set result with count of bytes received + stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); - NANOCLR_CLEANUP_END(); + NANOCLR_NOCLEANUP(); } HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index ef5a05d683..9a7a86fd59 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -12,7 +12,7 @@ #define USBD_CFG_EP_ISOC_EN 0 ////////////////////////////////////////////////////////////////////////////////////////////////////// -#include +#include // need these declared here as they are scattered throughout Gecko SDK and config files extern char UsbClassVendorDescription[32 + 1]; From b76fa69853dfbed2a0a1ec6ba03881b4132f59bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 1 Nov 2022 09:26:59 +0000 Subject: [PATCH 272/572] Add processing of USB HAL events --- src/CLR/Core/Hardware/Hardware.cpp | 10 ++++++++++ src/CLR/Include/nanoCLR_Hardware.h | 9 +++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/CLR/Core/Hardware/Hardware.cpp b/src/CLR/Core/Hardware/Hardware.cpp index ce78baaa1e..2407a13a74 100644 --- a/src/CLR/Core/Hardware/Hardware.cpp +++ b/src/CLR/Core/Hardware/Hardware.cpp @@ -183,6 +183,16 @@ void CLR_HW_Hardware::ProcessActivity() eventsCLR |= Event_Bluetooth; } + if (events & SYSTEM_EVENT_FLAG_USB_IN) + { + eventsCLR |= Event_UsbIn; + } + + if (events & SYSTEM_EVENT_FLAG_USB_OUT) + { + eventsCLR |= Event_UsbOut; + } + if (eventsCLR) { g_CLR_RT_ExecutionEngine.SignalEvents(eventsCLR); diff --git a/src/CLR/Include/nanoCLR_Hardware.h b/src/CLR/Include/nanoCLR_Hardware.h index 1c4721605d..c9ad6eef80 100644 --- a/src/CLR/Include/nanoCLR_Hardware.h +++ b/src/CLR/Include/nanoCLR_Hardware.h @@ -22,10 +22,11 @@ struct CLR_HW_Hardware static const CLR_UINT32 c_Default_PowerLevel = PowerLevel__Sleep; static const CLR_UINT32 c_Default_WakeupEvents = SYSTEM_EVENT_FLAG_COM_IN | SYSTEM_EVENT_FLAG_COM_OUT | SYSTEM_EVENT_FLAG_STORAGE_IO | - SYSTEM_EVENT_FLAG_SYSTEM_TIMER | SYSTEM_EVENT_FLAG_SPI_MASTER | SYSTEM_EVENT_FLAG_I2C_MASTER | - SYSTEM_EVENT_HW_INTERRUPT | SYSTEM_EVENT_FLAG_SOCKET | SYSTEM_EVENT_FLAG_DEBUGGER_ACTIVITY | - SYSTEM_EVENT_FLAG_MESSAGING_ACTIVITY | SYSTEM_EVENT_FLAG_ONEWIRE_MASTER | SYSTEM_EVENT_FLAG_RADIO | - SYSTEM_EVENT_FLAG_WIFI_STATION | SYSTEM_EVENT_FLAG_BLUETOOTH; + SYSTEM_EVENT_FLAG_SYSTEM_TIMER | SYSTEM_EVENT_FLAG_USB_IN | SYSTEM_EVENT_FLAG_USB_OUT | + SYSTEM_EVENT_FLAG_SPI_MASTER | SYSTEM_EVENT_FLAG_I2C_MASTER | SYSTEM_EVENT_HW_INTERRUPT | + SYSTEM_EVENT_FLAG_SOCKET | SYSTEM_EVENT_FLAG_DEBUGGER_ACTIVITY | SYSTEM_EVENT_FLAG_MESSAGING_ACTIVITY | + SYSTEM_EVENT_FLAG_ONEWIRE_MASTER | SYSTEM_EVENT_FLAG_RADIO | SYSTEM_EVENT_FLAG_WIFI_STATION | + SYSTEM_EVENT_FLAG_BLUETOOTH; //--// From 4db4bd8e4c8f50293fb627779ae30bc29ad94531 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 1 Nov 2022 09:27:40 +0000 Subject: [PATCH 273/572] Add deinit for WINUSB --- ...v_usbstream_native_System_Device_Usb_UsbStream.cpp | 4 ++++ targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d4947c7e17..b9c1f640c8 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -96,6 +96,10 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClos (void)stack; + // abort any transfer in progress, just in case + sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); + platform_free(UsbStream_PAL.RxBuffer); UsbStream_PAL.RxBuffer = NULL; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 2bb21ca669..42c3ba1c54 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -289,6 +289,17 @@ adc0Initialized = false; #if (GECKO_USE_ADC1 == TRUE) && defined(NANO_GG_ADC_NATIVE_TARGET_H) ADC_Reset(ADC1); adc1Initialized = false; +#endif + +#if GECKO_FEATURE_USBD_WINUSB == TRUE + + // abort any transfer in progress, just in case + sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); + + platform_free(UsbStream_PAL.RxBuffer); + UsbStream_PAL.RxBuffer = NULL; + #endif // #if (HAL_USE_UART == TRUE) From 69719e19401d1184b43634acd8ab53d37fdb3c64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 1 Nov 2022 09:34:06 +0000 Subject: [PATCH 274/572] Add missing INT start/end blocks in USB interrupt handlers --- ...s_dev_usbstream_native_System_Device_Usb_UsbStream.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index b9c1f640c8..2a10e06f22 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -21,12 +21,16 @@ static void UsbAsyncWriteCompleted( (void)buf_len; (void)status; + NATIVE_INTERRUPT_START + NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; // store TX count usbPal->TxBytesSent = xfer_len; Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); + + NATIVE_INTERRUPT_END } static void UsbAsyncReadCompleted( @@ -42,12 +46,16 @@ static void UsbAsyncReadCompleted( (void)buf_len; (void)status; + NATIVE_INTERRUPT_START + NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; // store RX count usbPal->RxBytesReceived = xfer_len; Events_Set(SYSTEM_EVENT_FLAG_USB_IN); + + NATIVE_INTERRUPT_END } // -- // From 09b414480d27eddc9670edc3e026dc3f38513b89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 1 Nov 2022 11:46:03 +0000 Subject: [PATCH 275/572] Fix implementation of UsbStream Read and Write for events --- ...eam_native_System_Device_Usb_UsbStream.cpp | 44 +++++++++++-------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 2a10e06f22..be89a10f00 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -260,17 +260,21 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); - } - // timeout expired - if (!eventResult) - { - // timeout has expired - // cancel the async operation... - sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); + if (eventResult) + { + // done here + break; + } + else + { + // timeout has expired + // cancel the async operation... + sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); - // ... return exception - NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + // ... return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } } // pop timeout heap block from stack @@ -371,17 +375,21 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); - } - // timeout expired - if (!eventResult) - { - // timeout has expired - // cancel the async operation... - sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); + if (eventResult) + { + // done here + break; + } + else + { + // timeout has expired + // cancel the async operation... + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - // ... return exception - NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + // ... return exception + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } } // pop timeout heap block from stack From 5319587a91d4b56aecb66d3d5ddbaf37d1cb138d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 2 Nov 2022 14:44:20 +0000 Subject: [PATCH 276/572] Move declaration of UsbEventType --- .../sys_dev_usbstream_native.h | 3 ++- .../autogen/sl_usbd_class_vendor_instances.c | 7 ------- .../autogen/sl_usbd_class_vendor_instances.h | 16 ++++++++++++++++ 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 4e6d3af44f..9affc024fe 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -12,13 +12,14 @@ #include ///////////////////////////////////////////////////////////////////////////////////////////////////////////// -// moved to targets\AzureRTOS\SiliconLabs\_common\autogen\sl_usbd_class_vendor_instances.c for convenience // +// moved to targets\AzureRTOS\SiliconLabs\_common\autogen\sl_usbd_class_vendor_instances.h for convenience // ///////////////////////////////////////////////////////////////////////////////////////////////////////////// // typedef enum __nfpack UsbEventType // { // UsbEventType_Invalid = 0, // UsbEventType_DeviceConnected = 1, // UsbEventType_DeviceDisconnected = 2, +// UsbEventType_DataAvailable = 3, // } UsbEventType; struct Library_sys_dev_usbstream_native_System_Device_Usb_DeviceConnectionEventArgs diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index f2477f527e..5d67738782 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -42,13 +42,6 @@ char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; // flag for USB WinUSB intialized static bool usbdVendorWinusbInited = false; -typedef enum __nfpack UsbEventType -{ - UsbEventType_Invalid = 0, - UsbEventType_DeviceConnected = 1, - UsbEventType_DeviceDisconnected = 2, -} UsbEventType; - //**************************************************************************** // Function declarations. diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h index 72776bcc84..3a39905eb1 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -9,6 +9,14 @@ #include +typedef enum __nfpack UsbEventType +{ + UsbEventType_Invalid = 0, + UsbEventType_DeviceConnected = 1, + UsbEventType_DeviceDisconnected = 2, + UsbEventType_DataAvailable = 3, +} UsbEventType; + #define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" /// Length of GUID Property Name @@ -31,6 +39,14 @@ __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req /* init functions for all vendor instances */ +#ifdef __cplusplus +extern "C" { +#endif + sl_status_t sli_usbd_vendor_winusb_init(void); +#ifdef __cplusplus +} +#endif + #endif From a9ef232185962943aeb413dbe30f50d3f1459108 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 2 Nov 2022 15:15:01 +0000 Subject: [PATCH 277/572] Rework CMake for native assemblies to ease merge from upstream --- CMake/Modules/FindNF_NativeAssemblies.cmake | 23 +++++++++++---------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index 0fce21d52f..79f38723e7 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -317,11 +317,6 @@ endif() if(API_System.Device.I2s) ##### API name here (doted name) PerformSettingsForApiEntry("System.Device.I2s") - -# Com.SkyworksInc.NanoFramework.Devices.I2c -if(API_Com.SkyworksInc.NanoFramework.Devices.I2c) - ##### API name here (doted name) - PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.I2c") endif() # System.Device.Pwm @@ -336,12 +331,6 @@ if(API_System.IO.Ports) PerformSettingsForApiEntry("System.IO.Ports") endif() -# Com.SkyworksInc.NanoFramework.Devices.Spi -if(API_Com.SkyworksInc.NanoFramework.Devices.Spi) - ##### API name here (doted name) - PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.Spi") -endif() - # System.Device.Spi if(API_System.Device.Spi) ##### API name here (doted name) @@ -366,6 +355,18 @@ if(API_Windows.Storage) PerformSettingsForApiEntry("Windows.Storage") endif() +# Com.SkyworksInc.NanoFramework.Devices.I2c +if(API_Com.SkyworksInc.NanoFramework.Devices.I2c) + ##### API name here (doted name) + PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.I2c") +endif() + +# Com.SkyworksInc.NanoFramework.Devices.Spi +if(API_Com.SkyworksInc.NanoFramework.Devices.Spi) + ##### API name here (doted name) + PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.Spi") +endif() + # Interop assemblies ParseInteropAssemblies() From 470c49f7c9a3bb3f6d18df981a74911965140e06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 2 Nov 2022 18:16:54 +0000 Subject: [PATCH 278/572] Fix SPI bus index for Gecko --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 40 ++++++------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 575b048925..1cc49113a8 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -144,42 +144,38 @@ NF_PAL_SPI *GetNfPalfromBusIndex(uint8_t busIndex) // get the PAL struct for the SPI bus switch (busIndex) { - ////////////////////////////////// - // Gecko USART index is 0 based // - ////////////////////////////////// - #if GECKO_USE_SPI0 == TRUE - case 1: + case 0: palSpi = &SPI0_PAL; break; #endif #if GECKO_USE_SPI1 == TRUE - case 2: + case 1: palSpi = &SPI1_PAL; break; #endif #if GECKO_USE_SPI2 == TRUE - case 3: + case 2: palSpi = &SPI2_PAL; break; #endif #if GECKO_USE_SPI3 == TRUE - case 4: + case 3: palSpi = &SPI3_PAL; break; #endif #if GECKO_USE_SPI4 == TRUE - case 5: + case 4: palSpi = &SPI4_PAL; break; #endif #if GECKO_USE_SPI5 == TRUE - case 6: + case 5: palSpi = &SPI5_PAL; break; #endif @@ -495,26 +491,22 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon // why do we need this? because several SPIDevice objects can be created associated to the same bus switch (busIndex) { - ////////////////////////////////// - // Gecko USART index is 0 based // - ////////////////////////////////// - #if GECKO_USE_SPI0 == TRUE - case 1: + case 0: palSpi = &SPI0_PAL; initSpiConfig = &InitSpiConfig0; break; #endif #if GECKO_USE_SPI1 == TRUE - case 2: + case 1: palSpi = &SPI1_PAL; initSpiConfig = &InitSpiConfig1; break; #endif #if GECKO_USE_SPI2 == TRUE - case 3: + case 2: palSpi = &SPI2_PAL; initSpiConfig = &InitSpiConfig2; @@ -522,21 +514,21 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon #endif #if GECKO_USE_SPI3 == TRUE - case 4: + case 3: palSpi = &SPI3_PAL; initSpiConfig = &InitSpiConfig3; break; #endif #if GECKO_USE_SPI4 == TRUE - case 5: + case 4: palSpi = &SPI4_PAL; initSpiConfig = &InitSpiConfig4; break; #endif #if GECKO_USE_SPI5 == TRUE - case 6: + case 5: palSpi = &SPI5_PAL; initSpiConfig = &InitSpiConfig5; break; @@ -605,10 +597,6 @@ bool CPU_SPI_Uninitialize(uint8_t busIndex) // get the PAL struct for the SPI bus switch (busIndex) { - ////////////////////////////////// - // Gecko USART index is 0 based // - ////////////////////////////////// - #if GECKO_USE_SPI0 == TRUE case 0: palSpi = &SPI0_PAL; @@ -678,10 +666,6 @@ uint32_t CPU_SPI_PortsMap() { uint32_t map = 0; - ////////////////////////////////// - // Gecko USART index is 0 based // - ////////////////////////////////// - #if GECKO_USE_SPI0 == TRUE map |= 0x01; #endif From 68724b0fcb9a0036cc6b715b4013a7c28de4fd8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 3 Nov 2022 12:03:12 +0000 Subject: [PATCH 279/572] Fix indexes with I2C0 PAL structs --- .../sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp index cf4ea3efd6..a0ffe2910d 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -172,7 +172,7 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOI { I2C0_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); - if (I2C1_PAL.Configuration == NULL) + if (I2C0_PAL.Configuration == NULL) { NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); } @@ -183,7 +183,7 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOI ConfigPins_I2C0(); I2C0_PAL.Configuration->port = I2C0; - palI2c = &I2C1_PAL; + palI2c = &I2C0_PAL; // increase device counter I2C0_DeviceCounter++; From 27ffbf162563082834c4a6f03c4f240f597403de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 3 Nov 2022 12:03:48 +0000 Subject: [PATCH 280/572] Add config for I2C0 exposing EXP header pins --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md | 5 +++++ .../SL_STK3701A/target_system_device_i2c_config.cpp | 13 ++++++++++++- .../SL_STK3701A/target_system_device_i2c_config.h | 1 + 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index 87239e5f29..1d88368a98 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -28,6 +28,11 @@ PWM has enabled the following GPIOs: ## I2C +I2C0 (this is referenced as I2C1 in C#) +Available in EXP header +I2C0_SDA: PC6, EXP Header Pin 19 +I2C0_SCL: PC7, EXP Header Pin 17 + I2C2 (this is referenced as I2C3 in C#) Connected to the following devices on the GG11 board: Si7021: Relative Humidity and Temperature Sensor diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp index 2914cfa6c8..6899b00ed0 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp @@ -5,6 +5,17 @@ #include +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PC7 +// port for I2C0_SDA is: PC6 + +// GPIO alternate pin function is 2 for both pins (see Alternate Functionality mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortC, gpioPortC, 7, 6, 2, 2) + ////////// // I2C2 // ////////// @@ -18,5 +29,5 @@ // port for I2C2_SCL is: GPIOI_5 // port for I2C2_SDA is: GPIOI_4 -// GPIO alternate pin function is 7 for both pins (see alternate function mapping table in device datasheet) +// GPIO alternate pin function is 7 for both pins (see Alternate Functionality mapping table in device datasheet) I2C_CONFIG_PINS(2, gpioPortI, gpioPortI, 5, 4, 7, 7) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h index 847fb55566..0e5a564e80 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h @@ -3,4 +3,5 @@ // See LICENSE file in the project root for full license information. // +#define GECKO_USE_I2C0 TRUE #define GECKO_USE_I2C2 TRUE From 51a2c8bf2eaf8a3c99c421b01ad37f0caa8ac237 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 3 Nov 2022 12:04:05 +0000 Subject: [PATCH 281/572] Fix index of SPI in readme --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index 1d88368a98..86fe5c9fb6 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -51,7 +51,7 @@ SPI0_MOSI: PE10, EXP Header Pin 4 SPI0_MISO: PE11, EXP Header Pin 6 SPI0_CS: PE13, EXP Header Pin 10 -SPI0 (this is referenced as SPI2 in C#) +SPI1 (this is referenced as SPI2 in C#) Connected to board LCD module SPI1_SCK: PC15 From b119a505ad06d06f09fcebe3f83d3e499a8495b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 3 Nov 2022 17:56:03 +0000 Subject: [PATCH 282/572] Fix I2C pin mapping for EXP header --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md | 4 ++-- .../SL_STK3701A/target_system_device_i2c_config.cpp | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md index 86fe5c9fb6..5a583087ed 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/README.md @@ -30,8 +30,8 @@ PWM has enabled the following GPIOs: I2C0 (this is referenced as I2C1 in C#) Available in EXP header -I2C0_SDA: PC6, EXP Header Pin 19 -I2C0_SCL: PC7, EXP Header Pin 17 +I2C0_SDA: PC0, EXP Header Pin 16 +I2C0_SCL: PC1, EXP Header Pin 15 I2C2 (this is referenced as I2C3 in C#) Connected to the following devices on the GG11 board: diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp index 6899b00ed0..8c32bba8e1 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.cpp @@ -10,11 +10,11 @@ ////////// // pin configuration for I2C0 -// port for I2C0_SCL is: PC7 -// port for I2C0_SDA is: PC6 +// port for I2C0_SCL is: PC1 +// port for I2C0_SDA is: PC0 -// GPIO alternate pin function is 2 for both pins (see Alternate Functionality mapping table in device datasheet) -I2C_CONFIG_PINS(0, gpioPortC, gpioPortC, 7, 6, 2, 2) +// GPIO alternate pin function is 4 for both pins (see Alternate Functionality mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortC, gpioPortC, 1, 0, 4, 4) ////////// // I2C2 // From da4d098ba00478cc9f616dd0388b00d2fc993739 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 3 Nov 2022 18:02:25 +0000 Subject: [PATCH 283/572] Fix I2C bus indexing --- ...ksInc_NanoFramework_Devices_I2c_I2cBus.cpp | 28 ++++++------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp index e89a3a31c3..9cab8c74ec 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -129,12 +129,8 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 switch (busIndex) { - //////////////////////////////////// - // Gecko I2C bus index is 0 based // - //////////////////////////////////// - #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) - case 1: + case 0: if (I2C0_PAL.Configuration == NULL) { I2C0_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); @@ -159,7 +155,7 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) - case 2: + case 1: if (I2C1_PAL.Configuration == NULL) { I2C1_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); @@ -184,7 +180,7 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) - case 3: + case 2: if (I2C2_PAL.Configuration == NULL) { I2C2_PAL.Configuration = (I2CSPM_Init_TypeDef *)platform_malloc(sizeof(I2CSPM_Init_TypeDef)); @@ -256,12 +252,9 @@ HRESULT DisposeI2c(uint8_t busIndex, NF_PAL_I2C *&palI2c) // Gecko I2C bus index is 0 based switch (busIndex) { - //////////////////////////////////// - // Gecko I2C bus index is 0 based // - //////////////////////////////////// #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) - case 1: + case 0: palI2c = &I2C0_PAL; // free memory @@ -274,7 +267,7 @@ HRESULT DisposeI2c(uint8_t busIndex, NF_PAL_I2C *&palI2c) #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) - case 2: + case 1: // free memory platform_free(I2C1_PAL.Configuration); @@ -285,7 +278,7 @@ HRESULT DisposeI2c(uint8_t busIndex, NF_PAL_I2C *&palI2c) #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) - case 3: + case 2: // free memory platform_free(I2C2_PAL.Configuration); @@ -384,24 +377,21 @@ static HRESULT NativeTransmit(uint8_t busIndex, NF_PAL_I2C *&palI2c, CLR_RT_Stac // get the driver for the I2C bus switch (busIndex) { - //////////////////////////////////// - // Gecko I2C bus index is 0 based // - //////////////////////////////////// #if defined(I2C0) && (GECKO_USE_I2C0 == TRUE) - case 1: + case 0: palI2c = &I2C0_PAL; break; #endif #if defined(I2C1) && (GECKO_USE_I2C1 == TRUE) - case 2: + case 1: palI2c = &I2C1_PAL; break; #endif #if defined(I2C2) && (GECKO_USE_I2C2 == TRUE) - case 3: + case 2: palI2c = &I2C2_PAL; break; #endif From cc5ecd020f38e4e5e5e772fd408e70ba87b546cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 3 Nov 2022 23:59:50 +0000 Subject: [PATCH 284/572] Fix I2C config --- .../SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h index 85223e2e09..8b7431bf9d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_com_sky_nf_dev_i2c_config.h @@ -1,3 +1,4 @@ // Copyright Skyworks Solutions, Inc. All Rights Reserved. +#define GECKO_USE_I2C0 TRUE #define GECKO_USE_I2C2 TRUE From 5a5944e872697d941626f847a9107e28d57845f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 4 Nov 2022 15:14:16 +0000 Subject: [PATCH 285/572] Fix null ref pointer in WinUSB client --- targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 42c3ba1c54..c900f55b52 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -297,8 +297,11 @@ adc1Initialized = false; sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - platform_free(UsbStream_PAL.RxBuffer); - UsbStream_PAL.RxBuffer = NULL; + if(UsbStream_PAL.RxBuffer != NULL) + { + platform_free(UsbStream_PAL.RxBuffer); + UsbStream_PAL.RxBuffer = NULL; + } #endif From 32a15b7dfbc793681ba780c2319c428e9af9b716 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 4 Nov 2022 16:30:11 +0000 Subject: [PATCH 286/572] Fix access to static field with I2C bus speed --- ...kyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp index 9cab8c74ec..5e64b91c21 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -646,6 +646,9 @@ HRESULT Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_ uint8_t busIndex; I2cBusSpeed busSpeed; NF_PAL_I2C *palI2c = NULL; + + CLR_IDX assemblyIdx; + CLR_RT_Assembly *thisAssembly = NULL; CLR_RT_HeapBlock_Array *busSpeedCollection = NULL; // get a pointer to the managed object instance and check that it's not NULL @@ -655,10 +658,13 @@ HRESULT Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_ // get bus index busIndex = (uint8_t)stack.Arg1().NumericByRef().s4; - // get a pointer to the managed I2C connectionSettings object instance - busSpeedCollection = (CLR_RT_HeapBlock_Array *)pThis[FIELD_STATIC___busSpeed].DereferenceArray(); - - busSpeed = (I2cBusSpeed)*busSpeedCollection->GetElement(busIndex); + // get ref to SpiBaseConfiguration from static _busConnectionSettings array... + // need to access it through the assembly + assemblyIdx = pThis->ObjectCls().Assembly(); + thisAssembly = g_CLR_RT_TypeSystem.m_assemblies[assemblyIdx - 1]; + busSpeedCollection = thisAssembly->GetStaticField(FIELD_STATIC___busSpeed)->DereferenceArray(); + // ...access it by index + busSpeed = (I2cBusSpeed) * ((I2cBusSpeed *)busSpeedCollection->GetElement(busIndex)); // init I2C bus NANOCLR_CHECK_HRESULT(InitI2c(busIndex, busSpeed, palI2c)); From 6f6f8adddd60a7af9470ca490362330c921bcfa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 4 Nov 2022 16:49:12 +0000 Subject: [PATCH 287/572] Characterization of I2C bus speed --- ...e_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp index 5e64b91c21..5518292c18 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus.cpp @@ -28,6 +28,10 @@ uint8_t I2C1_DeviceCounter = 0; uint8_t I2C2_DeviceCounter = 0; #endif +// these values have adjust following characterization of Skyworks EVB rev2.0 +#define I2C_FREQ_STANDARD_SKYWORKS_EVB 110000 +#define I2C_FREQ_FAST_SKYWORKS_EVB 676000 + // estimate the time required to perform the I2C transaction bool IsLongRunningOperation( uint16_t writeSize, @@ -214,12 +218,12 @@ HRESULT InitI2c(uint8_t busIndex, I2cBusSpeed busSpeed, struct NF_PAL_I2C *palI2 // Get a general low-level I2C configuration, depending on user's managed parameters if (busSpeed == I2cBusSpeed_StandardMode) { - palI2c->Configuration->i2cMaxFreq = I2C_FREQ_STANDARD_MAX; + palI2c->Configuration->i2cMaxFreq = I2C_FREQ_STANDARD_SKYWORKS_EVB; palI2c->Configuration->i2cClhr = i2cClockHLRStandard; } else { - palI2c->Configuration->i2cMaxFreq = I2C_FREQ_FAST_MAX; + palI2c->Configuration->i2cMaxFreq = I2C_FREQ_FAST_SKYWORKS_EVB; palI2c->Configuration->i2cClhr = i2cClockHLRAsymetric; } From bb79c62e78811f96c7f05ddb2aaaefbbfdbec0f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 7 Nov 2022 19:01:45 +0000 Subject: [PATCH 288/572] External crystals are not enabled anymore --- .../SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c index 93eb4ef0a5..8107177acc 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c @@ -34,9 +34,9 @@ void sl_platform_init(void) sl_device_init_nvic(); sl_board_preinit(); sl_device_init_dcdc(); - sl_device_init_hfxo(); + //sl_device_init_hfxo(); sl_device_init_hfrco(); - sl_device_init_lfxo(); + //sl_device_init_lfxo(); sl_device_init_lfrco(); sl_device_init_clocks(); sl_device_init_emu(); From fef08824cf98e23b97a186343099be68192b25b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 7 Nov 2022 19:02:08 +0000 Subject: [PATCH 289/572] Update declaration for UsbStream assembly --- src/System.Device.UsbStream/sys_dev_usbstream_native.cpp | 5 +++-- src/System.Device.UsbStream/sys_dev_usbstream_native.h | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index e465544e00..c3ef06f918 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -60,6 +60,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, @@ -75,9 +76,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x19581C1B, + 0x2ADFC2C3, method_lookup, - { 100, 0, 0, 2 } + { 100, 0, 0, 3 } }; // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 9affc024fe..b405a80e1e 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -71,7 +71,6 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream //--// }; - extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream; #endif // SYS_DEV_USBSTREAM_NATIVE_H From 04b3d60bf52e8beb612ea18422549a955ea8b8ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 8 Nov 2022 14:07:55 +0000 Subject: [PATCH 290/572] Fix USB vendor config --- .../SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h index a604eb6826..c055ad3f2f 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -96,7 +96,7 @@ extern char UsbClassVendorDescription[32 + 1]; // Number of configurations <1-255> // Default: 1 // Number of configurations. -#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 2 // Number of subclass instances <1-255> // Default: 2 @@ -188,7 +188,7 @@ extern char UsbClassVendorDescription[32 + 1]; // Number of configurations <1-255> // Default: 1 // Number of configurations. -#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 1 +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 // pointer to USB Class Vendor description #define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription From 9d6ad809e4634790025e964b095d0a6b54be78f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 8 Nov 2022 14:11:19 +0000 Subject: [PATCH 291/572] USB product name can be set from UsbStream - This is now possible when there is a single USB device. Was only working for composite devices. --- .../autogen/sl_usbd_class_vendor_instances.c | 13 ++++++++++++- .../SiliconLabs/_common/nano_sl_usbd_class_vendor.c | 9 +++++++++ .../_include/nano_sl_usbd_class_vendor.h | 2 ++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 5d67738782..2f1217a65e 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -9,6 +9,7 @@ #include "sl_status.h" #include +#include #ifdef __GNUC__ #pragma GCC diagnostic push @@ -34,6 +35,7 @@ // need to declare this here as extern extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2); +extern sl_status_t sl_usbd_vendor_update_device_product_string(const char *product_string); // storage for USB class vendor description char UsbClassVendorDescription[32 + 1]; @@ -159,9 +161,18 @@ sl_status_t sli_usbd_vendor_winusb_init() token = strtok(NULL, ", "); } +#if HAL_WP_USE_USB_CDC == FALSE + // no USB CDC so this won't be a composite device + // need to set the description here from USB Class vendor description + sl_usbd_vendor_update_device_product_string((const char *)UsbClassVendorDescription); + + // also need to adjust the class number for the Microsoft extend property + class_number--; +#endif + // add device class GUID to WinUSB properties sl_usbd_vendor_add_microsoft_ext_property( - config_number, + class_number, SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, DEVICEINTERFACE_GUID_PROP_NAME_LEN, diff --git a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c index ce1a3b4955..eb748df429 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c +++ b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_class_vendor.c @@ -1376,4 +1376,13 @@ sl_status_t sl_usbd_vendor_abort_write_bulk(uint8_t class_nbr) return status; } +sl_status_t sl_usbd_vendor_update_device_product_string(const char *product_string) +{ + sli_usbd_device_t *p_dev; + p_dev = &usbd_ptr->device; + p_dev->device_config.product_str_ptr = product_string; + + return SL_STATUS_OK; +} + // [END_NF_CHANGE] diff --git a/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h b/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h index 474f50a20f..a7b7ebcadb 100644 --- a/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h +++ b/targets/AzureRTOS/SiliconLabs/_include/nano_sl_usbd_class_vendor.h @@ -409,6 +409,8 @@ sl_status_t sl_usbd_vendor_abort_read_bulk(uint8_t class_nbr); // Returns SL_STATUS_OK on success or another SL_STATUS code on failure. sl_status_t sl_usbd_vendor_abort_write_bulk(uint8_t class_nbr); +sl_status_t sl_usbd_vendor_update_device_product_string(const char *product_string); + // [END_NF_CHANGE] #ifdef __cplusplus From aaade2f57acbfe21cd06fdadbe0c6957d1c91516 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 8 Nov 2022 17:55:01 +0000 Subject: [PATCH 292/572] Update UsbStream assembly declaration - Also update validations and fixed the exceptions being thrown. --- .../sys_dev_usbstream_native.cpp | 11 +- .../sys_dev_usbstream_native.h | 4 +- ...tive_System_Device_Usb_UsbStream_stubs.cpp | 16 +- ...eam_native_System_Device_Usb_UsbStream.cpp | 214 +++++++++--------- 4 files changed, 123 insertions(+), 122 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index c3ef06f918..5e45804279 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -42,11 +42,11 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4, NULL, NULL, NULL, - NULL, - NULL, + Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VOID__SZARRAY_U1__I4__I4, NULL, NULL, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN, @@ -61,10 +61,9 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4, NULL, NULL, @@ -76,9 +75,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x2ADFC2C3, + 0x6F6BE161, method_lookup, - { 100, 0, 0, 3 } + { 100, 0, 0, 4 } }; // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index b405a80e1e..6ee1b90532 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -60,12 +60,12 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream static const int FIELD__DataReceived = 9; NANOCLR_NATIVE_DECLARE(Flush___VOID); + NANOCLR_NATIVE_DECLARE(Read___I4__SZARRAY_U1__I4__I4); + NANOCLR_NATIVE_DECLARE(Write___VOID__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); NANOCLR_NATIVE_DECLARE(get_BytesToRead___I4); NANOCLR_NATIVE_DECLARE(NativeClose___VOID); NANOCLR_NATIVE_DECLARE(NativeOpen___I4__STRING__STRING); - NANOCLR_NATIVE_DECLARE(NativeWrite___VOID__SZARRAY_U1__I4__I4); - NANOCLR_NATIVE_DECLARE(NativeRead___I4__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(NativeReceivedBytesThreshold___VOID__I4); //--// diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp index 8df842110f..9ae6003c96 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp @@ -14,8 +14,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VO NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -24,7 +23,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConn NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VOID__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -33,7 +32,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesT NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -42,8 +42,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClos NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -52,8 +51,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -62,7 +60,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index be89a10f00..b337d4c2d4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -69,108 +69,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VO NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - bool conn; - - if (sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) - { - stack.SetResult_Boolean(conn); - } - else - { - NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); - } - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - // get length of Rx ring buffer - stack.SetResult_U4(UsbStream_PAL.RxRingBuffer.Length()); - - NANOCLR_NOCLEANUP_NOLABEL(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - (void)stack; - - // abort any transfer in progress, just in case - sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); - sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - - platform_free(UsbStream_PAL.RxBuffer); - UsbStream_PAL.RxBuffer = NULL; - - NANOCLR_NOCLEANUP_NOLABEL(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - const char *deviceDescription; - const char *deviceClassGuid; - int32_t bufferSize; - - // int32_t bufferSize; - - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); - - // get device class GUID - deviceClassGuid = stack.Arg1().RecoverString(); - - // clear destination - memset(UsbClassVendorDeviceInterfaceGuid, 0, sizeof(UsbClassVendorDeviceInterfaceGuid)); - - for (uint16_t i = 0; i < sizeof(UsbClassVendorDeviceInterfaceGuid); i += 2) - { - UsbClassVendorDeviceInterfaceGuid[i] = *deviceClassGuid++; - } - - // get description - deviceDescription = stack.Arg2().RecoverString(); - FAULT_ON_NULL(deviceDescription); - - // store device description - hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); - - if (sli_usbd_vendor_winusb_init() != SL_STATUS_OK) - { - NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); - } - - // alloc buffer memory - bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; - UsbStream_PAL.RxBuffer = (uint8_t *)platform_malloc(bufferSize); - - // sanity check - if (UsbStream_PAL.RxBuffer == NULL) - { - NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); - } - - // init buffer - UsbStream_PAL.RxRingBuffer.Initialize(UsbStream_PAL.RxBuffer, bufferSize); - - stack.SetResult_I4(sl_usbd_vendor_winusb_number); - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrite___VOID__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VOID__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -199,6 +98,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit // dereference the data buffer from the argument dataBuffer = stack.Arg1().DereferenceArray(); + FAULT_ON_NULL_ARG(dataBuffer); + offset = stack.Arg2().NumericByRef().s4; count = stack.Arg3().NumericByRef().s4; @@ -210,7 +111,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit if ((offset > length) || (count > length)) { - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); } if (offset + count > length) @@ -283,7 +184,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeWrit NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead___I4__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -312,6 +213,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead // dereference the data buffer from the argument dataBuffer = stack.Arg1().DereferenceArray(); + FAULT_ON_NULL_ARG(dataBuffer); + offset = stack.Arg2().NumericByRef().s4; count = stack.Arg3().NumericByRef().s4; @@ -323,7 +226,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead if ((offset > length) || (count > length)) { - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); } if (offset + count > length) @@ -400,6 +303,107 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeRead NANOCLR_NOCLEANUP(); } +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + bool conn; + + if (sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) + { + stack.SetResult_Boolean(conn); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // get length of Rx ring buffer + stack.SetResult_U4(UsbStream_PAL.RxRingBuffer.Length()); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + (void)stack; + + // abort any transfer in progress, just in case + sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); + + platform_free(UsbStream_PAL.RxBuffer); + UsbStream_PAL.RxBuffer = NULL; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + const char *deviceDescription; + const char *deviceClassGuid; + int32_t bufferSize; + + // int32_t bufferSize; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get device class GUID + deviceClassGuid = stack.Arg1().RecoverString(); + + // clear destination + memset(UsbClassVendorDeviceInterfaceGuid, 0, sizeof(UsbClassVendorDeviceInterfaceGuid)); + + for (uint16_t i = 0; i < sizeof(UsbClassVendorDeviceInterfaceGuid); i += 2) + { + UsbClassVendorDeviceInterfaceGuid[i] = *deviceClassGuid++; + } + + // get description + deviceDescription = stack.Arg2().RecoverString(); + FAULT_ON_NULL(deviceDescription); + + // store device description + hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); + + if (sli_usbd_vendor_winusb_init() != SL_STATUS_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // alloc buffer memory + bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; + UsbStream_PAL.RxBuffer = (uint8_t *)platform_malloc(bufferSize); + + // sanity check + if (UsbStream_PAL.RxBuffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // init buffer + UsbStream_PAL.RxRingBuffer.Initialize(UsbStream_PAL.RxBuffer, bufferSize); + + stack.SetResult_I4(sl_usbd_vendor_winusb_number); + + NANOCLR_NOCLEANUP(); +} + HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( CLR_RT_StackFrame &stack) { From f0335bf2802540e069c5209cc147ce012e43cc8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 9 Nov 2022 17:45:58 +0000 Subject: [PATCH 293/572] Add linker file for Release build - Update block storage configuration for release build. --- .../common/Device_BlockStorage.c | 23 +- .../nanoBooter/efm32gg11b_booter.ld | 235 +++++++++++++++++ .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 3 - .../SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld | 246 ++++++++++++++++++ 4 files changed, 492 insertions(+), 15 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c index dcf2d55e8c..fffa338a97 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c @@ -9,38 +9,37 @@ // 2kB blocks const BlockRange BlockRange1[] = { - // 08000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 10}, + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - // 0800B000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 11, 158}, + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 64}, - // 0804F800 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, + // 00041000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 65, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the // configuration manager files to the CMake and call ConfigurationManager_Initialize() // in nanoBooter so the configuration can be managed when in booter mode /////////////////////////////////////////////////////////////////////////////////////// - // 080FF800 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, /////////////////////////////////////////////////////////////////////////////////////// }; const BlockRegionInfo BlockRegions[] = { { - // STM32L4 flash requires 64bits width programming - (BlockRegionAttribute_ProgramWidthIs64bits), + (0), // start address for block region - 0x08000000, + 0x00000000, // total number of blocks in this region 512, // total number of bytes per block - 0x800, + 0x1000, ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld index 58e8ea7a09..ed9e23d4cc 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -237,9 +237,6 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if flash0 usage exceeds flash0 size */ - ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") } /* Code rules inclusion.*/ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..713b624d56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1784k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00041000, len = 1784k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld From eb933e6cfb2fd5fa2e413f8d44705ffdcfb60696 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 09:39:36 +0000 Subject: [PATCH 294/572] Add LED feedback for status - Fast blink READY LED for nanoBooter and slow blink when running nanoCLR. - Clean up commented code. --- .../SKY_EEVB_PROTO1/nanoBooter/main.c | 32 +++++-------------- .../SKY_EEVB_PROTO1/nanoCLR/main.c | 28 +++------------- 2 files changed, 13 insertions(+), 47 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c index a390e72e55..f0170df77e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -45,8 +45,6 @@ extern void ReceiverThread_entry(uint32_t parameter); TX_THREAD blinkThread; ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; -TX_THREAD blinkThread1; -ALIGN_TYPE blinkThread1Stack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; void BlinkThread_entry(uint32_t parameter) { @@ -54,22 +52,11 @@ void BlinkThread_entry(uint32_t parameter) while (1) { - GPIO_PinOutToggle(gpioPortB, 0); + GPIO_PinOutToggle(gpioPortE, 9); tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); } } -void BlinkThread1_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); - //GPIO_PinOutToggle(gpioPortB, 1); - } -} - void tx_application_define(void *first_unused_memory) { (void)first_unused_memory; @@ -180,16 +167,13 @@ int main(void) // Initialize the board sl_system_init(); - // configure - // GPIO_PinModeSet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN, gpioModeInput, 0); - GPIO_PinModeSet(gpioPortB, 0, gpioModePushPull, 0); - -// // output HFRCO onto PD7 -// GPIO_PinModeSet(gpioPortD, 7, gpioModePushPull, 0); -// CMU->ROUTELOC0 = CMU_ROUTELOC0_CLKOUT0LOC_LOC2; -// CMU->CTRL |= CMU_CTRL_CLKOUTSEL0_USHFRCOQ; -// CMU->ROUTEPEN = CMU_ROUTEPEN_CLKOUT0PEN; - + // configure LED READY for output + GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); + // while (1) + // { + // __NOP(); + // } + /* Hang here forever... */ // init boot clipboard InitBootClipboard(); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c index 2c2caa70e4..6a3541eb42 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -77,29 +77,8 @@ void BlinkThread_entry(uint32_t parameter) while (1) { - //GPIO_PinOutToggle(BSP_GPIO_LED0_PORT, BSP_GPIO_LED0_PIN + 1); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(250)); - - // // Wait for device connection. - // reqStatus = sl_usbd_vendor_is_enabled(1, &conn); - // _ASSERTE(reqStatus == SL_STATUS_OK); - - // while (conn != true) - // { - // tx_thread_sleep(TX_TICKS_PER_MILLISEC(250)); - - // reqStatus = sl_usbd_vendor_is_enabled(1, &conn); - - // _ASSERTE(reqStatus == SL_STATUS_OK); - // } - - // reqStatus = sl_usbd_vendor_read_bulk_sync(1, - // (void *)buffer, - // 3, - // 0, - // &p_xfer_len); - - // _ASSERTE(reqStatus == SL_STATUS_OK); + GPIO_PinOutToggle(gpioPortE, 9); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); } } @@ -225,6 +204,9 @@ int main(void) { sl_system_init(); + // configure LED READY for output + GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); + // init boot clipboard InitBootClipboard(); From 09d86389eaf44263d6811fa44ed2e0d6e457b4bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 10:47:39 +0000 Subject: [PATCH 295/572] Remove code starting second blink thread - Missed commit eb933e6cfb2fd5fa2e413f8d44705ffdcfb60696. --- .../SKY_EEVB_PROTO1/nanoBooter/main.c | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c index f0170df77e..81a7cf8dca 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -101,26 +101,6 @@ void tx_application_define(void *first_unused_memory) } } - // Create blink thread - status = tx_thread_create( - &blinkThread1, - "Blink Thread1", - BlinkThread1_entry, - 0, - (uint8_t *)blinkThread1Stack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - // Create receiver thread status = tx_thread_create( &receiverThread, From 8910369a2dc289676ec038bd86894766640e46c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 11:19:02 +0000 Subject: [PATCH 296/572] Fix SPI index bus access --- ...tive_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index b35f4c36ea..aa872990c5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -564,8 +564,9 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ // get bus index busIndex = (int8_t)stack.Arg1().NumericByRef().s4; - // SPI bus index is 1 based, but the array is 0 based - BusConfigChangesPending[busIndex - 1] = true; + BusConfigChangesPending[busIndex] = true; + + NANOCLR_NOCLEANUP(); NANOCLR_NOCLEANUP(); } \ No newline at end of file From 01076a63cc0e28084927d63d098fb2aa24a53c7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 11:33:09 +0000 Subject: [PATCH 297/572] Update Skyworks SPI - Update assembly declaration. - Implement native get bus speed. - Following Skyworks-Timing-Software/MCU#27. --- .../com_sky_nf_dev_spi_native.cpp | 5 +- .../com_sky_nf_dev_spi_native.h | 1 + ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 95 ++++++++++++++++++- 3 files changed, 98 insertions(+), 3 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index 4a6b82f253..68ff4292d6 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -28,6 +28,7 @@ static const CLR_RT_MethodHandler method_lookup[] = Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4, NULL, NULL, NULL, @@ -39,9 +40,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = { "Com.SkyworksInc.NanoFramework.Devices.Spi", - 0x294C1D50, + 0xAAF7F1A5, method_lookup, - { 100, 0, 0, 3 } + { 100, 0, 0, 4 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index aebf5f005f..9042fcc9bc 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -53,6 +53,7 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN); NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN); NANOCLR_NATIVE_DECLARE(NativeReportBusSettingsChanged___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4); //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index aa872990c5..8cefd984ed 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -567,6 +567,99 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ BusConfigChangesPending[busIndex] = true; NANOCLR_NOCLEANUP(); +} + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4( + CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NF_PAL_SPI *palSpi = NULL; + int8_t busIndex; + uint32_t clockDivValue; + uint32_t refFreq; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // get bus index + // Gecko SPI bus index is 0 based + busIndex = (int8_t)stack.Arg1().NumericByRef().s4 - 1; + + // get the PAL struct for the SPI bus + switch (busIndex) + { +#if GECKO_USE_SPI0 == TRUE + case 0: + palSpi = &SPI0_PAL; + + break; +#endif + +#if GECKO_USE_SPI1 == TRUE + case 1: + palSpi = &SPI1_PAL; + + break; +#endif + +#if GECKO_USE_SPI2 == TRUE + case 2: + palSpi = &SPI2_PAL; + + break; +#endif + +#if GECKO_USE_SPI3 == TRUE + case 3: + palSpi = &SPI3_PAL; + + break; +#endif + +#if GECKO_USE_SPI4 == TRUE + case 4: + palSpi = &SPI4_PAL; + break; +#endif + +#if GECKO_USE_SPI5 == TRUE + case 5: + palSpi = &SPI5_PAL; + + break; +#endif + + default: + // the requested SPI bus is not valid + return false; + } + + // The divider field of the USART->CLKDIV register is of the following form: + // xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider + // The driver it's only setting the integral part of the divider, so we just need to + // rotate the value 5 + 3 bits to the right to get the actual divider value + + clockDivValue = palSpi->Handle->peripheral.usartPort->CLKDIV >> 8; +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (palSpi->Handle->peripheral.usartPort == USART2) + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } + else + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + + stack.SetResult_I4(clockDivValue * refFreq); NANOCLR_NOCLEANUP(); -} \ No newline at end of file +} From c14a7a9089a51ae1fcbf330059e717c6a74ebaa6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 11:33:23 +0000 Subject: [PATCH 298/572] Fix SPI bus index access --- ...ative_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 8cefd984ed..232e6d7fb9 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -118,7 +118,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) if (stack.m_customState == 0) { // check if this SPI has been initialized - palSpi = GetNfPalfromBusIndex(busIndex); + palSpi = GetNfPalfromBusIndex(busIndex - 1); if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex - 1]) { @@ -289,7 +289,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // return of CLR_E_BUSY means async started hr = SPI_nWrite_nRead( palSpi, - SpiConfigs[busIndex], + SpiConfigs[busIndex - 1], rws, (uint8_t *)writeData, (int32_t)writeSize, From a6628b6a731d14479e45f4baaba8f6098f6cb2cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 12:23:16 +0000 Subject: [PATCH 299/572] Update UsbStream declaration - Following nanoframework/System.Device.UsbClient#18. --- .../sys_dev_usbstream_native.cpp | 18 +-- .../sys_dev_usbstream_native.h | 9 +- ...tive_System_Device_Usb_UsbStream_stubs.cpp | 36 +----- .../autogen/sl_usbd_class_vendor_instances.h | 1 - ...eam_native_System_Device_Usb_UsbStream.cpp | 115 ++++-------------- .../sys_dev_usbstream_native_target.h | 4 - .../SiliconLabs/_nanoCLR/targetHAL.cpp | 6 - 7 files changed, 28 insertions(+), 161 deletions(-) diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp index 5e45804279..0340277c6f 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.cpp @@ -41,7 +41,6 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4, NULL, NULL, @@ -50,34 +49,21 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, NULL, NULL, NULL, NULL, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID, Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING, - Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4, - NULL, - NULL, - NULL, - NULL, NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Device_UsbStream = { "System.Device.UsbStream", - 0x6F6BE161, + 0x21BF24CB, method_lookup, - { 100, 0, 0, 4 } + { 100, 0, 0, 6 } }; // clang-format on diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native.h b/src/System.Device.UsbStream/sys_dev_usbstream_native.h index 6ee1b90532..aaae100c56 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native.h +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native.h @@ -19,7 +19,6 @@ // UsbEventType_Invalid = 0, // UsbEventType_DeviceConnected = 1, // UsbEventType_DeviceDisconnected = 2, -// UsbEventType_DataAvailable = 3, // } UsbEventType; struct Library_sys_dev_usbstream_native_System_Device_Usb_DeviceConnectionEventArgs @@ -54,19 +53,13 @@ struct Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream static const int FIELD___disposed = 3; static const int FIELD___writeTimeout = 4; static const int FIELD___readTimeout = 5; - static const int FIELD___receivedBytesThreshold = 6; - static const int FIELD___bufferSize = 7; - static const int FIELD__UsbDeviceConnectionChanged = 8; - static const int FIELD__DataReceived = 9; + static const int FIELD__UsbDeviceConnectionChanged = 6; - NANOCLR_NATIVE_DECLARE(Flush___VOID); NANOCLR_NATIVE_DECLARE(Read___I4__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(Write___VOID__SZARRAY_U1__I4__I4); NANOCLR_NATIVE_DECLARE(get_IsConnected___BOOLEAN); - NANOCLR_NATIVE_DECLARE(get_BytesToRead___I4); NANOCLR_NATIVE_DECLARE(NativeClose___VOID); NANOCLR_NATIVE_DECLARE(NativeOpen___I4__STRING__STRING); - NANOCLR_NATIVE_DECLARE(NativeReceivedBytesThreshold___VOID__I4); //--// }; diff --git a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp index 9ae6003c96..839a3c7290 100644 --- a/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp +++ b/src/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream_stubs.cpp @@ -5,15 +5,6 @@ #include -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - - NANOCLR_NOCLEANUP(); -} - HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -32,26 +23,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConnected___BOOLEAN( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -60,8 +32,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClos NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); @@ -70,8 +41,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen___I4__STRING__STRING( CLR_RT_StackFrame &stack ) { NANOCLR_HEADER(); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h index 3a39905eb1..0e763ef420 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -14,7 +14,6 @@ typedef enum __nfpack UsbEventType UsbEventType_Invalid = 0, UsbEventType_DeviceConnected = 1, UsbEventType_DeviceDisconnected = 2, - UsbEventType_DataAvailable = 3, } UsbEventType; #define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index b337d4c2d4..54d3aecc82 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -60,16 +60,7 @@ static void UsbAsyncReadCompleted( // -- // -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Flush___VOID(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VOID__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -123,7 +114,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO data = dataBuffer->GetElement(offset); // setup timeout from managed property - hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___readTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); // this is a long running operation... @@ -134,15 +125,17 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO // bump custom state stack.m_customState = 2; - // start write operation with async API + // clear RX counter + UsbStream_PAL.RxBytesReceived = 0; + + // start read operation with async API // requesting handling of "End-of-transfer" - reqStatus = sl_usbd_vendor_write_bulk_async( + reqStatus = sl_usbd_vendor_read_bulk_async( sl_usbd_vendor_winusb_number, (void *)data, count, - UsbAsyncWriteCompleted, - &UsbStream_PAL, - true); + UsbAsyncReadCompleted, + &UsbStream_PAL); if (reqStatus == SL_STATUS_INVALID_STATE) { @@ -160,7 +153,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO { // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); if (eventResult) { @@ -171,7 +164,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO { // timeout has expired // cancel the async operation... - sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); // ... return exception NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); @@ -180,11 +173,13 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO // pop timeout heap block from stack stack.PopValue(); + // set result with count of bytes received + stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4__SZARRAY_U1__I4__I4( +HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VOID__SZARRAY_U1__I4__I4( CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -238,7 +233,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ data = dataBuffer->GetElement(offset); // setup timeout from managed property - hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___readTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); + hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); // this is a long running operation... @@ -249,17 +244,15 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ // bump custom state stack.m_customState = 2; - // clear RX counter - UsbStream_PAL.RxBytesReceived = 0; - - // start read operation with async API + // start write operation with async API // requesting handling of "End-of-transfer" - reqStatus = sl_usbd_vendor_read_bulk_async( + reqStatus = sl_usbd_vendor_write_bulk_async( sl_usbd_vendor_winusb_number, (void *)data, count, - UsbAsyncReadCompleted, - &UsbStream_PAL); + UsbAsyncWriteCompleted, + &UsbStream_PAL, + true); if (reqStatus == SL_STATUS_INVALID_STATE) { @@ -277,7 +270,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ { // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbIn, eventResult)); + g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, Event_UsbOut, eventResult)); if (eventResult) { @@ -288,7 +281,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ { // timeout has expired // cancel the async operation... - sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); + sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); // ... return exception NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); @@ -297,8 +290,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ // pop timeout heap block from stack stack.PopValue(); - // set result with count of bytes received - stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); NANOCLR_NOCLEANUP(); } @@ -322,16 +313,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConn NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_BytesToRead___I4(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - // get length of Rx ring buffer - stack.SetResult_U4(UsbStream_PAL.RxRingBuffer.Length()); - - NANOCLR_NOCLEANUP_NOLABEL(); -} - HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -342,9 +323,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClos sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - platform_free(UsbStream_PAL.RxBuffer); - UsbStream_PAL.RxBuffer = NULL; - NANOCLR_NOCLEANUP_NOLABEL(); } @@ -355,7 +333,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen const char *deviceDescription; const char *deviceClassGuid; - int32_t bufferSize; // int32_t bufferSize; @@ -386,55 +363,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); } - // alloc buffer memory - bufferSize = pThis[FIELD___bufferSize].NumericByRef().s4; - UsbStream_PAL.RxBuffer = (uint8_t *)platform_malloc(bufferSize); - - // sanity check - if (UsbStream_PAL.RxBuffer == NULL) - { - NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); - } - - // init buffer - UsbStream_PAL.RxRingBuffer.Initialize(UsbStream_PAL.RxBuffer, bufferSize); - stack.SetResult_I4(sl_usbd_vendor_winusb_number); NANOCLR_NOCLEANUP(); } - -HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeReceivedBytesThreshold___VOID__I4( - CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - int32_t threshold; - - // get a pointer to the managed object instance and check that it's not NULL - CLR_RT_HeapBlock *pThis = stack.This(); - FAULT_ON_NULL(pThis); - - // check if threshold is valid - threshold = (int32_t)stack.Arg1().NumericByRef().s4; - - if (threshold <= 0) - { - NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); - } - - // update field - pThis[FIELD___receivedBytesThreshold].NumericByRef().s4 = threshold; - - // update threshold value - UsbStream_PAL.ReceivedBytesThreshold = threshold; - - // fake call to event handler in case the new threshold was set - // to a value lower than the bytes that are already available - if ((uint32_t)threshold <= UsbStream_PAL.RxRingBuffer.Length()) - { - // PostManagedEvent(EVENT_SERIAL, 0, portIndex, SerialData_Chars); - } - - NANOCLR_NOCLEANUP(); -} diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index 9a7a86fd59..ddf7e35ebb 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -23,11 +23,7 @@ extern "C" sl_status_t sli_usbd_vendor_winusb_init(void); // struct representing the UART typedef struct { - HAL_RingBuffer RxRingBuffer; - uint8_t *RxBuffer; - uint16_t RxBytesToRead; uint16_t RxBytesReceived; - uint32_t ReceivedBytesThreshold; uint16_t TxBytesSent; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index c900f55b52..ed8cac613a 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -297,12 +297,6 @@ adc1Initialized = false; sl_usbd_vendor_abort_write_bulk(sl_usbd_vendor_winusb_number); sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - if(UsbStream_PAL.RxBuffer != NULL) - { - platform_free(UsbStream_PAL.RxBuffer); - UsbStream_PAL.RxBuffer = NULL; - } - #endif // #if (HAL_USE_UART == TRUE) From 34562bf1a8b7dbf94fa8fee0f6de46332c8f95c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 10 Nov 2022 14:14:42 +0000 Subject: [PATCH 300/572] Clean up unused init for winusb --- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c index 6a3541eb42..311aa0c1e5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -189,10 +189,6 @@ void tx_application_define(void *first_unused_memory) usb_device_hid_app_init(); #endif -#if GECKO_FEATURE_USBD_WINUSB == TRUE - //sli_usbd_vendor_winusb_init(); -#endif - #if HAL_WP_USE_USB_CDC == TRUE sli_usbd_cdc_acm_acm0_init(); usb_device_cdc_acm_app_init(); From a11d7de826cf442f4a32cdb115d12dea3df1ca2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 14 Nov 2022 09:16:37 +0000 Subject: [PATCH 301/572] Work in Skyworks SPI - Update assembly declaration. - Rework code accordingly. - Improvements in handling bus index. --- .../com_sky_nf_dev_spi_native.cpp | 8 +- .../com_sky_nf_dev_spi_native.h | 4 +- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 156 +++++++----------- .../sys_dev_spi_native_target.h | 6 + 4 files changed, 72 insertions(+), 102 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index 68ff4292d6..cc1c28a434 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -25,8 +25,8 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN, - Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + NULL, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4, NULL, @@ -40,9 +40,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = { "Com.SkyworksInc.NanoFramework.Devices.Spi", - 0xAAF7F1A5, + 0x060333BF, method_lookup, - { 100, 0, 0, 4 } + { 100, 0, 0, 5 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 9042fcc9bc..5e328a1e69 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -50,8 +50,8 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S static const int FIELD___syncLock = 1; static const int FIELD___bufferSingleOperation = 2; - NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN); - NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + NANOCLR_NATIVE_DECLARE( + NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); NANOCLR_NATIVE_DECLARE(NativeReportBusSettingsChanged___VOID__I4); NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 232e6d7fb9..c86975885b 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -75,14 +75,11 @@ bool System_Device_IsLongRunningOperation( } } -HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) +HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - CLR_IDX assemblyIdx; - CLR_RT_Assembly *thisAssembly = NULL; CLR_RT_HeapBlock *config = NULL; - CLR_RT_HeapBlock_Array *busConnectionSettings; CLR_RT_HeapBlock_Array *writeBuffer; CLR_RT_HeapBlock_Array *readBuffer; CLR_RT_HeapBlock *writeSpanByte; @@ -113,27 +110,22 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) busIndex = (int8_t)stack.Arg1().NumericByRef().s4; // SPI bus index is 1 based, but the array is 0 based - spiDeviceConfig = &SpiConfigs[busIndex - 1]; + busIndex--; + + spiDeviceConfig = &SpiConfigs[busIndex]; if (stack.m_customState == 0) { // check if this SPI has been initialized - palSpi = GetNfPalfromBusIndex(busIndex - 1); + palSpi = GetNfPalfromBusIndex(busIndex); - if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex - 1]) + if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex]) { // SPI bus not initialized or config changes pending // compose SPI_DEVICE_CONFIGURATION - // get ref to SpiBaseConfiguration from static _busConnectionSettings array... - // need to access it through the assembly - assemblyIdx = pThis->ObjectCls().Assembly(); - thisAssembly = g_CLR_RT_TypeSystem.m_assemblies[assemblyIdx - 1]; - busConnectionSettings = - thisAssembly->GetStaticField(Devices_Spi_SpiBus::FIELD_STATIC___busConnectionSettings) - ->DereferenceArray(); - // ...access it by index, which is 0 based - config = ((CLR_RT_HeapBlock *)busConnectionSettings->GetElement(busIndex - 1))->Dereference(); + // get SpiBaseConfiguration from argument + config = stack.Arg5().Dereference(); // CS is always active low spiDeviceConfig->ChipSelectActive = false; @@ -142,7 +134,8 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) // always bus master spiDeviceConfig->BusMode = SpiBusMode_master; - spiDeviceConfig->Spi_Bus = busIndex; + // SPI bus index is 1 based, but the array is 0 based + spiDeviceConfig->Spi_Bus = busIndex + 1; spiDeviceConfig->Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiMode].NumericByRef().s4; spiDeviceConfig->DataOrder16 = @@ -159,88 +152,59 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack, bool isSpanByte) CPU_SPI_Initialize_Extended(busIndex, *spiDeviceConfig, true); // lower changes pending flag - BusConfigChangesPending[busIndex - 1] = false; + BusConfigChangesPending[busIndex] = false; } - // Buffers used either for the SpanBye either for the Byte array + // dereference the write and read SpanByte from the arguments + writeSpanByte = stack.Arg2().Dereference(); - if (isSpanByte) + if (writeSpanByte != NULL) { - // dereference the write and read SpanByte from the arguments - writeSpanByte = stack.Arg2().Dereference(); - - if (writeSpanByte != NULL) - { - // get buffer - writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); - - if (writeBuffer != NULL) - { - // Get the write offset, only the elements defined by the span must be written, not the whole - // array - writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; - - // use the span length as write size, only the elements defined by the span must be written - writeSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; - writeData = (unsigned char *)writeBuffer->GetElement(writeOffset); - } - } - - if (writeData == NULL) - { - // nothing to write, have to zero this - writeSize = 0; - } - - readSpanByte = stack.Arg3().Dereference(); + // get buffer + writeBuffer = writeSpanByte[SpanByte::FIELD___array].DereferenceArray(); - if (readSpanByte != NULL) + if (writeBuffer != NULL) { - // get buffer - readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); - - if (readBuffer != NULL) - { - // Get the read offset, only the elements defined by the span must be read, not the whole array - readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; + // Get the write offset, only the elements defined by the span must be written, not the whole + // array + writeOffset = writeSpanByte[SpanByte::FIELD___start].NumericByRef().s4; - // use the span length as read size, only the elements defined by the span must be read - readSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; - readData = (unsigned char *)readBuffer->GetElement(readOffset); - } - } - - if (readData == NULL) - { - // nothing to read, have to zero this - readSize = 0; + // use the span length as write size, only the elements defined by the span must be written + writeSize = writeSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + writeData = (unsigned char *)writeBuffer->GetElement(writeOffset); } } - else - { - writeBuffer = stack.Arg2().DereferenceArray(); - if (writeBuffer != NULL) - { - // grab the pointer to the array by getting the first element of the array - writeData = (unsigned char *)writeBuffer->GetFirstElementUInt16(); + if (writeData == NULL) + { + // nothing to write, have to zero this + writeSize = 0; + } - // get the size of the buffer by reading the number of elements in the HeapBlock array - writeSize = writeBuffer->m_numOfElements; - } + readSpanByte = stack.Arg3().Dereference(); - readBuffer = stack.Arg3().DereferenceArray(); + if (readSpanByte != NULL) + { + // get buffer + readBuffer = readSpanByte[SpanByte::FIELD___array].DereferenceArray(); if (readBuffer != NULL) { - // grab the pointer to the array by getting the first element of the array - readData = (unsigned char *)readBuffer->GetFirstElementUInt16(); + // Get the read offset, only the elements defined by the span must be read, not the whole array + readOffset = readSpanByte[SpanByte::FIELD___start].NumericByRef().s4; - // get the size of the buffer by reading the number of elements in the HeapBlock array - readSize = readBuffer->m_numOfElements; + // use the span length as read size, only the elements defined by the span must be read + readSize = readSpanByte[SpanByte::FIELD___length].NumericByRef().s4; + readData = (unsigned char *)readBuffer->GetElement(readOffset); } } + if (readData == NULL) + { + // nothing to read, have to zero this + readSize = 0; + } + // assuming full duplex all the time fullDuplex = true; @@ -531,21 +495,12 @@ static HRESULT SPI_nWrite_nRead( } HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: - NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN(CLR_RT_StackFrame &stack) + NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - NANOCLR_CHECK_HRESULT(ExecuteTransfer(stack, true)); - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: - NativeTransfer___VOID__I4__SZARRAY_U2__SZARRAY_U2__BOOLEAN(CLR_RT_StackFrame &stack) -{ - NANOCLR_HEADER(); - - NANOCLR_CHECK_HRESULT(ExecuteTransfer(stack, false)); + NANOCLR_CHECK_HRESULT(ExecuteTransfer(stack)); NANOCLR_NOCLEANUP(); } @@ -561,8 +516,8 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ CLR_RT_HeapBlock *pThis = stack.This(); FAULT_ON_NULL(pThis); - // get bus index - busIndex = (int8_t)stack.Arg1().NumericByRef().s4; + // SPI bus index is 1 based, but the array is 0 based + busIndex = (int8_t)stack.Arg1().NumericByRef().s4 - 1; BusConfigChangesPending[busIndex] = true; @@ -578,6 +533,7 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ int8_t busIndex; uint32_t clockDivValue; uint32_t refFreq; + uint32_t realClk; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -633,7 +589,13 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ default: // the requested SPI bus is not valid - return false; + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex]) + { + // the configuration has not been set yet, or there are pending changes + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); } // The divider field of the USART->CLKDIV register is of the following form: @@ -659,7 +621,9 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ #endif #endif - stack.SetResult_I4(clockDivValue * refFreq); + realClk = (refFreq - 1) / (2 * clockDivValue); + + stack.SetResult_I4(realClk); NANOCLR_NOCLEANUP(); } diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index 77c15b72d8..76482f3d71 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -63,6 +63,12 @@ #define GECKO_USE_SPI5 FALSE #endif +// adjust number of buses +#if defined(NUM_SPI_BUSES) +#undef NUM_SPI_BUSES +#endif +#define NUM_SPI_BUSES 6 + // struct representing the SPI bus struct NF_PAL_SPI { From fa4392d8e640e43686fc14afa51488cc32bca2a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 16 Nov 2022 17:04:19 +0000 Subject: [PATCH 302/572] Fix compiler defs in adc controller init --- ..._adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 2dbbdd0ad7..4259f3c83d 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -73,13 +73,13 @@ HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration // is this ADC already initialized? if ( -#if GECKO_USE_ADC0 && !GECKO_USE_ADC1 +#if GECKO_USE_ADC0 (adcDriver == ADC0 && !*adcInitialized) #endif #if GECKO_USE_ADC0 && GECKO_USE_ADC1 || #endif -#if !GECKO_USE_ADC0 && GECKO_USE_ADC1 +#if GECKO_USE_ADC1 (adcDriver == ADC1 && !*adcInitialized) #endif ) From 996436bb61e22aca0348af6fd08797a02f8e1071 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 16 Nov 2022 17:05:33 +0000 Subject: [PATCH 303/572] Fix ADC controller initialization - Add call to ADC_Reset. - Disable EM2 clock. --- ..._adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp index 4259f3c83d..ff93141af5 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/nanoFramework.GiantGecko.Adc/nano_gg_adc_native_nanoFramework_GiantGecko_Adc_AdcController.cpp @@ -109,9 +109,11 @@ HRESULT OpenAdcChannel(int32_t channelNumber, CLR_RT_HeapBlock *adcConfiguration adcInit->timebase = ADC_TimebaseCalc(0); #if defined(_ADC_CTRL_ADCCLKMODE_MASK) - adcInit->em2ClockConfig = adcEm2ClockOnDemand; + adcInit->em2ClockConfig = adcEm2Disabled; #endif + ADC_Reset(adcDriver); + // init ADC ADC_Init(adcDriver, adcInit); From 2e79f3bc2faec4d0302bef3cf695e1695b122d65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 21 Nov 2022 13:42:58 +0000 Subject: [PATCH 304/572] Fix CMake path for dev container ***NO_CI*** --- .devcontainer/devcontainer.json | 1 - 1 file changed, 1 deletion(-) diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json index 986f4164a6..71cc17578a 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/devcontainer.json @@ -26,7 +26,6 @@ "cmake.configureSettings": { "CMAKE_MAKE_PROGRAM":"/usr/bin/ninja" }, - "cmake.cmakePath": "/usr/bin/cmake", "cmake.configureOnOpen": false }, // Add the IDs of extensions you want installed when the container is created. From fccf69d8b5f44cef0193de0a660dae3c05bc1928 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 21 Nov 2022 18:51:47 +0000 Subject: [PATCH 305/572] Improvements in UsbStream write operation - Optimization to use async write only if needed. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 54d3aecc82..ef958c8c35 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -129,7 +129,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ UsbStream_PAL.RxBytesReceived = 0; // start read operation with async API - // requesting handling of "End-of-transfer" reqStatus = sl_usbd_vendor_read_bulk_async( sl_usbd_vendor_winusb_number, (void *)data, @@ -194,6 +193,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; + uint32_t xfer_len; + bool isLongRunning = false; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -236,8 +237,14 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO hbTimeout.SetInteger((CLR_INT64)pThis[FIELD___writeTimeout].NumericByRef().s4 * TIME_CONVERSION__TO_MILLISECONDS); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(hbTimeout, timeoutTicks)); + // check if it's worth to use async API + if (count > 64) + { + isLongRunning = true; + } + // this is a long running operation... - if (stack.m_customState == 1) + if (isLongRunning && stack.m_customState == 1) { // ... and hasn't started yet @@ -252,7 +259,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO count, UsbAsyncWriteCompleted, &UsbStream_PAL, - true); + false); if (reqStatus == SL_STATUS_INVALID_STATE) { @@ -265,8 +272,20 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); } } + else + { + // start write operation with async API + // requesting handling of "End-of-transfer" + reqStatus = sl_usbd_vendor_write_bulk_sync( + sl_usbd_vendor_winusb_number, + (void *)data, + count, + *timeoutTicks, + false, + &xfer_len); + } - while (eventResult) + while (isLongRunning && eventResult) { // non-blocking wait allowing other threads to run while we wait for the USB operation to complete NANOCLR_CHECK_HRESULT( From 3ce8546c0cdd68c4a45a51633e3bd9bf558c73d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 24 Nov 2022 18:06:08 +0000 Subject: [PATCH 306/572] Initial work adding support for hardware CRC32 --- .../SiliconLabs/_common/CMakeLists.txt | 2 +- .../SiliconLabs/_common/nanoSupport_CRC32.c | 44 +++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt index e654b32e50..86fbb3bc2c 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_common/CMakeLists.txt @@ -6,7 +6,7 @@ # Azure RTOS ST specific file list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_SL_MscFlashDriver.c) list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c) -# list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c) +list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c) list(APPEND TARGET_AZURERTOS_COMMON_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/sys_calls.c) # append Target files diff --git a/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c b/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c new file mode 100644 index 0000000000..8b27f87d69 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c @@ -0,0 +1,44 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include > +#include +#include +#include + +// strong implementation of this function specific Gecko targets +uint32_t SUPPORT_ComputeCRC(const void *rgBlock, const uint32_t nLength, const uint32_t crc) +{ + // Prepare GPCRC_DATA for inputs + GPCRC_Start(GPCRC); + + + + uint32_t myCrc = crcCompute(rgBlock, nLength, crc); + + crcReleaseModule(); + + return myCrc; +}; + +void InitGpCrc(void) +{ + // Enable clocks required + CMU_ClockEnable(cmuClock_GPCRC, true); + + // Declare init structs + GPCRC_Init_TypeDef init = GPCRC_INIT_DEFAULT; + + // Starting value in GPCRC_DATA + init.initValue = 0x04C11DB7; + // Reset GPCRC_DATA to 0xFFFF_FFFF after every read + init.autoInit = true; + // Reverse all bits of the incoming message + init.reverseBits = true; + + // Initialize GPCRC + GPCRC_Init(GPCRC, &init); +} From 39e4573cb2d2557c2cf3ac42cb4423325ab9712f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 6 Dec 2022 13:18:08 +0000 Subject: [PATCH 307/572] Fix handling USB timeout for write operation --- ...v_usbstream_native_System_Device_Usb_UsbStream.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index ef958c8c35..d1eb27cabe 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -186,6 +186,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO CLR_RT_HeapBlock_Array *dataBuffer; CLR_RT_HeapBlock hbTimeout; int64_t *timeoutTicks; + int16_t timeoutMiliseconds = 0; bool eventResult = true; uint8_t *data; @@ -193,7 +194,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO uint32_t count = 0; uint32_t offset = 0; sl_status_t reqStatus; - uint32_t xfer_len; + uint32_t xfer_len = 0; bool isLongRunning = false; // get a pointer to the managed object instance and check that it's not NULL @@ -274,13 +275,19 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO } else { + if (*timeoutTicks != TIMEOUT_INFINITE) + { + // convert from ticks to milliseconds + timeoutMiliseconds = (int16_t)pThis[FIELD___writeTimeout].NumericByRef().s4; + } + // start write operation with async API // requesting handling of "End-of-transfer" reqStatus = sl_usbd_vendor_write_bulk_sync( sl_usbd_vendor_winusb_number, (void *)data, count, - *timeoutTicks, + timeoutMiliseconds, false, &xfer_len); } From f8ae9726c6e5ed02f6cbb851056858935e2be551 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 6 Dec 2022 13:29:38 +0000 Subject: [PATCH 308/572] Increase block size for SL_STK3701A debug build --- .../AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 4 ++-- .../SL_STK3701A/common/Device_BlockStorage-DEBUG.c | 10 +++++----- .../SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld | 4 ++-- .../SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index 8bd99ba614..da698ef41d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -67,13 +67,13 @@ if(SRECORD_TOOL_AVAILABLE) nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 12000 + 13000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) else() nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 12000 + 13000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) endif() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c index 71c9310708..2b61b85671 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage-DEBUG.c @@ -10,13 +10,13 @@ const BlockRange BlockRange1[] = { // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 17}, + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, - // 00012000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 18, 237}, + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 238}, - // 000EE000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + // 000EF000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 239, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld index 74c3541c99..8941c58e5c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00000000, len = 72k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00012000, len = 0 /* space reserved for application deployment */ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld index bbd167197f..3029b11ab9 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00012000, len = 2M - 72k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x000EE000, len = 904k /* space reserved for application deployment */ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EF000, len = 900k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 856e00327e963a8562b21b1184d0e0139b7d2882 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 6 Dec 2022 13:30:01 +0000 Subject: [PATCH 309/572] Add missing processor defines for USB configuration --- .../SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h | 4 ++++ .../System.Device.UsbStream/sys_dev_usbstream_native_target.h | 1 + 2 files changed, 5 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h index 8a31e51491..c870d532f6 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_device_config.h @@ -56,6 +56,10 @@ extern char *UsbSerialNumber[]; // Default: USBD_LANG_ID_ENGLISH_US #define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US +#define USBD_CFG_HS_EN 0 +#define USBD_CFG_EP_ISOC_EN 0 +#define USBD_CFG_OPTIMIZE_SPD 0 + // // <<< end of configuration section >>> diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index ddf7e35ebb..121cffeea4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -10,6 +10,7 @@ ////////////////////////////////////////////////////////////////////////////////////////////////////// #define USBD_CFG_HS_EN 0 #define USBD_CFG_EP_ISOC_EN 0 +#define USBD_CFG_OPTIMIZE_SPD 0 ////////////////////////////////////////////////////////////////////////////////////////////////////// #include From 17b3123bdf0b200fcec7f9acbfbab6b897cd229e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 6 Dec 2022 18:00:02 +0000 Subject: [PATCH 310/572] Adjust loop in wait for events to improve global responsiveness --- targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp b/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp index 6188ea35f7..670fd50311 100644 --- a/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp +++ b/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp @@ -100,7 +100,7 @@ uint32_t Events_WaitForEvents(uint32_t powerLevel, uint32_t wakeupSystemEvents, } // no events, pass control to the OS - tx_thread_sleep(TX_TICKS_PER_MILLISEC(100)); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1)); // check if reboot or exit flags were set when the other OS threads executed if (CLR_EE_DBG_IS(RebootPending) || CLR_EE_DBG_IS(ExitPending)) From 88db897f4ad4f4c447cf1f409e6164d5b163f0c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 6 Dec 2022 19:14:34 +0000 Subject: [PATCH 311/572] Fix configuration manager - Add back commented out code. - Add missing processing for Wireless AP configs. --- .../targetHAL_ConfigurationManager.cpp | 238 +++++++++--------- 1 file changed, 124 insertions(+), 114 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp b/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp index 77f66bb623..238f9c3e83 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp +++ b/targets/AzureRTOS/SiliconLabs/_common/targetHAL_ConfigurationManager.cpp @@ -6,8 +6,7 @@ #include #include #include -// #include -// #include +//#include #if defined(WIFI_DRIVER_ISM43362) && defined(I_AM_NANOCLR) #include @@ -19,9 +18,9 @@ uint32_t GetExistingConfigSize() { uint32_t currentConfigSize = 0; - // currentConfigSize = - // g_TargetConfiguration.NetworkInterfaceConfigs->Count * sizeof(HAL_Configuration_NetworkInterface); - // currentConfigSize += g_TargetConfiguration.Wireless80211Configs->Count * sizeof(HAL_Configuration_Wireless80211); + currentConfigSize = + g_TargetConfiguration.NetworkInterfaceConfigs->Count * sizeof(HAL_Configuration_NetworkInterface); + currentConfigSize += g_TargetConfiguration.Wireless80211Configs->Count * sizeof(HAL_Configuration_Wireless80211); return currentConfigSize; } @@ -35,10 +34,10 @@ __nfweak void ConfigurationManager_Initialize() memset(&stream, 0, sizeof(BlockStorageStream)); BlockStorageStream_Initialize(&stream, BlockUsage_CONFIG); - BlockStorageDevice* device = BlockStorageList_GetFirstDevice(); - DeviceBlockInfo * deviceBlockInfo = BlockStorageDevice_GetDeviceInfo(device); - - if(deviceBlockInfo->Regions[stream.RegionIndex].Attributes & BlockRegionAttribute_ProgramWidthIs64bits) + BlockStorageDevice *device = BlockStorageList_GetFirstDevice(); + DeviceBlockInfo *deviceBlockInfo = BlockStorageDevice_GetDeviceInfo(device); + + if (deviceBlockInfo->Regions[stream.RegionIndex].Attributes & BlockRegionAttribute_ProgramWidthIs64bits) { programWidth = 64 / 8; } @@ -91,39 +90,41 @@ __nfweak void ConfigurationManager_EnumerateConfigurationBlocks() platform_free(networkConfig); } -// // find wireless 80211 network configuration blocks -// HAL_CONFIGURATION_NETWORK_WIRELESS80211 *networkWirelessConfigs = -// (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks( -// (uint32_t)&__nanoConfig_start__, -// (uint32_t)&__nanoConfig_end__); - -// #if (TARGET_HAS_WIFI_SUPPORT == 1) -// if (networkWirelessConfigs->Count == 0) -// { -// // there is no network config block available, get a default -// HAL_Configuration_Wireless80211 *wirelessConfig = -// (HAL_Configuration_Wireless80211 *)platform_malloc(sizeof(HAL_Configuration_Wireless80211)); - -// InitialiseWirelessDefaultConfig(wirelessConfig, 0); - -// // config block created, store it -// ConfigurationManager_StoreConfigurationBlock( -// wirelessConfig, -// DeviceConfigurationOption_Wireless80211Network, -// 0, -// sizeof(HAL_Configuration_Wireless80211), -// 0, -// false); - -// // have to enumerate again to pick it up -// networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *) -// ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks( -// (uint32_t)&__nanoConfig_start__, -// (uint32_t)&__nanoConfig_end__); - -// platform_free(wirelessConfig); -// } -// #endif + // find wireless 80211 network configuration blocks + HAL_CONFIGURATION_NETWORK_WIRELESS80211 *networkWirelessConfigs = + (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks( + (uint32_t)&__nanoConfig_start__, + (uint32_t)&__nanoConfig_end__); + +#if defined(TARGET_HAS_WIFI_SUPPORT) && (TARGET_HAS_WIFI_SUPPORT == 1) + + if (networkWirelessConfigs->Count == 0) + { + // there is no network config block available, get a default + HAL_Configuration_Wireless80211 *wirelessConfig = + (HAL_Configuration_Wireless80211 *)platform_malloc(sizeof(HAL_Configuration_Wireless80211)); + + InitialiseWirelessDefaultConfig(wirelessConfig, 0); + + // config block created, store it + ConfigurationManager_StoreConfigurationBlock( + wirelessConfig, + DeviceConfigurationOption_Wireless80211Network, + 0, + sizeof(HAL_Configuration_Wireless80211), + 0, + false); + + // have to enumerate again to pick it up + networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *) + ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks( + (uint32_t)&__nanoConfig_start__, + (uint32_t)&__nanoConfig_end__); + + platform_free(wirelessConfig); + } + +#endif // find X509 certificate blocks HAL_CONFIGURATION_X509_CERTIFICATE *certificateStore = @@ -142,9 +143,10 @@ __nfweak void ConfigurationManager_EnumerateConfigurationBlocks() // the malloc size for each struct is computed separately uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); - // uint32_t sizeOfWireless80211Configs = - // offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + - // networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + uint32_t sizeOfWireless80211Configs = + offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + + networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + uint32_t sizeOfWirelessAPConfigs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESSAP, Configs); uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + certificateStore->Count * sizeof(certificateStore->Certificates[0]); uint32_t sizeOfX509DeviceCertificate = offsetof(HAL_CONFIGURATION_X509_DEVICE_CERTIFICATE, Certificates) + @@ -152,8 +154,10 @@ __nfweak void ConfigurationManager_EnumerateConfigurationBlocks() g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK *)platform_malloc(sizeOfNetworkInterfaceConfigs); - // g_TargetConfiguration.Wireless80211Configs = - // (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)platform_malloc(sizeOfWireless80211Configs); + g_TargetConfiguration.Wireless80211Configs = + (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)platform_malloc(sizeOfWireless80211Configs); + g_TargetConfiguration.WirelessAPConfigs = + (HAL_CONFIGURATION_NETWORK_WIRELESSAP *)platform_malloc(sizeOfWirelessAPConfigs); g_TargetConfiguration.CertificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE *)platform_malloc(sizeOfX509CertificateStore); g_TargetConfiguration.DeviceCertificates = @@ -164,10 +168,15 @@ __nfweak void ConfigurationManager_EnumerateConfigurationBlocks() (HAL_CONFIGURATION_NETWORK *)g_TargetConfiguration.NetworkInterfaceConfigs, networkConfigs, sizeOfNetworkInterfaceConfigs); + memcpy( + (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)g_TargetConfiguration.Wireless80211Configs, + networkWirelessConfigs, + sizeOfWireless80211Configs); // memcpy( - // (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)g_TargetConfiguration.Wireless80211Configs, - // networkWirelessConfigs, - // sizeOfWireless80211Configs); + // (HAL_CONFIGURATION_NETWORK_WIRELESSAP *)g_TargetConfiguration.WirelessAPConfigs, + // networkWirelessApConfigs, + // sizeOfWirelessAPConfigs); + g_TargetConfiguration.WirelessAPConfigs->Count = 0; memcpy( (HAL_CONFIGURATION_X509_CERTIFICATE *)g_TargetConfiguration.CertificateStore, certificateStore, @@ -179,7 +188,7 @@ __nfweak void ConfigurationManager_EnumerateConfigurationBlocks() // now free the memory of the original structs platform_free(networkConfigs); - // platform_free(networkWirelessConfigs); + platform_free(networkWirelessConfigs); platform_free(certificateStore); platform_free(deviceCertificates); } @@ -323,50 +332,51 @@ __nfweak bool ConfigurationManager_StoreConfigurationBlock( else if (configuration == DeviceConfigurationOption_Wireless80211Network) { -// #if (TARGET_HAS_WIFI_SUPPORT == 1) - -// if (g_TargetConfiguration.Wireless80211Configs == NULL || -// (g_TargetConfiguration.Wireless80211Configs->Count == 0 && configurationIndex == 0)) -// { -// // there is no wireless 80211 config block, so we are storing the default one -// // THIS IS THE SECOND CONFIG BLOCK THAT'S AUTO-CREATED -// // OK to continue -// // set storage address contiguous to the network config block -// storageAddress = (uint32_t)&__nanoConfig_start__ + sizeof(HAL_Configuration_NetworkInterface); - -// // check programming width -// if(programWidth > 0) -// { -// // round address to the next valid programming width -// storageAddress += programWidth - storageAddress % programWidth; -// } -// } -// else -// { -// // the requested config block is beyond the available count -// if ((configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) -// { -// return FALSE; -// } - -// // set storage address from block address, plus the requested offset -// storageAddress = -// (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex] + offset; -// } - -// // set block size, in case it's not already set -// blockSize = sizeof(HAL_Configuration_Wireless80211); - -// // make sure the config block marker is set -// memcpy( -// configurationBlock, -// c_MARKER_CONFIGURATION_WIRELESS80211_V1, -// sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); - -// #else -// // no support for WIFI in this STM32 build -// return FALSE; -// #endif + // #if (TARGET_HAS_WIFI_SUPPORT == 1) + + // if (g_TargetConfiguration.Wireless80211Configs == NULL || + // (g_TargetConfiguration.Wireless80211Configs->Count == 0 && configurationIndex == 0)) + // { + // // there is no wireless 80211 config block, so we are storing the default one + // // THIS IS THE SECOND CONFIG BLOCK THAT'S AUTO-CREATED + // // OK to continue + // // set storage address contiguous to the network config block + // storageAddress = (uint32_t)&__nanoConfig_start__ + sizeof(HAL_Configuration_NetworkInterface); + + // // check programming width + // if(programWidth > 0) + // { + // // round address to the next valid programming width + // storageAddress += programWidth - storageAddress % programWidth; + // } + // } + // else + // { + // // the requested config block is beyond the available count + // if ((configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + // { + // return FALSE; + // } + + // // set storage address from block address, plus the requested offset + // storageAddress = + // (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex] + + // offset; + // } + + // // set block size, in case it's not already set + // blockSize = sizeof(HAL_Configuration_Wireless80211); + + // // make sure the config block marker is set + // memcpy( + // configurationBlock, + // c_MARKER_CONFIGURATION_WIRELESS80211_V1, + // sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + + // #else + // // no support for WIFI in this STM32 build + // return FALSE; + // #endif } else if (configuration == DeviceConfigurationOption_X509CaRootBundle) { @@ -714,38 +724,38 @@ __nfweak bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface { (void)configurationIndex; -// #if (TARGET_HAS_WIFI_SUPPORT == 1) + // #if (TARGET_HAS_WIFI_SUPPORT == 1) -// memset(config, 0, sizeof(HAL_Configuration_NetworkInterface)); + // memset(config, 0, sizeof(HAL_Configuration_NetworkInterface)); -// // make sure the config block marker is set -// memcpy(config->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + // // make sure the config block marker is set + // memcpy(config->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); -// // currently only Wireless station is supported -// config->InterfaceType = NetworkInterfaceType_Wireless80211; -// config->StartupAddressMode = AddressMode_DHCP; -// config->AutomaticDNS = 1; -// config->SpecificConfigId = 0; + // // currently only Wireless station is supported + // config->InterfaceType = NetworkInterfaceType_Wireless80211; + // config->StartupAddressMode = AddressMode_DHCP; + // config->AutomaticDNS = 1; + // config->SpecificConfigId = 0; -// // fill in MAX with 0xFF to allow it updating it later -// memset(config->MacAddress, 0xFF, sizeof(config->MacAddress)); + // // fill in MAX with 0xFF to allow it updating it later + // memset(config->MacAddress, 0xFF, sizeof(config->MacAddress)); -// // get default MAC -// #if defined(WIFI_DRIVER_ISM43362) && defined(I_AM_NANOCLR) -// // OK to ignore the return value, no harm done if it fails -// WIFI_GetMAC_Address(config->MacAddress); -// #endif + // // get default MAC + // #if defined(WIFI_DRIVER_ISM43362) && defined(I_AM_NANOCLR) + // // OK to ignore the return value, no harm done if it fails + // WIFI_GetMAC_Address(config->MacAddress); + // #endif -// return TRUE; + // return TRUE; -// #else + // #else (void)config; // can't create a "default" network config because we are lacking definition of a MAC address return FALSE; -// #endif + // #endif } int32_t ConfigurationManager_FindNetworkConfigurationMatchingWirelessConfigurationFromId(uint32_t configurationId) From c572b019089aa5b19310a78bea3d1e5714f7f276 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 9 Dec 2022 13:47:13 +0000 Subject: [PATCH 312/572] Add hardware implementation for CRC32 calculations - Using GPCRC unit from Gecko. --- CMake/Modules/FindGecko_SDK.cmake | 1 + .../autogen/sl_event_handler_default.c | 3 ++ .../SiliconLabs/_common/nanoSupport_CRC32.c | 30 ++++++++++++------- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 8ecb3ca2cc..3f9655480d 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -75,6 +75,7 @@ set(gecko_sdk_srcs em_csen.c em_emu.c em_ldma.c + em_gpcrc.c em_gpio.c em_i2c.c # em_lcd.c diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c index e33e721d06..04773ff231 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_event_handler_default.c @@ -28,6 +28,8 @@ #include #include +extern void InitGpCrc(void); + // implemented as weak function to allow overriding at platform level __nfweak void sl_platform_init(void) { @@ -41,6 +43,7 @@ __nfweak void sl_platform_init(void) sl_device_init_emu(); sl_board_init(); sl_power_manager_init(); + InitGpCrc(); } // implemented as weak function to allow overriding at platform level diff --git a/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c b/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c index 8b27f87d69..9774c6a459 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c +++ b/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c @@ -4,7 +4,7 @@ // #include -#include > +#include #include #include #include @@ -12,16 +12,26 @@ // strong implementation of this function specific Gecko targets uint32_t SUPPORT_ComputeCRC(const void *rgBlock, const uint32_t nLength, const uint32_t crc) { - // Prepare GPCRC_DATA for inputs - GPCRC_Start(GPCRC); + const uint8_t *ptr = (const uint8_t *)rgBlock; + // anything to do here? + if (nLength == 0) + { + return crc; + } + // set intial value + GPCRC_InitValueSet(GPCRC, crc); - uint32_t myCrc = crcCompute(rgBlock, nLength, crc); + // Prepare GPCRC_DATA for inputs + GPCRC_Start(GPCRC); - crcReleaseModule(); + for (uint32_t i = 0; i < nLength; i++) + { + GPCRC_InputU8(GPCRC, *ptr++); + } - return myCrc; + return GPCRC_DataReadBitReversed(GPCRC); }; void InitGpCrc(void) @@ -32,12 +42,10 @@ void InitGpCrc(void) // Declare init structs GPCRC_Init_TypeDef init = GPCRC_INIT_DEFAULT; - // Starting value in GPCRC_DATA - init.initValue = 0x04C11DB7; - // Reset GPCRC_DATA to 0xFFFF_FFFF after every read - init.autoInit = true; - // Reverse all bits of the incoming message + // reverse all bits of the incoming message init.reverseBits = true; + // all buffers are treated as byte buffers + init.enableByteMode = true; // Initialize GPCRC GPCRC_Init(GPCRC, &init); From 74a3d03a7f184b91d8c30288d86ee3189f2ff517 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 11 Dec 2022 09:03:07 +0000 Subject: [PATCH 313/572] Improve VS Code task to flash to Giant Gecko devices - Add command to "release" the CPU that has been previously halted. --- .jlink/flash_gg11.jlink | 1 + 1 file changed, 1 insertion(+) diff --git a/.jlink/flash_gg11.jlink b/.jlink/flash_gg11.jlink index cc3418b21f..af9be891a8 100644 --- a/.jlink/flash_gg11.jlink +++ b/.jlink/flash_gg11.jlink @@ -2,4 +2,5 @@ speed auto Halt LoadFile nanobooter-nanoclr.bin,0 Reset +Go Exit \ No newline at end of file From 39ecb34d9e7af13022437f9c04f5bf63ca0e1906 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 11 Dec 2022 09:14:55 +0000 Subject: [PATCH 314/572] Add linker files for SL_STK3701A (release build) --- .../nanoBooter/efm32gg11b_booter.ld | 235 +++++++++++++++++ .../SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld | 249 ++++++++++++++++++ 2 files changed, 484 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..3029b11ab9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,249 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EF000, len = 900k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld From 744196c56f3e4f2a85b30d86b7433d8830e99eba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 11 Dec 2022 09:16:12 +0000 Subject: [PATCH 315/572] Fix compiler warning about uninit vars --- .../sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp | 2 +- .../sys_io_ser_native_System_IO_Ports_SerialPort.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp b/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp index 366b2a7510..ffec8b0ce1 100644 --- a/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp +++ b/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp @@ -277,7 +277,7 @@ HRESULT Library_sys_dev_spi_native_System_Device_Spi_SpiDevice::NativeOpenDevice { NANOCLR_HEADER(); - uint32_t handle; + uint32_t handle = -1; SPI_DEVICE_CONFIGURATION spiConfig; CLR_RT_HeapBlock *config = NULL; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp index 1f8e30116f..960b79c02e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.IO.Ports/sys_io_ser_native_System_IO_Ports_SerialPort.cpp @@ -900,7 +900,7 @@ HRESULT Library_sys_io_ser_native_System_IO_Ports_SerialPort::NativeWriteString_ bool isNewAllocation = false; char *buffer = NULL; - uint32_t bufferLength; + uint32_t bufferLength = 0; int32_t length = 0; // get a pointer to the managed object instance and check that it's not NULL From b98e685343504b67b15d8a89f5c3949c95c8ebba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 11 Dec 2022 09:23:32 +0000 Subject: [PATCH 316/572] Rename struct element for clarity --- src/PAL/Include/CPU_SPI_decl.h | 2 +- .../sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/PAL/Include/CPU_SPI_decl.h b/src/PAL/Include/CPU_SPI_decl.h index 605c7cb021..57e333f3bb 100644 --- a/src/PAL/Include/CPU_SPI_decl.h +++ b/src/PAL/Include/CPU_SPI_decl.h @@ -74,7 +74,7 @@ struct SPI_DEVICE_CONFIGURATION // SPI bus Configuration (full-duplex is default) SpiBusConfiguration BusConfiguration; // True = SPI data takes the form of 16-bit words otherwise 8-bit words. - bool MD16bits; + bool DataIs16bits; // Data order for 16 bit operation DataBitOrder DataOrder16; // Rough estimate on the time it takes to send/receive one byte (in milliseconds) diff --git a/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp b/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp index ffec8b0ce1..68318579ec 100644 --- a/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp +++ b/src/System.Device.Spi/sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp @@ -289,6 +289,7 @@ HRESULT Library_sys_dev_spi_native_System_Device_Spi_SpiDevice::NativeOpenDevice config = pThis[Library_sys_dev_spi_native_System_Device_Spi_SpiDevice::FIELD___connectionSettings].Dereference(); spiConfig.BusMode = SpiBusMode_master; + spiConfig.DataIs16bits = false; // internally SPI bus ID is zero based, so better take care of that here spiConfig.Spi_Bus = config[SpiConnectionSettings::FIELD___busId].NumericByRef().s4 - 1; From 2738c4acdf70651ccfea95a12e95085d407f28d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 11 Dec 2022 09:23:51 +0000 Subject: [PATCH 317/572] Rename following last commit --- .../SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 1cc49113a8..e6c7cb8104 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -225,7 +225,7 @@ void GetSpiConfig(const SPI_DEVICE_CONFIGURATION &config, NF_SpiDriver_Init_t &i initSpiData.dummyTxValue = 0; // Sets the order of bytes transmission : MSB first or LSB first initSpiData.bitOrder = config.DataOrder16 == DataBitOrder_MSB ? spidrvBitOrderMsbFirst : spidrvBitOrderLsbFirst; - initSpiData.frameLength = config.MD16bits ? 16 : 8; + initSpiData.frameLength = config.DataIs16bits ? 16 : 8; initSpiData.isHalfDuplex = config.BusConfiguration == SpiBusConfiguration_HalfDuplex ? true : false; } From a231d000ed0ee6ef5e49915d6fe2a05ce8e6b3a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 12 Dec 2022 16:55:42 +0000 Subject: [PATCH 318/572] Fix block storage config for SL_STK3701A (release build) --- .../SL_STK3701A/common/Device_BlockStorage.c | 23 +++++++++---------- .../nanoBooter/efm32gg11b_booter.ld | 2 +- .../SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld | 4 ++-- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c index dcf2d55e8c..6cf62cf8b2 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/common/Device_BlockStorage.c @@ -9,13 +9,13 @@ // 2kB blocks const BlockRange BlockRange1[] = { - // 08000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 10}, + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - // 0800B000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 11, 158}, + // 0000C000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 158}, - // 0804F800 deployment + // 000EF000 deployment {BlockRange_BLOCKTYPE_DEPLOYMENT, 159, 509}, /////////////////////////////////////////////////////////////////////////////////////// @@ -23,24 +23,23 @@ const BlockRange BlockRange1[] = { // configuration manager files to the CMake and call ConfigurationManager_Initialize() // in nanoBooter so the configuration can be managed when in booter mode /////////////////////////////////////////////////////////////////////////////////////// - // 080FF800 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 510, 511}, + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, /////////////////////////////////////////////////////////////////////////////////////// }; const BlockRegionInfo BlockRegions[] = { { - // STM32L4 flash requires 64bits width programming - (BlockRegionAttribute_ProgramWidthIs64bits), + (0), // start address for block region - 0x08000000, + 0x00000000, // total number of blocks in this region 512, // total number of bytes per block - 0x800, + 0x1000, ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, @@ -49,7 +48,7 @@ const BlockRegionInfo BlockRegions[] = { const DeviceBlockInfo Device_BlockInfo = { - // STM32 flash memory is XIP + // GG11 flash memory is XIP (MediaAttribute_SupportsXIP), // UINT32 BytesPerSector diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld index 8941c58e5c..60294b9977 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld @@ -32,7 +32,7 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld index 3029b11ab9..d407ccbc64 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/efm32gg11b_CLR.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x000EF000, len = 900k /* space reserved for application deployment */ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 908k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x0009F000, len = 908k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 2aa0e2507c0831a1d8599e7f3482bf0be401013f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 13 Dec 2022 01:48:51 +0000 Subject: [PATCH 319/572] Add System.Runtime.Serialization - Add declaration for assembly. - Update CMake to support this new API. - Remove unsupported serialization flags. - Remove unnecessary params in BinaryFormatter deserialize/serialize functions. - Add build option to CMake template for STM32F091 to disable binary serialization. - .NET virtual target has support for binary serialization enabled as default. --- CMake/Modules/FindNF_CoreCLR.cmake | 13 +- CMake/Modules/FindNF_NativeAssemblies.cmake | 7 + .../FindSystem.Runtime.Serialization.cmake | 50 + CMakeLists.txt | 17 +- CMakeUserPresets.TEMPLATE.json | 3 +- nf.props | 2 +- .../corlib_native_System_WeakReference.cpp | 2 +- .../Core/Serialization/BinaryFormatter.cpp | 1559 +++++++++-------- .../Serialization/BinaryFormatter_stub.cpp | 140 +- src/CLR/Core/TypeSystem.cpp | 9 +- .../Include/nanoCLR_Runtime__Serialization.h | 36 +- .../System.Runtime.Serialization.vcxproj | 162 ++ ...stem.Runtime.Serialization.vcxproj.filters | 26 + .../nf_system_runtime_serialization.cpp | 27 + .../nf_system_runtime_serialization.h | 49 + ...tion_Formatters_Binary_BinaryFormatter.cpp | 61 + targets/netcore/nanoCLR.sln | 156 +- .../nanoFramework.nanoCLR.vcxproj | 9 +- .../CLR_RT_InteropAssembliesTable.cpp | 5 +- 19 files changed, 1555 insertions(+), 778 deletions(-) create mode 100644 CMake/Modules/FindSystem.Runtime.Serialization.cmake create mode 100644 src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj create mode 100644 src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj.filters create mode 100644 src/System.Runtime.Serialization/nf_system_runtime_serialization.cpp create mode 100644 src/System.Runtime.Serialization/nf_system_runtime_serialization.h create mode 100644 src/System.Runtime.Serialization/nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter.cpp diff --git a/CMake/Modules/FindNF_CoreCLR.cmake b/CMake/Modules/FindNF_CoreCLR.cmake index 86bf095e7a..6fe86a6437 100644 --- a/CMake/Modules/FindNF_CoreCLR.cmake +++ b/CMake/Modules/FindNF_CoreCLR.cmake @@ -135,7 +135,6 @@ set(NF_CoreCLR_SRCS # Core stubs RPC_stub.cpp - BinaryFormatter_stub.cpp # CLR stubs Debugger_stub.cpp @@ -181,6 +180,18 @@ if(NF_FEATURE_SUPPORT_REFLECTION) list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_RuntimeMethodInfo.cpp) list(APPEND NF_CoreCLR_SRCS corlib_native_System_RuntimeType.cpp) list(APPEND NF_CoreCLR_SRCS corlib_native_System_Type.cpp) + + # should we include binary serialization support? + if(NF_FEATURE_BINARY_SERIALIZATION) + list(APPEND NF_CoreCLR_SRCS BinaryFormatter.cpp) + else() + # binary serialization stubs because we're not supporting reflection + list(APPEND NF_CoreCLR_SRCS BinaryFormatter_stubs.cpp) + endif() + +else() + # binary serialization stubs because we're not supporting reflection + list(APPEND NF_CoreCLR_SRCS BinaryFormatter_stubs.cpp) endif() # include Collection support files depending on build option diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index 8817b3ca6d..c27cd03d35 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -27,6 +27,7 @@ option(API_System.Device.I2s "option for System.Device.I2s AP option(API_System.Device.Pwm "option for System.Device.Pwm API") option(API_System.IO.Ports "option for System.IO.Ports API") option(API_System.Device.Spi "option for System.Device.Spi API") +option(API_System.Runtime.Serialization "option for System.Runtime.Serialization API") option(API_Windows.Storage "option for Windows.Storage") option(API_nanoFramework.Graphics "option for nanoFramework.Graphics") option(API_nanoFramework.Device.Bluetooth "option for nanoFramework.Device.Bluetooth") @@ -335,6 +336,12 @@ if(API_System.Device.Spi) PerformSettingsForApiEntry("System.Device.Spi") endif() +# System.Runtime.Serialization +if(API_System.Runtime.Serialization) + ##### API name here (doted name) + PerformSettingsForApiEntry("System.Runtime.Serialization") +endif() + # System.Device.Wifi if(API_System.Device.Wifi) ##### API name here (doted name) diff --git a/CMake/Modules/FindSystem.Runtime.Serialization.cmake b/CMake/Modules/FindSystem.Runtime.Serialization.cmake new file mode 100644 index 0000000000..c9a2d1ce06 --- /dev/null +++ b/CMake/Modules/FindSystem.Runtime.Serialization.cmake @@ -0,0 +1,50 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Runtime.Serialization) + + +# set include directories +list(APPEND System.Runtime.Serialization_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND System.Runtime.Serialization_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND System.Runtime.Serialization_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND System.Runtime.Serialization_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND System.Runtime.Serialization_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND System.Runtime.Serialization_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/System.Runtime.Serialization) + +# source files +set(System.Runtime.Serialization_SRCS + + nf_system_runtime_serialization.cpp + + nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter.cpp + +) + +foreach(SRC_FILE ${System.Runtime.Serialization_SRCS}) + + set(System.Runtime.Serialization_SRC_FILE SRC_FILE-NOTFOUND) + + find_file(System.Runtime.Serialization_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/System.Runtime.Serialization + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${System.Runtime.Serialization_SRC_FILE}") + endif() + + list(APPEND System.Runtime.Serialization_SOURCES ${System.Runtime.Serialization_SRC_FILE}) + +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(System.Runtime.Serialization DEFAULT_MSG System.Runtime.Serialization_INCLUDE_DIRS System.Runtime.Serialization_SOURCES) diff --git a/CMakeLists.txt b/CMakeLists.txt index e0eae14cf4..12c411fc6e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -446,15 +446,30 @@ option(NF_NETWORKING_ENC28J60 "option to use ENC28J60 network driver") # handles inclusion of System.Reflection API ############################################# -# set default option for SNTP to ON +# set default option for Reflection API to ON option(NF_FEATURE_SUPPORT_REFLECTION "option to add support for System.Reflection API" ON) +# set default option for Serialization API to ON +option(NF_FEATURE_BINARY_SERIALIZATION "option to add support for binary serialization" ON) if(NF_FEATURE_SUPPORT_REFLECTION) set(TARGET_NANOCLR_REFLECTION TRUE CACHE INTERNAL "enable support for System.Reflection API") message(STATUS "Support for System.Reflection API enabled") + + if(NF_FEATURE_BINARY_SERIALIZATION) + set(API_System.Runtime.Serialization TRUE CACHE INTERNAL "enable support for System.Runtime.Serialization API") + message(STATUS "Support for binary serialization enabled") + else() + set(API_System.Runtime.Serialization FALSE CACHE INTERNAL "disable support for System.Runtime.Serialization API") + message(STATUS "Support for binary serialization **IS NOT** enabled") + endif() + else() set(TARGET_NANOCLR_REFLECTION FALSE CACHE INTERNAL "DISABLE support for System.Reflection API") message(STATUS "Support for System.Reflection API **IS NOT** enabled") + + # disable binary serialization if Reflection is disabled + set(API_System.Runtime.Serialization FALSE CACHE INTERNAL "disable support for System.Runtime.Serialization API") + message(STATUS "Support for binary serialization **IS NOT** enabled") endif() ################################################################# diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index e60c3822cb..b02f3b8df4 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -93,7 +93,8 @@ ], "cacheVariables": { "TARGET_BOARD": "${presetName}", - "NF_INTEROP_ASSEMBLIES": null + "NF_INTEROP_ASSEMBLIES": null, + "NF_FEATURE_BINARY_SERIALIZATION": "OFF" } }, { diff --git a/nf.props b/nf.props index 4273cea3f6..344ec3edcf 100644 --- a/nf.props +++ b/nf.props @@ -16,7 +16,7 @@ - VIRTUAL_DEVICE;SUPPORT_ANY_BASE_CONVERSION;NANOCLR_REFLECTION=TRUE;NANOCLR_SYSTEM_COLLECTIONS=TRUE; + VIRTUAL_DEVICE;NANOCLR_BINARY_SERIALIZATION;SUPPORT_ANY_BASE_CONVERSION;NANOCLR_REFLECTION=TRUE;NANOCLR_SYSTEM_COLLECTIONS=TRUE; stdcpp20 stdc17 diff --git a/src/CLR/CorLib/corlib_native_System_WeakReference.cpp b/src/CLR/CorLib/corlib_native_System_WeakReference.cpp index b0eed1ed4c..3302217807 100644 --- a/src/CLR/CorLib/corlib_native_System_WeakReference.cpp +++ b/src/CLR/CorLib/corlib_native_System_WeakReference.cpp @@ -131,7 +131,7 @@ HRESULT CLR_RT_HeapBlock_WeakReference::GetTarget(CLR_RT_HeapBlock &targetRefere CLR_RT_ProtectFromGC gcInput(input); CLR_RT_ProtectFromGC gcOutput(output); - if (FAILED(CLR_RT_BinaryFormatter::Deserialize(output, input, NULL, NULL, 0))) + if (FAILED(CLR_RT_BinaryFormatter::Deserialize(output, input, NULL, 0))) { output.SetObjectReference(NULL); } diff --git a/src/CLR/Core/Serialization/BinaryFormatter.cpp b/src/CLR/Core/Serialization/BinaryFormatter.cpp index e6739610e9..b5025897e3 100644 --- a/src/CLR/Core/Serialization/BinaryFormatter.cpp +++ b/src/CLR/Core/Serialization/BinaryFormatter.cpp @@ -8,31 +8,35 @@ //////////////////////////////////////////////////////////////////////////////////////////////////// -//this method simply informs if Serialization is enabled -//the stub version of this method returns False +// this method simply informs if Serialization is enabled +// the stub version of this method returns False bool CLR_RT_BinaryFormatter::SerializationEnabled() { NATIVE_PROFILE_CLR_SERIALIZATION(); return true; } -CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixDereference( CLR_RT_HeapBlock* v ) +CLR_RT_HeapBlock *CLR_RT_BinaryFormatter::TypeHandler::FixDereference(CLR_RT_HeapBlock *v) { NATIVE_PROFILE_CLR_SERIALIZATION(); return (v && v->DataType() == DATATYPE_OBJECT) ? v->Dereference() : v; } -CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixNull( CLR_RT_HeapBlock* v ) +CLR_RT_HeapBlock *CLR_RT_BinaryFormatter::TypeHandler::FixNull(CLR_RT_HeapBlock *v) { NATIVE_PROFILE_CLR_SERIALIZATION(); - if(v && v->DataType() == DATATYPE_OBJECT && v->Dereference() == NULL) return NULL; + if (v && v->DataType() == DATATYPE_OBJECT && v->Dereference() == NULL) + return NULL; return v; } //--// -HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CLR_RT_BinaryFormatter* bf, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* expected ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( + CLR_RT_BinaryFormatter *bf, + SerializationHintsAttribute *hints, + CLR_RT_TypeDescriptor *expected) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); @@ -41,12 +45,12 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CLR_RT_Bina m_bf = bf; - if(hints) + if (hints) { m_hints = *hints; } - if(expected) + if (expected) { m_typeExpected = &m_typeExpected_tmp; @@ -56,57 +60,59 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CLR_RT_Bina NANOCLR_NOCLEANUP_NOLABEL(); } -HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue( CLR_RT_HeapBlock* v ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue(CLR_RT_HeapBlock *v) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); m_value = NULL; - m_type = NULL; + m_type = NULL; - v = TypeHandler::FixNull( v ); - if(v) + v = TypeHandler::FixNull(v); + if (v) { m_value = &m_value_tmp; - m_type = &m_type_tmp; + m_type = &m_type_tmp; - m_value->Assign( *v ); + m_value->Assign(*v); - NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject( *v )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject(*v)); #if defined(NANOCLR_APPDOMAINS) - if(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) + if (m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) { - //MarshalByRefObjects are special for the AppDomain marshaler, and need to get marshaled regardless of whether or not they - //are serializable + // MarshalByRefObjects are special for the AppDomain marshaler, and need to get marshaled regardless of + // whether or not they are serializable - if((m_type->m_handlerCls.CrossReference().m_flags & CLR_RT_TypeDef_CrossReference::TD_CR_IsMarshalByRefObject) || - m_value->IsTransparentProxy()) - { + if ((m_type->m_handlerCls.CrossReference().m_flags & + CLR_RT_TypeDef_CrossReference::TD_CR_IsMarshalByRefObject) || + m_value->IsTransparentProxy()) + { m_fIsMarshalByRefObject = true; - } + } } - + #endif - if((m_type->m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Serializable) == 0) + if ((m_type->m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Serializable) == 0) { #if defined(NANOCLR_APPDOMAINS) - - if(m_fIsMarshalByRefObject) NANOCLR_SET_AND_LEAVE(S_OK); - //For marshaling, we want to throw an exception if we can't correctly marshal an object across AD boundaries - //In fact, this should probably be turned on for all serialization, but I don't know what other implications that - //would have + if (m_fIsMarshalByRefObject) + NANOCLR_SET_AND_LEAVE(S_OK); + + // For marshaling, we want to throw an exception if we can't correctly marshal an object across AD + // boundaries In fact, this should probably be turned on for all serialization, but I don't know what other + // implications that would have - if(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) + if (m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) { NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); } #endif m_value = NULL; - m_type = NULL; - } + m_type = NULL; + } } NANOCLR_NOCLEANUP(); @@ -117,59 +123,59 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue( CLR_RT_HeapBlock* v ) int CLR_RT_BinaryFormatter::TypeHandler::SignatureRequirements() { NATIVE_PROFILE_CLR_SERIALIZATION(); - int res = c_Signature_Header | c_Signature_Type | c_Signature_Length; - CLR_RT_TypeDescriptor* td; - CLR_RT_TypeDescriptor sub; + int res = c_Signature_Header | c_Signature_Type | c_Signature_Length; + CLR_RT_TypeDescriptor *td; + CLR_RT_TypeDescriptor sub; - if(m_hints.m_arraySize != 0) + if (m_hints._arraySize != 0) { res &= ~c_Signature_Length; } m_typeForced = NULL; - if(m_typeExpected != NULL) + if (m_typeExpected != NULL) { - switch(m_typeExpected->m_flags) + switch (m_typeExpected->m_flags) { - case CLR_RT_DataTypeLookup::c_Primitive: - case CLR_RT_DataTypeLookup::c_Enum : - case CLR_RT_DataTypeLookup::c_ValueType: - res = 0; - break; - - default: - if(m_hints.m_flags & SF_FixedType) - { - res &= ~c_Signature_Type; + case CLR_RT_DataTypeLookup::c_Primitive: + case CLR_RT_DataTypeLookup::c_Enum: + case CLR_RT_DataTypeLookup::c_ValueType: + res = 0; break; - } - if(m_typeExpected->m_flags & CLR_RT_DataTypeLookup::c_Array) - { - sub.InitializeFromType( m_typeExpected->m_reflex.m_data.m_type ); + default: + if (m_hints._options & SF_FixedType) + { + res &= ~c_Signature_Type; + break; + } - td = ⊂ - } - else - { - td = m_typeExpected; - } + if (m_typeExpected->m_flags & CLR_RT_DataTypeLookup::c_Array) + { + sub.InitializeFromType(m_typeExpected->m_reflex.m_data.m_type); - if(td->m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Sealed) - { - res &= ~c_Signature_Type; - break; - } + td = ⊂ + } + else + { + td = m_typeExpected; + } + + if (td->m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Sealed) + { + res &= ~c_Signature_Type; + break; + } } } - if((res & c_Signature_Type) == 0) + if ((res & c_Signature_Type) == 0) { - m_typeForced = &m_typeForced_tmp; + m_typeForced = &m_typeForced_tmp; *m_typeForced = *m_typeExpected; - if(m_hints.m_flags & SF_PointerNeverNull) + if (m_hints._options & SF_PointerNeverNull) { res &= ~c_Signature_Header; } @@ -178,56 +184,57 @@ int CLR_RT_BinaryFormatter::TypeHandler::SignatureRequirements() return res; } -bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes( CLR_RT_TypeDescriptor* left, CLR_RT_TypeDescriptor* right ) +bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes(CLR_RT_TypeDescriptor *left, CLR_RT_TypeDescriptor *right) { NATIVE_PROFILE_CLR_SERIALIZATION(); - if(!left && !right) return true; - if(!left || !right) return false; + if (!left && !right) + return true; + if (!left || !right) + return false; - return memcmp( left, right, sizeof(*left) ) == 0; + return memcmp(left, right, sizeof(*left)) == 0; } -CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType( CLR_RT_TypeDescriptor* type ) +CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType(CLR_RT_TypeDescriptor *type) { NATIVE_PROFILE_CLR_SERIALIZATION(); return (CLR_DataType)type->m_handlerCls.m_target->dataType; } -CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType( CLR_RT_TypeDescriptor* type ) +CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType(CLR_RT_TypeDescriptor *type) { NATIVE_PROFILE_CLR_SERIALIZATION(); - return c_CLR_RT_DataTypeLookup[ type->GetDataType() ].m_sizeInBits; + return c_CLR_RT_DataTypeLookup[type->GetDataType()].m_sizeInBits; } -bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType( CLR_RT_TypeDescriptor* type ) +bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType(CLR_RT_TypeDescriptor *type) { NATIVE_PROFILE_CLR_SERIALIZATION(); - return (c_CLR_RT_DataTypeLookup[ type->GetDataType() ].m_flags & CLR_RT_DataTypeLookup::c_Signed) != 0; + return (c_CLR_RT_DataTypeLookup[type->GetDataType()].m_flags & CLR_RT_DataTypeLookup::c_Signed) != 0; } //--// -HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature( int& res ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature(int &res) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); CLR_UINT32 idx; - int mask = SignatureRequirements(); + int mask = SignatureRequirements(); - if((mask & c_Signature_Type) == 0) + if ((mask & c_Signature_Type) == 0) { - if(m_type && CompareTypes( m_type, m_typeForced ) == false) + if (m_type && CompareTypes(m_type, m_typeForced) == false) { - while(true) + while (true) { - if(m_typeForced->m_flags == CLR_RT_DataTypeLookup::c_Enum) + if (m_typeForced->m_flags == CLR_RT_DataTypeLookup::c_Enum) { break; } - if(m_typeForced->m_handlerCls.IsATypeHandler() && - m_type ->m_handlerCls.IsATypeHandler() ) + if (m_typeForced->m_handlerCls.IsATypeHandler() && m_type->m_handlerCls.IsATypeHandler()) { break; } @@ -237,242 +244,249 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature( int& res ) } } - if(m_value == NULL) + if (m_value == NULL) { - if(mask == 0) + if (mask == 0) { // // Special case for null strings (strings don't emit an hash): send a string of length -1. // - if(m_typeExpected->GetDataType() == DATATYPE_STRING) + if (m_typeExpected->GetDataType() == DATATYPE_STRING) { - NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned( 0xFFFFFFFF )); + NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned(0xFFFFFFFF)); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Null, TE_L1)); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Null, TE_L1 )); - - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } //--// #if defined(NANOCLR_APPDOMAINS) - if(m_fIsMarshalByRefObject) + if (m_fIsMarshalByRefObject) { - CLR_RT_HeapBlock* valPtr = m_value->Dereference(); + CLR_RT_HeapBlock *valPtr = m_value->Dereference(); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other, TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Other, TE_L2 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L3_MBRO , TE_L3 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Other, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L2_Other, TE_L2)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L3_MBRO, TE_L3)); - { + { /* The bit stream contains pointers to the MBRO and its AppDomain. Only the header is used, and no duplicate detection is necessary -- all proxies pointing at the same object are equal. which will get marshaled into either a proxy or MBRO, depending on the destination AppDomain. - Live pointers are stored, but this is ok since it is for marshaling only. The objects cannot - can collected during a GC due to the live object that is being marshaled. + Live pointers are stored, but this is ok since it is for marshaling only. The objects cannot + can collected during a GC due to the live object that is being marshaled. */ _ASSERTE(CLR_EE_DBG_IS(NoCompaction)); - CLR_RT_HeapBlock* ptr; - CLR_RT_AppDomain* appDomain; + CLR_RT_HeapBlock *ptr; + CLR_RT_AppDomain *appDomain; - if(valPtr->DataType() == DATATYPE_TRANSPARENT_PROXY) + if (valPtr->DataType() == DATATYPE_TRANSPARENT_PROXY) { - ptr = valPtr->TransparentProxyDereference(); - appDomain = valPtr->TransparentProxyAppDomain (); + ptr = valPtr->TransparentProxyDereference(); + appDomain = valPtr->TransparentProxyAppDomain(); } else { - ptr = valPtr; + ptr = valPtr; appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); } - - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)ptr, 32)); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)appDomain, 32)); + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits((CLR_UINT32)(size_t)ptr, 32)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits((CLR_UINT32)(size_t)appDomain, 32)); } - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } #endif - idx = m_bf->SearchDuplicate( m_value ); - if(idx != (CLR_UINT32)-1) + idx = m_bf->SearchDuplicate(m_value); + if (idx != (CLR_UINT32)-1) { // // No duplicates allowed for fixed-type objects. // - if((mask & c_Signature_Header) == 0) + if ((mask & c_Signature_Header) == 0) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } - NANOCLR_CHECK_HRESULT(m_bf->WriteBits ( TE_L1_Duplicate, TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned( idx )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Duplicate, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned(idx)); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } //--// - NANOCLR_CHECK_HRESULT(EmitSignature_Inner( mask, m_type, m_value )); - - res = c_Action_ObjectData; NANOCLR_SET_AND_LEAVE(S_OK); + NANOCLR_CHECK_HRESULT(EmitSignature_Inner(mask, m_type, m_value)); + res = c_Action_ObjectData; + NANOCLR_SET_AND_LEAVE(S_OK); NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( int mask, CLR_RT_TypeDescriptor* type, CLR_RT_HeapBlock* value ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( + int mask, + CLR_RT_TypeDescriptor *type, + CLR_RT_HeapBlock *value) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); // Unbox reflection types - if(value && value->DataType() == DATATYPE_OBJECT) + if (value && value->DataType() == DATATYPE_OBJECT) { - CLR_RT_HeapBlock* pObj = value->Dereference(); - - if(pObj && pObj->DataType() == DATATYPE_REFLECTION) + CLR_RT_HeapBlock *pObj = value->Dereference(); + + if (pObj && pObj->DataType() == DATATYPE_REFLECTION) { value = pObj; } } - if(value && value->DataType() == DATATYPE_REFLECTION) + if (value && value->DataType() == DATATYPE_REFLECTION) { - switch(value->ReflectionDataConst().m_kind) + switch (value->ReflectionDataConst().m_kind) { - case REFLECTION_TYPE: - case REFLECTION_TYPE_DELAYED: - if((mask & c_Signature_Header) != 0) - { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other, TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Other, TE_L2 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L3_Type , TE_L3 )); - } - break; + case REFLECTION_TYPE: + case REFLECTION_TYPE_DELAYED: + if ((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Other, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L2_Other, TE_L2)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L3_Type, TE_L3)); + } + break; #if defined(NANOCLR_APPDOMAINS) - case REFLECTION_ASSEMBLY: - case REFLECTION_CONSTRUCTOR: - case REFLECTION_METHOD: - case REFLECTION_FIELD: - if((m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) == 0) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + case REFLECTION_ASSEMBLY: + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + case REFLECTION_FIELD: + if ((m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) == 0) + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); - if((mask & c_Signature_Header) != 0) - { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other , TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Other , TE_L2 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L3_Reflection, TE_L3 )); - } - break; + if ((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Other, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L2_Other, TE_L2)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L3_Reflection, TE_L3)); + } + break; #endif - default: - NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); - } + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } } - else if(value && (type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList))) + else if (value && (type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList))) { - CLR_RT_HeapBlock_Array* array; - int sizeReal = -1; + CLR_RT_HeapBlock_Array *array; + int sizeReal = -1; - if(type->m_flags & CLR_RT_DataTypeLookup::c_Array) + if (type->m_flags & CLR_RT_DataTypeLookup::c_Array) { - if((mask & c_Signature_Header) != 0) + if ((mask & c_Signature_Header) != 0) { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other, TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Array, TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Other, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L2_Array, TE_L2)); } - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)type->m_reflex.m_levels, TE_ArrayDepth )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits((CLR_UINT32)type->m_reflex.m_levels, TE_ArrayDepth)); - CLR_RT_TypeDescriptor typeSub; typeSub.InitializeFromType( type->m_reflex.m_data.m_type ); + CLR_RT_TypeDescriptor typeSub; + typeSub.InitializeFromType(type->m_reflex.m_data.m_type); - NANOCLR_CHECK_HRESULT(EmitSignature_Inner( c_Signature_Header | c_Signature_Type, &typeSub, NULL )); + NANOCLR_CHECK_HRESULT(EmitSignature_Inner(c_Signature_Header | c_Signature_Type, &typeSub, NULL)); } - sizeReal = value->DereferenceArray()->m_numOfElements; } else { int capacity; - if((mask & c_Signature_Header) != 0) + if ((mask & c_Signature_Header) != 0) { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other , TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_ArrayList, TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Other, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L2_ArrayList, TE_L2)); } - NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( *value, array, sizeReal, capacity )); + NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList(*value, array, sizeReal, capacity)); } - if((mask & c_Signature_Length) != 0) + if ((mask & c_Signature_Length) != 0) { - int bitsMax = m_hints.m_bitPacked; + int bitsMax = m_hints._bitPacked; - if(bitsMax != 0) + if (bitsMax != 0) { - if(sizeReal >= (1 << bitsMax)) + if (sizeReal >= (1 << bitsMax)) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } - NANOCLR_SET_AND_LEAVE(m_bf->WriteBits( (CLR_UINT32)sizeReal, bitsMax )); + NANOCLR_SET_AND_LEAVE(m_bf->WriteBits((CLR_UINT32)sizeReal, bitsMax)); } else { - NANOCLR_SET_AND_LEAVE(m_bf->WriteCompressedUnsigned( (CLR_UINT32)sizeReal )); + NANOCLR_SET_AND_LEAVE(m_bf->WriteCompressedUnsigned((CLR_UINT32)sizeReal)); } } else { - int sizeExpected = m_hints.m_arraySize; + int sizeExpected = m_hints._arraySize; - if(sizeExpected > 0 && sizeExpected != sizeReal) + if (sizeExpected > 0 && sizeExpected != sizeReal) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } } } - else if(type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || - type->m_flags == CLR_RT_DataTypeLookup::c_Enum ) + else if (type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || type->m_flags == CLR_RT_DataTypeLookup::c_Enum) { - if((mask & c_Signature_Header) != 0) + if ((mask & c_Signature_Header) != 0) { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other , TE_L1 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Primitive, TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Other, TE_L1)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L2_Primitive, TE_L2)); } - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { - NANOCLR_SET_AND_LEAVE(m_bf->WriteBits( CLR_RT_TypeSystem::MapDataTypeToElementType( type->GetDataType() ), TE_ElementType )); + NANOCLR_SET_AND_LEAVE( + m_bf->WriteBits(CLR_RT_TypeSystem::MapDataTypeToElementType(type->GetDataType()), TE_ElementType)); } } else { - if((mask & c_Signature_Header) != 0) + if ((mask & c_Signature_Header) != 0) { - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Reference, TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(TE_L1_Reference, TE_L1)); } - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { - NANOCLR_SET_AND_LEAVE(m_bf->WriteType( type->m_handlerCls.CrossReference().m_hash )); + NANOCLR_SET_AND_LEAVE(m_bf->WriteType(type->m_handlerCls.CrossReference().m_hash)); } } @@ -481,7 +495,7 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( int mask, CLR_ //--// -HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature(int &res) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); @@ -489,114 +503,117 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) int mask = SignatureRequirements(); m_value = NULL; - m_type = NULL; + m_type = NULL; - if(m_typeForced) + if (m_typeForced) { m_type = &m_type_tmp; *m_type = *m_typeForced; } - if((mask & c_Signature_Header) != 0) + if ((mask & c_Signature_Header) != 0) { CLR_UINT32 levelOne; CLR_UINT32 levelTwo; CLR_UINT32 levelThree; + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(levelOne, TE_L1)); - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelOne, TE_L1 )); - - if(levelOne == TE_L1_Null) + if (levelOne == TE_L1_Null) { - if(m_hints.m_flags & SF_PointerNeverNull) + if (m_hints._options & SF_PointerNeverNull) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } - if(levelOne == TE_L1_Duplicate) + if (levelOne == TE_L1_Duplicate) { - CLR_RT_HeapBlock* dup; - CLR_UINT32 idx; + CLR_RT_HeapBlock *dup; + CLR_UINT32 idx; - NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned( idx )); + NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned(idx)); - dup = m_bf->GetDuplicate( idx ); - if(dup == NULL) + dup = m_bf->GetDuplicate(idx); + if (dup == NULL) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } m_value = &m_value_tmp; - m_value->SetObjectReference( dup ); + m_value->SetObjectReference(dup); m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject( *m_value )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject(*m_value)); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } - if(levelOne == TE_L1_Reference) + if (levelOne == TE_L1_Reference) { - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { CLR_RT_ReflectionDef_Index idx; - NANOCLR_CHECK_HRESULT(m_bf->ReadType( idx )); + NANOCLR_CHECK_HRESULT(m_bf->ReadType(idx)); m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromReflection( idx )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromReflection(idx)); } } else { - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelTwo, TE_L2 )); - if(levelTwo == TE_L2_Primitive) + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(levelTwo, TE_L2)); + if (levelTwo == TE_L2_Primitive) { - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { CLR_UINT32 et; - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( et, TE_ElementType )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(et, TE_ElementType)); m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromDataType( CLR_RT_TypeSystem::MapElementTypeToDataType( et ) )); + NANOCLR_CHECK_HRESULT( + m_type->InitializeFromDataType(CLR_RT_TypeSystem::MapElementTypeToDataType(et))); } } - else if(levelTwo == TE_L2_Array) + else if (levelTwo == TE_L2_Array) { - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { CLR_UINT32 depth; - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( depth, TE_ArrayDepth )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(depth, TE_ArrayDepth)); - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelOne, TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(levelOne, TE_L1)); - if(levelOne == TE_L1_Reference) + if (levelOne == TE_L1_Reference) { CLR_RT_ReflectionDef_Index idx; - NANOCLR_CHECK_HRESULT(m_bf->ReadType( idx )); + NANOCLR_CHECK_HRESULT(m_bf->ReadType(idx)); m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromReflection( idx )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromReflection(idx)); } - else if(levelOne == TE_L1_Other) + else if (levelOne == TE_L1_Other) { - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelTwo, TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(levelTwo, TE_L2)); - if(levelTwo == TE_L2_Primitive) + if (levelTwo == TE_L2_Primitive) { CLR_UINT32 et; - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( et, TE_ElementType )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(et, TE_ElementType)); m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromDataType( CLR_RT_TypeSystem::MapElementTypeToDataType( et ) )); + NANOCLR_CHECK_HRESULT( + m_type->InitializeFromDataType(CLR_RT_TypeSystem::MapElementTypeToDataType(et))); } else { @@ -612,74 +629,78 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) m_type->ConvertToArray(); } } - else if(levelTwo == TE_L2_ArrayList) + else if (levelTwo == TE_L2_ArrayList) { - if((mask & c_Signature_Type) != 0) + if ((mask & c_Signature_Type) != 0) { m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromType( g_CLR_RT_WellKnownTypes.m_ArrayList )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromType(g_CLR_RT_WellKnownTypes.m_ArrayList)); } } - else if(levelTwo == TE_L2_Other) + else if (levelTwo == TE_L2_Other) { - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelThree, TE_L3 )); - if(levelThree == TE_L3_Type) + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(levelThree, TE_L3)); + if (levelThree == TE_L3_Type) { m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromType( g_CLR_RT_WellKnownTypes.m_Type )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromType(g_CLR_RT_WellKnownTypes.m_Type)); } #if defined(NANOCLR_APPDOMAINS) else if (levelThree == TE_L3_Reflection) { CLR_RT_ReflectionDef_Index value; - CLR_UINT64 data; + CLR_UINT64 data; _ASSERTE(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal); - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( data, 64 )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(data, 64)); + + value.SetRawData(data); - value.SetRawData( data ); - m_value = &m_value_tmp; - NANOCLR_CHECK_HRESULT(m_value->SetReflection( value )); + NANOCLR_CHECK_HRESULT(m_value->SetReflection(value)); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } else if (levelThree == TE_L3_MBRO) { CLR_UINT32 uintPtr; CLR_UINT32 uintAppDomain; - CLR_RT_HeapBlock* ptr; - CLR_RT_AppDomain* appDomain; - - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( uintPtr , 32 )); - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( uintAppDomain, 32 )); + CLR_RT_HeapBlock *ptr; + CLR_RT_AppDomain *appDomain; + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(uintPtr, 32)); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(uintAppDomain, 32)); - _ASSERTE(CLR_EE_DBG_IS( NoCompaction )); + _ASSERTE(CLR_EE_DBG_IS(NoCompaction)); + + ptr = (CLR_RT_HeapBlock *)(size_t)uintPtr; + appDomain = (CLR_RT_AppDomain *)(size_t)uintAppDomain; - ptr = (CLR_RT_HeapBlock*)(size_t)uintPtr; - appDomain = (CLR_RT_AppDomain*)(size_t)uintAppDomain; - m_type = &m_type_tmp; - NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject( *ptr )); + NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject(*ptr)); m_value = &m_value_tmp; - if(appDomain != g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()) + if (appDomain != g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()) { - //The MarshalByRefObject lives in a separate AppDomain. - //We need to allocate a TRANSPARENT_PROXY object on the stack - - CLR_RT_HeapBlock* proxy = g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForObjects( DATATYPE_TRANSPARENT_PROXY, 0, 1 ); CHECK_ALLOCATION(proxy); + // The MarshalByRefObject lives in a separate AppDomain. + // We need to allocate a TRANSPARENT_PROXY object on the stack + + CLR_RT_HeapBlock *proxy = + g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForObjects(DATATYPE_TRANSPARENT_PROXY, 0, 1); + CHECK_ALLOCATION(proxy); + + proxy->SetTransparentProxyReference(appDomain, ptr); - proxy->SetTransparentProxyReference( appDomain, ptr ); - ptr = proxy; } - //Set the value reference to either the MBRO, or the proxy - m_value->SetObjectReference( ptr ); + // Set the value reference to either the MBRO, or the proxy + m_value->SetObjectReference(ptr); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } #endif else @@ -690,28 +711,28 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) } } - if(m_type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) + if (m_type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) { CLR_UINT32 len; - if(mask & c_Signature_Length) + if (mask & c_Signature_Length) { - int bitsMax = m_hints.m_bitPacked; + int bitsMax = m_hints._bitPacked; - if(bitsMax != 0) + if (bitsMax != 0) { - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( len, bitsMax )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(len, bitsMax)); } else { - NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned( len )); + NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned(len)); } } else { CLR_RT_TypeDescriptor sub; - if(m_type->m_reflex.m_levels != 1) + if (m_type->m_reflex.m_levels != 1) { // // Only simple arrays can have variable size. @@ -719,175 +740,190 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } - sub.InitializeFromType( m_type->m_reflex.m_data.m_type ); + sub.InitializeFromType(m_type->m_reflex.m_data.m_type); - len = m_hints.m_arraySize; + len = m_hints._arraySize; - if(len == (CLR_UINT32)-1) + if (len == (CLR_UINT32)-1) { len = m_bf->BitsAvailable(); - switch(TypeHandler::GetSizeOfType( &sub )) + switch (TypeHandler::GetSizeOfType(&sub)) { - case 1: break; - case 8: len /= 8; break; - case 16: len /= 16; break; - case 32: len /= 32; break; - case 64: len /= 64; break; - default: - NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + case 1: + break; + case 8: + len /= 8; + break; + case 16: + len /= 16; + break; + case 32: + len /= 32; + break; + case 64: + len /= 64; + break; + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } } } - if(m_type->m_flags & CLR_RT_DataTypeLookup::c_ArrayList) + if (m_type->m_flags & CLR_RT_DataTypeLookup::c_ArrayList) { - CLR_RT_HeapBlock_Array* array; + CLR_RT_HeapBlock_Array *array; m_value = &m_value_tmp; - NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewArrayList( *m_value, len, array )); + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewArrayList(*m_value, len, array)); } else { m_value = &m_value_tmp; - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( *m_value, len, m_type->m_reflex )); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(*m_value, len, m_type->m_reflex)); } } else { m_value = &m_value_tmp; - if(m_type->m_handlerCls.IsATypeHandler()) + if (m_type->m_handlerCls.IsATypeHandler()) { CLR_RT_ReflectionDef_Index idx; - NANOCLR_CHECK_HRESULT(m_bf->ReadType( idx )); + NANOCLR_CHECK_HRESULT(m_bf->ReadType(idx)); - NANOCLR_CHECK_HRESULT(m_value->SetReflection( idx )); + NANOCLR_CHECK_HRESULT(m_value->SetReflection(idx)); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } - NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObject( *m_value, m_type->m_handlerCls )); + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObject(*m_value, m_type->m_handlerCls)); } - res = c_Action_ObjectData; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_ObjectData; + NANOCLR_SET_AND_LEAVE(S_OK); NANOCLR_NOCLEANUP(); } //--// -HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue(int &res) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_HeapBlock* value = m_value->FixBoxingReference(); - CLR_UINT64 val; - CLR_UINT32 bits; - bool fSigned; + CLR_RT_HeapBlock *value = m_value->FixBoxingReference(); + CLR_UINT64 val; + CLR_UINT32 bits; + bool fSigned; // unbox reflection types - if(value->DataType() == DATATYPE_OBJECT) + if (value->DataType() == DATATYPE_OBJECT) { - CLR_RT_HeapBlock* obj = value->Dereference(); - - if(obj && obj->DataType() == DATATYPE_REFLECTION) + CLR_RT_HeapBlock *obj = value->Dereference(); + + if (obj && obj->DataType() == DATATYPE_REFLECTION) { value = obj; } } - if(value->DataType() == DATATYPE_REFLECTION) + if (value->DataType() == DATATYPE_REFLECTION) { - switch(value->ReflectionDataConst().m_kind) + switch (value->ReflectionDataConst().m_kind) { - case REFLECTION_TYPE: - case REFLECTION_TYPE_DELAYED: - NANOCLR_CHECK_HRESULT(m_bf->WriteType( value->ReflectionDataConst() )); - break; + case REFLECTION_TYPE: + case REFLECTION_TYPE_DELAYED: + NANOCLR_CHECK_HRESULT(m_bf->WriteType(value->ReflectionDataConst())); + break; #if defined(NANOCLR_APPDOMAINS) - case REFLECTION_ASSEMBLY: - case REFLECTION_CONSTRUCTOR: - case REFLECTION_METHOD: - case REFLECTION_FIELD: - { + case REFLECTION_ASSEMBLY: + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + case REFLECTION_FIELD: + { CLR_UINT64 data; _ASSERTE(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal); data = value->ReflectionDataConst().GetRawData(); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( data, 64 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(data, 64)); } - break; -#endif + break; +#endif } - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } - if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) + if (m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) { - CLR_INT64* pVal = Library_corlib_native_System_DateTime::GetValuePtr( *value ); FAULT_ON_NULL(pVal); + CLR_INT64 *pVal = Library_corlib_native_System_DateTime::GetValuePtr(*value); + FAULT_ON_NULL(pVal); - val = *(CLR_UINT64*)pVal; - bits = 64; + val = *(CLR_UINT64 *)pVal; + bits = 64; fSigned = false; } - else if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) + else if (m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) { - CLR_INT64* pVal = Library_corlib_native_System_TimeSpan::GetValuePtr( *value ); FAULT_ON_NULL(pVal); + CLR_INT64 *pVal = Library_corlib_native_System_TimeSpan::GetValuePtr(*value); + FAULT_ON_NULL(pVal); - val = *(CLR_UINT64*)pVal; - bits = 64; + val = *(CLR_UINT64 *)pVal; + bits = 64; fSigned = true; } - else if(m_type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || - m_type->m_flags == CLR_RT_DataTypeLookup::c_Enum ) + else if (m_type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || m_type->m_flags == CLR_RT_DataTypeLookup::c_Enum) { - bits = TypeHandler::GetSizeOfType( m_type ); - if(bits == CLR_RT_DataTypeLookup::c_VariableSize) + bits = TypeHandler::GetSizeOfType(m_type); + if (bits == CLR_RT_DataTypeLookup::c_VariableSize) { - const char* szText = value->RecoverString(); - CLR_UINT32 len = szText ? (CLR_UINT32)hal_strlen_s( szText ) : 0xFFFFFFFF; + const char *szText = value->RecoverString(); + CLR_UINT32 len = szText ? (CLR_UINT32)hal_strlen_s(szText) : 0xFFFFFFFF; - NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned( len )); + NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned(len)); - if(len != (CLR_UINT32)-1) + if (len != (CLR_UINT32)-1) { - NANOCLR_CHECK_HRESULT(m_bf->WriteArray( (CLR_UINT8*)szText, len )); + NANOCLR_CHECK_HRESULT(m_bf->WriteArray((CLR_UINT8 *)szText, len)); } - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } - else if(bits == CLR_RT_DataTypeLookup::c_NA) + else if (bits == CLR_RT_DataTypeLookup::c_NA) { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } - CLR_RT_HeapBlock* v = FixDereference( value ); FAULT_ON_NULL(v); + CLR_RT_HeapBlock *v = FixDereference(value); + FAULT_ON_NULL(v); val = v->NumericByRefConst().u8; - fSigned = TypeHandler::GetSignOfType( m_type ); + fSigned = TypeHandler::GetSignOfType(m_type); } #if defined(NANOCLR_APPDOMAINS) - else if(m_fIsMarshalByRefObject) + else if (m_fIsMarshalByRefObject) { - CLR_RT_HeapBlock* valPtr = value->Dereference(); - CLR_RT_AppDomain* appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); - - if(valPtr->DataType() == DATATYPE_TRANSPARENT_PROXY) + CLR_RT_HeapBlock *valPtr = value->Dereference(); + CLR_RT_AppDomain *appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); + + if (valPtr->DataType() == DATATYPE_TRANSPARENT_PROXY) { appDomain = valPtr->TransparentProxyAppDomain(); - valPtr = valPtr->TransparentProxyDereference(); + valPtr = valPtr->TransparentProxyDereference(); } - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)valPtr , 32 )); - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)appDomain, 32 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits((CLR_UINT32)(size_t)valPtr, 32)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits((CLR_UINT32)(size_t)appDomain, 32)); NANOCLR_SET_AND_LEAVE(S_OK); } @@ -895,36 +931,40 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) else { - NANOCLR_SET_AND_LEAVE(TrackObject( res )); + NANOCLR_SET_AND_LEAVE(TrackObject(res)); } { CLR_UINT32 shift = 64 - bits; - if(shift) + if (shift) { val <<= shift; - if(fSigned) val = (CLR_UINT64)((CLR_INT64 )val >> shift); - else val = (CLR_UINT64)((CLR_UINT64)val >> shift); + if (fSigned) + val = (CLR_UINT64)((CLR_INT64)val >> shift); + else + val = (CLR_UINT64)((CLR_UINT64)val >> shift); } } - if(m_hints.m_bitPacked) bits = m_hints.m_bitPacked; + if (m_hints._bitPacked) + bits = m_hints._bitPacked; - val -= m_hints.m_rangeBias; + val -= m_hints._rangeBias; - if(fSigned) + if (fSigned) { CLR_INT64 valS = (CLR_INT64)val; - if(m_hints.m_scale != 0) valS /= (CLR_INT64)m_hints.m_scale; + if (m_hints._scale != 0) + valS /= (CLR_INT64)m_hints._scale; - if(bits != 64) + if (bits != 64) { - CLR_INT64 maxVal = (LONGLONGCONSTANT(1) << (bits-1)) - 1; + CLR_INT64 maxVal = (LONGLONGCONSTANT(1) << (bits - 1)) - 1; - if(valS < (-maxVal-1) || valS > maxVal) + if (valS < (-maxVal - 1) || valS > maxVal) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } @@ -936,13 +976,14 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) { CLR_UINT64 valU = (CLR_UINT64)val; - if(m_hints.m_scale != 0) valU /= (CLR_UINT64)m_hints.m_scale; + if (m_hints._scale != 0) + valU /= (CLR_UINT64)m_hints._scale; - if(bits != 64) + if (bits != 64) { CLR_UINT64 maxVal = (ULONGLONGCONSTANT(1) << bits) - 1; - if(valU > maxVal) + if (valU > maxVal) { NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); } @@ -951,118 +992,126 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) val = (CLR_UINT64)valU; } - NANOCLR_CHECK_HRESULT(m_bf->WriteBits( val, bits )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits(val, bits)); - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue( int& res ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue(int &res) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_UINT64* dst; - CLR_UINT64 val; - CLR_UINT32 bits; - bool fSigned; + CLR_UINT64 *dst; + CLR_UINT64 val; + CLR_UINT32 bits; + bool fSigned; - if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) + if (m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) { - CLR_INT64* pVal = Library_corlib_native_System_DateTime::GetValuePtr( *m_value ); FAULT_ON_NULL(pVal); + CLR_INT64 *pVal = Library_corlib_native_System_DateTime::GetValuePtr(*m_value); + FAULT_ON_NULL(pVal); - dst = (CLR_UINT64*)pVal; - bits = 64; + dst = (CLR_UINT64 *)pVal; + bits = 64; fSigned = false; } - else if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) + else if (m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) { - CLR_INT64* pVal = Library_corlib_native_System_TimeSpan::GetValuePtr( *m_value ); FAULT_ON_NULL(pVal); + CLR_INT64 *pVal = Library_corlib_native_System_TimeSpan::GetValuePtr(*m_value); + FAULT_ON_NULL(pVal); - dst = (CLR_UINT64*)pVal; - bits = 64; + dst = (CLR_UINT64 *)pVal; + bits = 64; fSigned = true; } - else if(m_type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || - m_type->m_flags == CLR_RT_DataTypeLookup::c_Enum ) + else if (m_type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || m_type->m_flags == CLR_RT_DataTypeLookup::c_Enum) { - bits = TypeHandler::GetSizeOfType( m_type ); + bits = TypeHandler::GetSizeOfType(m_type); - if(bits == CLR_RT_DataTypeLookup::c_VariableSize) + if (bits == CLR_RT_DataTypeLookup::c_VariableSize) { CLR_UINT32 len; - NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned( len )); + NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned(len)); - if(len == 0xFFFFFFFF) + if (len == 0xFFFFFFFF) { - m_value->SetObjectReference( NULL ); + m_value->SetObjectReference(NULL); } else { - CLR_RT_HeapBlock_String* str = CLR_RT_HeapBlock_String::CreateInstance( *m_value, len ); CHECK_ALLOCATION(str); - char* dst = (char*)str->StringText(); + CLR_RT_HeapBlock_String *str = CLR_RT_HeapBlock_String::CreateInstance(*m_value, len); + CHECK_ALLOCATION(str); + char *dst = (char *)str->StringText(); - NANOCLR_CHECK_HRESULT(m_bf->ReadArray( (CLR_UINT8*)dst, len )); - dst[ len ] = 0; + NANOCLR_CHECK_HRESULT(m_bf->ReadArray((CLR_UINT8 *)dst, len)); + dst[len] = 0; } - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); } - else if(bits == CLR_RT_DataTypeLookup::c_NA) + else if (bits == CLR_RT_DataTypeLookup::c_NA) { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } else { - m_value->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(m_type->GetDataType(),0,1) ); - m_value->ClearData( ); + m_value->SetDataId(CLR_RT_HEAPBLOCK_RAW_ID(m_type->GetDataType(), 0, 1)); + m_value->ClearData(); - dst = (CLR_UINT64*)&m_value->NumericByRef().u8; + dst = (CLR_UINT64 *)&m_value->NumericByRef().u8; - fSigned = TypeHandler::GetSignOfType( m_type ); + fSigned = TypeHandler::GetSignOfType(m_type); } } else { - NANOCLR_SET_AND_LEAVE(TrackObject( res )); + NANOCLR_SET_AND_LEAVE(TrackObject(res)); } - if(m_hints.m_bitPacked) bits = m_hints.m_bitPacked; + if (m_hints._bitPacked) + bits = m_hints._bitPacked; - NANOCLR_CHECK_HRESULT(m_bf->ReadBits( val, bits )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits(val, bits)); - if(bits != 64) + if (bits != 64) { int revBits = 64 - bits; val <<= revBits; - if(fSigned) val = (CLR_UINT64)((CLR_INT64)val >> revBits); - else val = ( val >> revBits); + if (fSigned) + val = (CLR_UINT64)((CLR_INT64)val >> revBits); + else + val = (val >> revBits); } - if(m_hints.m_scale != 0) + if (m_hints._scale != 0) { - val *= m_hints.m_scale; + val *= m_hints._scale; } - *dst = val + m_hints.m_rangeBias; + *dst = val + m_hints._rangeBias; - res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + res = c_Action_None; + NANOCLR_SET_AND_LEAVE(S_OK); NANOCLR_NOCLEANUP(); } //--// -HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject( int& res ) +HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject(int &res) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - if(m_type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) + if (m_type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) { res = c_Action_ObjectElements; } @@ -1070,42 +1119,45 @@ HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject( int& res ) { res = c_Action_ObjectFields; - if(m_typeExpected && m_typeExpected->m_flags == CLR_RT_DataTypeLookup::c_ValueType) + if (m_typeExpected && m_typeExpected->m_flags == CLR_RT_DataTypeLookup::c_ValueType) { NANOCLR_SET_AND_LEAVE(S_OK); } } - NANOCLR_SET_AND_LEAVE(m_bf->TrackDuplicate( m_value )); + NANOCLR_SET_AND_LEAVE(m_bf->TrackDuplicate(m_value)); NANOCLR_NOCLEANUP(); } //////////////////////////////////////////////////////////////////////////////////////////////////// -HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_HeapBlock* type ) +HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( + CLR_RT_BinaryFormatter *parent, + SerializationHintsAttribute *hints, + CLR_RT_HeapBlock *type) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_TypeDef_Instance inst; - CLR_RT_TypeDescriptor desc; - CLR_RT_TypeDescriptor* pDesc; + CLR_RT_TypeDef_Instance inst; + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor *pDesc; SerializationHintsAttribute hintsTmp; - if(type && CLR_RT_ReflectionDef_Index::Convert( *type, inst, NULL )) + if (type && CLR_RT_ReflectionDef_Index::Convert(*type, inst, NULL)) { - NANOCLR_CHECK_HRESULT(desc.InitializeFromType( inst )); + NANOCLR_CHECK_HRESULT(desc.InitializeFromType(inst)); pDesc = &desc; - if(hints == NULL) + if (hints == NULL) { hints = &hintsTmp; NANOCLR_CLEAR(*hints); - hints->m_flags = (SerializationFlags)(SF_PointerNeverNull | SF_FixedType); + hints->_options = (SerializationFlags)(SF_PointerNeverNull | SF_FixedType); } } else @@ -1113,25 +1165,28 @@ HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* p pDesc = NULL; } - NANOCLR_SET_AND_LEAVE(CreateInstance( parent, hints, pDesc )); + NANOCLR_SET_AND_LEAVE(CreateInstance(parent, hints, pDesc)); NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* type ) +HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( + CLR_RT_BinaryFormatter *parent, + SerializationHintsAttribute *hints, + CLR_RT_TypeDescriptor *type) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - State* ptr = EVENTCACHE_EXTRACT_NODE_INITTOZERO(g_CLR_RT_EventCache,State,DATATYPE_SERIALIZER_STATE); + State *ptr = EVENTCACHE_EXTRACT_NODE_INITTOZERO(g_CLR_RT_EventCache, State, DATATYPE_SERIALIZER_STATE); CHECK_ALLOCATION(ptr); - parent->m_states.LinkAtBack( ptr ); + parent->m_states.LinkAtBack(ptr); - ptr->m_parent = parent; + ptr->m_parent = parent; ptr->m_value_NeedProcessing = true; - ptr->m_value.TypeHandler_Initialize( parent, hints, type ); + ptr->m_value.TypeHandler_Initialize(parent, hints, type); NANOCLR_NOCLEANUP(); } @@ -1139,36 +1194,39 @@ HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* p void CLR_RT_BinaryFormatter::State::DestroyInstance() { NATIVE_PROFILE_CLR_SERIALIZATION(); - g_CLR_RT_EventCache.Append_Node( this ); + g_CLR_RT_EventCache.Append_Node(this); } //--// -HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_TypeDef_Instance& cls ) +HRESULT CLR_RT_BinaryFormatter::State::FindHints(SerializationHintsAttribute &hints, const CLR_RT_TypeDef_Instance &cls) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); NANOCLR_CLEAR(hints); - if(cls.m_target->flags & CLR_RECORD_TYPEDEF::TD_HasAttributes) + if (cls.m_target->flags & CLR_RECORD_TYPEDEF::TD_HasAttributes) { - CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( g_CLR_RT_WellKnownTypes.m_SerializationHintsAttribute ); - CLR_RT_AttributeEnumerator en; en.Initialize( cls ); + CLR_RT_TypeDef_Instance inst; + inst.InitializeFromIndex(g_CLR_RT_WellKnownTypes.m_SerializationHintsAttribute); + CLR_RT_AttributeEnumerator en; + en.Initialize(cls); - if(en.MatchNext( &inst, NULL )) + if (en.MatchNext(&inst, NULL)) { CLR_RT_AttributeParser parser; - NANOCLR_CHECK_HRESULT(parser.Initialize( en )); + NANOCLR_CHECK_HRESULT(parser.Initialize(en)); - while(true) + while (true) { - CLR_RT_AttributeParser::Value* val; + CLR_RT_AttributeParser::Value *val; - NANOCLR_CHECK_HRESULT(parser.Next( val )); + NANOCLR_CHECK_HRESULT(parser.Next(val)); - if(val == NULL) break; + if (val == NULL) + break; } } } @@ -1176,41 +1234,50 @@ HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& h NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_FieldDef_Instance& fld ) +HRESULT CLR_RT_BinaryFormatter::State::FindHints( + SerializationHintsAttribute &hints, + const CLR_RT_FieldDef_Instance &fld) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); NANOCLR_CLEAR(hints); - if(fld.m_target->flags & CLR_RECORD_FIELDDEF::FD_HasAttributes) + if (fld.m_target->flags & CLR_RECORD_FIELDDEF::FD_HasAttributes) { - CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( g_CLR_RT_WellKnownTypes.m_SerializationHintsAttribute ); - CLR_RT_AttributeEnumerator en; en.Initialize( fld ); + CLR_RT_TypeDef_Instance inst; + inst.InitializeFromIndex(g_CLR_RT_WellKnownTypes.m_SerializationHintsAttribute); + CLR_RT_AttributeEnumerator en; + en.Initialize(fld); - if(en.MatchNext( &inst, NULL )) + if (en.MatchNext(&inst, NULL)) { CLR_RT_AttributeParser parser; - NANOCLR_CHECK_HRESULT(parser.Initialize( en )); + NANOCLR_CHECK_HRESULT(parser.Initialize(en)); - while(true) + while (true) { - CLR_RT_AttributeParser::Value* val; + CLR_RT_AttributeParser::Value *val; - NANOCLR_CHECK_HRESULT(parser.Next( val )); + NANOCLR_CHECK_HRESULT(parser.Next(val)); - if(val == NULL) + if (val == NULL) { break; } else { - if (!strcmp( val->m_name, "Flags" )) hints.m_flags = (SerializationFlags)val->m_value.NumericByRef().u4; - else if(!strcmp( val->m_name, "ArraySize" )) hints.m_arraySize = val->m_value.NumericByRef().s4; - else if(!strcmp( val->m_name, "BitPacked" )) hints.m_bitPacked = val->m_value.NumericByRef().s4; - else if(!strcmp( val->m_name, "RangeBias" )) hints.m_rangeBias = val->m_value.NumericByRef().s8; - else if(!strcmp( val->m_name, "Scale" )) hints.m_scale = val->m_value.NumericByRef().u8; + if (!strcmp(val->m_name, "Flags")) + hints._options = (SerializationFlags)val->m_value.NumericByRef().u4; + else if (!strcmp(val->m_name, "ArraySize")) + hints._arraySize = val->m_value.NumericByRef().s4; + else if (!strcmp(val->m_name, "BitPacked")) + hints._bitPacked = val->m_value.NumericByRef().s4; + else if (!strcmp(val->m_name, "RangeBias")) + hints._rangeBias = val->m_value.NumericByRef().s8; + else if (!strcmp(val->m_name, "Scale")) + hints._scale = val->m_value.NumericByRef().u8; } } } @@ -1221,40 +1288,42 @@ HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& h //--// -HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst ) +HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing(CLR_RT_HeapBlock &dst) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_HeapBlock* src = m_value.m_value; - CLR_DataType dt = dst.DataType(); - CLR_DataType dt2 = (dt == DATATYPE_ARRAY_BYREF) ? (CLR_DataType)dst.DereferenceArray()->m_typeOfElement : dt; - - if(c_CLR_RT_DataTypeLookup[ dt2 ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) + CLR_RT_HeapBlock *src = m_value.m_value; + CLR_DataType dt = dst.DataType(); + CLR_DataType dt2 = (dt == DATATYPE_ARRAY_BYREF) ? (CLR_DataType)dst.DereferenceArray()->m_typeOfElement : dt; + + if (c_CLR_RT_DataTypeLookup[dt2].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) { - if(src && (c_CLR_RT_DataTypeLookup[ src->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) + if (src && + (c_CLR_RT_DataTypeLookup[src->DataType()].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) { - src = TypeHandler::FixNull( src ); + src = TypeHandler::FixNull(src); } - if(src == NULL || (c_CLR_RT_DataTypeLookup[ src->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) + if (src == NULL || + (c_CLR_RT_DataTypeLookup[src->DataType()].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } } else { - if(src) - { + if (src) + { bool fBox = false; - if(c_CLR_RT_DataTypeLookup[ src->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) + if (c_CLR_RT_DataTypeLookup[src->DataType()].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) { fBox = true; } - else if(src->IsAValueType()) + else if (src->IsAValueType()) { - if(dt == DATATYPE_ARRAY_BYREF) + if (dt == DATATYPE_ARRAY_BYREF) { fBox = (dt2 != DATATYPE_VALUETYPE); } @@ -1266,32 +1335,45 @@ HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst // // Box reflection types // - else if(src->DataType() == DATATYPE_REFLECTION) + else if (src->DataType() == DATATYPE_REFLECTION) { - const CLR_RT_ReflectionDef_Index* reflex; - const CLR_RT_TypeDef_Index* cls; + const CLR_RT_ReflectionDef_Index *reflex; + const CLR_RT_TypeDef_Index *cls = NULL; CLR_RT_HeapBlock *pDst = &dst; reflex = &(src->ReflectionDataConst()); - - switch(reflex->m_kind) + + switch (reflex->m_kind) { - case REFLECTION_ASSEMBLY : cls = &g_CLR_RT_WellKnownTypes.m_Assembly ; break; - case REFLECTION_TYPE : cls = &g_CLR_RT_WellKnownTypes.m_Type ; break; - case REFLECTION_TYPE_DELAYED: cls = &g_CLR_RT_WellKnownTypes.m_Type ; break; - case REFLECTION_CONSTRUCTOR : cls = &g_CLR_RT_WellKnownTypes.m_ConstructorInfo; break; - case REFLECTION_METHOD : cls = &g_CLR_RT_WellKnownTypes.m_MethodInfo ; break; - case REFLECTION_FIELD : cls = &g_CLR_RT_WellKnownTypes.m_FieldInfo ; break; + case REFLECTION_ASSEMBLY: + cls = &g_CLR_RT_WellKnownTypes.m_Assembly; + break; + case REFLECTION_TYPE: + cls = &g_CLR_RT_WellKnownTypes.m_Type; + break; + case REFLECTION_TYPE_DELAYED: + cls = &g_CLR_RT_WellKnownTypes.m_Type; + break; + case REFLECTION_CONSTRUCTOR: + cls = &g_CLR_RT_WellKnownTypes.m_ConstructorInfo; + break; + case REFLECTION_METHOD: + cls = &g_CLR_RT_WellKnownTypes.m_MethodInfo; + break; + case REFLECTION_FIELD: + cls = &g_CLR_RT_WellKnownTypes.m_FieldInfo; + break; } - // + // // Dereference array element and create boxed reflection type - // - if(dt == DATATYPE_ARRAY_BYREF) + // + if (dt == DATATYPE_ARRAY_BYREF) { - CLR_RT_HeapBlock_Array* array = dst.DereferenceArray(); FAULT_ON_NULL(array); + CLR_RT_HeapBlock_Array *array = dst.DereferenceArray(); + FAULT_ON_NULL(array); - pDst = (CLR_RT_HeapBlock*)array->GetElement( dst.ArrayIndex() ); + pDst = (CLR_RT_HeapBlock *)array->GetElement(dst.ArrayIndex()); } // @@ -1299,7 +1381,6 @@ HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst // g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*pDst, *cls); - // // Set reflection type // @@ -1308,24 +1389,25 @@ HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst NANOCLR_SET_AND_LEAVE(S_OK); } - if(fBox) + if (fBox) { - NANOCLR_CHECK_HRESULT(m_value.m_value->PerformBoxing( m_value.m_type->m_handlerCls )); + NANOCLR_CHECK_HRESULT(m_value.m_value->PerformBoxing(m_value.m_type->m_handlerCls)); } } else { - src = &m_value.m_value_tmp; src->SetObjectReference( NULL ); + src = &m_value.m_value_tmp; + src->SetObjectReference(NULL); } } - if(dt == DATATYPE_ARRAY_BYREF) + if (dt == DATATYPE_ARRAY_BYREF) { - NANOCLR_CHECK_HRESULT(src->StoreToReference( dst, 0 )); + NANOCLR_CHECK_HRESULT(src->StoreToReference(dst, 0)); } else { - dst.Assign( *src ); + dst.Assign(*src); } NANOCLR_NOCLEANUP(); @@ -1336,25 +1418,26 @@ HRESULT CLR_RT_BinaryFormatter::State::GetValue() NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - State* prev = (State*)Prev(); - if(prev->Prev() == NULL) + State *prev = (State *)Prev(); + if (prev->Prev() == NULL) { - NANOCLR_SET_AND_LEAVE(m_value.SetValue( &m_parent->m_value )); + NANOCLR_SET_AND_LEAVE(m_value.SetValue(&m_parent->m_value)); } - if(prev->m_fields_NeedProcessing) + if (prev->m_fields_NeedProcessing) { - NANOCLR_SET_AND_LEAVE(m_value.SetValue( prev->m_fields_Pointer )); + NANOCLR_SET_AND_LEAVE(m_value.SetValue(prev->m_fields_Pointer)); } - if(prev->m_array_NeedProcessing) + if (prev->m_array_NeedProcessing) { - CLR_RT_HeapBlock ref; ref.InitializeArrayReferenceDirect( *prev->m_array, prev->m_array_CurrentPos-1 ); + CLR_RT_HeapBlock ref; + ref.InitializeArrayReferenceDirect(*prev->m_array, prev->m_array_CurrentPos - 1); CLR_RT_HeapBlock val; - NANOCLR_CHECK_HRESULT(val.LoadFromReference( ref )); + NANOCLR_CHECK_HRESULT(val.LoadFromReference(ref)); - NANOCLR_SET_AND_LEAVE(m_value.SetValue( &val )); + NANOCLR_SET_AND_LEAVE(m_value.SetValue(&val)); } NANOCLR_NOCLEANUP(); @@ -1365,26 +1448,27 @@ HRESULT CLR_RT_BinaryFormatter::State::SetValueAndDestroyInstance() NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - if(m_parent->m_fDeserialize) + if (m_parent->m_fDeserialize) { - State* prev = (State*)Prev(); + State *prev = (State *)Prev(); - if(prev->Prev() == NULL) + if (prev->Prev() == NULL) { - NANOCLR_CHECK_HRESULT(AssignAndFixBoxing( m_parent->m_value )); + NANOCLR_CHECK_HRESULT(AssignAndFixBoxing(m_parent->m_value)); } else { - if(prev->m_fields_NeedProcessing) + if (prev->m_fields_NeedProcessing) { - NANOCLR_CHECK_HRESULT(AssignAndFixBoxing( *prev->m_fields_Pointer )); + NANOCLR_CHECK_HRESULT(AssignAndFixBoxing(*prev->m_fields_Pointer)); } - if(prev->m_array_NeedProcessing) + if (prev->m_array_NeedProcessing) { - CLR_RT_HeapBlock ref; ref.InitializeArrayReferenceDirect( *prev->m_array, prev->m_array_CurrentPos-1 ); + CLR_RT_HeapBlock ref; + ref.InitializeArrayReferenceDirect(*prev->m_array, prev->m_array_CurrentPos - 1); - NANOCLR_CHECK_HRESULT(AssignAndFixBoxing( ref )); + NANOCLR_CHECK_HRESULT(AssignAndFixBoxing(ref)); } } } @@ -1401,146 +1485,149 @@ HRESULT CLR_RT_BinaryFormatter::State::Advance() NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - if(m_value_NeedProcessing) + if (m_value_NeedProcessing) { int res; m_value_NeedProcessing = false; - if(m_parent->m_fDeserialize) + if (m_parent->m_fDeserialize) { - NANOCLR_CHECK_HRESULT(m_value.ReadSignature( res )); + NANOCLR_CHECK_HRESULT(m_value.ReadSignature(res)); #if defined(NANOCLR_APPDOMAINS) - //Make sure that the type being deserialized is loaded in the current appDomain + // Make sure that the type being deserialized is loaded in the current appDomain { - if(m_parent->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) + if (m_parent->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) { - CLR_RT_TypeDef_Index idx; idx.Clear(); - CLR_RT_HeapBlock* value = m_value.m_value; + CLR_RT_TypeDef_Index idx; + idx.Clear(); + CLR_RT_HeapBlock *value = m_value.m_value; - if(value && value->DataType() == DATATYPE_REFLECTION) - { - switch(value->ReflectionDataConst().m_kind) + if (value && value->DataType() == DATATYPE_REFLECTION) + { + switch (value->ReflectionDataConst().m_kind) { case REFLECTION_TYPE: idx.m_data = value->ReflectionDataConst().m_data.m_type.m_data; break; - case REFLECTION_TYPE_DELAYED: - //should this be allowed for appdomain+marshaling??? - break; + case REFLECTION_TYPE_DELAYED: + // should this be allowed for appdomain+marshaling??? + break; case REFLECTION_ASSEMBLY: + { + CLR_RT_Assembly_Instance inst; + + if (!inst.InitializeFromIndex(value->ReflectionDataConst().m_data.m_assm)) { - CLR_RT_Assembly_Instance inst; - - if(!inst.InitializeFromIndex( value->ReflectionDataConst().m_data.m_assm )) - { - _ASSERTE(false); - } - - if(!g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly( inst.m_assm )) - { - NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); - } + _ASSERTE(false); } - break; - case REFLECTION_CONSTRUCTOR: - case REFLECTION_METHOD: - { - CLR_RT_MethodDef_Instance inst; - if(!inst.InitializeFromIndex( value->ReflectionDataConst().m_data.m_method )) - { - _ASSERTE(false); - } + if (!g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly(inst.m_assm)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); + } + } + break; + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + { + CLR_RT_MethodDef_Instance inst; - idx.Set( inst.Assembly(), inst.CrossReference().GetOwner() ); + if (!inst.InitializeFromIndex(value->ReflectionDataConst().m_data.m_method)) + { + _ASSERTE(false); } - break; + + idx.Set(inst.Assembly(), inst.CrossReference().GetOwner()); + } + break; case REFLECTION_FIELD: + { + CLR_RT_FieldDef_Instance inst; + CLR_RT_TypeDescriptor desc; + + if (!inst.InitializeFromIndex(value->ReflectionDataConst().m_data.m_field)) { - CLR_RT_FieldDef_Instance inst; - CLR_RT_TypeDescriptor desc; - - if(!inst.InitializeFromIndex( value->ReflectionDataConst().m_data.m_field )) - { - _ASSERTE(false); - } - - NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition( inst )); - - idx = desc.m_handlerCls; + _ASSERTE(false); } - break; + + NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition(inst)); + + idx = desc.m_handlerCls; + } + break; } } - else if(m_value.m_type) + else if (m_value.m_type) { - idx = m_value.m_type->m_handlerCls; + idx = m_value.m_type->m_handlerCls; } - if(idx.m_data != 0) + if (idx.m_data != 0) { - NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->VerifyTypeIsLoaded( idx )); + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->VerifyTypeIsLoaded(idx)); } } } #endif - } else { NANOCLR_CHECK_HRESULT(GetValue()); - NANOCLR_CHECK_HRESULT(m_value.EmitSignature( res )); + NANOCLR_CHECK_HRESULT(m_value.EmitSignature(res)); } - if(res != TypeHandler::c_Action_None) + if (res != TypeHandler::c_Action_None) { - if(m_parent->m_fDeserialize) + if (m_parent->m_fDeserialize) { - NANOCLR_CHECK_HRESULT(m_value.ReadValue( res )); - + NANOCLR_CHECK_HRESULT(m_value.ReadValue(res)); } else { - NANOCLR_CHECK_HRESULT(m_value.EmitValue( res )); + NANOCLR_CHECK_HRESULT(m_value.EmitValue(res)); } - switch(res) + switch (res) { - case TypeHandler::c_Action_None: - break; + case TypeHandler::c_Action_None: + break; - case TypeHandler::c_Action_ObjectFields: + case TypeHandler::c_Action_ObjectFields: { m_fields_NeedProcessing = true; - m_fields_CurrentClass = m_value.m_type->m_handlerCls; - m_fields_CurrentField = 0; - m_fields_Pointer = NULL; + m_fields_CurrentClass = m_value.m_type->m_handlerCls; + m_fields_CurrentField = 0; + m_fields_Pointer = NULL; break; } - case TypeHandler::c_Action_ObjectElements: + case TypeHandler::c_Action_ObjectElements: { m_array_NeedProcessing = true; - m_array_CurrentPos = 0; + m_array_CurrentPos = 0; - if(m_value.m_type->m_flags & CLR_RT_DataTypeLookup::c_ArrayList) + if (m_value.m_type->m_flags & CLR_RT_DataTypeLookup::c_ArrayList) { int capacity; - NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( *m_value.m_value, m_array, m_array_LastPos, capacity )); + NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( + *m_value.m_value, + m_array, + m_array_LastPos, + capacity)); m_array_ExpectedType = NULL; } else { - m_array = m_value.m_value->DereferenceArray(); + m_array = m_value.m_value->DereferenceArray(); m_array_LastPos = m_array->m_numOfElements; m_array_ExpectedType = &m_array_ExpectedType_Tmp; - m_value.m_type->GetElementType( *m_array_ExpectedType ); + m_value.m_type->GetElementType(*m_array_ExpectedType); } break; @@ -1549,19 +1636,18 @@ HRESULT CLR_RT_BinaryFormatter::State::Advance() } } - if(m_fields_NeedProcessing) + if (m_fields_NeedProcessing) { NANOCLR_SET_AND_LEAVE(AdvanceToTheNextField()); } - if(m_array_NeedProcessing) + if (m_array_NeedProcessing) { NANOCLR_SET_AND_LEAVE(AdvanceToTheNextElement()); } NANOCLR_SET_AND_LEAVE(SetValueAndDestroyInstance()); - NANOCLR_NOCLEANUP(); } @@ -1572,33 +1658,35 @@ HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextField() NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - while(NANOCLR_INDEX_IS_VALID(m_fields_CurrentClass)) + while (NANOCLR_INDEX_IS_VALID(m_fields_CurrentClass)) { - if(m_fields_CurrentField < m_fields_CurrentClass.m_target->iFields_Num) + if (m_fields_CurrentField < m_fields_CurrentClass.m_target->iFields_Num) { - int offset = m_fields_CurrentClass.m_target->iFields_First + m_fields_CurrentField++; - CLR_RT_FieldDef_Index idx ; idx.Set( m_fields_CurrentClass.Assembly(), offset ); - CLR_RT_FieldDef_Instance inst; inst.InitializeFromIndex( idx ); + int offset = m_fields_CurrentClass.m_target->iFields_First + m_fields_CurrentField++; + CLR_RT_FieldDef_Index idx; + idx.Set(m_fields_CurrentClass.Assembly(), offset); + CLR_RT_FieldDef_Instance inst; + inst.InitializeFromIndex(idx); m_fields_Pointer = m_value.m_value->Dereference() + inst.CrossReference().m_offset; - if((inst.m_target->flags & CLR_RECORD_FIELDDEF::FD_NotSerialized) == 0) + if ((inst.m_target->flags & CLR_RECORD_FIELDDEF::FD_NotSerialized) == 0) { SerializationHintsAttribute hints; - CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor desc; - if(m_value.m_type->m_flags & CLR_RT_DataTypeLookup::c_Enum) + if (m_value.m_type->m_flags & CLR_RT_DataTypeLookup::c_Enum) { hints = m_value.m_hints; } else { - NANOCLR_CHECK_HRESULT(FindHints( hints, inst )); + NANOCLR_CHECK_HRESULT(FindHints(hints, inst)); } - NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition( inst )); + NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition(inst)); - NANOCLR_SET_AND_LEAVE(State::CreateInstance( m_parent, &hints, &desc )); + NANOCLR_SET_AND_LEAVE(State::CreateInstance(m_parent, &hints, &desc)); } } else @@ -1620,30 +1708,34 @@ HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - if(m_array_ExpectedType && (c_CLR_RT_DataTypeLookup[ m_array->m_typeOfElement ].m_flags & CLR_RT_DataTypeLookup::c_Numeric)) + if (m_array_ExpectedType && + (c_CLR_RT_DataTypeLookup[m_array->m_typeOfElement].m_flags & CLR_RT_DataTypeLookup::c_Numeric)) { - CLR_UINT8* ptr = m_array->GetFirstElement(); - CLR_UINT32 bits = TypeHandler::GetSizeOfType( m_array_ExpectedType ); - int count = m_array_LastPos; - bool fDeserialize = m_parent->m_fDeserialize; + CLR_UINT8 *ptr = m_array->GetFirstElement(); + CLR_UINT32 bits = TypeHandler::GetSizeOfType(m_array_ExpectedType); + int count = m_array_LastPos; + bool fDeserialize = m_parent->m_fDeserialize; CLR_UINT32 size; CLR_UINT64 val; - size = bits / 8; if(size == 0) size = 1; + size = bits / 8; + if (size == 0) + size = 1; - while(count > 0) + while (count > 0) { - if(fDeserialize) + if (fDeserialize) { - NANOCLR_CHECK_HRESULT(m_parent->ReadBits( val, bits )); + NANOCLR_CHECK_HRESULT(m_parent->ReadBits(val, bits)); - memcpy( ptr, &val, size ); + memcpy(ptr, &val, size); } else { - val = 0; memcpy( &val, ptr, size ); + val = 0; + memcpy(&val, ptr, size); - NANOCLR_CHECK_HRESULT(m_parent->WriteBits( val, bits )); + NANOCLR_CHECK_HRESULT(m_parent->WriteBits(val, bits)); } ptr += size; @@ -1651,13 +1743,13 @@ HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() count--; } } - else if(m_array_CurrentPos < m_array_LastPos) + else if (m_array_CurrentPos < m_array_LastPos) { m_array_CurrentPos++; - SerializationHintsAttribute* hints; + SerializationHintsAttribute *hints; - if(m_value.m_hints.m_flags & (SF_FixedType | SF_PointerNeverNull)) + if (m_value.m_hints._options & (SF_FixedType | SF_PointerNeverNull)) { hints = &m_value.m_hints; } @@ -1666,7 +1758,7 @@ HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() hints = NULL; } - NANOCLR_SET_AND_LEAVE(State::CreateInstance( m_parent, hints, m_array_ExpectedType )); + NANOCLR_SET_AND_LEAVE(State::CreateInstance(m_parent, hints, m_array_ExpectedType)); } NANOCLR_SET_AND_LEAVE(SetValueAndDestroyInstance()); @@ -1676,27 +1768,31 @@ HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() //////////////////////////////////////////////////////////////////////////////////////////////////// -HRESULT CLR_RT_BinaryFormatter::CreateInstance( CLR_UINT8* buf, int len, CLR_RT_BinaryFormatter*& res ) +HRESULT CLR_RT_BinaryFormatter::CreateInstance(CLR_UINT8 *buf, int len, CLR_RT_BinaryFormatter *&res) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_BinaryFormatter* ptr = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_BinaryFormatter,DATATYPE_SERIALIZER_HEAD); - - res = ptr; CHECK_ALLOCATION(ptr); - - ptr->m_stream = NULL; // CLR_RT_HeapBlock_MemoryStream* m_stream; - ptr->m_idx = 0; // CLR_UINT32 m_idx; - ptr->m_lastTypeRead = 0; // CLR_UINT32 m_lastTypeRead; - ptr->m_duplicates.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_duplicates; // EVENT HEAP - NO RELOCATION - list of CLR_RT_BinaryFormatter::DuplicateTracker - ptr->m_states .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_states; // EVENT HEAP - NO RELOCATION - list of CLR_RT_BinaryFormatter::State - // - ptr->m_fDeserialize = (buf != NULL); // bool m_fDeserialize; - ptr->m_value.SetObjectReference( NULL ); // CLR_RT_HeapBlock m_value; - ptr->m_value_desc.TypeDescriptor_Initialize(); // CLR_RT_TypeDescriptor m_value_desc; + CLR_RT_BinaryFormatter *ptr = + EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache, CLR_RT_BinaryFormatter, DATATYPE_SERIALIZER_HEAD); + res = ptr; + CHECK_ALLOCATION(ptr); - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance( ptr->m_stream, buf, len )); + ptr->m_stream = NULL; // CLR_RT_HeapBlock_MemoryStream* m_stream; + ptr->m_idx = 0; // CLR_UINT32 m_idx; + ptr->m_lastTypeRead = 0; // CLR_UINT32 m_lastTypeRead; + ptr->m_duplicates + .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_duplicates; // EVENT HEAP - NO + // RELOCATION - list of CLR_RT_BinaryFormatter::DuplicateTracker + ptr->m_states.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_states; // EVENT HEAP - + // NO RELOCATION - list of CLR_RT_BinaryFormatter::State + // + ptr->m_fDeserialize = (buf != NULL); // bool m_fDeserialize; + ptr->m_value.SetObjectReference(NULL); // CLR_RT_HeapBlock m_value; + ptr->m_value_desc.TypeDescriptor_Initialize(); // CLR_RT_TypeDescriptor m_value_desc; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance(ptr->m_stream, buf, len)); NANOCLR_NOCLEANUP(); } @@ -1704,12 +1800,12 @@ HRESULT CLR_RT_BinaryFormatter::CreateInstance( CLR_UINT8* buf, int len, CLR_RT_ void CLR_RT_BinaryFormatter::DestroyInstance() { NATIVE_PROFILE_CLR_SERIALIZATION(); - m_states .DblLinkedList_PushToCache(); + m_states.DblLinkedList_PushToCache(); m_duplicates.DblLinkedList_PushToCache(); - CLR_RT_HeapBlock_MemoryStream::DeleteInstance( m_stream ); + CLR_RT_HeapBlock_MemoryStream::DeleteInstance(m_stream); - g_CLR_RT_EventCache.Append_Node( this ); + g_CLR_RT_EventCache.Append_Node(this); } HRESULT CLR_RT_BinaryFormatter::Advance() @@ -1717,9 +1813,11 @@ HRESULT CLR_RT_BinaryFormatter::Advance() NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - while(true) + while (true) { - State* top = (State*)m_states.LastNode(); if(top->Prev() == NULL) break; + State *top = (State *)m_states.LastNode(); + if (top->Prev() == NULL) + break; NANOCLR_CHECK_HRESULT(top->Advance()); } @@ -1729,47 +1827,65 @@ HRESULT CLR_RT_BinaryFormatter::Advance() //--// -void CLR_RT_BinaryFormatter::PrepareForGC( void* data ) +void CLR_RT_BinaryFormatter::PrepareForGC(void *data) { NATIVE_PROFILE_CLR_SERIALIZATION(); - if(data != NULL) + if (data != NULL) { - CLR_RT_BinaryFormatter* bf = (CLR_RT_BinaryFormatter*)data; + CLR_RT_BinaryFormatter *bf = (CLR_RT_BinaryFormatter *)data; - g_CLR_RT_GarbageCollector.CheckSingleBlock_Force( &bf->m_value ); + g_CLR_RT_GarbageCollector.CheckSingleBlock_Force(&bf->m_value); - NANOCLR_FOREACH_NODE(CLR_RT_BinaryFormatter::State,state,bf->m_states) + NANOCLR_FOREACH_NODE(CLR_RT_BinaryFormatter::State, state, bf->m_states) { - g_CLR_RT_GarbageCollector.CheckSingleBlock_Force( state->m_value.m_value ); + g_CLR_RT_GarbageCollector.CheckSingleBlock_Force(state->m_value.m_value); } NANOCLR_FOREACH_NODE_END(); } } -HRESULT CLR_RT_BinaryFormatter::Serialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32 flags ) +HRESULT CLR_RT_BinaryFormatter::Serialize(CLR_RT_HeapBlock &refData, CLR_RT_HeapBlock &object) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_BinaryFormatter* bf = NULL; - CLR_RT_ProtectFromGC pgc( (void**)&bf, CLR_RT_BinaryFormatter::PrepareForGC ); + CLR_RT_HeapBlock cls; + CLR_UINT32 flags = 0; + + cls.SetObjectReference(NULL); + + // unbox reflection types + CLR_RT_HeapBlock *pObj = &object; + + if (pObj->DataType() == DATATYPE_OBJECT) + { + pObj = pObj->Dereference(); + + if (pObj && pObj->DataType() == DATATYPE_REFLECTION) + { + flags = CLR_RT_BinaryFormatter::c_Flags_Marshal; + } + } - refData.SetObjectReference( NULL ); + CLR_RT_BinaryFormatter *bf = NULL; + CLR_RT_ProtectFromGC pgc((void **)&bf, CLR_RT_BinaryFormatter::PrepareForGC); - NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::CreateInstance( NULL, 0, bf )); + refData.SetObjectReference(NULL); - NANOCLR_CHECK_HRESULT(State::CreateInstance( bf, NULL, cls )); + NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::CreateInstance(NULL, 0, bf)); + + NANOCLR_CHECK_HRESULT(State::CreateInstance(bf, NULL, &cls)); bf->m_flags = flags; - bf->m_value.Assign( object ); + bf->m_value.Assign(object); NANOCLR_CHECK_HRESULT(bf->Advance()); - NANOCLR_CHECK_HRESULT(bf->m_stream->ToArray( refData )); + NANOCLR_CHECK_HRESULT(bf->m_stream->ToArray(refData)); NANOCLR_CLEANUP(); - if(bf) + if (bf) { bf->DestroyInstance(); @@ -1779,49 +1895,81 @@ HRESULT CLR_RT_BinaryFormatter::Serialize( CLR_RT_HeapBlock& refData, CLR_RT_Hea NANOCLR_CLEANUP_END(); } -HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +HRESULT CLR_RT_BinaryFormatter::Deserialize( + CLR_RT_HeapBlock &refData, + CLR_RT_HeapBlock &object, + CLR_UINT32 *unknownType, + CLR_UINT32 flags) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_HeapBlock_Array* array = object.DereferenceArray(); + CLR_RT_HeapBlock cls; + + cls.SetObjectReference(NULL); - refData.SetObjectReference( NULL ); + // unbox reflection types + CLR_RT_HeapBlock *pObj = &object; - if(array != NULL) + if (pObj->DataType() == DATATYPE_OBJECT) { - NANOCLR_SET_AND_LEAVE(CLR_RT_BinaryFormatter::Deserialize( refData, array->GetFirstElement(), array->m_numOfElements, cls, unknownType, flags )); + pObj = pObj->Dereference(); + + if (pObj && pObj->DataType() == DATATYPE_REFLECTION) + { + flags = CLR_RT_BinaryFormatter::c_Flags_Marshal; + } + } + + CLR_RT_HeapBlock_Array *array = object.DereferenceArray(); + + refData.SetObjectReference(NULL); + + if (array != NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_RT_BinaryFormatter::Deserialize( + refData, + array->GetFirstElement(), + array->m_numOfElements, + &cls, + unknownType, + flags)); } NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT8* data, CLR_UINT32 size, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +HRESULT CLR_RT_BinaryFormatter::Deserialize( + CLR_RT_HeapBlock &refData, + CLR_UINT8 *data, + CLR_UINT32 size, + CLR_RT_HeapBlock *cls, + CLR_UINT32 *unknownType, + CLR_UINT32 flags) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - CLR_RT_BinaryFormatter* bf = NULL; - CLR_RT_ProtectFromGC pgc( (void**)&bf, CLR_RT_BinaryFormatter::PrepareForGC ); + CLR_RT_BinaryFormatter *bf = NULL; + CLR_RT_ProtectFromGC pgc((void **)&bf, CLR_RT_BinaryFormatter::PrepareForGC); - refData.SetObjectReference( NULL ); + refData.SetObjectReference(NULL); - NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::CreateInstance( data, size, bf )); + NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::CreateInstance(data, size, bf)); - NANOCLR_CHECK_HRESULT(State::CreateInstance( bf, NULL, cls )); + NANOCLR_CHECK_HRESULT(State::CreateInstance(bf, NULL, cls)); bf->m_flags = flags; NANOCLR_CHECK_HRESULT(bf->Advance()); - refData.Assign( bf->m_value ); - + refData.Assign(bf->m_value); NANOCLR_CLEANUP(); - if(bf) + if (bf) { - if(unknownType) + if (unknownType) { *unknownType = (hr == CLR_E_WRONG_TYPE) ? bf->m_lastTypeRead : 0; } @@ -1836,31 +1984,32 @@ HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT //--// -HRESULT CLR_RT_BinaryFormatter::TrackDuplicate( CLR_RT_HeapBlock* object ) +HRESULT CLR_RT_BinaryFormatter::TrackDuplicate(CLR_RT_HeapBlock *object) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - DuplicateTracker* ptr = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,DuplicateTracker,DATATYPE_SERIALIZER_DUPLICATE); + DuplicateTracker *ptr = + EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache, DuplicateTracker, DATATYPE_SERIALIZER_DUPLICATE); CHECK_ALLOCATION(ptr); - m_duplicates.LinkAtBack( ptr ); + m_duplicates.LinkAtBack(ptr); - ptr->m_ptr = TypeHandler::FixDereference( object ); + ptr->m_ptr = TypeHandler::FixDereference(object); ptr->m_idx = m_idx++; NANOCLR_NOCLEANUP(); } -CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate( CLR_RT_HeapBlock* object ) +CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate(CLR_RT_HeapBlock *object) { NATIVE_PROFILE_CLR_SERIALIZATION(); - object = TypeHandler::FixDereference( object ); + object = TypeHandler::FixDereference(object); - NANOCLR_FOREACH_NODE(DuplicateTracker,ptr,m_duplicates) + NANOCLR_FOREACH_NODE(DuplicateTracker, ptr, m_duplicates) { - if(ptr->m_ptr == object) + if (ptr->m_ptr == object) { return ptr->m_idx; } @@ -1870,12 +2019,12 @@ CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate( CLR_RT_HeapBlock* object ) return (CLR_UINT32)-1; } -CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::GetDuplicate( CLR_UINT32 idx ) +CLR_RT_HeapBlock *CLR_RT_BinaryFormatter::GetDuplicate(CLR_UINT32 idx) { NATIVE_PROFILE_CLR_SERIALIZATION(); - NANOCLR_FOREACH_NODE(DuplicateTracker,ptr,m_duplicates) + NANOCLR_FOREACH_NODE(DuplicateTracker, ptr, m_duplicates) { - if(ptr->m_idx == idx) + if (ptr->m_idx == idx) { return ptr->m_ptr; } @@ -1887,27 +2036,48 @@ CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::GetDuplicate( CLR_UINT32 idx ) //--//--// -int CLR_RT_BinaryFormatter::BitsAvailable( ) { return m_stream->BitsAvailable( ); } +int CLR_RT_BinaryFormatter::BitsAvailable() +{ + return m_stream->BitsAvailable(); +} -HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT32& res, int bits ) { return m_stream->ReadBits ( res, bits ); } -HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT32 val, int bits ) { return m_stream->WriteBits ( val, bits ); } +HRESULT CLR_RT_BinaryFormatter::ReadBits(CLR_UINT32 &res, int bits) +{ + return m_stream->ReadBits(res, bits); +} +HRESULT CLR_RT_BinaryFormatter::WriteBits(CLR_UINT32 val, int bits) +{ + return m_stream->WriteBits(val, bits); +} -HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT64& res, int bits ) { return m_stream->ReadBits ( res, bits ); } -HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT64 val, int bits ) { return m_stream->WriteBits ( val, bits ); } +HRESULT CLR_RT_BinaryFormatter::ReadBits(CLR_UINT64 &res, int bits) +{ + return m_stream->ReadBits(res, bits); +} +HRESULT CLR_RT_BinaryFormatter::WriteBits(CLR_UINT64 val, int bits) +{ + return m_stream->WriteBits(val, bits); +} -HRESULT CLR_RT_BinaryFormatter::ReadArray ( CLR_UINT8* buf, int bytes ) { return m_stream->ReadArray ( buf, bytes ); } -HRESULT CLR_RT_BinaryFormatter::WriteArray ( const CLR_UINT8* buf, int bytes ) { return m_stream->WriteArray ( buf, bytes ); } +HRESULT CLR_RT_BinaryFormatter::ReadArray(CLR_UINT8 *buf, int bytes) +{ + return m_stream->ReadArray(buf, bytes); +} +HRESULT CLR_RT_BinaryFormatter::WriteArray(const CLR_UINT8 *buf, int bytes) +{ + return m_stream->WriteArray(buf, bytes); +} -HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned( CLR_UINT32& val ) +HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned(CLR_UINT32 &val) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); CLR_UINT32 extra; - NANOCLR_CHECK_HRESULT(m_stream->ReadBits( val, 8 )); + NANOCLR_CHECK_HRESULT(m_stream->ReadBits(val, 8)); - if(val == 0xFF) + if (val == 0xFF) { val = 0xFFFFFFFF; } @@ -1915,60 +2085,66 @@ HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned( CLR_UINT32& val ) { int bits = 0; - switch(val & 0xC0) + switch (val & 0xC0) { - case 0x00: bits = 0; break; - case 0x40: bits = 0; break; - case 0x80: bits = 8; break; - case 0xC0: bits = 24; break; + case 0x00: + bits = 0; + break; + case 0x40: + bits = 0; + break; + case 0x80: + bits = 8; + break; + case 0xC0: + bits = 24; + break; } - if(bits) + if (bits) { - hr = m_stream->ReadBits( extra, bits ); + hr = m_stream->ReadBits(extra, bits); val = ((val & ~0xC0) << bits) | extra; } } - NANOCLR_CLEANUP(); NANOCLR_CLEANUP_END(); } -HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned( CLR_UINT32 val ) +HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned(CLR_UINT32 val) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); int bits; - if(val == 0xFFFFFFFF) + if (val == 0xFFFFFFFF) { bits = 8; } - else if(val < 0x80) + else if (val < 0x80) { bits = 8; } - else if(val < 0x3F00) + else if (val < 0x3F00) { - val |= 0x8000; - bits = 16; + val |= 0x8000; + bits = 16; } - else if(val < 0x3F000000) + else if (val < 0x3F000000) { - val |= 0xC0000000; - bits = 32; + val |= 0xC0000000; + bits = 32; } else { NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); } - NANOCLR_CHECK_HRESULT(m_stream->WriteBits( val, bits )); - + NANOCLR_CHECK_HRESULT(m_stream->WriteBits(val, bits)); NANOCLR_CLEANUP(); @@ -1977,40 +2153,39 @@ HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned( CLR_UINT32 val ) //--// -HRESULT CLR_RT_BinaryFormatter::ReadType( CLR_RT_ReflectionDef_Index& val ) +HRESULT CLR_RT_BinaryFormatter::ReadType(CLR_RT_ReflectionDef_Index &val) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - NANOCLR_CHECK_HRESULT(m_stream->ReadBits( m_lastTypeRead, 32 )); + NANOCLR_CHECK_HRESULT(m_stream->ReadBits(m_lastTypeRead, 32)); - val.InitializeFromHash( m_lastTypeRead ); + val.InitializeFromHash(m_lastTypeRead); NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::WriteType( const CLR_RT_ReflectionDef_Index& val ) +HRESULT CLR_RT_BinaryFormatter::WriteType(const CLR_RT_ReflectionDef_Index &val) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(WriteType( val.GetTypeHash() )); + NANOCLR_SET_AND_LEAVE(WriteType(val.GetTypeHash())); NANOCLR_NOCLEANUP(); } -HRESULT CLR_RT_BinaryFormatter::WriteType( CLR_UINT32 hash ) +HRESULT CLR_RT_BinaryFormatter::WriteType(CLR_UINT32 hash) { NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_HEADER(); - if(hash == 0xFFFFFFFF || hash == 0) + if (hash == 0xFFFFFFFF || hash == 0) { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } - NANOCLR_SET_AND_LEAVE(m_stream->WriteBits( hash, 32 )); + NANOCLR_SET_AND_LEAVE(m_stream->WriteBits(hash, 32)); NANOCLR_NOCLEANUP(); } - diff --git a/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp b/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp index 50be39ea8a..f0fb10be81 100644 --- a/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp +++ b/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp @@ -11,7 +11,7 @@ __nfweak bool CLR_RT_BinaryFormatter::SerializationEnabled() return false; } -__nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixDereference( CLR_RT_HeapBlock* v ) +__nfweak CLR_RT_HeapBlock *CLR_RT_BinaryFormatter::TypeHandler::FixDereference(CLR_RT_HeapBlock *v) { (void)v; @@ -19,7 +19,7 @@ __nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixDereference( return NULL; } -__nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixNull( CLR_RT_HeapBlock* v ) +__nfweak CLR_RT_HeapBlock *CLR_RT_BinaryFormatter::TypeHandler::FixNull(CLR_RT_HeapBlock *v) { (void)v; @@ -29,7 +29,10 @@ __nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixNull( CLR_RT_ //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CLR_RT_BinaryFormatter* bf, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* expected ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( + CLR_RT_BinaryFormatter *bf, + SerializationHintsAttribute *hints, + CLR_RT_TypeDescriptor *expected) { (void)bf; (void)hints; @@ -39,7 +42,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CL NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue( CLR_RT_HeapBlock* v ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue(CLR_RT_HeapBlock *v) { (void)v; @@ -55,7 +58,9 @@ __nfweak int CLR_RT_BinaryFormatter::TypeHandler::SignatureRequirements() return 0; } -__nfweak bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes( CLR_RT_TypeDescriptor* left, CLR_RT_TypeDescriptor* right ) +__nfweak bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes( + CLR_RT_TypeDescriptor *left, + CLR_RT_TypeDescriptor *right) { (void)left; (void)right; @@ -64,7 +69,7 @@ __nfweak bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes( CLR_RT_TypeDesc return true; } -__nfweak CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType( CLR_RT_TypeDescriptor* type ) +__nfweak CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType(CLR_RT_TypeDescriptor *type) { (void)type; @@ -72,7 +77,7 @@ __nfweak CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType( CLR_RT_T return (CLR_DataType)0; } -__nfweak CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType( CLR_RT_TypeDescriptor* type ) +__nfweak CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType(CLR_RT_TypeDescriptor *type) { (void)type; @@ -80,7 +85,7 @@ __nfweak CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType( CLR_RT_T return 0; } -__nfweak bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType( CLR_RT_TypeDescriptor* type ) +__nfweak bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType(CLR_RT_TypeDescriptor *type) { (void)type; @@ -90,7 +95,7 @@ __nfweak bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType( CLR_RT_TypeDes //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature( int& res ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature(int &res) { (void)res; @@ -98,7 +103,10 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature( int& res ) NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( int mask, CLR_RT_TypeDescriptor* type, CLR_RT_HeapBlock* value ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( + int mask, + CLR_RT_TypeDescriptor *type, + CLR_RT_HeapBlock *value) { (void)mask; (void)type; @@ -110,7 +118,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( int m //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature(int &res) { (void)res; @@ -120,7 +128,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue(int &res) { (void)res; @@ -128,7 +136,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue( int& res ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue(int &res) { (void)res; @@ -138,7 +146,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue( int& res ) //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject( int& res ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject(int &res) { (void)res; @@ -148,7 +156,10 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject( int& res ) //////////////////////////////////////////////////////////////////////////////////////////////////// -__nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_HeapBlock* type ) +__nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( + CLR_RT_BinaryFormatter *parent, + SerializationHintsAttribute *hints, + CLR_RT_HeapBlock *type) { (void)parent; (void)hints; @@ -158,7 +169,10 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFor NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* type ) +__nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( + CLR_RT_BinaryFormatter *parent, + SerializationHintsAttribute *hints, + CLR_RT_TypeDescriptor *type) { (void)parent; (void)hints; @@ -175,7 +189,8 @@ __nfweak void CLR_RT_BinaryFormatter::State::DestroyInstance() //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_TypeDef_Instance& cls ) +__nfweak HRESULT + CLR_RT_BinaryFormatter::State::FindHints(SerializationHintsAttribute &hints, const CLR_RT_TypeDef_Instance &cls) { (void)hints; (void)cls; @@ -184,7 +199,8 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAtt NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_FieldDef_Instance& fld ) +__nfweak HRESULT + CLR_RT_BinaryFormatter::State::FindHints(SerializationHintsAttribute &hints, const CLR_RT_FieldDef_Instance &fld) { (void)hints; (void)fld; @@ -195,7 +211,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAtt //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst ) +__nfweak HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing(CLR_RT_HeapBlock &dst) { (void)dst; @@ -241,7 +257,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() //////////////////////////////////////////////////////////////////////////////////////////////////// -__nfweak HRESULT CLR_RT_BinaryFormatter::CreateInstance( CLR_UINT8* buf, int len, CLR_RT_BinaryFormatter*& res ) +__nfweak HRESULT CLR_RT_BinaryFormatter::CreateInstance(CLR_UINT8 *buf, int len, CLR_RT_BinaryFormatter *&res) { (void)buf; (void)len; @@ -264,29 +280,30 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::Advance() //--// -__nfweak void CLR_RT_BinaryFormatter::PrepareForGC( void* data ) +__nfweak void CLR_RT_BinaryFormatter::PrepareForGC(void *data) { (void)data; NATIVE_PROFILE_CLR_SERIALIZATION(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::Serialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32 flags ) +__nfweak HRESULT CLR_RT_BinaryFormatter::Serialize(CLR_RT_HeapBlock &refData, CLR_RT_HeapBlock &object) { (void)refData; (void)object; - (void)cls; - (void)flags; NATIVE_PROFILE_CLR_SERIALIZATION(); NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +__nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( + CLR_RT_HeapBlock &refData, + CLR_RT_HeapBlock &object, + CLR_UINT32 *unknownType, + CLR_UINT32 flags) { (void)refData; (void)object; - (void)cls; (void)unknownType; (void)flags; @@ -294,7 +311,13 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT8* data, CLR_UINT32 size, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +__nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( + CLR_RT_HeapBlock &refData, + CLR_UINT8 *data, + CLR_UINT32 size, + CLR_RT_HeapBlock *cls, + CLR_UINT32 *unknownType, + CLR_UINT32 flags) { (void)refData; (void)data; @@ -309,7 +332,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::TrackDuplicate( CLR_RT_HeapBlock* object ) +__nfweak HRESULT CLR_RT_BinaryFormatter::TrackDuplicate(CLR_RT_HeapBlock *object) { (void)object; @@ -317,7 +340,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::TrackDuplicate( CLR_RT_HeapBlock* objec NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate( CLR_RT_HeapBlock* object ) +__nfweak CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate(CLR_RT_HeapBlock *object) { (void)object; @@ -325,7 +348,7 @@ __nfweak CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate( CLR_RT_HeapBlock* o return (CLR_UINT32)-1; } -__nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::GetDuplicate( CLR_UINT32 idx ) +__nfweak CLR_RT_HeapBlock *CLR_RT_BinaryFormatter::GetDuplicate(CLR_UINT32 idx) { (void)idx; @@ -335,18 +358,51 @@ __nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::GetDuplicate( CLR_UINT32 idx //--//--// -__nfweak int CLR_RT_BinaryFormatter::BitsAvailable( ) { return 0; } +__nfweak int CLR_RT_BinaryFormatter::BitsAvailable() +{ + return 0; +} -__nfweak HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT32& res, int bits ) { (void)res; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT32 val, int bits ) { (void)val; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadBits(CLR_UINT32 &res, int bits) +{ + (void)res; + (void)bits; + NANOCLR_FEATURE_STUB_RETURN(); +} +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteBits(CLR_UINT32 val, int bits) +{ + (void)val; + (void)bits; + NANOCLR_FEATURE_STUB_RETURN(); +} -__nfweak HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT64& res, int bits ) { (void)res; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT64 val, int bits ) { (void)val; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadBits(CLR_UINT64 &res, int bits) +{ + (void)res; + (void)bits; + NANOCLR_FEATURE_STUB_RETURN(); +} +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteBits(CLR_UINT64 val, int bits) +{ + (void)val; + (void)bits; + NANOCLR_FEATURE_STUB_RETURN(); +} -__nfweak HRESULT CLR_RT_BinaryFormatter::ReadArray ( CLR_UINT8* buf, int bytes ) { (void)buf; (void)bytes; NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::WriteArray ( const CLR_UINT8* buf, int bytes ) { (void)buf; (void)bytes; NANOCLR_FEATURE_STUB_RETURN(); } +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadArray(CLR_UINT8 *buf, int bytes) +{ + (void)buf; + (void)bytes; + NANOCLR_FEATURE_STUB_RETURN(); +} +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteArray(const CLR_UINT8 *buf, int bytes) +{ + (void)buf; + (void)bytes; + NANOCLR_FEATURE_STUB_RETURN(); +} -__nfweak HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned( CLR_UINT32& val ) +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned(CLR_UINT32 &val) { (void)val; @@ -354,7 +410,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned( CLR_UINT32& val NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned( CLR_UINT32 val ) +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned(CLR_UINT32 val) { (void)val; @@ -364,7 +420,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned( CLR_UINT32 val //--// -__nfweak HRESULT CLR_RT_BinaryFormatter::ReadType( CLR_RT_ReflectionDef_Index& val ) +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadType(CLR_RT_ReflectionDef_Index &val) { (void)val; @@ -372,7 +428,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::ReadType( CLR_RT_ReflectionDef_Index& v NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::WriteType( const CLR_RT_ReflectionDef_Index& val ) +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteType(const CLR_RT_ReflectionDef_Index &val) { (void)val; @@ -380,7 +436,7 @@ __nfweak HRESULT CLR_RT_BinaryFormatter::WriteType( const CLR_RT_ReflectionDef_I NANOCLR_FEATURE_STUB_RETURN(); } -__nfweak HRESULT CLR_RT_BinaryFormatter::WriteType( CLR_UINT32 hash ) +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteType(CLR_UINT32 hash) { (void)hash; diff --git a/src/CLR/Core/TypeSystem.cpp b/src/CLR/Core/TypeSystem.cpp index 28169f5c2f..2975b989cd 100644 --- a/src/CLR/Core/TypeSystem.cpp +++ b/src/CLR/Core/TypeSystem.cpp @@ -1545,8 +1545,11 @@ void CLR_RT_Assembly::Assembly_Initialize(CLR_RT_Assembly::Offsets &offsets) } } -{ITERATE_THROUGH_RECORDS(this, i, MethodDef, METHODDEF){dst->m_data = CLR_EmptyIndex; -} +{ + ITERATE_THROUGH_RECORDS(this, i, MethodDef, METHODDEF) + { + dst->m_data = CLR_EmptyIndex; + } } #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) @@ -2514,7 +2517,7 @@ HRESULT CLR_RT_AppDomain::MarshalObject(CLR_RT_HeapBlock &src, CLR_RT_HeapBlock CLR_RT_BinaryFormatter::Serialize(blk, src, NULL, CLR_RT_BinaryFormatter::c_Flags_Marshal)); (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain(appDomainDst); - hr = CLR_RT_BinaryFormatter::Deserialize(dst, blk, NULL, NULL, CLR_RT_BinaryFormatter::c_Flags_Marshal); + hr = CLR_RT_BinaryFormatter::Deserialize(dst, blk, NULL, CLR_RT_BinaryFormatter::c_Flags_Marshal); CLR_EE_DBG_RESTORE(NoCompaction, fNoCompaction); } diff --git a/src/CLR/Include/nanoCLR_Runtime__Serialization.h b/src/CLR/Include/nanoCLR_Runtime__Serialization.h index 9096ee121e..32446403f6 100644 --- a/src/CLR/Include/nanoCLR_Runtime__Serialization.h +++ b/src/CLR/Include/nanoCLR_Runtime__Serialization.h @@ -6,14 +6,14 @@ #ifndef NANOCLR_RUNTIME__SERIALIZATION_H #define NANOCLR_RUNTIME__SERIALIZATION_H +// clang-format off + struct CLR_RT_BinaryFormatter : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - { - ////////////////////////////////////////////////////////////////// - // - // Keep in sync with definitions in Reflection.cs!!!! - // Keep in sync with definitions in Reflection.cs!!!! - // Keep in sync with definitions in Reflection.cs!!!! - // + ////////////////////////////////////////////////////////////////////////////////////////////////////////// + // !!! KEEP IN SYNC WITH System.Runtime.Serialization.SerializationHintsAttribute (in managed code) !!! // + ////////////////////////////////////////////////////////////////////////////////////////////////////////// + static const int TE_L1 = 2; static const CLR_UINT32 TE_L1_Null = 0x00000000; static const CLR_UINT32 TE_L1_Duplicate = 0x00000001; // N bits for the duplicate id. @@ -42,10 +42,6 @@ struct CLR_RT_BinaryFormatter : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO // enum SerializationFlags { - SF_Encrypted = 0x00000001, - SF_Compressed = 0x00000002, // Value uses range compression (max 2^30 values). - SF_Optional = 0x00000004, // If the value cannot be deserialized, skip it. - SF_PointerNeverNull = 0x00000010, SF_ElementsNeverNull = 0x00000020, @@ -54,13 +50,17 @@ struct CLR_RT_BinaryFormatter : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO // struct SerializationHintsAttribute { - SerializationFlags m_flags; + SerializationFlags _options; - int m_arraySize; // -1 == extend to the end of the stream. + // -1 == extend to the end of the stream. + int _arraySize; - int m_bitPacked; // In bits. - CLR_INT64 m_rangeBias; - CLR_UINT64 m_scale; // For time, it's in ticks. + // In bits. + int _bitPacked; + CLR_INT64 _rangeBias; + + // For time, it's in ticks. + CLR_UINT64 _scale; }; // ////////////////////////////////////////////////////////////////// @@ -246,8 +246,8 @@ struct CLR_RT_BinaryFormatter : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO void DestroyInstance(); HRESULT Advance (); - static HRESULT Serialize ( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object , CLR_RT_HeapBlock* cls , CLR_UINT32 flags ); - static HRESULT Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object , CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ); + static HRESULT Serialize ( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object ); + static HRESULT Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object , CLR_UINT32* unknownType , CLR_UINT32 flags ); static HRESULT Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT8* data, CLR_UINT32 size, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ); HRESULT TrackDuplicate ( CLR_RT_HeapBlock* object ); @@ -281,4 +281,6 @@ struct CLR_RT_BinaryFormatter : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO static void PrepareForGC( void* data ); }; +// clang-format on + #endif // NANOCLR_RUNTIME__SERIALIZATION_H diff --git a/src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj b/src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj new file mode 100644 index 0000000000..13e4246a1e --- /dev/null +++ b/src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj @@ -0,0 +1,162 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + {C9264D0A-AC25-46B0-BD08-4A3252427F19} + Win32Proj + System.Runtime.Serialization + 10.0 + + + + StaticLibrary + true + v143 + Unicode + + + StaticLibrary + false + v143 + true + Unicode + + + StaticLibrary + true + v143 + Unicode + + + StaticLibrary + false + v143 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CLR\Core;..\CLR\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CLR\Core;..\CLR\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CLR\Core;..\CLR\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\targets\win32\Include;..\Include;..\CLR\Include;..\CLR\Core;..\CLR\CorLib;..\HAL\Include;..\PAL\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj.filters b/src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj.filters new file mode 100644 index 0000000000..a39795b480 --- /dev/null +++ b/src/System.Runtime.Serialization/System.Runtime.Serialization.vcxproj.filters @@ -0,0 +1,26 @@ + + + + + Source Files + + + Source Files + + + + + {ed983272-2da5-42a2-956f-57c46bc194f9} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {cb3271da-1d71-4807-a5aa-ab5d6daaccbf} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + + + Header Files + + + \ No newline at end of file diff --git a/src/System.Runtime.Serialization/nf_system_runtime_serialization.cpp b/src/System.Runtime.Serialization/nf_system_runtime_serialization.cpp new file mode 100644 index 0000000000..fb6a642b5e --- /dev/null +++ b/src/System.Runtime.Serialization/nf_system_runtime_serialization.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_runtime_serialization.h" + +// clang-format off + +static const CLR_RT_MethodHandler method_lookup[] = +{ + Library_nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter::Serialize___STATIC__SZARRAY_U1__OBJECT, + Library_nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter::Deserialize___STATIC__OBJECT__SZARRAY_U1, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Runtime_Serialization = +{ + "System.Runtime.Serialization", + 0x0A066871, + method_lookup, + { 100, 0, 0, 0 } +}; + + +// clang-format on diff --git a/src/System.Runtime.Serialization/nf_system_runtime_serialization.h b/src/System.Runtime.Serialization/nf_system_runtime_serialization.h new file mode 100644 index 0000000000..5d2f42731b --- /dev/null +++ b/src/System.Runtime.Serialization/nf_system_runtime_serialization.h @@ -0,0 +1,49 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef NF_SYSTEM_RUNTIME_SERIALIZATION_H +#define NF_SYSTEM_RUNTIME_SERIALIZATION_H + +#include +#include +#include + +// declared as struct SerializationHintsAttribute in src\CLR\Include\nanoCLR_Runtime__Serialization.h +// typedef enum __nfpack SerializationOptions +// { +// SerializationOptions_PointerNeverNull = 16, +// SerializationOptions_ElementsNeverNull = 32, +// SerializationOptions_FixedType = 256, +// } SerializationOptions; + +struct Library_nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter +{ + NANOCLR_NATIVE_DECLARE(Serialize___STATIC__SZARRAY_U1__OBJECT); + NANOCLR_NATIVE_DECLARE(Deserialize___STATIC__OBJECT__SZARRAY_U1); + + //--// +}; + +struct Library_nf_system_runtime_serialization_System_Runtime_Serialization_SerializationException +{ + static const int FIELD__Type = 5; + + //--// +}; + +struct Library_nf_system_runtime_serialization_System_Runtime_Serialization_SerializationHintsAttribute +{ + static const int FIELD__Options = 1; + static const int FIELD__ArraySize = 2; + static const int FIELD__BitPacked = 3; + static const int FIELD__RangeBias = 4; + static const int FIELD__Scale = 5; + + //--// +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Runtime_Serialization; + +#endif // NF_SYSTEM_RUNTIME_SERIALIZATION_H diff --git a/src/System.Runtime.Serialization/nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter.cpp b/src/System.Runtime.Serialization/nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter.cpp new file mode 100644 index 0000000000..ca43054f76 --- /dev/null +++ b/src/System.Runtime.Serialization/nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter.cpp @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_runtime_serialization.h" + +HRESULT Library_nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter:: + Serialize___STATIC__SZARRAY_U1__OBJECT(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_BinaryFormatter::Serialize(stack.PushValue(), stack.Arg0())); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_runtime_serialization_System_Runtime_Serialization_Formatters_Binary_BinaryFormatter:: + Deserialize___STATIC__OBJECT__SZARRAY_U1(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + CLR_UINT32 hash = 0; + + NANOCLR_SET_AND_LEAVE(CLR_RT_BinaryFormatter::Deserialize(stack.PushValue(), stack.Arg0(), &hash, 0)); + + NANOCLR_CLEANUP(); + + if (hr == CLR_E_WRONG_TYPE && hash != 0) + { + CLR_RT_HeapBlock &res = stack.m_owningThread->m_currentException; + + CLR_RT_TypeDef_Index serializationExceptionTypeDef; + + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( + "SerializationException", + "System.Runtime.Serialization", + serializationExceptionTypeDef); + + if ((Library_corlib_native_System_Exception::CreateInstance( + res, + serializationExceptionTypeDef, + CLR_E_UNKNOWN_TYPE, + &stack)) == S_OK) + { + CLR_RT_ReflectionDef_Index idx; + + idx.InitializeFromHash(hash); + + res.Dereference() + [Library_nf_system_runtime_serialization_System_Runtime_Serialization_SerializationException:: + FIELD__Type] + .SetReflection(idx); + } + + hr = CLR_E_PROCESS_EXCEPTION; + } + + NANOCLR_CLEANUP_END(); +} diff --git a/targets/netcore/nanoCLR.sln b/targets/netcore/nanoCLR.sln index 7b58939109..5d8c3b44ef 100644 --- a/targets/netcore/nanoCLR.sln +++ b/targets/netcore/nanoCLR.sln @@ -61,8 +61,6 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "NativeEventDispatcher_stub" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RPC_stub", "..\..\src\CLR\Core\RPC\RPC_stub.vcxproj", "{D0B2ADFE-3347-4D73-9364-9C36935D12F8}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Serialization_stub", "..\..\src\CLR\Core\Serialization\Serialization_stub.vcxproj", "{C337041D-344D-49FE-AD99-B137E7FD0188}" -EndProject Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Core", "Core", "{515E72C2-A29C-4742-B0EB-509801A04F5B}" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Core", "..\..\src\CLR\Core\Core.vcxproj", "{89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}" @@ -80,278 +78,414 @@ Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "nanoFramework.nanoCLR.Host" EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "System.Device.Gpio", "..\..\src\System.Device.Gpio\System.Device.Gpio.vcxproj", "{830A7E28-7B2B-4BE6-8888-A39775A0092A}" EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "System.Runtime.Serialization", "..\..\src\System.Runtime.Serialization\System.Runtime.Serialization.vcxproj", "{C9264D0A-AC25-46B0-BD08-4A3252427F19}" +EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Any CPU = Debug|Any CPU + Debug|x64 = Debug|x64 Debug|x86 = Debug|x86 Release|Any CPU = Release|Any CPU + Release|x64 = Release|x64 Release|x86 = Release|x86 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution {06700522-0275-4149-AC58-93445ADD1D32}.Debug|Any CPU.ActiveCfg = Debug|x64 {06700522-0275-4149-AC58-93445ADD1D32}.Debug|Any CPU.Build.0 = Debug|x64 + {06700522-0275-4149-AC58-93445ADD1D32}.Debug|x64.ActiveCfg = Debug|x64 + {06700522-0275-4149-AC58-93445ADD1D32}.Debug|x64.Build.0 = Debug|x64 {06700522-0275-4149-AC58-93445ADD1D32}.Debug|x86.ActiveCfg = Debug|Win32 {06700522-0275-4149-AC58-93445ADD1D32}.Debug|x86.Build.0 = Debug|Win32 {06700522-0275-4149-AC58-93445ADD1D32}.Release|Any CPU.ActiveCfg = Release|x64 {06700522-0275-4149-AC58-93445ADD1D32}.Release|Any CPU.Build.0 = Release|x64 + {06700522-0275-4149-AC58-93445ADD1D32}.Release|x64.ActiveCfg = Release|x64 + {06700522-0275-4149-AC58-93445ADD1D32}.Release|x64.Build.0 = Release|x64 {06700522-0275-4149-AC58-93445ADD1D32}.Release|x86.ActiveCfg = Release|Win32 {06700522-0275-4149-AC58-93445ADD1D32}.Release|x86.Build.0 = Release|Win32 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Debug|Any CPU.ActiveCfg = Debug|x64 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Debug|Any CPU.Build.0 = Debug|x64 + {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Debug|x64.ActiveCfg = Debug|x64 + {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Debug|x64.Build.0 = Debug|x64 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Debug|x86.ActiveCfg = Debug|Win32 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Debug|x86.Build.0 = Debug|Win32 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Release|Any CPU.ActiveCfg = Release|x64 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Release|Any CPU.Build.0 = Release|x64 + {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Release|x64.ActiveCfg = Release|x64 + {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Release|x64.Build.0 = Release|x64 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Release|x86.ActiveCfg = Release|Win32 {4F6DD35B-A0C8-47EE-880A-1224FADE9276}.Release|x86.Build.0 = Release|Win32 {84C62EFC-DBA2-4D47-BB81-322E8902C6D6}.Debug|Any CPU.ActiveCfg = Debug|x64 {84C62EFC-DBA2-4D47-BB81-322E8902C6D6}.Debug|Any CPU.Build.0 = Debug|x64 + {84C62EFC-DBA2-4D47-BB81-322E8902C6D6}.Debug|x64.ActiveCfg = Debug|x64 + {84C62EFC-DBA2-4D47-BB81-322E8902C6D6}.Debug|x64.Build.0 = Debug|x64 {84C62EFC-DBA2-4D47-BB81-322E8902C6D6}.Debug|x86.ActiveCfg = Debug|Win32 {84C62EFC-DBA2-4D47-BB81-322E8902C6D6}.Debug|x86.Build.0 = Debug|Win32 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Debug|x64 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Debug|Any CPU.Build.0 = Debug|x64 + {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Debug|x64.ActiveCfg = Debug|x64 + {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Debug|x64.Build.0 = Debug|x64 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Debug|x86.ActiveCfg = Debug|Win32 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Debug|x86.Build.0 = Debug|Win32 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Release|Any CPU.ActiveCfg = Release|x64 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Release|Any CPU.Build.0 = Release|x64 + {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Release|x64.ActiveCfg = Release|x64 + {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Release|x64.Build.0 = Release|x64 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Release|x86.ActiveCfg = Release|Win32 {830A7E28-7B2B-4BE6-8888-A39775A0092A}.Release|x86.Build.0 = Release|Win32 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Debug|Any CPU.ActiveCfg = Debug|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Debug|Any CPU.Build.0 = Debug|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Debug|x64.ActiveCfg = Debug|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Debug|x64.Build.0 = Debug|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Debug|x86.ActiveCfg = Debug|Win32 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Debug|x86.Build.0 = Debug|Win32 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Release|Any CPU.ActiveCfg = Release|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Release|Any CPU.Build.0 = Release|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Release|x64.ActiveCfg = Release|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Release|x64.Build.0 = Release|x64 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Release|x86.ActiveCfg = Release|Win32 + {C9264D0A-AC25-46B0-BD08-4A3252427F19}.Release|x86.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE @@ -382,11 +516,11 @@ Global {8ACD05E8-42FB-4A49-9D8B-79239F0EED25} = {966ADF45-F9C2-4559-A8C1-30DA28498442} {5406EB0C-2243-47E1-9F21-F2D7CA277092} = {966ADF45-F9C2-4559-A8C1-30DA28498442} {D0B2ADFE-3347-4D73-9364-9C36935D12F8} = {966ADF45-F9C2-4559-A8C1-30DA28498442} - {C337041D-344D-49FE-AD99-B137E7FD0188} = {966ADF45-F9C2-4559-A8C1-30DA28498442} {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1} = {515E72C2-A29C-4742-B0EB-509801A04F5B} {58E950CC-2FF6-423C-B006-A70A19272F20} = {515E72C2-A29C-4742-B0EB-509801A04F5B} {2A840DC3-FFA8-4562-BD13-AB2B0BA02CB6} = {515E72C2-A29C-4742-B0EB-509801A04F5B} {830A7E28-7B2B-4BE6-8888-A39775A0092A} = {E91B7D05-94FA-4E24-8981-411E6A60092E} + {C9264D0A-AC25-46B0-BD08-4A3252427F19} = {E91B7D05-94FA-4E24-8981-411E6A60092E} EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution SolutionGuid = {574F8A61-4693-4FDE-8770-BFAFF64BB7A0} diff --git a/targets/netcore/nanoFramework.nanoCLR/nanoFramework.nanoCLR.vcxproj b/targets/netcore/nanoFramework.nanoCLR/nanoFramework.nanoCLR.vcxproj index 3ed15116f2..dc35ac46b4 100644 --- a/targets/netcore/nanoFramework.nanoCLR/nanoFramework.nanoCLR.vcxproj +++ b/targets/netcore/nanoFramework.nanoCLR/nanoFramework.nanoCLR.vcxproj @@ -251,12 +251,6 @@ {16bf6131-a3b8-4b97-b867-e45669fb48bd} - - {c337041d-344d-49fe-ad99-b137e7fd0188} - false - false - false - {58e950cc-2ff6-423c-b006-a70a19272f20} @@ -320,6 +314,9 @@ {46556afc-c248-4082-abe6-9b07f4e57579} + + {c9264d0a-ac25-46b0-bd08-4a3252427f19} + {3cae286f-0ef8-45e4-8111-afa0aa9282b4} diff --git a/targets/win32/nanoCLR/Generated/CLR_RT_InteropAssembliesTable.cpp b/targets/win32/nanoCLR/Generated/CLR_RT_InteropAssembliesTable.cpp index 327f4151fa..dcc80e6874 100644 --- a/targets/win32/nanoCLR/Generated/CLR_RT_InteropAssembliesTable.cpp +++ b/targets/win32/nanoCLR/Generated/CLR_RT_InteropAssembliesTable.cpp @@ -10,6 +10,7 @@ extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Math; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_System_Collections; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_System_Text; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Native; +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Runtime_Serialization; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_ResourceManager; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Storage; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Networking_Sntp; @@ -28,13 +29,13 @@ const CLR_RT_NativeAssemblyData *g_CLR_InteropAssembliesNativeData[] = { &g_CLR_AssemblyNative_nanoFramework_System_Text, &g_CLR_AssemblyNative_nanoFramework_ResourceManager, &g_CLR_AssemblyNative_nanoFramework_Runtime_Native, + &g_CLR_AssemblyNative_System_Runtime_Serialization, &g_CLR_AssemblyNative_nanoFramework_Runtime_Events, &g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs, &g_CLR_AssemblyNative_Windows_Storage, &g_CLR_AssemblyNative_nanoFramework_Networking_Sntp, &g_CLR_AssemblyNative_System_Net, &g_CLR_AssemblyNative_System_IO_Ports, - &g_CLR_AssemblyNative_System_Device_Gpio -}; + &g_CLR_AssemblyNative_System_Device_Gpio}; const uint16_t g_CLR_InteropAssembliesCount = ARRAYSIZE(g_CLR_InteropAssembliesNativeData); From 3700f16a53ee947ce4e8b04042990b164cbcdd92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 16 Dec 2022 17:30:57 +0000 Subject: [PATCH 320/572] Fix address of deployment region --- targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt | 2 +- .../SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt index da698ef41d..f48bb4d512 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakeLists.txt @@ -73,7 +73,7 @@ if(SRECORD_TOOL_AVAILABLE) nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 13000 + 0C000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) endif() diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld index 60294b9977..98793699a7 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/efm32gg11b_booter.ld @@ -33,7 +33,7 @@ __RAM_segment_used_end__ = 0; MEMORY { flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 5dde4a067805d2702ddf9d2800f4807377457729 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 19 Dec 2022 12:46:46 +0000 Subject: [PATCH 321/572] Fix CRC32 calculation for continuation --- .../SiliconLabs/_common/nanoSupport_CRC32.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c b/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c index 9774c6a459..bb084257c1 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c +++ b/targets/AzureRTOS/SiliconLabs/_common/nanoSupport_CRC32.c @@ -20,11 +20,16 @@ uint32_t SUPPORT_ComputeCRC(const void *rgBlock, const uint32_t nLength, const u return crc; } - // set intial value - GPCRC_InitValueSet(GPCRC, crc); + if(crc == 0) + { + // this is NOT continuing a previous CRC calculation + + // set intial value + GPCRC_InitValueSet(GPCRC, crc); - // Prepare GPCRC_DATA for inputs - GPCRC_Start(GPCRC); + // Prepare GPCRC_DATA for inputs + GPCRC_Start(GPCRC); + } for (uint32_t i = 0; i < nLength; i++) { From 34e3ed5eb1104bf24ff134e1d065f6772c9f8187 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Dec 2022 12:38:20 +0000 Subject: [PATCH 322/572] Port changes from upstream rename --- ...ative_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index c86975885b..f06d682cb7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -144,10 +144,10 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; spiDeviceConfig->BusConfiguration = (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___busConfiguration].NumericByRef().s4; - spiDeviceConfig->MD16bits = + spiDeviceConfig->DataIs16bits = config[SpiBaseConfiguration::FIELD___databitLength].NumericByRef().s4 == 16 ? true : false; // store this here too - palSpi->BufferIs16bits = spiDeviceConfig->MD16bits; + palSpi->BufferIs16bits = spiDeviceConfig->DataIs16bits; CPU_SPI_Initialize_Extended(busIndex, *spiDeviceConfig, true); From 5297c237b68b0f35c0abcf692ac60ddde5607a6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Dec 2022 12:48:11 +0000 Subject: [PATCH 323/572] Add SPI config for DUT - Closes Skyworks-Timing-Software/MCU#33 --- .../target_com_sky_nf_dev_spi_config.cpp | 13 +++++++++++++ .../target_com_sky_nf_dev_spi_config.h | 1 + 2 files changed, 14 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp index ea3cba003b..bef6c57e2b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp @@ -17,3 +17,16 @@ // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4, 4) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h index 56b68d1d4e..409945557b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h @@ -4,3 +4,4 @@ // #define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE From b76044a39b5c12d39239e72e9047621640db1e16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Dec 2022 18:56:50 +0000 Subject: [PATCH 324/572] Code clean-up --- .../SKY_EEVB_PROTO1/nanoBooter/main.c | 35 +++++++------------ .../SKY_EEVB_PROTO1/nanoCLR/main.c | 25 +++++-------- 2 files changed, 21 insertions(+), 39 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c index 81a7cf8dca..a5d6edbbe1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -65,11 +65,6 @@ void tx_application_define(void *first_unused_memory) // Create a byte memory pool from which to allocate the thread stacks. tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - // #if (HAL_NF_USE_STM32_CRC == TRUE) - // // startup crc - // crcStart(NULL); - // #endif - // initialize block storage list and devices // in CLR this is called in nanoHAL_Initialize() // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command @@ -149,11 +144,7 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); - // while (1) - // { - // __NOP(); - // } - /* Hang here forever... */ + // init boot clipboard InitBootClipboard(); @@ -166,18 +157,18 @@ int main(void) // // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter // //if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN) != 0) // { - // check for valid CLR image - // we are checking for a valid image at the deployment address, which is pointing to the CLR address - if (CheckValidCLRImage((uint32_t)&__deployment_start__)) - { - // there seems to be a valid CLR image - - // need to change HF clock to internal RCO so the CLR can boot smoothly - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); - - // launch nanoCLR - LaunchCLR((uint32_t)&__deployment_start__); - } + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } // } // } diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c index 311aa0c1e5..b0b152b165 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -59,26 +59,22 @@ TX_THREAD clrStartupThread; uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; extern void ClrStartupThread_entry(uint32_t parameter); -extern sl_status_t sl_usbd_vendor_read_bulk_sync(uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, - bool *p_enabled); +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); void BlinkThread_entry(uint32_t parameter) { (void)parameter; -// uint8_t buffer[10]; -// uint32_t p_xfer_len; -// sl_status_t reqStatus; -// bool conn; while (1) { GPIO_PinOutToggle(gpioPortE, 9); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); } } @@ -93,11 +89,6 @@ void tx_application_define(void *first_unused_memory) // start watchdog // Watchdog_Init(); - // #if (HAL_NF_USE_STM32_CRC == TRUE) - // // startup crc - // crcStart(NULL); - // #endif - #if (TRACE_TO_STDIO == TRUE) StdioPort_Init(); #endif From ec5438e8e747eccd4aae0478247c9baf195a5d09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 28 Dec 2022 19:16:37 +0000 Subject: [PATCH 325/572] Add stay in BL GPIO - Add GPIO config. - Update code checking for button press. --- .../SKY_EEVB_PROTO1/nanoBooter/main.c | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c index a5d6edbbe1..1b09c4b3ad 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -145,6 +145,9 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); + // configure + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + // init boot clipboard InitBootClipboard(); @@ -152,25 +155,25 @@ int main(void) // the board to remain in nanoBooter and not launching nanoCLR // check if there is a request to remain on nanoBooter - // if (!IsToRemainInBooter()) - // { - // // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter - // //if (GPIO_PinInGet(BSP_GPIO_PB0_PORT, BSP_GPIO_PB0_PIN) != 0) - // { - // check for valid CLR image - // we are checking for a valid image at the deployment address, which is pointing to the CLR address - if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + if (!IsToRemainInBooter()) { - // there seems to be a valid CLR image - - // need to change HF clock to internal RCO so the CLR can boot smoothly - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); - - // launch nanoCLR - LaunchCLR((uint32_t)&__deployment_start__); + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } } - // } - // } // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running sl_system_kernel_start(); From cdd0aee7538f3db232398440cddbfc4f1d5d945f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Dec 2022 00:00:39 +0000 Subject: [PATCH 326/572] Update ADC channels config - Closes Skyworks-Timing-Software/MCU#34 --- .../target_nano_gg_adc_config.cpp | 53 +++++++++++-------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp index 26e7a90b6e..32147d6ec7 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp @@ -5,31 +5,42 @@ #include -// PA15: ADC0 APORT2X Channel 15 -// PE15: ADC0 APORT4X Channel 15 -// PE14: ADC0 APORT4Y Channel 14 -// PE13: ADC0 APORT4X Channel 13 -// PE12: ADC0 APORT4Y Channel 12 -// PE11: ADC0 APORT4X Channel 11 +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - // MCU_ADC1 + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // {0, adcPosSelAPORT2XCH15}, - // MCU_ADC2 - {0, adcPosSelAPORT4XCH15}, - // MCU_ADC3 - {0, adcPosSelAPORT4YCH14}, - // MCU_ADC4 - {0, adcPosSelAPORT4XCH13}, - // MCU_ADC5 - {0, adcPosSelAPORT4YCH12}, - // MCU_ADC6 - {0, adcPosSelAPORT4XCH11}, - - // these are the internal sources - {0, adcPosSelTEMP}, - {0, adcPosSelAVDD}, + // + {0, adcPosSelAPORT3XCH6}, }; const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); From f8a15a7054c2f477c4d7be879dbf95e1c5eee864 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 29 Dec 2022 00:27:43 +0000 Subject: [PATCH 327/572] Update GPIO config for READY LED --- .../AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c | 4 ++-- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c index 1b09c4b3ad..b46688d09c 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c @@ -52,7 +52,7 @@ void BlinkThread_entry(uint32_t parameter) while (1) { - GPIO_PinOutToggle(gpioPortE, 9); + GPIO_PinOutToggle(gpioPortB, 12); tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); } } @@ -143,7 +143,7 @@ int main(void) sl_system_init(); // configure LED READY for output - GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); // configure GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c index b0b152b165..53a80cabf3 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c @@ -73,7 +73,7 @@ void BlinkThread_entry(uint32_t parameter) while (1) { - GPIO_PinOutToggle(gpioPortE, 9); + GPIO_PinOutToggle(gpioPortB, 12); tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); } } @@ -192,7 +192,7 @@ int main(void) sl_system_init(); // configure LED READY for output - GPIO_PinModeSet(gpioPortE, 9, gpioModePushPull, 0); + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); // init boot clipboard InitBootClipboard(); From d6f2b0ef2f7e4e6f8db792daf64bad3f2c52165e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Jan 2023 14:45:34 +0000 Subject: [PATCH 328/572] Update Gecko SDK to v4.2.0 --- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 901408d261..8aa8332b4a 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -70,7 +70,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.1.1") + set(GECKO_SDK_VERSION "v4.2.0") endif() if(NO_GECKO_SDK_SOURCE) From 36a236c8e313122891ee2987df724dddc45cb9b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Jan 2023 14:54:22 +0000 Subject: [PATCH 329/572] Port changes in CPU SPI - From #2518 --- .../SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index e6c7cb8104..0947a87aa4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -311,7 +311,7 @@ HRESULT CPU_SPI_nWrite_nRead( if (palSpi->ChipSelect >= 0) { // assert pin based on CS active level - CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); + CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActiveState); } if (sync) @@ -398,7 +398,7 @@ HRESULT CPU_SPI_nWrite_nRead( if (palSpi->ChipSelect >= 0) { // assert pin based on CS active level - CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActive); + CPU_GPIO_SetPinState(palSpi->ChipSelect, (GpioPinValue)sdev.ChipSelectActiveState); } // this is a Async operation @@ -581,7 +581,7 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon if (busConfiguration.DeviceChipSelect >= 0) { GetIoLine(busConfiguration.DeviceChipSelect, &port, &portPin); - GPIO_PinModeSet(port, portPin, gpioModePushPull, busConfiguration.ChipSelectActive ? 0 : 1); + GPIO_PinModeSet(port, portPin, gpioModePushPull, busConfiguration.ChipSelectActiveState ? 0 : 1); } } From 0abb760853eff467aa2e709c10e9dfa328ca1651 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Jan 2023 14:55:04 +0000 Subject: [PATCH 330/572] Migrate HAL Time to follow new code - From #2515 --- .../SiliconLabs/_include/targetHAL_Time.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h b/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h index 604aa20859..e58e91a0b7 100644 --- a/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h +++ b/targets/AzureRTOS/SiliconLabs/_include/targetHAL_Time.h @@ -10,4 +10,26 @@ #define HAL_Time_CurrentSysTicks tx_time_get +#ifdef __cplusplus +extern "C" +{ +#endif + + // Converts CMSIS sysTicks to .NET ticks (100 nanoseconds) + inline __attribute__((always_inline)) uint64_t HAL_Time_SysTicksToTime(uint64_t sysTicks) + { + // need to convert Azure RTOS ticks to 100 nanoseconds + return sysTicks * TX_TIMER_TICKS_PER_SECOND * 10; + } + + // because HAL_Time_SysTicksToTime needs to be called from C we need a proxy to allow it to be called from 'C' code + inline __attribute__((always_inline)) uint64_t HAL_Time_SysTicksToTime_C(uint64_t sysTicks) + { + return sysTicks * TX_TIMER_TICKS_PER_SECOND * 10; + } + +#ifdef __cplusplus +} +#endif + #endif //_TARGET_HAL_TIME_H_ From ade31d61424beb84e9932f9acdc3360e201b5267 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Jan 2023 15:05:31 +0000 Subject: [PATCH 331/572] Port changes in CPU SPI - From #2518 --- ...ative_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index f06d682cb7..27e218af14 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -128,7 +128,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) config = stack.Arg5().Dereference(); // CS is always active low - spiDeviceConfig->ChipSelectActive = false; + spiDeviceConfig->ChipSelectActiveState = false; // CS is controled by the Gecko SDK driver spiDeviceConfig->DeviceChipSelect = -1; // always bus master @@ -209,7 +209,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) fullDuplex = true; // Set up read/write settings for SPI_Write_Read call - rws = {fullDuplex, 0, palSpi->BufferIs16bits, 0}; + rws = {fullDuplex, 0, palSpi->BufferIs16bits, 0, palSpi->ChipSelect, false}; // Check to see if we should run async so as not to hold up other tasks isLongRunningOperation = System_Device_IsLongRunningOperation( From 9a26c716a6b92eee9eb1fd3650ed2cb8fe74b48f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Jan 2023 18:48:56 +0000 Subject: [PATCH 332/572] Work CI-CD - Add github action to merge upstream in main and skyworks-evb branches. Cron DISABLED . --- .../workflows/merge-upstream-skyworks-evb.yml | 36 +++++++++++++++++++ .github/workflows/merge-upstream.yml | 36 +++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 .github/workflows/merge-upstream-skyworks-evb.yml create mode 100644 .github/workflows/merge-upstream.yml diff --git a/.github/workflows/merge-upstream-skyworks-evb.yml b/.github/workflows/merge-upstream-skyworks-evb.yml new file mode 100644 index 0000000000..03b0e3c962 --- /dev/null +++ b/.github/workflows/merge-upstream-skyworks-evb.yml @@ -0,0 +1,36 @@ +name: Merge from upstream into skyworks-evb +on: + # schedule: + # # scheduled for 00:00 every day + # - cron: '0 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + ref: skyworks-evb + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + with: + target_sync_branch: skyworks-evb + upstream_sync_branch: main + upstream_sync_repo: nanoframework/nf-interpreter + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml new file mode 100644 index 0000000000..4eb8d2d06b --- /dev/null +++ b/.github/workflows/merge-upstream.yml @@ -0,0 +1,36 @@ +name: Merge from upstream into main +on: + # schedule: + # # scheduled for 00:00 every day + # - cron: '0 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + ref: main + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + with: + target_sync_branch: main + upstream_sync_branch: main + upstream_sync_repo: nanoframework/nf-interpreter + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} From 284774dde7185444eccbe2c1e0bcd5ab359f2c18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Jan 2023 18:58:38 +0000 Subject: [PATCH 333/572] Work CI-CD - Add github action to build EEVB1. --- .github/workflows/build_skyworks_evb1.yml | 52 +++++++++++++++++++++++ CMakeUserPresets.SKY_EEVB_PROTO1.json | 33 ++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 .github/workflows/build_skyworks_evb1.yml create mode 100644 CMakeUserPresets.SKY_EEVB_PROTO1.json diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml new file mode 100644 index 0000000000..9ee8f82e67 --- /dev/null +++ b/.github/workflows/build_skyworks_evb1.yml @@ -0,0 +1,52 @@ +name: Build SKY_EEVB_PROTO1 + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_PROTO1: + runs-on: windows-latest + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + + - uses: lukka/get-cmake@latest + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: 'latest' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + run: | + $file = "CMakeUserPresets.json" + Rename-Item -Path "CMakeUserPresets.SKY_EEVB_PROTO1.json" -NewName $file + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: 'SKY_EEVB_PROTO1' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel']" + buildPreset: 'SKY_EEVB_PROTO1' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v2 + with: + name: 'SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex diff --git a/CMakeUserPresets.SKY_EEVB_PROTO1.json b/CMakeUserPresets.SKY_EEVB_PROTO1.json new file mode 100644 index 0000000000..6c41ef25d4 --- /dev/null +++ b/CMakeUserPresets.SKY_EEVB_PROTO1.json @@ -0,0 +1,33 @@ +{ + "version": 3, + "configurePresets": [ + { + "name": "SKY_EEVB_PROTO1", + "inherits": [ + "SL_STK3701A_preset" + ], + "cacheVariables": { + "TARGET_BOARD": { + "type": "STRING", + "value": "${presetName}" + }, + "TARGET_SERIAL_BAUDRATE": "921600", + "GECKO_FEATURE_USBD_HID": "OFF", + "GECKO_FEATURE_USBD_WINUSB": "OFF", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Adc": "OFF", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_nanoFramework.Device.OneWire": "ON", + "NF_INTEROP_ASSEMBLIES": null + } + } + ], + "buildPresets": [ + { + "name": "SKY_EEVB_PROTO1", + "displayName": "SKY_EEVB_PROTO1", + "configurePreset": "SKY_EEVB_PROTO1" + } + ] +} \ No newline at end of file From 9c0b7b38403bf6502143b9d27761c6c47f9695b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:06:27 +0000 Subject: [PATCH 334/572] Update CMake preset for SKY EVB proto --- CMakeUserPresets.SKY_EEVB_PROTO1.json | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CMakeUserPresets.SKY_EEVB_PROTO1.json b/CMakeUserPresets.SKY_EEVB_PROTO1.json index 6c41ef25d4..0bdd96ab14 100644 --- a/CMakeUserPresets.SKY_EEVB_PROTO1.json +++ b/CMakeUserPresets.SKY_EEVB_PROTO1.json @@ -19,6 +19,10 @@ "API_System.Device.Adc": "OFF", "API_nanoFramework.GiantGecko.Adc": "ON", "API_nanoFramework.Device.OneWire": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "NF_INTEROP_ASSEMBLIES": null } } From 96ee6efa04a0c4e135eac7dace61156dc3ab5596 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:16:10 +0000 Subject: [PATCH 335/572] Fix duplicated include --- .../_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h index cc6d50b392..76482f3d71 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/sys_dev_spi_native_target.h @@ -12,7 +12,6 @@ #include #include -#include #include "nf_gecko_spi_driver.h" // set missing defines From 95efe99661d3e14e23751c1a07fa3a7f7d226d1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:16:35 +0000 Subject: [PATCH 336/572] Switch off System.IO.Ports for EVB preset --- CMakeUserPresets.SKY_EEVB_PROTO1.json | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeUserPresets.SKY_EEVB_PROTO1.json b/CMakeUserPresets.SKY_EEVB_PROTO1.json index 0bdd96ab14..2c977bf4ae 100644 --- a/CMakeUserPresets.SKY_EEVB_PROTO1.json +++ b/CMakeUserPresets.SKY_EEVB_PROTO1.json @@ -16,6 +16,7 @@ "GECKO_FEATURE_USBD_WINUSB": "OFF", "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", + "API_System.IO.Ports": "OFF", "API_System.Device.Adc": "OFF", "API_nanoFramework.GiantGecko.Adc": "ON", "API_nanoFramework.Device.OneWire": "ON", From db9cacc2a31cbfe6d88b43538169cd1c579c624a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:27:19 +0000 Subject: [PATCH 337/572] Revert CPU SPI to Skyworks version --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 39 ++++++++++++++----- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 0947a87aa4..7e7d1a4434 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -45,7 +45,7 @@ static void CompleteTransfer(NF_SpiDriver_Handle_t handle) } // Callback used when a async transfer operation completes -static void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) +void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) { (void)transferStatus; (void)itemsTransferred; @@ -477,10 +477,10 @@ HRESULT CPU_SPI_nWrite_nRead( NANOCLR_NOCLEANUP(); } -bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) +// this is exposing the extended call that allow for re-configuration of SPI +bool CPU_SPI_Initialize_Extended(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration, bool reconfigure) { NF_PAL_SPI *palSpi = NULL; - NF_SpiDriver_Init_t *initSpiData = NULL; Ecode_t configResult; GPIO_Port_TypeDef port; uint32_t portPin; @@ -541,7 +541,6 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon if (palSpi->Handle == NULL) { - // allocate memory for the USART_InitSync_TypeDef palSpi->Handle = (NF_SpiDriver_Handle_t)platform_malloc(sizeof(NF_SpiDriver_HandleData_t)); @@ -554,25 +553,27 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon memset(palSpi->Handle, 0, sizeof(NF_SpiDriver_HandleData_t)); // allocate memory for the NF_SpiDriver_Init_t - initSpiData = (NF_SpiDriver_Init_t *)platform_malloc(sizeof(NF_SpiDriver_Init_t)); + palSpi->InitSpiData = (NF_SpiDriver_Init_t *)platform_malloc(sizeof(NF_SpiDriver_Init_t)); // sanity check allocation - if (initSpiData == NULL) + if (palSpi->InitSpiData == NULL) { platform_free(palSpi->Handle); return false; } - memset(initSpiData, 0, sizeof(NF_SpiDriver_Init_t)); + memset(palSpi->InitSpiData, 0, sizeof(NF_SpiDriver_Init_t)); // call handler to configure pins - initSpiConfig(*initSpiData, busConfiguration.BusConfiguration == SpiBusConfiguration_HalfDuplex); + initSpiConfig(*palSpi->InitSpiData, busConfiguration.BusConfiguration == SpiBusConfiguration_HalfDuplex); + +jump_to_init: // get the SPI configuration - GetSpiConfig(busConfiguration, *initSpiData); + GetSpiConfig(busConfiguration, *palSpi->InitSpiData); - configResult = NF_SpiDriver_Init(palSpi->Handle, initSpiData); + configResult = NF_SpiDriver_Init(palSpi->Handle, palSpi->InitSpiData); _ASSERTE(configResult == ECODE_OK); palSpi->ChipSelect = busConfiguration.DeviceChipSelect; @@ -584,10 +585,28 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busCon GPIO_PinModeSet(port, portPin, gpioModePushPull, busConfiguration.ChipSelectActiveState ? 0 : 1); } } + else + { + // there's already a handle, check if we need to re-configure the SPI bus + if(reconfigure) + { + // deinitalize the SPI bus + NF_SpiDriver_DeInit(palSpi->Handle); + + // jump straight to init + goto jump_to_init; + } + } return true; } +// this is exposing the "standard" call +bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &busConfiguration) +{ + return CPU_SPI_Initialize_Extended(busIndex, busConfiguration, false); +} + bool CPU_SPI_Uninitialize(uint8_t busIndex) { NF_PAL_SPI *palSpi = NULL; From 42312053a58f3cd69c23fbd68d685b6560701eba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:34:16 +0000 Subject: [PATCH 338/572] Work CI-CD - Dummy change. --- .github/workflows/merge-upstream.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml index 4eb8d2d06b..2cbc65ce95 100644 --- a/.github/workflows/merge-upstream.yml +++ b/.github/workflows/merge-upstream.yml @@ -34,3 +34,4 @@ jobs: - name: Show value of 'has_new_commits' run: echo ${{ steps.sync.outputs.has_new_commits }} + From 0b61064f86eca3f5d11e4dd2b1f817312a12eb52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:37:12 +0000 Subject: [PATCH 339/572] Work CI-CD - Add maintenance github action. --- .github/workflows/merge-upstream.yml | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 .github/workflows/merge-upstream.yml diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml new file mode 100644 index 0000000000..4eb8d2d06b --- /dev/null +++ b/.github/workflows/merge-upstream.yml @@ -0,0 +1,36 @@ +name: Merge from upstream into main +on: + # schedule: + # # scheduled for 00:00 every day + # - cron: '0 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + ref: main + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + with: + target_sync_branch: main + upstream_sync_branch: main + upstream_sync_repo: nanoframework/nf-interpreter + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} From 8bb900d4538edebfac734d86ef4ccae4ea6030de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:39:41 +0000 Subject: [PATCH 340/572] Delete merge-upstream.yml --- .github/workflows/merge-upstream.yml | 36 ---------------------------- 1 file changed, 36 deletions(-) delete mode 100644 .github/workflows/merge-upstream.yml diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml deleted file mode 100644 index 4eb8d2d06b..0000000000 --- a/.github/workflows/merge-upstream.yml +++ /dev/null @@ -1,36 +0,0 @@ -name: Merge from upstream into main -on: - # schedule: - # # scheduled for 00:00 every day - # - cron: '0 0 * * *' - - workflow_dispatch: - -jobs: - merge-from-upstream-repo: - runs-on: ubuntu-latest - steps: - - name: Checkout - uses: actions/checkout@v3 - with: - ref: main - fetch-depth: 0 - token: ${{ secrets.GITHUB_TOKEN }} - - - name: Merge from upstream repo - uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 - with: - target_sync_branch: main - upstream_sync_branch: main - upstream_sync_repo: nanoframework/nf-interpreter - - - name: New commits found - if: steps.sync.outputs.has_new_commits == 'true' - run: echo "New commits were found to sync." - - - name: No new commits - if: steps.sync.outputs.has_new_commits == 'false' - run: echo "There were no new commits." - - - name: Show value of 'has_new_commits' - run: echo ${{ steps.sync.outputs.has_new_commits }} From db3d1d6061e39c06447438a32bbf6a2a219c9f26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 18:45:27 +0000 Subject: [PATCH 341/572] Work CI-CD - Add github actions. --- .github/workflows/build_skyworks_evb1.yml | 52 +++++++++++++++++++ .../workflows/merge-upstream-skyworks-evb.yml | 36 +++++++++++++ .github/workflows/merge-upstream.yml | 37 +++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 .github/workflows/build_skyworks_evb1.yml create mode 100644 .github/workflows/merge-upstream-skyworks-evb.yml create mode 100644 .github/workflows/merge-upstream.yml diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml new file mode 100644 index 0000000000..8b9778c19a --- /dev/null +++ b/.github/workflows/build_skyworks_evb1.yml @@ -0,0 +1,52 @@ +name: Build SKY_EEVB_PROTO1 + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_PROTO1: + runs-on: windows-latest + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + + - uses: lukka/get-cmake@latest + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '11.3.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + run: | + $file = "CMakeUserPresets.json" + Rename-Item -Path "CMakeUserPresets.SKY_EEVB_PROTO1.json" -NewName $file + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: 'SKY_EEVB_PROTO1' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel']" + buildPreset: 'SKY_EEVB_PROTO1' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v2 + with: + name: 'SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex diff --git a/.github/workflows/merge-upstream-skyworks-evb.yml b/.github/workflows/merge-upstream-skyworks-evb.yml new file mode 100644 index 0000000000..fed36c0c84 --- /dev/null +++ b/.github/workflows/merge-upstream-skyworks-evb.yml @@ -0,0 +1,36 @@ +name: Merge from upstream into skyworks-evb +on: + # schedule: + # # scheduled for 00:00 every day + # - cron: '0 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + ref: skyworks-evb + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + with: + target_sync_branch: skyworks-evb + upstream_sync_branch: main + upstream_sync_repo: Skyworks-Timing-Software/nf-interpreter + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml new file mode 100644 index 0000000000..2cbc65ce95 --- /dev/null +++ b/.github/workflows/merge-upstream.yml @@ -0,0 +1,37 @@ +name: Merge from upstream into main +on: + # schedule: + # # scheduled for 00:00 every day + # - cron: '0 0 * * *' + + workflow_dispatch: + +jobs: + merge-from-upstream-repo: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + ref: main + fetch-depth: 0 + token: ${{ secrets.GITHUB_TOKEN }} + + - name: Merge from upstream repo + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + with: + target_sync_branch: main + upstream_sync_branch: main + upstream_sync_repo: nanoframework/nf-interpreter + + - name: New commits found + if: steps.sync.outputs.has_new_commits == 'true' + run: echo "New commits were found to sync." + + - name: No new commits + if: steps.sync.outputs.has_new_commits == 'false' + run: echo "There were no new commits." + + - name: Show value of 'has_new_commits' + run: echo ${{ steps.sync.outputs.has_new_commits }} + From 76f0b1783fa65de4ec459f4e169d457fadb9629b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 3 Feb 2023 19:59:08 +0000 Subject: [PATCH 342/572] Fix for path lenght --- CMakeLists.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index afc59b80f6..7eb2358e0f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -34,10 +34,11 @@ set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/CMake/Modules) list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/CMake) ######################################################## +nf_check_path_limits() + include(binutils.common) include(binutils.ESP32) -nf_check_path_limits() ###################################################### # set build type to release if not specified otherwise From ba8004330ba1df72dc890bf65b07835a8cc5fbea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 8 Feb 2023 20:12:11 +0000 Subject: [PATCH 343/572] Add missing GP CRC init to platform init - Was missing as this target implements strong version of sl_platform_init. --- .../SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c index 8107177acc..c0d02691c1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c @@ -28,18 +28,21 @@ #include #include +extern void InitGpCrc(void); + void sl_platform_init(void) { CHIP_Init(); sl_device_init_nvic(); sl_board_preinit(); sl_device_init_dcdc(); - //sl_device_init_hfxo(); + // sl_device_init_hfxo(); sl_device_init_hfrco(); - //sl_device_init_lfxo(); + // sl_device_init_lfxo(); sl_device_init_lfrco(); sl_device_init_clocks(); sl_device_init_emu(); sl_board_init(); sl_power_manager_init(); + InitGpCrc(); } From 345e3709ff2c780f1b507597415b6b678b7690ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 8 Feb 2023 20:17:03 +0000 Subject: [PATCH 344/572] Fix linker file for SKY_EEVB_PROTO1 (booter build) --- .../SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld index ed9e23d4cc..e4ef8fc200 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -32,11 +32,11 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 904k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x000EE000, len = 904k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ } /* Linker script to place sections and symbol values. Should be used together From c9e25cb0812f1468c691f7f9c0cc8f422bd7e8cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 8 Feb 2023 20:24:46 +0000 Subject: [PATCH 345/572] Work CI-CD - Fix CMake. ***NO_CI*** --- CMakeLists.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7eb2358e0f..afc59b80f6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -34,11 +34,10 @@ set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/CMake/Modules) list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/CMake) ######################################################## -nf_check_path_limits() - include(binutils.common) include(binutils.ESP32) +nf_check_path_limits() ###################################################### # set build type to release if not specified otherwise From 151c7d9ee746f7faa58b945117e617e490f54e51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Feb 2023 00:08:04 +0000 Subject: [PATCH 346/572] Add CMake preset for SKY EVB1 - Update github action. --- .github/workflows/build_skyworks_evb1.yml | 15 ++++- CMakePresets.json | 1 + .../SKY_EEVB_PROTO1/CMakePresets.json | 65 +++++++++++++++++++ 3 files changed, 79 insertions(+), 2 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 8b9778c19a..bc302807f3 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -31,9 +31,20 @@ jobs: } - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config run: | - $file = "CMakeUserPresets.json" - Rename-Item -Path "CMakeUserPresets.SKY_EEVB_PROTO1.json" -NewName $file + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - run: nbgv cloud -a -c diff --git a/CMakePresets.json b/CMakePresets.json index d070b6f9a3..70673a9a53 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -6,6 +6,7 @@ "CMake/xtensa-esp32c3.json", "CMake/xtensa-esp32s2.json", "targets/AzureRTOS/SiliconLabs/SL_STK3701A/CMakePresets.json", + "targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json", "targets/AzureRTOS/ST/ORGPAL_PALTHREE/CMakePresets.json", "targets/AzureRTOS/ST/ST_B_L475E_IOT01A/CMakePresets.json", "targets/ChibiOS/ORGPAL_PALTHREE/CMakePresets.json", diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json new file mode 100644 index 0000000000..972e4f151a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json @@ -0,0 +1,65 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_EEVB_PROTO1", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "${presetName}", + "TARGET_NAME": "SKY_EEVB_PROTO1", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "SWO_OUTPUT": "OFF", + "NF_BUILD_RTM": "OFF", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "GECKO_FEATURE_USBD_HID": "OFF", + "GECKO_FEATURE_USBD_WINUSB": "OFF", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_EEVB_PROTO1", + "displayName": "SKY_EEVB_PROTO1", + "configurePreset": "SKY_EEVB_PROTO1" + } + ] +} From e78b7c387a54e1001c86148dd05f629a735192f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Feb 2023 00:35:08 +0000 Subject: [PATCH 347/572] Work CI-CD - Udpate gituhb action. --- .github/workflows/build_skyworks_evb1.yml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 8b9778c19a..bc302807f3 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -31,9 +31,20 @@ jobs: } - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config run: | - $file = "CMakeUserPresets.json" - Rename-Item -Path "CMakeUserPresets.SKY_EEVB_PROTO1.json" -NewName $file + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - run: nbgv cloud -a -c From b6d4a1c9c91fcbb1adab219ade9403af8b1c4c18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Feb 2023 17:36:35 +0000 Subject: [PATCH 348/572] Work CI-CD - Update action to latest version. --- .github/workflows/build_skyworks_evb1.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index bc302807f3..fe76eeb408 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -55,7 +55,7 @@ jobs: buildPreset: 'SKY_EEVB_PROTO1' buildPresetAdditionalArgs: "['--config MinSizeRel']" - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v3 with: name: 'SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | From 05e458fdb526411f808d494b4c663547bcc4fa7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Feb 2023 17:38:03 +0000 Subject: [PATCH 349/572] Work CI-CD - Enable cron config for daily merge from upstream. --- .github/workflows/merge-upstream.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml index 2cbc65ce95..3a3b54193c 100644 --- a/.github/workflows/merge-upstream.yml +++ b/.github/workflows/merge-upstream.yml @@ -1,8 +1,8 @@ name: Merge from upstream into main on: - # schedule: - # # scheduled for 00:00 every day - # - cron: '0 0 * * *' + schedule: + # scheduled for 00:00 every day + - cron: '0 0 * * *' workflow_dispatch: From 57805a756095e86896691ec1e5baae60a6679358 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 14 Feb 2023 17:39:23 +0000 Subject: [PATCH 350/572] Work CI-CD - Enable cron config for daily merge from main branch. --- .github/workflows/merge-upstream-skyworks-evb.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/merge-upstream-skyworks-evb.yml b/.github/workflows/merge-upstream-skyworks-evb.yml index fed36c0c84..050bea6594 100644 --- a/.github/workflows/merge-upstream-skyworks-evb.yml +++ b/.github/workflows/merge-upstream-skyworks-evb.yml @@ -1,8 +1,8 @@ name: Merge from upstream into skyworks-evb on: - # schedule: - # # scheduled for 00:00 every day - # - cron: '0 0 * * *' + schedule: + # scheduled for 00:00 every day + - cron: '15 0 * * *' workflow_dispatch: From 7d22b624b55bd2fc1e0284f261397ffe0ce0adb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 Feb 2023 14:35:52 +0000 Subject: [PATCH 351/572] Bump GCC version for gtihub action --- .github/workflows/build_skyworks_evb1.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index fe76eeb408..439d246dda 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -18,7 +18,7 @@ jobs: - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: - release: '11.3.Rel1' + release: '12.2.Rel1' - name: Tweak GCC path run: | From d578725a6197d778b2a16825e7fa5aa4421164cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 16 Feb 2023 09:25:14 +0000 Subject: [PATCH 352/572] Update community target sub-module @7bdacb2 --- targets-community | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets-community b/targets-community index 9822c83b3f..7bdacb274b 160000 --- a/targets-community +++ b/targets-community @@ -1 +1 @@ -Subproject commit 9822c83b3f898404f76f73119f4737ddb5903841 +Subproject commit 7bdacb274bcf8f77157694fd1a66f04d45c8db98 From 676fdcf231c57aa5ee05e37cdeb8e30309853b44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 23 Feb 2023 10:33:18 +0000 Subject: [PATCH 353/572] Fix build for 1-Wire UART - Build failing after migration to Gecko SKD 4.2.1. --- .../_common/autogen/sl_iostream_init_usart_instances.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 940c09537f..71e5e99c18 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -152,6 +152,7 @@ sl_status_t sl_iostream_usart_init_vcom(void) #if HAL_USE_ONEWIRE == TRUE sl_status_t sl_iostream_usart_init_onewire(void); +static sl_iostream_uart_t sl_iostream_onewire; sl_iostream_t *sl_iostream_onewire_handle = &sl_iostream_onewire.stream; sl_iostream_uart_t *sl_iostream_uart_onewire_handle = &sl_iostream_onewire; static sl_iostream_usart_context_t context_onewire; @@ -239,8 +240,6 @@ sl_status_t sl_iostream_usart_init_onewire(void) void sl_iostream_usart_init_instances(void) { - sl_status_t status; - #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) // Enable power manager notifications sl_power_manager_subscribe_em_transition_event(&events_handle, &events_info); @@ -248,7 +247,7 @@ void sl_iostream_usart_init_instances(void) // Instantiate usart instance(s) #if HAL_WP_USE_SERIAL == TRUE - status = sl_iostream_usart_init_vcom(); + sl_status_t status = sl_iostream_usart_init_vcom(); EFM_ASSERT(status == SL_STATUS_OK); #endif } From b80ebd8c373d1807ac06ccadf04d673008d0047c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 23 Feb 2023 10:47:00 +0000 Subject: [PATCH 354/572] Work CI-CD - checkout pulling siubmodules. --- .github/workflows/build_skyworks_evb1.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 439d246dda..5e475f1540 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -12,6 +12,7 @@ jobs: with: fetch-depth: 0 ref: 'skyworks-evb' + submodules: true - uses: lukka/get-cmake@latest From fa0a53b43cb8c7cab18e8753fc0f773ee6dd44f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 23 Feb 2023 10:48:18 +0000 Subject: [PATCH 355/572] Work CI-CD - Checkout submodules. --- .github/workflows/build_skyworks_evb1.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 439d246dda..5e475f1540 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -12,6 +12,7 @@ jobs: with: fetch-depth: 0 ref: 'skyworks-evb' + submodules: true - uses: lukka/get-cmake@latest From b8e46c349ae2148f6df248e35d1c478064734319 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 23 Feb 2023 10:51:10 +0000 Subject: [PATCH 356/572] Fix path to community targets sub-module ***NO_CI*** --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 1682bdc6c1..4d08649586 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "targets-community"] path = targets-community - url = ../nf-Community-Targets.git + url = https://github.com/nanoframework/nf-Community-Targets.git From 927289996248c7514f144f7b9ab6e73294e6d628 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 23 Feb 2023 12:41:49 +0000 Subject: [PATCH 357/572] Fix address for bin package --- targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt index a240dd3202..bab63d4097 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt @@ -69,7 +69,7 @@ if(SRECORD_TOOL_AVAILABLE) nf_generate_bin_package( ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 13000 + C000 ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) endif() From a508178eea4da017ca0bc507aa474281a0f11cd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 23 Feb 2023 13:18:28 +0000 Subject: [PATCH 358/572] Work CI-CD - Add install for srecord in github action for build. --- .github/workflows/build_skyworks_evb1.yml | 29 ++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 5e475f1540..f6b5fa9d4d 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -16,6 +16,33 @@ jobs: - uses: lukka/get-cmake@latest + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: @@ -52,7 +79,7 @@ jobs: - uses: lukka/run-cmake@v10 with: configurePreset: 'SKY_EEVB_PROTO1' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel']" + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" buildPreset: 'SKY_EEVB_PROTO1' buildPresetAdditionalArgs: "['--config MinSizeRel']" From 85424917cd9821f6d4cffe830f724e6c838dfc48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 31 Mar 2023 00:59:27 +0100 Subject: [PATCH 359/572] Update Gecko SDK to 4.2.2 --- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index f1079f3b35..6fc0b90563 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -70,7 +70,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.2.1") + set(GECKO_SDK_VERSION "v4.2.2") endif() if(NO_GECKO_SDK_SOURCE) From a39a5de18b5d101cdd7feda2522ebc0f28f4aa8e Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 2 Apr 2023 12:35:51 -0500 Subject: [PATCH 360/572] Add System.Device.UsbStream to our board target --- .../AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json index 972e4f151a..6d6568658f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json @@ -50,7 +50,8 @@ "API_System.Device.Spi": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON" + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON" } } ], From 35ea0c0e3ec248c8ca1af20914b22f0afbf5e5b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 3 Apr 2023 14:57:05 +0100 Subject: [PATCH 361/572] Work CI-CD - Add back comment for debugger help code. ***NO_CI*** --- .../FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake index b3999bac6c..0e876fb4c3 100644 --- a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.I2c.cmake @@ -39,9 +39,9 @@ foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRCS}) CMAKE_FIND_ROOT_PATH_BOTH ) - #if (BUILD_VERBOSE) + if (BUILD_VERBOSE) message("${SRC_FILE} >> ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE}") - #endif() + endif() list(APPEND Com.SkyworksInc.NanoFramework.Devices.I2c_SOURCES ${Com.SkyworksInc.NanoFramework.Devices.I2c_SRC_FILE}) From 9281b03427fdaa57b5c6d5cd6fe8ebcc747f833f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 3 Apr 2023 15:24:47 +0100 Subject: [PATCH 362/572] Work CI-CD - Add create tag on build. ***NO_CI*** --- .github/workflows/build_skyworks_evb1.yml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index f6b5fa9d4d..c816fd19fe 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -89,3 +89,15 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex + + - name: Tag the build + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) \ No newline at end of file From 6fe8232eb1d027d69780bd924522a4d04aca8602 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 3 Apr 2023 15:01:20 +0100 Subject: [PATCH 363/572] Work CI-CD - Replace github action with instructiosn to run from other branche. --- .github/workflows/build_skyworks_evb1.yml | 58 +++-------------------- 1 file changed, 7 insertions(+), 51 deletions(-) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 5e475f1540..90745328bd 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -8,57 +8,13 @@ jobs: runs-on: windows-latest steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - uses: lukka/get-cmake@latest - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config + - name: PLEASE RUN FROM TARGET BRANCH run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: 'SKY_EEVB_PROTO1' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel']" - buildPreset: 'SKY_EEVB_PROTO1' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - uses: actions/upload-artifact@v3 - with: - name: 'SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex + "*****************************************************************" | Write-Host -ForegroundColor White + " ⚠️ Please run the action from the 'skyworks-evb' branch ⚠️ " | Write-Host -ForegroundColor White + "*****************************************************************" | Write-Host -ForegroundColor White + "" | Write-Host -ForegroundColor White -NoNewline + "You can do this by selecting the branch name in the drop-down " | Write-Host -ForegroundColor White + "that shows in the GitHub action runner under 'Use workflow from' " | Write-Host -ForegroundColor White From d3f7fee538264d2a1747fb50f38ae96dc7e120e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 3 Apr 2023 15:59:14 +0100 Subject: [PATCH 364/572] Increase CLR block storage size to fit build with USB stream feature --- .../SKY_EEVB_PROTO1/common/Device_BlockStorage.c | 6 +++--- .../SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c index fffa338a97..5af685ff82 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c @@ -13,10 +13,10 @@ const BlockRange BlockRange1[] = { {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 64}, + {BlockRange_BLOCKTYPE_CODE, 12, 65}, - // 00041000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 65, 510}, + // 00042000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 66, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld index 713b624d56..3ce42ce5c5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1784k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00041000, len = 1784k /* space reserved for application deployment */ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1780k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00042000, len = 1780k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 6fee9265e779145b75aae6b2449d898909efe739 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 3 Apr 2023 16:25:05 +0100 Subject: [PATCH 365/572] Change tag format - As requested. --- .github/workflows/build_skyworks_evb1.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index c816fd19fe..4bf41ffb3d 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file From a20ed5899d779e7b7fb8fd0dc47d3eb520ba0c41 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 3 Apr 2023 10:55:46 -0500 Subject: [PATCH 366/572] Rename Skyworks target folder; add additional build for standard SIF APIs to facilitate testing with old STM32 code --- .../CMakeLists.txt | 0 .../CMakePresets.json | 25 +++++++++++++++++-- .../{SKY_EEVB_PROTO1 => SKY_EVBs}/README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../{SKY_EEVB_PROTO1 => SKY_EVBs}/bspconfig.h | 0 .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../config/uartdrv_config.h | 0 .../{SKY_EEVB_PROTO1 => SKY_EVBs}/launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../nanoCLR/main.c | 0 .../nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../nanoCLR/usb_hid_app.c | 0 .../target_BlockStorage.c | 0 .../target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../target_common.c | 0 .../target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../target_stdio_config.c | 0 .../target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../target_tx_user.h | 0 .../target_ux_user.h | 0 69 files changed, 23 insertions(+), 2 deletions(-) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/CMakePresets.json (74%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EEVB_PROTO1 => SKY_EVBs}/target_ux_user.h (100%) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakePresets.json similarity index 74% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakePresets.json index 6d6568658f..993ce657e1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "SKY_EEVB_PROTO1", + "name": "SKY_EEVB", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -16,7 +16,7 @@ "hidden": false, "cacheVariables": { "TARGET_BOARD": "${presetName}", - "TARGET_NAME": "SKY_EEVB_PROTO1", + "TARGET_NAME": "SKY_EEVB", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", @@ -53,6 +53,21 @@ "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON" } + }, + { + "name": "SKY_EEVB_STD_SIF", + "inherits": [ + "SKY_EEVB" + ], + "cacheVariables": { + "TARGET_BOARD": "${presetName}", + "TARGET_NAME": "SKY_EEVB_STD_SIF", + "API_System.Device.Spi": "ON", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", + "API_System.Device.I2c": "ON", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "OFF", + "API_System.Device.UsbStream": "ON" + } } ], "buildPresets": [ @@ -61,6 +76,12 @@ "name": "SKY_EEVB_PROTO1", "displayName": "SKY_EEVB_PROTO1", "configurePreset": "SKY_EEVB_PROTO1" + }, + { + "inherits": "base-user", + "name": "SKY_EEVB_STD_SIF", + "displayName": "SKY_EEVB_STD_SIF", + "configurePreset": "SKY_EEVB_STD_SIF" } ] } diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/README.md rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/launch.json rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EEVB_PROTO1/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_ux_user.h From 4017c9a5579e71af9eab608fd0b429f4c9ead1df Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 3 Apr 2023 11:12:23 -0500 Subject: [PATCH 367/572] More Skyworks target folder/name changes + first attempt at Github action update --- .github/workflows/build_skyworks_evb1.yml | 19 +++++++++++++------ targets/AzureRTOS/CMakePresets.json | 2 +- .../{SKY_EVBs => SKY_EVB}/CMakeLists.txt | 0 .../{SKY_EVBs => SKY_EVB}/CMakePresets.json | 6 +++--- .../{SKY_EVBs => SKY_EVB}/README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../{SKY_EVBs => SKY_EVB}/bspconfig.h | 0 .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../{SKY_EVBs => SKY_EVB}/config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../config/uartdrv_config.h | 0 .../{SKY_EVBs => SKY_EVB}/launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../{SKY_EVBs => SKY_EVB}/nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../{SKY_EVBs => SKY_EVB}/nanoCLR/main.c | 0 .../{SKY_EVBs => SKY_EVB}/nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../nanoCLR/usb_hid_app.c | 0 .../target_BlockStorage.c | 0 .../target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../{SKY_EVBs => SKY_EVB}/target_common.c | 0 .../{SKY_EVBs => SKY_EVB}/target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../target_stdio_config.c | 0 .../target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../{SKY_EVBs => SKY_EVB}/target_tx_user.h | 0 .../{SKY_EVBs => SKY_EVB}/target_ux_user.h | 0 71 files changed, 17 insertions(+), 10 deletions(-) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/CMakePresets.json (95%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVBs => SKY_EVB}/target_ux_user.h (100%) diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/build_skyworks_evb1.yml index 4bf41ffb3d..c85d2946a7 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/build_skyworks_evb1.yml @@ -1,10 +1,10 @@ -name: Build SKY_EEVB_PROTO1 +name: Build SKY_EVB on: workflow_dispatch jobs: - build_SKY_EEVB_PROTO1: + build_SKY_EVBs: runs-on: windows-latest steps: @@ -78,14 +78,21 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: 'SKY_EEVB_PROTO1' + configurePreset: 'SKY_EEVB' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: 'SKY_EEVB_PROTO1' + buildPreset: 'SKY_EEVB' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: lukka/run-cmake@v10 + with: + configurePreset: 'SKY_EEVB_STD_SIF' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: 'SKY_EEVB_STD_SIF' buildPresetAdditionalArgs: "['--config MinSizeRel']" - uses: actions/upload-artifact@v3 with: - name: 'SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: 'SKY_EVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex @@ -98,6 +105,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EEVB_PROTO1-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 85498ea2f8..d75cdb673b 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -2,7 +2,7 @@ "version": 4, "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", - "SiliconLabs/SKY_EEVB_PROTO1/CMakePresets.json", + "SiliconLabs/SKY_EVB/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json similarity index 95% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index 993ce657e1..c31c8e318b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -73,9 +73,9 @@ "buildPresets": [ { "inherits": "base-user", - "name": "SKY_EEVB_PROTO1", - "displayName": "SKY_EEVB_PROTO1", - "configurePreset": "SKY_EEVB_PROTO1" + "name": "SKY_EEVB", + "displayName": "SKY_EEVB", + "configurePreset": "SKY_EEVB" }, { "inherits": "base-user", diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/README.md rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/launch.json rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVBs/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_EVB/target_ux_user.h From 0b41ab7bfa8469993512b052d5c6915dcd47e027 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 3 Apr 2023 15:25:58 -0500 Subject: [PATCH 368/572] Create script to create Github build YAML files --- ..._skyworks_evb1.yml => Build_SKY_EEVB.yaml} | 13 +-- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 103 ++++++++++++++++++ .github/workflows/Makefile | 2 + .github/workflows/SKY-TARGETS.txt | 2 + .../workflows/build_skyworks_evb.yml.template | 103 ++++++++++++++++++ .github/workflows/make-sky-yamls.pl | 15 +++ 6 files changed, 228 insertions(+), 10 deletions(-) rename .github/workflows/{build_skyworks_evb1.yml => Build_SKY_EEVB.yaml} (84%) create mode 100644 .github/workflows/Build_SKY_EEVB_STD_SIF.yaml create mode 100644 .github/workflows/Makefile create mode 100644 .github/workflows/SKY-TARGETS.txt create mode 100644 .github/workflows/build_skyworks_evb.yml.template create mode 100644 .github/workflows/make-sky-yamls.pl diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/Build_SKY_EEVB.yaml similarity index 84% rename from .github/workflows/build_skyworks_evb1.yml rename to .github/workflows/Build_SKY_EEVB.yaml index c85d2946a7..8689b82b0f 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/Build_SKY_EEVB.yaml @@ -1,10 +1,10 @@ -name: Build SKY_EVB +name: Build SKY_EEVB on: workflow_dispatch jobs: - build_SKY_EVBs: + build_SKY_EEVB: runs-on: windows-latest steps: @@ -83,16 +83,9 @@ jobs: buildPreset: 'SKY_EEVB' buildPresetAdditionalArgs: "['--config MinSizeRel']" - - uses: lukka/run-cmake@v10 - with: - configurePreset: 'SKY_EEVB_STD_SIF' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: 'SKY_EEVB_STD_SIF' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - uses: actions/upload-artifact@v3 with: - name: 'SKY_EVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: 'SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml new file mode 100644 index 0000000000..869b7fa8f6 --- /dev/null +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -0,0 +1,103 @@ +name: Build SKY_EEVB_STD_SIF + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF: + runs-on: windows-latest + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: 'SKY_EEVB_STD_SIF' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: 'SKY_EEVB_STD_SIF' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v3 + with: + name: 'SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + + - name: Tag the build + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) \ No newline at end of file diff --git a/.github/workflows/Makefile b/.github/workflows/Makefile new file mode 100644 index 0000000000..7ba347485f --- /dev/null +++ b/.github/workflows/Makefile @@ -0,0 +1,2 @@ +all: + perl make-sky-yamls.pl \ No newline at end of file diff --git a/.github/workflows/SKY-TARGETS.txt b/.github/workflows/SKY-TARGETS.txt new file mode 100644 index 0000000000..12da030541 --- /dev/null +++ b/.github/workflows/SKY-TARGETS.txt @@ -0,0 +1,2 @@ +SKY_EEVB +SKY_EEVB_STD_SIF \ No newline at end of file diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template new file mode 100644 index 0000000000..6ea51b8a37 --- /dev/null +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -0,0 +1,103 @@ +name: Build @TARGET@ + +on: + workflow_dispatch + +jobs: + build_@TARGET@: + runs-on: windows-latest + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '@TARGET@' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '@TARGET@' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v3 + with: + name: '@TARGET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + + - name: Tag the build + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/@TARGET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) \ No newline at end of file diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/make-sky-yamls.pl new file mode 100644 index 0000000000..74739780a2 --- /dev/null +++ b/.github/workflows/make-sky-yamls.pl @@ -0,0 +1,15 @@ +#!/usr/bin/perl + +use strict; +use File::Slurp; + +my $targets_buff = read_file("SKY-TARGETS.txt"); +my @targets = split /\r\n|\n|\r/, $targets_buff; + +foreach my $target (@targets) +{ + print("$target ...\n"); + my $yaml = read_file("build_skyworks_evb.yml.template"); + $yaml =~ s/\@TARGET\@/$target/g; + write_file("Build_$target.yaml", $yaml); +} From 8131035e9d1ac103d094b88e7bb5c1d9aacd28ff Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 3 Apr 2023 16:56:01 -0500 Subject: [PATCH 369/572] Update Github YAML script to create placeholder main branch versions --- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 12 +++++------ .github/workflows/Makefile | 10 ++++++++-- .../build_skyworks_evb.main.yml.template | 20 +++++++++++++++++++ .github/workflows/make-sky-yamls.pl | 12 ++++++++++- 4 files changed, 45 insertions(+), 9 deletions(-) create mode 100644 .github/workflows/build_skyworks_evb.main.yml.template diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml index 869b7fa8f6..8689b82b0f 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -1,10 +1,10 @@ -name: Build SKY_EEVB_STD_SIF +name: Build SKY_EEVB on: workflow_dispatch jobs: - build_SKY_EEVB_STD_SIF: + build_SKY_EEVB: runs-on: windows-latest steps: @@ -78,14 +78,14 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: 'SKY_EEVB_STD_SIF' + configurePreset: 'SKY_EEVB' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: 'SKY_EEVB_STD_SIF' + buildPreset: 'SKY_EEVB' buildPresetAdditionalArgs: "['--config MinSizeRel']" - uses: actions/upload-artifact@v3 with: - name: 'SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: 'SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/.github/workflows/Makefile b/.github/workflows/Makefile index 7ba347485f..35a3b44c0d 100644 --- a/.github/workflows/Makefile +++ b/.github/workflows/Makefile @@ -1,2 +1,8 @@ -all: - perl make-sky-yamls.pl \ No newline at end of file +usage: + @echo "Use make branch or make main" + +branch: + perl make-sky-yamls.pl --branch + +main: + perl make-sky-yamls.pl --main diff --git a/.github/workflows/build_skyworks_evb.main.yml.template b/.github/workflows/build_skyworks_evb.main.yml.template new file mode 100644 index 0000000000..9d9dff4210 --- /dev/null +++ b/.github/workflows/build_skyworks_evb.main.yml.template @@ -0,0 +1,20 @@ +name: Build @TARGET@ + +on: + workflow_dispatch + +jobs: + build_@TARGET@: + runs-on: windows-latest + + steps: + + - name: PLEASE RUN FROM TARGET BRANCH + run: | + + "*****************************************************************" | Write-Host -ForegroundColor White + " ⚠️ Please run the action from the 'skyworks-evb' branch ⚠️ " | Write-Host -ForegroundColor White + "*****************************************************************" | Write-Host -ForegroundColor White + "" | Write-Host -ForegroundColor White -NoNewline + "You can do this by selecting the branch name in the drop-down " | Write-Host -ForegroundColor White + "that shows in the GitHub action runner under 'Use workflow from' " | Write-Host -ForegroundColor White diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/make-sky-yamls.pl index 74739780a2..af5c864666 100644 --- a/.github/workflows/make-sky-yamls.pl +++ b/.github/workflows/make-sky-yamls.pl @@ -3,13 +3,23 @@ use strict; use File::Slurp; +my $opt = shift; + +my $yaml; +if ($opt eq "--main") { + $yaml = read_file("build_skyworks_evb.main.yml.template"); +} elsif ($opt eq "--branch") { + $yaml = read_file("build_skyworks_evb.yml.template"); +} else { + die "bad usage\n"; +} + my $targets_buff = read_file("SKY-TARGETS.txt"); my @targets = split /\r\n|\n|\r/, $targets_buff; foreach my $target (@targets) { print("$target ...\n"); - my $yaml = read_file("build_skyworks_evb.yml.template"); $yaml =~ s/\@TARGET\@/$target/g; write_file("Build_$target.yaml", $yaml); } From 1b2c2244dbbe6448cfa2a16a4fc6fb03761de0c4 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 3 Apr 2023 17:08:23 -0500 Subject: [PATCH 370/572] Update main branch actions YAML --- ..._skyworks_evb1.yml => Build_SKY_EEVB.yaml} | 4 +- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 20 ++++ .github/workflows/Makefile | 8 ++ .github/workflows/SKY-TARGETS.txt | 2 + .../build_skyworks_evb.main.yml.template | 20 ++++ .../workflows/build_skyworks_evb.yml.template | 103 ++++++++++++++++++ .github/workflows/make-sky-yamls.pl | 25 +++++ 7 files changed, 180 insertions(+), 2 deletions(-) rename .github/workflows/{build_skyworks_evb1.yml => Build_SKY_EEVB.yaml} (93%) create mode 100644 .github/workflows/Build_SKY_EEVB_STD_SIF.yaml create mode 100644 .github/workflows/Makefile create mode 100644 .github/workflows/SKY-TARGETS.txt create mode 100644 .github/workflows/build_skyworks_evb.main.yml.template create mode 100644 .github/workflows/build_skyworks_evb.yml.template create mode 100644 .github/workflows/make-sky-yamls.pl diff --git a/.github/workflows/build_skyworks_evb1.yml b/.github/workflows/Build_SKY_EEVB.yaml similarity index 93% rename from .github/workflows/build_skyworks_evb1.yml rename to .github/workflows/Build_SKY_EEVB.yaml index 90745328bd..5b52b129a2 100644 --- a/.github/workflows/build_skyworks_evb1.yml +++ b/.github/workflows/Build_SKY_EEVB.yaml @@ -1,10 +1,10 @@ -name: Build SKY_EEVB_PROTO1 +name: Build SKY_EEVB on: workflow_dispatch jobs: - build_SKY_EEVB_PROTO1: + build_SKY_EEVB: runs-on: windows-latest steps: diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml new file mode 100644 index 0000000000..5b52b129a2 --- /dev/null +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -0,0 +1,20 @@ +name: Build SKY_EEVB + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB: + runs-on: windows-latest + + steps: + + - name: PLEASE RUN FROM TARGET BRANCH + run: | + + "*****************************************************************" | Write-Host -ForegroundColor White + " ⚠️ Please run the action from the 'skyworks-evb' branch ⚠️ " | Write-Host -ForegroundColor White + "*****************************************************************" | Write-Host -ForegroundColor White + "" | Write-Host -ForegroundColor White -NoNewline + "You can do this by selecting the branch name in the drop-down " | Write-Host -ForegroundColor White + "that shows in the GitHub action runner under 'Use workflow from' " | Write-Host -ForegroundColor White diff --git a/.github/workflows/Makefile b/.github/workflows/Makefile new file mode 100644 index 0000000000..35a3b44c0d --- /dev/null +++ b/.github/workflows/Makefile @@ -0,0 +1,8 @@ +usage: + @echo "Use make branch or make main" + +branch: + perl make-sky-yamls.pl --branch + +main: + perl make-sky-yamls.pl --main diff --git a/.github/workflows/SKY-TARGETS.txt b/.github/workflows/SKY-TARGETS.txt new file mode 100644 index 0000000000..12da030541 --- /dev/null +++ b/.github/workflows/SKY-TARGETS.txt @@ -0,0 +1,2 @@ +SKY_EEVB +SKY_EEVB_STD_SIF \ No newline at end of file diff --git a/.github/workflows/build_skyworks_evb.main.yml.template b/.github/workflows/build_skyworks_evb.main.yml.template new file mode 100644 index 0000000000..9d9dff4210 --- /dev/null +++ b/.github/workflows/build_skyworks_evb.main.yml.template @@ -0,0 +1,20 @@ +name: Build @TARGET@ + +on: + workflow_dispatch + +jobs: + build_@TARGET@: + runs-on: windows-latest + + steps: + + - name: PLEASE RUN FROM TARGET BRANCH + run: | + + "*****************************************************************" | Write-Host -ForegroundColor White + " ⚠️ Please run the action from the 'skyworks-evb' branch ⚠️ " | Write-Host -ForegroundColor White + "*****************************************************************" | Write-Host -ForegroundColor White + "" | Write-Host -ForegroundColor White -NoNewline + "You can do this by selecting the branch name in the drop-down " | Write-Host -ForegroundColor White + "that shows in the GitHub action runner under 'Use workflow from' " | Write-Host -ForegroundColor White diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template new file mode 100644 index 0000000000..6ea51b8a37 --- /dev/null +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -0,0 +1,103 @@ +name: Build @TARGET@ + +on: + workflow_dispatch + +jobs: + build_@TARGET@: + runs-on: windows-latest + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '@TARGET@' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '@TARGET@' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v3 + with: + name: '@TARGET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + + - name: Tag the build + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/@TARGET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) \ No newline at end of file diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/make-sky-yamls.pl new file mode 100644 index 0000000000..af5c864666 --- /dev/null +++ b/.github/workflows/make-sky-yamls.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl + +use strict; +use File::Slurp; + +my $opt = shift; + +my $yaml; +if ($opt eq "--main") { + $yaml = read_file("build_skyworks_evb.main.yml.template"); +} elsif ($opt eq "--branch") { + $yaml = read_file("build_skyworks_evb.yml.template"); +} else { + die "bad usage\n"; +} + +my $targets_buff = read_file("SKY-TARGETS.txt"); +my @targets = split /\r\n|\n|\r/, $targets_buff; + +foreach my $target (@targets) +{ + print("$target ...\n"); + $yaml =~ s/\@TARGET\@/$target/g; + write_file("Build_$target.yaml", $yaml); +} From f7050a7f1fa0bc71cae02a66ca4f37a61f3f9864 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 3 Apr 2023 17:12:41 -0500 Subject: [PATCH 371/572] Fix YAML script --- .github/workflows/Build_SKY_EEVB.yaml | 2 +- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 4 ++-- .github/workflows/build_skyworks_evb.main.yml.template | 2 +- .github/workflows/make-sky-yamls.pl | 7 ++++--- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB.yaml b/.github/workflows/Build_SKY_EEVB.yaml index 5b52b129a2..b50adbf61d 100644 --- a/.github/workflows/Build_SKY_EEVB.yaml +++ b/.github/workflows/Build_SKY_EEVB.yaml @@ -1,4 +1,4 @@ -name: Build SKY_EEVB +name: Build SKY_EEVB on: workflow_dispatch diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml index 5b52b129a2..613fd00069 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -1,10 +1,10 @@ -name: Build SKY_EEVB +name: Build SKY_EEVB_STD_SIF on: workflow_dispatch jobs: - build_SKY_EEVB: + build_SKY_EEVB_STD_SIF: runs-on: windows-latest steps: diff --git a/.github/workflows/build_skyworks_evb.main.yml.template b/.github/workflows/build_skyworks_evb.main.yml.template index 9d9dff4210..a4d6856785 100644 --- a/.github/workflows/build_skyworks_evb.main.yml.template +++ b/.github/workflows/build_skyworks_evb.main.yml.template @@ -1,4 +1,4 @@ -name: Build @TARGET@ +name: Build @TARGET@ on: workflow_dispatch diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/make-sky-yamls.pl index af5c864666..4fa5dae1af 100644 --- a/.github/workflows/make-sky-yamls.pl +++ b/.github/workflows/make-sky-yamls.pl @@ -5,11 +5,11 @@ my $opt = shift; -my $yaml; +my $yaml_file; if ($opt eq "--main") { - $yaml = read_file("build_skyworks_evb.main.yml.template"); + $yaml_file = "build_skyworks_evb.main.yml.template"; } elsif ($opt eq "--branch") { - $yaml = read_file("build_skyworks_evb.yml.template"); + $yaml_file = "build_skyworks_evb.yml.template"; } else { die "bad usage\n"; } @@ -20,6 +20,7 @@ foreach my $target (@targets) { print("$target ...\n"); + my $yaml = read_file($yaml_file); $yaml =~ s/\@TARGET\@/$target/g; write_file("Build_$target.yaml", $yaml); } From 5c4f50e7ea4c87a5c7795e09db0db5493da694ce Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 06:38:19 -0500 Subject: [PATCH 372/572] Remove unused file --- CMakeUserPresets.SKY_EEVB_PROTO1.json | 38 --------------------------- 1 file changed, 38 deletions(-) delete mode 100644 CMakeUserPresets.SKY_EEVB_PROTO1.json diff --git a/CMakeUserPresets.SKY_EEVB_PROTO1.json b/CMakeUserPresets.SKY_EEVB_PROTO1.json deleted file mode 100644 index 2c977bf4ae..0000000000 --- a/CMakeUserPresets.SKY_EEVB_PROTO1.json +++ /dev/null @@ -1,38 +0,0 @@ -{ - "version": 3, - "configurePresets": [ - { - "name": "SKY_EEVB_PROTO1", - "inherits": [ - "SL_STK3701A_preset" - ], - "cacheVariables": { - "TARGET_BOARD": { - "type": "STRING", - "value": "${presetName}" - }, - "TARGET_SERIAL_BAUDRATE": "921600", - "GECKO_FEATURE_USBD_HID": "OFF", - "GECKO_FEATURE_USBD_WINUSB": "OFF", - "HAL_WP_USE_SERIAL": "OFF", - "HAL_WP_USE_USB_CDC": "ON", - "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", - "API_nanoFramework.GiantGecko.Adc": "ON", - "API_nanoFramework.Device.OneWire": "ON", - "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", - "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "NF_INTEROP_ASSEMBLIES": null - } - } - ], - "buildPresets": [ - { - "name": "SKY_EEVB_PROTO1", - "displayName": "SKY_EEVB_PROTO1", - "configurePreset": "SKY_EEVB_PROTO1" - } - ] -} \ No newline at end of file From 84510aa8a1011e53df7f37ec2583c6893797134a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 07:22:32 -0500 Subject: [PATCH 373/572] Update build YAML to support different target and preset names --- .github/workflows/Build_SKY_EEVB.yaml | 4 ++-- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 4 ++-- .github/workflows/SKY-BUILDS.txt | 4 ++++ .github/workflows/SKY-TARGETS.txt | 2 -- .../build_skyworks_evb.main.yml.template | 4 ++-- .../workflows/build_skyworks_evb.yml.template | 8 +++---- .github/workflows/make-sky-yamls.pl | 22 ++++++++++++++----- 7 files changed, 31 insertions(+), 17 deletions(-) create mode 100644 .github/workflows/SKY-BUILDS.txt delete mode 100644 .github/workflows/SKY-TARGETS.txt diff --git a/.github/workflows/Build_SKY_EEVB.yaml b/.github/workflows/Build_SKY_EEVB.yaml index 8689b82b0f..4ec8a0b34a 100644 --- a/.github/workflows/Build_SKY_EEVB.yaml +++ b/.github/workflows/Build_SKY_EEVB.yaml @@ -78,7 +78,7 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: 'SKY_EEVB' + configurePreset: 'SKY_EVB' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" buildPreset: 'SKY_EEVB' buildPresetAdditionalArgs: "['--config MinSizeRel']" @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml index 869b7fa8f6..42a7714088 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -78,7 +78,7 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: 'SKY_EEVB_STD_SIF' + configurePreset: 'SKY_EVB' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" buildPreset: 'SKY_EEVB_STD_SIF' buildPresetAdditionalArgs: "['--config MinSizeRel']" @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/.github/workflows/SKY-BUILDS.txt b/.github/workflows/SKY-BUILDS.txt new file mode 100644 index 0000000000..3320148d76 --- /dev/null +++ b/.github/workflows/SKY-BUILDS.txt @@ -0,0 +1,4 @@ +# Format is: +# Target,Preset +SKY_EVB,SKY_EEVB +SKY_EVB,SKY_EEVB_STD_SIF \ No newline at end of file diff --git a/.github/workflows/SKY-TARGETS.txt b/.github/workflows/SKY-TARGETS.txt deleted file mode 100644 index 12da030541..0000000000 --- a/.github/workflows/SKY-TARGETS.txt +++ /dev/null @@ -1,2 +0,0 @@ -SKY_EEVB -SKY_EEVB_STD_SIF \ No newline at end of file diff --git a/.github/workflows/build_skyworks_evb.main.yml.template b/.github/workflows/build_skyworks_evb.main.yml.template index a4d6856785..929cad03b6 100644 --- a/.github/workflows/build_skyworks_evb.main.yml.template +++ b/.github/workflows/build_skyworks_evb.main.yml.template @@ -1,10 +1,10 @@ -name: Build @TARGET@ +name: Build @PRESET@ on: workflow_dispatch jobs: - build_@TARGET@: + build_@PRESET@: runs-on: windows-latest steps: diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index 6ea51b8a37..c3e7e09499 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -1,10 +1,10 @@ -name: Build @TARGET@ +name: Build @PRESET@ on: workflow_dispatch jobs: - build_@TARGET@: + build_@PRESET@: runs-on: windows-latest steps: @@ -80,12 +80,12 @@ jobs: with: configurePreset: '@TARGET@' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '@TARGET@' + buildPreset: '@PRESET@' buildPresetAdditionalArgs: "['--config MinSizeRel']" - uses: actions/upload-artifact@v3 with: - name: '@TARGET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: '@PRESET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/make-sky-yamls.pl index 4fa5dae1af..aa680ba91f 100644 --- a/.github/workflows/make-sky-yamls.pl +++ b/.github/workflows/make-sky-yamls.pl @@ -14,13 +14,25 @@ die "bad usage\n"; } -my $targets_buff = read_file("SKY-TARGETS.txt"); -my @targets = split /\r\n|\n|\r/, $targets_buff; +my %presets_found; -foreach my $target (@targets) +my $builds_file = "SKY-BUILDS.txt"; +my $buff = read_file($builds_file); +my @lines = split /\r\n|\n|\r/, $buff; + +foreach my $line (@lines) { - print("$target ...\n"); + # warn $line; + next if ($line =~ /^#/); + my($target,$preset) = split(/,/,$line); + + # Don't allow a preset name to be used more than once + die "preset $preset is used more than one in $builds_file\n" if ($presets_found{$preset}); + $presets_found{$preset} = 1; + + print("$target/$preset ...\n"); my $yaml = read_file($yaml_file); $yaml =~ s/\@TARGET\@/$target/g; - write_file("Build_$target.yaml", $yaml); + $yaml =~ s/\@PRESET\@/$preset/g; + write_file("Build_$preset.yaml", $yaml); } From 81c10ac57e5ed6f1e687a7e31a44f4488747552d Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 07:43:07 -0500 Subject: [PATCH 374/572] Update build YAML maker, output --- .github/workflows/Build_SKY_EEVB.yaml | 2 +- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 2 +- .github/workflows/build_skyworks_evb.yml.template | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB.yaml b/.github/workflows/Build_SKY_EEVB.yaml index 4ec8a0b34a..073bbacdf3 100644 --- a/.github/workflows/Build_SKY_EEVB.yaml +++ b/.github/workflows/Build_SKY_EEVB.yaml @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml index 42a7714088..d54e441624 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index c3e7e09499..9fa09a184e 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -98,6 +98,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/@TARGET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/@PRESET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file From bccd9fda4abfc8dda19deb7600294438cf7ab7a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 4 Apr 2023 17:44:18 +0100 Subject: [PATCH 375/572] Fix target board in cmake presets - Need to specify target name instead of referring to preset name as it's different. --- targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index c31c8e318b..ce11ac948a 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -15,7 +15,7 @@ ], "hidden": false, "cacheVariables": { - "TARGET_BOARD": "${presetName}", + "TARGET_BOARD": "SKY_EVB", "TARGET_NAME": "SKY_EEVB", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", @@ -60,7 +60,7 @@ "SKY_EEVB" ], "cacheVariables": { - "TARGET_BOARD": "${presetName}", + "TARGET_BOARD": "SKY_EVB", "TARGET_NAME": "SKY_EEVB_STD_SIF", "API_System.Device.Spi": "ON", "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", From d44fb42f1c2d7ffe2ad7eaa5c1886b38e39a5c40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 4 Apr 2023 17:44:55 +0100 Subject: [PATCH 376/572] Fix build github action to use env var to specify cmake preset to build --- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml index d54e441624..e1f03638c8 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -6,6 +6,9 @@ on: jobs: build_SKY_EEVB_STD_SIF: runs-on: windows-latest + + env: + TARGET_NAME: 'SKY_EEVB_STD_SIF' steps: - uses: actions/checkout@v3 @@ -78,14 +81,14 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: 'SKY_EVB' + configurePreset: '${{ env.TARGET_NAME }}' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: 'SKY_EEVB_STD_SIF' + buildPreset: '${{ env.TARGET_NAME }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" - uses: actions/upload-artifact@v3 with: - name: 'SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: ${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex @@ -98,6 +101,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EEVB_STD_SIF-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file From 67b6b7e2c725e6cbae5c60e75841a4661149745a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 13:04:39 -0500 Subject: [PATCH 377/572] Updated github action template based on Jose's tweak to to use env var to specify cmake preset to build; recreate both presets --- .github/workflows/Build_SKY_EEVB.yaml | 11 +++++++---- .github/workflows/Build_SKY_EEVB_STD_SIF.yaml | 2 +- .github/workflows/build_skyworks_evb.yml.template | 11 +++++++---- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB.yaml b/.github/workflows/Build_SKY_EEVB.yaml index 073bbacdf3..86948ae883 100644 --- a/.github/workflows/Build_SKY_EEVB.yaml +++ b/.github/workflows/Build_SKY_EEVB.yaml @@ -7,6 +7,9 @@ jobs: build_SKY_EEVB: runs-on: windows-latest + env: + TARGET_NAME: 'SKY_EEVB' + steps: - uses: actions/checkout@v3 with: @@ -78,14 +81,14 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: 'SKY_EVB' + configurePreset: '${{ env.TARGET_NAME }}' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: 'SKY_EEVB' + buildPreset: '${{ env.TARGET_NAME }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" - uses: actions/upload-artifact@v3 with: - name: 'SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: ${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex @@ -98,6 +101,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/SKY_EEVB-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml index e1f03638c8..1ea485c37b 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml @@ -6,7 +6,7 @@ on: jobs: build_SKY_EEVB_STD_SIF: runs-on: windows-latest - + env: TARGET_NAME: 'SKY_EEVB_STD_SIF' diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index 9fa09a184e..e6e6860266 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -7,6 +7,9 @@ jobs: build_@PRESET@: runs-on: windows-latest + env: + TARGET_NAME: '@PRESET@' + steps: - uses: actions/checkout@v3 with: @@ -78,14 +81,14 @@ jobs: - uses: lukka/run-cmake@v10 with: - configurePreset: '@TARGET@' + configurePreset: '${{ env.TARGET_NAME }}' configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '@PRESET@' + buildPreset: '${{ env.TARGET_NAME }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" - uses: actions/upload-artifact@v3 with: - name: '@PRESET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: ${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex @@ -98,6 +101,6 @@ jobs: github.rest.git.createRef({ owner: context.repo.owner, repo: context.repo.repo, - ref: 'refs/tags/@PRESET@-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha }) \ No newline at end of file From f0ef327b64cc441b86c73b80db462518006cd407 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 14:45:39 -0500 Subject: [PATCH 378/572] Add standard I2C/SPI driver HAL files (I hope this is what is needed) --- .../target_system_device_i2c_config.cpp | 28 ++++++++++++++++ .../SKY_EVB/target_system_device_i2c_config.h | 4 +++ .../target_system_device_spi_config.cpp | 33 +++++++++++++++++++ .../SKY_EVB/target_system_device_spi_config.h | 7 ++++ 4 files changed, 72 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..38074baf86 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..7ca2ea0257 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp @@ -0,0 +1,33 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4, 4) + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h new file mode 100644 index 0000000000..409945557b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE From 3ea55b544a696400e20af623ef9f0d69e874feb8 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 19:42:39 -0500 Subject: [PATCH 379/572] Fix standard SPI driver HAL files (I hope) --- .../SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp index 7ca2ea0257..28ce292b35 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp @@ -16,7 +16,7 @@ // SPI1_CS: PD3, location 1 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(1, 1, 1, 1, 1) +INIT_SPI_CONFIG(1, 1, 1, 1) ////////// // SPI2 // @@ -29,5 +29,5 @@ INIT_SPI_CONFIG(1, 1, 1, 1, 1) // SPI2_CS: PF9, location 1 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(2, 4, 4, 4, 4) +INIT_SPI_CONFIG(2, 4, 4, 4) From 45829d64268a418bbde2add6afaec425940f7557 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Apr 2023 19:53:18 -0500 Subject: [PATCH 380/572] More standard I2C/SPI driver HAL file tweaks (I hope this is what is needed) --- .../SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h | 2 +- .../SiliconLabs/SL_STK3701A/target_system_device_spi_config.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h index 0e5a564e80..8945b4cb74 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_i2c_config.h @@ -4,4 +4,4 @@ // #define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C2 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h index 6dfccbd22e..409945557b 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_system_device_spi_config.h @@ -3,5 +3,5 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 TRUE #define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE From 1c8052115131ababb741bf6953dc222b9357310b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 5 Apr 2023 09:18:36 +0100 Subject: [PATCH 381/572] Fix SPI struct index --- targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp index 0a04aee8f8..19d74e68fb 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL.cpp @@ -122,7 +122,7 @@ void nanoHAL_Initialize() memset(&SPI1_PAL, 0, sizeof(NF_PAL_SPI)); #endif #if (GECKO_USE_SPI2 == TRUE) - memset(&SPI0_PAL, 0, sizeof(NF_PAL_SPI)); + memset(&SPI2_PAL, 0, sizeof(NF_PAL_SPI)); #endif #if (GECKO_USE_SPI3 == TRUE) memset(&SPI3_PAL, 0, sizeof(NF_PAL_SPI)); From 73c43fc716b19b8f1ef0d77f5a65e19d48d49eff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 2 May 2023 01:53:31 +0100 Subject: [PATCH 382/572] Update COM I2C skyworks declaration --- .../com_sky_nf_dev_i2c_native.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp index b67bab15d6..45dd0ee516 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.I2c/com_sky_nf_dev_i2c_native.cpp @@ -12,6 +12,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, Library_com_sky_nf_dev_i2c_native_Com_SkyworksInc_NanoFramework_Devices_I2c_I2cBus::NativeTransmit___VOID__I4__U1__SystemSpanByte__SystemSpanByte, NULL, NULL, @@ -27,7 +28,7 @@ const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramewo "Com.SkyworksInc.NanoFramework.Devices.I2c", 0x913E3D1E, method_lookup, - { 100, 0, 0, 1 } + { 100, 0, 0, 2 } }; // clang-format on From b4a175037860c27dd9364347bbea41a4b7dbf980 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 01:00:01 +0100 Subject: [PATCH 383/572] Improve documentation on WinUSB usage --- targets/AzureRTOS/SiliconLabs/README.md | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index 284b48f3dc..31caeacc3e 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -12,7 +12,7 @@ As an alternative it can be generated from the device unique ID. For this the de In order to add a WinUSB device configuration, the follow is required: -1. Set build option `GECKO_FEATURE_USBD_WINUSB` to `ON`. +1. Set build option `GECKO_FEATURE_USBD_WINUSB` to `ON`. As an alternative, if you plan to use the UsbStream # class, the latter is not required. Just set to `ON` the respective build option `API_System.Device.UsbStream`. 1. Add the following files to the target folder (mind the location) [sl_usbd_class_vendor_instances.c](SL_STK3701A/autogen/sl_usbd_class_vendor_instances.c) @@ -23,5 +23,10 @@ In order to add a WinUSB device configuration, the follow is required: 1. Add the following compiler definition to the target CMakelists.txt `NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). -1. Define a GUID for the device class and set define `DEVICE_CLASS_GUID_PROPERTY` with it. Check [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h). +1. If defining the WinUSB device before compile time: define a GUID for the device class and set define `DEVICE_CLASS_GUID_PROPERTY` with it. Check [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h). For details check [Microsoft documentation](https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/automatic-installation-of-winusb#registering-a-device-interface-guid) about setting a WinUSB device that does not require an INF file to install. + +1. In case the `System.Device.UsbStream` is being used, the device description and class GUID are defined in the C# code, therefore no other configuration is required at build time. + +> **Warning** When performing a debug session from Visual Studio, if the deployment occurs on a blank device, an exception will occur when calling `UsbClient.CreateUsbStream()`. This will NOT happen on subsequent debug sessions nor on a device running the application standalone. The reason for this is that when that call is executed, a new USB interface and associated end points are added to the USB device configuration in order to add that new WinUSB device supporting the `UsbStream`. +This happens because of a limitation of the Gecko SDK as it doesn't allow adding a new interface after the USB device core is running. Stopping the USB device entirely to perform this action is not possible (or better, not desirable) because the CDC device on the same USB composite is being used to connect to Visual Studio. Stopping it would cease communication with Visual Studio, thus ending the debug session. From 6fb07a964a5f690fa807310a70e684460b54e574 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 09:43:08 +0100 Subject: [PATCH 384/572] Rename define to disambiguate --- .../_common/autogen/sl_usbd_class_vendor_instances.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h index 0e763ef420..f5d4490a24 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.h @@ -19,11 +19,11 @@ typedef enum __nfpack UsbEventType #define DEVICEINTERFACE_GUID_PROP_NAME L"DeviceInterfaceGUID" /// Length of GUID Property Name -#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof (DEVICEINTERFACE_GUID_PROP_NAME) +#define DEVICEINTERFACE_GUID_PROP_NAME_LEN sizeof(DEVICEINTERFACE_GUID_PROP_NAME) // GUID for device class that will be reported to WinUSB (going into DeviceInterfaceGUID extended property) -#define DEVICE_CLASS_GUID_PROPERTY L"{00000000-0000-0000-0000-000000000000}" -#define DEVICE_CLASS_GUID_PROPERTY_LEN sizeof(DEVICE_CLASS_GUID_PROPERTY) +#define DEVICE_CLASS_GUID_PROPERTY_PLACEHOLDER L"{00000000-0000-0000-0000-000000000000}" +#define DEVICE_CLASS_GUID_PROPERTY_LEN sizeof(DEVICE_CLASS_GUID_PROPERTY_PLACEHOLDER) /* class numbers assigned by the USB stack after init */ @@ -39,10 +39,11 @@ __WEAK void sl_usbd_vendor_winusb_on_setup_request_event(const sl_usbd_setup_req /* init functions for all vendor instances */ #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -sl_status_t sli_usbd_vendor_winusb_init(void); + sl_status_t sli_usbd_vendor_winusb_init(void); #ifdef __cplusplus } From f51ecb618f869470e5a48de99a893819454b9fc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 09:46:30 +0100 Subject: [PATCH 385/572] Fixes for UART IOStream depending on features being used --- .../sl_iostream_init_usart_instances.c | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c index 71e5e99c18..e5ef9d328c 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_iostream_init_usart_instances.c @@ -301,37 +301,46 @@ static void events_handler(sl_power_manager_em_t from, sl_power_manager_em_t to) ((to == SL_POWER_MANAGER_EM1) || (to == SL_POWER_MANAGER_EM0))) { +#if HAL_USE_ONEWIRE == TRUE // Wake the USART Tx pin back up out = GPIO_PinOutGet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN, gpioModePushPull, out); +#endif // HAL_USE_ONEWIRE +#if HAL_WP_USE_SERIAL == TRUE // Wake the USART Tx pin back up out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModePushPull, out); +#endif // HAL_WP_USE_SERIAL + } else if ( ((to == SL_POWER_MANAGER_EM2) || (to == SL_POWER_MANAGER_EM3)) && ((from == SL_POWER_MANAGER_EM1) || (from == SL_POWER_MANAGER_EM0))) { +#if HAL_USE_ONEWIRE == TRUE // Sleep the USART Tx pin on series 2 devices to save energy out = GPIO_PinOutGet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_ONEWIRE_TX_PORT, SL_IOSTREAM_USART_ONEWIRE_TX_PIN, gpioModeDisabled, out); +#endif // HAL_USE_ONEWIRE +#if HAL_WP_USE_SERIAL == TRUE // Sleep the USART Tx pin on series 2 devices to save energy out = GPIO_PinOutGet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN); GPIO_PinModeSet(SL_IOSTREAM_USART_VCOM_TX_PORT, SL_IOSTREAM_USART_VCOM_TX_PIN, gpioModeDisabled, out); +#endif // HAL_WP_USE_SERIAL + } #endif // _SILICON_LABS_32B_SERIES_2 - // Enable next byte detect to wake from sleep if (to < SL_POWER_MANAGER_EM2) { + // Only prepare for wakeup from EM1 or less, since USART doesn't run in EM2 - // Enable next byte detection to wakeup from sleep on next byte - context_onewire.context.set_next_byte_detect(sl_iostream_onewire_handle->context, true); - - // Enable next byte detection to wakeup from sleep on next byte - context_vcom.context.set_next_byte_detect(sl_iostream_vcom_handle->context, true); + if (sl_iostream_uart_vcom_handle->stream.context != NULL) + { + sl_iostream_uart_prepare_for_sleep(sl_iostream_uart_vcom_handle); + } } } #endif // SL_CATALOG_POWER_MANAGER_PRESENT From 4c786d530d2e77b732c0cde4434ca1b0027464f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 11:05:22 +0100 Subject: [PATCH 386/572] Update Gecko SDK to 4.2.3 --- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 6fc0b90563..c1c82e0627 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -70,7 +70,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.2.2") + set(GECKO_SDK_VERSION "v4.2.3") endif() if(NO_GECKO_SDK_SOURCE) From 3c5865586b4e4b093b2d17da981baa34842e34bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 11:05:41 +0100 Subject: [PATCH 387/572] Remove unnecessary (confusing) build options --- targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index ce11ac948a..aa9af63979 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -43,8 +43,6 @@ "API_Windows.Storage": "OFF", "API_nanoFramework.Graphics": "OFF", "TARGET_SERIAL_BAUDRATE": "921600", - "GECKO_FEATURE_USBD_HID": "OFF", - "GECKO_FEATURE_USBD_WINUSB": "OFF", "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_System.Device.Spi": "OFF", From 4a8127e30e16beef44d29911b3150fe2b9c3678d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 12:10:29 +0100 Subject: [PATCH 388/572] Remove gcc pragmas to ignore undefined macros - Fix upstream with latest USB release in Gecko SDK. --- .../autogen/sl_usbd_class_cdc_acm_instances.c | 11 ------- .../autogen/sl_usbd_class_cdc_acm_instances.h | 9 ------ .../autogen/sl_usbd_class_hid_instances.c | 18 +++-------- .../autogen/sl_usbd_configuration_instances.c | 10 ------ .../SL_STK3701A/nanoCLR/usb_hid_app.c | 10 ------ .../_common/WireProtocol_HAL_Interface.c | 18 +++-------- .../WireProtocol_ReceiverThread_Platform.c | 11 ------- .../autogen/sl_usbd_class_vendor_instances.c | 31 +++++++++++-------- .../_common/autogen/sl_usbd_init.c | 10 ------ .../_common/sl_usbd_class_hid_azurertos.c | 11 ------- .../_common/sl_usbd_core_azuretos.c | 22 ------------- .../SiliconLabs/_common/usb_cdc_acm_app.c | 11 ------- .../sys_dev_usbstream_native_target.h | 10 ------ 13 files changed, 26 insertions(+), 156 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c index 6e311890b9..12f715438d 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.c @@ -8,18 +8,7 @@ // Includes. #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include /* template headers */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h index 8fa8f62373..dd62731af5 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_cdc_acm_instances.h @@ -7,17 +7,8 @@ #ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT #define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - /* class numbers assigned by the USB stack after init */ extern uint8_t sl_usbd_cdc_acm_acm0_number; diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c index 33c10907fc..2d2f895096 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_class_hid_instances.c @@ -7,23 +7,13 @@ //**************************************************************************** // Includes. -#include "sl_status.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - +#include #include -#include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif +#include /* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_hid_instances.h" +#include +#include /* include config file for the instances */ diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c index 18f8c70f9d..0a865bccfc 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/autogen/sl_usbd_configuration_instances.c @@ -8,18 +8,8 @@ // Includes. #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - /* template headers */ #include "sl_usbd_configuration_instances.h" diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c index 8f926ef311..f058c33353 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/usb_hid_app.c @@ -11,18 +11,8 @@ #include #include -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include #include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include // Task configuration diff --git a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c index e9a6ccb89e..9af59550f7 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c +++ b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_HAL_Interface.c @@ -17,20 +17,10 @@ #include #elif HAL_WP_USE_USB_CDC == TRUE -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - -#include "sl_usbd_core.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "sl_usbd_class_cdc.h" -#include "sl_usbd_class_cdc_acm.h" -#include "sl_usbd_class_cdc_acm_instances.h" +#include +#include +#include +#include #endif #if defined(TRACE_MASK) && (TRACE_MASK & TRACE_VERBOSE) != 0 diff --git a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c index 9a41a5c391..8ac2a62363 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c +++ b/targets/AzureRTOS/SiliconLabs/_common/WireProtocol_ReceiverThread_Platform.c @@ -10,20 +10,9 @@ #include #include -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include #include - #include #define TASK_DELAY_MS 250u diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 2f1217a65e..642eee18ff 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -10,24 +10,13 @@ #include "sl_status.h" #include #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include #include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include "sl_usbd_class_vendor.h" /* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_vendor_instances.h" +#include +#include /* include config file for the instances */ @@ -139,6 +128,22 @@ sl_status_t sli_usbd_vendor_winusb_init() /* store class number globally */ sl_usbd_vendor_winusb_number = class_number; + // even if not initialized, check if it's active + bool classIsEnabled; + + if(sl_usbd_vendor_is_enabled(class_number, &classIsEnabled) != SL_STATUS_OK) + { + // error getting class enabled status + return SL_STATUS_FAIL; + } + + if(classIsEnabled) + { + // already active, disable it to add new configuration + //sl_usbd_vendor_disable + //usbd_vendor_disable(sl_usbd_configuration_config0_number, void *p_if_class_arg) + } + /* tokenize configs by "," and spaces */ token = strtok(configs, ", "); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c index fb3759f4a8..1968eabb67 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_init.c @@ -4,18 +4,8 @@ #include #include "sl_status.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #if GECKO_FEATURE_USBD_HID == TRUE #include "sl_usbd_class_hid.h" #endif diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c index 4a48212a9c..ec6ea856d8 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_class_hid_azurertos.c @@ -11,19 +11,8 @@ #include #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include #include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include #include diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c index 18989438c7..b928784fe8 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_usbd_core_azuretos.c @@ -12,33 +12,11 @@ #include #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include #include -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - - TX_THREAD task_handle; uint32_t usbdCoreThreadStack[SL_USBD_TASK_STACK_SIZE / sizeof(uint32_t)]; uint8_t message_queue_storage[sizeof(sli_usbd_core_event_t) * SL_USBD_CORE_EVENT_BUS_NBR]; diff --git a/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c b/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c index a1d3153910..56a70aaf88 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c +++ b/targets/AzureRTOS/SiliconLabs/_common/usb_cdc_acm_app.c @@ -10,18 +10,7 @@ #include #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include "sl_usbd_class_cdc.h" #include "sl_usbd_class_cdc_acm.h" diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index 121cffeea4..fa510b9d91 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -3,16 +3,6 @@ // See LICENSE file in the project root for full license information. // -////////////////////////////////////////////////////////////////////////////////////////////////////// -// Need to add these here, until Silabs fixes the include files. -// Also can't use the #pragma GCC diagnostic ignored "-Wundef" in C++ because there's a bug with it // -// It's reportedly fixed and will be available in GCC 13. -////////////////////////////////////////////////////////////////////////////////////////////////////// -#define USBD_CFG_HS_EN 0 -#define USBD_CFG_EP_ISOC_EN 0 -#define USBD_CFG_OPTIMIZE_SPD 0 -////////////////////////////////////////////////////////////////////////////////////////////////////// - #include // need these declared here as they are scattered throughout Gecko SDK and config files From ad7e929051a0d0681d460d65df9a4c8101a98b7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 May 2023 12:10:49 +0100 Subject: [PATCH 389/572] Remove gcc pragmas to ignore undefined macros - Fix upstream with latest USB release in Gecko SDK. --- .../autogen/sl_usbd_class_cdc_acm_instances.c | 11 ----------- .../autogen/sl_usbd_class_cdc_acm_instances.h | 9 --------- .../SKY_EVB/autogen/sl_usbd_class_hid_instances.c | 12 +----------- .../autogen/sl_usbd_configuration_instances.c | 10 ---------- .../SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c | 10 ---------- 5 files changed, 1 insertion(+), 51 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c index 6e311890b9..12f715438d 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c @@ -8,18 +8,7 @@ // Includes. #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include /* template headers */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h index 8fa8f62373..dd62731af5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h @@ -7,17 +7,8 @@ #ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT #define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - /* class numbers assigned by the USB stack after init */ extern uint8_t sl_usbd_cdc_acm_acm0_number; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c index 33c10907fc..18d550951b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c @@ -7,20 +7,10 @@ //**************************************************************************** // Includes. -#include "sl_status.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - +#include #include #include "sl_usbd_class_hid.h" -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - /* template headers */ #include "sl_usbd_configuration_instances.h" #include "sl_usbd_class_hid_instances.h" diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c index 18f8c70f9d..0a865bccfc 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c @@ -8,18 +8,8 @@ // Includes. #include - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - /* template headers */ #include "sl_usbd_configuration_instances.h" diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c index 8f926ef311..f058c33353 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c @@ -11,18 +11,8 @@ #include #include -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wundef" -#endif - #include #include "sl_usbd_class_hid.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - #include // Task configuration From c2cd5f7182fff47efb37f7934528baa8020a5b75 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 10 May 2023 10:16:16 +0100 Subject: [PATCH 390/572] Increase block storage for CLR --- .../SiliconLabs/SKY_EVB/common/Device_BlockStorage.c | 6 +++--- .../AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c index 5af685ff82..09982097e3 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c @@ -13,10 +13,10 @@ const BlockRange BlockRange1[] = { {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 65}, + {BlockRange_BLOCKTYPE_CODE, 12, 66}, - // 00042000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 66, 510}, + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld index 3ce42ce5c5..d17abebca3 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1780k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00042000, len = 1780k /* space reserved for application deployment */ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From ca39e505d9d60f7e5f31905d3c0e3e1a7a0798fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 18 May 2023 16:07:10 +0100 Subject: [PATCH 391/572] Improve execution of USB stream R/W operations with timeouts - USB async complete handlers now do not fire internal events if the operation was aborted. - Add missing reset for TX count when starting a write operation. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d1eb27cabe..17b4bd4fe4 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -25,10 +25,14 @@ static void UsbAsyncWriteCompleted( NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; - // store TX count - usbPal->TxBytesSent = xfer_len; + // process this only IF the operation wasn't aborted + if (status != SL_STATUS_ABORT) + { + // store TX count + usbPal->TxBytesSent = xfer_len; - Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); + Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); + } NATIVE_INTERRUPT_END } @@ -44,16 +48,19 @@ static void UsbAsyncReadCompleted( (void)class_nbr; (void)p_buf; (void)buf_len; - (void)status; NATIVE_INTERRUPT_START NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; - // store RX count - usbPal->RxBytesReceived = xfer_len; + // process this only IF the operation wasn't aborted + if (status != SL_STATUS_ABORT) + { + // store RX count + usbPal->RxBytesReceived = xfer_len; - Events_Set(SYSTEM_EVENT_FLAG_USB_IN); + Events_Set(SYSTEM_EVENT_FLAG_USB_IN); + } NATIVE_INTERRUPT_END } @@ -172,6 +179,7 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ // pop timeout heap block from stack stack.PopValue(); + // set result with count of bytes received stack.SetResult_I4(UsbStream_PAL.RxBytesReceived); @@ -252,6 +260,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO // bump custom state stack.m_customState = 2; + // clear TX counter + UsbStream_PAL.TxBytesSent = 0; + // start write operation with async API // requesting handling of "End-of-transfer" reqStatus = sl_usbd_vendor_write_bulk_async( From 275c43d2e0a117c4b4d66bb8bee61aa4b2ff1ace Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 18 May 2023 19:09:41 +0100 Subject: [PATCH 392/572] Improve handling of IsConnected property - Doesn't throw anymore when USB system is not ready. --- ...stream_native_System_Device_Usb_UsbStream.cpp | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 17b4bd4fe4..6c0c619839 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -336,18 +336,14 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::get_IsConn { NANOCLR_HEADER(); - bool conn; + // default to false + bool conn = false; - if (sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn) == SL_STATUS_OK) - { - stack.SetResult_Boolean(conn); - } - else - { - NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); - } + // don't care about return value as we'll just return false if the connection state can't be determined + sl_usbd_vendor_is_enabled(sl_usbd_vendor_winusb_number, &conn); + stack.SetResult_Boolean(conn); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP_NOLABEL(); } HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeClose___VOID(CLR_RT_StackFrame &stack) From 4e15cfda6394aecf361e1588a5946721167bd281 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 19 May 2023 15:47:29 +0100 Subject: [PATCH 393/572] Minor improvements in Skyworks SPI --- .../System.Device.Spi/nf_gecko_spi_driver.cpp | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp index 63da94ffc6..f8820dbbb7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -727,7 +727,9 @@ Ecode_t NF_SpiDriver_Transfer( { Ecode_t retVal; - if ((retVal = TransferApiPrologue(handle, (void *)txBuffer, count)) != ECODE_EMDRV_SPIDRV_OK) + retVal = TransferApiPrologue(handle, (void *)txBuffer, count); + + if (retVal != ECODE_EMDRV_SPIDRV_OK) { return retVal; } @@ -767,7 +769,9 @@ Ecode_t NF_SpiDriver_TransferBlocking(NF_SpiDriver_Handle_t handle, const void * { Ecode_t retVal; - if ((retVal = TransferApiBlockingPrologue(handle, (void *)txBuffer, count)) != ECODE_EMDRV_SPIDRV_OK) + retVal = TransferApiBlockingPrologue(handle, (void *)txBuffer, count); + + if (retVal != ECODE_EMDRV_SPIDRV_OK) { return retVal; } @@ -811,7 +815,9 @@ Ecode_t NF_SpiDriver_Transmit( { Ecode_t retVal; - if ((retVal = TransferApiPrologue(handle, (void *)buffer, count)) != ECODE_EMDRV_SPIDRV_OK) + retVal = TransferApiPrologue(handle, (void *)buffer, count); + + if (retVal != ECODE_EMDRV_SPIDRV_OK) { return retVal; } @@ -844,7 +850,9 @@ Ecode_t NF_SpiDriver_TransmitBlocking(NF_SpiDriver_Handle_t handle, const void * { Ecode_t retVal; - if ((retVal = TransferApiBlockingPrologue(handle, (void *)buffer, count)) != ECODE_EMDRV_SPIDRV_OK) + retVal = TransferApiBlockingPrologue(handle, (void *)buffer, count); + + if (retVal != ECODE_EMDRV_SPIDRV_OK) { return retVal; } From 6465f32a5d9f87a82b7763cb9f1c108dcfc47b76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 19 May 2023 17:13:30 +0100 Subject: [PATCH 394/572] Add and rename CMake presets - Addresses Skyworks-Timing-Software/MCU#68. --- .../SiliconLabs/SKY_EVB/CMakePresets.json | 189 ++++++++++-------- 1 file changed, 104 insertions(+), 85 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index aa9af63979..1ca953b72b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -1,85 +1,104 @@ -{ - "version": 4, - "include": [ - "../../../../CMake/arm-gcc.json", - "../../../../config/user-tools-repos.json", - "../../../../config/user-prefs.json" - ], - "configurePresets": [ - { - "name": "SKY_EEVB", - "inherits": [ - "arm-gcc-cortex-preset", - "user-tools-repos", - "user-prefs" - ], - "hidden": false, - "cacheVariables": { - "TARGET_BOARD": "SKY_EVB", - "TARGET_NAME": "SKY_EEVB", - "RTOS": "AzureRTOS", - "TARGET_SERIES": "EFM32GG11", - "SUPPORT_ANY_BASE_CONVERSION": "OFF", - "NF_FEATURE_DEBUGGER": "ON", - "NF_FEATURE_RTC": "ON", - "NF_FEATURE_HAS_SDCARD": "OFF", - "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "SWO_OUTPUT": "OFF", - "NF_BUILD_RTM": "OFF", - "API_System.Math": "ON", - "API_Hardware.GiantGecko": "ON", - "API_System.Device.Gpio": "ON", - "API_System.Device.Pwm": "ON", - "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", - "API_System.Device.Dac": "OFF", - "API_System.Net": "OFF", - "API_nanoFramework.Device.OneWire": "ON", - "API_nanoFramework.Devices.Can": "OFF", - "API_nanoFramework.ResourceManager": "ON", - "API_nanoFramework.System.Collections": "ON", - "API_nanoFramework.System.Text": "ON", - "API_nanoFramework.GiantGecko.Adc": "ON", - "API_Windows.Storage": "OFF", - "API_nanoFramework.Graphics": "OFF", - "TARGET_SERIAL_BAUDRATE": "921600", - "HAL_WP_USE_SERIAL": "OFF", - "HAL_WP_USE_USB_CDC": "ON", - "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", - "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON" - } - }, - { - "name": "SKY_EEVB_STD_SIF", - "inherits": [ - "SKY_EEVB" - ], - "cacheVariables": { - "TARGET_BOARD": "SKY_EVB", - "TARGET_NAME": "SKY_EEVB_STD_SIF", - "API_System.Device.Spi": "ON", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", - "API_System.Device.I2c": "ON", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "OFF", - "API_System.Device.UsbStream": "ON" - } - } - ], - "buildPresets": [ - { - "inherits": "base-user", - "name": "SKY_EEVB", - "displayName": "SKY_EEVB", - "configurePreset": "SKY_EEVB" - }, - { - "inherits": "base-user", - "name": "SKY_EEVB_STD_SIF", - "displayName": "SKY_EEVB_STD_SIF", - "configurePreset": "SKY_EEVB_STD_SIF" - } - ] -} +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_EEVB_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "SKY_EVB", + "TARGET_NAME": "SKY_EEVB_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "SWO_OUTPUT": "OFF", + "NF_BUILD_RTM": "OFF", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON" + } + }, + { + "name": "SKY_EEVB_Release", + "inherits": [ + "SKY_EEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "NF_BUILD_RTM": "ON" + } + }, + { + "name": "SKY_EEVB_STD_SIF_Debug", + "inherits": [ + "SKY_EEVB_Debug" + ], + "cacheVariables": { + "TARGET_BOARD": "SKY_EVB", + "TARGET_NAME": "SKY_EEVB_STD_SIF_Debug", + "API_System.Device.Spi": "ON", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", + "API_System.Device.I2c": "ON", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "OFF", + "API_System.Device.UsbStream": "ON" + } + }, + { + "name": "SKY_EEVB_STD_SIF_Release", + "inherits": [ + "SKY_EEVB_STD_SIF_Debug" + ], + "cacheVariables": { + "NF_BUILD_RTM": "ON" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_EEVB_Debug", + "displayName": "SKY_EEVB_Debug", + "configurePreset": "SKY_EEVB_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_EEVB_STD_SIF_Debug", + "displayName": "SKY_EEVB_STD_SIF_Debug", + "configurePreset": "SKY_EEVB_STD_SIF_Debug" + } + ] +} From 832d0a864352d91447f3e5af5839bb34750a1725 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 19 May 2023 17:23:51 +0100 Subject: [PATCH 395/572] Work on github actions for build pipelines - Rename targets. - Add new targets for RTM release builds. - Fix artifacts name. - Closes Skyworks-Timing-Software/MCU#68. --- ...KY_EEVB.yaml => Build_SKY_EEVB_Debug.yaml} | 6 +- .github/workflows/Build_SKY_EEVB_Release.yaml | 106 ++++++++++++++++++ ...yaml => Build_SKY_EEVB_STD_SIF_Debug.yaml} | 6 +- .../Build_SKY_EEVB_STD_SIF_Release.yaml | 106 ++++++++++++++++++ 4 files changed, 218 insertions(+), 6 deletions(-) rename .github/workflows/{Build_SKY_EEVB.yaml => Build_SKY_EEVB_Debug.yaml} (94%) create mode 100644 .github/workflows/Build_SKY_EEVB_Release.yaml rename .github/workflows/{Build_SKY_EEVB_STD_SIF.yaml => Build_SKY_EEVB_STD_SIF_Debug.yaml} (93%) create mode 100644 .github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml diff --git a/.github/workflows/Build_SKY_EEVB.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml similarity index 94% rename from .github/workflows/Build_SKY_EEVB.yaml rename to .github/workflows/Build_SKY_EEVB_Debug.yaml index 86948ae883..d7b4f6a1d7 100644 --- a/.github/workflows/Build_SKY_EEVB.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -1,4 +1,4 @@ -name: Build SKY_EEVB +name: Build SKY_EEVB_Debug on: workflow_dispatch @@ -8,7 +8,7 @@ jobs: runs-on: windows-latest env: - TARGET_NAME: 'SKY_EEVB' + TARGET_NAME: 'SKY_EEVB_Debug' steps: - uses: actions/checkout@v3 @@ -88,7 +88,7 @@ jobs: - uses: actions/upload-artifact@v3 with: - name: ${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Build_SKY_EEVB_Release.yaml new file mode 100644 index 0000000000..a6ff8ef6ee --- /dev/null +++ b/.github/workflows/Build_SKY_EEVB_Release.yaml @@ -0,0 +1,106 @@ +name: Build SKY_EEVB_Release + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB: + runs-on: windows-latest + + env: + TARGET_NAME: 'SKY_EEVB_Release' + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ env.TARGET_NAME }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ env.TARGET_NAME }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v3 + with: + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + + - name: Tag the build + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) \ No newline at end of file diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml similarity index 93% rename from .github/workflows/Build_SKY_EEVB_STD_SIF.yaml rename to .github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml index 1ea485c37b..ec1845fa9b 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -1,4 +1,4 @@ -name: Build SKY_EEVB_STD_SIF +name: Build SKY_EEVB_STD_SIF_Debug on: workflow_dispatch @@ -8,7 +8,7 @@ jobs: runs-on: windows-latest env: - TARGET_NAME: 'SKY_EEVB_STD_SIF' + TARGET_NAME: 'SKY_EEVB_STD_SIF_Debug' steps: - uses: actions/checkout@v3 @@ -88,7 +88,7 @@ jobs: - uses: actions/upload-artifact@v3 with: - name: ${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml new file mode 100644 index 0000000000..c515071e8f --- /dev/null +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -0,0 +1,106 @@ +name: Build SKY_EEVB_STD_SIF_Release + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF: + runs-on: windows-latest + + env: + TARGET_NAME: 'SKY_EEVB_STD_SIF_Release' + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ env.TARGET_NAME }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ env.TARGET_NAME }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - uses: actions/upload-artifact@v3 + with: + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + + - name: Tag the build + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) \ No newline at end of file From db7231629b15cfab647400720982690fe947cb07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 19 May 2023 19:15:24 +0100 Subject: [PATCH 396/572] Fix processing Wire Protocol header reception - Call to memmove and marker comparison where wrong and where causing issues depending on length of data received. --- src/CLR/WireProtocol/WireProtocol_Message.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/CLR/WireProtocol/WireProtocol_Message.c b/src/CLR/WireProtocol/WireProtocol_Message.c index b23cc72b1a..0ac610bfe2 100644 --- a/src/CLR/WireProtocol/WireProtocol_Message.c +++ b/src/CLR/WireProtocol/WireProtocol_Message.c @@ -279,7 +279,7 @@ void WP_Message_Process() break; } - size_t lenCmp = min(len, sizeof(_inboundMessage.m_header.m_signature)); + size_t lenCmp = min(len, sizeof(((WP_Packet *)0)->m_signature)); if (memcmp(&_inboundMessage.m_header, MARKER_DEBUGGER_V1, lenCmp) == 0) { @@ -290,11 +290,8 @@ void WP_Message_Process() break; } - // move buffer 1 position down - memmove( - (uint8_t *)&(_inboundMessage.m_header), - ((uint8_t *)&(_inboundMessage.m_header) + 1), - len - 1); + // move buffer one position to the left + memmove((uint8_t *)&(_inboundMessage.m_header), ((uint8_t *)&(_inboundMessage.m_header) + 1), len); _pos--; _size++; From f09186ae237daa336d3883766e9f22e8c8315e3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Fri, 19 May 2023 19:24:48 +0100 Subject: [PATCH 397/572] Fix CMakepresets declaration - Wrong at 6465f32a5d9f87a82b7763cb9f1c108dcfc47b76 --- .../SiliconLabs/SKY_EVB/CMakePresets.json | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index 1ca953b72b..f7d636a916 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -94,11 +94,23 @@ "displayName": "SKY_EEVB_Debug", "configurePreset": "SKY_EEVB_Debug" }, + { + "inherits": "base-user", + "name": "SKY_EEVB_Release", + "displayName": "SKY_EEVB_Release", + "configurePreset": "SKY_EEVB_Release" + }, { "inherits": "base-user", "name": "SKY_EEVB_STD_SIF_Debug", "displayName": "SKY_EEVB_STD_SIF_Debug", "configurePreset": "SKY_EEVB_STD_SIF_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_EEVB_STD_SIF_Release", + "displayName": "SKY_EEVB_STD_SIF_Release", + "configurePreset": "SKY_EEVB_STD_SIF_Release" } ] -} +} \ No newline at end of file From b0733f01d0b37b2000abc31163f5a2152191adb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 23 May 2023 12:22:03 +0100 Subject: [PATCH 398/572] Split Cmake presets for Skyworks --- .../SiliconLabs/SKY_EVB/CMakePresets.json | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index f7d636a916..d74054b5d8 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "SKY_EEVB_Debug", + "name": "SKY_EEVB", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -16,16 +16,12 @@ "hidden": false, "cacheVariables": { "TARGET_BOARD": "SKY_EVB", - "TARGET_NAME": "SKY_EEVB_Debug", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", - "NF_FEATURE_DEBUGGER": "ON", "NF_FEATURE_RTC": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "SWO_OUTPUT": "OFF", - "NF_BUILD_RTM": "OFF", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", @@ -53,22 +49,33 @@ } }, { - "name": "SKY_EEVB_Release", + "name": "SKY_EEVB_Debug", "inherits": [ "SKY_EEVB_Debug" ], "hidden": false, "cacheVariables": { + "TARGET_NAME": "SKY_EEVB_Debug", + "NF_FEATURE_DEBUGGER": "ON" + } + }, + { + "name": "SKY_EEVB_Release", + "inherits": [ + "SKY_EEVB" + ], + "hidden": false, + "cacheVariables": { + "NF_FEATURE_DEBUGGER": "OFF", "NF_BUILD_RTM": "ON" } }, { "name": "SKY_EEVB_STD_SIF_Debug", "inherits": [ - "SKY_EEVB_Debug" + "SKY_EEVB" ], "cacheVariables": { - "TARGET_BOARD": "SKY_EVB", "TARGET_NAME": "SKY_EEVB_STD_SIF_Debug", "API_System.Device.Spi": "ON", "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", @@ -83,6 +90,7 @@ "SKY_EEVB_STD_SIF_Debug" ], "cacheVariables": { + "NF_FEATURE_DEBUGGER": "OFF", "NF_BUILD_RTM": "ON" } } From b9e950183c2821ce433d8d763eba03200e661ed5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 23 May 2023 15:18:01 +0100 Subject: [PATCH 399/572] Fix cmake presets for Skyworks --- .../SiliconLabs/SKY_EVB/CMakePresets.json | 23 ++++++------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json index d74054b5d8..6dd6c4ac42 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "SKY_EEVB", + "name": "SKY_EEVB_Debug", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -16,10 +16,12 @@ "hidden": false, "cacheVariables": { "TARGET_BOARD": "SKY_EVB", + "TARGET_NAME": "SKY_EEVB_Debug", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "API_System.Math": "ON", @@ -48,32 +50,21 @@ "API_System.Device.UsbStream": "ON" } }, - { - "name": "SKY_EEVB_Debug", - "inherits": [ - "SKY_EEVB_Debug" - ], - "hidden": false, - "cacheVariables": { - "TARGET_NAME": "SKY_EEVB_Debug", - "NF_FEATURE_DEBUGGER": "ON" - } - }, { "name": "SKY_EEVB_Release", "inherits": [ - "SKY_EEVB" + "SKY_EEVB_Debug" ], "hidden": false, "cacheVariables": { - "NF_FEATURE_DEBUGGER": "OFF", + "TARGET_NAME": "SKY_EEVB", "NF_BUILD_RTM": "ON" } }, { "name": "SKY_EEVB_STD_SIF_Debug", "inherits": [ - "SKY_EEVB" + "SKY_EEVB_Debug" ], "cacheVariables": { "TARGET_NAME": "SKY_EEVB_STD_SIF_Debug", @@ -90,7 +81,7 @@ "SKY_EEVB_STD_SIF_Debug" ], "cacheVariables": { - "NF_FEATURE_DEBUGGER": "OFF", + "TARGET_NAME": "SKY_EEVB_STD_SIF", "NF_BUILD_RTM": "ON" } } From b34b13219cae2ff90e64447544f6aa38b30df39f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 May 2023 10:37:35 +0100 Subject: [PATCH 400/572] Added revert to nanoBooter to CLR settings --- targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c index 53a80cabf3..6661c9eb80 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c @@ -139,6 +139,7 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; clrSettings.EnterDebuggerLoopAfterExit = true; + clrSettings.RevertToBooterOnFault = true; // Create CLR startup thread status = tx_thread_create( From 5794ef551f00ae15a9d5f309db0fc12cc37f7540 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 26 May 2023 19:56:38 +0100 Subject: [PATCH 401/572] Improvements in USB stream processing - Add tx and rx events to PAL struct. - Rework USB event handlers to fire managed event processing only if the event was expected. - Rx and Tx events are cleared in event handlers and set beforehand in preparation for execution. --- ...eam_native_System_Device_Usb_UsbStream.cpp | 27 ++++++++++++++++--- .../sys_dev_usbstream_native_target.h | 3 +++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 6c0c619839..d227242864 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -26,7 +26,8 @@ static void UsbAsyncWriteCompleted( NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; // process this only IF the operation wasn't aborted - if (status != SL_STATUS_ABORT) + // AND we're expecting an event + if (status != SL_STATUS_ABORT && usbPal->WaitingForTxEvent) { // store TX count usbPal->TxBytesSent = xfer_len; @@ -34,6 +35,9 @@ static void UsbAsyncWriteCompleted( Events_Set(SYSTEM_EVENT_FLAG_USB_OUT); } + // clear the flag + usbPal->WaitingForTxEvent = false; + NATIVE_INTERRUPT_END } @@ -54,7 +58,8 @@ static void UsbAsyncReadCompleted( NF_PAL_USB *usbPal = (NF_PAL_USB *)p_callback_arg; // process this only IF the operation wasn't aborted - if (status != SL_STATUS_ABORT) + // AND we're expecting an event + if (status != SL_STATUS_ABORT && usbPal->WaitingForRxEvent) { // store RX count usbPal->RxBytesReceived = xfer_len; @@ -62,6 +67,9 @@ static void UsbAsyncReadCompleted( Events_Set(SYSTEM_EVENT_FLAG_USB_IN); } + // clear the flag + usbPal->WaitingForRxEvent = false; + NATIVE_INTERRUPT_END } @@ -105,8 +113,6 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ length = dataBuffer->m_numOfElements; // check parameters - FAULT_ON_NULL_ARG(dataBuffer); - if ((offset > length) || (count > length)) { NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); @@ -135,6 +141,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ // clear RX counter UsbStream_PAL.RxBytesReceived = 0; + // set event flag + UsbStream_PAL.WaitingForRxEvent = true; + // start read operation with async API reqStatus = sl_usbd_vendor_read_bulk_async( sl_usbd_vendor_winusb_number, @@ -163,6 +172,13 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ if (eventResult) { + // if different than expected, abort anyway + if (UsbStream_PAL.RxBytesReceived != count) + { + // cancel the async operation... + sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); + } + // done here break; } @@ -263,6 +279,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Write___VO // clear TX counter UsbStream_PAL.TxBytesSent = 0; + // set event flag + UsbStream_PAL.WaitingForTxEvent = true; + // start write operation with async API // requesting handling of "End-of-transfer" reqStatus = sl_usbd_vendor_write_bulk_async( diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index fa510b9d91..a30122a4b0 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -18,6 +18,9 @@ typedef struct uint16_t TxBytesSent; + bool WaitingForRxEvent; + bool WaitingForTxEvent; + } NF_PAL_USB; extern NF_PAL_USB UsbStream_PAL; From 34b4679e977564555b01edeb7132978c99674fce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 30 May 2023 16:32:45 +0100 Subject: [PATCH 402/572] USB device product now is updated in UsbStream open - Remove wrong doc about class vendor description. (it not exposed through the build system) --- targets/AzureRTOS/SiliconLabs/README.md | 2 -- .../sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/README.md b/targets/AzureRTOS/SiliconLabs/README.md index d9970d517b..0471ddb914 100644 --- a/targets/AzureRTOS/SiliconLabs/README.md +++ b/targets/AzureRTOS/SiliconLabs/README.md @@ -21,8 +21,6 @@ In order to add a WinUSB device configuration, the follow is required: [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h) -1. Add the following compiler definition to the target CMakelists.txt `NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION=\"Description-of-your-deice-goes-here\"` (mind the maximum length of 32). - 1. If defining the WinUSB device before compile time: define a GUID for the device class and set define `DEVICE_CLASS_GUID_PROPERTY` with it. Check [sl_usbd_class_winusb_config.h](SL_STK3701A/config/sl_usbd_class_winusb_config.h). For details check [Microsoft documentation](https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/automatic-installation-of-winusb#registering-a-device-interface-guid) about setting a WinUSB device that does not require an INF file to install. diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index d227242864..b2350a49a7 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -410,6 +410,9 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen // store device description hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); + // also update USB device product string + sl_usbd_vendor_update_device_product_string((const char *)UsbClassVendorDescription); + if (sli_usbd_vendor_winusb_init() != SL_STATUS_OK) { NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); From 4f6a97acb70252bc22a1c7cdfbadf2bc7c851132 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 30 May 2023 16:34:06 +0100 Subject: [PATCH 403/572] Cleanup USB device config --- .../SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h index d637b5e987..5c220728b9 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h @@ -27,17 +27,15 @@ extern char *UsbSerialNumber[]; #define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 // Device Manufacturer Name -// Default: "Silicon Labs" // Device manufacturer string. #define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" // Device Product Name -// Default: "Product" // Device product string. -#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EEVB" +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "" // Device Serial Number -// Default: "1234567890ABCDEF" // Device serial number string. #define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber From cad0083fb7fdbbde3df879b3dc70a0b08341e504 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 31 May 2023 13:42:26 +0100 Subject: [PATCH 404/572] Update Skyworks SPI - Update declaration. - Update code accordingly. - Following Skyworks-Timing-Software/MCU#79. --- .../com_sky_nf_dev_spi_native.cpp | 6 +++- .../com_sky_nf_dev_spi_native.h | 33 +++++++++---------- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 4 +-- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index cc1c28a434..c6e9ac922b 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -26,6 +26,10 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, + NULL, + NULL, + NULL, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4, @@ -42,7 +46,7 @@ const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramewo "Com.SkyworksInc.NanoFramework.Devices.Spi", 0x060333BF, method_lookup, - { 100, 0, 0, 5 } + { 100, 0, 0, 7 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 5e328a1e69..f6f418e13c 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -16,29 +16,29 @@ // } DataFlow; // defined src\System.Device.Spi\sys_dev_spi_native.h -// typedef enum __nfpack SpiBusConfiguration -// { -// SpiBusConfiguration_FullDuplex = 0, -// SpiBusConfiguration_HalfDuplex = 1, -// SpiBusConfiguration_Simplex = 2, -// } SpiBusConfiguration; +typedef enum __nfpack SpiPhasePolarityMode +{ + SpiPhasePolarityMode_Mode0 = 0, + SpiPhasePolarityMode_Mode1 = 1, + SpiPhasePolarityMode_Mode2 = 2, + SpiPhasePolarityMode_Mode3 = 3, +} SpiPhasePolarityMode; // defined src\System.Device.Spi\sys_dev_spi_native.h -// typedef enum __nfpack SpiMode -// { -// SpiMode_Mode0 = 0, -// SpiMode_Mode1 = 1, -// SpiMode_Mode2 = 2, -// SpiMode_Mode3 = 3, -// } SpiMode; +typedef enum __nfpack SpiWireMode +{ + SpiWireMode_FullDuplex = 0, + SpiWireMode_HalfDuplex = 1, + SpiWireMode_Simplex = 2, +} SpiWireMode; struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration { static const int FIELD___clockFrequency = 1; static const int FIELD___databitLength = 2; - static const int FIELD___spiMode = 3; + static const int FIELD___spiPhasePolarityMode = 3; static const int FIELD___dataFlow = 4; - static const int FIELD___busConfiguration = 5; + static const int FIELD___spiWireMode = 5; //--// }; @@ -50,8 +50,7 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S static const int FIELD___syncLock = 1; static const int FIELD___bufferSingleOperation = 2; - NANOCLR_NATIVE_DECLARE( - NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); NANOCLR_NATIVE_DECLARE(NativeReportBusSettingsChanged___VOID__I4); NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 27e218af14..bb60149923 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -137,13 +137,13 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) // SPI bus index is 1 based, but the array is 0 based spiDeviceConfig->Spi_Bus = busIndex + 1; - spiDeviceConfig->Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiMode].NumericByRef().s4; + spiDeviceConfig->Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiWireMode].NumericByRef().s4; spiDeviceConfig->DataOrder16 = (DataBitOrder)config[SpiBaseConfiguration::FIELD___dataFlow].NumericByRef().s4; spiDeviceConfig->Clock_RateHz = config[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRef().s4; spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; spiDeviceConfig->BusConfiguration = - (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___busConfiguration].NumericByRef().s4; + (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___spiPhasePolarityMode].NumericByRef().s4; spiDeviceConfig->DataIs16bits = config[SpiBaseConfiguration::FIELD___databitLength].NumericByRef().s4 == 16 ? true : false; // store this here too From 53d962305527303296126ca72367b55de1248b09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 31 May 2023 18:46:31 +0100 Subject: [PATCH 405/572] Add build metadata file to actions --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index d7b4f6a1d7..0e031dc735 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -86,12 +86,30 @@ jobs: buildPreset: '${{ env.TARGET_NAME }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build-metadata.txt" + + $metadata = "Build metadata" + [Environment]::NewLine + $metadata += "---------------" + [Environment]::NewLine + $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + $metadata += "Repository owner: ${{ github.repository_owner }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + - uses: actions/upload-artifact@v3 with: name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build-metadata.txt - name: Tag the build uses: actions/github-script@v6 @@ -103,4 +121,4 @@ jobs: repo: context.repo.repo, ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha - }) \ No newline at end of file + }) From 318672e617d4f0f147ef7767566cbcb78e224579 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 31 May 2023 18:55:18 +0100 Subject: [PATCH 406/572] test conditions --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index 0e031dc735..ceaf077210 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -79,13 +79,6 @@ jobs: - run: nbgv cloud -a -c - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - name: Collect metadata run: | $file = "${{ github.workspace }}/build-metadata.txt" @@ -112,6 +105,7 @@ jobs: ${{ github.workspace }}/build-metadata.txt - name: Tag the build + if: needs.pr-check.outputs.number != 'null' uses: actions/github-script@v6 with: script: | From 1e1252ef4a591e46c8305c536b1339c059eea901 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 31 May 2023 19:10:37 +0100 Subject: [PATCH 407/572] Fix condition --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index ceaf077210..1d14540b6d 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -105,7 +105,7 @@ jobs: ${{ github.workspace }}/build-metadata.txt - name: Tag the build - if: needs.pr-check.outputs.number != 'null' + if: ${{ github.event.pull_request.number == 'null' }} uses: actions/github-script@v6 with: script: | From 7d8d061049d1448ae20666c3f1d9bc2a5c4c7a5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 1 Jun 2023 09:06:27 +0100 Subject: [PATCH 408/572] Changes in file name and text --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index 1d14540b6d..d352a99afc 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -81,10 +81,8 @@ jobs: - name: Collect metadata run: | - $file = "${{ github.workspace }}/build-metadata.txt" + $file = "${{ github.workspace }}/build-info.txt" - $metadata = "Build metadata" + [Environment]::NewLine - $metadata += "---------------" + [Environment]::NewLine $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine @@ -92,7 +90,6 @@ jobs: $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine - $metadata += "Repository owner: ${{ github.repository_owner }}" + [Environment]::NewLine $metadata | Out-File -FilePath $file -Encoding utf-8 -Append From b1f4e601eb10ff9b735a3cad0175af77775f305b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 1 Jun 2023 09:12:38 +0100 Subject: [PATCH 409/572] Correct file name --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index d352a99afc..1652a05e40 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -99,7 +99,7 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build-metadata.txt + ${{ github.workspace }}/build-info.txt - name: Tag the build if: ${{ github.event.pull_request.number == 'null' }} From dea3b09b109108b0653327ac1e0ec9b08e0e7553 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 1 Jun 2023 09:21:17 +0100 Subject: [PATCH 410/572] Add again build step --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index 1652a05e40..3bbe9f9407 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -79,6 +79,13 @@ jobs: - run: nbgv cloud -a -c + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ env.TARGET_NAME }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ env.TARGET_NAME }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + - name: Collect metadata run: | $file = "${{ github.workspace }}/build-info.txt" From 1301c142992a915e24ed834d00a98e75c89aec01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 1 Jun 2023 13:10:35 +0100 Subject: [PATCH 411/572] Add build metadadata to all actions and template --- .github/workflows/Build_SKY_EEVB_Release.yaml | 18 +- .../Build_SKY_EEVB_STD_SIF_Debug.yaml | 228 ++++++++++-------- .../Build_SKY_EEVB_STD_SIF_Release.yaml | 228 ++++++++++-------- .../workflows/build_skyworks_evb.yml.template | 228 ++++++++++-------- 4 files changed, 383 insertions(+), 319 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Build_SKY_EEVB_Release.yaml index a6ff8ef6ee..cf5c89df18 100644 --- a/.github/workflows/Build_SKY_EEVB_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_Release.yaml @@ -86,14 +86,30 @@ jobs: buildPreset: '${{ env.TARGET_NAME }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build-info.txt" + + $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + - uses: actions/upload-artifact@v3 with: name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build-info.txt - name: Tag the build + if: ${{ github.event.pull_request.number == 'null' }} uses: actions/github-script@v6 with: script: | @@ -103,4 +119,4 @@ jobs: repo: context.repo.repo, ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', sha: context.sha - }) \ No newline at end of file + }) diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml index ec1845fa9b..6c05f959b1 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -1,106 +1,122 @@ -name: Build SKY_EEVB_STD_SIF_Debug - -on: - workflow_dispatch - -jobs: - build_SKY_EEVB_STD_SIF: - runs-on: windows-latest - - env: - TARGET_NAME: 'SKY_EEVB_STD_SIF_Debug' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - - - name: Tag the build - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) \ No newline at end of file +name: Build SKY_EEVB_STD_SIF_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF: + runs-on: windows-latest + + env: + TARGET_NAME: 'SKY_EEVB_STD_SIF_Debug' + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ env.TARGET_NAME }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ env.TARGET_NAME }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build-info.txt" + + $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + + - uses: actions/upload-artifact@v3 + with: + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build-info.txt + + - name: Tag the build + if: ${{ github.event.pull_request.number == 'null' }} + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml index c515071e8f..73068bb67b 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -1,106 +1,122 @@ -name: Build SKY_EEVB_STD_SIF_Release - -on: - workflow_dispatch - -jobs: - build_SKY_EEVB_STD_SIF: - runs-on: windows-latest - - env: - TARGET_NAME: 'SKY_EEVB_STD_SIF_Release' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - - - name: Tag the build - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) \ No newline at end of file +name: Build SKY_EEVB_STD_SIF_Release + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF: + runs-on: windows-latest + + env: + TARGET_NAME: 'SKY_EEVB_STD_SIF_Release' + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ env.TARGET_NAME }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ env.TARGET_NAME }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build-info.txt" + + $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + + - uses: actions/upload-artifact@v3 + with: + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build-info.txt + + - name: Tag the build + if: ${{ github.event.pull_request.number == 'null' }} + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index e6e6860266..a5a07cd94c 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -1,106 +1,122 @@ -name: Build @PRESET@ - -on: - workflow_dispatch - -jobs: - build_@PRESET@: - runs-on: windows-latest - - env: - TARGET_NAME: '@PRESET@' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - uses: actions/upload-artifact@v3 - with: - name: ${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - - - name: Tag the build - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) \ No newline at end of file +name: Build @PRESET@ + +on: + workflow_dispatch + +jobs: + build_@PRESET@: + runs-on: windows-latest + + env: + TARGET_NAME: '@PRESET@' + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ env.TARGET_NAME }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ env.TARGET_NAME }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build-info.txt" + + $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + + - uses: actions/upload-artifact@v3 + with: + name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build-info.txt + + - name: Tag the build + if: ${{ github.event.pull_request.number == 'null' }} + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) From 17ce5c36e45c6730329ad065f3e37f15e7674c6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 5 Jun 2023 17:44:22 +0100 Subject: [PATCH 412/572] Add support for NoStackTraceInExceptions - Add new debugger execution condition flag. - Update code accordingly to skip processing this according the flag. --- .../CorLib/corlib_native_System_Exception.cpp | 80 +++++++++++-------- src/CLR/Core/Interpreter.cpp | 17 ++-- src/CLR/Include/nanoCLR_Runtime.h | 15 ++-- 3 files changed, 67 insertions(+), 45 deletions(-) diff --git a/src/CLR/CorLib/corlib_native_System_Exception.cpp b/src/CLR/CorLib/corlib_native_System_Exception.cpp index 4cc1caff22..8f00f47dfb 100644 --- a/src/CLR/CorLib/corlib_native_System_Exception.cpp +++ b/src/CLR/CorLib/corlib_native_System_Exception.cpp @@ -180,50 +180,66 @@ HRESULT Library_corlib_native_System_Exception::SetStackTrace(CLR_RT_HeapBlock & CLR_RT_HeapBlock *obj; CLR_RT_HeapBlock_Array *array; StackTrace *dst; - CLR_UINT32 depth; - - if (CLR_RT_ExecutionEngine::IsInstanceOf(ref, g_CLR_RT_WellKnownTypes.m_Exception) == false) - NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); - - //--// + CLR_UINT32 depth = 0; obj = ref.Dereference(); - depth = 0; - NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame, stackSub, stack) + if (CLR_RT_ExecutionEngine::IsInstanceOf(ref, g_CLR_RT_WellKnownTypes.m_Exception) == false) { - depth++; + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } - NANOCLR_FOREACH_NODE_BACKWARD_END(); - - //--// - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( - obj[FIELD___stackTrace], - depth * sizeof(StackTrace), - g_CLR_RT_WellKnownTypes.m_UInt8)); - - //--// - - array = obj[FIELD___stackTrace].DereferenceArray(); - dst = (StackTrace *)array->GetFirstElement(); - - NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame, stackSub, stack) + if (CLR_EE_DBG_IS(NoStackTraceInExceptions)) { - dst->m_md = stackSub->m_call; - dst->m_IP = (CLR_UINT32)(stackSub->m_IP - stackSub->m_IPstart); + // stack trace is DISABLED - dst++; + // create an empty array for the stack trace + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + obj[FIELD___stackTrace], + depth, + g_CLR_RT_WellKnownTypes.m_UInt8)); + + //.. and assign it to the field + array = obj[FIELD___stackTrace].DereferenceArray(); } - NANOCLR_FOREACH_NODE_BACKWARD_END(); + else + { + // stack trace is enabled + + // crawl the stack to get the depth + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame, stackSub, stack) + { + depth++; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + obj[FIELD___stackTrace], + depth * sizeof(StackTrace), + g_CLR_RT_WellKnownTypes.m_UInt8)); + + // get a pointer to the array + array = obj[FIELD___stackTrace].DereferenceArray(); + dst = (StackTrace *)array->GetFirstElement(); + + // crawl the stack to get the stack trace + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame, stackSub, stack) + { + dst->m_md = stackSub->m_call; + dst->m_IP = (CLR_UINT32)(stackSub->m_IP - stackSub->m_IPstart); + + dst++; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); #if !defined(BUILD_RTM) - // shutting down the EE happens by Thread->Abort. These exceptions are by design, and - // don't need to be logged, or written to the console.... - if (!g_CLR_RT_ExecutionEngine.m_fShuttingDown) + // shutting down the EE happens by Thread->Abort. These exceptions are by design, and + // don't need to be logged, or written to the console.... + if (!g_CLR_RT_ExecutionEngine.m_fShuttingDown) #endif - { - CLR_RT_DUMP::EXCEPTION(*stack, ref); + { + CLR_RT_DUMP::EXCEPTION(*stack, ref); + } } } diff --git a/src/CLR/Core/Interpreter.cpp b/src/CLR/Core/Interpreter.cpp index ee6d267962..32bd726d8f 100644 --- a/src/CLR/Core/Interpreter.cpp +++ b/src/CLR/Core/Interpreter.cpp @@ -438,7 +438,7 @@ bool CLR_RT_Thread::FindEhBlock( // processed. #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) { if (!onlyFinallys || s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) { @@ -497,7 +497,7 @@ bool CLR_RT_Thread::FindEhBlock( } #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) { if (to == NULL || s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) { @@ -534,7 +534,8 @@ bool CLR_RT_Thread::FindEhBlock( if (ptrEhExt->IsFinally() && (!to || (to < ptrEhExt->m_tryStart || to >= ptrEhExt->m_tryEnd))) { #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && + s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) { CLR_Debug::Printf("Found match for a 'finally'\r\n"); } @@ -549,7 +550,8 @@ bool CLR_RT_Thread::FindEhBlock( if (ptrEhExt->IsCatchAll()) { #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && + s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) { CLR_Debug::Printf("Found match for a 'catch all'\r\n"); } @@ -564,7 +566,8 @@ bool CLR_RT_Thread::FindEhBlock( CLR_RT_ExecutionEngine::IsInstanceOf(m_currentException, ptrEhExt->m_typeFilter)) { #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && + s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) { if (ptrEhExt->IsFilter()) { @@ -589,7 +592,7 @@ bool CLR_RT_Thread::FindEhBlock( } #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) { if (to == NULL || s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) { @@ -1005,7 +1008,7 @@ HRESULT CLR_RT_Thread::Execute_IL(CLR_RT_StackFrame &stackArg) #endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) #if defined(NANOCLR_TRACE_EXCEPTIONS) && defined(VIRTUAL_DEVICE) - if (s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) { CLR_PROF_HANDLER_SUSPEND_TIME(); diff --git a/src/CLR/Include/nanoCLR_Runtime.h b/src/CLR/Include/nanoCLR_Runtime.h index 3086011eb8..bb54848008 100644 --- a/src/CLR/Include/nanoCLR_Runtime.h +++ b/src/CLR/Include/nanoCLR_Runtime.h @@ -3454,13 +3454,16 @@ struct CLR_RT_ExecutionEngine c_fDebugger_StateProgramRunning + c_fDebugger_StateProgramExited + c_fDebugger_StateResolutionFailed; // static const int c_fDebugger_BreakpointsDisabled = 0x00001000; - // - static const int c_fDebugger_Quiet = 0x00010000; // Do not spew debug text to the debugger + // Do not spew debug text to the debugger + static const int c_fDebugger_Quiet = 0x00010000; static const int c_fDebugger_ExitPending = 0x00020000; - // - static const int c_fDebugger_PauseTimers = - 0x04000000; // Threads associated with timers are created in "suspended" mode. - static const int c_fDebugger_NoCompaction = 0x08000000; // Don't perform compaction during execution. + + // Execution engine won't process stack trace when an exception occurs. + static const int c_fDebugger_NoStackTraceInExceptions = 0x02000000; + // Threads associated with timers are created in "suspended" mode. + static const int c_fDebugger_PauseTimers = 0x04000000; + // Don't perform compaction during execution. + static const int c_fDebugger_NoCompaction = 0x08000000; // static const int c_fDebugger_SourceLevelDebugging = 0x10000000; static const int c_fDebugger_RebootPending = 0x20000000; From 149676fde5fdfcccecba4503a2080b3b25b03bea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 6 Jun 2023 09:55:45 +0100 Subject: [PATCH 413/572] Fix path for build info - Now is in the build folder. - https://github.com/Skyworks-Timing-Software/MCU/issues/81#issuecomment-1577243200_ --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 4 ++-- .github/workflows/Build_SKY_EEVB_Release.yaml | 4 ++-- .github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml | 4 ++-- .github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml | 4 ++-- .github/workflows/build_skyworks_evb.yml.template | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index 3bbe9f9407..d1358133e4 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -88,7 +88,7 @@ jobs: - name: Collect metadata run: | - $file = "${{ github.workspace }}/build-info.txt" + $file = "${{ github.workspace }}/build/build-info.txt" $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine @@ -106,7 +106,7 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build-info.txt + ${{ github.workspace }}/build/build-info.txt - name: Tag the build if: ${{ github.event.pull_request.number == 'null' }} diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Build_SKY_EEVB_Release.yaml index cf5c89df18..e47e90f366 100644 --- a/.github/workflows/Build_SKY_EEVB_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_Release.yaml @@ -88,7 +88,7 @@ jobs: - name: Collect metadata run: | - $file = "${{ github.workspace }}/build-info.txt" + $file = "${{ github.workspace }}/build/build-info.txt" $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine @@ -106,7 +106,7 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build-info.txt + ${{ github.workspace }}/build/build-info.txt - name: Tag the build if: ${{ github.event.pull_request.number == 'null' }} diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml index 6c05f959b1..350fda4b92 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -88,7 +88,7 @@ jobs: - name: Collect metadata run: | - $file = "${{ github.workspace }}/build-info.txt" + $file = "${{ github.workspace }}/build/build-info.txt" $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine @@ -106,7 +106,7 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build-info.txt + ${{ github.workspace }}/build/build-info.txt - name: Tag the build if: ${{ github.event.pull_request.number == 'null' }} diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml index 73068bb67b..fe482ccd4f 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -88,7 +88,7 @@ jobs: - name: Collect metadata run: | - $file = "${{ github.workspace }}/build-info.txt" + $file = "${{ github.workspace }}/build/build-info.txt" $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine @@ -106,7 +106,7 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build-info.txt + ${{ github.workspace }}/build/build-info.txt - name: Tag the build if: ${{ github.event.pull_request.number == 'null' }} diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index a5a07cd94c..12af1c955d 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -88,7 +88,7 @@ jobs: - name: Collect metadata run: | - $file = "${{ github.workspace }}/build-info.txt" + $file = "${{ github.workspace }}/build/build-info.txt" $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine @@ -106,7 +106,7 @@ jobs: path: | ${{ github.workspace }}/build/*.bin ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build-info.txt + ${{ github.workspace }}/build/build-info.txt - name: Tag the build if: ${{ github.event.pull_request.number == 'null' }} From 0decdef5067b02305a8be0e5ff104a61e7954511 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Tue, 6 Jun 2023 15:32:41 +0100 Subject: [PATCH 414/572] Move to github actions workflow (#5) [skip ci] --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 119 +---------------- .github/workflows/Build_SKY_EEVB_Release.yaml | 119 +---------------- .../Build_SKY_EEVB_STD_SIF_Debug.yaml | 121 +---------------- .../Build_SKY_EEVB_STD_SIF_Release.yaml | 121 +---------------- .../workflows/build_skyworks_evb.yml.template | 119 +---------------- .github/workflows/skyworks_evb_build.yaml | 126 ++++++++++++++++++ 6 files changed, 148 insertions(+), 577 deletions(-) create mode 100644 .github/workflows/skyworks_evb_build.yaml diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index d1358133e4..0718f262a8 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -5,118 +5,7 @@ on: jobs: build_SKY_EEVB: - runs-on: windows-latest - - env: - TARGET_NAME: 'SKY_EEVB_Debug' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - name: Collect metadata - run: | - $file = "${{ github.workspace }}/build/build-info.txt" - - $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine - $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine - $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine - $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine - $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine - $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine - $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine - - $metadata | Out-File -FilePath $file -Encoding utf-8 -Append - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build/build-info.txt - - - name: Tag the build - if: ${{ github.event.pull_request.number == 'null' }} - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) + name: Build SKY_EEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_Debug' diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Build_SKY_EEVB_Release.yaml index e47e90f366..7fdc5252b2 100644 --- a/.github/workflows/Build_SKY_EEVB_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_Release.yaml @@ -5,118 +5,7 @@ on: jobs: build_SKY_EEVB: - runs-on: windows-latest - - env: - TARGET_NAME: 'SKY_EEVB_Release' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - name: Collect metadata - run: | - $file = "${{ github.workspace }}/build/build-info.txt" - - $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine - $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine - $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine - $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine - $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine - $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine - $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine - - $metadata | Out-File -FilePath $file -Encoding utf-8 -Append - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build/build-info.txt - - - name: Tag the build - if: ${{ github.event.pull_request.number == 'null' }} - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) + name: Build SKY_EEVB_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_Release' diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml index 350fda4b92..b0132c3bab 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -4,119 +4,8 @@ on: workflow_dispatch jobs: - build_SKY_EEVB_STD_SIF: - runs-on: windows-latest - - env: - TARGET_NAME: 'SKY_EEVB_STD_SIF_Debug' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - name: Collect metadata - run: | - $file = "${{ github.workspace }}/build/build-info.txt" - - $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine - $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine - $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine - $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine - $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine - $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine - $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine - - $metadata | Out-File -FilePath $file -Encoding utf-8 -Append - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build/build-info.txt - - - name: Tag the build - if: ${{ github.event.pull_request.number == 'null' }} - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) + build_SKY_EEVB: + name: Build SKY_EEVB_STD_SIF_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_STD_SIF_Debug' diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml index fe482ccd4f..c8cc4ff60b 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -4,119 +4,8 @@ on: workflow_dispatch jobs: - build_SKY_EEVB_STD_SIF: - runs-on: windows-latest - - env: - TARGET_NAME: 'SKY_EEVB_STD_SIF_Release' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - name: Collect metadata - run: | - $file = "${{ github.workspace }}/build/build-info.txt" - - $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine - $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine - $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine - $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine - $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine - $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine - $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine - - $metadata | Out-File -FilePath $file -Encoding utf-8 -Append - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build/build-info.txt - - - name: Tag the build - if: ${{ github.event.pull_request.number == 'null' }} - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) + build_SKY_EEVB: + name: Build SKY_EEVB_STD_SIF_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_STD_SIF_Release' diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index 12af1c955d..411d7955ab 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -5,118 +5,7 @@ on: jobs: build_@PRESET@: - runs-on: windows-latest - - env: - TARGET_NAME: '@PRESET@' - - steps: - - uses: actions/checkout@v3 - with: - fetch-depth: 0 - ref: 'skyworks-evb' - submodules: true - - - uses: lukka/get-cmake@latest - - - name: Install SRecord - run: | - $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" - $output = "${{ runner.temp }}\srecord.zip" - - "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # Stop security tripping us up - [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" - - # download zip with Ninja tool - (New-Object Net.WebClient).DownloadFile($url, $output) - - "OK" | Write-Host -ForegroundColor Green - - "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline - - # unzip tool - Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null - - "OK" | Write-Host -ForegroundColor Green - - $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') - - echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - - - name: Install arm-none-eabi-gcc - uses: carlosperate/arm-none-eabi-gcc-action@v1 - with: - release: '12.2.Rel1' - - - name: Tweak GCC path - run: | - $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" - if($currentPath.EndsWith("bin")) - { - $fixedPath = $currentPath.Replace("\bin", "") - - echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - } - - - name: Rename CMake presets - working-directory: ${{ github.workspace }}/config - run: | - $file = "user-tools-repos.json" - Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file - - [regex]$pattern='user-tools-repos-cloud' - $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - - $file = "user-prefs.json" - Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - - $filecontent = Get-Content($file) - attrib $file -r - $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 - - - run: nbgv cloud -a -c - - - uses: lukka/run-cmake@v10 - with: - configurePreset: '${{ env.TARGET_NAME }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - buildPreset: '${{ env.TARGET_NAME }}' - buildPresetAdditionalArgs: "['--config MinSizeRel']" - - - name: Collect metadata - run: | - $file = "${{ github.workspace }}/build/build-info.txt" - - $metadata += "Target: ${{ env.TARGET_NAME }}" + [Environment]::NewLine - $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine - $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine - $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine - $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine - $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine - $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine - - $metadata | Out-File -FilePath $file -Encoding utf-8 -Append - - - uses: actions/upload-artifact@v3 - with: - name: '${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' - path: | - ${{ github.workspace }}/build/*.bin - ${{ github.workspace }}/build/*.hex - ${{ github.workspace }}/build/build-info.txt - - - name: Tag the build - if: ${{ github.event.pull_request.number == 'null' }} - uses: actions/github-script@v6 - with: - script: | - const {DIST_VERSION} = process.env - github.rest.git.createRef({ - owner: context.repo.owner, - repo: context.repo.repo, - ref: 'refs/tags/${{ env.TARGET_NAME }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', - sha: context.sha - }) + name: Build @PRESET@ + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: '@PRESET@' diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml new file mode 100644 index 0000000000..fd938e06cf --- /dev/null +++ b/.github/workflows/skyworks_evb_build.yaml @@ -0,0 +1,126 @@ +name: Skyworks .NET nanoFramework target build +run-name: Workflow for Skyworks .NET nanoFramework target build + +on: + workflow_call: + inputs: + targetName: + required: true + type: string + +jobs: + build-skyworks-target: + name: Build Skyworks target + timeout-minutes: 15 + runs-on: windows-latest + + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + ref: 'skyworks-evb' + submodules: true + + - uses: lukka/get-cmake@latest + + - name: Install SRecord + run: | + $url = "https://dl.cloudsmith.io/public/net-nanoframework/internal-build-tools/raw/names/srecord-win32/versions/latest/srecord-1.64-win32.zip" + $output = "${{ runner.temp }}\srecord.zip" + + "Downloading SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + "OK" | Write-Host -ForegroundColor Green + + "Installing SRecord..." | Write-Host -ForegroundColor White -NoNewline + + # unzip tool + Expand-Archive $output -DestinationPath ${{ runner.temp }}\srecord > $null + + "OK" | Write-Host -ForegroundColor Green + + $srecPath = "${{ runner.temp }}\srecord".Replace('\', '/') + + echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + + - name: Install arm-none-eabi-gcc + uses: carlosperate/arm-none-eabi-gcc-action@v1 + with: + release: '12.2.Rel1' + + - name: Tweak GCC path + run: | + $currentPath = "$env:ARM_NONE_EABI_GCC_PATH" + if($currentPath.EndsWith("bin")) + { + $fixedPath = $currentPath.Replace("\bin", "") + + echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + } + + - name: Rename CMake presets + working-directory: ${{ github.workspace }}/config + run: | + $file = "user-tools-repos.json" + Rename-Item -Path "user-tools-repos.TEMPLATE.json" -NewName $file + + [regex]$pattern='user-tools-repos-cloud' + $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 + + $file = "user-prefs.json" + Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file + + $filecontent = Get-Content($file) + attrib $file -r + $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 + + - run: nbgv cloud -a -c + + - uses: lukka/run-cmake@v10 + with: + configurePreset: '${{ inputs.targetName }}' + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + buildPreset: '${{ inputs.targetName }}' + buildPresetAdditionalArgs: "['--config MinSizeRel']" + + - name: Collect metadata + run: | + $file = "${{ github.workspace }}/build/build-info.txt" + + $metadata += "Target: ${{ inputs.targetName }}" + [Environment]::NewLine + $metadata += "Version: ${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}" + [Environment]::NewLine + $metadata += "Build date: $(Get-Date -Format 'yyyy-MM-dd HH:mm:ss')" + [Environment]::NewLine + $metadata += "Commit: ${{ github.sha }}" + [Environment]::NewLine + $metadata += "Branch: ${{ github.ref }}" + [Environment]::NewLine + $metadata += "Workflow: ${{ github.workflow }}" + [Environment]::NewLine + $metadata += "Repository: ${{ github.repository }}" + [Environment]::NewLine + + $metadata | Out-File -FilePath $file -Encoding utf-8 -Append + + - uses: actions/upload-artifact@v3 + with: + name: '${{ inputs.targetName }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' + path: | + ${{ github.workspace }}/build/*.bin + ${{ github.workspace }}/build/*.hex + ${{ github.workspace }}/build/build-info.txt + + - name: Tag the build + if: ${{ github.event.pull_request.number == 'null' }} + uses: actions/github-script@v6 + with: + script: | + const {DIST_VERSION} = process.env + github.rest.git.createRef({ + owner: context.repo.owner, + repo: context.repo.repo, + ref: 'refs/tags/${{ inputs.targetName }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}', + sha: context.sha + }) From 3713a4d1e60a650fa3d0af39a61885e1f71ac511 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 16 Jun 2023 14:26:29 +0100 Subject: [PATCH 415/572] Fix Events_SetBoolTimer for Azure RTOS - Timer change was being called with the wrong parameters. --- targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp b/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp index 670fd50311..551806fe7b 100644 --- a/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp +++ b/targets/AzureRTOS/_common/nanoCLR/targetPAL_Events.cpp @@ -51,7 +51,7 @@ void Events_SetBoolTimer(bool *timerCompleteFlag, uint32_t millisecondsFromNow) // need to stop the timer first tx_timer_deactivate(&boolEventsTimer); - tx_timer_change(&boolEventsTimer, 0, TX_TICKS_PER_MILLISEC(millisecondsFromNow)); + tx_timer_change(&boolEventsTimer, TX_TICKS_PER_MILLISEC(millisecondsFromNow), 0); tx_timer_activate(&boolEventsTimer); } } From 5b7f5641f2c4ddaa251406914299b198b85ad7fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 22 Jun 2023 15:01:17 +0100 Subject: [PATCH 416/572] Migrate GEcko SDK to v4.3.0 - Update cmake. - Update code as needed. - Add dummy implementation of Gecko API call to fix issue causing hard fault. --- CMake/Modules/FindGecko_SDK.cmake | 2 ++ targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- .../SiliconLabs/SL_STK3701A/nanoBooter/main.c | 2 +- .../autogen/sl_device_init_clocks_default.c | 8 ++++---- .../SiliconLabs/_common/sl_sleeptimer_.c | 16 ++++++++++++++++ 5 files changed, 24 insertions(+), 6 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index a84c7721ea..44562bf196 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -109,6 +109,8 @@ set(gecko_sdk_srcs sl_sleeptimer_hal_rtc.c sl_sleeptimer_hal_rtcc.c + sl_sleeptimer_.c + sl_slist.c sl_system_init.c sl_system_kernel.c diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index c1c82e0627..4e4ea6561c 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -70,7 +70,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.2.3") + set(GECKO_SDK_VERSION "v4.3.0") endif() if(NO_GECKO_SDK_SOURCE) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c index e208520885..45b18d583c 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoBooter/main.c @@ -207,7 +207,7 @@ int main(void) // there seems to be a valid CLR image // need to change HF clock to internal RCO so the CLR can boot smoothly - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + CMU_CLOCK_SELECT_SET(HF, HFRCO); // launch nanoCLR LaunchCLR((uint32_t)&__deployment_start__); diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c index 536bf44098..cfde392023 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_device_init_clocks_default.c @@ -17,13 +17,13 @@ __nfweak sl_status_t sl_device_init_clocks(void) CMU_ClockEnable(cmuClock_HFLE, true); CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO); - CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); + CMU_CLOCK_SELECT_SET(LFA, LFXO); + CMU_CLOCK_SELECT_SET(LFB, LFXO); #if defined(_CMU_LFCCLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFXO); + CMU_CLOCK_SELECT_SET(LFC, LFXO); #endif #if defined(_CMU_LFECLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); + CMU_CLOCK_SELECT_SET(LFE, LFXO); #endif return SL_STATUS_OK; diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c b/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c new file mode 100644 index 0000000000..5a21d6d920 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c @@ -0,0 +1,16 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// Need a strong implementation (despite empty) as this one is declared as WEAK in Gecko SDK which is causing +// issues when linking statically. +// Reported to Silabs here: +// (https://community.silabs.com/s/question/0D58Y0000AUTvt2SQD/declaration-of-slisleeptimersetpmemrequirement) + +#if !defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ +} +#endif From 5795805b77a0dc381c066bf816fb5bd765e4fee8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 22 Jun 2023 15:04:38 +0100 Subject: [PATCH 417/572] Code updates following migration to Gecko SDK 4.3.0 --- .../SKY_EVB/autogen/sl_device_init_clocks.c | 10 +++++----- .../SKY_EVB/config/sl_device_init_hfxo_config.h | 4 ++++ .../AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c | 2 +- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c index 91f07c2383..5e12163b4b 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c @@ -10,18 +10,18 @@ sl_status_t sl_device_init_clocks(void) { - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_USHFRCO); + CMU_CLOCK_SELECT_SET(HF, USHFRCO); CMU_ClockEnable(cmuClock_HFLE, true); CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO); - CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFRCO); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); #if defined(_CMU_LFCCLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFC, cmuSelect_LFRCO); + CMU_CLOCK_SELECT_SET(LFC, LFRCO); #endif #if defined(_CMU_LFECLKSEL_MASK) - CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); + CMU_CLOCK_SELECT_SET(LFE, LFRCO); #endif return SL_STATUS_OK; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h index ec442f5030..8f04091ef4 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h @@ -15,6 +15,10 @@ // Default: 50000000 #define SL_DEVICE_INIT_HFXO_FREQ 50000000 +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + // CTUNE <0-511> // Default: 360 #define SL_DEVICE_INIT_HFXO_CTUNE 132 diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c index b46688d09c..0787f4a6a5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c @@ -167,7 +167,7 @@ int main(void) // there seems to be a valid CLR image // need to change HF clock to internal RCO so the CLR can boot smoothly - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + CMU_CLOCK_SELECT_SET(HF, HFRCO); // launch nanoCLR LaunchCLR((uint32_t)&__deployment_start__); From c046a747bf2eaa2143a2cd78f8e43f222f5852ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Jun 2023 12:02:14 +0100 Subject: [PATCH 418/572] Add DebuggerIsConnected - Exposes this information through a function. --- src/HAL/Include/nanoHAL_v2.h | 1 + src/HAL/nanoHAL_SystemInformation.cpp | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/src/HAL/Include/nanoHAL_v2.h b/src/HAL/Include/nanoHAL_v2.h index dc92c9bf1b..5f800f7e28 100644 --- a/src/HAL/Include/nanoHAL_v2.h +++ b/src/HAL/Include/nanoHAL_v2.h @@ -224,6 +224,7 @@ extern "C" void CPU_SetPowerModePlatform(PowerLevel_type powerLevel); // target specific handler for power mode changes (may be empty) void CPU_SetPowerModeTarget(PowerLevel_type powerLevel); + bool DebuggerIsConnected(); #ifdef __cplusplus } diff --git a/src/HAL/nanoHAL_SystemInformation.cpp b/src/HAL/nanoHAL_SystemInformation.cpp index c7a1dde26e..4550ac7903 100644 --- a/src/HAL/nanoHAL_SystemInformation.cpp +++ b/src/HAL/nanoHAL_SystemInformation.cpp @@ -6,6 +6,9 @@ #include #include +#include + +extern CLR_RT_ExecutionEngine g_CLR_RT_ExecutionEngine; bool GetHalSystemInfo(HalSystemInfo &systemInfo) { @@ -59,3 +62,8 @@ bool Target_GetReleaseInfo(NFReleaseInfo &releaseInfo) hal_strlen_s(PLATFORMNAMESTRING)); return TRUE; // alternatively, return false if you didn't initialize the releaseInfo structure. } + +bool DebuggerIsConnected() +{ + return ((g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions & CLR_RT_ExecutionEngine::c_fDebugger_Enabled) != 0); +} From 2702c6b4ad2b1ff85721ddda9a95942932533cb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Jun 2023 12:16:32 +0100 Subject: [PATCH 419/572] Replace Gecko SDK sl_usbd_code with nano version - Copy from original source, hacking sl_usbd_core_add_interface(). --- CMake/Modules/FindGecko_SDK.cmake | 12 +- .../SiliconLabs/_common/nano_sl_usbd_core.c | 6142 +++++++++++++++++ 2 files changed, 6147 insertions(+), 7 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 44562bf196..2b9d1aef42 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -152,7 +152,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_class_hid.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) - list(APPEND gecko_sdk_srcs sl_usbd_core.c) + list(APPEND gecko_sdk_srcs nano_sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) list(APPEND gecko_sdk_srcs sl_usbd_class_hid_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) @@ -180,7 +180,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_class_cdc.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) - list(APPEND gecko_sdk_srcs sl_usbd_core.c) + list(APPEND gecko_sdk_srcs nano_sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_init.c) list(APPEND gecko_sdk_srcs sl_malloc.c) @@ -192,15 +192,14 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_class_vendor_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) + list(APPEND gecko_sdk_srcs nano_sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) - list(APPEND gecko_sdk_srcs sl_usbd_core.c) - list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) - # this one is our own implementation list(APPEND gecko_sdk_srcs nano_sl_usbd_class_vendor.c) + list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_init.c) list(APPEND gecko_sdk_srcs sl_malloc.c) - + endif() foreach(src_file ${gecko_sdk_srcs}) @@ -257,7 +256,6 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") endforeach() # unset this warning as error required for this source file - SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_core.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_core_ep.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc.c PROPERTIES COMPILE_FLAGS -Wno-undef) SET_SOURCE_FILES_PROPERTIES(${gecko_sdk_SOURCE_DIR}/protocol/usb/src/sl_usbd_class_cdc_acm.c PROPERTIES COMPILE_FLAGS -Wno-undef) diff --git a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c new file mode 100644 index 0000000000..a8742b5c7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c @@ -0,0 +1,6142 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// This is an extension to the original file from Gecko SDK v4.3.0 +// Following +// https://community.silabs.com/s/question/0D58Y0000AGPoMDSQ1/how-to-add-a-new-usb-interface-when-the-device-is-already-started +// We have to hack our way into this. Stopping the USB core is not a decent solution because it momentarily interrupts +// the USB connection, thus causing a debug session to be lost. +// The workaround is to skip the check for the USB Core being started. +// It was found that, despite its started state, it's OK to add an interface to the USB Core. + +// clang-format off + +/******************************************************************************************************** + ******************************************************************************************************** + * INCLUDE FILES + ******************************************************************************************************** + *******************************************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sl_bit.h" +#include "sl_status.h" +#include "sl_string.h" + +#include "em_core.h" + +#include "sl_usbd_device_config.h" +#include "sl_usbd_core_config.h" +#include "sl_usbd_core.h" + +#include "sli_usbd_core.h" +#include "sli_usbd_driver.h" + +#include + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL DEFINES + ******************************************************************************************************** + *******************************************************************************************************/ + +#define SLI_USBD_LOG_BUS_CH (USBD, BUS) + +/******************************************************************************************************** + * OBJECTS TOTAL NUMBER DEFINES + *******************************************************************************************************/ + +#define SLI_USBD_CONFIG_NBR_TOT (255u - 1u) +#define SLI_USBD_INTERFACE_NBR_TOT (255u - 1u) +#define SLI_USBD_ALT_INTERFACE_NBR_TOT (255u - 1u) +#define SLI_USBD_INTERFACE_GROUP_NBR_TOT (255u - 1u) +#define SLI_USBD_ENDPOINT_NBR_TOT (255u - 1u) + +/******************************************************************************************************** + * PROTOCOL DEFINES + * + * Note(s) : (1) The descriptor buffer is used to send the device, configuration and string descriptors. + * + * (a) The size of the descriptor buffer is set to 64 which is the maximum packet size + * allowed by the USB specification for FS and HS devices. + * + * (2) USB spec 2.0 (section 9.6.3), table 9-10 specify the bitmap for the configuration + * attributes. + * + * D7 Reserved (set to one) + * D6 Self-powered + * D5 Remote Wakeup + * D4..0 Reserved (reset to zero) + *******************************************************************************************************/ + +#define SLI_USBD_DESC_BUF_LEN 64u // See Note #1a. +#define SLI_USBD_ENDPOINT_CTRL_ALLOC (0x01u | 0x02u) // (BIT_00 | BIT_01) + +#define SLI_USBD_CONFIG_DESC_SELF_POWERED 0x40u // BIT_06 See Note #2. +#define SLI_USBD_CONFIG_DESC_REMOTE_WAKEUP 0x20u // BIT_05 +#define SLI_USBD_CONFIG_DESC_RSVD_SET 0x80u // BIT_07 + +// Microsoft Desc Define +#define SLI_USBD_MICROSOFT_DESC_COMPAT_ID_HDR_VER_1_0 0x0010u +#define SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_HDR_VER_1_0 0x000Au +#define SLI_USBD_MICROSOFT_DESC_VER_1_0 0x0100u + +#define SLI_USBD_MICROSOFT_STR_LEN 18u // Length of MS OS string. +#define SLI_USBD_MICROSOFT_STR_IX 0xEEu // Index of MS OS string. + +#define SLI_USBD_MICROSOFT_DESC_COMPAT_ID_HDR_LEN 16u +#define SLI_USBD_MICROSOFT_DESC_COMPAT_ID_SECTION_LEN 24u + +#define SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_HDR_LEN 10u +#define SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_SECTION_HDR_LEN 8u + +#define SLI_USBD_MICROSOFT_FEATURE_COMPAT_ID 0x0004u +#define SLI_USBD_MICROSOFT_FEATURE_EXT_PROPERTIES 0x0005u + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL CONSTANTS + * + * Note(s) : (1) For more information, see "Extended Compat id OS Feature Descriptor Specification", + * Appendix A, available at http://msdn.microsoft.com/en-us/windows/hardware/gg463179.aspx. + ******************************************************************************************************** + *******************************************************************************************************/ + +/******************************************************************************************************** + * DEFAULT CONFIGURATIONS + *******************************************************************************************************/ + +#if (USBD_CFG_MS_OS_DESC_EN == 1) +// Signature used in MS OS string desc. +static const char usbd_microsoft_signature_str[] = "MSFT100"; + +static const char usbd_microsoft_compat_id[][8u] = { + { 0u, 0u, 0u, 0u, 0u, 0u, 0u, 0u }, + { 'R', 'N', 'D', 'I', 'S', 0u, 0u, 0u }, + { 'P', 'T', 'P', 0u, 0u, 0u, 0u, 0u }, + { 'M', 'T', 'P', 0u, 0u, 0u, 0u, 0u }, + { 'X', 'U', 'S', 'B', '2', '0', 0u, 0u }, + { 'B', 'L', 'U', 'T', 'U', 'T', 'H', 0u }, + { 'W', 'I', 'N', 'U', 'S', 'B', 0u, 0u }, +}; + +static const char usbd_microsoft_subcompat_id[][8u] = { + { 0u, 0u, 0u, 0u, 0u, 0u, 0u, 0u }, + { '1', '1', 0u, 0u, 0u, 0u, 0u, 0u }, + { '1', '2', 0u, 0u, 0u, 0u, 0u, 0u }, + { 'E', 'D', 'R', 0u, 0u, 0u, 0u, 0u }, +}; +#endif + +/******************************************************************************************************** + ******************************************************************************************************** + * GLOBAL CONSTANTS + ******************************************************************************************************** + *******************************************************************************************************/ + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL GLOBAL VARIABLES + ******************************************************************************************************** + *******************************************************************************************************/ + +static sli_usbd_t usb_device; + +static uint32_t descriptor_buffer[SLI_USBD_DESC_BUF_LEN / 4u] = { 0 }; +static uint32_t ctrl_status_buffer = 0; + +sli_usbd_t *usbd_ptr = NULL; + +#if (SLI_USBD_CFG_DBG_STATS_EN == 1) +sl_usbd_debug_device_stats_t usbd_debug_stats_device; +sl_usbd_debug_endpoint_stats_t usbd_debug_stats_endpoint_table[32u]; +#endif + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL FUNCTION PROTOTYPES + ******************************************************************************************************** + *******************************************************************************************************/ + +static sl_status_t usbd_core_add_device(void); + +// Standard Request Handlers +static void usbd_core_stdreq_handler(sli_usbd_device_t *p_dev); + +static bool usbd_core_device_stdreq(sli_usbd_device_t *p_dev, + uint8_t request); + +static bool usbd_core_interface_stdreq(sli_usbd_device_t *p_dev, + uint8_t request); + +static bool usbd_core_endpoint_stdreq(const sli_usbd_device_t *p_dev, + uint8_t request); + +static bool usbd_core_class_stdreq(const sli_usbd_device_t *p_dev); + +static bool usbd_core_vendor_stdreq(const sli_usbd_device_t *p_dev); + +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static bool usbd_core_microsoft_device_stdreq(const sli_usbd_device_t *p_dev); + +static bool usbd_core_microsoft_interface_stdreq(const sli_usbd_device_t *p_dev); + +static bool usbd_core_microsoft_ext_property_stdreq(const sli_usbd_device_t *p_dev, + sli_usbd_configuration_t *p_config, + uint8_t if_nbr, + uint16_t len); +#endif + +static bool usbd_core_get_descriptor_stdreq(sli_usbd_device_t *p_dev); + +static void usbd_core_unset_configuration(sli_usbd_device_t *p_dev); + +static sl_status_t usbd_core_set_configuration(sli_usbd_device_t *p_dev, + uint8_t config_nbr); + +static sl_status_t usbd_core_send_device_descriptor(sli_usbd_device_t *p_dev, + bool other, + uint16_t req_len); + +static sl_status_t usbd_core_send_configuration_descriptor(sli_usbd_device_t *p_dev, + uint8_t config_nbr, + bool other, + uint16_t req_len); + +#if (USBD_CFG_STR_EN == 1) +static sl_status_t usbd_core_send_string_descriptor(sli_usbd_device_t *p_dev, + uint8_t str_ix, + uint16_t req_len); + +static sl_status_t usbd_core_add_string(sli_usbd_device_t *p_dev, + const char *p_str); + +static uint8_t usbd_core_get_string_index(const sli_usbd_device_t *p_dev, + const char *p_str); + +static const char *usbd_core_get_string_descriptor(const sli_usbd_device_t *p_dev, + uint8_t str_nbr); +#endif + +static void usbd_core_start_descriptor_write(sli_usbd_device_t *p_dev, + uint16_t req_len); + +static sl_status_t usbd_core_stop_descriptor_write(sli_usbd_device_t *p_dev); + +static void usbd_core_write_08b_to_descriptor_buf(sli_usbd_device_t *p_dev, + uint8_t val); + +static void usbd_core_write_16b_to_descriptor_buf(sli_usbd_device_t *p_dev, + uint16_t val); + +static void usbd_core_write_to_descriptor_buf(sli_usbd_device_t *p_dev, + const uint8_t *p_buf, + uint16_t len); + +// USB Object Functions +static sli_usbd_configuration_t *usbd_core_get_configuration_structure(const sli_usbd_device_t *p_dev, + uint8_t config_nbr); + +static sli_usbd_interface_t *usbd_core_get_interface_structure(const sli_usbd_configuration_t *p_config, + uint8_t if_nbr); + +static sli_usbd_alt_interface_t *usbd_core_get_alt_interface_structure(const sli_usbd_interface_t *p_if, + uint8_t if_alt_nbr); + +static sl_status_t usbd_core_open_alt_interface(sli_usbd_device_t *p_dev, + uint8_t if_nbr, + const sli_usbd_alt_interface_t *p_if_alt); + +static void usbd_core_close_alt_interface(sli_usbd_device_t *p_dev, + const sli_usbd_alt_interface_t *p_if_alt); + +static sli_usbd_interface_group_t *usbd_core_get_interface_group_structure(const sli_usbd_configuration_t *p_config, + uint8_t if_grp_nbr); + +static void usbd_core_set_event(sli_usbd_event_code_t event); + +static void usbd_core_process_event(sli_usbd_device_t *p_dev, + sli_usbd_event_code_t event); + +static sl_status_t usbd_core_add_endpoint(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + uint8_t attrib, + bool dir_in, + uint16_t max_pkt_len, + uint8_t interval, + uint8_t *p_ep_addr); + +static sl_status_t usbd_core_allocate_endpoint(sl_usbd_device_speed_t spd, + uint8_t type, + bool dir_in, + uint16_t max_pkt_len, + uint8_t if_alt_nbr, + sli_usbd_endpoint_info_t *p_ep, + uint32_t *p_alloc_bit_map, + bool *p_alloc); + +/******************************************************************************************************** + ******************************************************************************************************** + * GLOBAL FUNCTIONS + ******************************************************************************************************** + *******************************************************************************************************/ + +/****************************************************************************************************//** + * Initializes the USB device stack + *******************************************************************************************************/ +sl_status_t sl_usbd_core_init(void) +{ + sli_usbd_t *p_usbd; + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + sli_usbd_interface_group_t *p_if_grp; + sli_usbd_endpoint_info_t *p_ep; + uint16_t tbl_ix; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + p_usbd = &usb_device; + + p_usbd->config_nbr_next = SL_USBD_CONFIGURATION_QUANTITY; + p_usbd->interface_next = SL_USBD_INTERFACE_QUANTITY; + p_usbd->alt_interface_nbr_next = SL_USBD_ALT_INTERFACE_QUANTITY; +#if (SL_USBD_INTERFACE_GROUP_QUANTITY > 0) + p_usbd->interface_group_nbr_next = SL_USBD_INTERFACE_GROUP_QUANTITY; +#endif + p_usbd->endpoint_info_nbr_next = SL_USBD_DESCRIPTOR_QUANTITY; + p_usbd->std_req_timeout_ms = 5000u; + + CORE_ENTER_ATOMIC(); + usbd_ptr = p_usbd; + CORE_EXIT_ATOMIC(); + + // Device Initialization + p_dev = &usbd_ptr->device; + // Default dev addr. + p_dev->address = 0u; + p_dev->state = SL_USBD_DEVICE_STATE_NONE; + p_dev->state_prev = SL_USBD_DEVICE_STATE_NONE; + p_dev->conn_status = false; + p_dev->speed = SL_USBD_DEVICE_SPEED_INVALID; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + // Init HS & FS cfg list + memset(p_dev->config_fs_speed_table_ptrs, 0, sizeof(sli_usbd_configuration_t *) * SL_USBD_CONFIGURATION_QUANTITY); +#if (USBD_CFG_HS_EN == 1) + memset(p_dev->config_hs_speed_table_ptrs, 0, sizeof(sli_usbd_configuration_t *) * SL_USBD_CONFIGURATION_QUANTITY); +#endif + +#else + // linked-list implementation. + p_dev->config_fs_head_ptr = NULL; + p_dev->config_fs_tail_ptr = NULL; +#if (USBD_CFG_HS_EN == 1) + p_dev->config_hs_head_ptr = NULL; + p_dev->config_hs_tail_ptr = NULL; +#endif +#endif + + p_dev->config_cur_ptr = NULL; + p_dev->config_cur_nbr = SL_USBD_CONFIG_NBR_NONE; + p_dev->config_fs_total_nbr = 0u; +#if (USBD_CFG_HS_EN == 1) + p_dev->config_hs_total_nbr = 0u; +#endif + + memset(p_dev->endpoint_interface_table, 0, (SL_USBD_ENDPOINT_MAX_NBR * (sizeof(uint8_t)))); + + // Alloc desc buf from heap. + p_dev->desc_buf_ptr = (uint8_t *)descriptor_buffer; + if (p_dev->desc_buf_ptr == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + memset(p_dev->desc_buf_ptr, 0, SLI_USBD_DESC_BUF_LEN); + + // Alloc ctrl status buf from heap. + p_dev->ctrl_status_buf_ptr = (uint8_t *)&ctrl_status_buffer; + if (p_dev->ctrl_status_buf_ptr == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + p_dev->actual_buf_ptr = p_dev->desc_buf_ptr; + p_dev->desc_buf_index = 0u; + p_dev->desc_buf_req_len = 0u; + p_dev->desc_buf_max_len = SLI_USBD_DESC_BUF_LEN; + p_dev->desc_buf_status_ptr = NULL; + +#if (SL_USBD_STRING_QUANTITY > 0) + memset(p_dev->str_descriptor_table, 0, SL_USBD_STRING_QUANTITY * sizeof(char *)); + p_dev->str_max_index = 0u; +#endif +#if (USBD_CFG_MS_OS_DESC_EN == 1) + p_dev->str_microsoft_vendor_code = 0u; +#endif + + memset(&p_dev->setup_req, 0, sizeof(sl_usbd_setup_req_t)); + + memset(&p_dev->setup_req_next, 0, sizeof(sl_usbd_setup_req_t)); + + p_dev->endpoint_max_ctrl_pkt_size = 0u; + p_dev->endpoint_max_phy_nbr = 0u; + + memset(p_dev->endpoint_interface_table, SL_USBD_INTERFACE_NBR_NONE, SL_USBD_ENDPOINT_MAX_NBR); + + p_dev->self_power = false; + p_dev->remote_wakeup = 0u; + + SLI_USBD_DBG_STATS_DEV_RESET(); + + // Configuration Table Initialization + for (tbl_ix = 0u; tbl_ix < SL_USBD_CONFIGURATION_QUANTITY; tbl_ix++) { + p_config = &usbd_ptr->config_table[tbl_ix]; + p_config->attrib = 0x00u; + p_config->max_power = 0u; + p_config->desc_len = 0u; + +#if (USBD_CFG_STR_EN == 1) + p_config->name_ptr = NULL; +#endif + +// Init IF list +#if (USBD_CFG_OPTIMIZE_SPD == 1) + // array implementation. + memset(p_config->interface_table_ptrs, 0, sizeof(sli_usbd_interface_t *) * SL_USBD_INTERFACE_QUANTITY); + +#if (SL_USBD_INTERFACE_GROUP_QUANTITY > 0u) + memset(p_config->interface_group_table_ptrs, 0, sizeof(sli_usbd_interface_group_t*) * SL_USBD_INTERFACE_GROUP_QUANTITY); +#endif +#else + // linked-list implementation. + p_config->interface_head_ptr = NULL; + p_config->interface_tail_ptr = NULL; + p_config->interface_group_head_ptr = NULL; + p_config->interface_group_tail_ptr = NULL; + p_config->next_ptr = NULL; +#endif + p_config->interface_nbr_total = 0u; + p_config->interface_group_nbr_total = 0u; + p_config->endpoint_alloc_map = 0x00u; +#if (USBD_CFG_HS_EN == 1) + p_config->config_other_speed = SL_USBD_CONFIG_NBR_NONE; +#endif + } + // Interface Table Initialization + for (tbl_ix = 0u; tbl_ix < SL_USBD_INTERFACE_QUANTITY; tbl_ix++) { + p_if = &usbd_ptr->interface_table[tbl_ix]; + p_if->class_code = SL_USBD_CLASS_CODE_USE_IF_DESC; + p_if->class_sub_code = SL_USBD_SUBCLASS_CODE_USE_IF_DESC; + p_if->class_protocol_code = SL_USBD_PROTOCOL_CODE_USE_IF_DESC; + p_if->class_driver_ptr = NULL; + p_if->class_arg_ptr = NULL; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + memset(p_if->alt_table_ptrs, 0, sizeof(sli_usbd_alt_interface_t *) * SL_USBD_ALT_INTERFACE_QUANTITY); +#else + p_if->alt_head_ptr = NULL; + p_if->alt_tail_ptr = NULL; +#endif + p_if->alt_cur_ptr = NULL; + p_if->alt_cur = SL_USBD_ALT_INTERFACE_NBR_NONE; + p_if->alt_nbr_total = 0u; + p_if->group_nbr = SL_USBD_INTERFACE_GROUP_NBR_NONE; + p_if->endpoint_alloc_map = 0x00u; +#if (USBD_CFG_OPTIMIZE_SPD == 0) + p_if->next_ptr = NULL; +#endif + } + // Alternate Settings Table Initialization + for (tbl_ix = 0u; tbl_ix < SL_USBD_ALT_INTERFACE_QUANTITY; tbl_ix++) { + p_if_alt = &usbd_ptr->alt_interface_table[tbl_ix]; + p_if_alt->class_arg_ptr = NULL; + p_if_alt->endpoint_alloc_map = 0x00u; + p_if_alt->endpoint_nbr_total = 0u; +#if (USBD_CFG_STR_EN == 1) + p_if_alt->name_ptr = NULL; +#endif +#if (USBD_CFG_OPTIMIZE_SPD == 0) + p_if_alt->next_ptr = NULL; +#endif +#if (USBD_CFG_OPTIMIZE_SPD == 1) + memset(p_if_alt->endpoint_table_ptrs, 0, SL_USBD_ENDPOINT_MAX_NBR * sizeof(sli_usbd_endpoint_info_t *)); + p_if_alt->endpoint_table_map = 0u; +#else + p_if_alt->endpoint_head_ptr = NULL; + p_if_alt->endpoint_tail_ptr = NULL; +#endif + } + +#if (SL_USBD_INTERFACE_GROUP_QUANTITY > 0u) + // Interface Group Table Initialization + for (tbl_ix = 0u; tbl_ix < SL_USBD_INTERFACE_GROUP_QUANTITY; tbl_ix++) { + p_if_grp = &usbd_ptr->interface_group_table[tbl_ix]; + p_if_grp->class_code = SL_USBD_CLASS_CODE_USE_IF_DESC; + p_if_grp->class_sub_code = SL_USBD_SUBCLASS_CODE_USE_IF_DESC; + p_if_grp->class_protocol_code = SL_USBD_PROTOCOL_CODE_USE_IF_DESC; + p_if_grp->interface_start = SL_USBD_INTERFACE_NBR_NONE; + p_if_grp->interface_count = 0u; +#if (USBD_CFG_STR_EN == 1) + p_if_grp->name_ptr = NULL; +#endif +#if (USBD_CFG_OPTIMIZE_SPD == 0) + p_if_grp->next_ptr = NULL; +#endif + } +#endif + + // Endpoint Information Table Initialization + for (tbl_ix = 0u; tbl_ix < SL_USBD_DESCRIPTOR_QUANTITY; tbl_ix++) { + p_ep = &usbd_ptr->endpoint_info_table[tbl_ix]; + p_ep->address = SL_USBD_ENDPOINT_NBR_NONE; + p_ep->attrib = 0x00u; + p_ep->interval = 0u; + // Default sync addr is zero. + p_ep->sync_addr = 0u; + // Default feedback rate exponent is zero. + p_ep->sync_refresh = 0u; +#if (USBD_CFG_OPTIMIZE_SPD == 0) + p_ep->next_ptr = NULL; +#endif + } + +#if (USBD_CFG_STR_EN == 1) + usbd_ptr->str_quantity_per_device = SL_USBD_STRING_QUANTITY; +#endif + + status = sli_usbd_core_init_endpoint(); + if (status != SL_STATUS_OK) { + return status; + } + + status = usbd_core_add_device(); + if (status != SL_STATUS_OK) { + return status; + } + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Starts the device stack + *******************************************************************************************************/ +sl_status_t sl_usbd_core_start_device(void) +{ + sli_usbd_device_t *p_dev; + bool init; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Chk curr dev state. + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) + && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + return SL_STATUS_INVALID_STATE; + } + + init = false; + + // If dev not initialized, call dev drv 'Init()' function. + if (p_dev->state == SL_USBD_DEVICE_STATE_NONE) { + status = sli_usbd_driver_init(); + if (status != SL_STATUS_OK) { + return status; + } + + init = true; + } + + status = sli_usbd_driver_start(); + + if (init == true) { + CORE_ENTER_ATOMIC(); + p_dev->state = SL_USBD_DEVICE_STATE_INIT; + CORE_EXIT_ATOMIC(); + } + + return status; +} + +/****************************************************************************************************//** + * Stops the device stack + *******************************************************************************************************/ +sl_status_t sl_usbd_core_stop_device(void) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->state == SL_USBD_DEVICE_STATE_NONE) { + return SL_STATUS_INVALID_STATE; + } + + // Close curr cfg. + usbd_core_unset_configuration(p_dev); + status = sli_usbd_driver_stop(); + + CORE_ENTER_ATOMIC(); + // Re-init dev stack to 'INIT' state. + p_dev->state = SL_USBD_DEVICE_STATE_INIT; + p_dev->state_prev = SL_USBD_DEVICE_STATE_INIT; + p_dev->conn_status = false; + CORE_EXIT_ATOMIC(); + + return status; +} + +/****************************************************************************************************//** + * Adds a configuration attribute to the device + *******************************************************************************************************/ +sl_status_t sl_usbd_core_add_configuration(uint8_t attrib, + uint16_t max_pwr, + sl_usbd_device_speed_t spd, + const char *p_name, + uint8_t *p_cfg_nbr) +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + uint8_t config_tbl_ix; + uint8_t config_nbr; + sl_usbd_device_speed_t drv_spd; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + +#if (USBD_CFG_HS_EN == 0) + (void)&spd; + (void)&drv_spd; +#endif + + if (p_cfg_nbr == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk max pwr (see Note #1). + if (max_pwr > SL_USBD_MAX_BUS_PWR_LIMIT_mA) { + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Chk curr dev state. + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) + && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return SL_STATUS_INVALID_STATE; + } + +// Chk if dev supports high spd. +#if (USBD_CFG_HS_EN == 1) + sli_usbd_driver_get_speed(&drv_spd); + if ((drv_spd != SL_USBD_DEVICE_SPEED_HIGH) + && (spd == SL_USBD_DEVICE_SPEED_HIGH)) { + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } +#endif + + CORE_ENTER_ATOMIC(); + // Chk if cfg is avail. + if (usbd_ptr->config_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + config_tbl_ix = usbd_ptr->config_nbr_next - 1u; + +#if (USBD_CFG_HS_EN == 1) + // Add cfg to dev HS cfg. + if (spd == SL_USBD_DEVICE_SPEED_HIGH) { + config_nbr = p_dev->config_hs_total_nbr; + // Chk cfg limit. + if (config_nbr > SLI_USBD_CONFIG_NBR_TOT) { + CORE_EXIT_ATOMIC(); + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + p_dev->config_hs_total_nbr++; + } else { +#endif + // FS cfg. + config_nbr = p_dev->config_fs_total_nbr; + // Chk cfg limit. + if (config_nbr > SLI_USBD_CONFIG_NBR_TOT) { + CORE_EXIT_ATOMIC(); + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + p_dev->config_fs_total_nbr++; +#if (USBD_CFG_HS_EN == 1) +} +#endif + usbd_ptr->config_nbr_next--; + + // Configuration Structure Initialization + p_config = &usbd_ptr->config_table[config_tbl_ix]; + + // Link cfg into dev struct. +#if (USBD_CFG_OPTIMIZE_SPD == 1) + CORE_EXIT_ATOMIC(); + +#if (USBD_CFG_HS_EN == 1) + if (spd == SL_USBD_DEVICE_SPEED_HIGH) { + p_dev->config_hs_speed_table_ptrs[config_nbr] = p_config; + // Set spd bit in cfg nbr. + SL_SET_BIT(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT); + } else { +#endif + p_dev->config_fs_speed_table_ptrs[config_nbr] = p_config; +#if (USBD_CFG_HS_EN == 1) +} +#endif + +#else + p_config->next_ptr = NULL; + +#if (USBD_CFG_HS_EN == 1) + if (spd == SL_USBD_DEVICE_SPEED_HIGH) { + // Link cfg in HS list. + if (p_dev->config_hs_head_ptr == NULL) { + p_dev->config_hs_head_ptr = p_config; + p_dev->config_hs_tail_ptr = p_config; + } else { + p_dev->config_hs_tail_ptr->next_ptr = p_config; + p_dev->config_hs_tail_ptr = p_config; + } + // Set spd bit in cfg nbr. + SL_SET_BIT(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT); + } else { +#endif + // Link cfg in FS list. + if (p_dev->config_fs_head_ptr == NULL) { + p_dev->config_fs_head_ptr = p_config; + p_dev->config_fs_tail_ptr = p_config; + } else { + p_dev->config_fs_tail_ptr->next_ptr = p_config; + p_dev->config_fs_tail_ptr = p_config; + } +#if (USBD_CFG_HS_EN == 1) +} +#endif + CORE_EXIT_ATOMIC(); +#endif + +#if (USBD_CFG_STR_EN == 1) + p_config->name_ptr = p_name; +#endif + + p_config->attrib = attrib; + // Init EP alloc bitmap. + p_config->endpoint_alloc_map = SLI_USBD_ENDPOINT_CTRL_ALLOC; + p_config->max_power = max_pwr; + // Init cfg desc len. + p_config->desc_len = 0u; + +#if (USBD_CFG_STR_EN == 1) + // Add cfg string to dev. + status = usbd_core_add_string(p_dev, p_name); + if (status != SL_STATUS_OK) { + *p_cfg_nbr = SL_USBD_CONFIG_NBR_NONE; + return status; + } +#else + (void)&p_name; +#endif + + *p_cfg_nbr = config_nbr; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Associate a configuration with its alternative-speed counterpart + *******************************************************************************************************/ +#if (USBD_CFG_HS_EN == 1) +sl_status_t sl_usbd_core_associate_other_speed_configuration(uint8_t config_nbr, + uint8_t config_other) +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_configuration_t *p_config_other; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Chk curr dev state. + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) + && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + return SL_STATUS_INVALID_STATE; + } + + // Chk if both cfg are from same spd. + if (((config_nbr & SL_USBD_CONFIG_NBR_SPD_BIT) ^ (config_other & SL_USBD_CONFIG_NBR_SPD_BIT)) != SL_USBD_CONFIG_NBR_SPD_BIT) { + return SL_STATUS_INVALID_PARAMETER; + } + + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); + + if (p_config == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + p_config_other = usbd_core_get_configuration_structure(p_dev, config_other); + + if (p_config_other == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk if cfg already associated. + if (!((p_config->config_other_speed == SL_USBD_CONFIG_NBR_NONE) + && (p_config_other->config_other_speed == SL_USBD_CONFIG_NBR_NONE))) { + return SL_STATUS_INVALID_PARAMETER; + } + + p_config->config_other_speed = config_other; + p_config_other->config_other_speed = config_nbr; + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * Gets the current device state + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_device_state(sl_usbd_device_state_t *p_dev_state) +{ + sli_usbd_device_t *p_dev; + + if (p_dev_state == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + *p_dev_state = p_dev->state; + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Get device speed + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_device_speed(sl_usbd_device_speed_t *p_dev_speed) +{ + sli_usbd_device_t *p_dev; + + if (p_dev_speed == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->state == SL_USBD_DEVICE_STATE_NONE) { + *p_dev_speed = SL_USBD_DEVICE_SPEED_INVALID; + return SL_STATUS_INVALID_STATE; + } + + *p_dev_speed = p_dev->speed; + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Sets the device's current power source + *******************************************************************************************************/ +sl_status_t sl_usbd_core_set_device_self_power(bool self_pwr) +{ + sli_usbd_device_t *p_dev; + CORE_DECLARE_IRQ_STATE; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + CORE_ENTER_ATOMIC(); + p_dev->self_power = self_pwr; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Set the device's Microsoft vendor code + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +sl_status_t sl_usbd_core_set_device_microsoft_vendor_code(uint8_t vendor_code) +{ + sli_usbd_device_t *p_dev; + CORE_DECLARE_IRQ_STATE; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + CORE_ENTER_ATOMIC(); + p_dev->str_microsoft_vendor_code = vendor_code; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * Get device configuration + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_device_configuration(sl_usbd_device_config_t **p_dev_cfg) +{ + sli_usbd_device_t *p_dev; + + if (p_dev_cfg == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + *p_dev_cfg = &p_dev->device_config; + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Gets the last frame number from the driver + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_device_frame_number(uint16_t *p_frame_nbr) +{ + sli_usbd_device_t *p_dev; + + if (p_frame_nbr == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->state == SL_USBD_DEVICE_STATE_NONE) { + *p_frame_nbr = 0; + return SL_STATUS_INVALID_STATE; + } + + sli_usbd_driver_get_frame_number(p_frame_nbr); + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Adds an interface to a specific configuration + *******************************************************************************************************/ +sl_status_t sl_usbd_core_add_interface(uint8_t cfg_nbr, + sl_usbd_class_driver_t *p_class_drv, + void *p_if_class_arg, + void *p_if_alt_class_arg, + uint8_t class_code, + uint8_t class_sub_code, + uint8_t class_protocol_code, + const char *p_name, + uint8_t *p_if_nbr) +{ + uint8_t if_tbl_ix; + uint8_t if_nbr; + uint8_t if_alt_nbr; + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + if (p_if_nbr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (p_class_drv == NULL) { + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_NULL_POINTER; + } + + // Chk if interface_descriptor() & interface_get_descriptor_size() are present or not. + if (!(((p_class_drv->interface_descriptor == NULL) && (p_class_drv->interface_get_descriptor_size == NULL)) + || ((p_class_drv->interface_descriptor != NULL) && (p_class_drv->interface_get_descriptor_size != NULL)))) { + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_NULL_POINTER; + } + + // Chk if endpoint_descriptor() & endpoint_get_descriptor_size() are present or not. + if (!(((p_class_drv->endpoint_descriptor == NULL) && (p_class_drv->endpoint_get_descriptor_size == NULL)) + || ((p_class_drv->endpoint_descriptor != NULL) && (p_class_drv->endpoint_get_descriptor_size != NULL)))) { + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_NULL_POINTER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + +// [NF_CHANGE] +// Chk curr dev state. +// { +// if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { +// *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; +// return SL_STATUS_INVALID_STATE; +// } +// [END_NF_CHANGE] + + // Get cfg struct. + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr); + + if (p_config == NULL) { + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + // Chk if IF struct is avail. + if (usbd_ptr->interface_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + if_tbl_ix = usbd_ptr->interface_next - 1u; + + // Chk if IF alt struct is avail. + if (usbd_ptr->alt_interface_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + if_alt_nbr = usbd_ptr->alt_interface_nbr_next - 1u; + + // Get next IF nbr in cfg. + if_nbr = p_config->interface_nbr_total; + // Chk IF limit. + if (if_nbr > SLI_USBD_INTERFACE_NBR_TOT) { + CORE_EXIT_ATOMIC(); + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + + usbd_ptr->interface_next--; + usbd_ptr->alt_interface_nbr_next--; + p_config->interface_nbr_total++; + + p_if = &usbd_ptr->interface_table[if_tbl_ix]; + // Get IF alt struct (see Note #1). + p_if_alt = &usbd_ptr->alt_interface_table[if_alt_nbr]; + + // Link IF and alt setting. +#if (USBD_CFG_OPTIMIZE_SPD == 1) + CORE_EXIT_ATOMIC(); + + p_config->interface_table_ptrs[if_nbr] = p_if; + p_if->alt_table_ptrs[0u] = p_if_alt; +#else + p_if->next_ptr = NULL; + p_if_alt->next_ptr = NULL; + p_if->alt_head_ptr = p_if_alt; + p_if->alt_tail_ptr = p_if_alt; + + if (p_config->interface_head_ptr == NULL) { + p_config->interface_head_ptr = p_if; + p_config->interface_tail_ptr = p_if; + } else { + p_config->interface_tail_ptr->next_ptr = p_if; + p_config->interface_tail_ptr = p_if; + } + CORE_EXIT_ATOMIC(); +#endif + + p_if->class_code = class_code; + p_if->class_sub_code = class_sub_code; + p_if->class_protocol_code = class_protocol_code; + p_if->class_driver_ptr = p_class_drv; + p_if->class_arg_ptr = p_if_class_arg; + p_if->endpoint_alloc_map = SLI_USBD_ENDPOINT_CTRL_ALLOC; + // Set curr alt setting. + p_if->alt_cur_ptr = p_if_alt; + p_if->alt_cur = 0u; + p_if->alt_nbr_total = 1u; + p_if_alt->endpoint_alloc_map = p_if->endpoint_alloc_map; + p_if_alt->class_arg_ptr = p_if_alt_class_arg; + +#if (USBD_CFG_STR_EN == 1) + p_if_alt->name_ptr = p_name; +#endif + + // Add IF string to dev. +#if (USBD_CFG_STR_EN == 1) + status = usbd_core_add_string(p_dev, p_name); + if (status != SL_STATUS_OK) { + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return status; + } +#else + (void)&p_name; +#endif + + *p_if_nbr = if_nbr; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Adds an alternate setting to a specific interface + *******************************************************************************************************/ +sl_status_t sl_usbd_core_add_alt_interface(uint8_t config_nbr, + uint8_t if_nbr, + void *p_class_arg, + const char *p_name, + uint8_t *p_if_alt_nbr) +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + uint8_t if_alt_tbl_ix; + uint8_t if_alt_nbr; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + if (p_if_alt_nbr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Get Object References + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Get config struct. + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); + + if (p_config == NULL) { + *p_if_alt_nbr = SL_USBD_ALT_INTERFACE_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get config struct. + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + + if (p_if == NULL) { + *p_if_alt_nbr = SL_USBD_ALT_INTERFACE_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + // Chk if next alt setting is avail. + if (usbd_ptr->alt_interface_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_if_alt_nbr = SL_USBD_ALT_INTERFACE_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + if_alt_tbl_ix = usbd_ptr->alt_interface_nbr_next - 1u; + + // Chk if alt setting is avail. + if_alt_nbr = p_if->alt_nbr_total; + if (if_alt_nbr > SLI_USBD_ALT_INTERFACE_NBR_TOT) { + CORE_EXIT_ATOMIC(); + *p_if_alt_nbr = SL_USBD_ALT_INTERFACE_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + + usbd_ptr->alt_interface_nbr_next--; + p_if->alt_nbr_total++; + + p_if_alt = &usbd_ptr->alt_interface_table[if_alt_tbl_ix]; + + // Add alt setting to IF. +#if (USBD_CFG_OPTIMIZE_SPD == 1) + CORE_EXIT_ATOMIC(); + + p_if->alt_table_ptrs[if_alt_nbr] = p_if_alt; +#else + p_if_alt->next_ptr = NULL; + + p_if->alt_tail_ptr->next_ptr = p_if_alt; + p_if->alt_tail_ptr = p_if_alt; + CORE_EXIT_ATOMIC(); +#endif + + p_if_alt->class_arg_ptr = p_class_arg; + p_if_alt->endpoint_alloc_map = SLI_USBD_ENDPOINT_CTRL_ALLOC; + +#if (USBD_CFG_STR_EN == 1) + p_if_alt->name_ptr = p_name; +#endif + + p_if_alt->endpoint_alloc_map &= ~p_if->endpoint_alloc_map; + p_if_alt->endpoint_alloc_map |= SLI_USBD_ENDPOINT_CTRL_ALLOC; + +#if (USBD_CFG_STR_EN == 1) + // Add alt setting string to dev. + status = usbd_core_add_string(p_dev, p_name); + if (status != SL_STATUS_OK) { + *p_if_alt_nbr = SL_USBD_ALT_INTERFACE_NBR_NONE; + return status; + } +#else + (void)&p_name; +#endif + + *p_if_alt_nbr = if_alt_nbr; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Creates an interface group + *******************************************************************************************************/ +sl_status_t sl_usbd_core_add_interface_group(uint8_t config_nbr, + uint8_t class_code, + uint8_t class_sub_code, + uint8_t class_protocol_code, + uint8_t if_start, + uint8_t if_cnt, + const char *p_name, + uint8_t *p_if_grp_num) +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_interface_group_t *p_if_grp; + uint8_t if_grp_tbl_ix; + uint8_t if_grp_nbr; + uint8_t if_nbr; + uint8_t if_end; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + if (p_if_grp_num == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (((uint16_t)(if_start) + (uint16_t)(if_cnt)) > (uint16_t)SLI_USBD_INTERFACE_NBR_TOT) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get Object References + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Get cfg struct. + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); + + if (p_config == NULL) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Verify that IFs do NOT belong to another group. + for (if_nbr = 0u; if_nbr < if_cnt; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr + if_start); + + if (p_if == NULL) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + if (p_if->group_nbr != SL_USBD_INTERFACE_GROUP_NBR_NONE) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_ALREADY_EXISTS; + } + } + + CORE_ENTER_ATOMIC(); + + // Chk if IF grp is avail. + if (usbd_ptr->interface_group_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + usbd_ptr->interface_group_nbr_next--; + if_grp_tbl_ix = usbd_ptr->interface_group_nbr_next; + + p_if_grp = &usbd_ptr->interface_group_table[if_grp_tbl_ix]; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + if_grp_nbr = p_config->interface_group_nbr_total; + p_config->interface_group_nbr_total++; + CORE_EXIT_ATOMIC(); + + p_config->interface_group_table_ptrs[if_grp_nbr] = p_if_grp; +#else + p_if_grp->next_ptr = NULL; + + if_grp_nbr = p_config->interface_group_nbr_total; + p_config->interface_group_nbr_total++; + + if (if_grp_nbr == 0u) { + p_config->interface_group_head_ptr = p_if_grp; + p_config->interface_group_tail_ptr = p_if_grp; + } else { + p_config->interface_group_tail_ptr->next_ptr = p_if_grp; + p_config->interface_group_tail_ptr = p_if_grp; + } + CORE_EXIT_ATOMIC(); +#endif + + p_if_grp->class_code = class_code; + p_if_grp->class_sub_code = class_sub_code; + p_if_grp->class_protocol_code = class_protocol_code; + p_if_grp->interface_start = if_start; + p_if_grp->interface_count = if_cnt; + +#if (USBD_CFG_STR_EN == 1) + p_if_grp->name_ptr = p_name; +#endif + + if_end = if_cnt + if_start; + for (if_nbr = if_start; if_nbr < if_end; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + + if (p_if == NULL) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + if (p_if->group_nbr != SL_USBD_INTERFACE_GROUP_NBR_NONE) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return SL_STATUS_ALREADY_EXISTS; + } + + CORE_ENTER_ATOMIC(); + p_if->group_nbr = if_grp_nbr; + CORE_EXIT_ATOMIC(); + } + +#if (USBD_CFG_STR_EN == 1) + // Add IF grp string to dev. + status = usbd_core_add_string(p_dev, p_name); + if (status != SL_STATUS_OK) { + *p_if_grp_num = SL_USBD_INTERFACE_GROUP_NBR_NONE; + return status; + } +#else + (void)&p_name; +#endif + + *p_if_grp_num = if_grp_nbr; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Gets the device descriptor + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_device_descriptor(uint8_t *p_buf, + uint8_t max_len, + uint8_t *p_desc_len) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + sl_status_t local_status; + + local_status = SL_STATUS_OK; + + if (p_desc_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (p_buf == NULL) { + *p_desc_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (max_len == 0) { + *p_desc_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->state != SL_USBD_DEVICE_STATE_NONE) { + *p_desc_len = 0; + return SL_STATUS_INVALID_STATE; + } + + p_dev->actual_buf_ptr = p_buf; + p_dev->desc_buf_max_len = max_len; + p_dev->desc_buf_status_ptr = &local_status; + + status = usbd_core_send_device_descriptor(p_dev, false, max_len); + + p_dev->desc_buf_status_ptr = NULL; + + *p_desc_len = p_dev->desc_buf_index; + return status; +} + +/****************************************************************************************************//** + * Gets a configuration descriptor + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_configuration_descriptor(uint8_t *p_buf, + uint16_t max_len, + uint8_t config_ix, + uint16_t *p_desc_len) +{ + sli_usbd_device_t *p_dev; + sl_status_t local_status; + sl_status_t status; + + local_status = SL_STATUS_OK; + + if (p_desc_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (p_buf == NULL) { + *p_desc_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (max_len == 0) { + *p_desc_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->state != SL_USBD_DEVICE_STATE_NONE) { + *p_desc_len = 0; + return SL_STATUS_INVALID_STATE; + } + + p_dev->actual_buf_ptr = p_buf; + p_dev->desc_buf_max_len = max_len; + p_dev->desc_buf_status_ptr = &local_status; + + status = usbd_core_send_configuration_descriptor(p_dev, config_ix, false, max_len); + + p_dev->desc_buf_status_ptr = NULL; + + *p_desc_len = p_dev->desc_buf_index; + return status; +} + +/****************************************************************************************************//** + * Get a string descriptor + *******************************************************************************************************/ +#if (USBD_CFG_STR_EN == 1) +sl_status_t sl_usbd_core_get_string_descriptor(uint8_t *p_buf, + uint8_t max_len, + uint8_t str_ix, + uint8_t *p_desc_len) +{ + sli_usbd_device_t *p_dev; + sl_status_t local_status; + sl_status_t status; + + local_status = SL_STATUS_OK; + + if (p_desc_len == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (p_buf == NULL) { + *p_desc_len = 0; + return SL_STATUS_NULL_POINTER; + } + + if (max_len == 0) { + *p_desc_len = 0; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->state != SL_USBD_DEVICE_STATE_NONE) { + *p_desc_len = 0; + return SL_STATUS_INVALID_STATE; + } + + p_dev->actual_buf_ptr = p_buf; + p_dev->desc_buf_max_len = max_len; + p_dev->desc_buf_status_ptr = &local_status; + + status = usbd_core_send_string_descriptor(p_dev, str_ix, max_len); + + p_dev->desc_buf_status_ptr = NULL; + + *p_desc_len = p_dev->desc_buf_index; + return status; +} +#endif + +/****************************************************************************************************//** + * Add string to USB device + *******************************************************************************************************/ +#if (USBD_CFG_STR_EN == 1) +sl_status_t sl_usbd_core_add_string(const char *p_str) +{ + sli_usbd_device_t *p_dev; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Chk curr dev state. + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) + && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + return SL_STATUS_INVALID_STATE; + } + + return usbd_core_add_string(p_dev, p_str); +} +#endif + +/****************************************************************************************************//** + * Get string index corresponding to a given string + *******************************************************************************************************/ +#if (USBD_CFG_STR_EN == 1) +sl_status_t sl_usbd_core_get_string_index(const char *p_str, + uint8_t *p_str_ix) +{ + sli_usbd_device_t *p_dev; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + *p_str_ix = usbd_core_get_string_index(p_dev, p_str); + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * Writes an 8-bit value to the descriptor buffer + *******************************************************************************************************/ +sl_status_t sl_usbd_core_write_08b_to_descriptor_buf(uint8_t val) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + status = *(p_dev->desc_buf_status_ptr); + + if (status == SL_STATUS_OK) { + usbd_core_write_to_descriptor_buf(p_dev, &val, 1u); + } + + return status; +} + +/****************************************************************************************************//** + * Writes a 16-bit value in the descriptor buffer + *******************************************************************************************************/ +sl_status_t sl_usbd_core_write_16b_to_descriptor_buf(uint16_t val) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + status = *(p_dev->desc_buf_status_ptr); + + if (status == SL_STATUS_OK) { + uint8_t buf[2u]; + + buf[0u] = (uint8_t)(val & 0xFFu); + buf[1u] = (uint8_t)((val >> 8u) & 0xFFu); + + usbd_core_write_to_descriptor_buf(p_dev, &buf[0u], 2u); + } + + return status; +} + +/****************************************************************************************************//** + * Writes a 24-bit value to the descriptor buffer + *******************************************************************************************************/ +sl_status_t sl_usbd_core_write_24b_to_descriptor_buf(uint32_t val) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + status = *(p_dev->desc_buf_status_ptr); + + if (status == SL_STATUS_OK) { + uint8_t buf[3u]; + + buf[0u] = (uint8_t)(val & 0xFFu); + buf[1u] = (uint8_t)((val >> 8u) & 0xFFu); + buf[2u] = (uint8_t)((val >> 16u) & 0xFFu); + + usbd_core_write_to_descriptor_buf(p_dev, &buf[0u], 3u); + } + + return status; +} + +/****************************************************************************************************//** + * Writes a 24-bit value to the descriptor buffer + *******************************************************************************************************/ +sl_status_t sl_usbd_core_write_32b_to_descriptor_buf(uint32_t val) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + status = *(p_dev->desc_buf_status_ptr); + + if (status == SL_STATUS_OK) { + uint8_t buf[4u]; + + buf[0u] = (uint8_t)(val & 0xFFu); + buf[1u] = (uint8_t)((val >> 8u) & 0xFFu); + buf[2u] = (uint8_t)((val >> 16u) & 0xFFu); + buf[3u] = (uint8_t)((val >> 24u) & 0xFFu); + + usbd_core_write_to_descriptor_buf(p_dev, &buf[0u], 4u); + } + + return status; +} + +/****************************************************************************************************//** + * Writes a buffer into the descriptor buffer + *******************************************************************************************************/ +sl_status_t sl_usbd_core_write_buf_to_descriptor_buf(const uint8_t *p_buf, + uint16_t len) +{ + sli_usbd_device_t *p_dev; + sl_status_t status; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if ((p_buf == NULL) || (len == 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } + + status = *(p_dev->desc_buf_status_ptr); + + if (status == SL_STATUS_OK) { + usbd_core_write_to_descriptor_buf(p_dev, p_buf, len); + } + + return status; +} + +/****************************************************************************************************//** + * Adds a bulk endpoint to alternate setting interface + *******************************************************************************************************/ +sl_status_t sl_usbd_core_add_bulk_endpoint(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + bool dir_in, + uint16_t max_pkt_len, + uint8_t *p_ep_addr) +{ + if (p_ep_addr == NULL) { + return SL_STATUS_NULL_POINTER; + } + +#if (USBD_CFG_HS_EN == 1) + // Chk EP size. + // SL_USBD_CONFIG_NBR_SPD_BIT will always be clear in FS. + if (((max_pkt_len != 0u) && (max_pkt_len != 512u)) + && (SL_IS_BIT_SET(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT))) { + *p_ep_addr = SL_USBD_ENDPOINT_ADDR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } +#endif + +#if (USBD_CFG_HS_EN == 1) + if (((max_pkt_len != 0u) + && (max_pkt_len != 8u) + && (max_pkt_len != 16u) + && (max_pkt_len != 32u) + && (max_pkt_len != 64u)) + && (SL_IS_BIT_CLEAR(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT) == true)) { +#else + if ( (max_pkt_len != 0u) + && (max_pkt_len != 8u) + && (max_pkt_len != 16u) + && (max_pkt_len != 32u) + && (max_pkt_len != 64u)) { +#endif + *p_ep_addr = SL_USBD_ENDPOINT_ADDR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + return usbd_core_add_endpoint(config_nbr, + if_nbr, + if_alt_nbr, + SL_USBD_ENDPOINT_TYPE_BULK, + dir_in, + max_pkt_len, + 0u, + p_ep_addr); +} + +/****************************************************************************************************//** + * Adds an interrupt endpoint to an alternate setting interface + *******************************************************************************************************/ +sl_status_t sl_usbd_core_add_interrupt_endpoint(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + bool dir_in, + uint16_t max_pkt_len, + uint16_t interval, + uint8_t *p_ep_addr) +{ + uint8_t interval_code; + + if (p_ep_addr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (interval == 0u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + +#if (USBD_CFG_HS_EN == 1) + // Full spd validation. + // SL_USBD_CONFIG_NBR_SPD_BIT will always be clear in FS. + if (SL_IS_BIT_CLEAR(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT) == true) { +#endif + if (max_pkt_len > 64u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + if (interval < 255u) { + interval_code = (uint8_t)interval; + } else { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } +#if (USBD_CFG_HS_EN == 1) +} else { + // High spd validation. + if (((if_alt_nbr == 0u) && (max_pkt_len > 64u)) || (max_pkt_len > 1024u)) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // See Note #2. + if (interval > SL_USBD_ENDPOINT_MAX_INTERVAL_VAL) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // interval must be a power of 2. + if (SLI_USBD_IS_PWR2(interval) == false) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + // Compute bInterval exponent in 2^(bInterval-1). + interval_code = (uint8_t)(32u - __CLZ(interval)); + + if (interval_code > 16u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } +} +#endif + + return usbd_core_add_endpoint(config_nbr, + if_nbr, + if_alt_nbr, + SL_USBD_ENDPOINT_TYPE_INTR, + dir_in, + max_pkt_len, + interval_code, + p_ep_addr); +} + +/****************************************************************************************************//** + * Adds an isochronous endpoint to alternate setting interface + *******************************************************************************************************/ +#if (USBD_CFG_EP_ISOC_EN == 1) +sl_status_t sl_usbd_core_add_isochronous_endpoint(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + bool dir_in, + uint8_t attrib, + uint16_t max_pkt_len, + uint8_t transaction_frame, + uint16_t interval, + uint8_t *p_ep_addr) +{ + uint16_t pkt_len; + uint8_t interval_code; + + if (p_ep_addr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Chk if dflt IF setting with isoc EP max_pkt_len > 0. + if ((if_alt_nbr == 0u) && (max_pkt_len > 0u)) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk if sync & usage bits are used. + if ((attrib & (uint8_t)(~(SL_USBD_ENDPOINT_TYPE_SYNC_MASK | SL_USBD_ENDPOINT_TYPE_USAGE_MASK))) != 0u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + +#if (USBD_CFG_HS_EN == 1) + // Full spd validation. + // SL_USBD_CONFIG_NBR_SPD_BIT will always be clear in FS. + if (SL_IS_BIT_CLEAR(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT) == true) { +#endif + if (max_pkt_len > 1023u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + if (transaction_frame != 1u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } +#if (USBD_CFG_HS_EN == 1) +} else { + // High spd validation. + switch (transaction_frame) { + case 1u: + if (max_pkt_len > 1024u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + break; + + case 2u: + if ((max_pkt_len < 513u) || (max_pkt_len > 1024u)) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + break; + + case 3u: + if ((max_pkt_len < 683u) || (max_pkt_len > 1024u)) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + break; + + default: + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } +} +#endif + + // Explicit feedback EP must be set to no sync. + if (((attrib & SL_USBD_ENDPOINT_TYPE_USAGE_MASK) == SL_USBD_ENDPOINT_TYPE_USAGE_FEEDBACK) + && ((attrib & SL_USBD_ENDPOINT_TYPE_SYNC_MASK) != SL_USBD_ENDPOINT_TYPE_SYNC_NONE)) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // See Note #3. + if (interval > SL_USBD_ENDPOINT_MAX_INTERVAL_VAL) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // interval must be a power of 2. + if (SLI_USBD_IS_PWR2(interval) == false) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Compute bInterval exponent in 2^(bInterval-1). + interval_code = (uint8_t)(32u - __CLZ(interval)); + + if (interval_code > 16u) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + pkt_len = (transaction_frame - 1u) << 11u | max_pkt_len; + + return usbd_core_add_endpoint(config_nbr, + if_nbr, + if_alt_nbr, + SL_USBD_ENDPOINT_TYPE_ISOC | attrib, + dir_in, + pkt_len, + interval_code, + p_ep_addr); +} +#endif + +/****************************************************************************************************//** + * Set synchronization feedback rate on synchronization isochronous endpoint + *******************************************************************************************************/ +#if (USBD_CFG_EP_ISOC_EN == 1) +sl_status_t sl_usbd_core_set_isochronous_endpoint_refresh_rate(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + uint8_t synch_ep_addr, + uint8_t sync_refresh) +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + sli_usbd_endpoint_info_t *p_ep; +#if (USBD_CFG_OPTIMIZE_SPD == 1) + uint32_t ep_alloc_map; +#endif + uint8_t ep_nbr; + bool found; + CORE_DECLARE_IRQ_STATE; + + // See Note #3. + if ((sync_refresh < 1u) || (sync_refresh > 9u)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get Object References + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Chk curr dev state. + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) + && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + return SL_STATUS_INVALID_STATE; + } + + // Get cfg struct. + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); + + if (p_config == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get IF struct. + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + + if (p_if == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk if audio class. + if (p_if->class_code != SL_USBD_CLASS_CODE_AUDIO) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk if audio class, version 1.0. + if (p_if->class_protocol_code != 0u) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get IF alt setting struct. + p_if_alt = usbd_core_get_alt_interface_structure(p_if, if_alt_nbr); + + if (p_if_alt == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + found = false; + p_ep = NULL; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_alloc_map = p_if_alt->endpoint_table_map; + while ((ep_alloc_map != 0x00u) + && (found != true)) { + ep_nbr = (uint8_t)__CLZ(__RBIT(ep_alloc_map)); + p_ep = p_if_alt->endpoint_table_ptrs[ep_nbr]; + + if (p_ep->address == synch_ep_addr) { + found = true; + } + + SL_CLEAR_BIT(ep_alloc_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); + } +#else + p_ep = p_if_alt->endpoint_head_ptr; + + for (ep_nbr = 0u; ep_nbr < p_if_alt->endpoint_nbr_total; ep_nbr++) { + if (p_ep->address == synch_ep_addr) { + found = true; + break; + } + + p_ep = p_ep->next_ptr; + } +#endif + + if (found != true) { + return SL_STATUS_INVALID_HANDLE; + } + // Chk EP type attrib. + if ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) != SL_USBD_ENDPOINT_TYPE_ISOC) { + return SL_STATUS_INVALID_HANDLE; + } + + // Chk EP sync type attrib. + switch (p_ep->attrib & SL_USBD_ENDPOINT_TYPE_SYNC_MASK) { + case SL_USBD_ENDPOINT_TYPE_SYNC_NONE: + break; + + case SL_USBD_ENDPOINT_TYPE_SYNC_ASYNC: + case SL_USBD_ENDPOINT_TYPE_SYNC_ADAPTIVE: + case SL_USBD_ENDPOINT_TYPE_SYNC_SYNC: + default: + return SL_STATUS_INVALID_HANDLE; + } + + // Chk EP usage type attrib. + switch (p_ep->attrib & SL_USBD_ENDPOINT_TYPE_USAGE_MASK) { + case SL_USBD_ENDPOINT_TYPE_USAGE_FEEDBACK: + // See Note #4. + break; + + case SL_USBD_ENDPOINT_TYPE_USAGE_DATA: + case SL_USBD_ENDPOINT_TYPE_USAGE_IMPLICIT_FEEDBACK: + default: + return SL_STATUS_INVALID_HANDLE; + } + + // Chk associated sync EP addr. + if (p_ep->sync_addr != 0u) { + return SL_STATUS_INVALID_HANDLE; + } + + CORE_ENTER_ATOMIC(); + p_ep->sync_refresh = sync_refresh; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * Associates synchronization endpoint to isochronous endpoint + *******************************************************************************************************/ +#if (USBD_CFG_EP_ISOC_EN == 1) +sl_status_t sl_usbd_core_set_isochronous_endpoint_sync_address(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + uint8_t data_ep_addr, + uint8_t sync_addr) +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + sli_usbd_endpoint_info_t *p_ep; + sli_usbd_endpoint_info_t *p_ep_isoc; +#if (USBD_CFG_OPTIMIZE_SPD == 1) + uint32_t ep_alloc_map; +#endif + uint8_t ep_nbr; + bool found_ep; + bool found_sync; + CORE_DECLARE_IRQ_STATE; + + // Get Object References + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Chk curr dev state. + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) + && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + return SL_STATUS_INVALID_STATE; + } + + // Get cfg struct. + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); + + if (p_config == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get IF struct. + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + + if (p_if == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk if audio class. + if (p_if->class_code != SL_USBD_CLASS_CODE_AUDIO) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Chk if audio class, version 1.0. + if (p_if->class_protocol_code != 0u) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Get IF alt setting struct. + p_if_alt = usbd_core_get_alt_interface_structure(p_if, if_alt_nbr); + + if (p_if_alt == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + found_ep = false; + found_sync = false; + p_ep_isoc = NULL; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_alloc_map = p_if_alt->endpoint_table_map; + while ((ep_alloc_map != 0x00u) + && ((found_ep != true) + || (found_sync != true))) { + ep_nbr = (uint8_t)__CLZ(__RBIT(ep_alloc_map)); + p_ep = p_if_alt->endpoint_table_ptrs[ep_nbr]; + + if (p_ep->address == data_ep_addr) { + found_ep = true; + p_ep_isoc = p_ep; + } + + if (p_ep->address == sync_addr) { + found_sync = true; + } + + SL_CLEAR_BIT(ep_alloc_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); + } +#else + p_ep = p_if_alt->endpoint_head_ptr; + + for (ep_nbr = 0u; ep_nbr < p_if_alt->endpoint_nbr_total; ep_nbr++) { + if (p_ep->address == data_ep_addr) { + found_ep = true; + p_ep_isoc = p_ep; + } + + if (p_ep->address == sync_addr) { + found_sync = true; + } + + if ((found_ep == true) + && (found_sync == true)) { + break; + } + + p_ep = p_ep->next_ptr; + } +#endif + + if (found_ep != true) { + return SL_STATUS_INVALID_HANDLE; + } + + if (found_sync != true) { + return SL_STATUS_INVALID_PARAMETER; + } + // Chk EP type attrib. + if ((p_ep_isoc->attrib & SL_USBD_ENDPOINT_TYPE_MASK) != SL_USBD_ENDPOINT_TYPE_ISOC) { + return SL_STATUS_INVALID_HANDLE; + } + + // Chk EP sync type attrib. + switch (p_ep_isoc->attrib & SL_USBD_ENDPOINT_TYPE_SYNC_MASK) { + case SL_USBD_ENDPOINT_TYPE_SYNC_ASYNC: + if (SL_USBD_ENDPOINT_IS_IN(p_ep_isoc->address) == true) { + return SL_STATUS_INVALID_HANDLE; + } + break; + + case SL_USBD_ENDPOINT_TYPE_SYNC_ADAPTIVE: + if (SL_USBD_ENDPOINT_IS_IN(p_ep_isoc->address) == false) { + return SL_STATUS_INVALID_HANDLE; + } + break; + + case SL_USBD_ENDPOINT_TYPE_SYNC_NONE: + case SL_USBD_ENDPOINT_TYPE_SYNC_SYNC: + default: + return SL_STATUS_INVALID_HANDLE; + } + + // Chk EP usage type attrib. + switch (p_ep_isoc->attrib & SL_USBD_ENDPOINT_TYPE_USAGE_MASK) { + case SL_USBD_ENDPOINT_TYPE_USAGE_DATA: + break; + + case SL_USBD_ENDPOINT_TYPE_USAGE_FEEDBACK: + case SL_USBD_ENDPOINT_TYPE_USAGE_IMPLICIT_FEEDBACK: + default: + return SL_STATUS_INVALID_HANDLE; + } + + // Refresh interval must be set to zero. + if (p_ep_isoc->sync_refresh != 0u) { + return SL_STATUS_INVALID_HANDLE; + } + + CORE_ENTER_ATOMIC(); + p_ep_isoc->sync_addr = sync_addr; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * Gets the maximum physical endpoint number + *******************************************************************************************************/ +sl_status_t sl_usbd_core_get_max_phy_endpoint_number(uint8_t *p_ep_phy_nbr) +{ + sli_usbd_device_t *p_dev; + + if (p_ep_phy_nbr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Get dev struct. + p_dev = &usbd_ptr->device; + + if (p_dev->endpoint_max_phy_nbr == 0u) { + *p_ep_phy_nbr = SL_USBD_ENDPOINT_PHY_NONE; + } else { + *p_ep_phy_nbr = p_dev->endpoint_max_phy_nbr - 1u; + } + + return SL_STATUS_OK; +} + +/******************************************************************************************************** + ******************************************************************************************************** + * INTERNAL FUNCTIONS + ******************************************************************************************************** + *******************************************************************************************************/ + +/****************************************************************************************************//** + * Notifies the USB connection bus events to the device stack + *******************************************************************************************************/ +sl_status_t sli_usbd_core_connect_event(void) +{ + usbd_core_set_event(SLI_USBD_EVENT_BUS_CONNECT); + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Notifies the USB disconnection bus events to the device stack + *******************************************************************************************************/ +sl_status_t sli_usbd_core_disconnect_event(void) +{ + usbd_core_set_event(SLI_USBD_EVENT_BUS_DISCONNECT); + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Notifies the USB High-Speed bus events to the device stack + *******************************************************************************************************/ +sl_status_t sli_usbd_core_high_speed_event(void) +{ + usbd_core_set_event(SLI_USBD_EVENT_BUS_HS); + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Notifies the USB reset bus events to the device stack + *******************************************************************************************************/ +sl_status_t sli_usbd_core_reset_event(void) +{ + usbd_core_set_event(SLI_USBD_EVENT_BUS_RESET); + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Notifies the USB suspend bus events to the device stack + *******************************************************************************************************/ +sl_status_t sli_usbd_core_suspend_event(void) +{ + usbd_core_set_event(SLI_USBD_EVENT_BUS_SUSPEND); + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Notifies the USB resume bus events to the device stack + *******************************************************************************************************/ +sl_status_t sli_usbd_core_resume_event(void) +{ + usbd_core_set_event(SLI_USBD_EVENT_BUS_RESUME); + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Sends a USB setup event to the core task + *******************************************************************************************************/ +sl_status_t sli_usbd_core_setup_event(void *p_buf) +{ + sli_usbd_device_t *p_dev; + sli_usbd_core_event_t core_event; + uint8_t *p_buf_08; + + // Get dev struct. + p_dev = &usbd_ptr->device; + + SLI_USBD_LOG_VRB(("USBD: Setup Pkt")); + + p_buf_08 = (uint8_t *)p_buf; + p_dev->setup_req_next.bmRequestType = p_buf_08[0u]; + p_dev->setup_req_next.bRequest = p_buf_08[1u]; + memcpy(&p_dev->setup_req_next.wValue, (p_buf_08 + 2u), 2u); + memcpy(&p_dev->setup_req_next.wIndex, (p_buf_08 + 4u), 2u); + memcpy(&p_dev->setup_req_next.wLength, (p_buf_08 + 6u), 2u); + + core_event.type = SLI_USBD_EVENT_SETUP; + + sli_usbd_core_os_put_core_event(&core_event); + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * Sends a USB endpoint event to the core task + *******************************************************************************************************/ +sl_status_t sli_usbd_core_endpoint_event(uint8_t ep_addr, + sl_status_t status) +{ + sli_usbd_core_event_t core_event; + + core_event.type = SLI_USBD_EVENT_ENDPOINT; + core_event.endpoint_address = ep_addr; + core_event.status = status; + + // Queue core event. + sli_usbd_core_os_put_core_event(&core_event); + + return SL_STATUS_OK; +} + +/******************************************************************************************************** + ******************************************************************************************************** + * LOCAL FUNCTIONS + ******************************************************************************************************** + *******************************************************************************************************/ + +/****************************************************************************************************//** + * usbd_core_add_device() + * + * @brief Adds a device to the stack and creates the default control endpoints. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +static sl_status_t usbd_core_add_device(void) +{ + sli_usbd_device_t *p_dev; + uint8_t ep_phy_nbr; + uint32_t ep_alloc_map; + sli_usbd_endpoint_info_t ep_info; + bool alloc; + sl_usbd_device_speed_t drv_spd; + sl_status_t status; + + sli_usbd_driver_get_speed(&drv_spd); + + // Initialize Device Structure + p_dev = &usbd_ptr->device; + p_dev->speed = drv_spd; + + // device configuration parameters from sl_usbd_device_config.h + p_dev->device_config.product_id = SL_USBD_DEVICE_PRODUCT_ID; + p_dev->device_config.vendor_id = SL_USBD_DEVICE_VENDOR_ID; + p_dev->device_config.device_bcd = SL_USBD_DEVICE_RELEASE_NUMBER; + p_dev->device_config.manufacturer_str_ptr = SL_USBD_DEVICE_MANUFACTURER_STRING; + p_dev->device_config.product_str_ptr = SL_USBD_DEVICE_PRODUCT_STRING; + p_dev->device_config.serial_nbr_str_ptr = SL_USBD_DEVICE_SERIAL_NUMBER_STRING; + p_dev->device_config.lang_id = SL_USBD_DEVICE_LANGUAGE_ID; + + ep_alloc_map = 0x00u; + + // Alloc physical EP for ctrl OUT. + usbd_core_allocate_endpoint(drv_spd, + SL_USBD_ENDPOINT_TYPE_CTRL, + false, + 0u, + 0u, + &ep_info, + &ep_alloc_map, + &alloc); + + if (alloc != true) { + return SL_STATUS_NOT_AVAILABLE; + } + + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_info.address); + ep_phy_nbr++; + + if (p_dev->endpoint_max_phy_nbr < ep_phy_nbr) { + p_dev->endpoint_max_phy_nbr = ep_phy_nbr; + } + + // Alloc physical EP for ctrl IN. + usbd_core_allocate_endpoint(drv_spd, + SL_USBD_ENDPOINT_TYPE_CTRL, + true, + 0u, + 0u, + &ep_info, + &ep_alloc_map, + &alloc); + + if (alloc != true) { + return SL_STATUS_NOT_AVAILABLE; + } + + p_dev->endpoint_max_ctrl_pkt_size = ep_info.max_pkt_size; + + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_info.address); + ep_phy_nbr++; + + if (p_dev->endpoint_max_phy_nbr < ep_phy_nbr) { + p_dev->endpoint_max_phy_nbr = ep_phy_nbr; + } + +#if (USBD_CFG_STR_EN == 1) + // Add device configuration strings: + + // Manufacturer string. + status = usbd_core_add_string(p_dev, + p_dev->device_config.manufacturer_str_ptr); + if (status != SL_STATUS_OK) { + return status; + } + + // Product string. + status = usbd_core_add_string(p_dev, + p_dev->device_config.product_str_ptr); + if (status != SL_STATUS_OK) { + return status; + } + + // Serial number string. + status = usbd_core_add_string(p_dev, + p_dev->device_config.serial_nbr_str_ptr); + if (status != SL_STATUS_OK) { + return status; + } +#endif + + status = sli_usbd_core_os_create_task(); + + return status; +} + +/****************************************************************************************************//** + * usbd_core_add_endpoint() + * + * @brief Add an endpoint to alternate setting interface. + * + * @param config_nbr Configuration number. + * + * @param if_nbr Interface number. + * + * @param if_alt_nbr Interface alternate setting number. + * + * @param attrib Endpoint's attributes. + * + * @param dir_in Endpoint Direction. + * + * @param max_pkt_len Endpoint maximum packet size. + * + * @param interval interval for polling data transfers. + * + * @param p_ep_addr Pointer to the variable that will receive endpoint address. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + *******************************************************************************************************/ +static sl_status_t usbd_core_add_endpoint(uint8_t config_nbr, + uint8_t if_nbr, + uint8_t if_alt_nbr, + uint8_t attrib, + bool dir_in, + uint16_t max_pkt_len, + uint8_t interval, + uint8_t *p_ep_addr) + +{ + sli_usbd_device_t *p_dev; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + sli_usbd_endpoint_info_t *p_ep; + uint8_t ep_type; + uint32_t ep_alloc_map; + uint32_t ep_alloc_map_clr; + uint8_t ep_nbr; + uint8_t ep_phy_nbr; + sl_usbd_device_speed_t dev_spd; + bool alloc; + CORE_DECLARE_IRQ_STATE; + + // Get Object References + + // Get dev struct. + p_dev = &usbd_ptr->device; + + // Get cfg struct. + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); + + if (p_config == NULL) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get IF struct. + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + + if (p_if == NULL) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + // Get IF alt setting struct. + p_if_alt = usbd_core_get_alt_interface_structure(p_if, if_alt_nbr); + + if (p_if_alt == NULL) { + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + // Chk if EP is avail. + if (usbd_ptr->endpoint_info_nbr_next == 0u) { + CORE_EXIT_ATOMIC(); + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_ALLOCATION_FAILED; + } + usbd_ptr->endpoint_info_nbr_next--; + ep_nbr = usbd_ptr->endpoint_info_nbr_next; + CORE_EXIT_ATOMIC(); + + ep_type = attrib & SL_USBD_ENDPOINT_TYPE_MASK; +#if (USBD_CFG_HS_EN == 1) + if (SL_IS_BIT_SET(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT) == true) { + dev_spd = SL_USBD_DEVICE_SPEED_HIGH; + } else { +#endif + dev_spd = SL_USBD_DEVICE_SPEED_FULL; +#if (USBD_CFG_HS_EN == 1) +} +#endif + + p_ep = &usbd_ptr->endpoint_info_table[ep_nbr]; + p_ep->interval = interval; + p_ep->attrib = attrib; + // Default sync addr is zero. + p_ep->sync_addr = 0u; + // Default feedback rate exponent is zero. + p_ep->sync_refresh = 0u; + + CORE_ENTER_ATOMIC(); + // Get cfg EP alloc bit map. + ep_alloc_map = p_config->endpoint_alloc_map; + // Clr EP already alloc'd in the IF. + ep_alloc_map &= ~p_if->endpoint_alloc_map; + ep_alloc_map |= p_if_alt->endpoint_alloc_map; + + ep_alloc_map_clr = ep_alloc_map; + + // Alloc physical EP. + usbd_core_allocate_endpoint(dev_spd, + ep_type, + dir_in, + // Mask out transactions per microframe. + max_pkt_len & 0x7FF, + if_alt_nbr, + p_ep, + &ep_alloc_map, + &alloc); + + if (alloc != true) { + CORE_EXIT_ATOMIC(); + *p_ep_addr = SL_USBD_ENDPOINT_NBR_NONE; + return SL_STATUS_NOT_AVAILABLE; + } + + // Set transactions per microframe. + p_ep->max_pkt_size |= max_pkt_len & 0x1800; + + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(p_ep->address); + ep_phy_nbr++; + + if (p_dev->endpoint_max_phy_nbr < ep_phy_nbr) { + p_dev->endpoint_max_phy_nbr = ep_phy_nbr; + } + + p_if_alt->endpoint_alloc_map |= ep_alloc_map & ~ep_alloc_map_clr; + p_if->endpoint_alloc_map |= p_if_alt->endpoint_alloc_map; + p_config->endpoint_alloc_map |= p_if->endpoint_alloc_map; + + p_if_alt->endpoint_nbr_total++; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(p_ep->address); + p_if_alt->endpoint_table_ptrs[ep_nbr] = p_ep; + SL_SET_BIT(p_if_alt->endpoint_table_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); +#else + p_ep->next_ptr = NULL; + if (p_if_alt->endpoint_head_ptr == NULL) { + p_if_alt->endpoint_head_ptr = p_ep; + p_if_alt->endpoint_tail_ptr = p_ep; + } else { + p_if_alt->endpoint_tail_ptr->next_ptr = p_ep; + p_if_alt->endpoint_tail_ptr = p_ep; + } +#endif + CORE_EXIT_ATOMIC(); + + *p_ep_addr = p_ep->address; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * usbd_core_allocate_endpoint() + * + * @brief Allocate a physical endpoint from the device controller. + * + * @param spd Endpoint speed. + * - SL_USBD_DEVICE_SPEED_FULL Endpoint is full-speed. + * - SL_USBD_DEVICE_SPEED_HIGH Endpoint is high-speed. + * + * @param type Endpoint type. + * - SL_USBD_ENDPOINT_TYPE_CTRL Control endpoint. + * - SL_USBD_ENDPOINT_TYPE_ISOC Isochronous endpoint. + * - SL_USBD_ENDPOINT_TYPE_BULK Bulk endpoint. + * - SL_USBD_ENDPOINT_TYPE_INTR Interrupt endpoint. + * + * @param dir_in Endpoint direction. + * - true IN endpoint. + * - false OUT endpoint. + * + * @param max_pkt_len Endpoint maximum packet size length. + * + * @param if_alt_nbr Alternate interface number containing the endpoint. + * + * @param p_ep Pointer to the variable that will receive the endpoint parameters. + * + * @param ---- Argument validated in 'sl_usbd_core_add_device()' & 'usbd_core_add_endpoint()' + * + * @param p_alloc_bit_map Pointer to allocation table bit-map. + * + * @param --------------- Argument validated in 'sl_usbd_core_add_device()' & 'usbd_core_add_endpoint()' + * + * @param p_alloc Pointer to a boolean where function result will be returned. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) 'Universal Serial Bus Specification, Revision 2.0, April 27, 2000' Section 5.5.3 + * @n + * "An endpoint for control transfers specifies the maximum data payload size that + * the endpoint can accept from or transmit to the bus. The allowable maximum control + * transfer data payload sizes for full-speed devices is 8, 16, 32, or 64 bytes; for + * high-speed devices, it is 64 bytes and for low-speed devices, it is 8 bytes." + * @n + * "All Host Controllers are required to have support for 8-, 16-, 32-, and 64-byte + * maximum data payload sizes for full-speed control endpoints, only 8-byte maximum + * data payload sizes for low-speed control endpoints, and only 64-byte maximum data + * payload size for high-speed control endpoints" + *******************************************************************************************************/ +static sl_status_t usbd_core_allocate_endpoint(sl_usbd_device_speed_t spd, + uint8_t type, + bool dir_in, + uint16_t max_pkt_len, + uint8_t if_alt_nbr, + sli_usbd_endpoint_info_t *p_ep, + uint32_t *p_alloc_bit_map, + bool *p_alloc) +{ + sli_usbd_driver_endpoint_info_t *p_ep_tbl; + uint8_t ep_tbl_ix; + uint8_t ep_attrib; + uint8_t ep_attrib_srch; + uint8_t ep_max_pkt_bits; + uint16_t ep_max_pkt; + bool ep_found; + +#if (USBD_CFG_HS_EN == 0) + (void)&spd; + (void)&if_alt_nbr; +#endif + + if (dir_in == true) { + ep_attrib_srch = SL_USBD_ENDPOINT_INFO_DIR_IN; + } else { + ep_attrib_srch = SL_USBD_ENDPOINT_INFO_DIR_OUT; + } + + switch (type) { + case SL_USBD_ENDPOINT_TYPE_CTRL: + SL_SET_BIT(ep_attrib_srch, SL_USBD_ENDPOINT_INFO_TYPE_CTRL); + break; + + case SL_USBD_ENDPOINT_TYPE_ISOC: + SL_SET_BIT(ep_attrib_srch, SL_USBD_ENDPOINT_INFO_TYPE_ISOC); + break; + + case SL_USBD_ENDPOINT_TYPE_BULK: + SL_SET_BIT(ep_attrib_srch, SL_USBD_ENDPOINT_INFO_TYPE_BULK); + break; + + case SL_USBD_ENDPOINT_TYPE_INTR: + SL_SET_BIT(ep_attrib_srch, SL_USBD_ENDPOINT_INFO_TYPE_INTR); + break; + + default: + *p_alloc = false; + return SL_STATUS_OK; + } + + // Get ctrl EP info tbl. + sli_usbd_driver_get_endpoint_info(&p_ep_tbl); + // Get attrib for first entry. + ep_attrib = p_ep_tbl->attrib; + ep_tbl_ix = 0u; + ep_found = false; + + // Search until last entry or EP found. + while ((ep_attrib != 0x00u) + && (ep_found == false)) { + // Chk if EP not alloc'd and EP attrib match req'd attrib. + if ((SL_IS_BIT_CLEAR(*p_alloc_bit_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_tbl_ix)) == true) + && (SL_IS_BIT_SET(ep_attrib, ep_attrib_srch) == true)) { + ep_max_pkt = p_ep_tbl[ep_tbl_ix].max_pkt_size; + + switch (type) { + // Chk ctrl transfer pkt size constrains. + case SL_USBD_ENDPOINT_TYPE_CTRL: + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 64u); + // Get next power of 2. + ep_max_pkt_bits = (uint8_t)(31u - __CLZ(ep_max_pkt)); + ep_max_pkt = SLI_USBD_SINGLE_BIT_MASK_16(ep_max_pkt_bits); +#if (USBD_CFG_HS_EN == 1) + if ((spd == SL_USBD_DEVICE_SPEED_HIGH) + && (ep_max_pkt != 64u)) { + break; + } + + if ((spd == SL_USBD_DEVICE_SPEED_HIGH) + && (ep_max_pkt < 8u)) { + break; + } +#endif + ep_found = true; + break; + + case SL_USBD_ENDPOINT_TYPE_BULK: +#if (USBD_CFG_HS_EN == 1) + // Max pkt size is 512 for bulk EP in HS. + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 512u); + if ((spd == SL_USBD_DEVICE_SPEED_HIGH) + && (ep_max_pkt == 512u)) { + ep_found = true; + break; + } +#endif + // Max pkt size is 64 for bulk EP in FS. + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 64u); + ep_max_pkt_bits = (uint8_t)(31u - __CLZ(ep_max_pkt)); + ep_max_pkt = SLI_USBD_SINGLE_BIT_MASK_16(ep_max_pkt_bits); +#if (USBD_CFG_HS_EN == 1) + if ((spd == SL_USBD_DEVICE_SPEED_HIGH) + && (ep_max_pkt >= 8u)) { + break; + } +#endif + ep_found = true; + break; + + case SL_USBD_ENDPOINT_TYPE_ISOC: +#if (USBD_CFG_HS_EN == 1) + if (spd == SL_USBD_DEVICE_SPEED_HIGH) { + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 1024u); + } else { +#endif + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 1023u); +#if (USBD_CFG_HS_EN == 1) + } +#endif + + if (max_pkt_len > 0u) { + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, max_pkt_len); + } + + ep_found = true; + break; + + case SL_USBD_ENDPOINT_TYPE_INTR: +#if (USBD_CFG_HS_EN == 1) + if ((spd == SL_USBD_DEVICE_SPEED_HIGH) + && (if_alt_nbr != 0u)) { + // Dflt IF intr EP max pkt size limited to 64. + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 1024u); + } else { +#endif + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, 64u); +#if (USBD_CFG_HS_EN == 1) + } +#endif + if (max_pkt_len > 0u) { + ep_max_pkt = SLI_USBD_GET_MIN(ep_max_pkt, max_pkt_len); + } + + ep_found = true; + break; + + default: + *p_alloc = false; + return SL_STATUS_OK; + } + + if ((ep_found == true) + && ((max_pkt_len == ep_max_pkt) + || (max_pkt_len == 0u))) { + p_ep->max_pkt_size = ep_max_pkt; + SL_SET_BIT(*p_alloc_bit_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_tbl_ix)); + p_ep->address = p_ep_tbl[ep_tbl_ix].nbr; + if (dir_in == true) { + // Add dir bit (IN EP). + p_ep->address |= SL_USBD_ENDPOINT_DIR_IN; + } + } else { + ep_found = false; + ep_tbl_ix++; + ep_attrib = p_ep_tbl[ep_tbl_ix].attrib; + } + } else { + ep_tbl_ix++; + ep_attrib = p_ep_tbl[ep_tbl_ix].attrib; + } + } + + if (ep_found == false) { + *p_alloc = false; + return SL_STATUS_OK; + } + + *p_alloc = true; + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * usbd_core_stdreq_handler() + * + * @brief Standard request process. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + *******************************************************************************************************/ +static void usbd_core_stdreq_handler(sli_usbd_device_t *p_dev) +{ + uint8_t recipient; + uint8_t type; + uint8_t request; + bool valid; + bool dev_to_host; + sl_status_t local_status; + CORE_DECLARE_IRQ_STATE; + + local_status = SL_STATUS_OK; + +#if (USBD_CFG_MS_OS_DESC_EN != 1) + (void)&local_status; +#endif + + CORE_ENTER_ATOMIC(); + // Copy setup request. + p_dev->setup_req.bmRequestType = p_dev->setup_req_next.bmRequestType; + p_dev->setup_req.bRequest = p_dev->setup_req_next.bRequest; + p_dev->setup_req.wValue = p_dev->setup_req_next.wValue; + p_dev->setup_req.wIndex = p_dev->setup_req_next.wIndex; + p_dev->setup_req.wLength = p_dev->setup_req_next.wLength; + CORE_EXIT_ATOMIC(); + + recipient = p_dev->setup_req.bmRequestType & SL_USBD_REQ_RECIPIENT_MASK; + type = p_dev->setup_req.bmRequestType & SL_USBD_REQ_TYPE_MASK; + request = p_dev->setup_req.bRequest; + dev_to_host = SL_IS_BIT_SET(p_dev->setup_req.bmRequestType, SL_USBD_REQ_DIR_BIT); + valid = false; + + switch (type) { + case SL_USBD_REQ_TYPE_STANDARD: + // Select req recipient: + switch (recipient) { + case SL_USBD_REQ_RECIPIENT_DEVICE: + // Device. + valid = usbd_core_device_stdreq(p_dev, request); + break; + + case SL_USBD_REQ_RECIPIENT_INTERFACE: + // Interface. + valid = usbd_core_interface_stdreq(p_dev, request); + break; + + case SL_USBD_REQ_RECIPIENT_ENDPOINT: + // Endpoint. + valid = usbd_core_endpoint_stdreq(p_dev, request); + break; + + case SL_USBD_REQ_RECIPIENT_OTHER: + // Not supported. + default: + break; + } + break; + + case SL_USBD_REQ_TYPE_CLASS: + // Class-specific req. + switch (recipient) { + case SL_USBD_REQ_RECIPIENT_INTERFACE: + case SL_USBD_REQ_RECIPIENT_ENDPOINT: + // Class-specific req. + valid = usbd_core_class_stdreq(p_dev); + break; + + case SL_USBD_REQ_RECIPIENT_DEVICE: + case SL_USBD_REQ_RECIPIENT_OTHER: + default: + break; + } + break; + + case SL_USBD_REQ_TYPE_VENDOR: + switch (recipient) { + case SL_USBD_REQ_RECIPIENT_INTERFACE: +#if (USBD_CFG_MS_OS_DESC_EN == 1) + if (request == p_dev->str_microsoft_vendor_code) { + p_dev->desc_buf_status_ptr = &local_status; + // Microsoft OS descriptor req. + valid = usbd_core_microsoft_interface_stdreq(p_dev); + p_dev->desc_buf_status_ptr = NULL; + } else { + // Vendor-specific req. + valid = usbd_core_vendor_stdreq(p_dev); + } + break; +#endif + + case SL_USBD_REQ_RECIPIENT_ENDPOINT: + // Vendor-specific req. + valid = usbd_core_vendor_stdreq(p_dev); + break; + + case SL_USBD_REQ_RECIPIENT_DEVICE: +#if (USBD_CFG_MS_OS_DESC_EN == 1) + if (request == p_dev->str_microsoft_vendor_code) { + p_dev->desc_buf_status_ptr = &local_status; + // Microsoft OS descriptor req. + valid = usbd_core_microsoft_device_stdreq(p_dev); + p_dev->desc_buf_status_ptr = NULL; + } +#endif + break; + + case SL_USBD_REQ_RECIPIENT_OTHER: + default: + break; + } + break; + + case SL_USBD_REQ_TYPE_RESERVED: + default: + break; + } + + if (valid == false) { + SLI_USBD_LOG_DBG(("USBD: Request Error")); + sli_usbd_core_stall_control_endpoint(); + } else { + uint32_t std_req_timeout; + + CORE_ENTER_ATOMIC(); + std_req_timeout = usbd_ptr->std_req_timeout_ms; + CORE_EXIT_ATOMIC(); + + if (dev_to_host == true) { + SLI_USBD_LOG_VRB(("USBD: Rx Status")); + sli_usbd_core_get_control_rx_status(std_req_timeout); + } else { + SLI_USBD_LOG_VRB(("USBD: Tx Status")); + sli_usbd_core_get_control_tx_status(std_req_timeout); + } + } +} + +/****************************************************************************************************//** + * usbd_core_device_stdreq() + * + * @brief Process device standard request. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param request USB device request. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + * + * @note (1) USB Spec 2.0, section 9.4.6 specifies the format of the SET_ADDRESS request. The + * SET_ADDRESS sets the device address for all future device access. + * - (a) The 'wValue' filed specify the device address to use for all subsequent accesses. + * - (b) If the specified device address is greater than 127 or if 'wIndex' or 'wLength' + * are non-zero, the behavior of the device is not specified. + * - (c) If the device is in the default state and the address specified is non-zero, + * the device shall enter the device address, otherwise the device remains in the + * default state' (this is not an error condition). + * - (d) If the device is in the address state and the address specified is zero, then + * the device shall enter the default state otherwise, the device remains in + * the address state but uses the newly-specified address. + * - (e) Device behavior when the SET_ADDRESS request is received while the device is not + * in the default or address state is not specified. + * - (f) USB Spec 2.0, section 9.2.6.3 specifies the maximum timeout for the SET_ADDRESS + * request: + * "After the reset/resume recovery interval, if a device receives a SetAddress() + * request, the device must be able to complete processing of the request and be + * able to successfully complete the Status stage of the request within 50 ms. In + * the case of the SetAddress() request, the Status stage successfully completes + * when the device sends the zero-length Status packet or when the device sees + * the ACK in response to the Status stage data packet." + * + * @note (2) USB Spec 2.0, section 9.4.7 specifies the format of the SET_CONFIGURATION request. + * - (a) The lower byte of 'wValue' field specifies the desired configuration. + * - (b) If 'wIndex', 'wLength', or the upper byte of wValue is non-zero, then the behavior + * of this request is not specified. + * - (c) The configuration value must be zero or match a configuration value from a + * configuration value from a configuration descriptor. If the configuration value + * is zero, the device is place in its address state. + * - (d) Device behavior when this request is received while the device is in the Default + * state is not specified. + * - (e) If device is in address state and the specified configuration value is zero, + * then the device remains in the Address state. If the specified configuration value + * matches the configuration value from a configuration descriptor, then that + * configuration is selected and the device enters the Configured state. Otherwise, + * the device responds with a Request Error. + * - (f) If the specified configuration value is zero, then the device enters the Address + * state. If the specified configuration value matches the configuration value from a + * configuration descriptor, then that configuration is selected and the device + * remains in the Configured state. Otherwise, the device responds with a Request + * Error. + * + * @note (3) USB Spec 2.0, section 9.4.2 specifies the format of the GET_CONFIGURATION request. + * - (a) If 'wValue' or 'wIndex' are non-zero or 'wLength' is not '1', then the device + * behavior is not specified. + * - (b) If the device is in default state, the device behavior is not specified. + * - (c) In address state a value of zero MUST be returned. + * - (d) In configured state, the non-zero bConfigurationValue of the current configuration + * must be returned. + * + * @note (4) USB Spec 2.0, section 9.4.5 specifies the format of the GET_STATUS request. + * - (a) If 'wValue' is non-zero or 'wLength is not equal to '2', or if wIndex is non-zero + * then the behavior of the device is not specified. + * - (b) USB Spec 2, 0, figure 9-4 shows the format of information returned by the device + * for a GET_STATUS request. + * @verbatim + * +====|====|====|====|====|====|====|========|=========+ + * | D0 | D1 | D2 | D3 | D4 | D3 | D2 | D1 | D0 | + * |----------------------------------|--------|---------| + * | RESERVED (RESET TO ZERO) | Remote | Self | + * | | Wakeup | Powered | + * +==================================|========|=========+ + * @endverbatim + * - (1) The Self Powered field indicates whether the device is currently self-powered. + * If D0 is reset to zero, the device is bus-powered. If D0 is set to one, the + * device is self-powered. The Self Powered field may not be changed by the + * SetFeature() or ClearFeature() requests. + * - (2) The Remote Wakeup field indicates whether the device is currently enabled to + * request remote wakeup. The default mode for devices that support remote wakeup + * is disabled. If D1 is reset to zero, the ability of the device to signal + * remote wakeup is disabled. If D1 is set to one, the ability of the device to + * signal remote wakeup is enabled. The Remote Wakeup field can be modified by + * the SetFeature() and ClearFeature() requests using the DEVICE_REMOTE_WAKEUP + * feature selector. This field is reset to zero when the device is reset. + * + * @note (5) USB Spec 2.0, section 9.4.1/9.4.9 specifies the format of the CLEAR_FEATURE/SET_FEATURE + * request. + * - (a) If 'wLength' or 'wIndex' are non-zero, then the device behavior is not specified. + * - (b) The device CLEAR_FEATURE request is only valid when the device is in the + * configured state. + *******************************************************************************************************/ +static bool usbd_core_device_stdreq(sli_usbd_device_t *p_dev, + uint8_t request) +{ + bool valid; + bool dev_to_host; + uint8_t dev_addr; + uint8_t cfg_nbr; + uint32_t std_req_timeout; + uint32_t xfer_len; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + std_req_timeout = usbd_ptr->std_req_timeout_ms; + CORE_EXIT_ATOMIC(); + + SLI_USBD_DBG_STATS_DEV_INC(std_req_device_nbr); + + dev_to_host = SL_IS_BIT_SET(p_dev->setup_req.bmRequestType, SL_USBD_REQ_DIR_BIT); + valid = false; + + switch (request) { + case SL_USBD_REQ_GET_DESCRIPTOR: + if (dev_to_host != true) { + break; + } + + valid = usbd_core_get_descriptor_stdreq(p_dev); + break; + + case SL_USBD_REQ_SET_ADDRESS: + if (dev_to_host != false) { + break; + } + + SLI_USBD_DBG_STATS_DEV_INC(std_req_set_address_nbr); + + // Get dev addr (see Note #1a). + dev_addr = (uint8_t)(p_dev->setup_req.wValue + & 0xFFu); + + SLI_USBD_LOG_VRB(("USBD: Set Address to addr #", (u)dev_addr)); + + // Validate request values. (see Note #1b). + if ((dev_addr > 127u) + || (p_dev->setup_req.wIndex != 0u) + || (p_dev->setup_req.wLength != 0u)) { + break; + } + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_DEFAULT: + if (dev_addr > 0u) { + // See Note #1c. + status = sli_usbd_driver_set_address(dev_addr); + if (status != SL_STATUS_OK) { + SLI_USBD_LOG_ERR(("USBD Set Address Failed")); + break; + } + + CORE_ENTER_ATOMIC(); + // Set dev in addressed state. + p_dev->address = dev_addr; + p_dev->state = SL_USBD_DEVICE_STATE_ADDRESSED; + CORE_EXIT_ATOMIC(); + + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_ADDRESSED: + if (dev_addr == 0u) { + // See Note #1c. If dev addr is zero set addr in dev drv. + status = sli_usbd_driver_set_address(0u); + if (status != SL_STATUS_OK) { + SLI_USBD_LOG_ERR(("USBD Set Address Failed")); + break; + } + + CORE_ENTER_ATOMIC(); + // Dev enters default state. + p_dev->address = 0u; + p_dev->state = SL_USBD_DEVICE_STATE_DEFAULT; + CORE_EXIT_ATOMIC(); + + valid = true; + } else { + // remains in addressed state and set new addr. + status = sli_usbd_driver_set_address(dev_addr); + if (status != SL_STATUS_OK) { + SLI_USBD_LOG_ERR(("USBD Set Address Failed")); + break; + } + + CORE_ENTER_ATOMIC(); + p_dev->address = dev_addr; + CORE_EXIT_ATOMIC(); + + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_CONFIGURED: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + SLI_USBD_LOG_ERR(("USBD Set Address Failed due to invalid device state.")); + break; + } + break; + + case SL_USBD_REQ_SET_CONFIGURATION: + if (dev_to_host != false) { + break; + } + + SLI_USBD_DBG_STATS_DEV_INC(std_req_set_configuration_nbr); + + // Validate request values (see Note #2b). + if (((p_dev->setup_req.wValue & 0xFF00u) != 0u) + && (p_dev->setup_req.wIndex != 0u) + && (p_dev->setup_req.wLength != 0u)) { + break; + } + // Get cfg value. + cfg_nbr = (uint8_t)(p_dev->setup_req.wValue & 0xFFu); + SLI_USBD_LOG_VRB(("USBD: Set Configuration #", (u)cfg_nbr)); + +#if (USBD_CFG_HS_EN == 1) + // Cfg value MUST exists. + if ((cfg_nbr > p_dev->config_hs_total_nbr) + && (p_dev->speed == SL_USBD_DEVICE_SPEED_HIGH)) { + SLI_USBD_LOG_ERR((" Set Configuration Cfg Invalid nbr")); + break; + } +#endif + + if ((cfg_nbr > p_dev->config_fs_total_nbr) + && (p_dev->speed == SL_USBD_DEVICE_SPEED_FULL)) { + SLI_USBD_LOG_ERR((" Set Configuration Cfg Invalid nbr")); + break; + } + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_ADDRESSED: + // See Note #2e. + if (cfg_nbr > 0u) { + // Open cfg. + status = usbd_core_set_configuration(p_dev, (cfg_nbr - 1u)); + + if (status != SL_STATUS_OK) { + SLI_USBD_LOG_ERR(("USBD Set Configuration Failed. status = ", status)); + break; + } + + valid = true; + } else { + // Remain in addressed state. + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_CONFIGURED: + // See Note #2f. + if (cfg_nbr > 0u) { + if (p_dev->config_cur_nbr == (cfg_nbr - 1u)) { + valid = true; + break; + } + + // Close curr cfg. + usbd_core_unset_configuration(p_dev); + + // Open cfg. + status = usbd_core_set_configuration(p_dev, (cfg_nbr - 1u)); + + if (status != SL_STATUS_OK) { + SLI_USBD_LOG_ERR(("USBD Set Configuration Failed. status = ", status)); + break; + } + + valid = true; + } else { + // Close curr cfg. + usbd_core_unset_configuration(p_dev); + + CORE_ENTER_ATOMIC(); + p_dev->state = SL_USBD_DEVICE_STATE_ADDRESSED; + CORE_EXIT_ATOMIC(); + + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_DEFAULT: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + SLI_USBD_LOG_ERR(("USBD Set Configuration Failed due to invalid device state.")); + break; + } + break; + + case SL_USBD_REQ_GET_CONFIGURATION: + if (dev_to_host != true) { + break; + } + + // Validate request values (see Note #3a). + if ((p_dev->setup_req.wLength != 1u) + && (p_dev->setup_req.wIndex != 0u) + && (p_dev->setup_req.wValue != 0u)) { + break; + } + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_ADDRESSED: + // See Note #3b. + cfg_nbr = 0u; + SLI_USBD_LOG_VRB(("USBD: Get Configuration #", (u)cfg_nbr)); + + // Uses Ctrl status buf to follow USB mem alignment. + p_dev->ctrl_status_buf_ptr[0u] = cfg_nbr; + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 1u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_DEVICE_STATE_CONFIGURED: + // See Note #3c. + if (p_dev->config_cur_ptr == NULL) { + break; + } + + cfg_nbr = p_dev->config_cur_nbr + 1u; + SLI_USBD_LOG_VRB(("USBD: Get Configuration #", (u)cfg_nbr)); + + // Uses Ctrl status buf to follow USB mem alignment. + p_dev->ctrl_status_buf_ptr[0u] = cfg_nbr; + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 1u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_DEFAULT: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + SLI_USBD_LOG_ERR(("USBD Get Configuration Failed due to invalid device state.")); + break; + } + break; + + case SL_USBD_REQ_GET_STATUS: + if (dev_to_host != true) { + break; + } + + // Validate request values (see Note #4a). + if ((p_dev->setup_req.wLength != 2u) + && (p_dev->setup_req.wIndex != 0u) + && (p_dev->setup_req.wValue != 0u)) { + break; + } + + SLI_USBD_LOG_VRB(("USBD: Get Status (Device)")); + p_dev->ctrl_status_buf_ptr[0u] = 0x00u; + p_dev->ctrl_status_buf_ptr[1u] = 0x00u; + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_ADDRESSED: + // See Note #4b. + if (p_dev->self_power == true) { + p_dev->ctrl_status_buf_ptr[0u] |= 0x01u; // BIT_00 + } + if (p_dev->remote_wakeup == true) { + p_dev->ctrl_status_buf_ptr[0u] |= 0x02u; // BIT_01 + } + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 2u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_DEVICE_STATE_CONFIGURED: + if (p_dev->config_cur_ptr != NULL) { + if (SL_IS_BIT_SET(p_dev->config_cur_ptr->attrib, SL_USBD_DEV_ATTRIB_SELF_POWERED)) { + p_dev->ctrl_status_buf_ptr[0u] |= 0x01u; // BIT_00 + } + if (SL_IS_BIT_SET(p_dev->config_cur_ptr->attrib, SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP)) { + p_dev->ctrl_status_buf_ptr[0u] |= 0x02u; // BIT_01 + } + } + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 2u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_DEFAULT: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + SLI_USBD_LOG_ERR(("USBD Get Status (Device) Failed due to invalid device state.")); + break; + } + break; + + case SL_USBD_REQ_CLEAR_FEATURE: + case SL_USBD_REQ_SET_FEATURE: + if (dev_to_host != false) { + break; + } + + // Validate request values. + if ((p_dev->setup_req.wLength != 0u) + && (p_dev->setup_req.wIndex != 0u)) { + break; + } + + if (request == SL_USBD_REQ_CLEAR_FEATURE) { + SLI_USBD_LOG_VRB(("USBD: Clear Feature (Device)")); + } else { + SLI_USBD_LOG_VRB(("USBD: Set Feature (Device)")); + } + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_CONFIGURED: + if (p_dev->config_cur_ptr == NULL) { + break; + } + + if ((p_dev->setup_req.wValue == SL_USBD_FEATURE_SEL_DEVICE_REMOTE_WAKEUP) + && (SL_IS_BIT_SET(p_dev->config_cur_ptr->attrib, SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP))) { + p_dev->remote_wakeup = (request == SL_USBD_REQ_CLEAR_FEATURE) ? 0u : 1u; + } + + valid = true; + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_DEFAULT: + case SL_USBD_DEVICE_STATE_ADDRESSED: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + if (request == SL_USBD_REQ_CLEAR_FEATURE) { + SLI_USBD_LOG_ERR(("USBD Clear Feature (Device) Failed due to invalid device state.")); + } else { + SLI_USBD_LOG_ERR(("USBD Set Feature (Device) Failed due to invalid device state.")); + } + break; + } + break; + + default: + break; + } + + SLI_USBD_DBG_STATS_DEV_INC_IF_TRUE(std_req_device_stall_nbr, (valid == false)); + + return (valid); +} + +/****************************************************************************************************//** + * usbd_core_interface_stdreq() + * + * @brief Process device standard request (Interface). + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param request USB device request. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + * + * @note (1) USB Spec 2.0, section 9.4.10 specifies the format of the SET_INTERFACE request. + * This request allows the host to select an alternate setting for the specified + * interface: + * - (a) Some USB devices have configurations with interfaces that have mutually + * exclusive settings. This request allows the host to select the desired + * alternate setting. If a device only supports a default setting for the + * specified interface, then a STALL may be returned in the Status stage of + * the request. This request cannot be used to change the set of configured + * interfaces (the SetConfiguration() request must be used instead). + * - (2) USB Spec 2.0, section 9.4.4 specifies the format of the GET_INTERFACE request. + * This request returns the selected alternate setting for the specified interface. + * - (a) If 'wValue' is non-zero or 'wLength' is not '1', then the device behavior is + * not specified. + * - (b) The GET_INTERFACE request is only valid when the device is in the configured + * state. + *******************************************************************************************************/ +static bool usbd_core_interface_stdreq(sli_usbd_device_t *p_dev, + uint8_t request) +{ + uint32_t std_req_timeout; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + sl_usbd_class_driver_t *p_class_drv; + uint8_t if_nbr; + uint8_t if_alt_nbr; + bool valid; + bool dev_to_host; + uint16_t req_len; + uint32_t xfer_len; + sl_status_t status; + sl_status_t local_status; + CORE_DECLARE_IRQ_STATE; + + local_status = SL_STATUS_OK; + + CORE_ENTER_ATOMIC(); + std_req_timeout = usbd_ptr->std_req_timeout_ms; + CORE_EXIT_ATOMIC(); + + SLI_USBD_DBG_STATS_DEV_INC(std_req_interface_nbr); + + p_config = p_dev->config_cur_ptr; + if (p_config == NULL) { + SLI_USBD_DBG_STATS_DEV_INC(std_req_interface_stall_nbr); + return (false); + } + + if_nbr = (uint8_t)(p_dev->setup_req.wIndex & 0xFFu); + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + SLI_USBD_DBG_STATS_DEV_INC(std_req_interface_stall_nbr); + return (false); + } + + dev_to_host = SL_IS_BIT_SET(p_dev->setup_req.bmRequestType, SL_USBD_REQ_DIR_BIT); + valid = false; + + switch (request) { + case SL_USBD_REQ_GET_STATUS: + if (dev_to_host != true) { + break; + } + + SLI_USBD_LOG_VRB(("USBD: Get Status (Interface) IF ", (u)if_nbr)); + + if ((p_dev->state != SL_USBD_DEVICE_STATE_ADDRESSED) + && (p_dev->state != SL_USBD_DEVICE_STATE_CONFIGURED)) { + break; + } + + if ((p_dev->state == SL_USBD_DEVICE_STATE_ADDRESSED) + && (if_nbr != 0u)) { + break; + } + + p_dev->ctrl_status_buf_ptr[0u] = 0x00u; + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 1u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_REQ_CLEAR_FEATURE: + case SL_USBD_REQ_SET_FEATURE: + if (dev_to_host != false) { + break; + } + + if (request == SL_USBD_REQ_CLEAR_FEATURE) { + SLI_USBD_LOG_VRB(("USBD: Clear Feature (Interface) IF ", (u)if_nbr)); + } else { + SLI_USBD_LOG_VRB(("USBD: Set Feature (Interface) IF ", (u)if_nbr)); + } + + if ((p_dev->state != SL_USBD_DEVICE_STATE_ADDRESSED) + && (p_dev->state != SL_USBD_DEVICE_STATE_CONFIGURED)) { + break; + } + + if ((p_dev->state == SL_USBD_DEVICE_STATE_ADDRESSED) + && (if_nbr != 0u)) { + break; + } + + valid = true; + break; + + case SL_USBD_REQ_GET_DESCRIPTOR: + if (dev_to_host != true) { + break; + } + + SLI_USBD_LOG_VRB(("USBD: Get Descriptor (Interface) IF ", (u)if_nbr)); + + p_class_drv = p_if->class_driver_ptr; + if (p_class_drv->interface_req == NULL) { + break; + } + + req_len = p_dev->setup_req.wLength; + usbd_core_start_descriptor_write(p_dev, req_len); + + p_dev->desc_buf_status_ptr = &local_status; + + valid = p_class_drv->interface_req(&p_dev->setup_req, + p_if->class_arg_ptr); + if (valid == true) { + status = usbd_core_stop_descriptor_write(p_dev); + if (status != SL_STATUS_OK) { + valid = false; + } + } + p_dev->desc_buf_status_ptr = NULL; + break; + + case SL_USBD_REQ_GET_INTERFACE: + if (dev_to_host != true) { + break; + } + + if (p_dev->state != SL_USBD_DEVICE_STATE_CONFIGURED) { + break; + } + + p_dev->ctrl_status_buf_ptr[0u] = p_if->alt_cur; + + SLI_USBD_LOG_VRB(("USBD: Get Interface IF ", (u)if_nbr, " Alt ", (u)p_if->alt_cur)); + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 1u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_REQ_SET_INTERFACE: + if (dev_to_host != false) { + break; + } + + if (p_dev->state != SL_USBD_DEVICE_STATE_CONFIGURED) { + break; + } + // Get IF alt setting nbr. + if_alt_nbr = (uint8_t)(p_dev->setup_req.wValue & 0xFFu); + p_if_alt = usbd_core_get_alt_interface_structure(p_if, if_alt_nbr); + + SLI_USBD_LOG_VRB(("USBD: Set Interface IF ", (u)if_nbr, " Alt ", (u)if_alt_nbr)); + + if (p_if_alt == NULL) { + SLI_USBD_LOG_ERR(("USBD: Set Interface Invalid Alt IF")); + break; + } + + // If alt setting is the same as the cur one, no further processing is needed. + if (p_if_alt == p_if->alt_cur_ptr) { + valid = true; + break; + } + + // Close the cur alt setting. + usbd_core_close_alt_interface(p_dev, p_if->alt_cur_ptr); + + // Open the new alt setting. + status = usbd_core_open_alt_interface(p_dev, if_nbr, p_if_alt); + // Re-open curr IF alt setting, in case it fails. + if (status != SL_STATUS_OK) { + status = usbd_core_open_alt_interface(p_dev, p_if->alt_cur, p_if->alt_cur_ptr); + break; + } + + CORE_ENTER_ATOMIC(); + // Set IF alt setting. + p_if->alt_cur_ptr = p_if_alt; + p_if->alt_cur = if_alt_nbr; + CORE_EXIT_ATOMIC(); + + // Notify class that IF or alt IF has been updated. + if (p_if->class_driver_ptr->alt_settings_update != NULL) { + p_if->class_driver_ptr->alt_settings_update(p_dev->config_cur_nbr, + if_nbr, + if_alt_nbr, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + + valid = true; + break; + + default: + p_class_drv = p_if->class_driver_ptr; + if (p_class_drv->interface_req == NULL) { + break; + } + + valid = p_class_drv->interface_req(&p_dev->setup_req, + p_if->class_arg_ptr); + break; + } + + SLI_USBD_DBG_STATS_DEV_INC_IF_TRUE(std_req_interface_stall_nbr, (valid == false)); + + return (valid); +} + +/****************************************************************************************************//** + * usbd_core_endpoint_stdreq() + * + * @brief Process device standard request (Endpoint). + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param request USB device request. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + *******************************************************************************************************/ +static bool usbd_core_endpoint_stdreq(const sli_usbd_device_t *p_dev, + uint8_t request) +{ + uint32_t std_req_timeout; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_alt_if; + bool ep_is_stall; + uint8_t if_nbr; + uint8_t ep_addr; + uint8_t ep_phy_nbr; + bool valid; + bool dev_to_host; + uint8_t feature; + uint32_t xfer_len; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + std_req_timeout = usbd_ptr->std_req_timeout_ms; + CORE_EXIT_ATOMIC(); + + SLI_USBD_DBG_STATS_DEV_INC(std_req_endpoint_nbr); + + ep_addr = (uint8_t)(p_dev->setup_req.wIndex & 0xFFu); + feature = (uint8_t)(p_dev->setup_req.wValue & 0xFFu); + dev_to_host = SL_IS_BIT_SET(p_dev->setup_req.bmRequestType, SL_USBD_REQ_DIR_BIT); + valid = false; + + switch (request) { + case SL_USBD_REQ_CLEAR_FEATURE: + case SL_USBD_REQ_SET_FEATURE: + if (dev_to_host != false) { + break; + } + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_ADDRESSED: + if (((ep_addr == 0x80u) + || (ep_addr == 0x00u)) + && (feature == SL_USBD_FEATURE_SEL_ENDPOINT_HALT)) { + if (request == SL_USBD_REQ_CLEAR_FEATURE) { + SLI_USBD_LOG_VRB(("USBD: Clear Feature (EP)(STALL) for EP 0x", (X)SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr))); + + status = sl_usbd_core_stall_endpoint(ep_addr, false); + if (status != SL_STATUS_OK) { + break; + } + } else { + SLI_USBD_LOG_VRB(("USBD: Set Feature (EP)(STALL) for EP 0x", (X)SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr))); + + status = sl_usbd_core_stall_endpoint(ep_addr, true); + if (status != SL_STATUS_OK) { + break; + } + } + + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_CONFIGURED: + if (feature == SL_USBD_FEATURE_SEL_ENDPOINT_HALT) { + if (request == SL_USBD_REQ_CLEAR_FEATURE) { + SLI_USBD_LOG_VRB(("USBD: Clear Feature (EP)(STALL) for EP 0x", (X)SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr))); + + status = sl_usbd_core_stall_endpoint(ep_addr, false); + if (status != SL_STATUS_OK) { + break; + } + } else { + SLI_USBD_LOG_VRB(("USBD: Set Feature (EP)(STALL) for EP 0x", (X)SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr))); + + status = sl_usbd_core_stall_endpoint(ep_addr, true); + if (status != SL_STATUS_OK) { + break; + } + } + + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_addr); + if_nbr = p_dev->endpoint_interface_table[ep_phy_nbr]; + p_if = usbd_core_get_interface_structure(p_dev->config_cur_ptr, if_nbr); + p_alt_if = p_if->alt_cur_ptr; + + // Notify class that EP state has been updated. + if (p_if->class_driver_ptr->endpoint_state_update != NULL) { + p_if->class_driver_ptr->endpoint_state_update(p_dev->config_cur_nbr, + if_nbr, + p_if->alt_cur, + ep_addr, + p_if->class_arg_ptr, + p_alt_if->class_arg_ptr); + } + + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_DEFAULT: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + break; + } + break; + + case SL_USBD_REQ_GET_STATUS: + if (dev_to_host != true) { + break; + } + + p_dev->ctrl_status_buf_ptr[0u] = 0x00u; + p_dev->ctrl_status_buf_ptr[1u] = 0x00u; + + switch (p_dev->state) { + case SL_USBD_DEVICE_STATE_ADDRESSED: + if ((ep_addr == 0x80u) + || (ep_addr == 0x00u)) { + SLI_USBD_LOG_VRB(("USBD: Get Status (EP)(STALL) for EP 0x", (X)SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr))); + sl_usbd_core_is_endpoint_stalled(ep_addr, &ep_is_stall); + if (ep_is_stall == true) { + p_dev->ctrl_status_buf_ptr[0u] = 0x01u; // BIT_00 + p_dev->ctrl_status_buf_ptr[1u] = 0x00u; + } + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0u], + 2u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + } + break; + + case SL_USBD_DEVICE_STATE_CONFIGURED: + SLI_USBD_LOG_VRB(("USBD: Get Status (EP)(STALL) for EP 0x", (X)SL_USBD_ENDPOINT_ADDR_TO_LOG(ep_addr))); + sl_usbd_core_is_endpoint_stalled(ep_addr, &ep_is_stall); + if (ep_is_stall == true) { + p_dev->ctrl_status_buf_ptr[0u] = 0x01u; // BIT_00 + p_dev->ctrl_status_buf_ptr[1u] = 0x00u; + } + + status = sl_usbd_core_write_control_sync((void *)&p_dev->ctrl_status_buf_ptr[0], + 2u, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + + valid = true; + break; + + case SL_USBD_DEVICE_STATE_NONE: + case SL_USBD_DEVICE_STATE_INIT: + case SL_USBD_DEVICE_STATE_ATTACHED: + case SL_USBD_DEVICE_STATE_DEFAULT: + case SL_USBD_DEVICE_STATE_SUSPENDED: + default: + break; + } + break; + + default: + break; + } + + SLI_USBD_DBG_STATS_DEV_INC_IF_TRUE(std_req_endpoint_stall_nbr, (valid == false)); + + return (valid); +} + +/****************************************************************************************************//** + * usbd_core_class_stdreq() + * + * @brief Class standard request handler. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + *******************************************************************************************************/ +static bool usbd_core_class_stdreq(const sli_usbd_device_t *p_dev) +{ + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sl_usbd_class_driver_t *p_class_drv; + uint8_t recipient; + uint8_t if_nbr; + uint8_t ep_addr; + uint8_t ep_phy_nbr; + bool valid; + + SLI_USBD_DBG_STATS_DEV_INC(std_req_class_nbr); + + p_config = p_dev->config_cur_ptr; + if (p_config == NULL) { + return (false); + } + + recipient = p_dev->setup_req.bmRequestType & SL_USBD_REQ_RECIPIENT_MASK; + + if (recipient == SL_USBD_REQ_RECIPIENT_INTERFACE) { + if_nbr = (uint8_t)(p_dev->setup_req.wIndex & 0xFFu); + } else { + ep_addr = (uint8_t)(p_dev->setup_req.wIndex & 0xFFu); + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_addr); + if_nbr = p_dev->endpoint_interface_table[ep_phy_nbr]; + } + + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + SLI_USBD_DBG_STATS_DEV_INC(std_req_class_stall_nbr); + return (false); + } + + p_class_drv = p_if->class_driver_ptr; + if (p_class_drv->class_req == NULL) { + SLI_USBD_DBG_STATS_DEV_INC(std_req_class_stall_nbr); + return (false); + } + + valid = p_class_drv->class_req(&p_dev->setup_req, + p_if->class_arg_ptr); + + SLI_USBD_DBG_STATS_DEV_INC_IF_TRUE(std_req_class_stall_nbr, (valid == false)); + + return (valid); +} + +/****************************************************************************************************//** + * usbd_core_vendor_stdreq() + * + * @brief Vendor standard request handler. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + *******************************************************************************************************/ +static bool usbd_core_vendor_stdreq(const sli_usbd_device_t *p_dev) +{ + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sl_usbd_class_driver_t *p_class_drv; + uint8_t recipient; + uint8_t if_nbr; + uint8_t ep_addr; + uint8_t ep_phy_nbr; + bool valid; + + p_config = p_dev->config_cur_ptr; + if (p_config == NULL) { + return (false); + } + + recipient = p_dev->setup_req.bmRequestType & SL_USBD_REQ_RECIPIENT_MASK; + + if (recipient == SL_USBD_REQ_RECIPIENT_INTERFACE) { + if_nbr = (uint8_t)(p_dev->setup_req.wIndex & 0xFFu); + } else { + ep_addr = (uint8_t)(p_dev->setup_req.wIndex & 0xFFu); + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(ep_addr); + if_nbr = p_dev->endpoint_interface_table[ep_phy_nbr]; + } + + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + return (false); + } + + p_class_drv = p_if->class_driver_ptr; + if (p_class_drv->vendor_req == NULL) { + return (false); + } + + valid = p_class_drv->vendor_req(&p_dev->setup_req, + p_if->class_arg_ptr); + + return (valid); +} + +/****************************************************************************************************//** + * usbd_core_microsoft_device_stdreq() + * + * @brief Microsoft descriptor request handler (when recipient is device). + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + * + * @note (1) For more information on Microsoft OS decriptors, see + * 'http://msdn.microsoft.com/en-us/library/windows/hardware/gg463179.aspx'. + * + * @note (2) Page feature is not supported so Microsoft OS descriptors have their length limited + * to 64Kbytes. + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static bool usbd_core_microsoft_device_stdreq(const sli_usbd_device_t *p_dev) +{ + bool valid; + uint8_t if_nbr; + uint8_t max_if; + uint8_t if_ix; + uint8_t compat_id_ix; + uint8_t subcompat_id_ix; + uint8_t section_cnt; + uint16_t feature; + uint16_t len; + uint8_t cfg_nbr = 0u; + uint32_t desc_len; + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sl_usbd_class_driver_t *p_class_drv; + sl_status_t status; + + valid = false; + feature = p_dev->setup_req.wIndex; + if_nbr = (uint8_t)(p_dev->setup_req.wValue & 0xFFu); + len = p_dev->setup_req.wLength; + + // Use 1st cfg as Microsoft doesn't specify cfg in setup pkt. +#if (USBD_CFG_HS_EN == 1) + if (p_dev->speed == SL_USBD_DEVICE_SPEED_HIGH) { + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr | SL_USBD_CONFIG_NBR_SPD_BIT); + } else { +#endif + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr); +#if (USBD_CFG_HS_EN == 1) +} +#endif + if (p_config == NULL) { + return (false); + } + + switch (feature) { + case SLI_USBD_MICROSOFT_FEATURE_COMPAT_ID: + // See note (1). + // Send Desc Header + // Compute length of descriptor. + desc_len = SLI_USBD_MICROSOFT_DESC_COMPAT_ID_HDR_LEN; + section_cnt = 0u; + if (if_nbr == 0u) { + // If req IF == 0, sends all dev compat IDs. + max_if = p_config->interface_nbr_total; + } else { + max_if = if_nbr + 1u; + } + + for (if_ix = if_nbr; if_ix < max_if; if_ix++) { + p_if = usbd_core_get_interface_structure(p_config, if_ix); + p_class_drv = p_if->class_driver_ptr; + if (p_class_drv->microsoft_get_compat_id != NULL) { + compat_id_ix = p_class_drv->microsoft_get_compat_id(&subcompat_id_ix); + if (compat_id_ix != SL_USBD_MICROSOFT_COMPAT_ID_NONE) { + desc_len += SLI_USBD_MICROSOFT_DESC_COMPAT_ID_SECTION_LEN; + section_cnt++; + } + } + } + + // Wr desc hdr. + usbd_core_start_descriptor_write((sli_usbd_device_t *)p_dev, desc_len); + + sl_usbd_core_write_32b_to_descriptor_buf(desc_len); + sl_usbd_core_write_16b_to_descriptor_buf(SLI_USBD_MICROSOFT_DESC_VER_1_0); + sl_usbd_core_write_16b_to_descriptor_buf(feature); + sl_usbd_core_write_08b_to_descriptor_buf(section_cnt); + // Add 7 null bytes (reserved). + sl_usbd_core_write_32b_to_descriptor_buf(0u); + sl_usbd_core_write_16b_to_descriptor_buf(0u); + sl_usbd_core_write_08b_to_descriptor_buf(0u); + + // Send Desc Sections + if (len != SLI_USBD_MICROSOFT_DESC_COMPAT_ID_HDR_VER_1_0) { + // If req len = version, only send desc hdr. + for (if_ix = if_nbr; if_ix < max_if; if_ix++) { + p_if = usbd_core_get_interface_structure(p_config, if_ix); + if (p_if->class_driver_ptr->microsoft_get_compat_id != NULL) { + compat_id_ix = p_if->class_driver_ptr->microsoft_get_compat_id(&subcompat_id_ix); + if (compat_id_ix != SL_USBD_MICROSOFT_COMPAT_ID_NONE) { + sl_usbd_core_write_08b_to_descriptor_buf(if_ix); + sl_usbd_core_write_08b_to_descriptor_buf(0x01u); + + sl_usbd_core_write_buf_to_descriptor_buf((uint8_t *)usbd_microsoft_compat_id[compat_id_ix], + 8u); + + sl_usbd_core_write_buf_to_descriptor_buf((uint8_t *)usbd_microsoft_subcompat_id[subcompat_id_ix], + 8u); + + // Add 6 null bytes (reserved). + sl_usbd_core_write_32b_to_descriptor_buf(0u); + sl_usbd_core_write_16b_to_descriptor_buf(0u); + } + } + } + } + + if (*(p_dev->desc_buf_status_ptr) == SL_STATUS_OK) { + status = usbd_core_stop_descriptor_write((sli_usbd_device_t *)p_dev); + *(p_dev->desc_buf_status_ptr) = status; + } + + if (*(p_dev->desc_buf_status_ptr) == SL_STATUS_OK) { + valid = true; + } + break; + + case SLI_USBD_MICROSOFT_FEATURE_EXT_PROPERTIES: + valid = usbd_core_microsoft_ext_property_stdreq(p_dev, + p_config, + if_nbr, + len); + break; + + default: + break; + } + + return (valid); +} +#endif + +/****************************************************************************************************//** + * usbd_core_microsoft_interface_stdreq() + * + * @brief Microsoft descriptor request handler (when recipient is interface). + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + * + * @note (1) For more information on Microsoft OS decriptors, see + * 'http://msdn.microsoft.com/en-us/library/windows/hardware/gg463179.aspx'. + * + * @note (2) Page feature is not supported so Microsoft OS descriptors have their length limited + * to 64Kbytes. + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static bool usbd_core_microsoft_interface_stdreq(const sli_usbd_device_t *p_dev) +{ + bool valid = false; + uint8_t if_nbr = (uint8_t)(p_dev->setup_req.wValue & 0xFFu); + uint16_t feature = p_dev->setup_req.wIndex; + uint16_t len = p_dev->setup_req.wLength; + sli_usbd_configuration_t *p_config; + + // Use 1st cfg as Microsoft doesn't specify cfg in setup pkt. +#if (USBD_CFG_HS_EN == 1) + if (p_dev->speed == SL_USBD_DEVICE_SPEED_HIGH) { + p_config = usbd_core_get_configuration_structure(p_dev, 0u | SL_USBD_CONFIG_NBR_SPD_BIT); + } else { +#endif + p_config = usbd_core_get_configuration_structure(p_dev, 0u); +#if (USBD_CFG_HS_EN == 1) +} +#endif + if (p_config == NULL) { + return (false); + } + + switch (feature) { + case SLI_USBD_MICROSOFT_FEATURE_EXT_PROPERTIES: + valid = usbd_core_microsoft_ext_property_stdreq(p_dev, + p_config, + if_nbr, + len); + break; + + default: + break; + } + + return (valid); +} +#endif + +/****************************************************************************************************//** + * usbd_core_microsoft_ext_property_stdreq() + * + * @brief Microsoft descriptor request handler (when recipient is interface). + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param if_nbr Interface number. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param len Length of descriptor as requested by host. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + * + * @note (1) For more information on Microsoft OS decriptors, see + * 'http://msdn.microsoft.com/en-us/library/windows/hardware/gg463179.aspx'. + * + * @note (2) Page feature is not supported so Microsoft OS descriptors have their length limited + * to 64Kbytes. + *******************************************************************************************************/ +#if (USBD_CFG_MS_OS_DESC_EN == 1) +static bool usbd_core_microsoft_ext_property_stdreq(const sli_usbd_device_t *p_dev, + sli_usbd_configuration_t *p_config, + uint8_t if_nbr, + uint16_t len) +{ + bool valid = false; + uint8_t section_cnt = 0u; + uint8_t ext_property_cnt; + uint8_t ext_property_ix; + uint32_t desc_len = SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_HDR_LEN; + sli_usbd_interface_t *p_if; + sl_usbd_class_driver_t *p_class_drv; + sl_usbd_microsoft_ext_property_t *p_ext_property; + sl_status_t status; + + // Send Desc Header + // Compute length of descriptor. + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + p_class_drv = p_if->class_driver_ptr; + + if (p_class_drv->microsoft_get_ext_property_table != NULL) { + ext_property_cnt = p_class_drv->microsoft_get_ext_property_table(&p_ext_property, if_nbr); + for (ext_property_ix = 0u; ext_property_ix < ext_property_cnt; ext_property_ix++) { + desc_len += SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_SECTION_HDR_LEN; + desc_len += p_ext_property->property_name_len; + desc_len += p_ext_property->property_len; + desc_len += 6u; + + section_cnt++; + p_ext_property++; + } + } + + usbd_core_start_descriptor_write((sli_usbd_device_t *)p_dev, desc_len); + + sl_usbd_core_write_32b_to_descriptor_buf(desc_len); + sl_usbd_core_write_16b_to_descriptor_buf(SLI_USBD_MICROSOFT_DESC_VER_1_0); + sl_usbd_core_write_16b_to_descriptor_buf(SLI_USBD_MICROSOFT_FEATURE_EXT_PROPERTIES); + sl_usbd_core_write_16b_to_descriptor_buf(section_cnt); + + // Send Desc Sections + // If req len = version, only send desc hdr. + if ((len != SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_HDR_VER_1_0) + && (p_class_drv->microsoft_get_ext_property_table != NULL)) { + ext_property_cnt = p_class_drv->microsoft_get_ext_property_table(&p_ext_property, if_nbr); + for (ext_property_ix = 0u; ext_property_ix < ext_property_cnt; ext_property_ix++) { + // Compute desc section len. + desc_len = SLI_USBD_MICROSOFT_DESC_EXT_PROPERTIES_SECTION_HDR_LEN; + desc_len += p_ext_property->property_name_len; + desc_len += p_ext_property->property_len; + desc_len += 6u; + + // Wr desc section. + sl_usbd_core_write_32b_to_descriptor_buf(desc_len); + sl_usbd_core_write_32b_to_descriptor_buf(p_ext_property->property_type); + + sl_usbd_core_write_16b_to_descriptor_buf(p_ext_property->property_name_len); + sl_usbd_core_write_buf_to_descriptor_buf((uint8_t *)p_ext_property->property_name_ptr, + p_ext_property->property_name_len); + + sl_usbd_core_write_32b_to_descriptor_buf(p_ext_property->property_len); + sl_usbd_core_write_buf_to_descriptor_buf((uint8_t *)p_ext_property->property_ptr, + p_ext_property->property_len); + + p_ext_property++; + } + } + + if (*(p_dev->desc_buf_status_ptr) == SL_STATUS_OK) { + status = usbd_core_stop_descriptor_write((sli_usbd_device_t *)p_dev); + *(p_dev->desc_buf_status_ptr) = status; + } + + if (*(p_dev->desc_buf_status_ptr) == SL_STATUS_OK) { + valid = true; + } + + return (valid); +} +#endif + +/****************************************************************************************************//** + * usbd_core_get_descriptor_stdreq() + * + * @brief GET_DESCRIPTOR standard request handler. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return true, if no error(s) occurred and request is supported. + * false, if any errors are returned. + *******************************************************************************************************/ +static bool usbd_core_get_descriptor_stdreq(sli_usbd_device_t *p_dev) +{ + uint8_t desc_type; + uint8_t desc_ix; + uint16_t req_len; + bool valid; + sl_status_t local_status; + sl_status_t status; +#if (USBD_CFG_HS_EN == 1) + sl_usbd_device_speed_t drv_spd; +#endif + + local_status = SL_STATUS_OK; + + desc_type = (uint8_t)((p_dev->setup_req.wValue >> 8u) & 0xFFu); + desc_ix = (uint8_t)(p_dev->setup_req.wValue & 0xFFu); + valid = false; + req_len = p_dev->setup_req.wLength; + // Set the desc buf as the current buf. + p_dev->actual_buf_ptr = p_dev->desc_buf_ptr; + // Set the max len for the desc buf. + p_dev->desc_buf_max_len = SLI_USBD_DESC_BUF_LEN; + p_dev->desc_buf_status_ptr = &local_status; + + switch (desc_type) { + case SL_USBD_DESC_TYPE_DEVICE: + SLI_USBD_LOG_VRB(("USBD: Get Descriptor (Device)")); + status = usbd_core_send_device_descriptor(p_dev, false, req_len); + if (status == SL_STATUS_OK) { + valid = true; + } + break; + + case SL_USBD_DESC_TYPE_CONFIGURATION: + SLI_USBD_LOG_VRB(("USBD: Get Descriptor (Configuration) ix #", (u)desc_ix)); + status = usbd_core_send_configuration_descriptor(p_dev, desc_ix, false, req_len); + if (status != SL_STATUS_OK) { + SLI_USBD_LOG_ERR(("USBD Get Descriptor (Configuration) Failed. status = ", status)); + } else { + valid = true; + } + break; + + case SL_USBD_DESC_TYPE_STRING: + SLI_USBD_LOG_VRB(("USBD: Get Descriptor (String) ix #", (u)desc_ix)); +#if (USBD_CFG_STR_EN == 1) + status = usbd_core_send_string_descriptor(p_dev, desc_ix, req_len); + if (status == SL_STATUS_OK) { + valid = true; + } +#endif + break; + + case SL_USBD_DESC_TYPE_DEVICE_QUALIFIER: + SLI_USBD_LOG_VRB(("USBD: Get Descriptor (Device Qualifier)")); +#if (USBD_CFG_HS_EN == 1) + sli_usbd_driver_get_speed(&drv_spd); + + // Chk if dev only supports FS. + if (drv_spd == SL_USBD_DEVICE_SPEED_FULL) { + break; + } + + status = usbd_core_send_device_descriptor(p_dev, true, req_len); + + if (status == SL_STATUS_OK) { + valid = true; + } +#endif + break; + + case SL_USBD_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + SLI_USBD_LOG_VRB(("USBD: Get Descriptor (Other Speed)")); +#if (USBD_CFG_HS_EN == 1) + sli_usbd_driver_get_speed(&drv_spd); + + if (drv_spd == SL_USBD_DEVICE_SPEED_FULL) { + break; + } + + status = usbd_core_send_configuration_descriptor(p_dev, desc_ix, true, req_len); + + if (status == SL_STATUS_OK) { + valid = true; + } +#endif + break; + + default: + break; + } + + p_dev->desc_buf_status_ptr = NULL; + return (valid); +} + +/****************************************************************************************************//** + * usbd_core_unset_configuration() + * + * @brief Close current device configuration. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue and + * 'sl_usbd_core_stop_device()' function. + *******************************************************************************************************/ +static void usbd_core_unset_configuration(sli_usbd_device_t *p_dev) +{ + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + uint8_t if_nbr; + CORE_DECLARE_IRQ_STATE; + + p_config = p_dev->config_cur_ptr; + if (p_config == NULL) { + return; + } + + // Notify app about clr cfg. + sl_usbd_on_config_event(SL_USBD_EVENT_CONFIG_UNSET, p_dev->config_cur_nbr); + + for (if_nbr = 0u; if_nbr < p_config->interface_nbr_total; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + return; + } + + p_if_alt = p_if->alt_cur_ptr; + if (p_if_alt == NULL) { + return; + } + + if (p_if->class_driver_ptr->disable != NULL) { + // Notify class that cfg is not active. + p_if->class_driver_ptr->disable(p_dev->config_cur_nbr, + p_if->class_arg_ptr); + } + } + + CORE_ENTER_ATOMIC(); + p_dev->state = SL_USBD_DEVICE_STATE_ADDRESSED; + CORE_EXIT_ATOMIC(); + + for (if_nbr = 0u; if_nbr < p_config->interface_nbr_total; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + return; + } + + p_if_alt = p_if->alt_cur_ptr; + if (p_if_alt == NULL) { + return; + } + + usbd_core_close_alt_interface(p_dev, p_if_alt); + + p_if_alt = usbd_core_get_alt_interface_structure(p_if, 0u); + + CORE_ENTER_ATOMIC(); + p_if->alt_cur_ptr = p_if_alt; + p_if->alt_cur = 0u; + CORE_EXIT_ATOMIC(); + } + + CORE_ENTER_ATOMIC(); + p_dev->config_cur_ptr = NULL; + p_dev->config_cur_nbr = SL_USBD_CONFIG_NBR_NONE; + CORE_EXIT_ATOMIC(); +} + +/****************************************************************************************************//** + * usbd_core_set_configuration() + * + * @brief Open specified configuration. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param config_nbr Configuration number. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +static sl_status_t usbd_core_set_configuration(sli_usbd_device_t *p_dev, + uint8_t config_nbr) + +{ + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_alt_interface_t *p_if_alt; + uint8_t if_nbr; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + +#if (USBD_CFG_HS_EN == 1) + if (p_dev->speed == SL_USBD_DEVICE_SPEED_HIGH) { + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr | SL_USBD_CONFIG_NBR_SPD_BIT); + } else { +#endif + p_config = usbd_core_get_configuration_structure(p_dev, config_nbr); +#if (USBD_CFG_HS_EN == 1) +} +#endif + + if (p_config == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + for (if_nbr = 0u; if_nbr < p_config->interface_nbr_total; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + p_if_alt = p_if->alt_cur_ptr; + if (p_if_alt == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + status = usbd_core_open_alt_interface(p_dev, if_nbr, p_if_alt); + + if (status != SL_STATUS_OK) { + return status; + } + } + + CORE_ENTER_ATOMIC(); + p_dev->config_cur_ptr = p_config; + p_dev->config_cur_nbr = config_nbr; + CORE_EXIT_ATOMIC(); + + CORE_ENTER_ATOMIC(); + p_dev->state = SL_USBD_DEVICE_STATE_CONFIGURED; + CORE_EXIT_ATOMIC(); + + for (if_nbr = 0u; if_nbr < p_config->interface_nbr_total; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + if (p_if == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } else { + if (p_if->class_driver_ptr->enable != NULL) { + // Notify class that cfg is active. + p_if->class_driver_ptr->enable(config_nbr, + p_if->class_arg_ptr); + } + } + } + + // Notify app about set cfg. + sl_usbd_on_config_event(SL_USBD_EVENT_CONFIG_SET, config_nbr); + + return SL_STATUS_OK; +} + +/****************************************************************************************************//** + * usbd_core_send_device_descriptor() + * + * @brief Send device configuration descriptor. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param other Other speed configuration : + * - true Current speed. + * - false Other operational speed. + * + * @param req_len Requested length by the host. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) USB Spec 2.0 table 9-8 describes the standard device descriptor. + * + * +--------+--------------------+-------+----------+-----------------------------------+ + * | Offset | Field | size | Value | Description | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 0 | bLength | 1 | Number | size of this descriptor | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 1 | bDescriptorType | 1 | Const | DEVICE Descriptor type | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 2 | bcdUSB | 2 | BCD USB | Specification release number | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 4 | bDeviceClass | 1 | Class | Class code. | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 5 | bDeviceSubClass | 1 | SubClass | Subclass code. | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 6 | bDeviceProtocol | 1 | protocol | protocol code. | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 7 | bMaxPacketSize0 | 1 | Number | Max packet size for EP zero | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 8 | idVendor | 2 | id | Vendor id | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 10 | idProduct | 2 | id | Product id | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 12 | bcdDevice | 2 | BCD | Dev release number in BCD format | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 14 | iManufacturer | 1 | Index | Index of manufacturer string | + * +--------+--------------------+-------+----------+-----------------------------------+ + * | 15 | iProduct | 1 | Index | Index of product string | + * +--------|--------------------|-------|----------|-----------------------------------+ + * | 16 | iSerialNumber | 1 | Index | Index of serial number string | + * +--------|--------------------|-------|----------|-----------------------------------+ + * | 17 | bNumConfigurations | 1 | Number | Number of possible configurations | + * +--------|--------------------|-------|----------|-----------------------------------+ + * + * ) To enable host to identify devices that use the Interface Association descriptor the + * device descriptor should contain the following values. + *******************************************************************************************************/ +static sl_status_t usbd_core_send_device_descriptor(sli_usbd_device_t *p_dev, + bool other, + uint16_t req_len) +{ + sli_usbd_configuration_t *p_config; + bool if_grp_en; + uint8_t cfg_nbr; + uint8_t cfg_nbr_spd; + uint8_t cfg_nbr_total; + sl_usbd_device_speed_t drv_spd; +#if (USBD_CFG_STR_EN == 1) + uint8_t str_ix; +#endif + +#if (USBD_CFG_HS_EN == 0) + (void)&other; + (void)&drv_spd; +#endif + + if_grp_en = false; + +#if (USBD_CFG_HS_EN == 1) + if (other == false) { +#endif + usbd_core_start_descriptor_write(p_dev, req_len); + // Desc len. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_DEV); + // Dev desc type. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_DEVICE); + // USB spec release nbr in BCD fmt (2.00). + usbd_core_write_16b_to_descriptor_buf(p_dev, 0x200u); + +#if (USBD_CFG_HS_EN == 1) + if (p_dev->speed == SL_USBD_DEVICE_SPEED_FULL) { +#endif + cfg_nbr_spd = 0x00u; + cfg_nbr_total = p_dev->config_fs_total_nbr; +#if (USBD_CFG_HS_EN == 1) +} else { + cfg_nbr_spd = SL_USBD_CONFIG_NBR_SPD_BIT; + cfg_nbr_total = p_dev->config_hs_total_nbr; +} +#endif + + cfg_nbr = 0u; + while ((cfg_nbr < cfg_nbr_total) + && (if_grp_en == false)) { + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr | cfg_nbr_spd); + if (p_config != NULL) { + if (p_config->interface_group_nbr_total > 0u) { + if_grp_en = true; + } + } + + cfg_nbr++; + } + + if (if_grp_en == false) { + // Dev class is specified in IF desc. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_CLASS_CODE_USE_IF_DESC); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_SUBCLASS_CODE_USE_IF_DESC); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_PROTOCOL_CODE_USE_IF_DESC); + } else { + // Multi-Interface function dev class. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_CLASS_CODE_MISCELLANEOUS); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_SUBCLASS_CODE_USE_COMMON_CLASS); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_PROTOCOL_CODE_USE_IAD); + } + // Set max pkt size for ctrl EP. + usbd_core_write_08b_to_descriptor_buf(p_dev, (uint8_t)p_dev->endpoint_max_ctrl_pkt_size); + // Set vendor id, product id and dev id. + usbd_core_write_16b_to_descriptor_buf(p_dev, p_dev->device_config.vendor_id); + usbd_core_write_16b_to_descriptor_buf(p_dev, p_dev->device_config.product_id); + usbd_core_write_16b_to_descriptor_buf(p_dev, p_dev->device_config.device_bcd); + +#if (USBD_CFG_STR_EN == 1) + str_ix = usbd_core_get_string_index(p_dev, p_dev->device_config.manufacturer_str_ptr); + usbd_core_write_08b_to_descriptor_buf(p_dev, str_ix); + str_ix = usbd_core_get_string_index(p_dev, p_dev->device_config.product_str_ptr); + usbd_core_write_08b_to_descriptor_buf(p_dev, str_ix); + str_ix = usbd_core_get_string_index(p_dev, p_dev->device_config.serial_nbr_str_ptr); + usbd_core_write_08b_to_descriptor_buf(p_dev, str_ix); +#else + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); +#endif + usbd_core_write_08b_to_descriptor_buf(p_dev, cfg_nbr_total); + +#if (USBD_CFG_HS_EN == 1) +} else { + sli_usbd_driver_get_speed(&drv_spd); + if (drv_spd != SL_USBD_DEVICE_SPEED_HIGH) { + return SL_STATUS_INVALID_PARAMETER; + } + usbd_core_start_descriptor_write(p_dev, req_len); + // Desc len. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_DEV_QUAL); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_DEVICE_QUALIFIER); + // USB spec release nbr in BCD fmt (2.00). + usbd_core_write_16b_to_descriptor_buf(p_dev, 0x200u); + + if (p_dev->speed == SL_USBD_DEVICE_SPEED_HIGH) { + cfg_nbr_spd = 0x00u; + cfg_nbr_total = p_dev->config_fs_total_nbr; + } else { + cfg_nbr_spd = SL_USBD_CONFIG_NBR_SPD_BIT; + cfg_nbr_total = p_dev->config_hs_total_nbr; + } + + cfg_nbr = 0u; + while ((cfg_nbr < cfg_nbr_total) + && (if_grp_en == false)) { + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr | cfg_nbr_spd); + if (p_config != NULL) { + if (p_config->interface_group_nbr_total > 0u) { + if_grp_en = true; + } + cfg_nbr++; + } + } + if (if_grp_en == false) { + // Dev class is specified in IF desc. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_CLASS_CODE_USE_IF_DESC); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_SUBCLASS_CODE_USE_IF_DESC); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_PROTOCOL_CODE_USE_IF_DESC); + } else { + // Multi-Interface function dev class. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_CLASS_CODE_MISCELLANEOUS); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_SUBCLASS_CODE_USE_COMMON_CLASS); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_PROTOCOL_CODE_USE_IAD); + } + // Set max pkt size for ctrl EP. + usbd_core_write_08b_to_descriptor_buf(p_dev, (uint8_t)p_dev->endpoint_max_ctrl_pkt_size); + usbd_core_write_08b_to_descriptor_buf(p_dev, cfg_nbr_total); + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); +} +#endif + + return usbd_core_stop_descriptor_write(p_dev); +} + +/****************************************************************************************************//** + * usbd_core_send_configuration_descriptor() + * + * @brief Send configuration descriptor. + * + * @param p_dev Pointer to device struct. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param cfg_nbr Configuration number. + * + * @param other Other speed configuration : + * false Descriptor is build for the current speed. + * true Descriptor is build for the other speed. + * + * @param req_len Requested length by the host. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +static sl_status_t usbd_core_send_configuration_descriptor(sli_usbd_device_t *p_dev, + uint8_t config_nbr, + bool other, + uint16_t req_len) +{ + sli_usbd_configuration_t *p_config; + sli_usbd_interface_t *p_if; + sli_usbd_endpoint_info_t *p_ep; + sli_usbd_alt_interface_t *p_if_alt; + sli_usbd_interface_group_t *p_if_grp; + sl_usbd_class_driver_t *p_if_drv; + uint8_t cfg_nbr_cur; + uint8_t ep_nbr; + uint8_t if_nbr; + uint8_t if_total; + uint8_t if_grp_cur; + uint8_t if_alt_nbr; + uint8_t attrib; +#if (USBD_CFG_STR_EN == 1) + uint8_t str_ix; +#endif +#if (USBD_CFG_OPTIMIZE_SPD == 1) + uint32_t ep_alloc_map; +#endif + +#if (USBD_CFG_HS_EN == 1) + if (p_dev->speed == SL_USBD_DEVICE_SPEED_HIGH) { + cfg_nbr_cur = config_nbr | SL_USBD_CONFIG_NBR_SPD_BIT; + } else { +#endif + cfg_nbr_cur = config_nbr; +#if (USBD_CFG_HS_EN == 1) +} +#endif + + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr_cur); + + if (p_config == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + +#if (USBD_CFG_HS_EN == 1) + // other will always be false when HS is disabled. + if (other == true) { + if (p_config->config_other_speed == SL_USBD_CONFIG_NBR_NONE) { + return SL_STATUS_INVALID_PARAMETER; + } + + cfg_nbr_cur = p_config->config_other_speed; + + // Retrieve cfg struct for other spd. + p_config = usbd_core_get_configuration_structure(p_dev, cfg_nbr_cur); + if (p_config == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + } +#endif + + // Init cfg desc len. + p_config->desc_len = SL_USBD_DESC_LEN_CFG; + + // Build Configuration Descriptor + usbd_core_start_descriptor_write(p_dev, req_len); + + // Desc len. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_CFG); + // Desc type. + if (other == true) { + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_OTHER_SPEED_CONFIGURATION); + } else { + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_CONFIGURATION); + } + + if_total = p_config->interface_nbr_total; + if_grp_cur = SL_USBD_INTERFACE_GROUP_NBR_NONE; + + for (if_nbr = 0u; if_nbr < if_total; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + p_if_drv = p_if->class_driver_ptr; + + if ((p_if->group_nbr != if_grp_cur) + && (p_if->group_nbr != SL_USBD_INTERFACE_GROUP_NBR_NONE)) { + // Add IF assoc desc len. + p_config->desc_len += SL_USBD_DESC_LEN_IF_ASSOCIATION; + if_grp_cur = p_if->group_nbr; + } + + p_config->desc_len += (SL_USBD_DESC_LEN_IF * p_if->alt_nbr_total); + + for (if_alt_nbr = 0u; if_alt_nbr < p_if->alt_nbr_total; if_alt_nbr++) { + p_if_alt = usbd_core_get_alt_interface_structure(p_if, if_alt_nbr); + p_config->desc_len += (SL_USBD_DESC_LEN_EP * p_if_alt->endpoint_nbr_total); + + // Add IF functional desc len. + if (p_if_drv->interface_get_descriptor_size != NULL) { + p_config->desc_len += p_if_drv->interface_get_descriptor_size(cfg_nbr_cur, + if_nbr, + if_alt_nbr, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_alloc_map = p_if_alt->endpoint_table_map; + while (ep_alloc_map != 0x00u) { + ep_nbr = (uint8_t)__CLZ(__RBIT(ep_alloc_map)); + p_ep = p_if_alt->endpoint_table_ptrs[ep_nbr]; + + // Add EP functional desc len. + if (p_if_drv->endpoint_get_descriptor_size != NULL) { + p_config->desc_len += p_if_drv->endpoint_get_descriptor_size(cfg_nbr_cur, + if_nbr, + if_alt_nbr, + p_ep->address, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + + if ((p_if->class_code == SL_USBD_CLASS_CODE_AUDIO) + && (p_if->class_protocol_code == 0u) + && (((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_ISOC) + || ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_INTR))) { + // EP desc on audio class v1.0 has 2 additional fields. + p_config->desc_len += 2u; + } + + SL_CLEAR_BIT(ep_alloc_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); + } +#else + p_ep = p_if_alt->endpoint_head_ptr; + + for (ep_nbr = 0u; ep_nbr < p_if_alt->endpoint_nbr_total; ep_nbr++) { + if (p_if_drv->endpoint_get_descriptor_size != NULL) { + p_config->desc_len += p_if_drv->endpoint_get_descriptor_size(cfg_nbr_cur, + if_nbr, + if_alt_nbr, + p_ep->address, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + + if ((p_if->class_code == SL_USBD_CLASS_CODE_AUDIO) + && (p_if->class_protocol_code == 0u) + && (((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_ISOC) + || ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_INTR))) { + // EP desc on audio class v1.0 has 2 additional fields. + p_config->desc_len += 2u; + } + + p_ep = p_ep->next_ptr; + } +#endif + } + } + + // Build Cfg Desc + // Desc len. + usbd_core_write_16b_to_descriptor_buf(p_dev, p_config->desc_len); + // nbr of IF. + usbd_core_write_08b_to_descriptor_buf(p_dev, p_config->interface_nbr_total); + // Cfg ix. + usbd_core_write_08b_to_descriptor_buf(p_dev, config_nbr + 1u); + +#if (USBD_CFG_STR_EN == 1) + // Add str ix. + str_ix = usbd_core_get_string_index(p_dev, p_config->name_ptr); + usbd_core_write_08b_to_descriptor_buf(p_dev, str_ix); +#else + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); +#endif + + attrib = SLI_USBD_CONFIG_DESC_RSVD_SET; + if (SL_IS_BIT_SET(p_config->attrib, SL_USBD_DEV_ATTRIB_SELF_POWERED)) { + SL_SET_BIT(attrib, SLI_USBD_CONFIG_DESC_SELF_POWERED); + } + if (SL_IS_BIT_SET(p_config->attrib, SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP)) { + SL_SET_BIT(attrib, SLI_USBD_CONFIG_DESC_REMOTE_WAKEUP); + } + usbd_core_write_08b_to_descriptor_buf(p_dev, attrib); + usbd_core_write_08b_to_descriptor_buf(p_dev, (uint8_t)((p_config->max_power + 1u) / 2u)); + + // Build Interface Descriptor + if_total = p_config->interface_nbr_total; + if_grp_cur = SL_USBD_INTERFACE_GROUP_NBR_NONE; + + for (if_nbr = 0u; if_nbr < if_total; if_nbr++) { + p_if = usbd_core_get_interface_structure(p_config, if_nbr); + p_if_drv = p_if->class_driver_ptr; + + if ((p_if->group_nbr != if_grp_cur) + && (p_if->group_nbr != SL_USBD_INTERFACE_GROUP_NBR_NONE)) { + // Add IF assoc desc (IAD). + p_if_grp = usbd_core_get_interface_group_structure(p_config, p_if->group_nbr); + + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_IF_ASSOCIATION); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_IAD); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if_grp->interface_start); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if_grp->interface_count); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if_grp->class_code); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if_grp->class_sub_code); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if_grp->class_protocol_code); + +#if (USBD_CFG_STR_EN == 1) + str_ix = usbd_core_get_string_index(p_dev, p_if_grp->name_ptr); + usbd_core_write_08b_to_descriptor_buf(p_dev, str_ix); +#else + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); +#endif + + if_grp_cur = p_if->group_nbr; + } + // Add IF/alt settings desc. + for (if_alt_nbr = 0u; if_alt_nbr < p_if->alt_nbr_total; if_alt_nbr++) { + p_if_alt = usbd_core_get_alt_interface_structure(p_if, if_alt_nbr); + + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_IF); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_INTERFACE); + usbd_core_write_08b_to_descriptor_buf(p_dev, if_nbr); + usbd_core_write_08b_to_descriptor_buf(p_dev, if_alt_nbr); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if_alt->endpoint_nbr_total); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if->class_code); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if->class_sub_code); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_if->class_protocol_code); + +#if (USBD_CFG_STR_EN == 1) + str_ix = usbd_core_get_string_index(p_dev, p_if_alt->name_ptr); + usbd_core_write_08b_to_descriptor_buf(p_dev, str_ix); +#else + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); +#endif + + if (p_if_drv->interface_descriptor != NULL) { + // Add class specific IF desc. + p_if_drv->interface_descriptor(cfg_nbr_cur, + if_nbr, + if_alt_nbr, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + // Build EP Desc +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_alloc_map = p_if_alt->endpoint_table_map; + while (ep_alloc_map != 0x00u) { + ep_nbr = (uint8_t)__CLZ(__RBIT(ep_alloc_map)); + p_ep = p_if_alt->endpoint_table_ptrs[ep_nbr]; + + if ((p_if->class_code == SL_USBD_CLASS_CODE_AUDIO) + && (p_if->class_protocol_code == 0u) + && (((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_ISOC) + || ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_INTR))) { + // EP desc on audio class v1.0 has 2 additional fields. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_EP + 2u); + } else { + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_EP); + } + + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_ENDPOINT); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->address); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->attrib); + usbd_core_write_16b_to_descriptor_buf(p_dev, p_ep->max_pkt_size); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->interval); + + if ((p_if->class_code == SL_USBD_CLASS_CODE_AUDIO) + && (p_if->class_protocol_code == 0u) + && (((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_ISOC) + || ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_INTR))) { + // EP desc on audio class v1.0 has 2 additional fields. + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->sync_refresh); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->sync_addr); + } + + if (p_if_drv->endpoint_descriptor != NULL) { + // Add class specific EP desc. + p_if_drv->endpoint_descriptor(cfg_nbr_cur, + if_nbr, + if_alt_nbr, + p_ep->address, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + + SL_CLEAR_BIT(ep_alloc_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); + } +#else + p_ep = p_if_alt->endpoint_head_ptr; + + for (ep_nbr = 0u; ep_nbr < p_if_alt->endpoint_nbr_total; ep_nbr++) { + if ((p_if->class_code == SL_USBD_CLASS_CODE_AUDIO) + && (p_if->class_protocol_code == 0u) + && (((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_ISOC) + || ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_INTR))) { + // EP desc on audio class v1.0 has 2 additional fields. + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_EP + 2u); + } else { + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_LEN_EP); + } + + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_ENDPOINT); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->address); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->attrib); + usbd_core_write_16b_to_descriptor_buf(p_dev, p_ep->max_pkt_size); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->interval); + + if ((p_if->class_code == SL_USBD_CLASS_CODE_AUDIO) + && (p_if->class_protocol_code == 0u) + && (((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_ISOC) + || ((p_ep->attrib & SL_USBD_ENDPOINT_TYPE_MASK) == SL_USBD_ENDPOINT_TYPE_INTR))) { + // EP desc on audio class v1.0 has 2 additional fields. + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->sync_refresh); + usbd_core_write_08b_to_descriptor_buf(p_dev, p_ep->sync_addr); + } + + if (p_if_drv->endpoint_descriptor != NULL) { + // Add class specific EP desc. + p_if_drv->endpoint_descriptor(cfg_nbr_cur, + if_nbr, + if_alt_nbr, + p_ep->address, + p_if->class_arg_ptr, + p_if_alt->class_arg_ptr); + } + + p_ep = p_ep->next_ptr; + } +#endif + } + } + + return usbd_core_stop_descriptor_write(p_dev); +} + +/****************************************************************************************************//** + * usbd_core_send_string_descriptor() + * + * @brief Send string descriptor. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param str_ix String index. + * + * @param req_len Requested length by the host. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ + +#if (USBD_CFG_STR_EN == 1) +static sl_status_t usbd_core_send_string_descriptor(sli_usbd_device_t *p_dev, + uint8_t str_ix, + uint16_t req_len) +{ + const char *p_str; + size_t len; +#if (USBD_CFG_MS_OS_DESC_EN == 1) + uint8_t ix; +#endif + + usbd_core_start_descriptor_write(p_dev, req_len); + + switch (str_ix) { + case 0u: + usbd_core_write_08b_to_descriptor_buf(p_dev, 4u); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_STRING); + usbd_core_write_16b_to_descriptor_buf(p_dev, p_dev->device_config.lang_id); + break; + +#if (USBD_CFG_MS_OS_DESC_EN == 1) + case SLI_USBD_MICROSOFT_STR_IX: + usbd_core_write_08b_to_descriptor_buf(p_dev, SLI_USBD_MICROSOFT_STR_LEN); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_STRING); + + for (ix = 0u; ix < 7u; ix++) { + usbd_core_write_08b_to_descriptor_buf(p_dev, (uint8_t)usbd_microsoft_signature_str[ix]); + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); + } + + usbd_core_write_08b_to_descriptor_buf(p_dev, p_dev->str_microsoft_vendor_code); + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); + break; +#endif + + default: + p_str = usbd_core_get_string_descriptor(p_dev, str_ix - 1u); + if (p_str != NULL) { + len = sl_strlen((char *)p_str); + len = (2u * len) + 2u; + len = SLI_USBD_GET_MIN(len, 255u); + len = len - (len % 2u); + + usbd_core_write_08b_to_descriptor_buf(p_dev, (uint8_t)len); + usbd_core_write_08b_to_descriptor_buf(p_dev, SL_USBD_DESC_TYPE_STRING); + + while (*p_str != '\0') { + usbd_core_write_08b_to_descriptor_buf(p_dev, (uint8_t)*p_str); + usbd_core_write_08b_to_descriptor_buf(p_dev, 0u); + + p_str++; + } + } else { + return SL_STATUS_NULL_POINTER; + } + break; + } + + return usbd_core_stop_descriptor_write(p_dev); +} +#endif + +/****************************************************************************************************//** + * usbd_core_start_descriptor_write() + * + * @brief Start write operation in the descriptor buffer. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param req_len Requested length by the host. + *******************************************************************************************************/ +static void usbd_core_start_descriptor_write(sli_usbd_device_t *p_dev, + uint16_t req_len) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + p_dev->desc_buf_index = 0u; + p_dev->desc_buf_req_len = req_len; + CORE_EXIT_ATOMIC(); +} + +/****************************************************************************************************//** + * usbd_core_stop_descriptor_write() + * + * @brief Stop write operation in the descriptor buffer. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) This function might be called in two contexts: when a Get Descriptor standard request + * is received, or when a driver supporting standard request auto-reply queries the + * device, a configuration or a string descriptor. The descriptor needs to be sent on + * control endpoint 0 only if this function is called for a Get Descriptor standard + * request. If the function is called when a driver needs the descriptor, nothing has to + * be done. + *******************************************************************************************************/ +static sl_status_t usbd_core_stop_descriptor_write(sli_usbd_device_t *p_dev) +{ + uint32_t xfer_len; + sl_status_t status; + + status = SL_STATUS_OK; + + // See Note #1. + if (p_dev->actual_buf_ptr == p_dev->desc_buf_ptr) { + if (p_dev->desc_buf_index > 0u) { + uint32_t std_req_timeout; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + std_req_timeout = usbd_ptr->std_req_timeout_ms; + CORE_EXIT_ATOMIC(); + + status = sl_usbd_core_write_control_sync(&p_dev->desc_buf_ptr[0u], + (uint32_t)p_dev->desc_buf_index, + std_req_timeout, + (p_dev->desc_buf_req_len > 0u) ? true : false, + &xfer_len); + } + } + + return status; +} + +/****************************************************************************************************//** + * usbd_core_write_08b_to_descriptor_buf() + * + * @brief Write 8-bit value in the descriptor buffer. + * + * @param p_dev Pointer to device. + * + * @param val 8-bit value. + *******************************************************************************************************/ +static void usbd_core_write_08b_to_descriptor_buf(sli_usbd_device_t *p_dev, + uint8_t val) +{ + if (*(p_dev->desc_buf_status_ptr) == SL_STATUS_OK) { + usbd_core_write_to_descriptor_buf(p_dev, &val, 1u); + } +} + +/****************************************************************************************************//** + * sl_usbd_core_write_16b_to_descriptor_buf() + * + * @brief Write 16-bit value in the descriptor buffer. + * + * @param p_dev Pointer to device. + * + * @param val 16-bit value. + *******************************************************************************************************/ +static void usbd_core_write_16b_to_descriptor_buf(sli_usbd_device_t *p_dev, + uint16_t val) +{ + if (*(p_dev->desc_buf_status_ptr) == SL_STATUS_OK) { + uint8_t buf[2u]; + + buf[0u] = (uint8_t)(val & 0xFFu); + buf[1u] = (uint8_t)((val >> 8u) & 0xFFu); + + usbd_core_write_to_descriptor_buf(p_dev, &buf[0u], 2u); + } +} + +/****************************************************************************************************//** + * usbd_core_write_to_descriptor_buf() + * + * @brief USB device configuration write request. + * + * @param p_dev Pointer to device. + * + * @param p_buf Pointer to data buffer. + * + * @param len Buffer length. + * + * @note (1) This function might be called in two contexts: when a Get Descriptor standard request + * is received, or when a driver supporting standard request auto-reply queries the + * device, a configuration or a string descriptor. In the Get Descriptor standard + * request case, if the buffer is full, a transfer on control endpoint 0 is done, before + * resuming to fill the buffer. In the case of a driver supporting standard request + * auto-reply, if the buffer is full, an error is set and the function exits. + * + * @note (2) If an error is reported by sl_usbd_core_write_control_sync() during the construction of the descriptor, + * this pointer will store the error code, stop the rest of the data phase, skip the + * status phase and ensure that the control endpoint 0 is stalled to notify the host + * that an error has occurred. + *******************************************************************************************************/ +static void usbd_core_write_to_descriptor_buf(sli_usbd_device_t *p_dev, + const uint8_t *p_buf, + uint16_t len) +{ + uint8_t *p_desc; + uint8_t buf_cur_ix; + uint16_t len_req; + uint32_t xfer_len; + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + p_desc = p_dev->actual_buf_ptr; + buf_cur_ix = p_dev->desc_buf_index; + len_req = p_dev->desc_buf_req_len; + status = SL_STATUS_OK; + + while ((len_req != 0u) + && (len != 0u)) { + if (buf_cur_ix >= p_dev->desc_buf_max_len) { + // Send data in response to std req. See Note #1. + if (p_dev->actual_buf_ptr == p_dev->desc_buf_ptr) { + uint32_t std_req_timeout; + + CORE_ENTER_ATOMIC(); + std_req_timeout = usbd_ptr->std_req_timeout_ms; + CORE_EXIT_ATOMIC(); + + buf_cur_ix = 0u; + status = sl_usbd_core_write_control_sync(&p_dev->desc_buf_ptr[0u], + SLI_USBD_DESC_BUF_LEN, + std_req_timeout, + false, + &xfer_len); + if (status != SL_STATUS_OK) { + break; + } + } else { + // Buf provided by driver is too small. See Note #1. + len_req = 0u; + status = SL_STATUS_ALLOCATION_FAILED; + } + } else { + p_desc[buf_cur_ix] = *p_buf; + p_buf++; + len--; + len_req--; + buf_cur_ix++; + } + } + + CORE_ENTER_ATOMIC(); + p_dev->desc_buf_index = buf_cur_ix; + p_dev->desc_buf_req_len = len_req; + if (p_dev->desc_buf_status_ptr != NULL) { + // See Note #2. + *(p_dev->desc_buf_status_ptr) = status; + } + CORE_EXIT_ATOMIC(); +} + +/****************************************************************************************************//** + * usbd_core_get_configuration_structure() + * + * @brief Get configuration structure. + * + * @param p_dev Pointer to device struct. + * + * @param config_nbr Configuration number. + * + * @return Pointer to configuration structure, if no errors are returned. + * + * Pointer to NULL, if any errors are returned. + *******************************************************************************************************/ +static sli_usbd_configuration_t *usbd_core_get_configuration_structure(const sli_usbd_device_t *p_dev, + uint8_t config_nbr) +{ + sli_usbd_configuration_t *p_config; + uint8_t cfg_val; +#if (USBD_CFG_OPTIMIZE_SPD == 0) + uint8_t config_ix; +#endif + +#if (USBD_CFG_HS_EN == 1) + // SL_USBD_CONFIG_NBR_SPD_BIT will always be clear in FS. + cfg_val = config_nbr & (uint8_t)(~SL_USBD_CONFIG_NBR_SPD_BIT); +#else + cfg_val = config_nbr; +#endif + +#if (USBD_CFG_OPTIMIZE_SPD == 1) // Array implementation. +#if (USBD_CFG_HS_EN == 1) + if (SL_IS_BIT_SET(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT) == true) { + // Chk if cfg nbr is valid. + if (cfg_val >= p_dev->config_hs_total_nbr) { + return (NULL); + } + // Get HS cfg struct. + p_config = p_dev->config_hs_speed_table_ptrs[cfg_val]; + } else { +#endif + // Chk if cfg nbr is valid. + if (cfg_val >= p_dev->config_fs_total_nbr) { + return (NULL); + } + // Get FS cfg struct. + p_config = p_dev->config_fs_speed_table_ptrs[cfg_val]; +#if (USBD_CFG_HS_EN == 1) +} +#endif +#else // Linked-list implementation. +#if (USBD_CFG_HS_EN == 1) + if (SL_IS_BIT_SET(config_nbr, SL_USBD_CONFIG_NBR_SPD_BIT)) { + // Chk if cfg nbr is valid. + if (cfg_val >= p_dev->config_hs_total_nbr) { + return (NULL); + } + p_config = p_dev->config_hs_head_ptr; + } else { +#endif + // Chk if cfg nbr is valid. + if (cfg_val >= p_dev->config_fs_total_nbr) { + return (NULL); + } + p_config = p_dev->config_fs_head_ptr; +#if (USBD_CFG_HS_EN == 1) +} +#endif + + // Iterate thru list until to get cfg struct. + for (config_ix = 0u; config_ix < cfg_val; config_ix++) { + p_config = p_config->next_ptr; + } +#endif + + return (p_config); +} + +/****************************************************************************************************//** + * usbd_core_set_event() + * + * @brief Send an event to the core task. + * + * @param event Event code : + * SLI_USBD_EVENT_BUS_RESET reset. + * SLI_USBD_EVENT_BUS_SUSPEND suspend. + * SLI_USBD_EVENT_BUS_RESUME resume. + * SLI_USBD_EVENT_BUS_CONNECT Connect. + * SLI_USBD_EVENT_BUS_DISCONNECT Disconnect. + * SLI_USBD_EVENT_BUS_HS High speed. + * SLI_USBD_EVENT_ENDPOINT Endpoint. + * SLI_USBD_EVENT_SETUP Setup. + *******************************************************************************************************/ +static void usbd_core_set_event(sli_usbd_event_code_t event) +{ + sli_usbd_core_event_t core_event; + + core_event.type = event; + core_event.status = SL_STATUS_OK; + + sli_usbd_core_os_put_core_event(&core_event); +} + +/****************************************************************************************************//** + * Processes all core events and core operations + *******************************************************************************************************/ +void sli_usbd_core_task_handler(void) +{ + sli_usbd_core_event_t core_event; + sli_usbd_device_t *p_dev; + uint8_t ep_addr; + sli_usbd_event_code_t event; + sl_status_t xfer_status; + sl_status_t status; + +#if SL_USBD_AUTO_START_USB_DEVICE == 1 + sl_usbd_core_start_device(); +#endif + + // event loop + while (true) { + // Wait for an event. + status = sli_usbd_core_os_get_core_event((void *) &core_event); + if (status == SL_STATUS_OK) { + event = core_event.type; + p_dev = &usbd_ptr->device; + + // Decode event. + switch (event) { + // Bus Events + case SLI_USBD_EVENT_BUS_RESET: + case SLI_USBD_EVENT_BUS_RESUME: + case SLI_USBD_EVENT_BUS_CONNECT: + case SLI_USBD_EVENT_BUS_HS: + case SLI_USBD_EVENT_BUS_SUSPEND: + case SLI_USBD_EVENT_BUS_DISCONNECT: + usbd_core_process_event(p_dev, event); + break; + + // Endpoint Events + case SLI_USBD_EVENT_ENDPOINT: + if (p_dev->state == SL_USBD_DEVICE_STATE_SUSPENDED) { + p_dev->state = p_dev->state_prev; + } + ep_addr = core_event.endpoint_address; + xfer_status = core_event.status; + sl_usbd_core_endpoint_transfer_async(ep_addr, xfer_status); + break; + + // Setup Events + case SLI_USBD_EVENT_SETUP: + SLI_USBD_DBG_STATS_DEV_INC(device_setup_event_nbr); + if (p_dev->state == SL_USBD_DEVICE_STATE_SUSPENDED) { + p_dev->state = p_dev->state_prev; + } + usbd_core_stdreq_handler(p_dev); + break; + + default: + break; + } + } + } +} + +/****************************************************************************************************//** + * usbd_core_process_event() + * + * @brief Processes bus related events. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param event Bus related events : + * SLI_USBD_EVENT_BUS_RESET reset. + * SLI_USBD_EVENT_BUS_SUSPEND suspend. + * SLI_USBD_EVENT_BUS_RESUME resume. + * SLI_USBD_EVENT_BUS_CONNECT Connect. + * SLI_USBD_EVENT_BUS_DISCONNECT Disconnect. + * SLI_USBD_EVENT_BUS_HS High speed. + * + * @note (1) This prevents a suspend event to overwrite the internal status with a suspend state in + * the case of multiple suspend events in a row. + * + * @note (2) USB Spec 2.0 section 9.1.1.6 states "When suspended, the USB device maintains any + * internal status, including its address and configuration." + * + * @note (3) A suspend event is usually followed by a resume event when the bus activity comes back. + * But in some cases, after a suspend event, a reset event can be notified to the Core + * before a resume event. Thus, the internal state of the device should not be changed + * to the previous one. + *******************************************************************************************************/ +static void usbd_core_process_event(sli_usbd_device_t *p_dev, + sli_usbd_event_code_t event) +{ + CORE_DECLARE_IRQ_STATE; + + switch (event) { + case SLI_USBD_EVENT_BUS_RESET: + SLI_USBD_DBG_STATS_DEV_INC(device_reset_event_nbr); + SLI_USBD_LOG_VRB_TO(SLI_USBD_LOG_BUS_CH, ("USBD Bus: reset")); + + CORE_ENTER_ATOMIC(); + if (p_dev->conn_status == false) { + p_dev->conn_status = true; + CORE_EXIT_ATOMIC(); + + // Call application connect callback. + sl_usbd_on_bus_event(SL_USBD_EVENT_BUS_CONNECT); + } else { + CORE_EXIT_ATOMIC(); + } + + // Close ctrl EP. + sli_usbd_core_close_control_endpoint(); + + if (p_dev->config_cur_nbr != SL_USBD_CONFIG_NBR_NONE) { + // Close curr cfg. + usbd_core_unset_configuration(p_dev); + } + + // Open ctrl EP. + sli_usbd_core_open_control_endpoint(p_dev->endpoint_max_ctrl_pkt_size); + + // Set dev in default state, reset dev speed. + CORE_ENTER_ATOMIC(); + p_dev->address = 0u; + p_dev->state = SL_USBD_DEVICE_STATE_DEFAULT; + p_dev->speed = SL_USBD_DEVICE_SPEED_FULL; + CORE_EXIT_ATOMIC(); + + // Call application reset callback. + sl_usbd_on_bus_event(SL_USBD_EVENT_BUS_RESET); + + break; + + case SLI_USBD_EVENT_BUS_SUSPEND: + SLI_USBD_DBG_STATS_DEV_INC(device_suspend_event_nbr); + SLI_USBD_LOG_VRB_TO(SLI_USBD_LOG_BUS_CH, ("USBD Bus: suspend")); + + CORE_ENTER_ATOMIC(); + // See Note #1. + if (p_dev->state != SL_USBD_DEVICE_STATE_SUSPENDED) { + // Save cur state (see Note #2). + p_dev->state_prev = p_dev->state; + } + // Set suspended state. + p_dev->state = SL_USBD_DEVICE_STATE_SUSPENDED; + CORE_EXIT_ATOMIC(); + + // Call application suspend callback. + sl_usbd_on_bus_event(SL_USBD_EVENT_BUS_SUSPEND); + break; + + case SLI_USBD_EVENT_BUS_RESUME: + SLI_USBD_DBG_STATS_DEV_INC(device_resume_event_nbr); + SLI_USBD_LOG_VRB_TO(SLI_USBD_LOG_BUS_CH, ("USBD Bus: resume")); + + CORE_ENTER_ATOMIC(); + // See Note #3. + if (p_dev->state == SL_USBD_DEVICE_STATE_SUSPENDED) { + // Restore prev state. + p_dev->state = p_dev->state_prev; + } + CORE_EXIT_ATOMIC(); + + // Call application resume callback. + sl_usbd_on_bus_event(SL_USBD_EVENT_BUS_RESUME); + + break; + + case SLI_USBD_EVENT_BUS_CONNECT: + SLI_USBD_DBG_STATS_DEV_INC(device_conn_event_nbr); + SLI_USBD_LOG_VRB_TO(SLI_USBD_LOG_BUS_CH, ("USBD Bus: Connect")); + + CORE_ENTER_ATOMIC(); + // Set attached state. + p_dev->state = SL_USBD_DEVICE_STATE_ATTACHED; + p_dev->conn_status = true; + CORE_EXIT_ATOMIC(); + + // Call application connect callback. + sl_usbd_on_bus_event(SL_USBD_EVENT_BUS_CONNECT); + + break; + + case SLI_USBD_EVENT_BUS_DISCONNECT: + SLI_USBD_DBG_STATS_DEV_INC(device_disconnect_event_nbr); + SLI_USBD_LOG_VRB_TO(SLI_USBD_LOG_BUS_CH, ("USBD Bus: Disconnect")); + + // Close ctrl EP. + sli_usbd_core_close_control_endpoint(); + + if (p_dev->config_cur_nbr != SL_USBD_CONFIG_NBR_NONE) { + // Close curr cfg. + usbd_core_unset_configuration(p_dev); + } + + CORE_ENTER_ATOMIC(); + // Set default address. + p_dev->address = 0u; + // Dev is not attached. + p_dev->state = SL_USBD_DEVICE_STATE_INIT; + // No active cfg. + p_dev->config_cur_nbr = SL_USBD_CONFIG_NBR_NONE; + p_dev->conn_status = false; + CORE_EXIT_ATOMIC(); + + // Call application disconnect callback. + sl_usbd_on_bus_event(SL_USBD_EVENT_BUS_DISCONNECT); + + break; + + case SLI_USBD_EVENT_BUS_HS: + SLI_USBD_LOG_VRB_TO(SLI_USBD_LOG_BUS_CH, ("USBD Bus: High Speed detection")); +#if (USBD_CFG_HS_EN == 1) + CORE_ENTER_ATOMIC(); + p_dev->speed = SL_USBD_DEVICE_SPEED_HIGH; + if (p_dev->state == SL_USBD_DEVICE_STATE_SUSPENDED) { + p_dev->state = p_dev->state_prev; + } + CORE_EXIT_ATOMIC(); +#endif + break; + + case SLI_USBD_EVENT_ENDPOINT: + case SLI_USBD_EVENT_SETUP: + default: + break; + } +} + +/****************************************************************************************************//** + * usbd_core_get_interface_structure() + * + * @brief Gets the interface structure. + * + * @param p_cfg Pointer to configuration structure. + * + * @param if_nbr Interface number. + * + * @return Pointer to interface structure, if no errors are returned. + * + * Pointer to NULL, if any errors are returned. + *******************************************************************************************************/ +static sli_usbd_interface_t *usbd_core_get_interface_structure(const sli_usbd_configuration_t *p_config, + uint8_t if_nbr) +{ + sli_usbd_interface_t *p_if; +#if (USBD_CFG_OPTIMIZE_SPD == 0) + uint8_t if_ix; +#endif + + // Chk if IF nbr is valid. + if (if_nbr >= p_config->interface_nbr_total) { + return (NULL); + } + + // Get IF struct. +#if (USBD_CFG_OPTIMIZE_SPD == 1) + p_if = p_config->interface_table_ptrs[if_nbr]; +#else + p_if = p_config->interface_head_ptr; + + for (if_ix = 0u; if_ix < if_nbr; if_ix++) { + p_if = p_if->next_ptr; + } +#endif + + return (p_if); +} + +/****************************************************************************************************//** + * usbd_core_get_alt_interface_structure() + * + * @brief Gets the alternate setting interface structure. + * + * @param p_if Pointer to interface structure. + * + * @param if_alt_nbr Alternate setting interface number. + * + * @return Pointer to alternate setting interface structure, if no errors are returned. + * + * Pointer to NULL, if any errors are returned. + *******************************************************************************************************/ +static sli_usbd_alt_interface_t *usbd_core_get_alt_interface_structure(const sli_usbd_interface_t *p_if, + uint8_t if_alt_nbr) +{ + sli_usbd_alt_interface_t *p_if_alt; +#if (USBD_CFG_OPTIMIZE_SPD == 0) + uint8_t if_alt_ix; +#endif + + // Chk alt setting nbr. + if (if_alt_nbr >= p_if->alt_nbr_total) { + return (NULL); + } + + // Get alt IF struct. +#if (USBD_CFG_OPTIMIZE_SPD == 1) + p_if_alt = p_if->alt_table_ptrs[if_alt_nbr]; +#else + p_if_alt = p_if->alt_head_ptr; + + for (if_alt_ix = 0u; if_alt_ix < if_alt_nbr; if_alt_ix++) { + p_if_alt = p_if_alt->next_ptr; + } +#endif + + return (p_if_alt); +} + +/****************************************************************************************************//** + * usbd_core_open_alt_interface() + * + * @brief Opens all endpoints from the specified alternate setting. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param if_nbr Interface number. + * + * @param p_if_alt Pointer to alternate setting interface. + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + *******************************************************************************************************/ +static sl_status_t usbd_core_open_alt_interface(sli_usbd_device_t *p_dev, + uint8_t if_nbr, + const sli_usbd_alt_interface_t *p_if_alt) +{ + uint8_t ep_nbr; + uint8_t ep_phy_nbr; + bool valid; + sli_usbd_endpoint_info_t *p_ep; +#if (USBD_CFG_OPTIMIZE_SPD == 1) + uint32_t ep_alloc_map; +#endif + sl_status_t status; + CORE_DECLARE_IRQ_STATE; + + valid = true; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_alloc_map = p_if_alt->endpoint_table_map; + while (ep_alloc_map != 0x00u) { + ep_nbr = (uint8_t)__CLZ(__RBIT(ep_alloc_map)); + p_ep = p_if_alt->endpoint_table_ptrs[ep_nbr]; + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(p_ep->address); + + CORE_ENTER_ATOMIC(); + p_dev->endpoint_interface_table[ep_phy_nbr] = if_nbr; + CORE_EXIT_ATOMIC(); + + status = sli_usbd_core_open_endpoint(p_ep->address, + p_ep->max_pkt_size, + p_ep->attrib, + p_ep->interval); + if (status != SL_STATUS_OK) { + valid = false; + break; + } + + SL_CLEAR_BIT(ep_alloc_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); + } +#else + p_ep = p_if_alt->endpoint_head_ptr; + + for (ep_nbr = 0u; ep_nbr < p_if_alt->endpoint_nbr_total; ep_nbr++) { + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(p_ep->address); + + CORE_ENTER_ATOMIC(); + p_dev->endpoint_interface_table[ep_phy_nbr] = if_nbr; + CORE_EXIT_ATOMIC(); + + status = sli_usbd_core_open_endpoint(p_ep->address, + p_ep->max_pkt_size, + p_ep->attrib, + p_ep->interval); + if (status != SL_STATUS_OK) { + valid = false; + break; + } + + p_ep = p_ep->next_ptr; + } +#endif + + if (valid == true) { + status = SL_STATUS_OK; + } else { + usbd_core_close_alt_interface(p_dev, p_if_alt); + } + + return status; +} + +/****************************************************************************************************//** + * usbd_core_close_alt_interface() + * + * @brief Closes all endpoints from the specified alternate setting. + * + * @param p_dev Pointer to USB device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param p_if_alt Pointer to alternate setting interface. + *******************************************************************************************************/ +static void usbd_core_close_alt_interface(sli_usbd_device_t *p_dev, + const sli_usbd_alt_interface_t *p_if_alt) +{ + uint8_t ep_nbr; + uint8_t ep_phy_nbr; + sli_usbd_endpoint_info_t *p_ep; +#if (USBD_CFG_OPTIMIZE_SPD == 1) + uint32_t ep_alloc_map; +#endif + CORE_DECLARE_IRQ_STATE; + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + ep_alloc_map = p_if_alt->endpoint_table_map; + while (ep_alloc_map != 0x00u) { + ep_nbr = (uint8_t)__CLZ(__RBIT(ep_alloc_map)); + p_ep = p_if_alt->endpoint_table_ptrs[ep_nbr]; + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(p_ep->address); + + CORE_ENTER_ATOMIC(); + p_dev->endpoint_interface_table[ep_phy_nbr] = SL_USBD_INTERFACE_NBR_NONE; + CORE_EXIT_ATOMIC(); + + sli_usbd_core_close_endpoint(p_ep->address); + + SL_CLEAR_BIT(ep_alloc_map, SLI_USBD_SINGLE_BIT_MASK_32(ep_nbr)); + } +#else + p_ep = p_if_alt->endpoint_head_ptr; + + for (ep_nbr = 0u; ep_nbr < p_if_alt->endpoint_nbr_total; ep_nbr++) { + ep_phy_nbr = SL_USBD_ENDPOINT_ADDR_TO_PHY(p_ep->address); + + CORE_ENTER_ATOMIC(); + p_dev->endpoint_interface_table[ep_phy_nbr] = SL_USBD_INTERFACE_NBR_NONE; + CORE_EXIT_ATOMIC(); + + sli_usbd_core_close_endpoint(p_ep->address); + + p_ep = p_ep->next_ptr; + } +#endif +} + +/****************************************************************************************************//** + * usbd_core_get_interface_group_structure() + * + * @brief Gets the interface group structure. + * + * @param p_cfg Pointer to configuration structure. + * + * @param if_grp_nbr Interface number. + * + * @return Pointer to interface group structure, if no errors are returned. + * + * Pointer to NULL, if any errors are returned. + *******************************************************************************************************/ +static sli_usbd_interface_group_t *usbd_core_get_interface_group_structure(const sli_usbd_configuration_t *p_config, + uint8_t if_grp_nbr) +{ + sli_usbd_interface_group_t *p_if_grp; +#if (USBD_CFG_OPTIMIZE_SPD == 0) + uint8_t if_grp_ix; +#endif + +#if (USBD_CFG_OPTIMIZE_SPD == 1) + p_if_grp = p_config->interface_group_table_ptrs[if_grp_nbr]; +#else + p_if_grp = p_config->interface_group_head_ptr; + + for (if_grp_ix = 0u; if_grp_ix < if_grp_nbr; if_grp_ix++) { + p_if_grp = p_if_grp->next_ptr; + } +#endif + + return (p_if_grp); +} + +/****************************************************************************************************//** + * usbd_core_add_string() + * + * @brief Adds the string to the USB device. + * + * @param p_dev Pointer to device structure. + * + * @param ----- Argument validated in the caller(s). + * + * @param p_str Pointer to string to add (see Note #1). + * + * @return Returns SL_STATUS_OK on success or another SL_STATUS code on failure. + * + * @note (1) USB spec 2.0 chapter 9.5 states "Where appropriate, descriptors contain references + * to string descriptors that provide displayable information describing a descriptor + * in human-readable form. The inclusion of string descriptors is optional. However, + * the reference fields within descriptors are mandatory. If a device does not support + * string descriptors, string reference fields must be reset to zero to indicate no + * string descriptor is available. + * + * Since string descriptors are optional, 'p_str' could be a NULL pointer. + *******************************************************************************************************/ + +#if (USBD_CFG_STR_EN == 1) +static sl_status_t usbd_core_add_string(sli_usbd_device_t *p_dev, + const char *p_str) +{ + uint8_t str_ix; + CORE_DECLARE_IRQ_STATE; + + // Return if NULL ptr. + if (p_str == NULL) { + return SL_STATUS_NULL_POINTER; + } + + for (str_ix = 0u; str_ix < p_dev->str_max_index; str_ix++) { + if (p_str == p_dev->str_descriptor_table[str_ix]) { + // Str already stored in tbl. + return SL_STATUS_OK; + } + } + + CORE_ENTER_ATOMIC(); + // Get curr str tbl ix. + str_ix = p_dev->str_max_index; + + // Chk if str can be stored in tbl. + if (str_ix >= usbd_ptr->str_quantity_per_device) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_ALLOCATION_FAILED; + } + + p_dev->str_descriptor_table[str_ix] = (char *)p_str; + p_dev->str_max_index++; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} +#endif + +/****************************************************************************************************//** + * usbd_core_get_string_descriptor() + * + * @brief Gets the string pointer. + * + * @param p_dev Pointer to device. + * + * @param ----- Argument validate by the caller(s). + * + * @param str_nbr Number of the string to obtain. + * + * @return Pointer to requested string, if no errors are returned. + * + * Pointer to NULL, if any errors are returned. + *******************************************************************************************************/ + +#if (USBD_CFG_STR_EN == 1) +static const char *usbd_core_get_string_descriptor(const sli_usbd_device_t *p_dev, + uint8_t str_nbr) +{ + const char *p_str; + + if (str_nbr > p_dev->str_max_index) { + return (NULL); + } + + p_str = p_dev->str_descriptor_table[str_nbr]; + return (p_str); +} +#endif + +/****************************************************************************************************//** + * usbd_core_get_string_index() + * + * @brief Get string index. + * + * @param p_dev Pointer to device. + * + * @param ----- Argument validated in 'USBD_DevSetupPkt()' before posting the event to queue. + * + * @param p_str Pointer to string. + * + * @return String index. + *******************************************************************************************************/ + +#if (USBD_CFG_STR_EN == 1) +static uint8_t usbd_core_get_string_index(const sli_usbd_device_t *p_dev, + const char *p_str) +{ + uint8_t str_ix; + + // Return if a NULL pointer. + if (p_str == NULL) { + return (0u); + } + + for (str_ix = 0u; str_ix < p_dev->str_max_index; str_ix++) { + if (p_str == p_dev->str_descriptor_table[str_ix]) { + // Str already stored in tbl. + return (str_ix + 1u); + } + } + + return (0u); +} +#endif + +// clang-format on From 86d4c93959d15c58eccc0813607bec8e6f5f7855 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 23 Jun 2023 12:19:52 +0100 Subject: [PATCH 420/572] Improvements in WINUSB init - Code checks for USB core started and stops and restarts as needed. - Code is now aware if a debugger is attached to the execution engine, if it is no USB Core restart happens. - Minor fixes in code style. --- .../autogen/sl_usbd_class_vendor_instances.c | 89 ++++++++++++++----- 1 file changed, 67 insertions(+), 22 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index d8f8c354c2..a812106106 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -7,18 +7,19 @@ //**************************************************************************** // Includes. -#include "sl_status.h" +#include #include #include #include -#include "sl_usbd_class_hid.h" -#include "sl_usbd_class_vendor.h" +#include +#include -/* template headers */ +// template headers #include #include +#include -/* include config file for the instances */ +// include config file for the instances #include @@ -98,6 +99,9 @@ sl_status_t sli_usbd_vendor_winusb_init() uint8_t class_number = 0; uint8_t config_number = 0; + sl_usbd_device_state_t deviceState; + bool needToReinit = false; + sl_status_t returnStatus = SL_STATUS_OK; char *configs = NULL; char *token = NULL; @@ -108,6 +112,21 @@ sl_status_t sli_usbd_vendor_winusb_init() return SL_STATUS_OK; } + // get current device state + sl_usbd_core_get_device_state(&deviceState); + + if (deviceState > SL_USBD_DEVICE_STATE_INIT) + { + // device is already initialized, stop USB core, **ONLY** if there isn't a debugger connected + if (!DebuggerIsConnected()) + { + sl_usbd_core_stop_device(); + + // flag to reinit + needToReinit = true; + } + } + /* configs to attach the class instance to */ configs = SL_USBD_VENDOR_WINUSB_CONFIGURATIONS; @@ -122,7 +141,10 @@ sl_status_t sli_usbd_vendor_winusb_init() SL_STATUS_OK) { // error creating instance - return SL_STATUS_FAIL; + returnStatus = SL_STATUS_FAIL; + + // done here + goto exit; } /* store class number globally */ @@ -134,7 +156,10 @@ sl_status_t sli_usbd_vendor_winusb_init() if (sl_usbd_vendor_is_enabled(class_number, &classIsEnabled) != SL_STATUS_OK) { // error getting class enabled status - return SL_STATUS_FAIL; + returnStatus = SL_STATUS_FAIL; + + // done here + goto exit; } if (classIsEnabled) @@ -144,10 +169,10 @@ sl_status_t sli_usbd_vendor_winusb_init() // usbd_vendor_disable(sl_usbd_configuration_config0_number, void *p_if_class_arg) } - /* tokenize configs by "," and spaces */ + // tokenize configs by "," and spaces token = strtok(configs, ", "); - /* loop over tokens */ + // loop over tokens while (token != NULL) { @@ -158,7 +183,10 @@ sl_status_t sli_usbd_vendor_winusb_init() if (sl_usbd_vendor_add_to_configuration(class_number, config_number) != SL_STATUS_OK) { // error adding class to configuration - return SL_STATUS_FAIL; + returnStatus = SL_STATUS_FAIL; + + // done here + goto exit; } } @@ -176,18 +204,35 @@ sl_status_t sli_usbd_vendor_winusb_init() #endif // add device class GUID to WinUSB properties - sl_usbd_vendor_add_microsoft_ext_property( - class_number, - SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, - (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, - DEVICEINTERFACE_GUID_PROP_NAME_LEN, - (const uint8_t *)UsbClassVendorDeviceInterfaceGuid, - sizeof(UsbClassVendorDeviceInterfaceGuid)); - - // all good here, update flag - usbdVendorWinusbInited = true; - - return SL_STATUS_OK; + if (sl_usbd_vendor_add_microsoft_ext_property( + class_number, + SL_USBD_MICROSOFT_PROPERTY_TYPE_REG_SZ, + (const uint8_t *)DEVICEINTERFACE_GUID_PROP_NAME, + DEVICEINTERFACE_GUID_PROP_NAME_LEN, + (const uint8_t *)UsbClassVendorDeviceInterfaceGuid, + sizeof(UsbClassVendorDeviceInterfaceGuid)) != SL_STATUS_OK) + { + // error adding GUID property + returnStatus = SL_STATUS_FAIL; + + // done here + goto exit; + } + else + { + // all good here, update flag + usbdVendorWinusbInited = true; + } + +exit: + + // reinit USB core if needed + if (needToReinit) + { + sl_usbd_core_start_device(); + } + + return returnStatus; } void sl_usbd_vendor_winusb_on_enable_event(void) From cf56170051ce17fefd59c21a2f783078a7291ec6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 26 Jun 2023 13:35:50 +0100 Subject: [PATCH 421/572] Fix unwanted CMake debug message --- .../FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake index 08e87d1c1c..c7ced8d93c 100644 --- a/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake +++ b/CMake/Modules/FindCom.SkyworksInc.NanoFramework.Devices.Spi.cmake @@ -40,9 +40,9 @@ foreach(SRC_FILE ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRCS}) CMAKE_FIND_ROOT_PATH_BOTH ) - #if (BUILD_VERBOSE) + if (BUILD_VERBOSE) message("${SRC_FILE} >> ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE}") - #endif() + endif() list(APPEND Com.SkyworksInc.NanoFramework.Devices.Spi_SOURCES ${Com.SkyworksInc.NanoFramework.Devices.Spi_SRC_FILE}) From 4638cb53a03e81cb8d33fb5448be63477d648089 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sat, 22 Jul 2023 11:30:20 -0500 Subject: [PATCH 422/572] Sky_EVB: add more standard defaults to .h; improve documentation; define default USB device string --- .../AzureRTOS/SiliconLabs/SKY_EVB/README.md | 45 +++++++++---------- .../SKY_EVB/config/sl_usbd_device_config.h | 2 +- .../target_com_sky_nf_dev_i2c_config.cpp | 10 ++--- .../target_com_sky_nf_dev_spi_config.cpp | 20 ++++----- .../SKY_EVB/target_nano_gg_adc_config.h | 1 + .../SKY_EVB/target_system_device_i2c_config.h | 1 + .../target_system_device_spi_config.cpp | 20 ++++----- .../SKY_EVB/target_system_device_spi_config.h | 4 ++ 8 files changed, 52 insertions(+), 51 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md index 30d3335c40..0262029c2d 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md @@ -1,31 +1,28 @@ -# Skyworks EVB featuring Silabs EFM32 Giant Gecko GG11 +# Skyworks EEVB featuring SiLabs EFM32 Giant Gecko GG11 -## ADC channels +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8050344361/EEVB+Controller+Board+Software+Control -ADC has enabled the following channels: -0 - reading from PA15 (MCU_ADC1) -1 - reading from PE15 (MCU_ADC1) -2 - reading from PE14 (MCU_ADC2) -3 - reading from PE13 (MCU_ADC3) -4 - reading from PE12 (MCU_ADC4) -5 - reading from PE11 (MCU_ADC5) -1 - internal temperature -2 - VCC +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB -## I2C +## Key Files -I2C0 (this is referenced as I2C1 in C#) -SCL is: PA1 -SDA is: PA0 +CMakePresets.json + Enable packages, targets, naming, etc. -I2C1 (this is referenced as I2C2 in C#) -SCL is: PC5 -SDA is: PC4 +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI -## SPI +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED -US1 (this is referenced as SPI2 in C#) -SCK: PD2 -MOSI: PD0 -MISO: PD1 -CS: PD3 diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h index 5c220728b9..1b672dc998 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h @@ -33,7 +33,7 @@ extern char *UsbSerialNumber[]; // Device Product Name // Device product string. // OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen -#define SL_USBD_DEVICE_PRODUCT_STRING "" +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" // Device Serial Number // Device serial number string. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp index 37dc3dbc9f..45f236e7a8 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp @@ -9,9 +9,8 @@ // I2C0 // ////////// -// pin configuration for I2C0 -// port for I2C0_SCL is: PA1 -// port for I2C0_SDA is: PA0 +// SCL: PA1 +// SDA: PA0 // GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) @@ -20,9 +19,8 @@ I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) // I2C1 // ////////// -// pin configuration for I2C1 -// port for I2C1_SCL is: PC5 -// port for I2C1_SDA is: PC4 +// SCL: PC5 +// SDA: PC4 // GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp index bef6c57e2b..4a303f4f39 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp @@ -9,11 +9,11 @@ // SPI1 // ////////// -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI1_SCK: PD2, location 1 -// SPI1_MOSI: PD0, location 1 -// SPI1_MISO: PD1, location 1 -// SPI1_CS: PD3, location 1 +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet INIT_SPI_CONFIG(1, 1, 1, 1, 1) @@ -22,11 +22,11 @@ INIT_SPI_CONFIG(1, 1, 1, 1, 1) // SPI2 // ////////// -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI2_SCK: PF8, location 1 -// SPI2_MOSI: PF6, location 1 -// SPI2_MISO: PF7, location 1 -// SPI2_CS: PF9, location 1 +// USART2 +// SCK: PF8 +// MOSI: PF6 +// MISO: PF7 +// CS: PF9 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet INIT_SPI_CONFIG(2, 4, 4, 4, 4) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h index 9423e913ff..0aece00b26 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h @@ -4,3 +4,4 @@ // #define GECKO_USE_ADC0 TRUE +#define GECKO_USE_ADC1 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h index ff99df51a3..654d7141ad 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h @@ -2,3 +2,4 @@ #define GECKO_USE_I2C0 TRUE #define GECKO_USE_I2C1 TRUE +#define GECKO_USE_I2C2 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp index 28ce292b35..09360b8d8e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp @@ -9,11 +9,11 @@ // SPI1 // ////////// -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI1_SCK: PD2, location 1 -// SPI1_MOSI: PD0, location 1 -// SPI1_MISO: PD1, location 1 -// SPI1_CS: PD3, location 1 +// USART1 +// SPI1_SCK: PD2 +// SPI1_MOSI: PD0 +// SPI1_MISO: PD1 +// SPI1_CS: PD3 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet INIT_SPI_CONFIG(1, 1, 1, 1) @@ -22,11 +22,11 @@ INIT_SPI_CONFIG(1, 1, 1, 1) // SPI2 // ////////// -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI2_SCK: PF8, location 1 -// SPI2_MOSI: PF6, location 1 -// SPI2_MISO: PF7, location 1 -// SPI2_CS: PF9, location 1 +// USART2 +// SPI2_SCK: PF8 +// SPI2_MOSI: PF6 +// SPI2_MISO: PF7 +// SPI2_CS: PF9 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet INIT_SPI_CONFIG(2, 4, 4, 4) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h index 409945557b..1ff4bd6324 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h @@ -3,5 +3,9 @@ // See LICENSE file in the project root for full license information. // +#define GECKO_USE_SPI0 FALSE #define GECKO_USE_SPI1 TRUE #define GECKO_USE_SPI2 TRUE +#define GECKO_USE_SPI3 FALSE +#define GECKO_USE_SPI4 FALSE +#define GECKO_USE_SPI5 FALSE From f90d54d547dcf9bc16e699f525567ac17ab54d79 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sat, 22 Jul 2023 11:54:15 -0500 Subject: [PATCH 423/572] SKY_Si5575_CEVB: initial commit --- .../SKY_SI5575_CEVB/CMakeLists.txt | 76 ++++ .../SKY_SI5575_CEVB/CMakePresets.json | 79 ++++ .../SiliconLabs/SKY_SI5575_CEVB/README.md | 28 ++ .../autogen/sl_device_init_clocks.c | 28 ++ .../autogen/sl_event_handler.c | 48 +++ .../SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c | 91 +++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 ++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 ++ .../autogen/sl_usbd_class_hid_instances.c | 277 ++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 32 ++ .../autogen/sl_usbd_configuration_instances.c | 61 ++++ .../autogen/sl_usbd_configuration_instances.h | 18 + .../SiliconLabs/SKY_SI5575_CEVB/bspconfig.h | 9 + .../SKY_SI5575_CEVB/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 123 +++++++ .../common/Device_BlockStorage.c | 123 +++++++ .../common/tx_initialize_low_level.S | 239 ++++++++++++ .../SKY_SI5575_CEVB/config/pin_config.h | 259 +++++++++++++ .../config/sl_board_control_config.h | 112 ++++++ .../config/sl_device_init_hfrco_config.h | 27 ++ .../config/sl_device_init_hfxo_config.h | 43 +++ .../config/sl_device_init_lfrco_config.h | 34 ++ .../config/sl_device_init_lfxo_config.h | 37 ++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++ .../config/sl_iostream_usart_vcom_config.h | 112 ++++++ .../SKY_SI5575_CEVB/config/sl_memory_config.h | 13 + .../config/sl_uartdrv_usart_vcom_config.h | 85 +++++ .../config/sl_usbd_class_acm0_config.h | 53 +++ .../config/sl_usbd_class_hid0_config.h | 143 ++++++++ .../config/sl_usbd_class_winusb_config.h | 59 +++ .../config/sl_usbd_config0_config.h | 51 +++ .../config/sl_usbd_core_config.h | 199 ++++++++++ .../config/sl_usbd_device_config.h | 60 +++ .../SKY_SI5575_CEVB/config/uartdrv_config.h | 114 ++++++ .../SiliconLabs/SKY_SI5575_CEVB/launch.json | 83 +++++ .../SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ++++++++++++ .../nanoBooter/efm32gg11b_booter.ld | 235 ++++++++++++ .../SKY_SI5575_CEVB/nanoBooter/main.c | 180 +++++++++ .../nanoBooter/target_board.h.in | 18 + .../SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt | 15 + .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 +++++++++++++ .../SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld | 246 +++++++++++++ .../SKY_SI5575_CEVB/nanoCLR/main.c | 203 +++++++++++ .../SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp | 8 + .../SKY_SI5575_CEVB/nanoCLR/target_board.h.in | 18 + .../SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c | 244 +++++++++++++ .../SKY_SI5575_CEVB/target_BlockStorage.c | 19 + .../SKY_SI5575_CEVB/target_BlockStorage.h | 12 + .../target_com_sky_nf_dev_i2c_config.cpp | 26 ++ .../target_com_sky_nf_dev_i2c_config.h | 4 + .../target_com_sky_nf_dev_spi_config.cpp | 45 +++ .../target_com_sky_nf_dev_spi_config.h | 8 + .../SKY_SI5575_CEVB/target_common.c | 27 ++ .../SKY_SI5575_CEVB/target_common.h.in | 52 +++ .../target_nano_gg_adc_config.cpp | 46 +++ .../target_nano_gg_adc_config.h | 7 + .../target_nf_dev_onewire_config.cpp | 8 + .../target_nf_dev_onewire_config.h | 11 + .../SKY_SI5575_CEVB/target_stdio_config.c | 7 + .../SKY_SI5575_CEVB/target_stdio_config.h | 5 + .../target_system_device_adc_config.cpp | 6 + .../target_system_device_adc_config.h | 6 + .../target_system_device_i2c_config.cpp | 32 ++ .../target_system_device_i2c_config.h | 8 + .../target_system_device_pwm_config.cpp | 17 + .../target_system_device_spi_config.cpp | 35 ++ .../target_system_device_spi_config.h | 9 + .../target_system_io_ports_config.cpp | 4 + .../target_system_io_ports_config.h | 5 + .../SKY_SI5575_CEVB/target_tx_user.h | 206 +++++++++++ .../SKY_SI5575_CEVB/target_ux_user.h | 345 ++++++++++++++++++ 73 files changed, 5653 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/README.md create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/bspconfig.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/tx_initialize_low_level.S create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_hid0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_winusb_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_ux_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json new file mode 100644 index 0000000000..789b8736d5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json @@ -0,0 +1,79 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_SI5575_CEVB_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "SKY_SI5575_CEVB", + "TARGET_NAME": "SKY_SI5575_CEVB_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON" + } + }, + { + "name": "SKY_SI5575_CEVB_Release", + "inherits": [ + "SKY_SI5575_CEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_SI5575_CEVB", + "NF_BUILD_RTM": "ON" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_SI5575_CEVB_Debug", + "displayName": "SKY_SI5575_CEVB_Debug", + "configurePreset": "SKY_SI5575_CEVB_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_SI5575_CEVB_Release", + "displayName": "SKY_SI5575_CEVB_Release", + "configurePreset": "SKY_SI5575_CEVB_Release" + } + ] +} \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/README.md b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/README.md new file mode 100644 index 0000000000..2fa32a045f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/README.md @@ -0,0 +1,28 @@ +# Skyworks Si5575 CEVB featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8175353962/Si5575+CEVB+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage.c new file mode 100644 index 0000000000..09982097e3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 66}, + + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..debd4df8ef --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[32 + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/main.c new file mode 100644 index 0000000000..0787f4a6a5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/main.c @@ -0,0 +1,180 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..d17abebca3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/main.c new file mode 100644 index 0000000000..6661c9eb80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/main.c @@ -0,0 +1,203 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + // Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + clrSettings.RevertToBooterOnFault = true; + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..6cb49e27e6 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,45 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 1, 1, 1, 1) + +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(3, 0, 0, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..bdfea3503d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..32147d6ec7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.cpp @@ -0,0 +1,46 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..6ed4dd99fa --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..74d8b5da5b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6e7b275464 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.h new file mode 100644 index 0000000000..c81f83afe3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +/* + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.h new file mode 100644 index 0000000000..3918070d91 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/* +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From 7d533e1aef467e56a84d1a9bfece4ea8840b19e8 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sat, 22 Jul 2023 12:22:47 -0500 Subject: [PATCH 424/572] SKY_Si5575_CEVB: add build target --- .github/workflows/SKY-BUILDS.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/SKY-BUILDS.txt b/.github/workflows/SKY-BUILDS.txt index 3320148d76..b170ed2b85 100644 --- a/.github/workflows/SKY-BUILDS.txt +++ b/.github/workflows/SKY-BUILDS.txt @@ -1,4 +1,5 @@ # Format is: # Target,Preset SKY_EVB,SKY_EEVB -SKY_EVB,SKY_EEVB_STD_SIF \ No newline at end of file +SKY_EVB,SKY_EEVB_STD_SIF +SKY_Si5575_CEVB,SKY_Si5575_CEVB \ No newline at end of file From 8098f33eaac68b609e60ef14049dbfe9fbd6164a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sat, 22 Jul 2023 12:23:01 -0500 Subject: [PATCH 425/572] SKY_Si5575_CEVB: add build target --- .github/workflows/Build_SKY_EEVB_Debug.yaml | 2 +- .github/workflows/Build_SKY_EEVB_Release.yaml | 2 +- .github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml | 2 +- .github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml | 2 +- .github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml | 11 +++++++++++ .github/workflows/SKY-BUILDS.txt | 8 +++++--- 6 files changed, 20 insertions(+), 7 deletions(-) create mode 100644 .github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml diff --git a/.github/workflows/Build_SKY_EEVB_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Debug.yaml index 0718f262a8..b26c649979 100644 --- a/.github/workflows/Build_SKY_EEVB_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_Debug.yaml @@ -4,7 +4,7 @@ on: workflow_dispatch jobs: - build_SKY_EEVB: + build_SKY_EEVB_Debug: name: Build SKY_EEVB_Debug uses: ./.github/workflows/skyworks_evb_build.yaml with: diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Build_SKY_EEVB_Release.yaml index 7fdc5252b2..53ce646496 100644 --- a/.github/workflows/Build_SKY_EEVB_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_Release.yaml @@ -4,7 +4,7 @@ on: workflow_dispatch jobs: - build_SKY_EEVB: + build_SKY_EEVB_Release: name: Build SKY_EEVB_Release uses: ./.github/workflows/skyworks_evb_build.yaml with: diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml index b0132c3bab..bf0ef7a076 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -4,7 +4,7 @@ on: workflow_dispatch jobs: - build_SKY_EEVB: + build_SKY_EEVB_STD_SIF_Debug: name: Build SKY_EEVB_STD_SIF_Debug uses: ./.github/workflows/skyworks_evb_build.yaml with: diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml index c8cc4ff60b..a5708c1c12 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml +++ b/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -4,7 +4,7 @@ on: workflow_dispatch jobs: - build_SKY_EEVB: + build_SKY_EEVB_STD_SIF_Release: name: Build SKY_EEVB_STD_SIF_Release uses: ./.github/workflows/skyworks_evb_build.yaml with: diff --git a/.github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml b/.github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml new file mode 100644 index 0000000000..d26c07097a --- /dev/null +++ b/.github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_Si5575_CEVB_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_Si5575_CEVB_Debug: + name: Build SKY_Si5575_CEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_Si5575_CEVB_Debug' diff --git a/.github/workflows/SKY-BUILDS.txt b/.github/workflows/SKY-BUILDS.txt index b170ed2b85..8f2171895c 100644 --- a/.github/workflows/SKY-BUILDS.txt +++ b/.github/workflows/SKY-BUILDS.txt @@ -1,5 +1,7 @@ # Format is: # Target,Preset -SKY_EVB,SKY_EEVB -SKY_EVB,SKY_EEVB_STD_SIF -SKY_Si5575_CEVB,SKY_Si5575_CEVB \ No newline at end of file +SKY_EVB,SKY_EEVB_Debug +SKY_EVB,SKY_EEVB_Release +SKY_EVB,SKY_EEVB_STD_SIF_Debug +SKY_EVB,SKY_EEVB_STD_SIF_Release +SKY_Si5575_CEVB,SKY_Si5575_CEVB_Debug \ No newline at end of file From 980dc1ca4a7897c4dcb1891c627eb3d5be28940b Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 08:10:35 -0500 Subject: [PATCH 426/572] SKY_Si5575_CEVB: fix case error in preset name --- .../SKY_SI5575_CEVB/CMakePresets.json | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json index 789b8736d5..c7b19bce4a 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "SKY_SI5575_CEVB_Debug", + "name": "SKY_Si5575_CEVB_Debug", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -15,8 +15,8 @@ ], "hidden": false, "cacheVariables": { - "TARGET_BOARD": "SKY_SI5575_CEVB", - "TARGET_NAME": "SKY_SI5575_CEVB_Debug", + "TARGET_BOARD": "SKY_Si5575_CEVB", + "TARGET_NAME": "SKY_Si5575_CEVB_Debug", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", @@ -51,13 +51,13 @@ } }, { - "name": "SKY_SI5575_CEVB_Release", + "name": "SKY_Si5575_CEVB_Release", "inherits": [ - "SKY_SI5575_CEVB_Debug" + "SKY_Si5575_CEVB_Debug" ], "hidden": false, "cacheVariables": { - "TARGET_NAME": "SKY_SI5575_CEVB", + "TARGET_NAME": "SKY_Si5575_CEVB", "NF_BUILD_RTM": "ON" } } @@ -65,15 +65,15 @@ "buildPresets": [ { "inherits": "base-user", - "name": "SKY_SI5575_CEVB_Debug", - "displayName": "SKY_SI5575_CEVB_Debug", - "configurePreset": "SKY_SI5575_CEVB_Debug" + "name": "SKY_Si5575_CEVB_Debug", + "displayName": "SKY_Si5575_CEVB_Debug", + "configurePreset": "SKY_Si5575_CEVB_Debug" }, { "inherits": "base-user", - "name": "SKY_SI5575_CEVB_Release", - "displayName": "SKY_SI5575_CEVB_Release", - "configurePreset": "SKY_SI5575_CEVB_Release" + "name": "SKY_Si5575_CEVB_Release", + "displayName": "SKY_Si5575_CEVB_Release", + "configurePreset": "SKY_Si5575_CEVB_Release" } ] } \ No newline at end of file From 6e84b4033a6d18f2300ff34f680d343d07458313 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 08:19:58 -0500 Subject: [PATCH 427/572] SKY_Si5575_CEVB: force rename for case fix --- .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/CMakeLists.txt | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/CMakePresets.json | 0 .../SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/bspconfig.h | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/uartdrv_config.h | 0 .../SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/main.c | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/usb_hid_app.c | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_BlockStorage.c | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_common.c | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_stdio_config.c | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_i2c_config.cpp | 0 .../target_system_device_i2c_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_device_spi_config.cpp | 0 .../target_system_device_spi_config.h | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_tx_user.h | 0 .../{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_ux_user.h | 0 73 files changed, 0 insertions(+), 0 deletions(-) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/CMakePresets.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_device_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_SI5575_CEVB => SKY_Si5575_CEVB1}/target_ux_user.h (100%) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakePresets.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakePresets.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/README.md b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/README.md rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/launch.json rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_device_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_SI5575_CEVB/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_ux_user.h From 7804559271a748422a1b0272ee743ca09b27c522 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 08:22:32 -0500 Subject: [PATCH 428/572] SKY_Si5575_CEVB: finish rename for case fix --- .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/CMakeLists.txt | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/CMakePresets.json | 0 .../SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/bspconfig.h | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/uartdrv_config.h | 0 .../SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/main.c | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/usb_hid_app.c | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_BlockStorage.c | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_common.c | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_stdio_config.c | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_i2c_config.cpp | 0 .../target_system_device_i2c_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_device_spi_config.cpp | 0 .../target_system_device_spi_config.h | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_tx_user.h | 0 .../{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_ux_user.h | 0 73 files changed, 0 insertions(+), 0 deletions(-) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/CMakePresets.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_device_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB1 => SKY_Si5575_CEVB}/target_ux_user.h (100%) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/README.md rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/launch.json rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_device_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB1/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_ux_user.h From 2d0ea1833fdb7b65c577d546427a1743f19e3da9 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 08:25:56 -0500 Subject: [PATCH 429/572] Deprecate some nanoCLR targets --- .../Build_SKY_EEVB_Release.yaml | 0 .../Build_SKY_EEVB_STD_SIF_Debug.yaml | 22 +++++++++---------- .../Build_SKY_EEVB_STD_SIF_Release.yaml | 22 +++++++++---------- .github/workflows/SKY-BUILDS.txt | 10 +++++---- 4 files changed, 28 insertions(+), 26 deletions(-) rename .github/workflows/{ => Archived}/Build_SKY_EEVB_Release.yaml (100%) rename .github/workflows/{ => Archived}/Build_SKY_EEVB_STD_SIF_Debug.yaml (95%) rename .github/workflows/{ => Archived}/Build_SKY_EEVB_STD_SIF_Release.yaml (95%) diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Archived/Build_SKY_EEVB_Release.yaml similarity index 100% rename from .github/workflows/Build_SKY_EEVB_Release.yaml rename to .github/workflows/Archived/Build_SKY_EEVB_Release.yaml diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Debug.yaml similarity index 95% rename from .github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml rename to .github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Debug.yaml index bf0ef7a076..0f8dfe4857 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Debug.yaml +++ b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Debug.yaml @@ -1,11 +1,11 @@ -name: Build SKY_EEVB_STD_SIF_Debug - -on: - workflow_dispatch - -jobs: - build_SKY_EEVB_STD_SIF_Debug: - name: Build SKY_EEVB_STD_SIF_Debug - uses: ./.github/workflows/skyworks_evb_build.yaml - with: - targetName: 'SKY_EEVB_STD_SIF_Debug' +name: Build SKY_EEVB_STD_SIF_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF_Debug: + name: Build SKY_EEVB_STD_SIF_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_STD_SIF_Debug' diff --git a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Release.yaml similarity index 95% rename from .github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml rename to .github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Release.yaml index a5708c1c12..aeeba5475f 100644 --- a/.github/workflows/Build_SKY_EEVB_STD_SIF_Release.yaml +++ b/.github/workflows/Archived/Build_SKY_EEVB_STD_SIF_Release.yaml @@ -1,11 +1,11 @@ -name: Build SKY_EEVB_STD_SIF_Release - -on: - workflow_dispatch - -jobs: - build_SKY_EEVB_STD_SIF_Release: - name: Build SKY_EEVB_STD_SIF_Release - uses: ./.github/workflows/skyworks_evb_build.yaml - with: - targetName: 'SKY_EEVB_STD_SIF_Release' +name: Build SKY_EEVB_STD_SIF_Release + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_STD_SIF_Release: + name: Build SKY_EEVB_STD_SIF_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_STD_SIF_Release' diff --git a/.github/workflows/SKY-BUILDS.txt b/.github/workflows/SKY-BUILDS.txt index 8f2171895c..83e8665dec 100644 --- a/.github/workflows/SKY-BUILDS.txt +++ b/.github/workflows/SKY-BUILDS.txt @@ -1,7 +1,9 @@ # Format is: # Target,Preset SKY_EVB,SKY_EEVB_Debug -SKY_EVB,SKY_EEVB_Release -SKY_EVB,SKY_EEVB_STD_SIF_Debug -SKY_EVB,SKY_EEVB_STD_SIF_Release -SKY_Si5575_CEVB,SKY_Si5575_CEVB_Debug \ No newline at end of file +SKY_Si5575_CEVB,SKY_Si5575_CEVB_Debug + +# No longer used +# SKY_EVB,SKY_EEVB_Release +# SKY_EVB,SKY_EEVB_STD_SIF_Release +# SKY_EVB,SKY_EEVB_STD_SIF_Debug From 90144d817ea870fe57f332d9017d096ebbd6c637 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 08:34:13 -0500 Subject: [PATCH 430/572] SKY_Si5575_CEVB: add to Gecko targets --- targets/AzureRTOS/CMakePresets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index d75cdb673b..92d3676dd4 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -3,6 +3,7 @@ "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", "SiliconLabs/SKY_EVB/CMakePresets.json", + "SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] From 359d710215f1044ab5bee8169a3a2ed158b02a27 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 09:01:54 -0500 Subject: [PATCH 431/572] Si5575_CEVB: rename target/presets to remove SKY_: running into length issue + better name anyway --- .../Build_SKY_Si5575_CEVB_Debug.yaml | 11 --------- .../workflows/Build_Si5575_CEVB_Debug.yaml | 11 +++++++++ .github/workflows/SKY-BUILDS.txt | 2 +- .github/workflows/make-sky-yamls.pl | 3 ++- .../CMakeLists.txt | 0 .../CMakePresets.json | 24 +++++++++---------- .../README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../bspconfig.h | 0 .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../config/uartdrv_config.h | 0 .../launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../nanoCLR/main.c | 0 .../nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../nanoCLR/usb_hid_app.c | 0 .../target_BlockStorage.c | 0 .../target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../target_common.c | 0 .../target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../target_stdio_config.c | 0 .../target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_i2c_config.cpp | 0 .../target_system_device_i2c_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_device_spi_config.cpp | 0 .../target_system_device_spi_config.h | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../target_tx_user.h | 0 .../target_ux_user.h | 0 77 files changed, 26 insertions(+), 25 deletions(-) delete mode 100644 .github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml create mode 100644 .github/workflows/Build_Si5575_CEVB_Debug.yaml rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/CMakePresets.json (79%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_device_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_Si5575_CEVB => Si5575_CEVB}/target_ux_user.h (100%) diff --git a/.github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml b/.github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml deleted file mode 100644 index d26c07097a..0000000000 --- a/.github/workflows/Build_SKY_Si5575_CEVB_Debug.yaml +++ /dev/null @@ -1,11 +0,0 @@ -name: Build SKY_Si5575_CEVB_Debug - -on: - workflow_dispatch - -jobs: - build_SKY_Si5575_CEVB_Debug: - name: Build SKY_Si5575_CEVB_Debug - uses: ./.github/workflows/skyworks_evb_build.yaml - with: - targetName: 'SKY_Si5575_CEVB_Debug' diff --git a/.github/workflows/Build_Si5575_CEVB_Debug.yaml b/.github/workflows/Build_Si5575_CEVB_Debug.yaml new file mode 100644 index 0000000000..ec53a8a115 --- /dev/null +++ b/.github/workflows/Build_Si5575_CEVB_Debug.yaml @@ -0,0 +1,11 @@ +name: Build Si5575_CEVB_Debug + +on: + workflow_dispatch + +jobs: + build_Si5575_CEVB_Debug: + name: Build Si5575_CEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5575_CEVB_Debug' diff --git a/.github/workflows/SKY-BUILDS.txt b/.github/workflows/SKY-BUILDS.txt index 83e8665dec..4dbc85b7b8 100644 --- a/.github/workflows/SKY-BUILDS.txt +++ b/.github/workflows/SKY-BUILDS.txt @@ -1,7 +1,7 @@ # Format is: # Target,Preset SKY_EVB,SKY_EEVB_Debug -SKY_Si5575_CEVB,SKY_Si5575_CEVB_Debug +Si5575_CEVB,Si5575_CEVB_Debug # No longer used # SKY_EVB,SKY_EEVB_Release diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/make-sky-yamls.pl index aa680ba91f..f52cd24b60 100644 --- a/.github/workflows/make-sky-yamls.pl +++ b/.github/workflows/make-sky-yamls.pl @@ -23,7 +23,8 @@ foreach my $line (@lines) { # warn $line; - next if ($line =~ /^#/); + next if ($line =~ /^\s*#/); + next if ($line =~ /^\s*$/); my($target,$preset) = split(/,/,$line); # Don't allow a preset name to be used more than once diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json similarity index 79% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index c7b19bce4a..ff34952eaf 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "SKY_Si5575_CEVB_Debug", + "name": "Si5575_CEVB_Debug", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -15,8 +15,8 @@ ], "hidden": false, "cacheVariables": { - "TARGET_BOARD": "SKY_Si5575_CEVB", - "TARGET_NAME": "SKY_Si5575_CEVB_Debug", + "TARGET_BOARD": "Si5575_CEVB", + "TARGET_NAME": "Si5575_CEVB_Debug", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", @@ -51,13 +51,13 @@ } }, { - "name": "SKY_Si5575_CEVB_Release", + "name": "Si5575_CEVB_Release", "inherits": [ - "SKY_Si5575_CEVB_Debug" + "Si5575_CEVB_Debug" ], "hidden": false, "cacheVariables": { - "TARGET_NAME": "SKY_Si5575_CEVB", + "TARGET_NAME": "Si5575_CEVB", "NF_BUILD_RTM": "ON" } } @@ -65,15 +65,15 @@ "buildPresets": [ { "inherits": "base-user", - "name": "SKY_Si5575_CEVB_Debug", - "displayName": "SKY_Si5575_CEVB_Debug", - "configurePreset": "SKY_Si5575_CEVB_Debug" + "name": "Si5575_CEVB_Debug", + "displayName": "Si5575_CEVB_Debug", + "configurePreset": "Si5575_CEVB_Debug" }, { "inherits": "base-user", - "name": "SKY_Si5575_CEVB_Release", - "displayName": "SKY_Si5575_CEVB_Release", - "configurePreset": "SKY_Si5575_CEVB_Release" + "name": "Si5575_CEVB_Release", + "displayName": "Si5575_CEVB_Release", + "configurePreset": "Si5575_CEVB_Release" } ] } \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/README.md b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/README.md rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/launch.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/launch.json rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_device_spi_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_Si5575_CEVB/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_ux_user.h From b52afa353b12587fd42d0a4f7ee7eb933823c83d Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 09:07:40 -0500 Subject: [PATCH 432/572] Si5575_CEVB: more rename --- targets/AzureRTOS/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 92d3676dd4..03cbb72f0c 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -3,7 +3,7 @@ "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", "SiliconLabs/SKY_EVB/CMakePresets.json", - "SiliconLabs/SKY_Si5575_CEVB/CMakePresets.json", + "SiliconLabs/Si5575_CEVB/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] From 47100ca005d5b677f1f8d45603f765fae6c1eef2 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 09:20:23 -0500 Subject: [PATCH 433/572] Si5575_CEVB: comment out some ADC stuff to try to fix build --- .../SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp index 32147d6ec7..d4018ffbeb 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp @@ -3,6 +3,7 @@ // See LICENSE file in the project root for full license information. // +/* #include // PA6 (Gecko APORT1X CH6) ADC IMON0 Channel @@ -44,3 +45,4 @@ const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { }; const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); +*/ \ No newline at end of file From 8de43436fed8b5de2c7509eebc40ca69f893b8fd Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 09:25:44 -0500 Subject: [PATCH 434/572] Rename SKY_EVB target to SKY_EEVB --- .github/workflows/{ => Archived}/Makefile | 0 .github/workflows/Archived/SKY-BUILDS.txt | 9 + .../{ => Archived}/make-sky-yamls.pl | 0 .github/workflows/SKY-BUILDS.txt | 9 - targets/AzureRTOS/CMakePresets.json | 2 +- .../{SKY_EVB => SKY_EEVB}/CMakeLists.txt | 0 .../{SKY_EVB => SKY_EEVB}/CMakePresets.json | 192 +++++++----------- .../{SKY_EVB => SKY_EEVB}/README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../{SKY_EVB => SKY_EEVB}/bspconfig.h | 0 .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../{SKY_EVB => SKY_EEVB}/config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../config/uartdrv_config.h | 0 .../{SKY_EVB => SKY_EEVB}/launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../{SKY_EVB => SKY_EEVB}/nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../{SKY_EVB => SKY_EEVB}/nanoCLR/main.c | 0 .../{SKY_EVB => SKY_EEVB}/nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../nanoCLR/usb_hid_app.c | 0 .../target_BlockStorage.c | 0 .../target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../{SKY_EVB => SKY_EEVB}/target_common.c | 0 .../{SKY_EVB => SKY_EEVB}/target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../target_stdio_config.c | 0 .../target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_i2c_config.cpp | 0 .../target_system_device_i2c_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_device_spi_config.cpp | 0 .../target_system_device_spi_config.h | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../{SKY_EVB => SKY_EEVB}/target_tx_user.h | 0 .../{SKY_EVB => SKY_EEVB}/target_ux_user.h | 0 78 files changed, 88 insertions(+), 124 deletions(-) rename .github/workflows/{ => Archived}/Makefile (100%) create mode 100644 .github/workflows/Archived/SKY-BUILDS.txt rename .github/workflows/{ => Archived}/make-sky-yamls.pl (100%) delete mode 100644 .github/workflows/SKY-BUILDS.txt rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/CMakePresets.json (66%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_device_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{SKY_EVB => SKY_EEVB}/target_ux_user.h (100%) diff --git a/.github/workflows/Makefile b/.github/workflows/Archived/Makefile similarity index 100% rename from .github/workflows/Makefile rename to .github/workflows/Archived/Makefile diff --git a/.github/workflows/Archived/SKY-BUILDS.txt b/.github/workflows/Archived/SKY-BUILDS.txt new file mode 100644 index 0000000000..360ce44a9b --- /dev/null +++ b/.github/workflows/Archived/SKY-BUILDS.txt @@ -0,0 +1,9 @@ +# Format is: +# Target,Preset +SKY_EEVB,SKY_EEVB_Debug +Si5575_CEVB,Si5575_CEVB_Debug + +# No longer used +# SKY_EEVB,SKY_EEVB_Release +# SKY_EEVB,SKY_EEVB_STD_SIF_Release +# SKY_EEVB,SKY_EEVB_STD_SIF_Debug diff --git a/.github/workflows/make-sky-yamls.pl b/.github/workflows/Archived/make-sky-yamls.pl similarity index 100% rename from .github/workflows/make-sky-yamls.pl rename to .github/workflows/Archived/make-sky-yamls.pl diff --git a/.github/workflows/SKY-BUILDS.txt b/.github/workflows/SKY-BUILDS.txt deleted file mode 100644 index 4dbc85b7b8..0000000000 --- a/.github/workflows/SKY-BUILDS.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Format is: -# Target,Preset -SKY_EVB,SKY_EEVB_Debug -Si5575_CEVB,Si5575_CEVB_Debug - -# No longer used -# SKY_EVB,SKY_EEVB_Release -# SKY_EVB,SKY_EEVB_STD_SIF_Release -# SKY_EVB,SKY_EEVB_STD_SIF_Debug diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 03cbb72f0c..567b2bf221 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -2,7 +2,7 @@ "version": 4, "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", - "SiliconLabs/SKY_EVB/CMakePresets.json", + "SiliconLabs/SKY_EEVB/CMakePresets.json", "SiliconLabs/Si5575_CEVB/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json similarity index 66% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 6dd6c4ac42..103a2a91c0 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -1,115 +1,79 @@ -{ - "version": 4, - "include": [ - "../../../../CMake/arm-gcc.json", - "../../../../config/user-tools-repos.json", - "../../../../config/user-prefs.json" - ], - "configurePresets": [ - { - "name": "SKY_EEVB_Debug", - "inherits": [ - "arm-gcc-cortex-preset", - "user-tools-repos", - "user-prefs" - ], - "hidden": false, - "cacheVariables": { - "TARGET_BOARD": "SKY_EVB", - "TARGET_NAME": "SKY_EEVB_Debug", - "RTOS": "AzureRTOS", - "TARGET_SERIES": "EFM32GG11", - "SUPPORT_ANY_BASE_CONVERSION": "OFF", - "NF_FEATURE_RTC": "ON", - "NF_FEATURE_DEBUGGER": "ON", - "NF_FEATURE_HAS_SDCARD": "OFF", - "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "API_System.Math": "ON", - "API_Hardware.GiantGecko": "ON", - "API_System.Device.Gpio": "ON", - "API_System.Device.Pwm": "ON", - "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", - "API_System.Device.Dac": "OFF", - "API_System.Net": "OFF", - "API_nanoFramework.Device.OneWire": "ON", - "API_nanoFramework.Devices.Can": "OFF", - "API_nanoFramework.ResourceManager": "ON", - "API_nanoFramework.System.Collections": "ON", - "API_nanoFramework.System.Text": "ON", - "API_nanoFramework.GiantGecko.Adc": "ON", - "API_Windows.Storage": "OFF", - "API_nanoFramework.Graphics": "OFF", - "TARGET_SERIAL_BAUDRATE": "921600", - "HAL_WP_USE_SERIAL": "OFF", - "HAL_WP_USE_USB_CDC": "ON", - "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", - "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON" - } - }, - { - "name": "SKY_EEVB_Release", - "inherits": [ - "SKY_EEVB_Debug" - ], - "hidden": false, - "cacheVariables": { - "TARGET_NAME": "SKY_EEVB", - "NF_BUILD_RTM": "ON" - } - }, - { - "name": "SKY_EEVB_STD_SIF_Debug", - "inherits": [ - "SKY_EEVB_Debug" - ], - "cacheVariables": { - "TARGET_NAME": "SKY_EEVB_STD_SIF_Debug", - "API_System.Device.Spi": "ON", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", - "API_System.Device.I2c": "ON", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "OFF", - "API_System.Device.UsbStream": "ON" - } - }, - { - "name": "SKY_EEVB_STD_SIF_Release", - "inherits": [ - "SKY_EEVB_STD_SIF_Debug" - ], - "cacheVariables": { - "TARGET_NAME": "SKY_EEVB_STD_SIF", - "NF_BUILD_RTM": "ON" - } - } - ], - "buildPresets": [ - { - "inherits": "base-user", - "name": "SKY_EEVB_Debug", - "displayName": "SKY_EEVB_Debug", - "configurePreset": "SKY_EEVB_Debug" - }, - { - "inherits": "base-user", - "name": "SKY_EEVB_Release", - "displayName": "SKY_EEVB_Release", - "configurePreset": "SKY_EEVB_Release" - }, - { - "inherits": "base-user", - "name": "SKY_EEVB_STD_SIF_Debug", - "displayName": "SKY_EEVB_STD_SIF_Debug", - "configurePreset": "SKY_EEVB_STD_SIF_Debug" - }, - { - "inherits": "base-user", - "name": "SKY_EEVB_STD_SIF_Release", - "displayName": "SKY_EEVB_STD_SIF_Release", - "configurePreset": "SKY_EEVB_STD_SIF_Release" - } - ] +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_EEVB_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "SKY_EEVB", + "TARGET_NAME": "SKY_EEVB_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON" + } + }, + { + "name": "SKY_EEVB_Release", + "inherits": [ + "SKY_EEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_EEVB", + "NF_BUILD_RTM": "ON" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_EEVB_Debug", + "displayName": "SKY_EEVB_Debug", + "configurePreset": "SKY_EEVB_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_EEVB_Release", + "displayName": "SKY_EEVB_Release", + "configurePreset": "SKY_EEVB_Release" + } + ] } \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/README.md rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/README.md diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/launch.json rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_device_spi_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_device_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/SKY_EVB/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_ux_user.h From 5d15fc7f06348ad04152aa8aa57df2142584f363 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 10:14:23 -0500 Subject: [PATCH 435/572] Si5575_CEVB: properly disable nanoFramework.GiantGecko.Adc --- .../AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 2 +- .../SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp | 7 ++++--- .../SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h | 5 ++++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index ff34952eaf..daebb4d28f 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -37,7 +37,7 @@ "API_nanoFramework.ResourceManager": "ON", "API_nanoFramework.System.Collections": "ON", "API_nanoFramework.System.Text": "ON", - "API_nanoFramework.GiantGecko.Adc": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", "API_Windows.Storage": "OFF", "API_nanoFramework.Graphics": "OFF", "TARGET_SERIAL_BAUDRATE": "921600", diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp index d4018ffbeb..563138f982 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp @@ -3,9 +3,11 @@ // See LICENSE file in the project root for full license information. // -/* #include +// No ADC on Si5575 CEVB; this file is ignored because CMakePresets.json +// sets API_nanoFramework.GiantGecko.Adc=OFF + // PA6 (Gecko APORT1X CH6) ADC IMON0 Channel // PA7 (Gecko APORT2X CH7) ADC IMON1 Channel // PA8 (Gecko APORT1X CH8) ADC IMON2 Channel @@ -44,5 +46,4 @@ const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { {0, adcPosSelAPORT3XCH6}, }; -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); -*/ \ No newline at end of file +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h index 6ed4dd99fa..88b50dc390 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h @@ -3,5 +3,8 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_ADC0 FALSE +// No ADC on Si5575 CEVB; this file is ignored because CMakePresets.json +// sets API_nanoFramework.GiantGecko.Adc=OFF + +#define GECKO_USE_ADC0 TRUE #define GECKO_USE_ADC1 FALSE From d76d60a0260008088a3c446c9493cbeda8465dc6 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 10:27:45 -0500 Subject: [PATCH 436/572] Si5575_CEVB: properly disable nanoFramework.GiantGecko.Adc --- .../Si5575_CEVB/target_nano_gg_adc_config.cpp | 10 +++++++--- .../Si5575_CEVB/target_nano_gg_adc_config.h | 6 ++++-- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp index 563138f982..519968e94a 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp @@ -3,10 +3,12 @@ // See LICENSE file in the project root for full license information. // +// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF +// Rather than delete this file, comment out C code + +/* #include -// No ADC on Si5575 CEVB; this file is ignored because CMakePresets.json -// sets API_nanoFramework.GiantGecko.Adc=OFF // PA6 (Gecko APORT1X CH6) ADC IMON0 Channel // PA7 (Gecko APORT2X CH7) ADC IMON1 Channel @@ -46,4 +48,6 @@ const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { {0, adcPosSelAPORT3XCH6}, }; -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); \ No newline at end of file +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h index 88b50dc390..891c97b3bc 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h @@ -3,8 +3,10 @@ // See LICENSE file in the project root for full license information. // -// No ADC on Si5575 CEVB; this file is ignored because CMakePresets.json -// sets API_nanoFramework.GiantGecko.Adc=OFF +// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF +// Rather than delete this file, comment out C code +/* #define GECKO_USE_ADC0 TRUE #define GECKO_USE_ADC1 FALSE +*/ \ No newline at end of file From 23ebfdced0a9de7260c4085e280ea37be8bc69c9 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Sun, 23 Jul 2023 10:45:09 -0500 Subject: [PATCH 437/572] Si5575_CEVB: properly disable nanoFramework.GiantGecko.Adc --- .gitignore | 1 + .../SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp | 4 ++-- .../SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 9727ed1dc9..4fc8344f26 100644 --- a/.gitignore +++ b/.gitignore @@ -380,3 +380,4 @@ sdkconfig CMakeUserPresets.json config/user-tools-repos.json config/user-prefs.json +targets/AzureRTOS/SiliconLabs/Si5575_CEVB/.vscode/settings.json diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp index 519968e94a..e6b40bb1d8 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp @@ -4,11 +4,11 @@ // // No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF -// Rather than delete this file, comment out C code -/* #include +/* + // PA6 (Gecko APORT1X CH6) ADC IMON0 Channel // PA7 (Gecko APORT2X CH7) ADC IMON1 Channel diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h index 891c97b3bc..f7685073ae 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h @@ -4,7 +4,6 @@ // // No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF -// Rather than delete this file, comment out C code /* #define GECKO_USE_ADC0 TRUE From 4ff742b92b6b0a9f712803b75efb9ebff4b0ca5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 24 Jul 2023 16:48:29 +0100 Subject: [PATCH 438/572] Fix ADC config for Si5575 --- .../Si5575_CEVB/target_nano_gg_adc_config.cpp | 47 ------------------- .../Si5575_CEVB/target_nano_gg_adc_config.h | 4 +- 2 files changed, 1 insertion(+), 50 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp index e6b40bb1d8..203df08df7 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp @@ -4,50 +4,3 @@ // // No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF - -#include - -/* - - -// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel -// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel -// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel -// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel -// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel -// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel -// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel -// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel -// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel -// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) -// PE6 (Gecko APORT3X CH6) ADC Cal Channel - -const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - - // IMON0 - {0, adcPosSelAPORT1XCH6}, - // - {0, adcPosSelAPORT2XCH7}, - // - {0, adcPosSelAPORT1XCH8}, - // - {0, adcPosSelAPORT2XCH9}, - // - {0, adcPosSelAPORT1XCH10}, - // - {0, adcPosSelAPORT2XCH11}, - // - {0, adcPosSelAPORT1XCH12}, - // - {0, adcPosSelAPORT2XCH13}, - // - {0, adcPosSelAPORT1XCH14}, - // - {0, adcPosSelAPORT2XCH15}, - // - {0, adcPosSelAPORT3XCH6}, -}; - -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h index f7685073ae..115d8a0324 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h @@ -5,7 +5,5 @@ // No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF -/* -#define GECKO_USE_ADC0 TRUE +#define GECKO_USE_ADC0 FALSE #define GECKO_USE_ADC1 FALSE -*/ \ No newline at end of file From e790223edea65da8156e1c3c99d4ac4f5ced4c32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 24 Jul 2023 16:48:47 +0100 Subject: [PATCH 439/572] Fix SPI build config for Si5575 --- .../Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp | 2 +- .../SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp index 6cb49e27e6..0838146c90 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp @@ -42,4 +42,4 @@ INIT_SPI_CONFIG(2, 1, 1, 1, 1) // CS: PE13 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(3, 0, 0, 0, 0) +INIT_SPI_CONFIG(0, 0, 0, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h index 3918070d91..409945557b 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h @@ -3,7 +3,5 @@ // See LICENSE file in the project root for full license information. // -/* #define GECKO_USE_SPI1 TRUE #define GECKO_USE_SPI2 TRUE -*/ \ No newline at end of file From 946c876709a0df558afdeb32b4057571a35bcdcc Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 24 Jul 2023 11:39:11 -0500 Subject: [PATCH 440/572] Si5575_CEVB: add back EEVB ADC config as comment; reorder SPI configs to be in 0..2 order --- .../target_com_sky_nf_dev_spi_config.cpp | 28 +++++------ .../Si5575_CEVB/target_nano_gg_adc_config.cpp | 46 +++++++++++++++++++ 2 files changed, 60 insertions(+), 14 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp index 0838146c90..147cb8f2df 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp @@ -5,6 +5,19 @@ #include +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + ////////// // SPI1 // ////////// @@ -29,17 +42,4 @@ INIT_SPI_CONFIG(1, 1, 1, 1, 1) // CS: PB6 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(2, 1, 1, 1, 1) - -////////// -// SPI0 // -////////// - -// USART0 -// SCK: PE12 -// MOSI: PE10 -// MISO: PE11 -// CS: PE13 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(0, 0, 0, 0, 0) +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp index 203df08df7..c6b9aca497 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp @@ -4,3 +4,49 @@ // // No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file From 92895085ef9e69c201d7d03caf813cfb8acb24ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 26 Jul 2023 18:35:53 +0100 Subject: [PATCH 441/572] Enable watchdog for Gecko targets - Add SDK code to build. - Add platform implementation. - Enable watchdog on SL_STK3701A target. --- CMake/Modules/FindGecko_SDK.cmake | 1 + .../SiliconLabs/SL_STK3701A/nanoCLR/main.c | 2 +- .../SiliconLabs/_nanoCLR/CMakeLists.txt | 5 ++++ .../SiliconLabs/_nanoCLR/targetHAL_Power.c | 3 +- .../SiliconLabs/_nanoCLR/targetHAL_Watchdog.c | 28 +++++++++++++++++++ 5 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Watchdog.c diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 79c3446e0d..4bdd471b30 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -90,6 +90,7 @@ set(gecko_sdk_srcs em_timer.c em_usart.c em_vdac.c + em_wdog.c # emdrv dmactrl.c diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c index e18c993d26..975c946002 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/nanoCLR/main.c @@ -79,7 +79,7 @@ void tx_application_define(void *first_unused_memory) tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); // start watchdog - // Watchdog_Init(); + Watchdog_Init(); // #if (HAL_NF_USE_STM32_CRC == TRUE) // // startup crc diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt index eb8981c659..b8a66f3f18 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt @@ -9,6 +9,11 @@ list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetP list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c) +# append watchdog only if option is ON +if(HAL_USE_WDG_OPTION) + list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Watchdog.c) +endif() + # make var global set(TARGET_AZURERTOS_NANOCLR_SOURCES ${TARGET_AZURERTOS_NANOCLR_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c index d47c999a6e..936a301cdf 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Power.c @@ -8,6 +8,7 @@ #include #include #include +#include #ifdef HAL_RTC_MODULE_ENABLED extern RTC_HandleTypeDef RtcHandle; @@ -41,7 +42,7 @@ void CPU_SetPowerMode(PowerLevel_type powerLevel) { case PowerLevel__Off: // stop watchdog - // wdgStop(&WDGD1); + WDOGn_Enable(DEFAULT_WDOG, false); // gracefully shutdown everything nanoHAL_Uninitialize_C(true); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Watchdog.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Watchdog.c new file mode 100644 index 0000000000..9e452dfeb8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetHAL_Watchdog.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#include + +// Method to initialize the watchdog. +void Watchdog_Init() +{ + // Watchdog Initialize settings + // 8193 clock cycles of a 1kHz clock ~8 seconds period + WDOG_Init_TypeDef wdogInit = WDOG_INIT_DEFAULT; + wdogInit.clkSel = wdogClkSelULFRCO; + wdogInit.perSel = wdogPeriod_8k; + + // Initializing watchdog with chosen settings + WDOGn_Init(DEFAULT_WDOG, &wdogInit); +} + +// Reset the watchdog. If not done within the timout period, +// the watchdog will trigger and MCU will reset +void Watchdog_Reset() +{ + WDOGn_Feed(DEFAULT_WDOG); +} From 142bd6f4a2bedf6f2227cacf036037b79fdb784b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 26 Jul 2023 18:36:26 +0100 Subject: [PATCH 442/572] Add call to watchdog init to Skyworks targets --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c | 2 +- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c index 6661c9eb80..def0fb1073 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c @@ -87,7 +87,7 @@ void tx_application_define(void *first_unused_memory) tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); // start watchdog - // Watchdog_Init(); + Watchdog_Init(); #if (TRACE_TO_STDIO == TRUE) StdioPort_Init(); diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c index 6661c9eb80..def0fb1073 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c @@ -87,7 +87,7 @@ void tx_application_define(void *first_unused_memory) tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); // start watchdog - // Watchdog_Init(); + Watchdog_Init(); #if (TRACE_TO_STDIO == TRUE) StdioPort_Init(); From ddbf9426f4dc33faf6f34086690ce5c8f9006c6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 28 Jul 2023 17:18:26 +0100 Subject: [PATCH 443/572] Watchdog off in Skkyworks targets --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 1 + targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 1 + 2 files changed, 2 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 103a2a91c0..4b13c1d71a 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -24,6 +24,7 @@ "NF_FEATURE_DEBUGGER": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index daebb4d28f..3bad279bda 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -24,6 +24,7 @@ "NF_FEATURE_DEBUGGER": "ON", "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", From 47a44c27b55ff01d9b0b5f2657bde3526df832ac Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Fri, 28 Jul 2023 11:23:12 -0500 Subject: [PATCH 444/572] Added CLR files for the STB Interposer --- .../SiliconLabs/STB_Interposer/CMakeLists.txt | 76 ++++ .../STB_Interposer/CMakePresets.json | 79 ++++ .../SiliconLabs/STB_Interposer/README.md | 28 ++ .../autogen/sl_device_init_clocks.c | 28 ++ .../STB_Interposer/autogen/sl_event_handler.c | 48 +++ .../STB_Interposer/autogen/sl_uartdrv_init.c | 91 +++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 ++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 ++ .../autogen/sl_usbd_class_hid_instances.c | 277 ++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 32 ++ .../autogen/sl_usbd_configuration_instances.c | 61 ++++ .../autogen/sl_usbd_configuration_instances.h | 18 + .../SiliconLabs/STB_Interposer/bspconfig.h | 9 + .../STB_Interposer/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 123 +++++++ .../common/Device_BlockStorage.c | 123 +++++++ .../common/tx_initialize_low_level.S | 239 ++++++++++++ .../STB_Interposer/config/pin_config.h | 259 +++++++++++++ .../config/sl_board_control_config.h | 112 ++++++ .../config/sl_device_init_hfrco_config.h | 27 ++ .../config/sl_device_init_hfxo_config.h | 43 +++ .../config/sl_device_init_lfrco_config.h | 34 ++ .../config/sl_device_init_lfxo_config.h | 37 ++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++ .../config/sl_iostream_usart_vcom_config.h | 112 ++++++ .../STB_Interposer/config/sl_memory_config.h | 13 + .../config/sl_uartdrv_usart_vcom_config.h | 85 +++++ .../config/sl_usbd_class_acm0_config.h | 53 +++ .../config/sl_usbd_class_hid0_config.h | 143 ++++++++ .../config/sl_usbd_class_winusb_config.h | 59 +++ .../config/sl_usbd_config0_config.h | 51 +++ .../config/sl_usbd_core_config.h | 199 ++++++++++ .../config/sl_usbd_device_config.h | 60 +++ .../STB_Interposer/config/uartdrv_config.h | 114 ++++++ .../SiliconLabs/STB_Interposer/launch.json | 83 +++++ .../STB_Interposer/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ++++++++++++ .../nanoBooter/efm32gg11b_booter.ld | 235 ++++++++++++ .../STB_Interposer/nanoBooter/main.c | 180 +++++++++ .../nanoBooter/target_board.h.in | 18 + .../STB_Interposer/nanoCLR/CMakeLists.txt | 15 + .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 +++++++++++++ .../STB_Interposer/nanoCLR/efm32gg11b_CLR.ld | 246 +++++++++++++ .../SiliconLabs/STB_Interposer/nanoCLR/main.c | 203 +++++++++++ .../STB_Interposer/nanoCLR/nanoHAL.cpp | 8 + .../STB_Interposer/nanoCLR/target_board.h.in | 18 + .../STB_Interposer/nanoCLR/usb_hid_app.c | 244 +++++++++++++ .../STB_Interposer/target_BlockStorage.c | 19 + .../STB_Interposer/target_BlockStorage.h | 12 + .../target_com_sky_nf_dev_i2c_config.cpp | 26 ++ .../target_com_sky_nf_dev_i2c_config.h | 4 + .../target_com_sky_nf_dev_spi_config.cpp | 9 + .../target_com_sky_nf_dev_spi_config.h | 7 + .../STB_Interposer/target_common.c | 27 ++ .../STB_Interposer/target_common.h.in | 52 +++ .../target_nano_gg_adc_config.cpp | 20 + .../target_nano_gg_adc_config.h | 7 + .../target_nf_dev_onewire_config.cpp | 8 + .../target_nf_dev_onewire_config.h | 11 + .../STB_Interposer/target_stdio_config.c | 7 + .../STB_Interposer/target_stdio_config.h | 5 + .../target_system_device_adc_config.cpp | 6 + .../target_system_device_adc_config.h | 6 + .../target_system_device_i2c_config.cpp | 28 ++ .../target_system_device_i2c_config.h | 4 + .../target_system_device_pwm_config.cpp | 17 + .../target_system_device_spi_config.cpp | 9 + .../target_system_device_spi_config.h | 6 + .../target_system_io_ports_config.cpp | 4 + .../target_system_io_ports_config.h | 5 + .../STB_Interposer/target_tx_user.h | 206 +++++++++++ .../STB_Interposer/target_ux_user.h | 345 ++++++++++++++++++ 73 files changed, 5553 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json new file mode 100644 index 0000000000..a5cf84d824 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -0,0 +1,79 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "STB_Interposer_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "STB_Interposer", + "TARGET_NAME": "STB_Interposer_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON" + } + }, + { + "name": "STB_Interposer_Release", + "inherits": [ + "STB_Interposer_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "STB_Interposer", + "NF_BUILD_RTM": "ON" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "STB_Interposer_Debug", + "displayName": "STB_Interposer_Debug", + "configurePreset": "STB_Interposer_Debug" + }, + { + "inherits": "base-user", + "name": "STB_Interposer_Release", + "displayName": "STB_Interposer_Release", + "configurePreset": "STB_Interposer_Release" + } + ] +} \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md b/targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md new file mode 100644 index 0000000000..60965af68c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/README.md @@ -0,0 +1,28 @@ +# Skyworks STB Interposer featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/NAT/pages/8204484955/Interposer+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c new file mode 100644 index 0000000000..09982097e3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 66}, + + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..debd4df8ef --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[32 + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c new file mode 100644 index 0000000000..0787f4a6a5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c @@ -0,0 +1,180 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..d17abebca3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c new file mode 100644 index 0000000000..def0fb1073 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c @@ -0,0 +1,203 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + clrSettings.RevertToBooterOnFault = true; + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..a1a1e723f2 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// The STB Interposer does not use SPI communication + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..11a6a341fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 FALSE +#define GECKO_USE_SPI2 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..ade2abefdb --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..d094f193c3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_ADC0 FAlSE +#define GECKO_USE_ADC1 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..74d8b5da5b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..38074baf86 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h new file mode 100644 index 0000000000..79c0cadd23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..e7f339e23e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// The STB Interposer does not use SPI communication. + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h new file mode 100644 index 0000000000..e52444eec5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// +#define GECKO_USE_SPI1 FALSE +#define GECKO_USE_SPI2 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From 09879d6a06964dfc3347f08a3e5a4c2e13a15ea0 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Fri, 28 Jul 2023 11:42:10 -0500 Subject: [PATCH 445/572] Added workflow yaml file for the STB Interposer. --- .github/workflows/Build_STB_Interposer_Debug.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 .github/workflows/Build_STB_Interposer_Debug.yaml diff --git a/.github/workflows/Build_STB_Interposer_Debug.yaml b/.github/workflows/Build_STB_Interposer_Debug.yaml new file mode 100644 index 0000000000..62d4043d28 --- /dev/null +++ b/.github/workflows/Build_STB_Interposer_Debug.yaml @@ -0,0 +1,11 @@ +name: Build STB_Interposer_Debug + +on: + workflow_dispatch + +jobs: + build_STB_Interposer_Debug: + name: Build STB_Interposer_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'STB_Interposer_Debug' From 933fdb485307a0856750479caf24d1d484655780 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Fri, 28 Jul 2023 11:55:28 -0500 Subject: [PATCH 446/572] Added STB_Interposer CMakePresets.json to the parent AzureRTOS .json. --- targets/AzureRTOS/CMakePresets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 567b2bf221..175e5970ac 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -4,6 +4,7 @@ "SiliconLabs/SL_STK3701A/CMakePresets.json", "SiliconLabs/SKY_EEVB/CMakePresets.json", "SiliconLabs/Si5575_CEVB/CMakePresets.json", + "SiliconLabs/STB_Interposer/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] From 8e040e5a3fd232e615757434ac35a639673323a9 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Mon, 31 Jul 2023 10:03:53 -0500 Subject: [PATCH 447/572] Re-enabling Skyworks spi in thge STB CMakePresets.json --- targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index 74e854b34b..caa1b26069 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -45,7 +45,7 @@ "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON" From c5623b0431bc67b702193decf3598b4c76a38f36 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Mon, 31 Jul 2023 10:15:33 -0500 Subject: [PATCH 448/572] Re-adding removed spi configuration to see if it's removal was breaking the build. --- .../target_com_sky_nf_dev_spi_config.cpp | 38 ++++++++++++++++++- .../target_com_sky_nf_dev_spi_config.h | 3 +- .../target_system_device_spi_config.cpp | 28 +++++++++++++- 3 files changed, 66 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp index a1a1e723f2..147cb8f2df 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp @@ -5,5 +5,41 @@ #include -// The STB Interposer does not use SPI communication +////////// +// SPI0 // +////////// +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h index 11a6a341fe..b89482cb72 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h @@ -3,5 +3,6 @@ // See LICENSE file in the project root for full license information. // +#define GECKO_USE_SPI0 FALSE #define GECKO_USE_SPI1 FALSE -#define GECKO_USE_SPI2 FALSE +#define GECKO_USE_SPI2 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp index e7f339e23e..3bf95a0eb3 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.cpp @@ -5,5 +5,31 @@ #include -// The STB Interposer does not use SPI communication. +/* +////////// +// SPI1 // +////////// +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file From 88c8bdb82c5a168a4fb968ae8fc7f400b0816642 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Mon, 31 Jul 2023 10:28:33 -0500 Subject: [PATCH 449/572] Fully re-enabling SPI. --- .../STB_Interposer/target_com_sky_nf_dev_spi_config.h | 6 +++--- .../STB_Interposer/target_system_device_spi_config.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h index b89482cb72..bdfea3503d 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h @@ -3,6 +3,6 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 FALSE -#define GECKO_USE_SPI1 FALSE -#define GECKO_USE_SPI2 FALSE \ No newline at end of file +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h index e52444eec5..742991d83c 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h @@ -2,5 +2,5 @@ // Copyright (c) .NET Foundation and Contributors // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI1 FALSE -#define GECKO_USE_SPI2 FALSE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE From 4ebc1bce25e24db1b2f92c2569c258c97816ee27 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Mon, 31 Jul 2023 10:41:06 -0500 Subject: [PATCH 450/572] Fixed casing typo in nano_gg_adc_config.h. --- .../SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h index d094f193c3..ce46252b6d 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.h @@ -3,5 +3,5 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_ADC0 FAlSE +#define GECKO_USE_ADC0 FALSE #define GECKO_USE_ADC1 FALSE \ No newline at end of file From 1804bb55a52f3d75cbc91db3949e62d3817e86d5 Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Mon, 31 Jul 2023 10:52:23 -0500 Subject: [PATCH 451/572] Added missing configuration to disable SPI in the STB Interposer CLR. --- .../STB_Interposer/CMakePresets.json | 2 +- .../target_com_sky_nf_dev_spi_config.cpp | 5 +-- .../target_com_sky_nf_dev_spi_config.h | 6 ++-- .../target_nano_gg_adc_config.cpp | 32 +++++++++++++++++++ .../target_system_device_i2c_config.cpp | 4 +++ .../target_system_device_i2c_config.h | 6 +++- .../target_system_device_spi_config.h | 5 +-- 7 files changed, 51 insertions(+), 9 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index caa1b26069..74e854b34b 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -45,7 +45,7 @@ "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON" diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp index 147cb8f2df..c30dd242f8 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp @@ -4,7 +4,7 @@ // #include - +/* ////////// // SPI0 // ////////// @@ -42,4 +42,5 @@ INIT_SPI_CONFIG(1, 1, 1, 1, 1) // CS: PB6 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file +INIT_SPI_CONFIG(2, 1, 1, 1, 1) +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h index bdfea3503d..dc19723c6f 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h @@ -3,6 +3,6 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 TRUE -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE \ No newline at end of file +#define GECKO_USE_SPI0 FALSE +#define GECKO_USE_SPI1 FALSE +#define GECKO_USE_SPI2 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp index ade2abefdb..7f4a89e9b8 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp @@ -3,6 +3,10 @@ // See LICENSE file in the project root for full license information. // +// No ADC on STB Interposer" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + #include // PA6 (Gecko APORT1X CH6) ADC IMON0 Channel @@ -17,4 +21,32 @@ // PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) // PE6 (Gecko APORT3X CH6) ADC Cal Channel +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp index 38074baf86..6e7b275464 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp @@ -5,6 +5,8 @@ #include +/* + ////////// // I2C0 // ////////// @@ -26,3 +28,5 @@ I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) // GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h index 79c0cadd23..c81f83afe3 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h @@ -1,4 +1,8 @@ // Copyright Skyworks Solutions, Inc. All Rights Reserved. +/* + #define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE \ No newline at end of file +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h index 742991d83c..11a6a341fe 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h @@ -2,5 +2,6 @@ // Copyright (c) .NET Foundation and Contributors // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE + +#define GECKO_USE_SPI1 FALSE +#define GECKO_USE_SPI2 FALSE From a6ce791a6e8bd5d099b279017a24a59ef4f72e5c Mon Sep 17 00:00:00 2001 From: Anthony Burns Date: Mon, 31 Jul 2023 11:14:13 -0500 Subject: [PATCH 452/572] Revert "Added missing configuration to disable SPI in the STB Interposer CLR." Leaving SPI enabled as the pins it uses will not be connected to anything on the Interposer This reverts commit 1804bb55a52f3d75cbc91db3949e62d3817e86d5. --- .../STB_Interposer/CMakePresets.json | 2 +- .../target_com_sky_nf_dev_spi_config.cpp | 5 ++- .../target_com_sky_nf_dev_spi_config.h | 6 ++-- .../target_nano_gg_adc_config.cpp | 32 ------------------- .../target_system_device_i2c_config.cpp | 4 --- .../target_system_device_i2c_config.h | 6 +--- .../target_system_device_spi_config.h | 5 ++- 7 files changed, 9 insertions(+), 51 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index 74e854b34b..caa1b26069 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -45,7 +45,7 @@ "HAL_WP_USE_SERIAL": "OFF", "HAL_WP_USE_USB_CDC": "ON", "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON" diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp index c30dd242f8..147cb8f2df 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp @@ -4,7 +4,7 @@ // #include -/* + ////////// // SPI0 // ////////// @@ -42,5 +42,4 @@ INIT_SPI_CONFIG(1, 1, 1, 1, 1) // CS: PB6 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -INIT_SPI_CONFIG(2, 1, 1, 1, 1) -*/ \ No newline at end of file +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h index dc19723c6f..bdfea3503d 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.h @@ -3,6 +3,6 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 FALSE -#define GECKO_USE_SPI1 FALSE -#define GECKO_USE_SPI2 FALSE +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp index 7f4a89e9b8..ade2abefdb 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nano_gg_adc_config.cpp @@ -3,10 +3,6 @@ // See LICENSE file in the project root for full license information. // -// No ADC on STB Interposer" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF - -/* - #include // PA6 (Gecko APORT1X CH6) ADC IMON0 Channel @@ -21,32 +17,4 @@ // PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) // PE6 (Gecko APORT3X CH6) ADC Cal Channel -const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - - // IMON0 - {0, adcPosSelAPORT1XCH6}, - // - {0, adcPosSelAPORT2XCH7}, - // - {0, adcPosSelAPORT1XCH8}, - // - {0, adcPosSelAPORT2XCH9}, - // - {0, adcPosSelAPORT1XCH10}, - // - {0, adcPosSelAPORT2XCH11}, - // - {0, adcPosSelAPORT1XCH12}, - // - {0, adcPosSelAPORT2XCH13}, - // - {0, adcPosSelAPORT1XCH14}, - // - {0, adcPosSelAPORT2XCH15}, - // - {0, adcPosSelAPORT3XCH6}, -}; - -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp index 6e7b275464..38074baf86 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.cpp @@ -5,8 +5,6 @@ #include -/* - ////////// // I2C0 // ////////// @@ -28,5 +26,3 @@ I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) // GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h index c81f83afe3..79c0cadd23 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_i2c_config.h @@ -1,8 +1,4 @@ // Copyright Skyworks Solutions, Inc. All Rights Reserved. -/* - #define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE - -*/ \ No newline at end of file +#define GECKO_USE_I2C1 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h index 11a6a341fe..742991d83c 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_system_device_spi_config.h @@ -2,6 +2,5 @@ // Copyright (c) .NET Foundation and Contributors // See LICENSE file in the project root for full license information. // - -#define GECKO_USE_SPI1 FALSE -#define GECKO_USE_SPI2 FALSE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE From 37c51702c609655e6fdd498230ca96149cbf9248 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 1 Aug 2023 15:49:38 +0100 Subject: [PATCH 453/572] Add NF_CLR_NO_IL_INLINE to SKY_EEVB --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 4b13c1d71a..846e8735d5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -25,6 +25,7 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", + "NF_CLR_NO_IL_INLINE": "ON", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", @@ -77,4 +78,4 @@ "configurePreset": "SKY_EEVB_Release" } ] -} \ No newline at end of file +} From 1f3a79c515f59421e2d8440b33f48644a25ab057 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 2 Aug 2023 18:29:08 +0100 Subject: [PATCH 454/572] Add support to configure length of USB Device Class Vendor description - Add code to validate length of description parameter. - Update CMakes accordingly. --- CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake | 6 ++++++ targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 1 + .../SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h | 2 +- .../SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h | 2 +- .../SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h | 2 +- .../SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h | 2 +- .../_common/autogen/sl_usbd_class_vendor_instances.c | 2 +- ...sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp | 6 ++++++ .../sys_dev_usbstream_native_target.h | 2 +- 9 files changed, 19 insertions(+), 6 deletions(-) diff --git a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake index ec5ada047e..b88d967725 100644 --- a/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake +++ b/CMake/Modules/AzureRTOS_EFM32GG11_GCC_options.cmake @@ -40,6 +40,12 @@ macro(nf_set_compile_options) target_compile_definitions(${NFSCO_TARGET} PUBLIC -DDEBUG_EFM=1) endif() + if(GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_LENGTH) + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DDEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN=${GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_LENGTH} ) + else() + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DDEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN=64 ) + endif() + endmacro() diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 4e4ea6561c..740a9fa051 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -10,6 +10,7 @@ set(SILABS_GECKO_SDK_REQUIRED TRUE PARENT_SCOPE) option(GECKO_FEATURE_USBD_HID "option to use Gecko SDK HID class") option(GECKO_FEATURE_USBD_WINUSB "option to use Gecko SDK USB vendor class for WinUSB") +option(GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_LENGTH "option to override Device Class Vendor description") ################################################################# # Options for Wire Protocol channel diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h index debd4df8ef..1058079e4f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/config/sl_usbd_core_config.h @@ -7,7 +7,7 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H -extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; // <<< Use Configuration Wizard in Context Menu >>> diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h index c055ad3f2f..ae01c52b94 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/config/sl_usbd_core_config.h @@ -7,7 +7,7 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H -extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; // <<< Use Configuration Wizard in Context Menu >>> diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h index debd4df8ef..1058079e4f 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/config/sl_usbd_core_config.h @@ -7,7 +7,7 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H -extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; // <<< Use Configuration Wizard in Context Menu >>> diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h index debd4df8ef..1058079e4f 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h @@ -7,7 +7,7 @@ #ifndef SL_USBD_CONFIG_H #define SL_USBD_CONFIG_H -extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; // <<< Use Configuration Wizard in Context Menu >>> diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index a812106106..8f7215bd57 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -28,7 +28,7 @@ extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t dat extern sl_status_t sl_usbd_vendor_update_device_product_string(const char *product_string); // storage for USB class vendor description -char UsbClassVendorDescription[32 + 1]; +char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; char UsbClassVendorDeviceInterfaceGuid[DEVICE_CLASS_GUID_PROPERTY_LEN]; // flag for USB WinUSB intialized diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index b2350a49a7..7344734546 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -407,6 +407,12 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::NativeOpen deviceDescription = stack.Arg2().RecoverString(); FAULT_ON_NULL(deviceDescription); + // validate device description length + if (hal_strlen_s(deviceDescription) > sizeof(UsbClassVendorDescription) - 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + // store device description hal_strcpy_s(UsbClassVendorDescription, sizeof(UsbClassVendorDescription), deviceDescription); diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h index a30122a4b0..53691a1f82 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_target.h @@ -6,7 +6,7 @@ #include // need these declared here as they are scattered throughout Gecko SDK and config files -extern char UsbClassVendorDescription[32 + 1]; +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; extern char UsbClassVendorDeviceInterfaceGuid[38 * 2 + 2]; extern uint8_t sl_usbd_vendor_winusb_number; extern "C" sl_status_t sli_usbd_vendor_winusb_init(void); From 1537633bfc29c4ec36a103714400e03718b65c97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 2 Aug 2023 18:30:14 +0100 Subject: [PATCH 455/572] Fix formatting of CMake presets files --- targets/AzureRTOS/CMakePresets.json | 4 ++-- .../AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json | 2 +- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 175e5970ac..00b15662ee 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -2,8 +2,8 @@ "version": 4, "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", - "SiliconLabs/SKY_EEVB/CMakePresets.json", - "SiliconLabs/Si5575_CEVB/CMakePresets.json", + "SiliconLabs/SKY_EEVB/CMakePresets.json", + "SiliconLabs/Si5575_CEVB/CMakePresets.json", "SiliconLabs/STB_Interposer/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index caa1b26069..c1b489553c 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -77,4 +77,4 @@ "configurePreset": "STB_Interposer_Release" } ] -} \ No newline at end of file +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index 3bad279bda..625a5a513a 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -77,4 +77,4 @@ "configurePreset": "Si5575_CEVB_Release" } ] -} \ No newline at end of file +} From c70c35c1f59f968917669c4901d041431b73f83e Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Thu, 24 Aug 2023 09:12:50 -0500 Subject: [PATCH 456/572] Add SKY_EEVB_Release back as standard build action --- .github/workflows/{Archived => }/Build_SKY_EEVB_Release.yaml | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename .github/workflows/{Archived => }/Build_SKY_EEVB_Release.yaml (100%) diff --git a/.github/workflows/Archived/Build_SKY_EEVB_Release.yaml b/.github/workflows/Build_SKY_EEVB_Release.yaml similarity index 100% rename from .github/workflows/Archived/Build_SKY_EEVB_Release.yaml rename to .github/workflows/Build_SKY_EEVB_Release.yaml From 7d950f072dfd540b38d1795cfee4c907a956361f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 24 Aug 2023 15:50:05 +0100 Subject: [PATCH 457/572] Fix code style --- src/CLR/Diagnostics/Profiler.cpp | 640 +++++++++++++++++-------------- 1 file changed, 343 insertions(+), 297 deletions(-) diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index fbaaec1e1d..55e31bb035 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -16,12 +16,12 @@ HRESULT CLR_PRF_Profiler::CreateInstance() g_CLR_PRF_Profiler.m_packetSeqId = 0; g_CLR_PRF_Profiler.m_stream = NULL; - g_CLR_PRF_Profiler.m_lastTimestamp = (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) - >> CLR_PRF_CMDS::Bits::TimestampShift); + g_CLR_PRF_Profiler.m_lastTimestamp = + (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) >> CLR_PRF_CMDS::Bits::TimestampShift); g_CLR_PRF_Profiler.m_currentAssembly = 0; g_CLR_PRF_Profiler.m_currentThreadPID = 0; NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance(g_CLR_PRF_Profiler.m_stream, NULL, 0)); - + NANOCLR_NOCLEANUP(); } @@ -41,9 +41,9 @@ HRESULT CLR_PRF_Profiler::Profiler_Cleanup() void CLR_PRF_Profiler::SendMemoryLayout() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - //Send Memory Layout - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Memory_Layout, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( 0 ); + // Send Memory Layout + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Memory_Layout, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(0); PackAndWriteBits(s_CLR_RT_Heap.m_size); Stream_Send(); } @@ -57,45 +57,48 @@ HRESULT CLR_PRF_Profiler::DumpHeap() CLR_UINT32 heapSize = 0; - if(CLR_EE_PRF_IS_NOT(Enabled)) { NANOCLR_SET_AND_LEAVE(S_OK); } + if (CLR_EE_PRF_IS_NOT(Enabled)) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } { - //Send HeapDump Begin Marker - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Start, CLR_PRF_CMDS::Bits::CommandHeader ); + // Send HeapDump Begin Marker + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapDump_Start, CLR_PRF_CMDS::Bits::CommandHeader); NANOCLR_CHECK_HRESULT(Stream_Send()); } DumpRoots(); - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, g_CLR_RT_ExecutionEngine.m_heap) { - CLR_RT_HeapBlock_Node* ptr; + CLR_RT_HeapBlock_Node *ptr; CLR_UINT32 size; - CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + CLR_RT_HeapBlock_Node *end = hc->m_payloadEnd; - for(ptr = hc->m_payloadStart, size = ptr->DataSize(); ptr < end; ptr+= size, size = ptr->DataSize()) + for (ptr = hc->m_payloadStart, size = ptr->DataSize(); ptr < end; ptr += size, size = ptr->DataSize()) { - if(ptr->DataType() != DATATYPE_FREEBLOCK && ptr->DataType() != DATATYPE_CACHEDBLOCK) + if (ptr->DataType() != DATATYPE_FREEBLOCK && ptr->DataType() != DATATYPE_CACHEDBLOCK) { heapSize += ptr->DataSize(); } DumpObject(ptr); - //Don't let the stream get too big. + // Don't let the stream get too big. NANOCLR_CHECK_HRESULT(Stream_Send()); } } NANOCLR_FOREACH_NODE_END(); { - //Send HeapDump End Marker - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Stop, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( heapSize ); + // Send HeapDump End Marker + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapDump_Stop, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(heapSize); NANOCLR_CHECK_HRESULT(Stream_Send()); } NANOCLR_CLEANUP(); - //Flush out all data we've collected. Stopping the device without informing the program is a bad idea. + // Flush out all data we've collected. Stopping the device without informing the program is a bad idea. Stream_Flush(); NANOCLR_CLEANUP_END(); @@ -106,14 +109,14 @@ HRESULT CLR_PRF_Profiler::DumpRoots() NATIVE_PROFILE_CLR_DIAGNOSTICS(); NANOCLR_HEADER(); - //Root proto: - //8bits: CLR_PRF_CMDS::c_Profiling_HeapDump_Root - //32bits: Address of Root - //3bits: Source of Root: Finalizer, AppDomain, Assembly, Thread, Stack? - //Only when source is Stack??: 32bits: CLR_RT_MethodDef_Index + // Root proto: + // 8bits: CLR_PRF_CMDS::c_Profiling_HeapDump_Root + // 32bits: Address of Root + // 3bits: Source of Root: Finalizer, AppDomain, Assembly, Thread, Stack? + // Only when source is Stack??: 32bits: CLR_RT_MethodDef_Index - //Iterate through all the finalizers - NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,g_CLR_RT_ExecutionEngine.m_finalizersPending) + // Iterate through all the finalizers + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer, fin, g_CLR_RT_ExecutionEngine.m_finalizersPending) { _ASSERTE(fin->m_object); _ASSERTE(fin->m_object->DataType() != DATATYPE_FREEBLOCK); @@ -123,7 +126,7 @@ HRESULT CLR_PRF_Profiler::DumpRoots() } NANOCLR_FOREACH_NODE_END(); - NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,g_CLR_RT_ExecutionEngine.m_finalizersAlive) + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer, fin, g_CLR_RT_ExecutionEngine.m_finalizersAlive) { _ASSERTE(fin->m_object); _ASSERTE(fin->m_object->DataType() != DATATYPE_FREEBLOCK); @@ -134,28 +137,30 @@ HRESULT CLR_PRF_Profiler::DumpRoots() NANOCLR_FOREACH_NODE_END(); #if defined(NANOCLR_APPDOMAINS) - //Iterate through all the appdomains - NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,g_CLR_RT_ExecutionEngine.m_appDomains) + // Iterate through all the appdomains + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain, appDomain, g_CLR_RT_ExecutionEngine.m_appDomains) { DumpRoot(appDomain, CLR_PRF_CMDS::RootTypes::Root_AppDomain, 0, NULL); } NANOCLR_FOREACH_NODE_END(); #endif - //Iterate through all the assemblies. + // Iterate through all the assemblies. NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) { - DumpRoot( pASSM, CLR_PRF_CMDS::RootTypes::Root_Assembly, 0, NULL ); + DumpRoot(pASSM, CLR_PRF_CMDS::RootTypes::Root_Assembly, 0, NULL); } NANOCLR_FOREACH_ASSEMBLY_END(); - { //Iterate through all threads. - CLR_RT_DblLinkedList* threadLists[ 2 ] = { &g_CLR_RT_ExecutionEngine.m_threadsReady, &g_CLR_RT_ExecutionEngine.m_threadsWaiting }; - for(int list = 0; list < 2; list++) + { // Iterate through all threads. + CLR_RT_DblLinkedList *threadLists[2] = { + &g_CLR_RT_ExecutionEngine.m_threadsReady, + &g_CLR_RT_ExecutionEngine.m_threadsWaiting}; + for (int list = 0; list < 2; list++) { - NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,*threadLists[ list ]) + NANOCLR_FOREACH_NODE(CLR_RT_Thread, th, *threadLists[list]) { - DumpRoot( th, CLR_PRF_CMDS::RootTypes::Root_Thread, 0, NULL ); + DumpRoot(th, CLR_PRF_CMDS::RootTypes::Root_Thread, 0, NULL); } NANOCLR_FOREACH_NODE_END(); } @@ -166,50 +171,58 @@ HRESULT CLR_PRF_Profiler::DumpRoots() NANOCLR_NOCLEANUP(); } -void CLR_PRF_Profiler::DumpRoot( CLR_RT_HeapBlock* root, CLR_UINT32 type, CLR_UINT32 flags, CLR_RT_MethodDef_Index* source ) +void CLR_PRF_Profiler::DumpRoot( + CLR_RT_HeapBlock *root, + CLR_UINT32 type, + CLR_UINT32 flags, + CLR_RT_MethodDef_Index *source) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Root, CLR_PRF_CMDS::Bits::CommandHeader ); - DumpPointer( root ); - m_stream->WriteBits( type, CLR_PRF_CMDS::Bits::RootTypes ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapDump_Root, CLR_PRF_CMDS::Bits::CommandHeader); + DumpPointer(root); + m_stream->WriteBits(type, CLR_PRF_CMDS::Bits::RootTypes); _ASSERTE(!flags); - if(type == CLR_PRF_CMDS::RootTypes::Root_Stack) + if (type == CLR_PRF_CMDS::RootTypes::Root_Stack) { PackAndWriteBits(*source); - } else { + } + else + { _ASSERTE(source == NULL); } } -void CLR_PRF_Profiler::DumpObject( CLR_RT_HeapBlock* ptr ) +void CLR_PRF_Profiler::DumpObject(CLR_RT_HeapBlock *ptr) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - //Object Proto: - // Free blocked and cached blocks are considered free memory and are not dumped. - // All other types: - // 8 bits - Profiling_HeapDump_Object - // 32 bit pointer - // 16 bit size - // 8 bit - DataType() const - // 32 bits are TypeDef info >>>> iff DataType == CLASSTYPE || DataType == VALUETYPE || DataType == SZARRAY <<<< - // 16 bits are Array Level info >>>> iff DataType == SZARRAY <<<< - // 1 bit - Reference Follows - // 0 - No more references. End of Packet - // 1 - 32-bit pointer to reference follows. Repeat. + // Object Proto: + // Free blocked and cached blocks are considered free memory and are not dumped. + // All other types: + // 8 bits - Profiling_HeapDump_Object + // 32 bit pointer + // 16 bit size + // 8 bit - DataType() const + // 32 bits are TypeDef info >>>> iff DataType == CLASSTYPE || DataType == VALUETYPE || DataType == SZARRAY <<<< + // 16 bits are Array Level info >>>> iff DataType == SZARRAY <<<< + // 1 bit - Reference Follows + // 0 - No more references. End of Packet + // 1 - 32-bit pointer to reference follows. Repeat. CLR_DataType dt = ptr->DataType(); _ASSERTE(dt < DATATYPE_FIRST_INVALID); - _ASSERTE(sizeof(CLR_RT_HeapBlock) == 12); //HeapBlockObjectPacket in ProfilerPackets.cs assumes sizeof(CLR_RT_HeapBlock) == 12 + _ASSERTE( + sizeof(CLR_RT_HeapBlock) == + 12); // HeapBlockObjectPacket in ProfilerPackets.cs assumes sizeof(CLR_RT_HeapBlock) == 12 - if(dt != DATATYPE_FREEBLOCK && dt != DATATYPE_CACHEDBLOCK) + if (dt != DATATYPE_FREEBLOCK && dt != DATATYPE_CACHEDBLOCK) { - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Object, CLR_PRF_CMDS::Bits::CommandHeader ); - DumpPointer( ptr ); - PackAndWriteBits( ptr->DataSize() ); - m_stream->WriteBits( (CLR_UINT32)dt,CLR_PRF_CMDS::Bits::DataType ); - - switch(dt) + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapDump_Object, CLR_PRF_CMDS::Bits::CommandHeader); + DumpPointer(ptr); + PackAndWriteBits(ptr->DataSize()); + m_stream->WriteBits((CLR_UINT32)dt, CLR_PRF_CMDS::Bits::DataType); + + switch (dt) { case DATATYPE_BOOLEAN: case DATATYPE_I1: @@ -226,23 +239,25 @@ void CLR_PRF_Profiler::DumpObject( CLR_RT_HeapBlock* ptr ) case DATATYPE_DATETIME: case DATATYPE_TIMESPAN: case DATATYPE_STRING: - //Boxed primitives.. All are non-pointer types -- no references. + // Boxed primitives.. All are non-pointer types -- no references. case DATATYPE_REFLECTION: - //Has a reference to an assembly, but it's unlikely to be the only thing keeping the assembly alive. + // Has a reference to an assembly, but it's unlikely to be the only thing keeping the assembly alive. case DATATYPE_BINARY_BLOB_HEAD: - //Unknown/unmanaged data-type. No references. + // Unknown/unmanaged data-type. No references. case DATATYPE_SUBTHREAD: - //Owned by a DATATYPE_THREAD; Don't dump back-reference. + // Owned by a DATATYPE_THREAD; Don't dump back-reference. case DATATYPE_MEMORY_STREAM_DATA: - //No references at all -- usually, and when not, its a pointer to an externally shown character buffer used for deserialization. + // No references at all -- usually, and when not, its a pointer to an externally shown character buffer + // used for deserialization. case DATATYPE_IO_PORT: - //No references for normal GPIO; there is a structure for interrupts, but that doesn't seem to be stored on the managed heap. + // No references for normal GPIO; there is a structure for interrupts, but that doesn't seem to be + // stored on the managed heap. case DATATYPE_TIMER_HEAD: case DATATYPE_LOCK_OWNER_HEAD: case DATATYPE_LOCK_REQUEST_HEAD: case DATATYPE_SERIALIZER_DUPLICATE: case DATATYPE_SERIALIZER_STATE: - //No unique forward-looking references. + // No unique forward-looking references. break; case DATATYPE_OBJECT: @@ -251,199 +266,206 @@ void CLR_PRF_Profiler::DumpObject( CLR_RT_HeapBlock* ptr ) #if defined(NANOCLR_APPDOMAINS) case DATATYPE_TRANSPARENT_PROXY: #endif - { - DumpSingleReference( ptr ); - break; - } + { + DumpSingleReference(ptr); + break; + } case DATATYPE_CLASS: case DATATYPE_VALUETYPE: - { - CLR_RT_TypeDef_Index idx = ptr->ObjectCls(); - _ASSERTE(NANOCLR_INDEX_IS_VALID(idx)); - PackAndWriteBits( idx ); - DumpSingleReference( ptr->ObjectLock() ); - DumpListOfReferences( ptr + 1, ptr->DataSize() - 1 ); //All items in list should have DataSize() == 1 therefore ptr->DataSize() - 1 == number of items in list. - break; - } + { + CLR_RT_TypeDef_Index idx = ptr->ObjectCls(); + _ASSERTE(NANOCLR_INDEX_IS_VALID(idx)); + PackAndWriteBits(idx); + DumpSingleReference(ptr->ObjectLock()); + DumpListOfReferences( + ptr + 1, + ptr->DataSize() - 1); // All items in list should have DataSize() == 1 therefore ptr->DataSize() - 1 + // == number of items in list. + break; + } case DATATYPE_SZARRAY: + { + // Special case needed to dump out array data type and levels. + CLR_RT_HeapBlock_Array *array = (CLR_RT_HeapBlock_Array *)ptr; + + PackAndWriteBits(array->ReflectionDataConst().m_data.m_type); + PackAndWriteBits(array->ReflectionDataConst().m_levels); + + if (array->m_fReference) { - //Special case needed to dump out array data type and levels. - CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; - - PackAndWriteBits( array->ReflectionDataConst().m_data.m_type ); - PackAndWriteBits( array->ReflectionDataConst().m_levels ); - - if(array->m_fReference) - { - DumpListOfReferences( (CLR_RT_HeapBlock*)array->GetFirstElement(), array->m_numOfElements ); - } - break; + DumpListOfReferences((CLR_RT_HeapBlock *)array->GetFirstElement(), array->m_numOfElements); } + break; + } case DATATYPE_ASSEMBLY: - { - CLR_RT_Assembly* assembly = (CLR_RT_Assembly*)ptr; - DumpSingleReference( assembly->m_pFile ); + { + CLR_RT_Assembly *assembly = (CLR_RT_Assembly *)ptr; + DumpSingleReference(assembly->m_pFile); #if !defined(NANOCLR_APPDOMAINS) - DumpListOfReferences( assembly->m_pStaticFields, assembly->m_iStaticFields ); + DumpListOfReferences(assembly->m_pStaticFields, assembly->m_iStaticFields); #endif - break; - } + break; + } case DATATYPE_WEAKCLASS: - { - CLR_RT_HeapBlock_WeakReference* wr = (CLR_RT_HeapBlock_WeakReference*)ptr; - DumpSingleReference( wr->m_targetDirect ); - break; - } + { + CLR_RT_HeapBlock_WeakReference *wr = (CLR_RT_HeapBlock_WeakReference *)ptr; + DumpSingleReference(wr->m_targetDirect); + break; + } case DATATYPE_DELEGATE_HEAD: - { - CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)ptr; - DumpSingleReference( &dlg->m_object ); - break; - } + { + CLR_RT_HeapBlock_Delegate *dlg = (CLR_RT_HeapBlock_Delegate *)ptr; + DumpSingleReference(&dlg->m_object); + break; + } case DATATYPE_DELEGATELIST_HEAD: - { - CLR_RT_HeapBlock_Delegate_List* dlgList = (CLR_RT_HeapBlock_Delegate_List*)ptr; - DumpListOfReferences( dlgList->GetDelegates(), dlgList->m_length ); - break; - } + { + CLR_RT_HeapBlock_Delegate_List *dlgList = (CLR_RT_HeapBlock_Delegate_List *)ptr; + DumpListOfReferences(dlgList->GetDelegates(), dlgList->m_length); + break; + } case DATATYPE_THREAD: + { + CLR_RT_Thread *th = (CLR_RT_Thread *)ptr; + + DumpSingleReference(th->m_dlg); + DumpSingleReference(th->m_currentException.Dereference()); + + for (int i = 0; i < th->m_nestedExceptionsPos; i++) { - CLR_RT_Thread* th = (CLR_RT_Thread*)ptr; - - DumpSingleReference( th->m_dlg ); - DumpSingleReference( th->m_currentException.Dereference() ); - - for(int i=0; im_nestedExceptionsPos; i++) - { - CLR_RT_HeapBlock* except = th->m_nestedExceptions[ i ].m_exception; - _ASSERTE(!except || except->DataType() == DATATYPE_CLASS || except->DataType() == DATATYPE_OBJECT); - DumpSingleReference( except ); - } - - DumpListOfReferences( th->m_locks); - DumpSingleReference ( th->m_waitForObject ); - DumpListOfReferences( th->m_stackFrames ); - DumpListOfReferences( th->m_subThreads ); - break; + CLR_RT_HeapBlock *except = th->m_nestedExceptions[i].m_exception; + _ASSERTE(!except || except->DataType() == DATATYPE_CLASS || except->DataType() == DATATYPE_OBJECT); + DumpSingleReference(except); } + DumpListOfReferences(th->m_locks); + DumpSingleReference(th->m_waitForObject); + DumpListOfReferences(th->m_stackFrames); + DumpListOfReferences(th->m_subThreads); + break; + } + case DATATYPE_STACK_FRAME: - { - CLR_RT_StackFrame* stack = (CLR_RT_StackFrame*)ptr; - DumpListOfReferences( stack->m_arguments, stack->m_call.m_target->numArgs ); - DumpListOfReferences( stack->m_locals , stack->m_call.m_target->numLocals ); - DumpListOfReferences( stack->m_evalStack, stack->TopValuePosition() ); - break; - } + { + CLR_RT_StackFrame *stack = (CLR_RT_StackFrame *)ptr; + DumpListOfReferences(stack->m_arguments, stack->m_call.m_target->numArgs); + DumpListOfReferences(stack->m_locals, stack->m_call.m_target->numLocals); + DumpListOfReferences(stack->m_evalStack, stack->TopValuePosition()); + break; + } case DATATYPE_OBJECT_TO_EVENT: - { - CLR_RT_ObjectToEvent_Source* otes = (CLR_RT_ObjectToEvent_Source*)ptr; - DumpSingleReference( otes->m_eventPtr ); //The managed object should reference this obj, which references the event. - break; - } + { + CLR_RT_ObjectToEvent_Source *otes = (CLR_RT_ObjectToEvent_Source *)ptr; + DumpSingleReference( + otes->m_eventPtr); // The managed object should reference this obj, which references the event. + break; + } case DATATYPE_LOCK_HEAD: - { - //Object points to Lock Head, Thread points to Lock Head, Lock Head points to list of lock owners and requests - CLR_RT_HeapBlock_Lock* lock = (CLR_RT_HeapBlock_Lock*)ptr; - DumpListOfReferences( lock->m_owners ); - DumpListOfReferences( lock->m_requests ); - break; - } + { + // Object points to Lock Head, Thread points to Lock Head, Lock Head points to list of lock owners and + // requests + CLR_RT_HeapBlock_Lock *lock = (CLR_RT_HeapBlock_Lock *)ptr; + DumpListOfReferences(lock->m_owners); + DumpListOfReferences(lock->m_requests); + break; + } case DATATYPE_ENDPOINT_HEAD: - { - CLR_RT_HeapBlock_EndPoint* ep = (CLR_RT_HeapBlock_EndPoint*)ptr; - DumpListOfReferences( ep->m_messages ); - break; - } + { + CLR_RT_HeapBlock_EndPoint *ep = (CLR_RT_HeapBlock_EndPoint *)ptr; + DumpListOfReferences(ep->m_messages); + break; + } case DATATYPE_WAIT_FOR_OBJECT_HEAD: - { - CLR_RT_HeapBlock_WaitForObject* wfo = (CLR_RT_HeapBlock_WaitForObject*)ptr; - DumpListOfReferences(wfo->GetWaitForObjects(), wfo->m_cObjects); - break; - } + { + CLR_RT_HeapBlock_WaitForObject *wfo = (CLR_RT_HeapBlock_WaitForObject *)ptr; + DumpListOfReferences(wfo->GetWaitForObjects(), wfo->m_cObjects); + break; + } case DATATYPE_FINALIZER_HEAD: - { - CLR_RT_HeapBlock_Finalizer* f = (CLR_RT_HeapBlock_Finalizer*)ptr; - DumpSingleReference( f->m_object ); - break; - } + { + CLR_RT_HeapBlock_Finalizer *f = (CLR_RT_HeapBlock_Finalizer *)ptr; + DumpSingleReference(f->m_object); + break; + } case DATATYPE_MEMORY_STREAM_HEAD: - { - CLR_RT_HeapBlock_MemoryStream* ms = (CLR_RT_HeapBlock_MemoryStream*)ptr; - DumpListOfReferences( ms->m_buffers ); - break; - } + { + CLR_RT_HeapBlock_MemoryStream *ms = (CLR_RT_HeapBlock_MemoryStream *)ptr; + DumpListOfReferences(ms->m_buffers); + break; + } case DATATYPE_SERIALIZER_HEAD: - { - CLR_RT_BinaryFormatter* bf = (CLR_RT_BinaryFormatter*)ptr; - DumpSingleReference ( bf->m_stream ); - DumpListOfReferences( bf->m_duplicates ); - DumpListOfReferences( bf->m_states ); - break; - } + { + CLR_RT_BinaryFormatter *bf = (CLR_RT_BinaryFormatter *)ptr; + DumpSingleReference(bf->m_stream); + DumpListOfReferences(bf->m_duplicates); + DumpListOfReferences(bf->m_states); + break; + } #if defined(NANOCLR_APPDOMAINS) - case DATATYPE_APPDOMAIN_HEAD: + case DATATYPE_APPDOMAIN_HEAD: { - CLR_RT_AppDomain* appDomain = (CLR_RT_AppDomain*)ptr; - DumpListOfReferences( appDomain->m_appDomainAssemblies ); - DumpSingleReference ( appDomain->m_globalLock ); - DumpSingleReference ( appDomain->m_strName ); - DumpSingleReference ( appDomain->m_outOfMemoryException ); + CLR_RT_AppDomain *appDomain = (CLR_RT_AppDomain *)ptr; + DumpListOfReferences(appDomain->m_appDomainAssemblies); + DumpSingleReference(appDomain->m_globalLock); + DumpSingleReference(appDomain->m_strName); + DumpSingleReference(appDomain->m_outOfMemoryException); break; } - case DATATYPE_APPDOMAIN_ASSEMBLY: + case DATATYPE_APPDOMAIN_ASSEMBLY: { - CLR_RT_AppDomainAssembly* appDomainAssembly = (CLR_RT_AppDomainAssembly*)ptr; - DumpListOfReferences( appDomainAssembly->m_pStaticFields, appDomainAssembly->m_assembly->m_iStaticFields ); + CLR_RT_AppDomainAssembly *appDomainAssembly = (CLR_RT_AppDomainAssembly *)ptr; + DumpListOfReferences( + appDomainAssembly->m_pStaticFields, + appDomainAssembly->m_assembly->m_iStaticFields); break; } #endif - default: + default: _ASSERTE(false); break; } DumpEndOfRefsList(); - } //if(dt != DATATYPE_FREEBLOCK && dt != DATATYPE_CACHEDBLOCK) + } // if(dt != DATATYPE_FREEBLOCK && dt != DATATYPE_CACHEDBLOCK) } -CLR_RT_HeapBlock* CLR_PRF_Profiler::FindReferencedObject(CLR_RT_HeapBlock* ref) +CLR_RT_HeapBlock *CLR_PRF_Profiler::FindReferencedObject(CLR_RT_HeapBlock *ref) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - while(ref) + while (ref) { CLR_DataType dt = ref->DataType(); - switch(dt) + switch (dt) { - case DATATYPE_BYREF: - case DATATYPE_OBJECT: - ref = ref->Dereference(); - break; + case DATATYPE_BYREF: + case DATATYPE_OBJECT: + ref = ref->Dereference(); + break; #if defined(NANOCLR_APPDOMAINS) - case DATATYPE_TRANSPARENT_PROXY: - ref = ref->TransparentProxyDereference(); - break; + case DATATYPE_TRANSPARENT_PROXY: + ref = ref->TransparentProxyDereference(); + break; #endif - case DATATYPE_ARRAY_BYREF: - ref = ref->Array(); - default: - return ref; + case DATATYPE_ARRAY_BYREF: + ref = ref->Array(); + default: + return ref; } } return NULL; @@ -455,34 +477,34 @@ void CLR_PRF_Profiler::DumpEndOfRefsList() SendFalse(); } -void CLR_PRF_Profiler::DumpPointer(void* ptr) +void CLR_PRF_Profiler::DumpPointer(void *ptr) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - PackAndWriteBits( (CLR_UINT32)((CLR_UINT8*)ptr - s_CLR_RT_Heap.m_location) ); + PackAndWriteBits((CLR_UINT32)((CLR_UINT8 *)ptr - s_CLR_RT_Heap.m_location)); } -void CLR_PRF_Profiler::DumpSingleReference(CLR_RT_HeapBlock* ptr) +void CLR_PRF_Profiler::DumpSingleReference(CLR_RT_HeapBlock *ptr) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); ptr = FindReferencedObject(ptr); - if(ptr) + if (ptr) { SendTrue(); DumpPointer(ptr); } } -void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_HeapBlock* firstItem, CLR_UINT16 count) +void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_HeapBlock *firstItem, CLR_UINT16 count) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - CLR_RT_HeapBlock* ptr; - for(ptr = firstItem; count > 0; ptr += ptr->DataSize(), count--) + CLR_RT_HeapBlock *ptr; + for (ptr = firstItem; count > 0; ptr += ptr->DataSize(), count--) { DumpSingleReference(ptr); } } -void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_DblLinkedList& list) +void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_DblLinkedList &list) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node, ptr, list) @@ -497,10 +519,10 @@ void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_DblLinkedList& list) void CLR_PRF_Profiler::Timestamp() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - //Send Profiling Timestamp - CLR_UINT32 time = (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) - >> CLR_PRF_CMDS::Bits::TimestampShift); - if(time > m_lastTimestamp) + // Send Profiling Timestamp + CLR_UINT32 time = + (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) >> CLR_PRF_CMDS::Bits::TimestampShift); + if (time > m_lastTimestamp) { m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Timestamp, CLR_PRF_CMDS::Bits::CommandHeader); PackAndWriteBits(time - m_lastTimestamp); @@ -512,7 +534,7 @@ void CLR_PRF_Profiler::Timestamp() //--// #if defined(NANOCLR_PROFILE_NEW_CALLS) -HRESULT CLR_PRF_Profiler::RecordContextSwitch(CLR_RT_Thread* nextThread) +HRESULT CLR_PRF_Profiler::RecordContextSwitch(CLR_RT_Thread *nextThread) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); NANOCLR_HEADER(); @@ -520,11 +542,11 @@ HRESULT CLR_PRF_Profiler::RecordContextSwitch(CLR_RT_Thread* nextThread) CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); - if(CLR_EE_PRF_IS(Calls)) + if (CLR_EE_PRF_IS(Calls)) { Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Calls_CtxSwitch, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( nextThread->m_pid ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Calls_CtxSwitch, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(nextThread->m_pid); m_currentThreadPID = nextThread->m_pid; NANOCLR_CHECK_HRESULT(Stream_Send()); } @@ -532,19 +554,19 @@ HRESULT CLR_PRF_Profiler::RecordContextSwitch(CLR_RT_Thread* nextThread) NANOCLR_NOCLEANUP(); } -HRESULT CLR_PRF_Profiler::RecordFunctionCall(CLR_RT_Thread* th, CLR_RT_MethodDef_Index md) +HRESULT CLR_PRF_Profiler::RecordFunctionCall(CLR_RT_Thread *th, CLR_RT_MethodDef_Index md) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); NANOCLR_HEADER(); _ASSERTE(th); - if(CLR_EE_PRF_IS(Calls)) + if (CLR_EE_PRF_IS(Calls)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); - if(th->m_pid != m_currentThreadPID) + if (th->m_pid != m_currentThreadPID) { - NANOCLR_CHECK_HRESULT(RecordContextSwitch( th )); + NANOCLR_CHECK_HRESULT(RecordContextSwitch(th)); } else { @@ -555,7 +577,7 @@ HRESULT CLR_PRF_Profiler::RecordFunctionCall(CLR_RT_Thread* th, CLR_RT_MethodDef m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Calls_Call, CLR_PRF_CMDS::Bits::CommandHeader); - if(md.Assembly() == m_currentAssembly) + if (md.Assembly() == m_currentAssembly) { SendFalse(); } @@ -572,19 +594,19 @@ HRESULT CLR_PRF_Profiler::RecordFunctionCall(CLR_RT_Thread* th, CLR_RT_MethodDef NANOCLR_NOCLEANUP(); } -HRESULT CLR_PRF_Profiler::RecordFunctionReturn(CLR_RT_Thread* th, CLR_PROF_CounterCallChain& prof) +HRESULT CLR_PRF_Profiler::RecordFunctionReturn(CLR_RT_Thread *th, CLR_PROF_CounterCallChain &prof) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); NANOCLR_HEADER(); _ASSERTE(th); - if(CLR_EE_PRF_IS(Calls)) + if (CLR_EE_PRF_IS(Calls)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); - if(th->m_pid != m_currentThreadPID) + if (th->m_pid != m_currentThreadPID) { - NANOCLR_CHECK_HRESULT(RecordContextSwitch( th )); + NANOCLR_CHECK_HRESULT(RecordContextSwitch(th)); } else { @@ -606,52 +628,52 @@ HRESULT CLR_PRF_Profiler::RecordFunctionReturn(CLR_RT_Thread* th, CLR_PROF_Count #if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) -void CLR_PRF_Profiler::TrackObjectCreation( CLR_RT_HeapBlock* ptr ) +void CLR_PRF_Profiler::TrackObjectCreation(CLR_RT_HeapBlock *ptr) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); _ASSERTE(ptr); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); CLR_UINT8 dt = ptr->DataType(); - if(dt != DATATYPE_STACK_FRAME && dt != DATATYPE_BINARY_BLOB_HEAD) + if (dt != DATATYPE_STACK_FRAME && dt != DATATYPE_BINARY_BLOB_HEAD) { Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Allocs_Alloc, CLR_PRF_CMDS::Bits::CommandHeader ); - DumpPointer( ptr ); - PackAndWriteBits( ptr->DataSize() ); - m_stream->WriteBits( (CLR_UINT32)dt, CLR_PRF_CMDS::Bits::DataType ); - if(dt == DATATYPE_CLASS || dt == DATATYPE_VALUETYPE) + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Allocs_Alloc, CLR_PRF_CMDS::Bits::CommandHeader); + DumpPointer(ptr); + PackAndWriteBits(ptr->DataSize()); + m_stream->WriteBits((CLR_UINT32)dt, CLR_PRF_CMDS::Bits::DataType); + if (dt == DATATYPE_CLASS || dt == DATATYPE_VALUETYPE) { - PackAndWriteBits( ptr->ObjectCls() ); + PackAndWriteBits(ptr->ObjectCls()); } - else if(dt == DATATYPE_SZARRAY) + else if (dt == DATATYPE_SZARRAY) { - CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; - PackAndWriteBits( array->ReflectionDataConst().m_data.m_type ); - PackAndWriteBits( array->ReflectionDataConst().m_levels ); + CLR_RT_HeapBlock_Array *array = (CLR_RT_HeapBlock_Array *)ptr; + PackAndWriteBits(array->ReflectionDataConst().m_data.m_type); + PackAndWriteBits(array->ReflectionDataConst().m_levels); } Stream_Send(); } } } -void CLR_PRF_Profiler::TrackObjectDeletion( CLR_RT_HeapBlock* ptr ) +void CLR_PRF_Profiler::TrackObjectDeletion(CLR_RT_HeapBlock *ptr) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); _ASSERTE(ptr); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); CLR_UINT8 dt = ptr->DataType(); - if(dt != DATATYPE_STACK_FRAME && dt != DATATYPE_CACHEDBLOCK ) + if (dt != DATATYPE_STACK_FRAME && dt != DATATYPE_CACHEDBLOCK) { Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Allocs_Delete, CLR_PRF_CMDS::Bits::CommandHeader ); - DumpPointer( ptr ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Allocs_Delete, CLR_PRF_CMDS::Bits::CommandHeader); + DumpPointer(ptr); Stream_Send(); } } @@ -660,22 +682,22 @@ void CLR_PRF_Profiler::TrackObjectDeletion( CLR_RT_HeapBlock* ptr ) void CLR_PRF_Profiler::TrackObjectRelocation() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); - CLR_RT_GarbageCollector::RelocationRegion* relocBlocks = g_CLR_RT_GarbageCollector.m_relocBlocks; + CLR_RT_GarbageCollector::RelocationRegion *relocBlocks = g_CLR_RT_GarbageCollector.m_relocBlocks; size_t relocCount = g_CLR_RT_GarbageCollector.m_relocCount; Timestamp(); m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Allocs_Relloc, CLR_PRF_CMDS::Bits::CommandHeader); - PackAndWriteBits(( CLR_UINT32)relocCount ); + PackAndWriteBits((CLR_UINT32)relocCount); - for(size_t i = 0; i < relocCount; i++) + for (size_t i = 0; i < relocCount; i++) { - DumpPointer( relocBlocks[ i ].m_start); - DumpPointer( relocBlocks[ i ].m_end ); - PackAndWriteBits( relocBlocks[i].m_offset ); + DumpPointer(relocBlocks[i].m_start); + DumpPointer(relocBlocks[i].m_end); + PackAndWriteBits(relocBlocks[i].m_offset); } } } @@ -683,13 +705,13 @@ void CLR_PRF_Profiler::TrackObjectRelocation() void CLR_PRF_Profiler::RecordGarbageCollectionBegin() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_GarbageCollect_Begin, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_GarbageCollect_Begin, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(g_CLR_RT_GarbageCollector.m_freeBytes); Stream_Send(); } } @@ -697,13 +719,13 @@ void CLR_PRF_Profiler::RecordGarbageCollectionBegin() void CLR_PRF_Profiler::RecordGarbageCollectionEnd() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_GarbageCollect_End, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_GarbageCollect_End, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(g_CLR_RT_GarbageCollector.m_freeBytes); Stream_Send(); } } @@ -711,13 +733,13 @@ void CLR_PRF_Profiler::RecordGarbageCollectionEnd() void CLR_PRF_Profiler::RecordHeapCompactionBegin() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapCompact_Begin, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapCompact_Begin, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(g_CLR_RT_GarbageCollector.m_freeBytes); Stream_Send(); } } @@ -725,13 +747,13 @@ void CLR_PRF_Profiler::RecordHeapCompactionBegin() void CLR_PRF_Profiler::RecordHeapCompactionEnd() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - if(CLR_EE_PRF_IS(Allocations)) + if (CLR_EE_PRF_IS(Allocations)) { CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); Timestamp(); - m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapCompact_End, CLR_PRF_CMDS::Bits::CommandHeader ); - PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapCompact_End, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(g_CLR_RT_GarbageCollector.m_freeBytes); Stream_Send(); } } @@ -743,13 +765,13 @@ void CLR_PRF_Profiler::RecordHeapCompactionEnd() void CLR_PRF_Profiler::SendTrue() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - m_stream->WriteBits( (CLR_UINT32)1, 1 ); + m_stream->WriteBits((CLR_UINT32)1, 1); } void CLR_PRF_Profiler::SendFalse() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - m_stream->WriteBits( (CLR_UINT32)0, 1 ); + m_stream->WriteBits((CLR_UINT32)0, 1); } void CLR_PRF_Profiler::PackAndWriteBits(CLR_UINT32 value) @@ -761,32 +783,53 @@ void CLR_PRF_Profiler::PackAndWriteBits(CLR_UINT32 value) */ _ASSERTE(sizeof(CLR_UINT32) == 4); - const CLR_UINT32 SHIFT_PER_NIBBLE = 2; //2^2 = 4 bits per nibble + const CLR_UINT32 SHIFT_PER_NIBBLE = 2; // 2^2 = 4 bits per nibble CLR_UINT32 nibbles = 1; - if( value & 0xF0000000) { nibbles = 8; } - else if(value & 0x0F000000) { nibbles = 7; } - else if(value & 0x00F00000) { nibbles = 6; } - else if(value & 0x000F0000) { nibbles = 5; } - else if(value & 0x0000F000) { nibbles = 4; } - else if(value & 0x00000F00) { nibbles = 3; } - else if(value & 0x000000F0) { nibbles = 2; } + if (value & 0xF0000000) + { + nibbles = 8; + } + else if (value & 0x0F000000) + { + nibbles = 7; + } + else if (value & 0x00F00000) + { + nibbles = 6; + } + else if (value & 0x000F0000) + { + nibbles = 5; + } + else if (value & 0x0000F000) + { + nibbles = 4; + } + else if (value & 0x00000F00) + { + nibbles = 3; + } + else if (value & 0x000000F0) + { + nibbles = 2; + } - m_stream->WriteBits( nibbles - 1, CLR_PRF_CMDS::Bits::NibbleCount ); - m_stream->WriteBits( value, nibbles << SHIFT_PER_NIBBLE ); + m_stream->WriteBits(nibbles - 1, CLR_PRF_CMDS::Bits::NibbleCount); + m_stream->WriteBits(value, nibbles << SHIFT_PER_NIBBLE); } -void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_TypeDef_Index& typeDef) +void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_TypeDef_Index &typeDef) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - PackAndWriteBits( typeDef.Assembly() ); - PackAndWriteBits( typeDef.Type() ); + PackAndWriteBits(typeDef.Assembly()); + PackAndWriteBits(typeDef.Type()); } -void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_MethodDef_Index& methodDef) +void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_MethodDef_Index &methodDef) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); - PackAndWriteBits( methodDef.Assembly() ); - PackAndWriteBits( methodDef.Method() ); + PackAndWriteBits(methodDef.Assembly()); + PackAndWriteBits(methodDef.Method()); } //--// @@ -797,13 +840,13 @@ HRESULT CLR_PRF_Profiler::Stream_Send() NANOCLR_HEADER(); const int BUFFER_THRESHOLD_BYTES = CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize * 2 / 3; - const int BUFFER_THRESHOLD_BITS = BUFFER_THRESHOLD_BYTES << 3; + const int BUFFER_THRESHOLD_BITS = BUFFER_THRESHOLD_BYTES << 3; - if(m_stream->BitsWritten() >= BUFFER_THRESHOLD_BITS) + if (m_stream->BitsWritten() >= BUFFER_THRESHOLD_BITS) { NANOCLR_CHECK_HRESULT(Stream_Flush()); - } - //else { Stream isn't above threshold; allow to cache. } + } + // else { Stream isn't above threshold; allow to cache. } NANOCLR_NOCLEANUP(); } @@ -813,39 +856,43 @@ HRESULT CLR_PRF_Profiler::Stream_Flush() NATIVE_PROFILE_CLR_DIAGNOSTICS(); NANOCLR_HEADER(); - //These need to be paired; If this function is ever used to send multiple stream types, each should get their own packet sequence id. + // These need to be paired; If this function is ever used to send multiple stream types, each should get their own + // packet sequence id. const CLR_UINT32 messageType = CLR_DBG_Commands::c_Profiling_Stream; - CLR_UINT8 buffer[ 2*sizeof(CLR_UINT16) + CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize ]; - CLR_DBG_Commands::Profiling_Stream* packet = (CLR_DBG_Commands::Profiling_Stream*)buffer; + CLR_UINT8 buffer[2 * sizeof(CLR_UINT16) + CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize]; + CLR_DBG_Commands::Profiling_Stream *packet = (CLR_DBG_Commands::Profiling_Stream *)buffer; NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_MemoryStream::Buffer, ptr, m_stream->m_buffers) { int payloadLength = ptr->m_length; - if(payloadLength > 0) + if (payloadLength > 0) { _ASSERTE(sizeof(ptr->m_payload) == CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize); int bitLength = payloadLength * 8; - if(ptr == m_stream->m_current) + if (ptr == m_stream->m_current) { bitLength -= m_stream->m_avail; } packet->m_bitLen = bitLength; packet->m_seqId = m_packetSeqId++; - memcpy(&packet[ 1 ], ptr->m_payload, payloadLength); + memcpy(&packet[1], ptr->m_payload, payloadLength); int packetLength = sizeof(CLR_DBG_Commands::Profiling_Stream) + payloadLength; - if(!CLR_EE_DBG_EVENT_SEND(messageType, packetLength, buffer, WP_Flags_c_NonCritical)) + if (!CLR_EE_DBG_EVENT_SEND(messageType, packetLength, buffer, WP_Flags_c_NonCritical)) { _ASSERTE(false); NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); } } - //Don't go past the cursor. - if(ptr == m_stream->m_current) { break; } + // Don't go past the cursor. + if (ptr == m_stream->m_current) + { + break; + } } NANOCLR_FOREACH_NODE_END(); @@ -854,5 +901,4 @@ HRESULT CLR_PRF_Profiler::Stream_Flush() NANOCLR_NOCLEANUP(); } -#endif //#if defined(NANOCLR_PROFILE_NEW) - +#endif // #if defined(NANOCLR_PROFILE_NEW) From 5a209769e5c07018d2716ee1cc9b2a25ef333100 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 24 Aug 2023 15:52:10 +0100 Subject: [PATCH 458/572] Fix switch case fall-through in profiler --- src/CLR/Diagnostics/Profiler.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index 55e31bb035..30d46cb91d 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -448,26 +448,33 @@ void CLR_PRF_Profiler::DumpObject(CLR_RT_HeapBlock *ptr) CLR_RT_HeapBlock *CLR_PRF_Profiler::FindReferencedObject(CLR_RT_HeapBlock *ref) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); + while (ref) { CLR_DataType dt = ref->DataType(); + switch (dt) { case DATATYPE_BYREF: case DATATYPE_OBJECT: ref = ref->Dereference(); break; + #if defined(NANOCLR_APPDOMAINS) case DATATYPE_TRANSPARENT_PROXY: ref = ref->TransparentProxyDereference(); break; #endif + case DATATYPE_ARRAY_BYREF: ref = ref->Array(); + return ref; + default: return ref; } } + return NULL; } From 98356ed4cff596ea92bb6da5246de2c5680c54a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 24 Aug 2023 15:52:48 +0100 Subject: [PATCH 459/572] Fix missing return value in debugger profiling command --- src/CLR/Debugger/Debugger.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/CLR/Debugger/Debugger.cpp b/src/CLR/Debugger/Debugger.cpp index 4c002646f4..adfed6eb3f 100644 --- a/src/CLR/Debugger/Debugger.cpp +++ b/src/CLR/Debugger/Debugger.cpp @@ -3108,6 +3108,8 @@ bool CLR_DBG_Debugger::Profiling_Command(WP_Message *msg) default: return false; } + + return true; } bool CLR_DBG_Debugger::Profiling_ChangeConditions(WP_Message *msg) From 295ce74b8847b154bbed71441541ee6fd4866dbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 24 Aug 2023 16:21:59 +0100 Subject: [PATCH 460/572] Fix RTM build for Profiler::DumpRoot --- src/CLR/Diagnostics/Profiler.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index 30d46cb91d..689103762b 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -178,11 +178,19 @@ void CLR_PRF_Profiler::DumpRoot( CLR_RT_MethodDef_Index *source) { NATIVE_PROFILE_CLR_DIAGNOSTICS(); + +#if defined(BUILD_RTM) + (void)flags; +#endif + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_HeapDump_Root, CLR_PRF_CMDS::Bits::CommandHeader); + DumpPointer(root); + m_stream->WriteBits(type, CLR_PRF_CMDS::Bits::RootTypes); _ASSERTE(!flags); + if (type == CLR_PRF_CMDS::RootTypes::Root_Stack) { PackAndWriteBits(*source); From ff7d77cc20159e5ca45fdd968da89a0c850a24e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 28 Aug 2023 10:12:46 +0100 Subject: [PATCH 461/572] Fix target names - Requested by Mike Muegel. --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 2 +- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 846e8735d5..efd0294aa9 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -59,7 +59,7 @@ ], "hidden": false, "cacheVariables": { - "TARGET_NAME": "SKY_EEVB", + "TARGET_NAME": "SKY_EEVB_Debug", "NF_BUILD_RTM": "ON" } } diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index 625a5a513a..7458268886 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -58,7 +58,7 @@ ], "hidden": false, "cacheVariables": { - "TARGET_NAME": "Si5575_CEVB", + "TARGET_NAME": "Si5575_CEVB_Release", "NF_BUILD_RTM": "ON" } } From d16e21b62622a1d878f92e3159f0cacf2c57bcd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 28 Aug 2023 19:40:39 +0100 Subject: [PATCH 462/572] Fix SendMemoryLayout - Now sending real managed heap start address. ***NO_CI*** --- src/CLR/Diagnostics/Profiler.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index 4e5e87e753..5c9fd30bd5 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -41,10 +41,12 @@ HRESULT CLR_PRF_Profiler::Profiler_Cleanup() void CLR_PRF_Profiler::SendMemoryLayout() { NATIVE_PROFILE_CLR_DIAGNOSTICS(); + // Send Memory Layout m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Memory_Layout, CLR_PRF_CMDS::Bits::CommandHeader); - PackAndWriteBits(0); + PackAndWriteBits((CLR_UINT32)s_CLR_RT_Heap.m_location); PackAndWriteBits(s_CLR_RT_Heap.m_size); + Stream_Send(); } From bb9c082369e18c2611a250db6e1b2ca6d3bd36a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 15:40:24 +0100 Subject: [PATCH 463/572] Fix output of x64 addresses in nanoCLR WIN64 build --- src/CLR/Core/GarbageCollector_Info.cpp | 60 ++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 9 deletions(-) diff --git a/src/CLR/Core/GarbageCollector_Info.cpp b/src/CLR/Core/GarbageCollector_Info.cpp index 987e8a2ccc..a451bea7e0 100644 --- a/src/CLR/Core/GarbageCollector_Info.cpp +++ b/src/CLR/Core/GarbageCollector_Info.cpp @@ -125,7 +125,11 @@ void CLR_RT_GarbageCollector::ValidateBlockNotInFreeList( CLR_RT_DblLinkedList& if(ptr <= dst && dst < ptrEnd) { - CLR_Debug::Printf( "Pointer into free list!! %08x %08x %08x\r\n", dst, ptr, ptrEnd ); +#if _WIN64 + CLR_Debug::Printf("Pointer into free list!! %I64X %I64X %I64X\r\n", dst, ptr, ptrEnd); +#else + CLR_Debug::Printf("Pointer into free list!! %08x %08x %08x\r\n", dst, ptr, ptrEnd); +#endif NANOCLR_DEBUG_STOP(); } @@ -205,20 +209,30 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker( void** ref ) if(s_mapOldToRecord.find( ref ) != s_mapOldToRecord.end()) { - CLR_Debug::Printf( "Duplicate base OLD: %08x\r\n", ref ); +#if _WIN64 + CLR_Debug::Printf("Duplicate base OLD: %I64X\r\n", ref); +#else + CLR_Debug::Printf("Duplicate base OLD: %08x\r\n", ref); +#endif + + NANOCLR_DEBUG_STOP(); } s_mapOldToRecord[ ref ] = ptr; if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst, false )) { - CLR_Debug::Printf( "Some data points into a free list: %08x\r\n", dst ); +#if _WIN64 + CLR_Debug::Printf("Some data points into a free list: %I64X\r\n", dst); +#else + CLR_Debug::Printf("Some data points into a free list: %08x\r\n", dst); +#endif NANOCLR_DEBUG_STOP(); } } - return false; + return true; } void CLR_RT_GarbageCollector::TestPointers_PopulateOld() @@ -264,7 +278,12 @@ void CLR_RT_GarbageCollector::TestPointers_Remap() if(s_mapNewToRecord.find( ref ) != s_mapNewToRecord.end()) { - CLR_Debug::Printf( "Duplicate base NEW: %08x\r\n", ref ); +#if _WIN64 + CLR_Debug::Printf("Duplicate base NEW: %I64X\r\n", ref); +#else + CLR_Debug::Printf("Duplicate base NEW: %08x\r\n", ref); +#endif + NANOCLR_DEBUG_STOP(); } s_mapNewToRecord[ ref ] = ptr; @@ -291,23 +310,46 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker( void** ref ) if(ptr->newPtr != dst) { - CLR_Debug::Printf( "Bad pointer: %08x %08x\r\n", ptr->newPtr, dst ); +#if _WIN64 + CLR_Debug::Printf("Bad pointer: %I64X %I64X\r\n", ptr->newPtr, dst); +#else + CLR_Debug::Printf("Bad pointer: %08x %08x\r\n", ptr->newPtr, dst); +#endif + NANOCLR_DEBUG_STOP(); } else if(ptr->data != *dst) { - CLR_Debug::Printf( "Bad data: %08x %08x\r\n", ptr->data, *dst ); +#if _WIN64 + CLR_Debug::Printf("Bad data: %I64X %I64X\r\n", ptr->data, *dst); +#else + CLR_Debug::Printf("Bad data: %08x %08x\r\n", ptr->data, *dst); +#endif + + NANOCLR_DEBUG_STOP(); } if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst, false )) { - CLR_Debug::Printf( "Some data points into a free list: %08x\r\n", dst ); +#if _WIN64 + CLR_Debug::Printf("Some data points into a free list: %I64X\r\n", dst); +#else + CLR_Debug::Printf("Some data points into a free list: %08x\r\n", dst); +#endif NANOCLR_DEBUG_STOP(); } + + return true; } else { - CLR_Debug::Printf( "Bad base: %08x\r\n", ref ); +#if _WIN64 + CLR_Debug::Printf("Bad base: 0x%0I64X\r\n", ref); +#else + CLR_Debug::Printf("Bad base: 0x%08x\r\n", ref); +#endif + + NANOCLR_DEBUG_STOP(); } } From 028a66a9c87eec4e708a9fbc8866b89c6f47c7b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 15:41:50 +0100 Subject: [PATCH 464/572] Fix code style formatting --- src/CLR/Core/GarbageCollector_Info.cpp | 170 +++++++++++++------------ 1 file changed, 89 insertions(+), 81 deletions(-) diff --git a/src/CLR/Core/GarbageCollector_Info.cpp b/src/CLR/Core/GarbageCollector_Info.cpp index a451bea7e0..3616091429 100644 --- a/src/CLR/Core/GarbageCollector_Info.cpp +++ b/src/CLR/Core/GarbageCollector_Info.cpp @@ -9,37 +9,41 @@ #if defined(NANOCLR_GC_VERBOSE) -void CLR_RT_GarbageCollector::GC_Stats( int& resNumberObjects, int& resSizeObjects, int& resNumberEvents, int& resSizeEvents ) +void CLR_RT_GarbageCollector::GC_Stats( + int &resNumberObjects, + int &resSizeObjects, + int &resNumberEvents, + int &resSizeEvents) { NATIVE_PROFILE_CLR_CORE(); resNumberObjects = 0; - resSizeObjects = 0; + resSizeObjects = 0; - resNumberEvents = 0; - resSizeEvents = 0; + resNumberEvents = 0; + resSizeEvents = 0; - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, g_CLR_RT_ExecutionEngine.m_heap) { - CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; - CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + CLR_RT_HeapBlock_Node *ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node *end = hc->m_payloadEnd; - while(ptr < end) + while (ptr < end) { CLR_UINT16 size = ptr->DataSize(); - hc->ValidateBlock( ptr ); + hc->ValidateBlock(ptr); - if(ptr->DataType() != DATATYPE_FREEBLOCK) + if (ptr->DataType() != DATATYPE_FREEBLOCK) { - if(ptr->IsEvent()) + if (ptr->IsEvent()) { resNumberEvents += 1; - resSizeEvents += size * sizeof(CLR_RT_HeapBlock); + resSizeEvents += size * sizeof(CLR_RT_HeapBlock); } else { resNumberObjects += 1; - resSizeObjects += size * sizeof(CLR_RT_HeapBlock); + resSizeObjects += size * sizeof(CLR_RT_HeapBlock); } } @@ -49,40 +53,39 @@ void CLR_RT_GarbageCollector::GC_Stats( int& resNumberObjects, int& resSizeObjec NANOCLR_FOREACH_NODE_END(); } - -static void DumpTimeout( CLR_RT_Thread* th, CLR_INT64& t ) +static void DumpTimeout(CLR_RT_Thread *th, CLR_INT64 &t) { NATIVE_PROFILE_CLR_CORE(); - CLR_Debug::Printf( ": %d", th ? th->m_pid : -1 ); + CLR_Debug::Printf(": %d", th ? th->m_pid : -1); - if(t < TIMEOUT_INFINITE) + if (t < TIMEOUT_INFINITE) { t -= HAL_Time_CurrentTime(); - CLR_Debug::Printf( " %d", (int)t ); + CLR_Debug::Printf(" %d", (int)t); } else { - CLR_Debug::Printf( " INFINITE" ); + CLR_Debug::Printf(" INFINITE"); } } void CLR_RT_GarbageCollector::DumpThreads() { NATIVE_PROFILE_CLR_CORE(); - NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsReady) + NANOCLR_FOREACH_NODE(CLR_RT_Thread, th, g_CLR_RT_ExecutionEngine.m_threadsReady) { th->DumpStack(); } NANOCLR_FOREACH_NODE_END(); - NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsWaiting) + NANOCLR_FOREACH_NODE(CLR_RT_Thread, th, g_CLR_RT_ExecutionEngine.m_threadsWaiting) { th->DumpStack(); } NANOCLR_FOREACH_NODE_END(); - CLR_Debug::Printf( "\r\n" ); + CLR_Debug::Printf("\r\n"); } #endif @@ -90,40 +93,40 @@ void CLR_RT_GarbageCollector::DumpThreads() #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_3_Compaction -void CLR_RT_GarbageCollector::ValidateCluster( CLR_RT_HeapCluster* hc ) +void CLR_RT_GarbageCollector::ValidateCluster(CLR_RT_HeapCluster *hc) { NATIVE_PROFILE_CLR_CORE(); - CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; - CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + CLR_RT_HeapBlock_Node *ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node *end = hc->m_payloadEnd; - while(ptr < end) + while (ptr < end) { - hc->ValidateBlock( ptr ); + hc->ValidateBlock(ptr); ptr += ptr->DataSize(); } } -void CLR_RT_GarbageCollector::ValidateHeap( CLR_RT_DblLinkedList& lst ) +void CLR_RT_GarbageCollector::ValidateHeap(CLR_RT_DblLinkedList &lst) { NATIVE_PROFILE_CLR_CORE(); - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, lst) { - ValidateCluster( hc ); + ValidateCluster(hc); } NANOCLR_FOREACH_NODE_END(); } -void CLR_RT_GarbageCollector::ValidateBlockNotInFreeList( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ) +void CLR_RT_GarbageCollector::ValidateBlockNotInFreeList(CLR_RT_DblLinkedList &lst, CLR_RT_HeapBlock_Node *dst) { NATIVE_PROFILE_CLR_CORE(); - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, lst) { - NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,hc->m_freeList) + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node, ptr, hc->m_freeList) { - CLR_RT_HeapBlock_Node* ptrEnd = ptr + ptr->DataSize(); + CLR_RT_HeapBlock_Node *ptrEnd = ptr + ptr->DataSize(); - if(ptr <= dst && dst < ptrEnd) + if (ptr <= dst && dst < ptrEnd) { #if _WIN64 CLR_Debug::Printf("Pointer into free list!! %I64X %I64X %I64X\r\n", dst, ptr, ptrEnd); @@ -139,22 +142,24 @@ void CLR_RT_GarbageCollector::ValidateBlockNotInFreeList( CLR_RT_DblLinkedList& NANOCLR_FOREACH_NODE_END(); } -bool CLR_RT_GarbageCollector::IsBlockInFreeList( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst, bool fExact ) +bool CLR_RT_GarbageCollector::IsBlockInFreeList(CLR_RT_DblLinkedList &lst, CLR_RT_HeapBlock_Node *dst, bool fExact) { NATIVE_PROFILE_CLR_CORE(); - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, lst) { - NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,hc->m_freeList) + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node, ptr, hc->m_freeList) { - if(fExact) + if (fExact) { - if(ptr == dst) return true; + if (ptr == dst) + return true; } else { - CLR_RT_HeapBlock_Node* ptrEnd = ptr + ptr->DataSize(); + CLR_RT_HeapBlock_Node *ptrEnd = ptr + ptr->DataSize(); - if(ptr <= dst && dst < ptrEnd) return true; + if (ptr <= dst && dst < ptrEnd) + return true; } } NANOCLR_FOREACH_NODE_END(); @@ -164,12 +169,13 @@ bool CLR_RT_GarbageCollector::IsBlockInFreeList( CLR_RT_DblLinkedList& lst, CLR_ return false; } -bool CLR_RT_GarbageCollector::IsBlockInHeap( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ) +bool CLR_RT_GarbageCollector::IsBlockInHeap(CLR_RT_DblLinkedList &lst, CLR_RT_HeapBlock_Node *dst) { NATIVE_PROFILE_CLR_CORE(); - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, lst) { - if(hc->m_payloadStart <= dst && dst < hc->m_payloadEnd) return true; + if (hc->m_payloadStart <= dst && dst < hc->m_payloadEnd) + return true; } NANOCLR_FOREACH_NODE_END(); @@ -183,31 +189,31 @@ bool CLR_RT_GarbageCollector::IsBlockInHeap( CLR_RT_DblLinkedList& lst, CLR_RT_H #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_4_CompactionPlus CLR_RT_GarbageCollector::Rel_List CLR_RT_GarbageCollector::s_lstRecords; -CLR_RT_GarbageCollector::Rel_Map CLR_RT_GarbageCollector::s_mapOldToRecord; -CLR_RT_GarbageCollector::Rel_Map CLR_RT_GarbageCollector::s_mapNewToRecord; +CLR_RT_GarbageCollector::Rel_Map CLR_RT_GarbageCollector::s_mapOldToRecord; +CLR_RT_GarbageCollector::Rel_Map CLR_RT_GarbageCollector::s_mapNewToRecord; //--// -bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker( void** ref ) +bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker(void **ref) { NATIVE_PROFILE_CLR_CORE(); - CLR_UINT32* dst = (CLR_UINT32*)*ref; + CLR_UINT32 *dst = (CLR_UINT32 *)*ref; - if(dst) + if (dst) { - RelocationRecord* ptr = new RelocationRecord(); + RelocationRecord *ptr = new RelocationRecord(); - s_lstRecords.push_back( ptr ); + s_lstRecords.push_back(ptr); - ptr->oldRef = ref; - ptr->oldPtr = dst; + ptr->oldRef = ref; + ptr->oldPtr = dst; - ptr->newRef = NULL; - ptr->newPtr = NULL; + ptr->newRef = NULL; + ptr->newPtr = NULL; - ptr->data = *dst; + ptr->data = *dst; - if(s_mapOldToRecord.find( ref ) != s_mapOldToRecord.end()) + if (s_mapOldToRecord.find(ref) != s_mapOldToRecord.end()) { #if _WIN64 CLR_Debug::Printf("Duplicate base OLD: %I64X\r\n", ref); @@ -218,9 +224,9 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker( void** ref ) NANOCLR_DEBUG_STOP(); } - s_mapOldToRecord[ ref ] = ptr; + s_mapOldToRecord[ref] = ptr; - if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst, false )) + if (IsBlockInFreeList(g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node *)dst, false)) { #if _WIN64 CLR_Debug::Printf("Some data points into a free list: %I64X\r\n", dst); @@ -240,23 +246,23 @@ void CLR_RT_GarbageCollector::TestPointers_PopulateOld() NATIVE_PROFILE_CLR_CORE(); Rel_List_Iter itLst; - for(itLst = s_lstRecords.begin(); itLst != s_lstRecords.end(); itLst++) + for (itLst = s_lstRecords.begin(); itLst != s_lstRecords.end(); itLst++) { - RelocationRecord* ptr = *itLst; + RelocationRecord *ptr = *itLst; delete ptr; } - s_lstRecords .clear(); + s_lstRecords.clear(); s_mapOldToRecord.clear(); s_mapNewToRecord.clear(); //--// - Heap_Relocate_Pass( TestPointers_PopulateOld_Worker ); + Heap_Relocate_Pass(TestPointers_PopulateOld_Worker); } -void CLR_RT_GarbageCollector::Relocation_UpdatePointer(void** ref) +void CLR_RT_GarbageCollector::Relocation_UpdatePointer(void **ref) { (void)ref; @@ -270,13 +276,15 @@ void CLR_RT_GarbageCollector::TestPointers_Remap() NATIVE_PROFILE_CLR_CORE(); Rel_Map_Iter it; - for(it = s_mapOldToRecord.begin(); it != s_mapOldToRecord.end(); it++) + for (it = s_mapOldToRecord.begin(); it != s_mapOldToRecord.end(); it++) { - RelocationRecord* ptr = it->second; - void** ref = it->first ; CLR_RT_GarbageCollector::Relocation_UpdatePointer( (void**)&ref ); - CLR_UINT32* dst = ptr->oldPtr; CLR_RT_GarbageCollector::Relocation_UpdatePointer( (void**)&dst ); + RelocationRecord *ptr = it->second; + void **ref = it->first; + CLR_RT_GarbageCollector::Relocation_UpdatePointer((void **)&ref); + CLR_UINT32 *dst = ptr->oldPtr; + CLR_RT_GarbageCollector::Relocation_UpdatePointer((void **)&dst); - if(s_mapNewToRecord.find( ref ) != s_mapNewToRecord.end()) + if (s_mapNewToRecord.find(ref) != s_mapNewToRecord.end()) { #if _WIN64 CLR_Debug::Printf("Duplicate base NEW: %I64X\r\n", ref); @@ -286,7 +294,7 @@ void CLR_RT_GarbageCollector::TestPointers_Remap() NANOCLR_DEBUG_STOP(); } - s_mapNewToRecord[ ref ] = ptr; + s_mapNewToRecord[ref] = ptr; ptr->newRef = ref; ptr->newPtr = dst; @@ -295,20 +303,20 @@ void CLR_RT_GarbageCollector::TestPointers_Remap() //--// -bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker( void** ref ) +bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker(void **ref) { NATIVE_PROFILE_CLR_CORE(); - CLR_UINT32* dst = (CLR_UINT32*)*ref; + CLR_UINT32 *dst = (CLR_UINT32 *)*ref; - if(dst) + if (dst) { - Rel_Map_Iter it = s_mapNewToRecord.find( ref ); + Rel_Map_Iter it = s_mapNewToRecord.find(ref); - if(it != s_mapNewToRecord.end()) + if (it != s_mapNewToRecord.end()) { - RelocationRecord* ptr = it->second; + RelocationRecord *ptr = it->second; - if(ptr->newPtr != dst) + if (ptr->newPtr != dst) { #if _WIN64 CLR_Debug::Printf("Bad pointer: %I64X %I64X\r\n", ptr->newPtr, dst); @@ -317,7 +325,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker( void** ref ) #endif NANOCLR_DEBUG_STOP(); } - else if(ptr->data != *dst) + else if (ptr->data != *dst) { #if _WIN64 CLR_Debug::Printf("Bad data: %I64X %I64X\r\n", ptr->data, *dst); @@ -328,7 +336,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker( void** ref ) NANOCLR_DEBUG_STOP(); } - if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst, false )) + if (IsBlockInFreeList(g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node *)dst, false)) { #if _WIN64 CLR_Debug::Printf("Some data points into a free list: %I64X\r\n", dst); @@ -359,7 +367,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker( void** ref ) void CLR_RT_GarbageCollector::TestPointers_PopulateNew() { NATIVE_PROFILE_CLR_CORE(); - Heap_Relocate_Pass( TestPointers_PopulateNew_Worker ); + Heap_Relocate_Pass(TestPointers_PopulateNew_Worker); } #endif From f5df49a21752e66992438f58820e051c6d02e32f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 16:17:34 +0100 Subject: [PATCH 465/572] Rework declarations for several functions and locals - To fix compiler warnings. --- .../CorLib/corlib_native_System_Convert.cpp | 12 ++++---- .../CorLib/corlib_native_System_Number.cpp | 29 ++++++++++--------- src/CLR/Core/CLR_RT_Memory.cpp | 2 +- src/CLR/Core/CLR_RT_RuntimeMemory.cpp | 10 +++---- src/CLR/Debugger/Debugger.cpp | 8 ++--- src/CLR/Diagnostics/Info.cpp | 2 +- src/CLR/Include/nanoCLR_Runtime.h | 10 +++---- 7 files changed, 38 insertions(+), 35 deletions(-) diff --git a/src/CLR/CorLib/corlib_native_System_Convert.cpp b/src/CLR/CorLib/corlib_native_System_Convert.cpp index 9733ecc959..7c35db46c5 100644 --- a/src/CLR/CorLib/corlib_native_System_Convert.cpp +++ b/src/CLR/CorLib/corlib_native_System_Convert.cpp @@ -604,7 +604,7 @@ HRESULT Library_corlib_native_System_Convert::ToBase64String___STATIC__STRING__S char *outArray = NULL; char *outArrayWitLineBreak = NULL; uint8_t *inArrayPointer = NULL; - uint8_t lineBreakCount; + size_t lineBreakCount; uint16_t offsetIndex = 0; uint8_t count = 0; uint16_t result; @@ -727,18 +727,18 @@ HRESULT Library_corlib_native_System_Convert::FromBase64String___STATIC__SZARRAY #if (SUPPORT_ANY_BASE_CONVERSION == TRUE) CLR_RT_HeapBlock_String *inString = NULL; - size_t outputLength; + uint32_t outputLength; char *outArray = NULL; CLR_UINT8 *returnArray; uint16_t result; - size_t length; + uint32_t length; inString = stack.Arg0().DereferenceString(); FAULT_ON_NULL(inString); FAULT_ON_NULL_ARG(inString->StringText()); - length = (size_t)hal_strlen_s(inString->StringText()); + length = hal_strlen_s(inString->StringText()); // estimate output length outputLength = length / 4 * 3; @@ -755,8 +755,8 @@ HRESULT Library_corlib_native_System_Convert::FromBase64String___STATIC__SZARRAY // need to tweak the parameter with the output length because it includes room for the terminator result = mbedtls_base64_decode( (unsigned char *)outArray, - (outputLength + 1), - &outputLength, + (size_t)(outputLength + 1), + (size_t *)&outputLength, (const unsigned char *)inString->StringText(), length); diff --git a/src/CLR/CorLib/corlib_native_System_Number.cpp b/src/CLR/CorLib/corlib_native_System_Number.cpp index 369115269f..4d9039e87e 100644 --- a/src/CLR/CorLib/corlib_native_System_Number.cpp +++ b/src/CLR/CorLib/corlib_native_System_Number.cpp @@ -88,35 +88,36 @@ int Library_corlib_native_System_Number::DoPrintfOnDataType(char *buffer, char * switch (dataType) { case DATATYPE_I1: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().s1); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().s1); break; case DATATYPE_U1: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().u1); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().u1); break; case DATATYPE_I2: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().s2); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().s2); break; case DATATYPE_U2: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().u2); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().u2); break; case DATATYPE_I4: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().s4); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().s4); break; case DATATYPE_U4: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().u4); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().u4); break; case DATATYPE_I8: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, (CLR_INT64_TEMP_CAST)value->NumericByRef().s8); + ret = (int)(int) + snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, (CLR_INT64_TEMP_CAST)value->NumericByRef().s8); break; case DATATYPE_U8: - ret = + ret = (int) snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, (CLR_UINT64_TEMP_CAST)value->NumericByRef().u8); break; case DATATYPE_R4: - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().r4); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, value->NumericByRef().r4); break; case DATATYPE_R8: - ret = + ret = (int) snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, (CLR_DOUBLE_TEMP_CAST)value->NumericByRef().r8); break; default: @@ -125,7 +126,9 @@ int Library_corlib_native_System_Number::DoPrintfOnDataType(char *buffer, char * // assure string valid even in cases when nothing was written if (ret >= 0) + { buffer[ret] = 0; + } return ret; } @@ -550,11 +553,11 @@ int Library_corlib_native_System_Number::Format_G( if (formatChar == 'g') { - ret += snprintf(&buffer[ret], FORMAT_RESULT_BUFFER_SIZE - ret, "e%+.2d", exponent); + ret += (int)snprintf(&buffer[ret], FORMAT_RESULT_BUFFER_SIZE - ret, "e%+.2d", exponent); } else { - ret += snprintf(&buffer[ret], FORMAT_RESULT_BUFFER_SIZE - ret, "E%+.2d", exponent); + ret += (int)snprintf(&buffer[ret], FORMAT_RESULT_BUFFER_SIZE - ret, "E%+.2d", exponent); } } } @@ -845,7 +848,7 @@ int Library_corlib_native_System_Number::Format_E(char *buffer, CLR_RT_HeapBlock snprintf(formatStr, FORMAT_FMTSTR_BUFFER_SIZE, "%%.%d%c", precision, formatChar); - ret = snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, copyValue); + ret = (int)snprintf(buffer, FORMAT_RESULT_BUFFER_SIZE, formatStr, copyValue); if (ret > 0) { diff --git a/src/CLR/Core/CLR_RT_Memory.cpp b/src/CLR/Core/CLR_RT_Memory.cpp index 2da9ee3471..3412e74b00 100644 --- a/src/CLR/Core/CLR_RT_Memory.cpp +++ b/src/CLR/Core/CLR_RT_Memory.cpp @@ -13,7 +13,7 @@ static CLR_UINT32 s_TotalAllocated; CLR_RT_MemoryRange s_CLR_RT_Heap = {0, 0}; -static int s_PreHeapInitIndex = 0; +static size_t s_PreHeapInitIndex = 0; //////////////////////////////////////////////////////////// diff --git a/src/CLR/Core/CLR_RT_RuntimeMemory.cpp b/src/CLR/Core/CLR_RT_RuntimeMemory.cpp index bc7937bef6..5d9f0ce59b 100644 --- a/src/CLR/Core/CLR_RT_RuntimeMemory.cpp +++ b/src/CLR/Core/CLR_RT_RuntimeMemory.cpp @@ -108,20 +108,20 @@ //--// -size_t LinkArraySize() +uint32_t LinkArraySize() { return (PLATFORM_DEPENDENT_ENTRY_SIZE + PLATFORM_DEPENDENT_HASH_TABLE_SIZE); } -size_t LinkMRUArraySize() +uint32_t LinkMRUArraySize() { return (PLATFORM_DEPENDENT_ENTRY_SIZE + 1); } -size_t PayloadArraySize() +uint32_t PayloadArraySize() { return PLATFORM_DEPENDENT_ENTRY_SIZE; } #ifndef NANOCLR_NO_IL_INLINE -size_t InlineBufferCount() +uint32_t InlineBufferCount() { return PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE; } @@ -141,7 +141,7 @@ unsigned int //--// -size_t InterruptRecords() +uint32_t InterruptRecords() { return PLATFORM_DEPENDENT_INTERRUPT_RECORDS; } diff --git a/src/CLR/Debugger/Debugger.cpp b/src/CLR/Debugger/Debugger.cpp index adfed6eb3f..d22bd95987 100644 --- a/src/CLR/Debugger/Debugger.cpp +++ b/src/CLR/Debugger/Debugger.cpp @@ -587,7 +587,7 @@ bool CLR_DBG_Debugger::Monitor_TargetInfo(WP_Message *msg) { Monitor_TargetInfo_Reply cmdReply; - bool fOK = nanoBooter_GetTargetInfo(&cmdReply.m_TargetInfo) == true; + bool fOK = (bool)nanoBooter_GetTargetInfo(&cmdReply.m_TargetInfo) == true; WP_ReplyToCommand(msg, fOK, false, &cmdReply, sizeof(Monitor_TargetInfo_Reply)); @@ -1779,7 +1779,7 @@ static bool FillValues( if (pTD != NULL) { - dst->m_td = *pTD; + dst->m_td.m_data = pTD->m_data; } else if (SUCCEEDED(desc.InitializeFromObject(*ptr))) { @@ -3543,7 +3543,7 @@ bool CLR_DBG_Debugger::Debugging_Resolve_Field(WP_Message *msg) CLR_RT_TypeDef_Instance instClass; instClass.InitializeFromField(inst); - cmdReply->m_td = instClass; + cmdReply->m_td.m_data = instClass.m_data; cmdReply->m_index = inst.CrossReference().m_offset; WP_ReplyToCommand(msg, true, false, cmdReply, sizeof(CLR_DBG_Commands::Debugging_Resolve_Field::Reply)); @@ -3589,7 +3589,7 @@ bool CLR_DBG_Debugger::Debugging_Resolve_Method(WP_Message *msg) char *szBuffer = cmdReply->m_method; size_t iBuffer = MAXSTRLEN(cmdReply->m_method); - cmdReply->m_td = instOwner; + cmdReply->m_td.m_data = instOwner.m_data; CLR_SafeSprintf(szBuffer, iBuffer, "%s", inst.m_assm->GetString(inst.m_target->name)); diff --git a/src/CLR/Diagnostics/Info.cpp b/src/CLR/Diagnostics/Info.cpp index 9ee3ee42b8..4b54ef3721 100644 --- a/src/CLR/Diagnostics/Info.cpp +++ b/src/CLR/Diagnostics/Info.cpp @@ -27,7 +27,7 @@ void CLR_Debug::SaveMessage(std::string str) NATIVE_PROFILE_CLR_DIAGNOSTICS(); // clear LR & CR - int pos; + size_t pos; if ((pos = str.find('\n')) != std::string::npos) { str.erase(pos); diff --git a/src/CLR/Include/nanoCLR_Runtime.h b/src/CLR/Include/nanoCLR_Runtime.h index 1c2511161b..cc6abaf7f6 100644 --- a/src/CLR/Include/nanoCLR_Runtime.h +++ b/src/CLR/Include/nanoCLR_Runtime.h @@ -3161,12 +3161,12 @@ struct CLR_RT_Thread : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP - N //////////////////////////////////////////////////////////////////////////////// -extern size_t LinkArraySize(); -extern size_t LinkMRUArraySize(); -extern size_t PayloadArraySize(); -extern size_t InterruptRecords(); +extern uint32_t LinkArraySize(); +extern uint32_t LinkMRUArraySize(); +extern uint32_t PayloadArraySize(); +extern uint32_t InterruptRecords(); #ifndef NANOCLR_NO_IL_INLINE -extern size_t InlineBufferCount(); +extern uint32_t InlineBufferCount(); #endif extern CLR_UINT32 g_scratchVirtualMethodTableLink[]; From 9d04e775d6b95cece3f36f39a313cffb380df8d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 16:35:40 +0100 Subject: [PATCH 466/572] Improve progress messages of GC and heap compaction --- src/CLR/Core/Execution.cpp | 6 +- src/CLR/Core/GarbageCollector.cpp | 10 +- src/CLR/Core/GarbageCollector_Compaction.cpp | 277 ++++++++++--------- src/CLR/Core/TypeSystem.cpp | 13 +- 4 files changed, 154 insertions(+), 152 deletions(-) diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp index c85741650e..4ea1be346a 100644 --- a/src/CLR/Core/Execution.cpp +++ b/src/CLR/Core/Execution.cpp @@ -1626,7 +1626,7 @@ CLR_RT_HeapBlock *CLR_RT_ExecutionEngine::ExtractHeapBlocks( { if (phase != 0) { - CLR_Debug::Printf("ExtractHeapBlocks succeeded at phase %d\r\n", phase); + CLR_Debug::Printf("\r\n\r\nExtractHeapBlocks succeeded at phase %d\r\n", phase); } } #endif @@ -1652,7 +1652,7 @@ CLR_RT_HeapBlock *CLR_RT_ExecutionEngine::ExtractHeapBlocks( if (s_CLR_RT_fTrace_Memory >= c_CLR_RT_Trace_Info) { CLR_Debug::Printf( - " Memory: ExtractHeapBlocks: %d bytes needed.\r\n", + "\r\n\r\n Memory: ExtractHeapBlocks: %d bytes needed.\r\n", length * sizeof(CLR_RT_HeapBlock)); } #endif @@ -1664,7 +1664,7 @@ CLR_RT_HeapBlock *CLR_RT_ExecutionEngine::ExtractHeapBlocks( default: // Total failure... #if !defined(BUILD_RTM) CLR_Debug::Printf( - "Failed allocation for %d blocks, %d bytes\r\n\r\n", + "\r\n\r\nFailed allocation for %d blocks, %d bytes\r\n\r\n", length, length * sizeof(CLR_RT_HeapBlock)); #endif diff --git a/src/CLR/Core/GarbageCollector.cpp b/src/CLR/Core/GarbageCollector.cpp index 6a3b46c428..3448648e6b 100644 --- a/src/CLR/Core/GarbageCollector.cpp +++ b/src/CLR/Core/GarbageCollector.cpp @@ -144,7 +144,7 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteGarbageCollection() #if defined(NANOCLR_GC_VERBOSE) if (s_CLR_RT_fTrace_GC >= c_CLR_RT_Trace_Info) { - CLR_Debug::Printf(" Memory: Start %s\r\n", HAL_Time_CurrentDateTimeToString()); + CLR_Debug::Printf("\r\n\r\n Memory: Start %s\r\n", HAL_Time_CurrentDateTimeToString()); } #endif @@ -176,7 +176,7 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteGarbageCollection() TIME_CONVERSION__TICKUNITS; CLR_Debug::Printf( - "GC: %dmsec %d bytes used, %d bytes available\r\n", + "\r\nGC: %dmsec %d bytes used, %d bytes available\r\n\r\n", milliSec, m_totalBytes - m_freeBytes, m_freeBytes); @@ -232,7 +232,7 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteGarbageCollection() if (countBlocks[dt]) { CLR_Debug::Printf( - "Type %02X (%-20s): %6d bytes\r\n", + "Type %02X (%-20s): %8d bytes\r\n", dt, c_CLR_RT_DataTypeLookup[dt].m_name, countBlocks[dt] * sizeof(CLR_RT_HeapBlock)); @@ -244,7 +244,7 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteGarbageCollection() if (countArryBlocks[dt2]) { CLR_Debug::Printf( - " Type %02X (%-17s): %6d bytes\r\n", + " Type %02X (%-17s): %8d bytes\r\n", dt2, c_CLR_RT_DataTypeLookup[dt2].m_name, countArryBlocks[dt2] * sizeof(CLR_RT_HeapBlock)); @@ -265,7 +265,7 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteGarbageCollection() #if defined(NANOCLR_GC_VERBOSE) if (s_CLR_RT_fTrace_GC >= c_CLR_RT_Trace_Info) { - CLR_Debug::Printf(" Memory: End %s\r\n", HAL_Time_CurrentDateTimeToString()); + CLR_Debug::Printf("\r\n\r\n Memory: End %s\r\n", HAL_Time_CurrentDateTimeToString()); } #endif diff --git a/src/CLR/Core/GarbageCollector_Compaction.cpp b/src/CLR/Core/GarbageCollector_Compaction.cpp index a18bb3c76c..22fc790889 100644 --- a/src/CLR/Core/GarbageCollector_Compaction.cpp +++ b/src/CLR/Core/GarbageCollector_Compaction.cpp @@ -13,11 +13,11 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteCompaction() #if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) g_CLR_PRF_Profiler.RecordHeapCompactionBegin(); #endif - + #if defined(NANOCLR_TRACE_MEMORY_STATS) - if(s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) + if (s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) { - CLR_Debug::Printf( "GC: performing heap compaction\r\n" ); + CLR_Debug::Printf("\r\nGC: performing heap compaction\r\n"); } #endif @@ -37,9 +37,9 @@ CLR_UINT32 CLR_RT_GarbageCollector::ExecuteCompaction() #endif #if defined(NANOCLR_TRACE_MEMORY_STATS) - if(s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) + if (s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) { - CLR_Debug::Printf( "GC: heap compaction completed\r\n" ); + CLR_Debug::Printf("\r\n\r\nGC: heap compaction completed\r\n"); } #endif @@ -56,151 +56,159 @@ void CLR_RT_GarbageCollector::Heap_Compact() //--// - RelocationRegion relocHelper[ c_minimumSpaceForCompact ]; - const size_t relocMax = ARRAYSIZE(relocHelper); + RelocationRegion relocHelper[c_minimumSpaceForCompact]; + const size_t relocMax = ARRAYSIZE(relocHelper); - Heap_Relocate_Prepare( relocHelper, relocMax ); + Heap_Relocate_Prepare(relocHelper, relocMax); - RelocationRegion* relocBlocks = relocHelper; - RelocationRegion* relocCurrent = relocBlocks; + RelocationRegion *relocBlocks = relocHelper; + RelocationRegion *relocCurrent = relocBlocks; //--// TestPointers_PopulateOld(); - - CLR_RT_HeapCluster* freeRegion_hc = NULL;; - CLR_RT_HeapBlock_Node* freeRegion = NULL; + CLR_RT_HeapCluster *freeRegion_hc = NULL; + ; + CLR_RT_HeapBlock_Node *freeRegion = NULL; - CLR_RT_HeapCluster* currentSource_hc = (CLR_RT_HeapCluster*)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); - while(currentSource_hc->Next()) + CLR_RT_HeapCluster *currentSource_hc = (CLR_RT_HeapCluster *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); + while (currentSource_hc->Next()) { - CLR_RT_HeapBlock_Node* currentSource = currentSource_hc->m_payloadStart; - CLR_RT_HeapBlock_Node* currentSource_end = currentSource_hc->m_payloadEnd; + CLR_RT_HeapBlock_Node *currentSource = currentSource_hc->m_payloadStart; + CLR_RT_HeapBlock_Node *currentSource_end = currentSource_hc->m_payloadEnd; - if(!freeRegion) + if (!freeRegion) { // // Move to the next first free region. // - freeRegion_hc = (CLR_RT_HeapCluster*)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); - while(true) + freeRegion_hc = (CLR_RT_HeapCluster *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); + while (true) { - CLR_RT_HeapCluster* freeRegion_hcNext = (CLR_RT_HeapCluster*)freeRegion_hc->Next(); if(!freeRegion_hcNext) break; + CLR_RT_HeapCluster *freeRegion_hcNext = (CLR_RT_HeapCluster *)freeRegion_hc->Next(); + if (!freeRegion_hcNext) + break; - freeRegion = freeRegion_hc->m_freeList.FirstNode(); if(freeRegion->Next()) break; + freeRegion = freeRegion_hc->m_freeList.FirstNode(); + if (freeRegion->Next()) + break; - freeRegion = NULL; + freeRegion = NULL; freeRegion_hc = freeRegion_hcNext; } - if(!freeRegion) break; + if (!freeRegion) + break; } - while(true) + while (true) { // // We can only move backward. // - if(currentSource < freeRegion) + if (currentSource < freeRegion) { - currentSource_hc = freeRegion_hc; - currentSource = freeRegion; + currentSource_hc = freeRegion_hc; + currentSource = freeRegion; currentSource_end = freeRegion_hc->m_payloadEnd; } - while(currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable )) + while (currentSource < currentSource_end && currentSource->IsFlagSet(CLR_RT_HeapBlock::HB_Unmovable)) { currentSource += currentSource->DataSize(); } - if(currentSource == currentSource_end) break; + if (currentSource == currentSource_end) + break; - ////////////////////////////////////////////////////// - // - // At this point, we have at least ONE movable block. - // - ////////////////////////////////////////////////////// + ////////////////////////////////////////////////////// + // + // At this point, we have at least ONE movable block. + // + ////////////////////////////////////////////////////// #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_4_CompactionPlus - if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, freeRegion, true ) == false) + if (IsBlockInFreeList(g_CLR_RT_ExecutionEngine.m_heap, freeRegion, true) == false) { - CLR_Debug::Printf( "'freeRegion' is not in a free list!! %08x\r\n", freeRegion ); + CLR_Debug::Printf("'freeRegion' is not in a free list!! %08x\r\n", freeRegion); NANOCLR_DEBUG_STOP(); } - if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, currentSource, false )) + if (IsBlockInFreeList(g_CLR_RT_ExecutionEngine.m_heap, currentSource, false)) { - CLR_Debug::Printf( "'currentSource' is in a free list!! %08x\r\n", currentSource ); + CLR_Debug::Printf("'currentSource' is in a free list!! %08x\r\n", currentSource); NANOCLR_DEBUG_STOP(); } #endif - if(m_relocCount >= relocMax) + if (m_relocCount >= relocMax) { - ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + ValidateHeap(g_CLR_RT_ExecutionEngine.m_heap); Heap_Relocate(); - ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + ValidateHeap(g_CLR_RT_ExecutionEngine.m_heap); - relocBlocks = m_relocBlocks; + relocBlocks = m_relocBlocks; relocCurrent = relocBlocks; TestPointers_PopulateOld(); } { - CLR_UINT32 move = 0; + CLR_UINT32 move = 0; CLR_UINT32 freeRegion_Size = freeRegion->DataSize(); - bool fSlide; + bool fSlide; - relocCurrent->m_destination = (CLR_UINT8*)freeRegion; - relocCurrent->m_start = (CLR_UINT8*)currentSource; - relocCurrent->m_offset = (CLR_UINT32)(relocCurrent->m_destination - relocCurrent->m_start); + relocCurrent->m_destination = (CLR_UINT8 *)freeRegion; + relocCurrent->m_start = (CLR_UINT8 *)currentSource; + relocCurrent->m_offset = (CLR_UINT32)(relocCurrent->m_destination - relocCurrent->m_start); - // // Are the free block and the last moved block adjacent? // - if(currentSource == freeRegion + freeRegion_Size) + if (currentSource == freeRegion + freeRegion_Size) { - while(currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable ) == false) + while (currentSource < currentSource_end && + currentSource->IsFlagSet(CLR_RT_HeapBlock::HB_Unmovable) == false) { CLR_UINT32 len = currentSource->DataSize(); currentSource += len; - move += len; + move += len; } fSlide = true; } else { - while(freeRegion_Size && currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable ) == false) + while (freeRegion_Size && currentSource < currentSource_end && + currentSource->IsFlagSet(CLR_RT_HeapBlock::HB_Unmovable) == false) { CLR_UINT32 len = currentSource->DataSize(); - if(freeRegion_Size < len) + if (freeRegion_Size < len) { break; } freeRegion_Size -= len; - currentSource += len; - move += len; + currentSource += len; + move += len; } fSlide = false; } - if(move) + if (move) { // // Skip forward to the next movable block. // - while(currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable )) + while (currentSource < currentSource_end && + currentSource->IsFlagSet(CLR_RT_HeapBlock::HB_Unmovable)) { currentSource += currentSource->DataSize(); } @@ -215,37 +223,35 @@ void CLR_RT_GarbageCollector::Heap_Compact() // Remove the old free block, copy the data, recreate the new free block. // Merge with the following one if they are adjacent now. // - CLR_RT_HeapBlock_Node* freeRegionNext = freeRegion->Next(); + CLR_RT_HeapBlock_Node *freeRegionNext = freeRegion->Next(); freeRegion->Unlink(); - - memmove( relocCurrent->m_destination, relocCurrent->m_start, moveBytes ); - if(freeRegion_Size) - { + memmove(relocCurrent->m_destination, relocCurrent->m_start, moveBytes); - freeRegion = freeRegion_hc->InsertInOrder( freeRegion + move, freeRegion_Size ); + if (freeRegion_Size) + { + freeRegion = freeRegion_hc->InsertInOrder(freeRegion + move, freeRegion_Size); } else { freeRegion = freeRegionNext; - } - if(fSlide == false) + if (fSlide == false) { - CLR_RT_HeapBlock_Node* dst = currentSource_hc->InsertInOrder( (CLR_RT_HeapBlock_Node*)relocCurrent->m_start, move ); + CLR_RT_HeapBlock_Node *dst = + currentSource_hc->InsertInOrder((CLR_RT_HeapBlock_Node *)relocCurrent->m_start, move); - if(dst < freeRegion && freeRegion < (dst + dst->DataSize())) + if (dst < freeRegion && freeRegion < (dst + dst->DataSize())) { freeRegion = dst; } - } - CLR_RT_GarbageCollector::ValidateCluster( currentSource_hc ); - CLR_RT_GarbageCollector::ValidateCluster( freeRegion_hc ); + CLR_RT_GarbageCollector::ValidateCluster(currentSource_hc); + CLR_RT_GarbageCollector::ValidateCluster(freeRegion_hc); relocCurrent++; m_relocCount++; @@ -253,31 +259,30 @@ void CLR_RT_GarbageCollector::Heap_Compact() else { freeRegion = freeRegion->Next(); - } - if(freeRegion->Next() == NULL) + if (freeRegion->Next() == NULL) { - freeRegion = NULL; - freeRegion_hc = (CLR_RT_HeapCluster*)freeRegion_hc->Next(); + freeRegion = NULL; + freeRegion_hc = (CLR_RT_HeapCluster *)freeRegion_hc->Next(); - while(true) + while (true) { - CLR_RT_HeapCluster* freeRegion_hcNext = (CLR_RT_HeapCluster*)freeRegion_hc->Next(); + CLR_RT_HeapCluster *freeRegion_hcNext = (CLR_RT_HeapCluster *)freeRegion_hc->Next(); if (!freeRegion_hcNext) { break; } freeRegion = freeRegion_hc->m_freeList.FirstNode(); - + if (freeRegion != NULL && freeRegion->Next()) { break; } - freeRegion = NULL; + freeRegion = NULL; freeRegion_hc = freeRegion_hcNext; } @@ -289,41 +294,41 @@ void CLR_RT_GarbageCollector::Heap_Compact() } } - currentSource_hc = (CLR_RT_HeapCluster*)currentSource_hc->Next(); + currentSource_hc = (CLR_RT_HeapCluster *)currentSource_hc->Next(); } - if(m_relocCount) + if (m_relocCount) { - ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + ValidateHeap(g_CLR_RT_ExecutionEngine.m_heap); Heap_Relocate(); - ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + ValidateHeap(g_CLR_RT_ExecutionEngine.m_heap); } } -void CLR_RT_GarbageCollector::Heap_Relocate_Prepare( RelocationRegion* blocks, size_t total ) +void CLR_RT_GarbageCollector::Heap_Relocate_Prepare(RelocationRegion *blocks, size_t total) { NATIVE_PROFILE_CLR_CORE(); m_relocBlocks = blocks; - m_relocTotal = total; - m_relocCount = 0; + m_relocTotal = total; + m_relocCount = 0; } -void CLR_RT_GarbageCollector::Heap_Relocate_AddBlock( CLR_UINT8* dst, CLR_UINT8* src, CLR_UINT32 length ) +void CLR_RT_GarbageCollector::Heap_Relocate_AddBlock(CLR_UINT8 *dst, CLR_UINT8 *src, CLR_UINT32 length) { NATIVE_PROFILE_CLR_CORE(); - RelocationRegion* reloc = m_relocBlocks; - size_t count = m_relocCount; + RelocationRegion *reloc = m_relocBlocks; + size_t count = m_relocCount; - while(count) + while (count) { - if(reloc->m_start > src) + if (reloc->m_start > src) { // // Insert region, so they are sorted by start address. // - memmove( &reloc[ 1 ], &reloc[ 0 ], count * sizeof(*reloc) ); + memmove(&reloc[1], &reloc[0], count * sizeof(*reloc)); break; } @@ -331,12 +336,12 @@ void CLR_RT_GarbageCollector::Heap_Relocate_AddBlock( CLR_UINT8* dst, CLR_UINT8* count--; } - reloc->m_start = src; - reloc->m_end = &src[ length ]; - reloc->m_destination = dst; - reloc->m_offset = (CLR_UINT32)(dst - src); + reloc->m_start = src; + reloc->m_end = &src[length]; + reloc->m_destination = dst; + reloc->m_offset = (CLR_UINT32)(dst - src); - if(++m_relocCount == m_relocTotal) + if (++m_relocCount == m_relocTotal) { Heap_Relocate(); } @@ -345,17 +350,19 @@ void CLR_RT_GarbageCollector::Heap_Relocate_AddBlock( CLR_UINT8* dst, CLR_UINT8* void CLR_RT_GarbageCollector::Heap_Relocate() { NATIVE_PROFILE_CLR_CORE(); - if(m_relocCount) + if (m_relocCount) { - RelocationRegion* relocBlocks = m_relocBlocks; + RelocationRegion *relocBlocks = m_relocBlocks; - CLR_UINT8* relocMinimum = relocBlocks->m_start; - CLR_UINT8* relocMaximum = relocBlocks->m_end; + CLR_UINT8 *relocMinimum = relocBlocks->m_start; + CLR_UINT8 *relocMaximum = relocBlocks->m_end; - for(size_t i=0; i relocBlocks->m_start) relocMinimum = relocBlocks->m_start; - if(relocMaximum < relocBlocks->m_end ) relocMaximum = relocBlocks->m_end; + if (relocMinimum > relocBlocks->m_start) + relocMinimum = relocBlocks->m_start; + if (relocMaximum < relocBlocks->m_end) + relocMaximum = relocBlocks->m_end; } m_relocMinimum = relocMinimum; @@ -363,7 +370,7 @@ void CLR_RT_GarbageCollector::Heap_Relocate() TestPointers_Remap(); - Heap_Relocate_Pass( NULL ); + Heap_Relocate_Pass(NULL); #if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) g_CLR_PRF_Profiler.TrackObjectRelocation(); @@ -377,23 +384,22 @@ void CLR_RT_GarbageCollector::Heap_Relocate() } } -void CLR_RT_GarbageCollector::Heap_Relocate_Pass( RelocateFtn ftn ) +void CLR_RT_GarbageCollector::Heap_Relocate_Pass(RelocateFtn ftn) { NATIVE_PROFILE_CLR_CORE(); - #if NANOCLR_VALIDATE_HEAP > NANOCLR_VALIDATE_HEAP_0_None +#if NANOCLR_VALIDATE_HEAP > NANOCLR_VALIDATE_HEAP_0_None m_relocWorker = ftn; - #else +#else (void)ftn; - #endif +#endif - NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, g_CLR_RT_ExecutionEngine.m_heap) { - CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; - CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; - + CLR_RT_HeapBlock_Node *ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node *end = hc->m_payloadEnd; - while(ptr < end) + while (ptr < end) { CLR_RT_HEAPBLOCK_RELOCATE(ptr); @@ -407,10 +413,10 @@ void CLR_RT_GarbageCollector::Heap_Relocate_Pass( RelocateFtn ftn ) //--// -void CLR_RT_GarbageCollector::Heap_Relocate( CLR_RT_HeapBlock* lst, CLR_UINT32 len ) +void CLR_RT_GarbageCollector::Heap_Relocate(CLR_RT_HeapBlock *lst, CLR_UINT32 len) { NATIVE_PROFILE_CLR_CORE(); - while(len--) + while (len--) { CLR_RT_HEAPBLOCK_RELOCATE(lst); @@ -418,41 +424,41 @@ void CLR_RT_GarbageCollector::Heap_Relocate( CLR_RT_HeapBlock* lst, CLR_UINT32 l } } -void CLR_RT_GarbageCollector::Heap_Relocate( void** ref ) +void CLR_RT_GarbageCollector::Heap_Relocate(void **ref) { NATIVE_PROFILE_CLR_CORE(); - CLR_UINT8* dst = (CLR_UINT8*)*ref; + CLR_UINT8 *dst = (CLR_UINT8 *)*ref; #if NANOCLR_VALIDATE_HEAP > NANOCLR_VALIDATE_HEAP_0_None - if(g_CLR_RT_GarbageCollector.m_relocWorker) + if (g_CLR_RT_GarbageCollector.m_relocWorker) { - g_CLR_RT_GarbageCollector.m_relocWorker( ref ); + g_CLR_RT_GarbageCollector.m_relocWorker(ref); } else #endif { - if(dst >= g_CLR_RT_GarbageCollector.m_relocMinimum && dst < g_CLR_RT_GarbageCollector.m_relocMaximum) + if (dst >= g_CLR_RT_GarbageCollector.m_relocMinimum && dst < g_CLR_RT_GarbageCollector.m_relocMaximum) { - RelocationRegion* relocBlocks = g_CLR_RT_GarbageCollector.m_relocBlocks; - size_t left = 0; - size_t right = g_CLR_RT_GarbageCollector.m_relocCount; + RelocationRegion *relocBlocks = g_CLR_RT_GarbageCollector.m_relocBlocks; + size_t left = 0; + size_t right = g_CLR_RT_GarbageCollector.m_relocCount; - while(left < right) + while (left < right) { - size_t center = (left + right) / 2; - RelocationRegion& relocCurrent = relocBlocks[ center ]; + size_t center = (left + right) / 2; + RelocationRegion &relocCurrent = relocBlocks[center]; - if(dst < relocCurrent.m_start) + if (dst < relocCurrent.m_start) { right = center; } - else if(dst >= relocCurrent.m_end) + else if (dst >= relocCurrent.m_end) { - left = center+1; + left = center + 1; } else { - *ref = (void*)(dst + relocCurrent.m_offset); + *ref = (void *)(dst + relocCurrent.m_offset); return; } @@ -463,18 +469,17 @@ void CLR_RT_GarbageCollector::Heap_Relocate( void** ref ) #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_3_Compaction -bool CLR_RT_GarbageCollector::Relocation_JustCheck( void** ref ) +bool CLR_RT_GarbageCollector::Relocation_JustCheck(void **ref) { NATIVE_PROFILE_CLR_CORE(); - CLR_UINT8* dst = (CLR_UINT8*)*ref; + CLR_UINT8 *dst = (CLR_UINT8 *)*ref; - if(dst) + if (dst) { - ValidateBlockNotInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst ); + ValidateBlockNotInFreeList(g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node *)dst); } return true; } #endif - diff --git a/src/CLR/Core/TypeSystem.cpp b/src/CLR/Core/TypeSystem.cpp index 624c0c9b45..87162b1711 100644 --- a/src/CLR/Core/TypeSystem.cpp +++ b/src/CLR/Core/TypeSystem.cpp @@ -32,11 +32,11 @@ int s_CLR_RT_fTrace_Exceptions = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info, c_CL #endif #if defined(NANOCLR_TRACE_INSTRUCTIONS) -int s_CLR_RT_fTrace_Instructions = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None, c_CLR_RT_Trace_None); +int s_CLR_RT_fTrace_Instructions = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info, c_CLR_RT_Trace_None); #endif #if defined(NANOCLR_GC_VERBOSE) -int s_CLR_RT_fTrace_Memory = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None, c_CLR_RT_Trace_None); +int s_CLR_RT_fTrace_Memory = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info, c_CLR_RT_Trace_None); #endif #if defined(NANOCLR_TRACE_MEMORY_STATS) @@ -44,7 +44,7 @@ int s_CLR_RT_fTrace_MemoryStats = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info, c_C #endif #if defined(NANOCLR_GC_VERBOSE) -int s_CLR_RT_fTrace_GC = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None, c_CLR_RT_Trace_None); +int s_CLR_RT_fTrace_GC = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info, c_CLR_RT_Trace_None); #endif #if defined(VIRTUAL_DEVICE) @@ -1545,11 +1545,8 @@ void CLR_RT_Assembly::Assembly_Initialize(CLR_RT_Assembly::Offsets &offsets) } } -{ - ITERATE_THROUGH_RECORDS(this, i, MethodDef, METHODDEF) - { - dst->m_data = CLR_EmptyIndex; - } +{ITERATE_THROUGH_RECORDS(this, i, MethodDef, METHODDEF){dst->m_data = CLR_EmptyIndex; +} } #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) From 4fb8d205afc059cb1cd9a789dd5d90b2ef564768 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 17:07:48 +0100 Subject: [PATCH 467/572] Add GC and compaction options for CLR_SETTINGS - Expose this in nanoCLR options. - Add code to adjust settings on CLR host run. --- src/CLR/Include/nanoCLR_Application.h | 2 ++ .../ExecuteCommandLineOptions.cs | 14 ++++++++++++++ .../ExecuteCommandProcessor.cs | 2 ++ .../NanoClrHostBuilder.cs | 8 +++++++- .../nanoFramework.nanoCLR.Host/NanoClrSettings.cs | 9 +++++++++ 5 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/CLR/Include/nanoCLR_Application.h b/src/CLR/Include/nanoCLR_Application.h index 98a1ade11d..44a68ae689 100644 --- a/src/CLR/Include/nanoCLR_Application.h +++ b/src/CLR/Include/nanoCLR_Application.h @@ -30,6 +30,8 @@ typedef struct CLR_SETTINGS bool RevertToBooterOnFault; #if defined(VIRTUAL_DEVICE) + bool PerformGarbageCollection; + bool PerformHeapCompaction; CLR_RT_StringVector StartArgs; #endif diff --git a/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandLineOptions.cs b/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandLineOptions.cs index 2c874e5f82..60d6f75872 100644 --- a/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandLineOptions.cs +++ b/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandLineOptions.cs @@ -93,6 +93,20 @@ public class ExecuteCommandLineOptions HelpText = "Option to remain in loop waiting for a debugger connection after the program exits.")] public bool EnterDebuggerLoopAfterExit { get; set; } + [Option( + "forcegc", + Required = false, + Default = false, + HelpText = "Option to force GC before each allocation.")] + public bool PerformGarbageCollection { get; set; } + + [Option( + "compactionaftergc", + Required = false, + Default = false, + HelpText = "Option to force heap compaction after each GC run.")] + public bool PerformHeapCompaction { get; set; } + [Option( "localinstance", Required = false, diff --git a/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandProcessor.cs b/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandProcessor.cs index 4bd0ff9944..ffef757d27 100644 --- a/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandProcessor.cs +++ b/targets/netcore/nanoFramework.nanoCLR.CLI/ExecuteCommandProcessor.cs @@ -129,6 +129,8 @@ public static int ProcessVerb( hostBuilder.WaitForDebugger = options.WaitForDebugger; hostBuilder.EnterDebuggerLoopAfterExit = options.EnterDebuggerLoopAfterExit; + hostBuilder.PerformGarbageCollection = options.PerformGarbageCollection; + hostBuilder.PerformHeapCompaction = options.PerformHeapCompaction; if (options.MonitorParentPid != null) { diff --git a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrHostBuilder.cs b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrHostBuilder.cs index aca36e7cda..e23a4497e5 100644 --- a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrHostBuilder.cs +++ b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrHostBuilder.cs @@ -26,6 +26,10 @@ public class nanoCLRHostBuilder public bool WaitForDebugger { get; set; } = false; public bool EnterDebuggerLoopAfterExit { get; set; } = false; + public bool PerformGarbageCollection { get; set; } = false; + + public bool PerformHeapCompaction { get; set; } = false; + public nanoCLRHostBuilder() { Interop.nanoCLR.DllPath = Path.Combine(Path.GetDirectoryName(Assembly.GetExecutingAssembly().Location), "NanoCLR"); @@ -118,7 +122,9 @@ public nanoCLRHost Build() { MaxContextSwitches = (ushort)MaxContextSwitches, WaitForDebugger = WaitForDebugger, - EnterDebuggerLoopAfterExit = EnterDebuggerLoopAfterExit + EnterDebuggerLoopAfterExit = EnterDebuggerLoopAfterExit, + PerformGarbageCollection = PerformGarbageCollection, + PerformHeapCompaction = PerformHeapCompaction }; return s_nanoClrHost; diff --git a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs index dcd4f72689..4416f0de18 100644 --- a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs +++ b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs @@ -16,11 +16,20 @@ internal struct nanoCLRSettings public bool EnterDebuggerLoopAfterExit { get; set; } + // this is here for compatibility with native structure, doesn't have any usage in virtual device + public bool RevertToBooterOnFault { get; } + + public bool PerformGarbageCollection { get; set; } + + public bool PerformHeapCompaction { get; set; } + public static nanoCLRSettings Default = new() { MaxContextSwitches = 50, WaitForDebugger = false, EnterDebuggerLoopAfterExit = false, + PerformGarbageCollection = false, + PerformHeapCompaction = false, }; } } From 2adca8e74f10ac10971809988476f73497a602e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 17:17:51 +0100 Subject: [PATCH 468/572] Fix return for WP_TransmitMessage - Should be returning true instead of the amount of data transmitted. --- .../nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp b/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp index 7bcb6aabfb..2b7192c1e4 100644 --- a/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp +++ b/targets/netcore/nanoFramework.nanoCLR/WireProtocol_HAL_Interface.cpp @@ -36,7 +36,7 @@ uint8_t WP_TransmitMessage(WP_Message *message) WireProtocolTransmitCallback(&data.front(), data.size()); } - return data.size(); + return true; } void WP_CheckAvailableIncomingData() From 1bcdec613fb2a336b932345c409ca9309602c92c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 17:07:48 +0100 Subject: [PATCH 469/572] Add GC and compaction options for CLR_SETTINGS - Expose this in nanoCLR options. - Add code to adjust settings on CLR host run. --- .../netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs | 3 --- targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp | 3 ++- targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp | 2 ++ targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h | 7 +++++++ 4 files changed, 11 insertions(+), 4 deletions(-) diff --git a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs index 4416f0de18..ee349c7eaf 100644 --- a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs +++ b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs @@ -16,9 +16,6 @@ internal struct nanoCLRSettings public bool EnterDebuggerLoopAfterExit { get; set; } - // this is here for compatibility with native structure, doesn't have any usage in virtual device - public bool RevertToBooterOnFault { get; } - public bool PerformGarbageCollection { get; set; } public bool PerformHeapCompaction { get; set; } diff --git a/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp b/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp index bc20c2f3d7..c76a8a025a 100644 --- a/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp +++ b/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp @@ -30,10 +30,11 @@ struct Settings m_clrOptions = params; -#if defined(PLATFORM_WINDOWS_EMULATOR) g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection = params.PerformGarbageCollection; g_CLR_RT_ExecutionEngine.m_fPerformHeapCompaction = params.PerformHeapCompaction; +#if defined(PLATFORM_WINDOWS_EMULATOR) + CLR_UINT32 clockFrequencyBaseline = 27000000; CLR_UINT32 clockFrequency = CPU_SystemClock(); double clockFrequencyRatio = 1; diff --git a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp index 40595de457..d0e10d61c3 100644 --- a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp +++ b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp @@ -112,6 +112,8 @@ void nanoCLR_Run(NANO_CLR_SETTINGS nanoClrSettings) clrSettings.MaxContextSwitches = nanoClrSettings.MaxContextSwitches; clrSettings.WaitForDebugger = nanoClrSettings.WaitForDebugger; clrSettings.EnterDebuggerLoopAfterExit = nanoClrSettings.EnterDebuggerLoopAfterExit; + clrSettings.PerformGarbageCollection = nanoClrSettings.PerformGarbageCollection; + clrSettings.PerformHeapCompaction = nanoClrSettings.PerformHeapCompaction; ClrStartup(clrSettings); diff --git a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h index eb814a997a..14cedf8f54 100644 --- a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h +++ b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h @@ -25,6 +25,13 @@ typedef struct NANO_CLR_SETTINGS // this is required for launching a debug session in Visual Studio // when building is set for RTM this configuration is ignored BOOL EnterDebuggerLoopAfterExit; + + // set this to TRUE if execution engine is to performa GC before each allocation + BOOL PerformGarbageCollection; + + // set this to TRUE if execution engine is to performa heap compaction after each GC run + BOOL PerformHeapCompaction; + } NANO_CLR_SETTINGS; typedef HRESULT(__stdcall *ConfigureRuntimeCallback)(); From 7fe42d64368e71d09c08d6f32942fe05a3445362 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 29 Aug 2023 17:07:48 +0100 Subject: [PATCH 470/572] Add GC and compaction options for CLR_SETTINGS - Expose this in nanoCLR options. - Add code to adjust settings on CLR host run. - Add new call to ExecutionEngine.CreateInstance taking CLR settings as parameter. - Adjust code to actually set execution engine config from start parameters. --- src/CLR/Core/Cache.cpp | 18 ++++++++++-- src/CLR/Core/Execution.cpp | 28 +++++++++++++++++++ src/CLR/Include/nanoCLR_Runtime.h | 5 ++++ .../NanoClrSettings.cs | 3 -- .../nanoFramework.nanoCLR/CLRStartup.cpp | 7 ++--- .../nanoFramework.nanoCLR/nanoCLR_native.cpp | 2 ++ .../nanoFramework.nanoCLR/nanoCLR_native.h | 7 +++++ 7 files changed, 60 insertions(+), 10 deletions(-) diff --git a/src/CLR/Core/Cache.cpp b/src/CLR/Core/Cache.cpp index 95707a2f63..84d8f1734b 100644 --- a/src/CLR/Core/Cache.cpp +++ b/src/CLR/Core/Cache.cpp @@ -571,13 +571,25 @@ CLR_RT_HeapBlock *CLR_RT_EventCache::Extract_Node_Bytes(CLR_UINT32 dataType, CLR CLR_RT_HeapBlock *CLR_RT_EventCache::Extract_Node(CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks) { NATIVE_PROFILE_CLR_CORE(); + #if defined(NANOCLR_FORCE_GC_BEFORE_EVERY_ALLOCATION) return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents(dataType, flags, blocks); #else - if (blocks > 0 && blocks < c_maxFastLists) - return Extract_Node_Fast(dataType, flags, blocks); + if (g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection) + { + return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents(dataType, flags, blocks); + } else - return Extract_Node_Slow(dataType, flags, blocks); + { + if (blocks > 0 && blocks < c_maxFastLists) + { + return Extract_Node_Fast(dataType, flags, blocks); + } + else + { + return Extract_Node_Slow(dataType, flags, blocks); + } + } #endif } diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp index 4ea1be346a..81dd9477d2 100644 --- a/src/CLR/Core/Execution.cpp +++ b/src/CLR/Core/Execution.cpp @@ -17,6 +17,26 @@ CLR_RT_ExecutionEngine::ExecutionConstraintCompensation CLR_RT_ExecutionEngine:: //--// +#if defined(VIRTUAL_DEVICE) + +HRESULT CLR_RT_ExecutionEngine::CreateInstance(CLR_SETTINGS params) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CLEAR(g_CLR_RT_ExecutionEngine); + + // config from CLR settings + g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection = params.PerformGarbageCollection; + g_CLR_RT_ExecutionEngine.m_fPerformHeapCompaction = params.PerformHeapCompaction; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.ExecutionEngine_Initialize()); + + NANOCLR_NOCLEANUP(); +} + +#else + HRESULT CLR_RT_ExecutionEngine::CreateInstance() { NATIVE_PROFILE_CLR_CORE(); @@ -29,6 +49,8 @@ HRESULT CLR_RT_ExecutionEngine::CreateInstance() NANOCLR_NOCLEANUP(); } +#endif + //--// HRESULT CLR_RT_ExecutionEngine::ExecutionEngine_Initialize() @@ -1586,6 +1608,12 @@ CLR_RT_HeapBlock *CLR_RT_ExecutionEngine::ExtractHeapBlocks( g_CLR_RT_EventCache.EventCache_Cleanup(); PerformGarbageCollection(); } +#else + if (g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection) + { + g_CLR_RT_EventCache.EventCache_Cleanup(); + PerformGarbageCollection(); + } #endif for (int phase = 0;; phase++) diff --git a/src/CLR/Include/nanoCLR_Runtime.h b/src/CLR/Include/nanoCLR_Runtime.h index cc6abaf7f6..cc6fda1640 100644 --- a/src/CLR/Include/nanoCLR_Runtime.h +++ b/src/CLR/Include/nanoCLR_Runtime.h @@ -3388,6 +3388,7 @@ CT_ASSERT(sizeof(CLR_RT_EventCache::Payload) == 12) #include #include +#include // #include //--// @@ -3666,7 +3667,11 @@ struct CLR_RT_ExecutionEngine //--// +#if defined(VIRTUAL_DEVICE) + static HRESULT CreateInstance(CLR_SETTINGS params); +#else static HRESULT CreateInstance(); +#endif HRESULT ExecutionEngine_Initialize(); diff --git a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs index 4416f0de18..ee349c7eaf 100644 --- a/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs +++ b/targets/netcore/nanoFramework.nanoCLR.Host/NanoClrSettings.cs @@ -16,9 +16,6 @@ internal struct nanoCLRSettings public bool EnterDebuggerLoopAfterExit { get; set; } - // this is here for compatibility with native structure, doesn't have any usage in virtual device - public bool RevertToBooterOnFault { get; } - public bool PerformGarbageCollection { get; set; } public bool PerformHeapCompaction { get; set; } diff --git a/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp b/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp index bc20c2f3d7..825a1f1ce1 100644 --- a/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp +++ b/targets/netcore/nanoFramework.nanoCLR/CLRStartup.cpp @@ -31,8 +31,6 @@ struct Settings m_clrOptions = params; #if defined(PLATFORM_WINDOWS_EMULATOR) - g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection = params.PerformGarbageCollection; - g_CLR_RT_ExecutionEngine.m_fPerformHeapCompaction = params.PerformHeapCompaction; CLR_UINT32 clockFrequencyBaseline = 27000000; CLR_UINT32 clockFrequency = CPU_SystemClock(); @@ -50,7 +48,7 @@ struct Settings g_HAL_Configuration_Windows.GraphHeapEnabled = false; #endif - NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CreateInstance()); + NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CreateInstance(params)); #if !defined(BUILD_RTM) CLR_Debug::Printf("Created EE.\r\n"); #endif @@ -437,7 +435,8 @@ struct Settings if (!m_fInitialized) { - CLR_RT_ExecutionEngine::CreateInstance(); + // TODO: all this LoadAssembliesSet is to be removed in another PR + // CLR_RT_ExecutionEngine::CreateInstance(); } { diff --git a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp index 40595de457..d0e10d61c3 100644 --- a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp +++ b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.cpp @@ -112,6 +112,8 @@ void nanoCLR_Run(NANO_CLR_SETTINGS nanoClrSettings) clrSettings.MaxContextSwitches = nanoClrSettings.MaxContextSwitches; clrSettings.WaitForDebugger = nanoClrSettings.WaitForDebugger; clrSettings.EnterDebuggerLoopAfterExit = nanoClrSettings.EnterDebuggerLoopAfterExit; + clrSettings.PerformGarbageCollection = nanoClrSettings.PerformGarbageCollection; + clrSettings.PerformHeapCompaction = nanoClrSettings.PerformHeapCompaction; ClrStartup(clrSettings); diff --git a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h index eb814a997a..14cedf8f54 100644 --- a/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h +++ b/targets/netcore/nanoFramework.nanoCLR/nanoCLR_native.h @@ -25,6 +25,13 @@ typedef struct NANO_CLR_SETTINGS // this is required for launching a debug session in Visual Studio // when building is set for RTM this configuration is ignored BOOL EnterDebuggerLoopAfterExit; + + // set this to TRUE if execution engine is to performa GC before each allocation + BOOL PerformGarbageCollection; + + // set this to TRUE if execution engine is to performa heap compaction after each GC run + BOOL PerformHeapCompaction; + } NANO_CLR_SETTINGS; typedef HRESULT(__stdcall *ConfigureRuntimeCallback)(); From cf7575be339255e268a760d197408dfd595779af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Thu, 31 Aug 2023 18:03:52 +0100 Subject: [PATCH 471/572] Fix compiler def check for RTM build and GC --- src/CLR/Core/Cache.cpp | 3 +++ src/CLR/Core/Execution.cpp | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/CLR/Core/Cache.cpp b/src/CLR/Core/Cache.cpp index 84d8f1734b..06a483fc83 100644 --- a/src/CLR/Core/Cache.cpp +++ b/src/CLR/Core/Cache.cpp @@ -575,11 +575,14 @@ CLR_RT_HeapBlock *CLR_RT_EventCache::Extract_Node(CLR_UINT32 dataType, CLR_UINT3 #if defined(NANOCLR_FORCE_GC_BEFORE_EVERY_ALLOCATION) return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents(dataType, flags, blocks); #else + +#if !defined(BUILD_RTM) || defined(VIRTUAL_DEVICE) if (g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection) { return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents(dataType, flags, blocks); } else +#endif { if (blocks > 0 && blocks < c_maxFastLists) { diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp index 8b2c694c77..f79e98b13e 100644 --- a/src/CLR/Core/Execution.cpp +++ b/src/CLR/Core/Execution.cpp @@ -1609,11 +1609,15 @@ CLR_RT_HeapBlock *CLR_RT_ExecutionEngine::ExtractHeapBlocks( PerformGarbageCollection(); } #else + +#if !defined(BUILD_RTM) || defined(VIRTUAL_DEVICE) if (g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection) { g_CLR_RT_EventCache.EventCache_Cleanup(); PerformGarbageCollection(); } +#endif + #endif for (int phase = 0;; phase++) From f6c16545d63fa366dddfcd567ab05ca7d2f8beb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 31 Aug 2023 19:12:16 +0100 Subject: [PATCH 472/572] Fix CLR startup params - Addresses nanoframework/Home#1350. --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c | 9 ++++++++- .../AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c | 9 ++++++++- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c index def0fb1073..2b709b5441 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c @@ -138,8 +138,15 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = false; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else clrSettings.EnterDebuggerLoopAfterExit = true; - clrSettings.RevertToBooterOnFault = true; +#endif // Create CLR startup thread status = tx_thread_create( diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c index def0fb1073..2b709b5441 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c @@ -138,8 +138,15 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = false; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else clrSettings.EnterDebuggerLoopAfterExit = true; - clrSettings.RevertToBooterOnFault = true; +#endif // Create CLR startup thread status = tx_thread_create( diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c index def0fb1073..2b709b5441 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c @@ -138,8 +138,15 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = false; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else clrSettings.EnterDebuggerLoopAfterExit = true; - clrSettings.RevertToBooterOnFault = true; +#endif // Create CLR startup thread status = tx_thread_create( From bd26b798062ab2fe27c4afb0e0c1595c09875526 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 4 Sep 2023 13:51:56 +0100 Subject: [PATCH 473/572] Fix mapping of managed SpiBaseConfiguration fields - Fixes Skyworks-Timing-Software/MCU#87. --- ..._Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index bb60149923..f2b07724dc 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -137,13 +137,18 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) // SPI bus index is 1 based, but the array is 0 based spiDeviceConfig->Spi_Bus = busIndex + 1; - spiDeviceConfig->Spi_Mode = (SpiMode)config[SpiBaseConfiguration::FIELD___spiWireMode].NumericByRef().s4; + // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode + // which is stored at _spiPhasePolarityMode + spiDeviceConfig->Spi_Mode = + (SpiMode)config[SpiBaseConfiguration::FIELD___spiPhasePolarityMode].NumericByRef().s4; spiDeviceConfig->DataOrder16 = (DataBitOrder)config[SpiBaseConfiguration::FIELD___dataFlow].NumericByRef().s4; spiDeviceConfig->Clock_RateHz = config[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRef().s4; spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; + // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode + // which is stored at _spiWireMode field spiDeviceConfig->BusConfiguration = - (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___spiPhasePolarityMode].NumericByRef().s4; + (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___spiWireMode].NumericByRef().s4; spiDeviceConfig->DataIs16bits = config[SpiBaseConfiguration::FIELD___databitLength].NumericByRef().s4 == 16 ? true : false; // store this here too From 335321bcd52607a266a8af07a72b2c009e45fa85 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 5 Sep 2023 15:52:26 -0500 Subject: [PATCH 474/572] Si5575 CEVB: add Release CLR build --- .github/workflows/Build_Si5575_CEVB_Release.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 .github/workflows/Build_Si5575_CEVB_Release.yaml diff --git a/.github/workflows/Build_Si5575_CEVB_Release.yaml b/.github/workflows/Build_Si5575_CEVB_Release.yaml new file mode 100644 index 0000000000..56e6cadf3b --- /dev/null +++ b/.github/workflows/Build_Si5575_CEVB_Release.yaml @@ -0,0 +1,11 @@ +name: Build Si5575_CEVB_Release + +on: + workflow_dispatch + +jobs: + build_Si5575_CEVB_Release: + name: Build Si5575_CEVB_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5575_CEVB_Release' From 471beb068b97a6e00759dfd56da8cad5f4742de5 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 6 Sep 2023 10:37:24 -0500 Subject: [PATCH 475/572] Fix SKY_EEVB_Release RTM target: it reported that it was the Debug release --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index efd0294aa9..5a394eda56 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -59,7 +59,7 @@ ], "hidden": false, "cacheVariables": { - "TARGET_NAME": "SKY_EEVB_Debug", + "TARGET_NAME": "SKY_EEVB_Release", "NF_BUILD_RTM": "ON" } } From 30bc2204505b2ff99cd916b08e015c3c49d39309 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 6 Sep 2023 14:50:22 +0100 Subject: [PATCH 476/572] Rework Profiler output message for object creation --- src/CLR/Diagnostics/Profiler.cpp | 81 ++++++++++++++++++++++++++++---- 1 file changed, 73 insertions(+), 8 deletions(-) diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index c0378c39f2..42463f5b91 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -679,32 +679,97 @@ void CLR_PRF_Profiler::TrackObjectCreation(CLR_RT_HeapBlock *ptr) if (dt != DATATYPE_STACK_FRAME && dt != DATATYPE_BINARY_BLOB_HEAD) { Timestamp(); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Allocs_Alloc, CLR_PRF_CMDS::Bits::CommandHeader); + DumpPointer(ptr); - PackAndWriteBits(ptr->DataSize()); + + CLR_UINT16 dataSize = ptr->DataSize(); + PackAndWriteBits(dataSize); + m_stream->WriteBits((CLR_UINT32)dt, CLR_PRF_CMDS::Bits::DataType); + if (dt == DATATYPE_CLASS || dt == DATATYPE_VALUETYPE) { - PackAndWriteBits(ptr->ObjectCls()); + CLR_RT_TypeDef_Index idx = ptr->ObjectCls(); + PackAndWriteBits(idx); + +#ifdef NANOCLR_TRACE_PROFILER_MESSAGES + +#ifdef _WIN64 + CLR_Debug::Printf( + "\r\n Profiler info: ! (0x0x%I64X | %d) DT: %d %d bytes idx: %08x\r\n", + (size_t)((CLR_UINT8 *)ptr), + (CLR_UINT32)((size_t *)ptr - s_CLR_RT_Heap.m_location), + (CLR_UINT32)dt, + (dataSize * sizeof(CLR_RT_HeapBlock)), + idx.m_data); + +#else + CLR_Debug::Printf( + "\r\n Profiler info: ! (0x%08X | %d) DT: %d %d bytes idx: %08x\r\n", + (CLR_UINT32)((CLR_UINT8 *)ptr), + (CLR_UINT32)((CLR_UINT8 *)ptr - s_CLR_RT_Heap.m_location), + (CLR_UINT32)dt, + (dataSize * sizeof(CLR_RT_HeapBlock)), + idx.m_data); +#endif + +#endif // NANOCLR_TRACE_PROFILER_MESSAGES } else if (dt == DATATYPE_SZARRAY) { CLR_RT_HeapBlock_Array *array = (CLR_RT_HeapBlock_Array *)ptr; PackAndWriteBits(array->ReflectionDataConst().m_data.m_type); PackAndWriteBits(array->ReflectionDataConst().m_levels); - } - Stream_Send(); #ifdef NANOCLR_TRACE_PROFILER_MESSAGES -#if _WIN64 - CLR_Debug::Printf("\r\n Profiler msg: ! %d 0x%I64X\r\n", m_currentThreadPID, (size_t)(CLR_UINT8 *)ptr); + CLR_RT_TypeDef_Index elementIdx = array->ReflectionDataConst().m_data.m_type; + +#ifdef _WIN64 + CLR_Debug::Printf( + "\r\n Profiler info: ! (0x0x%I64X | %d) DT: %d [%08x] %d bytes\r\n", + (size_t)((CLR_UINT8 *)ptr), + (CLR_UINT32)((size_t *)ptr - s_CLR_RT_Heap.m_location), + (CLR_UINT32)dt, + elementIdx.m_data, + (dataSize * sizeof(CLR_RT_HeapBlock))); #else - CLR_Debug::Printf("\r\n Profiler msg: ! %d 0x%08x\r\n", m_currentThreadPID, (size_t)(CLR_UINT8 *)ptr); + CLR_Debug::Printf( + "\r\n Profiler info: ! (0x%08X | %d) DT: %d [%08x] %d bytes\r\n", + (CLR_UINT32)((CLR_UINT8 *)ptr), + (CLR_UINT32)((CLR_UINT8 *)ptr - s_CLR_RT_Heap.m_location), + (CLR_UINT32)dt, + elementIdx.m_data, + (dataSize * sizeof(CLR_RT_HeapBlock))); #endif +#endif // NANOCLR_TRACE_PROFILER_MESSAGES + } +#ifdef NANOCLR_TRACE_PROFILER_MESSAGES + else + { +#ifdef _WIN64 + CLR_Debug::Printf( + "\r\n Profiler info: ! (0x0x%I64X | %d) DT: %d %d bytes\r\n", + (size_t)((CLR_UINT8 *)ptr), + (CLR_UINT32)((size_t *)ptr - s_CLR_RT_Heap.m_location), + (CLR_UINT32)dt, + (dataSize * sizeof(CLR_RT_HeapBlock))); -#endif // NANOCLR_TRACE_PROFILER_MESSAGES +#else + CLR_Debug::Printf( + "\r\n Profiler info: ! (0x%08X | %d) DT: %d %d bytes\r\n", + (CLR_UINT32)((CLR_UINT8 *)ptr), + (CLR_UINT32)((CLR_UINT8 *)ptr - s_CLR_RT_Heap.m_location), + (CLR_UINT32)dt, + (dataSize * sizeof(CLR_RT_HeapBlock))); +#endif + } +#endif // NANOCLR_TRACE_PROFILER_MESSAGES + + Stream_Send(); } } } From 98a9fe8f8ad28e3db4206219f49aa31ce3669d33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 11 Sep 2023 13:29:38 +0100 Subject: [PATCH 477/572] Remove redundant code line --- src/CLR/Diagnostics/Profiler.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index 72b992aee9..44cd87c69b 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -723,7 +723,6 @@ void CLR_PRF_Profiler::TrackObjectCreation(CLR_RT_HeapBlock *ptr) else if (dt == DATATYPE_SZARRAY) { CLR_RT_HeapBlock_Array *array = (CLR_RT_HeapBlock_Array *)ptr; - CLR_RT_TypeDef_Index elementIdx = array->ReflectionDataConst().m_data.m_type; PackAndWriteBits(array->ReflectionDataConst().m_data.m_type); PackAndWriteBits(array->ReflectionDataConst().m_levels); From ac29a1f977b380a7a364064b8ea9e116ac67ca24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 12 Sep 2023 11:44:16 +0100 Subject: [PATCH 478/572] Rework launch booter API to include error code - Struct updated to hold negative error codes. - Declaration updated to take parameter with error code. - Code updated accordingly. --- src/CLR/Debugger/Debugger.cpp | 2 +- src/CLR/Startup/CLRStartup.cpp | 5 +++-- src/HAL/Include/nanoHAL_Boot.h | 6 +++--- src/HAL/nanoHAL_Boot.c | 5 +++-- targets/win32/Include/targetHAL.h | 4 +++- 5 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/CLR/Debugger/Debugger.cpp b/src/CLR/Debugger/Debugger.cpp index d22bd95987..8a77f9082c 100644 --- a/src/CLR/Debugger/Debugger.cpp +++ b/src/CLR/Debugger/Debugger.cpp @@ -1066,7 +1066,7 @@ bool CLR_DBG_Debugger::Monitor_Reboot(WP_Message *msg) if (CLR_DBG_Commands::Monitor_Reboot::c_EnterNanoBooter == (cmd->m_flags & CLR_DBG_Commands::Monitor_Reboot::c_EnterNanoBooter)) { - success = RequestToLaunchNanoBooter(); + success = RequestToLaunchNanoBooter(0); } else if ( CLR_DBG_Commands::Monitor_Reboot::c_EnterProprietaryBooter == diff --git a/src/CLR/Startup/CLRStartup.cpp b/src/CLR/Startup/CLRStartup.cpp index 7f4926ed2b..60343a29bd 100644 --- a/src/CLR/Startup/CLRStartup.cpp +++ b/src/CLR/Startup/CLRStartup.cpp @@ -404,7 +404,7 @@ void ClrStartup(CLR_SETTINGS params) CLR_Debug::Printf("Ready.\r\n"); #endif - (void)g_CLR_RT_ExecutionEngine.Execute(NULL, params.MaxContextSwitches); + hr = g_CLR_RT_ExecutionEngine.Execute(NULL, params.MaxContextSwitches); #if !defined(BUILD_RTM) CLR_Debug::Printf("Done.\r\n"); @@ -435,7 +435,8 @@ void ClrStartup(CLR_SETTINGS params) // no proprietary bootloader available, launch nanoBooter #if (TARGET_HAS_NANOBOOTER == TRUE) - RequestToLaunchNanoBooter(); + + RequestToLaunchNanoBooter(hr); CPU_Reset(); #endif // TARGET_HAS_NANOBOOTER } diff --git a/src/HAL/Include/nanoHAL_Boot.h b/src/HAL/Include/nanoHAL_Boot.h index b73ddd38ad..69be53c3e2 100644 --- a/src/HAL/Include/nanoHAL_Boot.h +++ b/src/HAL/Include/nanoHAL_Boot.h @@ -42,7 +42,7 @@ typedef struct __nfpack BootClipboard BootRequest_Options BootRequest; uint32_t BootParameters; BootExecution_Options BootExecution; - uint32_t ErrorCode; + int32_t ErrorCode; VersionInfo BooterVersion; VersionInfo CLRVersion; @@ -73,9 +73,9 @@ extern "C" // Returns true if the there is a request to remain in nanoBooter bool IsToRemainInBooter(); - // Request to launch nanoBooter + // Request to launch nanoBooter and set an error code // Returns false in case it's not supported (which is considered the default). - bool RequestToLaunchNanoBooter(); + bool RequestToLaunchNanoBooter(int32_t errorCode); // Request to launch proprietary bootloader // Returns false in case it's not supported (which is considered the default). diff --git a/src/HAL/nanoHAL_Boot.c b/src/HAL/nanoHAL_Boot.c index 664b3c6243..73549508f8 100644 --- a/src/HAL/nanoHAL_Boot.c +++ b/src/HAL/nanoHAL_Boot.c @@ -61,14 +61,15 @@ inline bool IsToRemainInBooter() #endif } -// Request to launch nanoBooter +// Request to launch nanoBooter and report error code // Returns false in case it's not supported (which is considered the default). -inline bool RequestToLaunchNanoBooter() +inline bool RequestToLaunchNanoBooter(int32_t errorCode) { #if (TARGET_HAS_NANOBOOTER == TRUE) if (Target_HasNanoBooter()) { g_BootClipboard.BootRequest = BootRequest_NanoBooter; + g_BootClipboard.ErrorCode = errorCode; return true; } #endif diff --git a/targets/win32/Include/targetHAL.h b/targets/win32/Include/targetHAL.h index dc55a0b8dc..cd5248f844 100644 --- a/targets/win32/Include/targetHAL.h +++ b/targets/win32/Include/targetHAL.h @@ -83,8 +83,10 @@ inline bool RequestToLaunchProprietaryBootloader() return false; }; -inline bool RequestToLaunchNanoBooter() +inline bool RequestToLaunchNanoBooter(int32_t errorCode) { + (void)errorCode; + return false; }; From 2fe1b2e8276f56d52dca062272ecd23f2f285189 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 12 Sep 2023 12:12:48 +0100 Subject: [PATCH 479/572] Booter state is now updated on launch CLR - Before launching CLR from nanoBooter the code now goes through ReportSuccessfullNanoBooter. --- targets/AzureRTOS/ST/_common/LaunchCLR.c | 3 +++ targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c | 3 +++ targets/ChibiOS/_common/LaunchCLR.c | 3 +++ 3 files changed, 9 insertions(+) diff --git a/targets/AzureRTOS/ST/_common/LaunchCLR.c b/targets/AzureRTOS/ST/_common/LaunchCLR.c index fb660643d9..c8b3a44583 100644 --- a/targets/AzureRTOS/ST/_common/LaunchCLR.c +++ b/targets/AzureRTOS/ST/_common/LaunchCLR.c @@ -14,6 +14,9 @@ void LaunchCLR(uint32_t address) // function pointer to load nanoCLR ResetHandler address irq_vector_t JumpToNanoCLR; + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); + // load nanoCLR vector table const vectors_t *nanoCLRVectorTable = (vectors_t *)address; diff --git a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c index 8bf4e23bf1..94dd0486f1 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c +++ b/targets/AzureRTOS/SiliconLabs/_common/LaunchCLR.c @@ -15,6 +15,9 @@ void LaunchCLR(uint32_t address) // function pointer to load nanoCLR ResetHandler address irq_vector_t JumpToNanoCLR; + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); + // load nanoCLR vector table const vectors_t *nanoCLRVectorTable = (vectors_t *)address; diff --git a/targets/ChibiOS/_common/LaunchCLR.c b/targets/ChibiOS/_common/LaunchCLR.c index bb941b47a7..e82c116d53 100644 --- a/targets/ChibiOS/_common/LaunchCLR.c +++ b/targets/ChibiOS/_common/LaunchCLR.c @@ -14,6 +14,9 @@ void LaunchCLR(uint32_t address) // function pointer to load nanoCLR ResetHandler address irq_vector_t JumpToNanoCLR; + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); + // load nanoCLR vector table const vectors_t* nanoCLRVectorTable = (vectors_t*) address; From f4424760025bcda4278493f2caf690a36034b336 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 13 Sep 2023 18:32:53 +0100 Subject: [PATCH 480/572] Add new build options for profiler --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 6 +++++- .../AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json | 6 +++++- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 5a394eda56..a15a835edf 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -25,6 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", "NF_CLR_NO_IL_INLINE": "ON", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", @@ -60,7 +62,9 @@ "hidden": false, "cacheVariables": { "TARGET_NAME": "SKY_EEVB_Release", - "NF_BUILD_RTM": "ON" + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" } } ], diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index c1b489553c..f466f129b3 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -25,6 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", @@ -59,7 +61,9 @@ "hidden": false, "cacheVariables": { "TARGET_NAME": "STB_Interposer", - "NF_BUILD_RTM": "ON" + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" } } ], diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index 7458268886..fcdc3c71a8 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -25,6 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", @@ -59,7 +61,9 @@ "hidden": false, "cacheVariables": { "TARGET_NAME": "Si5575_CEVB_Release", - "NF_BUILD_RTM": "ON" + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" } } ], From be3489690a01a210956608b36405e70fe921c7f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 15 Sep 2023 00:14:02 +0100 Subject: [PATCH 481/572] Work CI-CD - Update GCC to v12.3.Rel1. --- .github/workflows/skyworks_evb_build.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index fd938e06cf..0499e61a8f 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -53,7 +53,7 @@ jobs: - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: - release: '12.2.Rel1' + release: '12.3.Rel1' - name: Tweak GCC path run: | From 7130d35846721613387bbd350291fce0c22bc791 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 19 Sep 2023 12:31:00 +0100 Subject: [PATCH 482/572] Fix compiler def check --- src/CLR/Core/Execution.cpp | 2 +- src/CLR/Core/GarbageCollector_Info.cpp | 16 ++++++++-------- src/CLR/Diagnostics/Profiler.cpp | 10 +++++----- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp index f79e98b13e..a23ea14161 100644 --- a/src/CLR/Core/Execution.cpp +++ b/src/CLR/Core/Execution.cpp @@ -176,7 +176,7 @@ HRESULT CLR_RT_ExecutionEngine::AllocateHeaps() CLR_Debug::Printf("Heap Cluster information\r\n"); -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Start: 0x%I64X\r\n", (size_t)heapFirstFree); CLR_Debug::Printf("Free: 0x%I64X\r\n", (size_t)heapFree); CLR_Debug::Printf("Block size: %d\r\n", sizeof(CLR_RT_HeapBlock)); diff --git a/src/CLR/Core/GarbageCollector_Info.cpp b/src/CLR/Core/GarbageCollector_Info.cpp index 3616091429..51ff270fa4 100644 --- a/src/CLR/Core/GarbageCollector_Info.cpp +++ b/src/CLR/Core/GarbageCollector_Info.cpp @@ -128,7 +128,7 @@ void CLR_RT_GarbageCollector::ValidateBlockNotInFreeList(CLR_RT_DblLinkedList &l if (ptr <= dst && dst < ptrEnd) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Pointer into free list!! %I64X %I64X %I64X\r\n", dst, ptr, ptrEnd); #else CLR_Debug::Printf("Pointer into free list!! %08x %08x %08x\r\n", dst, ptr, ptrEnd); @@ -215,7 +215,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker(void **ref) if (s_mapOldToRecord.find(ref) != s_mapOldToRecord.end()) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Duplicate base OLD: %I64X\r\n", ref); #else CLR_Debug::Printf("Duplicate base OLD: %08x\r\n", ref); @@ -228,7 +228,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker(void **ref) if (IsBlockInFreeList(g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node *)dst, false)) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Some data points into a free list: %I64X\r\n", dst); #else CLR_Debug::Printf("Some data points into a free list: %08x\r\n", dst); @@ -286,7 +286,7 @@ void CLR_RT_GarbageCollector::TestPointers_Remap() if (s_mapNewToRecord.find(ref) != s_mapNewToRecord.end()) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Duplicate base NEW: %I64X\r\n", ref); #else CLR_Debug::Printf("Duplicate base NEW: %08x\r\n", ref); @@ -318,7 +318,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker(void **ref) if (ptr->newPtr != dst) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Bad pointer: %I64X %I64X\r\n", ptr->newPtr, dst); #else CLR_Debug::Printf("Bad pointer: %08x %08x\r\n", ptr->newPtr, dst); @@ -327,7 +327,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker(void **ref) } else if (ptr->data != *dst) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Bad data: %I64X %I64X\r\n", ptr->data, *dst); #else CLR_Debug::Printf("Bad data: %08x %08x\r\n", ptr->data, *dst); @@ -338,7 +338,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker(void **ref) if (IsBlockInFreeList(g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node *)dst, false)) { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Some data points into a free list: %I64X\r\n", dst); #else CLR_Debug::Printf("Some data points into a free list: %08x\r\n", dst); @@ -351,7 +351,7 @@ bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker(void **ref) } else { -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf("Bad base: 0x%0I64X\r\n", ref); #else CLR_Debug::Printf("Bad base: 0x%08x\r\n", ref); diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index 44cd87c69b..bd7d1ce2a1 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -848,7 +848,7 @@ void CLR_PRF_Profiler::TrackObjectRelocation() #ifdef NANOCLR_TRACE_PROFILER_MESSAGES -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf( "\r\n Profiler msg: u 0x%I64X 0x%I64X %d\r\n", relocBlocks[i].m_start, @@ -887,7 +887,7 @@ void CLR_PRF_Profiler::RecordGarbageCollectionBegin() #ifdef NANOCLR_TRACE_PROFILER_MESSAGES -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf( "\r\n Profiler msg: b 1 0 0 0x%I64X 0x%I64X %d 0\r\n", (CLR_UINT32)s_CLR_RT_Heap.m_location, @@ -925,7 +925,7 @@ void CLR_PRF_Profiler::RecordGarbageCollectionEnd() #ifdef NANOCLR_TRACE_PROFILER_MESSAGES -#if _WIN64 +#ifdef _WIN64 NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster, hc, g_CLR_RT_ExecutionEngine.m_heap) { CLR_Debug::Printf("\r\n Profiler msg: v 0x%I64X 0\r\n", (CLR_UINT32)hc->m_payloadStart); @@ -975,7 +975,7 @@ void CLR_PRF_Profiler::RecordHeapCompactionBegin() #ifdef NANOCLR_TRACE_PROFILER_MESSAGES -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf( "\r\n Profiler msg: b 1 0 0 0x%I64X 0x%I64X %d 0\r\n", (CLR_UINT32)s_CLR_RT_Heap.m_location, @@ -1013,7 +1013,7 @@ void CLR_PRF_Profiler::RecordHeapCompactionEnd() #ifdef NANOCLR_TRACE_PROFILER_MESSAGES -#if _WIN64 +#ifdef _WIN64 CLR_Debug::Printf( "\r\n Profiler msg: b 0 0 0 0x%I64X 0x%I64X %d 0\r\n", (CLR_UINT32)s_CLR_RT_Heap.m_location, From 757f209b8ee3e2c9978977eb0ee45d9d2c2bb3a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 3 Oct 2023 11:14:56 +0100 Subject: [PATCH 483/572] Improvements Skyworks SPI assembly (#9) --- .../com_sky_nf_dev_spi_native.cpp | 3 +- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 90 +++++++++++-------- 2 files changed, 57 insertions(+), 36 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index c6e9ac922b..bf5094d1e6 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -30,6 +30,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4, @@ -46,7 +47,7 @@ const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramewo "Com.SkyworksInc.NanoFramework.Devices.Spi", 0x060333BF, method_lookup, - { 100, 0, 0, 7 } + { 100, 0, 0, 8 } }; // clang-format on diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index f2b07724dc..44c26aabca 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -37,6 +37,50 @@ void Com_Sky_Spi_Callback(int busIndex) Events_Set(SYSTEM_EVENT_FLAG_SPI_MASTER); } +void ConfigureAndInitSpiBus( + int8_t busIndex, + SPI_DEVICE_CONFIGURATION *&spiDeviceConfig, + const CLR_RT_HeapBlock *baseConfig) +{ + NF_PAL_SPI *palSpi = NULL; + + // CS is always active low + spiDeviceConfig->ChipSelectActiveState = false; + // CS is controled by the Gecko SDK driver + spiDeviceConfig->DeviceChipSelect = -1; + // always bus master + spiDeviceConfig->BusMode = SpiBusMode_master; + + // SPI bus index is 1 based, but the array is 0 based + spiDeviceConfig->Spi_Bus = busIndex + 1; + + // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode + // which is stored at _spiPhasePolarityMode + spiDeviceConfig->Spi_Mode = + (SpiMode)baseConfig[SpiBaseConfiguration::FIELD___spiPhasePolarityMode].NumericByRefConst().s4; + spiDeviceConfig->DataOrder16 = + (DataBitOrder)baseConfig[SpiBaseConfiguration::FIELD___dataFlow].NumericByRefConst().s4; + spiDeviceConfig->Clock_RateHz = baseConfig[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRefConst().s4; + spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; + // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode + // which is stored at _spiWireMode field + spiDeviceConfig->BusConfiguration = + (SpiBusConfiguration)baseConfig[SpiBaseConfiguration::FIELD___spiWireMode].NumericByRefConst().s4; + spiDeviceConfig->DataIs16bits = + baseConfig[SpiBaseConfiguration::FIELD___databitLength].NumericByRefConst().s4 == 16 ? true : false; + + // get PAL SPI + palSpi = GetNfPalfromBusIndex(busIndex); + + // store this here too + palSpi->BufferIs16bits = spiDeviceConfig->DataIs16bits; + + CPU_SPI_Initialize_Extended(busIndex, *spiDeviceConfig, true); + + // lower changes pending flag + BusConfigChangesPending[busIndex] = false; +} + // duplicated from src\System.Device.Spi\sys_dev_spi_native_System_Device_Spi_SpiDevice.cpp // estimate the time required to perform the SPI transaction // TODO doesn't take into account of full duplex or sequential ( assumes sequential at the moment ) @@ -79,7 +123,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - CLR_RT_HeapBlock *config = NULL; + CLR_RT_HeapBlock *baseConfig = NULL; CLR_RT_HeapBlock_Array *writeBuffer; CLR_RT_HeapBlock_Array *readBuffer; CLR_RT_HeapBlock *writeSpanByte; @@ -125,39 +169,9 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) // compose SPI_DEVICE_CONFIGURATION // get SpiBaseConfiguration from argument - config = stack.Arg5().Dereference(); - - // CS is always active low - spiDeviceConfig->ChipSelectActiveState = false; - // CS is controled by the Gecko SDK driver - spiDeviceConfig->DeviceChipSelect = -1; - // always bus master - spiDeviceConfig->BusMode = SpiBusMode_master; - - // SPI bus index is 1 based, but the array is 0 based - spiDeviceConfig->Spi_Bus = busIndex + 1; - - // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode - // which is stored at _spiPhasePolarityMode - spiDeviceConfig->Spi_Mode = - (SpiMode)config[SpiBaseConfiguration::FIELD___spiPhasePolarityMode].NumericByRef().s4; - spiDeviceConfig->DataOrder16 = - (DataBitOrder)config[SpiBaseConfiguration::FIELD___dataFlow].NumericByRef().s4; - spiDeviceConfig->Clock_RateHz = config[SpiBaseConfiguration::FIELD___clockFrequency].NumericByRef().s4; - spiDeviceConfig->ByteTime = (1.0 / spiDeviceConfig->Clock_RateHz) * 1000 * 8; - // this comes from Com.SkyworksInc.NanoFramework.Devices.Spi.SpiWireMode - // which is stored at _spiWireMode field - spiDeviceConfig->BusConfiguration = - (SpiBusConfiguration)config[SpiBaseConfiguration::FIELD___spiWireMode].NumericByRef().s4; - spiDeviceConfig->DataIs16bits = - config[SpiBaseConfiguration::FIELD___databitLength].NumericByRef().s4 == 16 ? true : false; - // store this here too - palSpi->BufferIs16bits = spiDeviceConfig->DataIs16bits; - - CPU_SPI_Initialize_Extended(busIndex, *spiDeviceConfig, true); - - // lower changes pending flag - BusConfigChangesPending[busIndex] = false; + baseConfig = stack.Arg5().Dereference(); + + ConfigureAndInitSpiBus(busIndex, spiDeviceConfig, baseConfig); } // dereference the write and read SpanByte from the arguments @@ -539,6 +553,8 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ uint32_t clockDivValue; uint32_t refFreq; uint32_t realClk; + CLR_RT_HeapBlock *baseConfig = NULL; + SPI_DEVICE_CONFIGURATION *spiDeviceConfig = NULL; // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); @@ -600,7 +616,11 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ if (palSpi->Handle == NULL || BusConfigChangesPending[busIndex]) { // the configuration has not been set yet, or there are pending changes - NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + // compose SPI_DEVICE_CONFIGURATION + // get SpiBaseConfiguration from argument + baseConfig = stack.Arg5().Dereference(); + + ConfigureAndInitSpiBus(busIndex, spiDeviceConfig, baseConfig); } // The divider field of the USART->CLKDIV register is of the following form: From 4383d469ca22a365c448d5fddca1579824cbec91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 4 Oct 2023 14:12:06 +0100 Subject: [PATCH 484/572] Fix implementation of NativeGetBusSpeed (#10) --- .../com_sky_nf_dev_spi_native.cpp | 6 +++--- .../com_sky_nf_dev_spi_native.h | 5 +++-- ...e_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 8 +++++--- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index bf5094d1e6..9b3368fa06 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -33,7 +33,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeReportBusSettingsChanged___VOID__I4, - Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4, + Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration, NULL, NULL, NULL, @@ -45,9 +45,9 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = { "Com.SkyworksInc.NanoFramework.Devices.Spi", - 0x060333BF, + 0xF287AE32, method_lookup, - { 100, 0, 0, 8 } + { 100, 0, 0, 9 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index f6f418e13c..da68c7bfbd 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -50,9 +50,10 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S static const int FIELD___syncLock = 1; static const int FIELD___bufferSingleOperation = 2; - NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); + NANOCLR_NATIVE_DECLARE( + NativeTransfer___VOID__I4__SystemSpanByte__SystemSpanByte__BOOLEAN__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); NANOCLR_NATIVE_DECLARE(NativeReportBusSettingsChanged___VOID__I4); - NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4); + NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); //--// }; diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 44c26aabca..0e3c61d15f 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -543,8 +543,8 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ NANOCLR_NOCLEANUP(); } -HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::NativeGetBusSpeed___I4__I4( - CLR_RT_StackFrame &stack) +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus:: + NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -564,6 +564,8 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ // Gecko SPI bus index is 0 based busIndex = (int8_t)stack.Arg1().NumericByRef().s4 - 1; + spiDeviceConfig = &SpiConfigs[busIndex]; + // get the PAL struct for the SPI bus switch (busIndex) { @@ -618,7 +620,7 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ // the configuration has not been set yet, or there are pending changes // compose SPI_DEVICE_CONFIGURATION // get SpiBaseConfiguration from argument - baseConfig = stack.Arg5().Dereference(); + baseConfig = stack.Arg2().Dereference(); ConfigureAndInitSpiBus(busIndex, spiDeviceConfig, baseConfig); } From 28a03ae49a0a4b5ca7fe882ecefa079f446c60b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 11 Oct 2023 15:29:30 +0100 Subject: [PATCH 485/572] Work CI-CD (#11) [skip ci] --- .github/workflows/skyworks_evb_build.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 0499e61a8f..244e3e8d2e 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -113,7 +113,7 @@ jobs: ${{ github.workspace }}/build/build-info.txt - name: Tag the build - if: ${{ github.event.pull_request.number == 'null' }} + if: ${{ github.event.pull_request.number == null }} uses: actions/github-script@v6 with: script: | From d51448dd193a451b6397e1f09988de6f5b96eb95 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 16 Oct 2023 08:37:08 -0500 Subject: [PATCH 486/572] SKY_EEVB: add Debug CLR build w/ watchdog enabled --- .../SiliconLabs/SKY_EEVB/CMakePresets.json | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index a15a835edf..f9c141c8f3 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -54,6 +54,17 @@ "API_System.Device.UsbStream": "ON" } }, + { + "name": "SKY_EEVB_Watchdog_Debug", + "inherits": [ + "SKY_EEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_EEVB_Watchdog_Debug", + "NF_FEATURE_WATCHDOG": "ON", + } + }, { "name": "SKY_EEVB_Release", "inherits": [ @@ -75,6 +86,12 @@ "displayName": "SKY_EEVB_Debug", "configurePreset": "SKY_EEVB_Debug" }, + { + "inherits": "base-user", + "name": "SKY_EEVB_Watchdog_Debug", + "displayName": "SKY_EEVB_Watchdog_Debug", + "configurePreset": "SKY_EEVB_Watchdog_Debug" + }, { "inherits": "base-user", "name": "SKY_EEVB_Release", From 162f04bf779ed5413a93c9b07569ed1bcd94be9d Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 16 Oct 2023 08:40:35 -0500 Subject: [PATCH 487/572] SKY_EEVB: add Github action for new Debug CLR build w/ watchdog enabled --- .github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 .github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml diff --git a/.github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml b/.github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml new file mode 100644 index 0000000000..e5fd26016b --- /dev/null +++ b/.github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_EEVB_Watchdog_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_EEVB_Watchdog_Debug: + name: Build SKY_EEVB_Watchdog_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_EEVB_Watchdog_Debug' From 32373ec259c4587eec2c68090e8f99b53294f702 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Mon, 16 Oct 2023 08:45:49 -0500 Subject: [PATCH 488/572] SKY_EEVB: fix Debug CLR build w/ watchdog enabled --- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index f9c141c8f3..5db16ff9e1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -62,7 +62,7 @@ "hidden": false, "cacheVariables": { "TARGET_NAME": "SKY_EEVB_Watchdog_Debug", - "NF_FEATURE_WATCHDOG": "ON", + "NF_FEATURE_WATCHDOG": "ON" } }, { From 36d99a4efc41453dfaba87ecd45c8639de7453f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 26 Oct 2023 04:12:42 +0100 Subject: [PATCH 489/572] Move declaration of Skyworks APIs to placeholders --- CMake/Modules/FindNF_NativeAssemblies.cmake | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/CMake/Modules/FindNF_NativeAssemblies.cmake b/CMake/Modules/FindNF_NativeAssemblies.cmake index b406e8d535..c54dc3edfe 100644 --- a/CMake/Modules/FindNF_NativeAssemblies.cmake +++ b/CMake/Modules/FindNF_NativeAssemblies.cmake @@ -32,8 +32,6 @@ option(API_Windows.Storage "option for Windows.Storage") option(API_nanoFramework.Graphics "option for nanoFramework.Graphics") option(API_nanoFramework.Device.Bluetooth "option for nanoFramework.Device.Bluetooth") option(API_System.Device.UsbStream "option for System.Device.UsbStream API") -option(API_Com.SkyworksInc.NanoFramework.Devices.I2c "option for Skyworks I2C API") -option(API_Com.SkyworksInc.NanoFramework.Devices.Spi "option for Skyworks SPI API") # Esp32 only option(API_Hardware.Esp32 "option for Hardware.Esp32") @@ -53,7 +51,8 @@ option(API_Hardware.GiantGecko "option for Hardware.GiantGecko" ################################### # add options for private APIs here - +option(API_Com.SkyworksInc.NanoFramework.Devices.I2c "option for Skyworks I2C API") +option(API_Com.SkyworksInc.NanoFramework.Devices.Spi "option for Skyworks SPI API") ################################### ################################################################# @@ -367,6 +366,12 @@ if(API_Windows.Storage) PerformSettingsForApiEntry("Windows.Storage") endif() +# Interop assemblies +ParseInteropAssemblies() + +################################## +# add parsing of private APIs here + # Com.SkyworksInc.NanoFramework.Devices.I2c if(API_Com.SkyworksInc.NanoFramework.Devices.I2c) ##### API name here (doted name) @@ -379,12 +384,6 @@ if(API_Com.SkyworksInc.NanoFramework.Devices.Spi) PerformSettingsForApiEntry("Com.SkyworksInc.NanoFramework.Devices.Spi") endif() -# Interop assemblies -ParseInteropAssemblies() - -################################## -# add parsing of private APIs here - ################################## # parse the declarations to have new lines and ';' From 5e2c5c5f0c46e6f738e3cfbd1b1fc745511b18df Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 31 Oct 2023 13:04:05 -0500 Subject: [PATCH 490/572] Field programmer: initial target commit --- targets/AzureRTOS/CMakePresets.json | 1 + .../Field_Programmer/.vscode/settings.json | 3 + .../Field_Programmer/CMakeLists.txt | 76 ++++ .../Field_Programmer/CMakePresets.json | 84 +++++ .../SiliconLabs/Field_Programmer/README.md | 28 ++ .../autogen/sl_device_init_clocks.c | 28 ++ .../autogen/sl_event_handler.c | 48 +++ .../autogen/sl_uartdrv_init.c | 91 +++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 ++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 ++ .../autogen/sl_usbd_class_hid_instances.c | 277 ++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 32 ++ .../autogen/sl_usbd_configuration_instances.c | 61 ++++ .../autogen/sl_usbd_configuration_instances.h | 18 + .../SiliconLabs/Field_Programmer/bspconfig.h | 9 + .../Field_Programmer/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 123 +++++++ .../common/Device_BlockStorage.c | 123 +++++++ .../common/tx_initialize_low_level.S | 239 ++++++++++++ .../Field_Programmer/config/pin_config.h | 259 +++++++++++++ .../config/sl_board_control_config.h | 112 ++++++ .../config/sl_device_init_hfrco_config.h | 27 ++ .../config/sl_device_init_hfxo_config.h | 43 +++ .../config/sl_device_init_lfrco_config.h | 34 ++ .../config/sl_device_init_lfxo_config.h | 37 ++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++ .../config/sl_iostream_usart_vcom_config.h | 112 ++++++ .../config/sl_memory_config.h | 13 + .../config/sl_uartdrv_usart_vcom_config.h | 85 +++++ .../config/sl_usbd_class_acm0_config.h | 53 +++ .../config/sl_usbd_class_hid0_config.h | 143 ++++++++ .../config/sl_usbd_class_winusb_config.h | 59 +++ .../config/sl_usbd_config0_config.h | 51 +++ .../config/sl_usbd_core_config.h | 199 ++++++++++ .../config/sl_usbd_device_config.h | 60 +++ .../Field_Programmer/config/uartdrv_config.h | 114 ++++++ .../SiliconLabs/Field_Programmer/launch.json | 83 +++++ .../nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ++++++++++++ .../nanoBooter/efm32gg11b_booter.ld | 235 ++++++++++++ .../Field_Programmer/nanoBooter/main.c | 180 +++++++++ .../nanoBooter/target_board.h.in | 18 + .../Field_Programmer/nanoCLR/CMakeLists.txt | 15 + .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 +++++++++++++ .../nanoCLR/efm32gg11b_CLR.ld | 246 +++++++++++++ .../Field_Programmer/nanoCLR/main.c | 210 +++++++++++ .../Field_Programmer/nanoCLR/nanoHAL.cpp | 8 + .../nanoCLR/target_board.h.in | 18 + .../Field_Programmer/nanoCLR/usb_hid_app.c | 244 +++++++++++++ .../Field_Programmer/target_BlockStorage.c | 19 + .../Field_Programmer/target_BlockStorage.h | 12 + .../target_com_sky_nf_dev_i2c_config.cpp | 26 ++ .../target_com_sky_nf_dev_i2c_config.h | 4 + .../target_com_sky_nf_dev_spi_config.cpp | 48 +++ .../target_com_sky_nf_dev_spi_config.h | 8 + .../Field_Programmer/target_common.c | 27 ++ .../Field_Programmer/target_common.h.in | 52 +++ .../target_nano_gg_adc_config.cpp | 52 +++ .../target_nano_gg_adc_config.h | 9 + .../target_nf_dev_onewire_config.cpp | 8 + .../target_nf_dev_onewire_config.h | 11 + .../Field_Programmer/target_stdio_config.c | 7 + .../Field_Programmer/target_stdio_config.h | 5 + .../target_system_device_adc_config.cpp | 6 + .../target_system_device_adc_config.h | 6 + .../target_system_device_i2c_config.cpp | 32 ++ .../target_system_device_i2c_config.h | 8 + .../target_system_device_pwm_config.cpp | 17 + .../target_system_device_spi_config.cpp | 35 ++ .../target_system_device_spi_config.h | 7 + .../target_system_io_ports_config.cpp | 4 + .../target_system_io_ports_config.h | 5 + .../Field_Programmer/target_tx_user.h | 206 +++++++++++ .../Field_Programmer/target_ux_user.h | 345 ++++++++++++++++++ 75 files changed, 5678 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/.vscode/settings.json create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/README.md create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/bspconfig.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/common/tx_initialize_low_level.S create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_hid0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_winusb_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/Field_Programmer/target_ux_user.h diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 00b15662ee..ba4d11dcc7 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -5,6 +5,7 @@ "SiliconLabs/SKY_EEVB/CMakePresets.json", "SiliconLabs/Si5575_CEVB/CMakePresets.json", "SiliconLabs/STB_Interposer/CMakePresets.json", + "SiliconLabs/Field_Programmer/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/.vscode/settings.json b/targets/AzureRTOS/SiliconLabs/Field_Programmer/.vscode/settings.json new file mode 100644 index 0000000000..cad7657dfa --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cmake.configureOnOpen": false +} \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json new file mode 100644 index 0000000000..a4cb1577d1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json @@ -0,0 +1,84 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "Field_Programmer_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "Field_Programmer", + "TARGET_NAME": "Field_Programmer_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON" + } + }, + { + "name": "Field_Programmer_Release", + "inherits": [ + "Field_Programmer_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "Field_Programmer_Release", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "Field_Programmer_Debug", + "displayName": "Field_Programmer_Debug", + "configurePreset": "Field_Programmer_Debug" + }, + { + "inherits": "base-user", + "name": "Field_Programmer_Release", + "displayName": "Field_Programmer_Release", + "configurePreset": "Field_Programmer_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/README.md b/targets/AzureRTOS/SiliconLabs/Field_Programmer/README.md new file mode 100644 index 0000000000..d5e436cd75 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/README.md @@ -0,0 +1,28 @@ +# Skyworks Field Programmer EVB featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8263237766/Gecko+Field+Programmer + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC <- NOT USED, ADC is disabled + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/bspconfig.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage.c new file mode 100644 index 0000000000..09982097e3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 66}, + + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/launch.json b/targets/AzureRTOS/SiliconLabs/Field_Programmer/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/main.c new file mode 100644 index 0000000000..0787f4a6a5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/main.c @@ -0,0 +1,180 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..d17abebca3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/main.c new file mode 100644 index 0000000000..2b709b5441 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/main.c @@ -0,0 +1,210 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = false; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..5642300661 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +// NOT ENABLED +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +// !ENABLED! +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +// NOT ENABLED +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..9f97bf8736 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 FALSE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 FALSE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.h.in b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..c6b9aca497 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.cpp @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..115d8a0324 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..74d8b5da5b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.h @@ -0,0 +1,11 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6e7b275464 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.h new file mode 100644 index 0000000000..c81f83afe3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +/* + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.h new file mode 100644 index 0000000000..409945557b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From 55c244ddb66427d08e2752714b5ca4cf3ca866a2 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 31 Oct 2023 13:08:03 -0500 Subject: [PATCH 491/572] Field programmer: add build action --- .github/workflows/Build_Field_Programmer_Debug.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 .github/workflows/Build_Field_Programmer_Debug.yaml diff --git a/.github/workflows/Build_Field_Programmer_Debug.yaml b/.github/workflows/Build_Field_Programmer_Debug.yaml new file mode 100644 index 0000000000..6ce2bcd146 --- /dev/null +++ b/.github/workflows/Build_Field_Programmer_Debug.yaml @@ -0,0 +1,11 @@ +name: Build Field_Programmer_Debug + +on: + workflow_dispatch + +jobs: + build_Field_Programmer_Debug: + name: Build Field_Programmer_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Field_Programmer_Debug' From bb891c71f072721931442e4b6b358e08701dc2aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Oct 2023 22:32:45 +0000 Subject: [PATCH 492/572] Work CI-CD - Add job to adjust path length limit. [skip_ci] --- .github/workflows/skyworks_evb_build.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 244e3e8d2e..0f0792fbdc 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -49,7 +49,6 @@ jobs: echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append - - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: @@ -65,6 +64,10 @@ jobs: echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append } + - name: Enable long paths + run: | + New-ItemProperty -Path "HKLM:\SYSTEM\CurrentControlSet\Control\FileSystem" -Name "LongPathsEnabled" -Value 1 -PropertyType DWORD -Force + - name: Rename CMake presets working-directory: ${{ github.workspace }}/config run: | From abe7af89cacb0ad26e58334139f5a550b5d309cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 31 Oct 2023 23:13:17 +0000 Subject: [PATCH 493/572] Add vars to allow long paths on windows builds --- .../AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json index a4cb1577d1..7aff8530bb 100644 --- a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json @@ -15,6 +15,8 @@ ], "hidden": false, "cacheVariables": { + "CMAKE_OBJECT_PATH_MAX": "260", + "CMAKE_OBJECT_NAME_MAX": "250", "TARGET_BOARD": "Field_Programmer", "TARGET_NAME": "Field_Programmer_Debug", "RTOS": "AzureRTOS", From 62249e0ec57568e50cfb4ecb890e8171d510f6e2 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 1 Nov 2023 14:58:15 -0500 Subject: [PATCH 494/572] Field programmer: rename to try to avoid compile errors --- .../Build_Field_Programmer_Debug.yaml | 8 +++---- targets/AzureRTOS/CMakePresets.json | 2 +- .../.vscode/settings.json | 0 .../CMakeLists.txt | 0 .../CMakePresets.json | 24 +++++++++---------- .../README.md | 0 .../autogen/sl_device_init_clocks.c | 0 .../autogen/sl_event_handler.c | 0 .../autogen/sl_uartdrv_init.c | 0 .../autogen/sl_uartdrv_instances.h | 0 .../autogen/sl_usbd_class_cdc_acm_instances.c | 0 .../autogen/sl_usbd_class_cdc_acm_instances.h | 0 .../autogen/sl_usbd_class_hid_instances.c | 0 .../autogen/sl_usbd_class_hid_instances.h | 0 .../autogen/sl_usbd_configuration_instances.c | 0 .../autogen/sl_usbd_configuration_instances.h | 0 .../bspconfig.h | 0 .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../common/tx_initialize_low_level.S | 0 .../config/pin_config.h | 0 .../config/sl_board_control_config.h | 0 .../config/sl_device_init_hfrco_config.h | 0 .../config/sl_device_init_hfxo_config.h | 0 .../config/sl_device_init_lfrco_config.h | 0 .../config/sl_device_init_lfxo_config.h | 0 .../config/sl_iostream_usart_onewire_config.h | 0 .../config/sl_iostream_usart_vcom_config.h | 0 .../config/sl_memory_config.h | 0 .../config/sl_uartdrv_usart_vcom_config.h | 0 .../config/sl_usbd_class_acm0_config.h | 0 .../config/sl_usbd_class_hid0_config.h | 0 .../config/sl_usbd_class_winusb_config.h | 0 .../config/sl_usbd_config0_config.h | 0 .../config/sl_usbd_core_config.h | 0 .../config/sl_usbd_device_config.h | 0 .../config/uartdrv_config.h | 0 .../launch.json | 0 .../nanoBooter/CMakeLists.txt | 0 .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 0 .../nanoBooter/efm32gg11b_booter.ld | 0 .../nanoBooter/main.c | 0 .../nanoBooter/target_board.h.in | 0 .../nanoCLR/CMakeLists.txt | 0 .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 0 .../nanoCLR/efm32gg11b_CLR.ld | 0 .../nanoCLR/main.c | 0 .../nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../nanoCLR/usb_hid_app.c | 0 .../target_BlockStorage.c | 0 .../target_BlockStorage.h | 0 .../target_com_sky_nf_dev_i2c_config.cpp | 0 .../target_com_sky_nf_dev_i2c_config.h | 0 .../target_com_sky_nf_dev_spi_config.cpp | 0 .../target_com_sky_nf_dev_spi_config.h | 0 .../target_common.c | 0 .../target_common.h.in | 0 .../target_nano_gg_adc_config.cpp | 0 .../target_nano_gg_adc_config.h | 0 .../target_nf_dev_onewire_config.cpp | 0 .../target_nf_dev_onewire_config.h | 0 .../target_stdio_config.c | 0 .../target_stdio_config.h | 0 .../target_system_device_adc_config.cpp | 0 .../target_system_device_adc_config.h | 0 .../target_system_device_i2c_config.cpp | 0 .../target_system_device_i2c_config.h | 0 .../target_system_device_pwm_config.cpp | 0 .../target_system_device_spi_config.cpp | 0 .../target_system_device_spi_config.h | 0 .../target_system_io_ports_config.cpp | 0 .../target_system_io_ports_config.h | 0 .../target_tx_user.h | 0 .../target_ux_user.h | 0 76 files changed, 17 insertions(+), 17 deletions(-) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/.vscode/settings.json (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/CMakePresets.json (81%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/README.md (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_device_init_clocks.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_event_handler.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_uartdrv_init.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_uartdrv_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_usbd_class_cdc_acm_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_usbd_class_cdc_acm_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_usbd_class_hid_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_usbd_class_hid_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_usbd_configuration_instances.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/autogen/sl_usbd_configuration_instances.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/bspconfig.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/common/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/common/Device_BlockStorage-DEBUG.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/common/Device_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/common/tx_initialize_low_level.S (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/pin_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_board_control_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_device_init_hfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_device_init_hfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_device_init_lfrco_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_device_init_lfxo_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_iostream_usart_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_iostream_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_memory_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_uartdrv_usart_vcom_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_usbd_class_acm0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_usbd_class_hid0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_usbd_class_winusb_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_usbd_config0_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_usbd_core_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/sl_usbd_device_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/config/uartdrv_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/launch.json (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoBooter/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoBooter/efm32gg11b_booter-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoBooter/efm32gg11b_booter.ld (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoBooter/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoBooter/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/CMakeLists.txt (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/efm32gg11b_CLR-DEBUG.ld (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/efm32gg11b_CLR.ld (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/main.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/nanoHAL.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/target_board.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/nanoCLR/usb_hid_app.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_BlockStorage.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_BlockStorage.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_com_sky_nf_dev_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_com_sky_nf_dev_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_com_sky_nf_dev_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_com_sky_nf_dev_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_common.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_common.h.in (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_nano_gg_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_nano_gg_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_nf_dev_onewire_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_nf_dev_onewire_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_stdio_config.c (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_stdio_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_adc_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_adc_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_i2c_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_i2c_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_pwm_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_spi_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_device_spi_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_io_ports_config.cpp (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_system_io_ports_config.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_tx_user.h (100%) rename targets/AzureRTOS/SiliconLabs/{Field_Programmer => FIELD_PROG}/target_ux_user.h (100%) diff --git a/.github/workflows/Build_Field_Programmer_Debug.yaml b/.github/workflows/Build_Field_Programmer_Debug.yaml index 6ce2bcd146..fbf4ea368e 100644 --- a/.github/workflows/Build_Field_Programmer_Debug.yaml +++ b/.github/workflows/Build_Field_Programmer_Debug.yaml @@ -1,11 +1,11 @@ -name: Build Field_Programmer_Debug +name: Build FIELD_PROG_Debug on: workflow_dispatch jobs: - build_Field_Programmer_Debug: - name: Build Field_Programmer_Debug + build_FIELD_PROG_Debug: + name: Build FIELD_PROG_Debug uses: ./.github/workflows/skyworks_evb_build.yaml with: - targetName: 'Field_Programmer_Debug' + targetName: 'FIELD_PROG_Debug' diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index ba4d11dcc7..1e96946efc 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -5,7 +5,7 @@ "SiliconLabs/SKY_EEVB/CMakePresets.json", "SiliconLabs/Si5575_CEVB/CMakePresets.json", "SiliconLabs/STB_Interposer/CMakePresets.json", - "SiliconLabs/Field_Programmer/CMakePresets.json", + "SiliconLabs/FIELD_PROG/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", "ST/ST_B_L475E_IOT01A/CMakePresets.json" ] diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/.vscode/settings.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/.vscode/settings.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/.vscode/settings.json rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/.vscode/settings.json diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json similarity index 81% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json index 7aff8530bb..860b28ed59 100644 --- a/targets/AzureRTOS/SiliconLabs/Field_Programmer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json @@ -7,7 +7,7 @@ ], "configurePresets": [ { - "name": "Field_Programmer_Debug", + "name": "FIELD_PROG_Debug", "inherits": [ "arm-gcc-cortex-preset", "user-tools-repos", @@ -17,8 +17,8 @@ "cacheVariables": { "CMAKE_OBJECT_PATH_MAX": "260", "CMAKE_OBJECT_NAME_MAX": "250", - "TARGET_BOARD": "Field_Programmer", - "TARGET_NAME": "Field_Programmer_Debug", + "TARGET_BOARD": "FIELD_PROG", + "TARGET_NAME": "FIELD_PROG_Debug", "RTOS": "AzureRTOS", "TARGET_SERIES": "EFM32GG11", "SUPPORT_ANY_BASE_CONVERSION": "OFF", @@ -56,13 +56,13 @@ } }, { - "name": "Field_Programmer_Release", + "name": "FIELD_PROG_Release", "inherits": [ - "Field_Programmer_Debug" + "FIELD_PROG_Debug" ], "hidden": false, "cacheVariables": { - "TARGET_NAME": "Field_Programmer_Release", + "TARGET_NAME": "FIELD_PROG_Release", "NF_BUILD_RTM": "ON", "NF_PROFILE_NEW_ALLOCATIONS": "OFF", "NF_TRACE_MEMORY_STATS": "OFF" @@ -72,15 +72,15 @@ "buildPresets": [ { "inherits": "base-user", - "name": "Field_Programmer_Debug", - "displayName": "Field_Programmer_Debug", - "configurePreset": "Field_Programmer_Debug" + "name": "FIELD_PROG_Debug", + "displayName": "FIELD_PROG_Debug", + "configurePreset": "FIELD_PROG_Debug" }, { "inherits": "base-user", - "name": "Field_Programmer_Release", - "displayName": "Field_Programmer_Release", - "configurePreset": "Field_Programmer_Release" + "name": "FIELD_PROG_Release", + "displayName": "FIELD_PROG_Release", + "configurePreset": "FIELD_PROG_Release" } ] } diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/README.md b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/README.md similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/README.md rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/README.md diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_device_init_clocks.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_device_init_clocks.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_device_init_clocks.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_event_handler.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_event_handler.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_event_handler.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_init.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_init.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_init.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_uartdrv_instances.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_uartdrv_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_cdc_acm_instances.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_cdc_acm_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_class_hid_instances.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_class_hid_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/autogen/sl_usbd_configuration_instances.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/autogen/sl_usbd_configuration_instances.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/bspconfig.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/bspconfig.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/bspconfig.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/bspconfig.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/common/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage-DEBUG.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage-DEBUG.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/common/Device_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/tx_initialize_low_level.S similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/common/tx_initialize_low_level.S rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/tx_initialize_low_level.S diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/pin_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/pin_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/pin_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_board_control_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_board_control_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_board_control_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfrco_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_hfxo_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_hfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfrco_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfrco_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfrco_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfxo_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_device_init_lfxo_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_device_init_lfxo_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_iostream_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_iostream_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_memory_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_memory_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_memory_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_uartdrv_usart_vcom_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_uartdrv_usart_vcom_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_uartdrv_usart_vcom_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_acm0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_acm0_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_acm0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_hid0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_hid0_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_hid0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_winusb_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_class_winusb_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_class_winusb_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_config0_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_config0_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_config0_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_core_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_core_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_core_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_device_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/sl_usbd_device_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/sl_usbd_device_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/uartdrv_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/config/uartdrv_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/config/uartdrv_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/launch.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/launch.json similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/launch.json rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/launch.json diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/efm32gg11b_booter.ld rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/efm32gg11b_booter.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/main.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoBooter/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/CMakeLists.txt similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/CMakeLists.txt rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/CMakeLists.txt diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR-DEBUG.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR-DEBUG.ld rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR-DEBUG.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/efm32gg11b_CLR.ld rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/main.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/nanoHAL.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/nanoHAL.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/target_board.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/target_board.h.in rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/target_board.h.in diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/usb_hid_app.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/nanoCLR/usb_hid_app.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/usb_hid_app.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_BlockStorage.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_BlockStorage.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_com_sky_nf_dev_spi_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.h.in b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.h.in similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_common.h.in rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_common.h.in diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nano_gg_adc_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nano_gg_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_nf_dev_onewire_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.c similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.c rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.c diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_stdio_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_stdio_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_adc_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_adc_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_i2c_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_i2c_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_pwm_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_pwm_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_pwm_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_device_spi_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.cpp similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.cpp rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.cpp diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_system_io_ports_config.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_io_ports_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_tx_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_tx_user.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_tx_user.h diff --git a/targets/AzureRTOS/SiliconLabs/Field_Programmer/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_ux_user.h similarity index 100% rename from targets/AzureRTOS/SiliconLabs/Field_Programmer/target_ux_user.h rename to targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_ux_user.h From 7dee6c8e7c3b39161fb1672a6ea75648ac39513c Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 1 Nov 2023 15:13:33 -0500 Subject: [PATCH 495/572] Field programmer: fix for SPI config --- .../FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp index 5642300661..68c45e5fa6 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp @@ -5,6 +5,7 @@ #include +/* ////////// // SPI0 // ////////// @@ -19,6 +20,8 @@ // NOT ENABLED INIT_SPI_CONFIG(0, 0, 0, 0, 0) +*/ + ////////// // SPI1 // ////////// @@ -33,6 +36,7 @@ INIT_SPI_CONFIG(0, 0, 0, 0, 0) // !ENABLED! INIT_SPI_CONFIG(1, 1, 1, 1, 1) +/* ////////// // SPI2 // ////////// @@ -45,4 +49,6 @@ INIT_SPI_CONFIG(1, 1, 1, 1, 1) // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet // NOT ENABLED -INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file +INIT_SPI_CONFIG(2, 1, 1, 1, 1) + +*/ \ No newline at end of file From 7d5d206f21e5912c313d2ad86e5582d47ade8d28 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 1 Nov 2023 15:27:45 -0500 Subject: [PATCH 496/572] Field programmer: fix for SPI config --- .../SiliconLabs/FIELD_PROG/target_system_device_spi_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h index 409945557b..77281d59a9 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_system_device_spi_config.h @@ -4,4 +4,4 @@ // #define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE +#define GECKO_USE_SPI2 FALSE From 1ca85c9be084815987e2f9fea2f16479db694328 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 2 Nov 2023 09:30:12 +0000 Subject: [PATCH 497/572] Revert "Work CI-CD" This reverts commit bb891c71f072721931442e4b6b358e08701dc2aa. --- .github/workflows/skyworks_evb_build.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 0f0792fbdc..244e3e8d2e 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -49,6 +49,7 @@ jobs: echo "SRECORD_PATH=$srecPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: @@ -64,10 +65,6 @@ jobs: echo "ARM_NONE_EABI_GCC_PATH=$fixedPath" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append } - - name: Enable long paths - run: | - New-ItemProperty -Path "HKLM:\SYSTEM\CurrentControlSet\Control\FileSystem" -Name "LongPathsEnabled" -Value 1 -PropertyType DWORD -Force - - name: Rename CMake presets working-directory: ${{ github.workspace }}/config run: | From 6e20d81010a1fe17dc4d800ee32dff990bf0c1fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 2 Nov 2023 09:31:04 +0000 Subject: [PATCH 498/572] Revert "Add vars to allow long paths on windows builds" This reverts commit abe7af89cacb0ad26e58334139f5a550b5d309cf. --- targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json index 860b28ed59..9de514a821 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json @@ -15,8 +15,6 @@ ], "hidden": false, "cacheVariables": { - "CMAKE_OBJECT_PATH_MAX": "260", - "CMAKE_OBJECT_NAME_MAX": "250", "TARGET_BOARD": "FIELD_PROG", "TARGET_NAME": "FIELD_PROG_Debug", "RTOS": "AzureRTOS", From a895ec791b02dd10bf513b16bfbf44492168694e Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Thu, 2 Nov 2023 13:35:44 -0500 Subject: [PATCH 499/572] Field programmer: cleanup SPI config; comment others --- .../target_com_sky_nf_dev_spi_config.cpp | 45 +++---------------- .../target_com_sky_nf_dev_spi_config.h | 5 +-- .../target_com_sky_nf_dev_spi_config.cpp | 3 ++ .../target_com_sky_nf_dev_spi_config.cpp | 3 ++ .../target_com_sky_nf_dev_spi_config.cpp | 3 ++ 5 files changed, 17 insertions(+), 42 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp index 68c45e5fa6..a8b2041199 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.cpp @@ -5,50 +5,17 @@ #include -/* -////////// -// SPI0 // -////////// +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. -// USART0 -// SCK: PE12 -// MOSI: PE10 -// MISO: PE11 -// CS: PE13 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -// NOT ENABLED -INIT_SPI_CONFIG(0, 0, 0, 0, 0) - -*/ +////////////////// +// SPI1 (USART1)// +////////////////// -////////// -// SPI1 // -////////// - -// USART1 // SCK: PD2 // MOSI: PD0 // MISO: PD1 // CS: PD3 // EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet -// !ENABLED! -INIT_SPI_CONFIG(1, 1, 1, 1, 1) - -/* -////////// -// SPI2 // -////////// - -// USART2 -// SCK: PB5 -// MOSI: PB3 -// MISO: PB4 -// CS: PB6 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -// NOT ENABLED -INIT_SPI_CONFIG(2, 1, 1, 1, 1) - -*/ \ No newline at end of file +INIT_SPI_CONFIG(1, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h index 9f97bf8736..e9226d5dfb 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_com_sky_nf_dev_spi_config.h @@ -3,6 +3,5 @@ // See LICENSE file in the project root for full license information. // -#define GECKO_USE_SPI0 FALSE -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 FALSE \ No newline at end of file +// DUT SPI on USART1 +#define GECKO_USE_SPI1 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp index 4a303f4f39..5adbeff229 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_com_sky_nf_dev_spi_config.cpp @@ -5,6 +5,9 @@ #include +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + ////////// // SPI1 // ////////// diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp index 147cb8f2df..6c5b724749 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_com_sky_nf_dev_spi_config.cpp @@ -5,6 +5,9 @@ #include +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + ////////// // SPI0 // ////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp index 147cb8f2df..6c5b724749 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp @@ -5,6 +5,9 @@ #include +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + ////////// // SPI0 // ////////// From 3bcf29bad91711526e50d22cef5e19d64c16c881 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 7 Nov 2023 18:16:52 +0000 Subject: [PATCH 500/572] Add dummy implementation of sli_sleeptimer_hal_power_manager_integration_init - Required after Gecko SDK 4.3.2 --- targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c b/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c index 5a21d6d920..e3a5edf68c 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c +++ b/targets/AzureRTOS/SiliconLabs/_common/sl_sleeptimer_.c @@ -14,3 +14,10 @@ void sli_sleeptimer_set_pm_em_requirement(void) { } #endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +void sli_sleeptimer_hal_power_manager_integration_init(void) +{ +} +#endif From 43386f500a02494244526680405ae4a8d932cbff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 7 Nov 2023 19:23:23 +0000 Subject: [PATCH 501/572] USB device now re-enumerates on CLR boot --- targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c index a8742b5c7b..a9b9ad67ef 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c +++ b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c @@ -40,6 +40,7 @@ #include "sli_usbd_driver.h" #include +#include /******************************************************************************************************** ******************************************************************************************************** @@ -5542,6 +5543,8 @@ void sli_usbd_core_task_handler(void) sl_status_t status; #if SL_USBD_AUTO_START_USB_DEVICE == 1 + sl_usbd_core_stop_device(); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(50)); sl_usbd_core_start_device(); #endif From 0c8544d1112791847c244d32fbe11132402d4936 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Fri, 10 Nov 2023 09:27:44 -0600 Subject: [PATCH 502/572] SKY_EEVB: add System.IO.Hashing --- .../SiliconLabs/SKY_EEVB/CMakePresets.json | 79 ++++++++++--------- 1 file changed, 40 insertions(+), 39 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 5db16ff9e1..1cdfa4aa6f 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -14,45 +14,46 @@ "user-prefs" ], "hidden": false, - "cacheVariables": { - "TARGET_BOARD": "SKY_EEVB", - "TARGET_NAME": "SKY_EEVB_Debug", - "RTOS": "AzureRTOS", - "TARGET_SERIES": "EFM32GG11", - "SUPPORT_ANY_BASE_CONVERSION": "OFF", - "NF_FEATURE_RTC": "ON", - "NF_FEATURE_DEBUGGER": "ON", - "NF_FEATURE_HAS_SDCARD": "OFF", - "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", - "NF_CLR_NO_IL_INLINE": "ON", - "API_System.Math": "ON", - "API_Hardware.GiantGecko": "ON", - "API_System.Device.Gpio": "ON", - "API_System.Device.Pwm": "ON", - "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", - "API_System.Device.Dac": "OFF", - "API_System.Net": "OFF", - "API_nanoFramework.Device.OneWire": "ON", - "API_nanoFramework.Devices.Can": "OFF", - "API_nanoFramework.ResourceManager": "ON", - "API_nanoFramework.System.Collections": "ON", - "API_nanoFramework.System.Text": "ON", - "API_nanoFramework.GiantGecko.Adc": "ON", - "API_Windows.Storage": "OFF", - "API_nanoFramework.Graphics": "OFF", - "TARGET_SERIAL_BAUDRATE": "921600", - "HAL_WP_USE_SERIAL": "OFF", - "HAL_WP_USE_USB_CDC": "ON", - "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", - "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON" - } + "cacheVariables": { + "TARGET_BOARD": "SKY_EEVB", + "TARGET_NAME": "SKY_EEVB_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", + "NF_CLR_NO_IL_INLINE": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "ON", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_System.IO.Hashing": "ON" + } }, { "name": "SKY_EEVB_Watchdog_Debug", From 165dcf8c2e10739b6bd966b6cc48c858acf3aa58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Nov 2023 18:53:32 +0000 Subject: [PATCH 503/572] Add extra comment about UART config for 1-Wire --- .../SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h | 2 ++ targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 2 +- .../SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h | 2 ++ .../SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h | 2 ++ .../SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h | 2 ++ 5 files changed, 9 insertions(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h index 74d8b5da5b..b5d0ffb355 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/target_nf_dev_onewire_config.h @@ -9,3 +9,5 @@ // enable USART0 #define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 1cdfa4aa6f..9a6d2ed81e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -52,7 +52,7 @@ "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON", - "API_System.IO.Hashing": "ON" + "API_nanoFramework.System.IO.Hashing": "ON" } }, { diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h index 74d8b5da5b..b5d0ffb355 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/target_nf_dev_onewire_config.h @@ -9,3 +9,5 @@ // enable USART0 #define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h index 74d8b5da5b..b5d0ffb355 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/target_nf_dev_onewire_config.h @@ -9,3 +9,5 @@ // enable USART0 #define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h index 74d8b5da5b..b5d0ffb355 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h @@ -9,3 +9,5 @@ // enable USART0 #define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h From e25ccb6367f8c0cf44432c22ecf3d411cedeaa89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 10 Nov 2023 18:53:49 +0000 Subject: [PATCH 504/572] Add extra comment about UART config for 1-Wire --- .../SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h index 2c21c90446..6a71f5dc7e 100644 --- a/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h +++ b/targets/AzureRTOS/SiliconLabs/SL_STK3701A/target_nf_dev_onewire_config.h @@ -9,3 +9,5 @@ // enable USART0 #define GECKO_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h From f95dd99162e3825f82baac82f45cf9c3745413af Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 28 Nov 2023 13:31:47 -0600 Subject: [PATCH 505/572] Add API_System.IO.Hashing to other EVB targets: required for latest base firmware and PC USB driver --- targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json | 3 ++- targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json | 3 ++- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json index 9de514a821..bc3f8c59ae 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json @@ -50,7 +50,8 @@ "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON" + "API_System.Device.UsbStream": "ON", + "API_System.IO.Hashing": "ON" } }, { diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index f466f129b3..2964a75e82 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -50,7 +50,8 @@ "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON" + "API_System.Device.UsbStream": "ON", + "API_System.IO.Hashing": "ON" } }, { diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index fcdc3c71a8..bfbdc55487 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -50,7 +50,8 @@ "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON" + "API_System.Device.UsbStream": "ON", + "API_System.IO.Hashing": "ON" } }, { From 9c9473dbb856c2dae6fb75644fa59eedf530f44a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 28 Nov 2023 13:55:35 -0600 Subject: [PATCH 506/572] Add API_nanoFramework.System.IO.Hashing to other EVB targets: required for latest base firmware and PC USB driver (fix for previous commit) --- targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json | 2 +- targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json | 2 +- targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json index bc3f8c59ae..31167607ee 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json @@ -51,7 +51,7 @@ "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON", - "API_System.IO.Hashing": "ON" + "API_nanoFramework.System.IO.Hashing": "ON" } }, { diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index 2964a75e82..21e007296b 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -51,7 +51,7 @@ "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON", - "API_System.IO.Hashing": "ON" + "API_nanoFramework.System.IO.Hashing": "ON" } }, { diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json index bfbdc55487..b35770bdc7 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json @@ -51,7 +51,7 @@ "API_System.Device.I2c": "OFF", "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", "API_System.Device.UsbStream": "ON", - "API_System.IO.Hashing": "ON" + "API_nanoFramework.System.IO.Hashing": "ON" } }, { From e45c43c3cb2112f40c7083acce8f0efeb3326781 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 21 Dec 2023 21:25:44 +0000 Subject: [PATCH 507/572] Work CI-CD - Update gcc version. --- .github/workflows/skyworks_evb_build.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 244e3e8d2e..7862cd84cf 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -53,7 +53,7 @@ jobs: - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: - release: '12.3.Rel1' + release: '13.2.Rel1' - name: Tweak GCC path run: | From b9071705b72507347c83afd9e3e7002f17d19881 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 21 Dec 2023 21:29:03 +0000 Subject: [PATCH 508/572] Increase block size for CLR region in release flavour --- .../SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c | 6 +++--- .../SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c index 09982097e3..e4792d9bb0 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/common/Device_BlockStorage.c @@ -13,10 +13,10 @@ const BlockRange BlockRange1[] = { {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 66}, + {BlockRange_BLOCKTYPE_CODE, 12, 67}, - // 00043000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld index d17abebca3..75f91c7370 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/efm32gg11b_CLR.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 653fba5cfbdf70bc30d9399bf6c438bedfe71fc3 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Thu, 4 Jan 2024 11:12:04 -0600 Subject: [PATCH 509/572] Add Si5400_CEVB target --- targets/AzureRTOS/CMakePresets.json | 1 + .../SiliconLabs/Si5400_CEVB/CMakeLists.txt | 76 ++++ .../SiliconLabs/Si5400_CEVB/CMakePresets.json | 85 +++++ .../SiliconLabs/Si5400_CEVB/README.md | 28 ++ .../autogen/sl_device_init_clocks.c | 28 ++ .../Si5400_CEVB/autogen/sl_event_handler.c | 48 +++ .../Si5400_CEVB/autogen/sl_uartdrv_init.c | 91 +++++ .../autogen/sl_uartdrv_instances.h | 35 ++ .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 ++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 ++ .../autogen/sl_usbd_class_hid_instances.c | 277 ++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 32 ++ .../autogen/sl_usbd_configuration_instances.c | 61 ++++ .../autogen/sl_usbd_configuration_instances.h | 18 + .../SiliconLabs/Si5400_CEVB/bspconfig.h | 9 + .../Si5400_CEVB/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 123 +++++++ .../Si5400_CEVB/common/Device_BlockStorage.c | 123 +++++++ .../common/tx_initialize_low_level.S | 239 ++++++++++++ .../Si5400_CEVB/config/pin_config.h | 259 +++++++++++++ .../config/sl_board_control_config.h | 112 ++++++ .../config/sl_device_init_hfrco_config.h | 27 ++ .../config/sl_device_init_hfxo_config.h | 43 +++ .../config/sl_device_init_lfrco_config.h | 34 ++ .../config/sl_device_init_lfxo_config.h | 37 ++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++ .../config/sl_iostream_usart_vcom_config.h | 112 ++++++ .../Si5400_CEVB/config/sl_memory_config.h | 13 + .../config/sl_uartdrv_usart_vcom_config.h | 85 +++++ .../config/sl_usbd_class_acm0_config.h | 53 +++ .../config/sl_usbd_class_hid0_config.h | 143 ++++++++ .../config/sl_usbd_class_winusb_config.h | 59 +++ .../config/sl_usbd_config0_config.h | 51 +++ .../Si5400_CEVB/config/sl_usbd_core_config.h | 199 ++++++++++ .../config/sl_usbd_device_config.h | 60 +++ .../Si5400_CEVB/config/uartdrv_config.h | 114 ++++++ .../SiliconLabs/Si5400_CEVB/launch.json | 83 +++++ .../Si5400_CEVB/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ++++++++++++ .../nanoBooter/efm32gg11b_booter.ld | 235 ++++++++++++ .../SiliconLabs/Si5400_CEVB/nanoBooter/main.c | 180 +++++++++ .../Si5400_CEVB/nanoBooter/target_board.h.in | 18 + .../Si5400_CEVB/nanoCLR/CMakeLists.txt | 15 + .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 +++++++++++++ .../Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld | 246 +++++++++++++ .../SiliconLabs/Si5400_CEVB/nanoCLR/main.c | 210 +++++++++++ .../Si5400_CEVB/nanoCLR/nanoHAL.cpp | 8 + .../Si5400_CEVB/nanoCLR/target_board.h.in | 18 + .../Si5400_CEVB/nanoCLR/usb_hid_app.c | 244 +++++++++++++ .../Si5400_CEVB/target_BlockStorage.c | 19 + .../Si5400_CEVB/target_BlockStorage.h | 12 + .../target_com_sky_nf_dev_i2c_config.cpp | 26 ++ .../target_com_sky_nf_dev_i2c_config.h | 4 + .../target_com_sky_nf_dev_spi_config.cpp | 48 +++ .../target_com_sky_nf_dev_spi_config.h | 8 + .../SiliconLabs/Si5400_CEVB/target_common.c | 27 ++ .../Si5400_CEVB/target_common.h.in | 52 +++ .../Si5400_CEVB/target_nano_gg_adc_config.cpp | 52 +++ .../Si5400_CEVB/target_nano_gg_adc_config.h | 9 + .../target_nf_dev_onewire_config.cpp | 8 + .../target_nf_dev_onewire_config.h | 13 + .../Si5400_CEVB/target_stdio_config.c | 7 + .../Si5400_CEVB/target_stdio_config.h | 5 + .../target_system_device_adc_config.cpp | 6 + .../target_system_device_adc_config.h | 6 + .../target_system_device_i2c_config.cpp | 32 ++ .../target_system_device_i2c_config.h | 8 + .../target_system_device_pwm_config.cpp | 17 + .../target_system_device_spi_config.cpp | 35 ++ .../target_system_device_spi_config.h | 7 + .../target_system_io_ports_config.cpp | 4 + .../target_system_io_ports_config.h | 5 + .../SiliconLabs/Si5400_CEVB/target_tx_user.h | 206 +++++++++++ .../SiliconLabs/Si5400_CEVB/target_ux_user.h | 345 ++++++++++++++++++ 74 files changed, 5678 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 1e96946efc..966e8655b2 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -4,6 +4,7 @@ "SiliconLabs/SL_STK3701A/CMakePresets.json", "SiliconLabs/SKY_EEVB/CMakePresets.json", "SiliconLabs/Si5575_CEVB/CMakePresets.json", + "SiliconLabs/Si5400_CEVB/CMakePresets.json", "SiliconLabs/STB_Interposer/CMakePresets.json", "SiliconLabs/FIELD_PROG/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json new file mode 100644 index 0000000000..b9f6e1728f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json @@ -0,0 +1,85 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "Si5400_CEVB_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "Si5400_CEVB", + "TARGET_NAME": "Si5400_CEVB_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_nanoFramework.System.IO.Hashing": "ON" + } + }, + { + "name": "Si5400_CEVB_Release", + "inherits": [ + "Si5400_CEVB_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "Si5400_CEVB_Release", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "Si5400_CEVB_Debug", + "displayName": "Si5400_CEVB_Debug", + "configurePreset": "Si5400_CEVB_Debug" + }, + { + "inherits": "base-user", + "name": "Si5400_CEVB_Release", + "displayName": "Si5400_CEVB_Release", + "configurePreset": "Si5400_CEVB_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md new file mode 100644 index 0000000000..c35099a766 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md @@ -0,0 +1,28 @@ +# Skyworks Si5400 CEVB featuring SiLabs EFM32 Giant Gecko GG11 + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8175353962/Si5400+CEVB+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c new file mode 100644 index 0000000000..09982097e3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 66}, + + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c new file mode 100644 index 0000000000..0787f4a6a5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c @@ -0,0 +1,180 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..d17abebca3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c new file mode 100644 index 0000000000..2b709b5441 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c @@ -0,0 +1,210 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = false; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..6c5b724749 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..bdfea3503d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..51d7628e5a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on Si5400 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..03d414a5c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on Si5400 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b5d0ffb355 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6e7b275464 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h new file mode 100644 index 0000000000..c81f83afe3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +/* + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h new file mode 100644 index 0000000000..409945557b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From 59f8a33a7c6edd4362e5d01971975b2cd3f11414 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Thu, 4 Jan 2024 11:15:23 -0600 Subject: [PATCH 510/572] Add Si5400_CEVB build actions --- .github/workflows/Build_Si5400_CEVB_Debug.yaml | 11 +++++++++++ .github/workflows/Build_Si5400_CEVB_Release.yaml | 11 +++++++++++ 2 files changed, 22 insertions(+) create mode 100644 .github/workflows/Build_Si5400_CEVB_Debug.yaml create mode 100644 .github/workflows/Build_Si5400_CEVB_Release.yaml diff --git a/.github/workflows/Build_Si5400_CEVB_Debug.yaml b/.github/workflows/Build_Si5400_CEVB_Debug.yaml new file mode 100644 index 0000000000..3069ccc16b --- /dev/null +++ b/.github/workflows/Build_Si5400_CEVB_Debug.yaml @@ -0,0 +1,11 @@ +name: Build Si5400_CEVB_Debug + +on: + workflow_dispatch + +jobs: + build_Si5400_CEVB_Debug: + name: Build Si5400_CEVB_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5400_CEVB_Debug' diff --git a/.github/workflows/Build_Si5400_CEVB_Release.yaml b/.github/workflows/Build_Si5400_CEVB_Release.yaml new file mode 100644 index 0000000000..d4d9aafb53 --- /dev/null +++ b/.github/workflows/Build_Si5400_CEVB_Release.yaml @@ -0,0 +1,11 @@ +name: Build Si5400_CEVB_Release + +on: + workflow_dispatch + +jobs: + build_Si5400_CEVB_Release: + name: Build Si5400_CEVB_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'Si5400_CEVB_Release' From 0310111c2095edea73899b42c54b637d75cfb045 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 11 Jan 2024 11:26:49 +0000 Subject: [PATCH 511/572] Add support for hardware TRNG --- CMake/Modules/FindGecko_SDK.cmake | 5 ++ .../SiliconLabs/_nanoCLR/CMakeLists.txt | 3 ++ .../SiliconLabs/_nanoCLR/targetRandom.cpp | 47 +++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 667ec83127..42993d59a6 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -47,6 +47,8 @@ list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/slee list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/emdrv/uartdrv/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/inc) list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/platform/security/sl_component/sl_psa_driver/inc) +list(APPEND Gecko_SDK_INCLUDE_DIRS ${gecko_sdk_SOURCE_DIR}/util/third_party/mbedtls/include) if(GECKO_FEATURE_USBD_HID OR HAL_WP_USE_USB_CDC OR @@ -127,6 +129,7 @@ set(gecko_sdk_srcs sl_event_handler.c sl_board_default_init_stub.c sl_i2cspm_init.c + sli_crypto_trng_driver.c # candidate for replacement with RTOS friendly version sl_i2cspm.c sl_string.c @@ -224,6 +227,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") ${gecko_sdk_SOURCE_DIR}/platform/service/sleeptimer/src ${gecko_sdk_SOURCE_DIR}/platform/service/system/src ${gecko_sdk_SOURCE_DIR}/platform/service/udelay/src + ${gecko_sdk_SOURCE_DIR}/platform/security/sl_component/sl_psa_driver/src ${gecko_sdk_SOURCE_DIR}/platform/driver/i2cspm/src ${gecko_sdk_SOURCE_DIR}/util/silicon_labs/silabs_core/memory_manager @@ -303,6 +307,7 @@ macro(nf_add_gecko_sdk) nf_set_compile_options(TARGET ${LIB_NAME} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS ${NFGCKSDK_EXTRA_COMPILE_DEFINITIONS} BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) + nf_set_compile_definitions(TARGET ${LIB_NAME} EXTRA_COMPILE_DEFINITIONS MBEDTLS_ENTROPY_HARDWARE_ALT BUILD_TARGET ${NFGCKSDK_BUILD_TARGET}) # add compile definitions required for WinUSB if(GECKO_FEATURE_USBD_WINUSB) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt index b8a66f3f18..28aa206190 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/CMakeLists.txt @@ -14,6 +14,9 @@ if(HAL_USE_WDG_OPTION) list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Watchdog.c) endif() +# for the moment, assume all Gecko MCUs we support have a TRNG +list(APPEND TARGET_AZURERTOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/targetRandom.cpp) + # make var global set(TARGET_AZURERTOS_NANOCLR_SOURCES ${TARGET_AZURERTOS_NANOCLR_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp new file mode 100644 index 0000000000..b80ceeb883 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp @@ -0,0 +1,47 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// +#include "Core.h" +#include +#include + +void CLR_RT_Random::Initialize() +{ + // no need to do anything here +} + +void CLR_RT_Random::Initialize(int seed) +{ + (void)seed; + + // no need to do anything here +} + +uint32_t CLR_RT_Random::Next() +{ + uint32_t rand; + size_t outLength; + + sli_crypto_trng_get_random((unsigned char *)&rand, sizeof(rand), &outLength); + + return rand; +} + +double CLR_RT_Random::NextDouble() +{ + uint32_t rand; + size_t outLength; + + sli_crypto_trng_get_random((unsigned char *)&rand, sizeof(rand), &outLength); + + // the hardware generator returns a value between 0 - 0xFFFFFFFF + return ((double)rand) / ((double)0xFFFFFFFF); +} + +void CLR_RT_Random::NextBytes(unsigned char *buffer, unsigned int count) +{ + size_t outLength; + + sli_crypto_trng_get_random(buffer, count, &outLength); +} From 65d01c35d1bad95af523e2f8d6ed314073e1939c Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 15 Jan 2024 16:24:29 +0000 Subject: [PATCH 512/572] Update github action versions (#2867) ***NO_CI*** --- .github/workflows/devcontainer-all.yaml | 8 ++++---- .github/workflows/devcontainer-azurertos.yaml | 8 ++++---- .github/workflows/devcontainer-chibios.yaml | 8 ++++---- .github/workflows/devcontainer-esp32.yml | 8 ++++---- .github/workflows/devcontainer-ti.yaml | 8 ++++---- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/.github/workflows/devcontainer-all.yaml b/.github/workflows/devcontainer-all.yaml index 18ed7639da..4f58abe8ad 100644 --- a/.github/workflows/devcontainer-all.yaml +++ b/.github/workflows/devcontainer-all.yaml @@ -23,7 +23,7 @@ jobs: steps: - name: Checkout Repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get container version run: | @@ -34,17 +34,17 @@ jobs: shell: pwsh - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v2 + uses: docker/setup-buildx-action@v3 - name: Login to GitHub Container Registry - uses: docker/login-action@v2 + uses: docker/login-action@v3 with: registry: ghcr.io username: ${{ github.repository_owner }} password: ${{ secrets.CONTAINER_BUILD_TOKEN }} - name: Build and Push Docker Image - uses: docker/build-push-action@v4 + uses: docker/build-push-action@v5 with: file: ${{ env.GCR_FILE }} push: true # Will only build if this is not here diff --git a/.github/workflows/devcontainer-azurertos.yaml b/.github/workflows/devcontainer-azurertos.yaml index 98990bd989..a7bbd3256a 100644 --- a/.github/workflows/devcontainer-azurertos.yaml +++ b/.github/workflows/devcontainer-azurertos.yaml @@ -23,7 +23,7 @@ jobs: steps: - name: Checkout Repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get container version run: | @@ -34,17 +34,17 @@ jobs: shell: pwsh - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v2 + uses: docker/setup-buildx-action@v3 - name: Login to GitHub Container Registry - uses: docker/login-action@v2 + uses: docker/login-action@v3 with: registry: ghcr.io username: ${{ github.repository_owner }} password: ${{ secrets.CONTAINER_BUILD_TOKEN }} - name: Build and Push Docker Image - uses: docker/build-push-action@v4 + uses: docker/build-push-action@v5 with: file: ${{ env.GCR_FILE }} push: true # Will only build if this is not here diff --git a/.github/workflows/devcontainer-chibios.yaml b/.github/workflows/devcontainer-chibios.yaml index ac6058bf74..ba220c5562 100644 --- a/.github/workflows/devcontainer-chibios.yaml +++ b/.github/workflows/devcontainer-chibios.yaml @@ -23,7 +23,7 @@ jobs: steps: - name: Checkout Repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get container version run: | @@ -34,17 +34,17 @@ jobs: shell: pwsh - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v2 + uses: docker/setup-buildx-action@v3 - name: Login to GitHub Container Registry - uses: docker/login-action@v2 + uses: docker/login-action@v3 with: registry: ghcr.io username: ${{ github.repository_owner }} password: ${{ secrets.CONTAINER_BUILD_TOKEN }} - name: Build and Push Docker Image - uses: docker/build-push-action@v4 + uses: docker/build-push-action@v5 with: file: ${{ env.GCR_FILE }} push: true # Will only build if this is not here diff --git a/.github/workflows/devcontainer-esp32.yml b/.github/workflows/devcontainer-esp32.yml index beec2de4dd..c904c8623c 100644 --- a/.github/workflows/devcontainer-esp32.yml +++ b/.github/workflows/devcontainer-esp32.yml @@ -23,7 +23,7 @@ jobs: steps: - name: Checkout Repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get container version run: | @@ -34,17 +34,17 @@ jobs: shell: pwsh - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v2 + uses: docker/setup-buildx-action@v3 - name: Login to GitHub Container Registry - uses: docker/login-action@v2 + uses: docker/login-action@v3 with: registry: ghcr.io username: ${{ github.repository_owner }} password: ${{ secrets.CONTAINER_BUILD_TOKEN }} - name: Build and Push Docker Image - uses: docker/build-push-action@v4 + uses: docker/build-push-action@v5 with: file: ${{ env.GCR_FILE }} push: true # Will only build if this is not here diff --git a/.github/workflows/devcontainer-ti.yaml b/.github/workflows/devcontainer-ti.yaml index 3c935a1ea7..2b483ad17a 100644 --- a/.github/workflows/devcontainer-ti.yaml +++ b/.github/workflows/devcontainer-ti.yaml @@ -23,7 +23,7 @@ jobs: steps: - name: Checkout Repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get container version run: | @@ -34,17 +34,17 @@ jobs: shell: pwsh - name: Set up Docker Buildx - uses: docker/setup-buildx-action@v2 + uses: docker/setup-buildx-action@v3 - name: Login to GitHub Container Registry - uses: docker/login-action@v2 + uses: docker/login-action@v3 with: registry: ghcr.io username: ${{ github.repository_owner }} password: ${{ secrets.CONTAINER_BUILD_TOKEN }} - name: Build and Push Docker Image - uses: docker/build-push-action@v4 + uses: docker/build-push-action@v5 with: file: ${{ env.GCR_FILE }} push: true # Will only build if this is not here From a5266e456b791186ae4d0281d748e3fb5d9fd4fe Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 15 Jan 2024 23:53:19 +0000 Subject: [PATCH 513/572] Code style fixes ***NO_CI*** --- ...orkInformation_WirelessAPConfiguration.cpp | 267 ++++++++++-------- 1 file changed, 150 insertions(+), 117 deletions(-) diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp index 972c2c9cdf..d3370423f1 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp @@ -6,50 +6,57 @@ #include "sys_net_native.h" - -HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::GetWirelessAPConfigurationCount___STATIC__I4( CLR_RT_StackFrame& stack ) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: + GetWirelessAPConfigurationCount___STATIC__I4(CLR_RT_StackFrame &stack) { #ifdef PLATFORM_ESP32 - NATIVE_PROFILE_CLR_NETWORK(); + NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); // grab the count right from the structure - stack.SetResult_I4(g_TargetConfiguration.WirelessAPConfigs->Count); + stack.SetResult_I4(g_TargetConfiguration.WirelessAPConfigs->Count); NANOCLR_NOCLEANUP_NOLABEL(); #else - NANOCLR_HEADER(); + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP(); #endif } -HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::GetWirelessAPConfiguration___STATIC__SystemNetNetworkInformationWirelessAPConfiguration__I4( CLR_RT_StackFrame& stack ) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: + GetWirelessAPConfiguration___STATIC__SystemNetNetworkInformationWirelessAPConfiguration__I4( + CLR_RT_StackFrame &stack) { #ifdef PLATFORM_ESP32 - NATIVE_PROFILE_CLR_NETWORK(); + NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); - HAL_Configuration_WirelessAP config; - CLR_RT_HeapBlock* pConfig; - CLR_UINT32 configurationIndex = stack.Arg0().NumericByRef().u4; - CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + HAL_Configuration_WirelessAP config; + CLR_RT_HeapBlock *pConfig; + CLR_UINT32 configurationIndex = stack.Arg0().NumericByRef().u4; + CLR_RT_HeapBlock &top = stack.PushValueAndClear(); NANOCLR_CLEAR(config); - + // load wireless AP configuration from the storage - if(!ConfigurationManager_GetConfigurationBlock((void*)&config, DeviceConfigurationOption_WirelessNetworkAP, configurationIndex)) + if (!ConfigurationManager_GetConfigurationBlock( + (void *)&config, + DeviceConfigurationOption_WirelessNetworkAP, + configurationIndex)) { NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); } // create new object for configuration - NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_WirelessAPConfiguration)); - + NANOCLR_CHECK_HRESULT( + g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_WirelessAPConfiguration)); + // load from stack - pConfig = top.Dereference(); FAULT_ON_NULL(pConfig); + pConfig = top.Dereference(); + FAULT_ON_NULL(pConfig); // fill in fields from config struct pConfig[FIELD___apId].SetInteger((CLR_UINT32)config.Id); @@ -59,37 +66,40 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura pConfig[FIELD___options].SetInteger((CLR_UINT8)config.Options); pConfig[FIELD___apChannel].SetInteger((CLR_UINT8)config.Channel); pConfig[FIELD___apMaxConnections].SetInteger((CLR_UINT8)config.MaxConnections); - - // the following ones are strings so a simple assignment isn't enough, need to create a managed string instance and copy over - // make sure the terminators are there + + // the following ones are strings so a simple assignment isn't enough, need to create a managed string instance and + // copy over make sure the terminators are there config.Password[WIRELESS82011_CONFIG_MAX_PASSWORD_LEN - 1] = 0; config.Ssid[WIRELESS82011_CONFIG_MAX_SSID_LEN - 1] = 0; - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___apPassword], (const char*)config.Password)); - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___apSsid], (const char*)config.Ssid)); + NANOCLR_CHECK_HRESULT( + CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___apPassword], (const char *)config.Password)); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___apSsid], (const char *)config.Ssid)); NANOCLR_NOCLEANUP(); #else - NANOCLR_HEADER(); + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP(); #endif } -HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::UpdateConfiguration___STATIC__VOID( CLR_RT_StackFrame& stack ) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: + UpdateConfiguration___STATIC__VOID(CLR_RT_StackFrame &stack) { #ifdef PLATFORM_ESP32 - NATIVE_PROFILE_CLR_NETWORK(); + NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); - HAL_Configuration_WirelessAP config; - CLR_RT_HeapBlock* pConfig = stack.Arg0().Dereference(); _ASSERTE(pConfig != NULL); - + HAL_Configuration_WirelessAP config; + CLR_RT_HeapBlock *pConfig = stack.Arg0().Dereference(); + _ASSERTE(pConfig != NULL); + CLR_UINT32 configurationIndex = pConfig[FIELD___apConfigurationIndex].NumericByRefConst().u4; - CLR_RT_HeapBlock_String* hbPassword = NULL; - CLR_RT_HeapBlock_String* hbSsid = NULL; + CLR_RT_HeapBlock_String *hbPassword = NULL; + CLR_RT_HeapBlock_String *hbSsid = NULL; CLR_UINT32 ssidLength; CLR_UINT32 passwordLength; @@ -105,131 +115,154 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura // the following ones are strings // make sure the terminators are there - hbPassword = pConfig[FIELD___apPassword].DereferenceString(); FAULT_ON_NULL(hbPassword); + hbPassword = pConfig[FIELD___apPassword].DereferenceString(); + FAULT_ON_NULL(hbPassword); passwordLength = hal_strlen_s(hbPassword->StringText()); - if (passwordLength >= sizeof(config.Password)) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); - hal_strncpy_s((char*)config.Password, WIRELESS82011_CONFIG_MAX_PASSWORD_LEN, hbPassword->StringText(), passwordLength); - - hbSsid = pConfig[FIELD___apSsid].DereferenceString(); FAULT_ON_NULL(hbSsid); + if (passwordLength >= sizeof(config.Password)) + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + hal_strncpy_s( + (char *)config.Password, + WIRELESS82011_CONFIG_MAX_PASSWORD_LEN, + hbPassword->StringText(), + passwordLength); + + hbSsid = pConfig[FIELD___apSsid].DereferenceString(); + FAULT_ON_NULL(hbSsid); ssidLength = hal_strlen_s(hbSsid->StringText()); - if (ssidLength >= sizeof(config.Ssid)) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); - hal_strncpy_s((char*)config.Ssid, WIRELESS82011_CONFIG_MAX_SSID_LEN, hbSsid->StringText(), ssidLength); + if (ssidLength >= sizeof(config.Ssid)) + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + hal_strncpy_s((char *)config.Ssid, WIRELESS82011_CONFIG_MAX_SSID_LEN, hbSsid->StringText(), ssidLength); // store configuration - if(ConfigurationManager_UpdateConfigurationBlock(&config, DeviceConfigurationOption_WirelessNetworkAP, configurationIndex) != TRUE) + if (ConfigurationManager_UpdateConfigurationBlock( + &config, + DeviceConfigurationOption_WirelessNetworkAP, + configurationIndex) != TRUE) { NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); } NANOCLR_NOCLEANUP(); #else - NANOCLR_HEADER(); + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP(); #endif } - -HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::NativeGetConnectedClients___STATIC__SZARRAY_SystemNetNetworkInformationWirelessAPStation__I4(CLR_RT_StackFrame& stack) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: + NativeGetConnectedClients___STATIC__SZARRAY_SystemNetNetworkInformationWirelessAPStation__I4( + CLR_RT_StackFrame &stack) { #ifdef PLATFORM_ESP32 - NANOCLR_HEADER(); - - CLR_RT_TypeDef_Index apStationTypeDef; - CLR_RT_HeapBlock* apStation; - CLR_RT_HeapBlock* hbObj; - - uint16_t stationCount = 0; - - uint8_t mac[6]; - uint8_t rssi; - uint32_t phyModes = 0; - - CLR_RT_HeapBlock& top = stack.PushValue(); - - // Get index of station info required or if index == 0 then return all connected stations - uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; - - - // find type, don't bother checking the result as it exists for sure - g_CLR_RT_TypeSystem.FindTypeDef("WirelessAPStation", "System.Net.NetworkInformation", apStationTypeDef); - - // Count stations connected - for (int x = 0; x < Network_Interface_Max_Stations(); x++) - { - if (index != 0 && x != index) continue; + NANOCLR_HEADER(); - if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) - { - stationCount++; - } - } + CLR_RT_TypeDef_Index apStationTypeDef; + CLR_RT_HeapBlock *apStation; + CLR_RT_HeapBlock *hbObj; - // Create an array of - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, stationCount, apStationTypeDef)); + uint16_t stationCount = 0; - // get a pointer to the first object in the array (which is of type ) - apStation = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + uint8_t mac[6]; + uint8_t rssi; + uint32_t phyModes = 0; - // Create Array - if (stationCount > 0) - { - for (int x = 0; x < Network_Interface_Max_Stations(); x++) - { - if (index != 0 && x != index) continue; + CLR_RT_HeapBlock &top = stack.PushValue(); - if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) - { - // create an instance of - NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*apStation, apStationTypeDef)); + // Get index of station info required or if index == 0 then return all connected stations + uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; - // dereference the object in order to reach its fields - hbObj = apStation->Dereference(); + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("WirelessAPStation", "System.Net.NetworkInformation", apStationTypeDef); - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___macAddress], 6, g_CLR_RT_WellKnownTypes.m_UInt8)); - memcpy(hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___macAddress].DereferenceArray()->GetFirstElement(), mac, 6); + // Count stations connected + for (int x = 0; x < Network_Interface_Max_Stations(); x++) + { + if (index != 0 && x != index) + continue; + if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) + { + stationCount++; + } + } - CLR_RT_HeapBlock& rssiFieldRef = hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___rssi]; - CLR_INT8* pRes2 = (CLR_INT8*)&rssiFieldRef.NumericByRef().s1; - *pRes2 = rssi; + // Create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, stationCount, apStationTypeDef)); - CLR_RT_HeapBlock& phyModesFieldRef = hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___phyModes]; - CLR_INT32* pRes3 = (CLR_INT32*)&phyModesFieldRef.NumericByRef().s4; - *pRes3 = phyModes; + // get a pointer to the first object in the array (which is of type ) + apStation = (CLR_RT_HeapBlock *)top.DereferenceArray()->GetFirstElement(); - apStation++; - } - } - } + // Create Array + if (stationCount > 0) + { + for (int x = 0; x < Network_Interface_Max_Stations(); x++) + { + if (index != 0 && x != index) + continue; + + if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*apStation, apStationTypeDef)); + + // dereference the object in order to reach its fields + hbObj = apStation->Dereference(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( + hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___macAddress], + 6, + g_CLR_RT_WellKnownTypes.m_UInt8)); + memcpy( + hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___macAddress] + .DereferenceArray() + ->GetFirstElement(), + mac, + 6); + + CLR_RT_HeapBlock &rssiFieldRef = + hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___rssi]; + CLR_INT8 *pRes2 = (CLR_INT8 *)&rssiFieldRef.NumericByRef().s1; + *pRes2 = rssi; + + CLR_RT_HeapBlock &phyModesFieldRef = + hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___phyModes]; + CLR_INT32 *pRes3 = (CLR_INT32 *)&phyModesFieldRef.NumericByRef().s4; + *pRes3 = phyModes; + + apStation++; + } + } + } - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP(); #else - NANOCLR_HEADER(); + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP(); #endif } -HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::NativeDeauthStation___STATIC__STRING__I4(CLR_RT_StackFrame& stack) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: + NativeDeauthStation___STATIC__STRING__I4(CLR_RT_StackFrame &stack) { #ifdef PLATFORM_ESP32 - NANOCLR_HEADER(); + NANOCLR_HEADER(); - uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; - - Network_Interface_Deauth_Station(index); + uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; - NANOCLR_NOCLEANUP_NOLABEL(); + Network_Interface_Deauth_Station(index); + + NANOCLR_NOCLEANUP_NOLABEL(); #else - NANOCLR_HEADER(); + NANOCLR_HEADER(); - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); - NANOCLR_NOCLEANUP(); + NANOCLR_NOCLEANUP(); #endif } From 825673282b89cd4214f32b983cea91e640cc7085 Mon Sep 17 00:00:00 2001 From: Adrian Soundy Date: Tue, 16 Jan 2024 16:20:09 +1300 Subject: [PATCH 514/572] Add support for IPV6 sockets (#2863) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: nfbot Co-authored-by: José Simões --- .../System.Net/sys_net_native.cpp | 16 +- .../System.Net/sys_net_native.h | 7 +- .../sys_net_native_System_Net_IPAddress.cpp | 21 +- ..._net_native_System_Net_IPAddress_stubs.cpp | 9 + ...et_NetworkInformation_NetworkInterface.cpp | 33 +- ...workInformation_NetworkInterface_stubs.cpp | 14 +- ...orkInformation_WirelessAPConfiguration.cpp | 22 +- ...native_System_Net_Sockets_NativeSocket.cpp | 124 +- src/PAL/COM/sockets/sockets_lwip.cpp | 24 +- src/PAL/Include/nanoPAL_Sockets.h | 57 +- src/PAL/Lwip/lwIP_Sockets.cpp | 313 ++++- src/PAL/Lwip/lwIP_Sockets.h | 9 +- src/PAL/Lwip/lwIP_Sockets_functions.cpp | 22 +- .../AzureRTOS/_common/NetX/netx_sockets.cpp | 39 +- targets/AzureRTOS/_common/NetX/netx_sockets.h | 4 +- .../_common/NetX/netx_sockets_functions.cpp | 8 +- .../AzureRTOS/_common/NetX/sockets_netx.cpp | 8 +- targets/ESP32/CMakePresets.json | 22 + .../_IDF/sdkconfig.default_rev3_ipv6.esp32 | 1127 +++++++++++++++++ targets/ESP32/_common/targetHAL_Network.cpp | 21 + .../_common/simplelink_sockets_functions.cpp | 8 +- 21 files changed, 1766 insertions(+), 142 deletions(-) create mode 100644 targets/ESP32/_IDF/sdkconfig.default_rev3_ipv6.esp32 diff --git a/src/DeviceInterfaces/System.Net/sys_net_native.cpp b/src/DeviceInterfaces/System.Net/sys_net_native.cpp index a398e956c3..d63570de86 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native.cpp @@ -48,7 +48,15 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::GetNetworkInterfaceCount___STATIC__I4, Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::GetNetworkInterface___STATIC__SystemNetNetworkInformationNetworkInterface__U4, - Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPAddressFromString___STATIC__I8__STRING, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPV4AddressFromString___STATIC__I8__STRING, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPV6AddressFromString___STATIC__SZARRAY_U2__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, NULL, NULL, NULL, @@ -85,6 +93,7 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, Library_sys_net_native_System_Net_IPAddress::IPv4ToString___STATIC__STRING__U4, + Library_sys_net_native_System_Net_IPAddress::IPv6ToString___STATIC__STRING__SZARRAY_U2, NULL, NULL, NULL, @@ -333,9 +342,8 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Net = { "System.Net", - 0x5BAB8CB3, + 0xA6875261, method_lookup, - { 100, 1, 5, 0 } + { 100, 2, 0, 0 } }; - // clang-format on diff --git a/src/DeviceInterfaces/System.Net/sys_net_native.h b/src/DeviceInterfaces/System.Net/sys_net_native.h index 0499791020..3f2d1195cc 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native.h +++ b/src/DeviceInterfaces/System.Net/sys_net_native.h @@ -137,7 +137,8 @@ struct Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface NANOCLR_NATIVE_DECLARE(GetIsNetworkAvailable___STATIC__BOOLEAN); NANOCLR_NATIVE_DECLARE(GetNetworkInterfaceCount___STATIC__I4); NANOCLR_NATIVE_DECLARE(GetNetworkInterface___STATIC__SystemNetNetworkInformationNetworkInterface__U4); - NANOCLR_NATIVE_DECLARE(IPAddressFromString___STATIC__I8__STRING); + NANOCLR_NATIVE_DECLARE(IPV4AddressFromString___STATIC__I8__STRING); + NANOCLR_NATIVE_DECLARE(IPV6AddressFromString___STATIC__SZARRAY_U2__STRING); //--// }; @@ -160,12 +161,16 @@ struct Library_sys_net_native_System_Net_IPAddress { static const int FIELD_STATIC__Any = 8; static const int FIELD_STATIC__Loopback = 9; + static const int FIELD_STATIC__IPv6Any = 10; + static const int FIELD_STATIC__IPv6Loopback = 11; static const int FIELD__Address = 1; static const int FIELD___family = 2; static const int FIELD___numbers = 3; + static const int FIELD___scopeid = 4; NANOCLR_NATIVE_DECLARE(IPv4ToString___STATIC__STRING__U4); + NANOCLR_NATIVE_DECLARE(IPv6ToString___STATIC__STRING__SZARRAY_U2); //--// }; diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress.cpp index aad01a15fc..e2f84bcbed 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress.cpp @@ -9,12 +9,25 @@ HRESULT Library_sys_net_native_System_Net_IPAddress::IPv4ToString___STATIC__STRI { NANOCLR_HEADER(); - // // get IP v4 address in numeric format - // const ip4_addr_t ip4Address = {stack.Arg0().NumericByRef().u4}; + // get IP v4 address in numeric format + NANOCLR_CHECK_HRESULT(stack.SetResult_String(SOCK_IPV4AddressToString(stack.Arg0().NumericByRef().u4))); - // NANOCLR_CHECK_HRESULT(stack.SetResult_String(ip4addr_ntoa(&ip4Address))); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_IPAddress::IPv6ToString___STATIC__STRING__SZARRAY_U2(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + +#if defined(LWIP_IPV6) && LWIP_IPV6 + // Get address of ushort array with ipv6 address + CLR_UINT16 *addr = (CLR_UINT16 *)stack.Arg0().DereferenceArray()->GetFirstElement(); - NANOCLR_CHECK_HRESULT(stack.SetResult_String(SOCK_IPAddressToString(stack.Arg0().NumericByRef().u4))); + // get IP v6 address in numeric format + NANOCLR_CHECK_HRESULT(stack.SetResult_String(SOCK_IPV6AddressToString(addr))); +#else + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); +#endif NANOCLR_NOCLEANUP(); } diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress_stubs.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress_stubs.cpp index 2a5263c97e..dbc32396ad 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress_stubs.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_IPAddress_stubs.cpp @@ -13,3 +13,12 @@ HRESULT Library_sys_net_native_System_Net_IPAddress::IPv4ToString___STATIC__STRI NANOCLR_NOCLEANUP(); } + +HRESULT Library_sys_net_native_System_Net_IPAddress::IPv6ToString___STATIC__STRING__SZARRAY_U2(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp index baaf990326..6813d22205 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp @@ -271,7 +271,7 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: pConfig[FIELD___ipv4dnsAddress1].SetInteger((CLR_UINT32)config.IPv4DNSAddress1); pConfig[FIELD___ipv4dnsAddress2].SetInteger((CLR_UINT32)config.IPv4DNSAddress2); - // FIXME IPV6 + // FIXME IPV6 these are arrays of CLR_UINT32 // pConfig[ FIELD___ipv6Address ].SetInteger( (CLR_UINT32)config.IPv6Address); // pConfig[ FIELD___ipv6GatewayAddress ].SetInteger( (CLR_UINT32)config.IPv6GatewayAddress); // pConfig[ FIELD___ipv6NetMask ].SetInteger( (CLR_UINT32)config.IPv6NetMask); @@ -293,8 +293,8 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPAddressFromString___STATIC__I8__STRING( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: + IPV4AddressFromString___STATIC__I8__STRING(CLR_RT_StackFrame &stack) { NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); @@ -303,9 +303,34 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::I LPCSTR ipString = stack.Arg0().RecoverString(); - NANOCLR_CHECK_HRESULT(SOCK_IPAddressFromString(ipString, &address)); + NANOCLR_CHECK_HRESULT(SOCK_IPV4AddressFromString(ipString, &address)); stack.PushValue().SetInteger((CLR_UINT64)address); NANOCLR_NOCLEANUP(); } + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: + IPV6AddressFromString___STATIC__SZARRAY_U2__STRING(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + +#if defined(LWIP_IPV6) && LWIP_IPV6 + LPCSTR ipString = stack.Arg0().RecoverString(); + uint16_t address[8]; + + NANOCLR_CHECK_HRESULT(SOCK_IPV6AddressFromString(ipString, address)); + + // Return array of uint16[8] + NANOCLR_CHECK_HRESULT( + CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 8, g_CLR_RT_WellKnownTypes.m_UInt16)); + { + uint16_t *p = (uint16_t *)stack.TopValue().DereferenceArray()->GetFirstElement(); + memcpy(p, address, sizeof(address)); + } +#else + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); +#endif + + NANOCLR_NOCLEANUP(); +} diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface_stubs.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface_stubs.cpp index 378447a785..87aac337ff 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface_stubs.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface_stubs.cpp @@ -55,8 +55,18 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: NANOCLR_NOCLEANUP(); } -HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPAddressFromString___STATIC__I8__STRING( - CLR_RT_StackFrame &stack) +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: + IPV4AddressFromString___STATIC__I8__STRING(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface:: + IPV6AddressFromString___STATIC__SZARRAY_U2__STRING(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp index d3370423f1..137e10364f 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp @@ -9,7 +9,7 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: GetWirelessAPConfigurationCount___STATIC__I4(CLR_RT_StackFrame &stack) { -#ifdef PLATFORM_ESP32 +#if defined(PLATFORM_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32H2) NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); @@ -30,7 +30,7 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura GetWirelessAPConfiguration___STATIC__SystemNetNetworkInformationWirelessAPConfiguration__I4( CLR_RT_StackFrame &stack) { -#ifdef PLATFORM_ESP32 +#if defined(PLATFORM_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32H2) NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); @@ -88,7 +88,7 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: UpdateConfiguration___STATIC__VOID(CLR_RT_StackFrame &stack) { -#ifdef PLATFORM_ESP32 +#if defined(PLATFORM_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32H2) NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); @@ -117,9 +117,13 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura // make sure the terminators are there hbPassword = pConfig[FIELD___apPassword].DereferenceString(); FAULT_ON_NULL(hbPassword); + passwordLength = hal_strlen_s(hbPassword->StringText()); if (passwordLength >= sizeof(config.Password)) + { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + hal_strncpy_s( (char *)config.Password, WIRELESS82011_CONFIG_MAX_PASSWORD_LEN, @@ -128,9 +132,13 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura hbSsid = pConfig[FIELD___apSsid].DereferenceString(); FAULT_ON_NULL(hbSsid); + ssidLength = hal_strlen_s(hbSsid->StringText()); if (ssidLength >= sizeof(config.Ssid)) + { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + hal_strncpy_s((char *)config.Ssid, WIRELESS82011_CONFIG_MAX_SSID_LEN, hbSsid->StringText(), ssidLength); // store configuration @@ -156,7 +164,7 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura NativeGetConnectedClients___STATIC__SZARRAY_SystemNetNetworkInformationWirelessAPStation__I4( CLR_RT_StackFrame &stack) { -#ifdef PLATFORM_ESP32 +#if defined(PLATFORM_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32H2) NANOCLR_HEADER(); CLR_RT_TypeDef_Index apStationTypeDef; @@ -181,7 +189,9 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura for (int x = 0; x < Network_Interface_Max_Stations(); x++) { if (index != 0 && x != index) + { continue; + } if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) { @@ -201,7 +211,9 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura for (int x = 0; x < Network_Interface_Max_Stations(); x++) { if (index != 0 && x != index) + { continue; + } if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) { @@ -250,7 +262,7 @@ HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfigura HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration:: NativeDeauthStation___STATIC__STRING__I4(CLR_RT_StackFrame &stack) { -#ifdef PLATFORM_ESP32 +#if defined(PLATFORM_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32H2) NANOCLR_HEADER(); uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp index 41208d0b4a..751fd014f7 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp @@ -528,6 +528,9 @@ CLR_INT32 Library_sys_net_native_System_Net_Sockets_NativeSocket::Helper__Select return res; } +// +// Marshal 'SOCK_sockaddr' to 'IPEndPoint' object +// HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddress( CLR_RT_HeapBlock &blkDst, const struct SOCK_sockaddr *addrSrc, @@ -539,8 +542,6 @@ HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddre (void)addrLenSrc; - SOCK_sockaddr_in *src = (SOCK_sockaddr_in *)addrSrc; - CLR_RT_TypeDef_Index ipAddressTypeDef; CLR_RT_TypeDef_Index ipEndPointTypeDef; CLR_RT_HeapBlock *ipAddressHbObj; @@ -554,6 +555,9 @@ HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddre ipEndPoint.SetObjectReference(NULL); CLR_RT_ProtectFromGC gc2(ipEndPoint); + CLR_INT32 port; + CLR_INT32 family; + // find type definition, don't bother checking the result as it exists for sure g_CLR_RT_TypeSystem.FindTypeDef("IPAddress", "System.Net", ipAddressTypeDef); @@ -572,20 +576,56 @@ HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddre { // get a reference to the managed fields and set them +#if defined(LWIP_IPV6) && LWIP_IPV6 + if (addrSrc->sa_family == SOCK_AF_INET6) + { + // IPV6 (SOCK_sockaddr_in6) + SOCK_sockaddr_in6 *src6 = (SOCK_sockaddr_in6 *)addrSrc; + + CLR_RT_HeapBlock &numbersFieldRef = + ipAddressHbObj[Library_sys_net_native_System_Net_IPAddress::FIELD___numbers]; + + NANOCLR_CHECK_HRESULT( + CLR_RT_HeapBlock_Array::CreateInstance(numbersFieldRef, 8, g_CLR_RT_WellKnownTypes.m_UInt16)); + + CLR_UINT16 *addrNumbers = (CLR_UINT16 *)numbersFieldRef.DereferenceArray()->GetFirstElement(); - // IPAddress _address field - // CLR_INT64 fields need to be accessed by pointer - CLR_RT_HeapBlock &addressFieldRef = ipAddressHbObj[Library_sys_net_native_System_Net_IPAddress::FIELD__Address]; - CLR_INT64 *pRes = (CLR_INT64 *)&addressFieldRef.NumericByRef().s8; - *pRes = src->sin_addr.S_un.S_addr; + // Copy address numbers + for (int i = 0; i < 8; i++) + { + addrNumbers[i] = SOCK_ntohs(src6->sin_addr.un.u16_addr[i]); + } + + ipAddressHbObj[Library_sys_net_native_System_Net_IPAddress::FIELD___scopeid].NumericByRef().s4 = + src6->scopeId; + + family = src6->sin_family; + port = src6->sin_port; + } + else +#endif + { + // IPV4 (SOCK_sockaddr_in) + SOCK_sockaddr_in *src = (SOCK_sockaddr_in *)addrSrc; + + // IPAddress _address field + // CLR_INT64 fields need to be accessed by pointer + CLR_RT_HeapBlock &addressFieldRef = + ipAddressHbObj[Library_sys_net_native_System_Net_IPAddress::FIELD__Address]; + CLR_INT64 *pRes = (CLR_INT64 *)&addressFieldRef.NumericByRef().s8; + *pRes = src->sin_addr.S_un.S_addr; + + family = src->sin_family; + port = src->sin_port; + } // IPAddress _family field - ipAddressHbObj[Library_sys_net_native_System_Net_IPAddress::FIELD___family].NumericByRef().s4 = src->sin_family; + ipAddressHbObj[Library_sys_net_native_System_Net_IPAddress::FIELD___family].NumericByRef().s4 = family; // IPEndPoint _port field // take care of endianess swapping ipEndPointHbObj[Library_sys_net_native_System_Net_IPEndPoint::FIELD___port].NumericByRef().s4 = - SOCK_ntohs(src->sin_port); + SOCK_ntohs(port); // set IPEndPoint address with IPAddress heap block object ipEndPointHbObj[Library_sys_net_native_System_Net_IPEndPoint::FIELD___address].SetObjectReference( @@ -600,6 +640,9 @@ HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddre NANOCLR_NOCLEANUP(); } +// +// Marshal 'IPEndPoint' object to 'SOCK_sockaddr' +// HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddress( struct SOCK_sockaddr *addrDst, CLR_UINT32 &addrLenDst, @@ -608,39 +651,76 @@ HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddre NATIVE_PROFILE_CLR_NETWORK(); NANOCLR_HEADER(); - SOCK_sockaddr_in *dst = (SOCK_sockaddr_in *)addrDst; - CLR_RT_HeapBlock *endPointAddress; CLR_RT_HeapBlock *remoteEndPointAddress; int64_t address; int32_t port; +#if defined(LWIP_IPV6) && LWIP_IPV6 + int32_t family; +#endif endPointAddress = blkEndPointAddress.Dereference(); FAULT_ON_NULL(endPointAddress); + // clear struct + memset(addrDst, 0, sizeof(SOCK_sockaddr)); + // get a pointer to the managed field object instance for m_Address remoteEndPointAddress = endPointAddress[Library_sys_net_native_System_Net_IPEndPoint::FIELD___address].Dereference(); FAULT_ON_NULL(remoteEndPointAddress); - // get value of m_Address field (type long) - address = - (CLR_INT64)remoteEndPointAddress[Library_sys_net_native_System_Net_IPAddress::FIELD__Address].NumericByRef().s8; +#if defined(LWIP_IPV6) && LWIP_IPV6 + family = remoteEndPointAddress[Library_sys_net_native_System_Net_IPAddress::FIELD___family].NumericByRef().s1; +#endif // get value of m_Port field (type int) port = endPointAddress[Library_sys_net_native_System_Net_IPEndPoint::FIELD___port].NumericByRef().s4; - // clear struct - memset(dst, 0, sizeof(SOCK_sockaddr)); +#if defined(LWIP_IPV6) && LWIP_IPV6 + if (family == SOCK_AF_INET6) + { + SOCK_sockaddr_in6 *dst = (SOCK_sockaddr_in6 *)addrDst; + CLR_RT_HeapBlock_Array *numbersArray; + CLR_UINT16 *addrNumbers; + + dst->sin_family = SOCK_AF_INET6; + // need to convert port number to network order + dst->sin_port = SOCK_htons(port); - dst->sin_family = SOCK_AF_INET; - // need to convert port number to network order - dst->sin_port = SOCK_htons(port); + numbersArray = + remoteEndPointAddress[Library_sys_net_native_System_Net_IPAddress::FIELD___numbers].DereferenceArray(); + FAULT_ON_NULL(numbersArray); - // address already in network byte order - memcpy((int8_t *)&dst->sin_addr.S_un.S_addr, (int8_t *)&address, sizeof(address)); + addrNumbers = (CLR_UINT16 *)numbersArray->GetFirstElement(); + for (int i = 0; i < 8; i++) + { + dst->sin_addr.un.u16_addr[i] = SOCK_ntohs(addrNumbers[i]); + } - addrLenDst = sizeof(address); + dst->scopeId = + remoteEndPointAddress[Library_sys_net_native_System_Net_IPAddress::FIELD___scopeid].NumericByRef().u4; + addrLenDst = sizeof(SOCK_sockaddr_in6); + } + else +#endif + { + SOCK_sockaddr_in *dst = (SOCK_sockaddr_in *)addrDst; + + // get value of m_Address field (type long) + address = (CLR_INT64)remoteEndPointAddress[Library_sys_net_native_System_Net_IPAddress::FIELD__Address] + .NumericByRef() + .s8; + + dst->sin_family = SOCK_AF_INET; + // need to convert port number to network order + dst->sin_port = SOCK_htons(port); + + // address already in network byte order + memcpy((int8_t *)&dst->sin_addr.S_un.S_addr, (int8_t *)&address, sizeof(address)); + + addrLenDst = sizeof(SOCK_sockaddr_in); + } NANOCLR_NOCLEANUP(); } diff --git a/src/PAL/COM/sockets/sockets_lwip.cpp b/src/PAL/COM/sockets/sockets_lwip.cpp index 4107f519ca..27b073aa19 100644 --- a/src/PAL/COM/sockets/sockets_lwip.cpp +++ b/src/PAL/COM/sockets/sockets_lwip.cpp @@ -203,20 +203,36 @@ HRESULT SOCK_CONFIGURATION_LinkStatus(uint32_t interfaceIndex, bool *status) return HAL_SOCK_CONFIGURATION_Link_status(interfaceIndex, status); } -HRESULT SOCK_IPAddressFromString(const char *ipString, uint64_t *address) +HRESULT SOCK_IPV4AddressFromString(const char *ipString, uint64_t *address) { NATIVE_PROFILE_PAL_COM(); - return HAL_SOCK_IPAddressFromString(ipString, address); + return HAL_SOCK_IPV4AddressFromString(ipString, address); } -const char *SOCK_IPAddressToString(uint32_t address) +const char *SOCK_IPV4AddressToString(uint32_t address) { NATIVE_PROFILE_PAL_COM(); - return HAL_SOCK_IPAddressToString(address); + return HAL_SOCK_IPV4AddressToString(address); } +#if LWIP_IPV6 +HRESULT SOCK_IPV6AddressFromString(const char *ipString, uint16_t *address) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_IPV6AddressFromString(ipString, address); +} + +const char *SOCK_IPV6AddressToString(uint16_t *address) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_IPV6AddressToString(address); +} +#endif + #define SOCKET_SHUTDOWN_READ 0 #define SOCKET_SHUTDOWN_WRITE 1 #define SOCKET_SHUTDOWN_READ_WRITE 2 diff --git a/src/PAL/Include/nanoPAL_Sockets.h b/src/PAL/Include/nanoPAL_Sockets.h index 78d5b86bab..7f23e98d6e 100644 --- a/src/PAL/Include/nanoPAL_Sockets.h +++ b/src/PAL/Include/nanoPAL_Sockets.h @@ -113,9 +113,12 @@ typedef unsigned long u_long; typedef unsigned __int64 u_int64; // // -#define SOCK_AF_UNSPEC 0 /* unspecified */ -#define SOCK_AF_INET 2 /* internetwork: UDP, TCP, etc. */ -#define SOCK_AF_INET6 28 +// unspecified +#define SOCK_AF_UNSPEC 0 +// internetwork (IPV4): UDP, TCP, etc. +#define SOCK_AF_INET 2 +// Ipv6 +#define SOCK_AF_INET6 23 typedef int SOCK_SOCKET; @@ -231,8 +234,13 @@ typedef int SOCK_SOCKET; #define SOCK_FIOASYNC SOCK__IOW('f', 125, u_long) /* set/clear async i/o */ // -#define SOCK_FD_SETSIZE 256 +#define SOCK_FD_SETSIZE 256 + +#if defined(LWIP_IPV6) && LWIP_IPV6 +#define SOCK_MAX_ADDR_SIZE 26 +#else #define SOCK_MAX_ADDR_SIZE 14 +#endif typedef struct SOCK_fd_set { @@ -246,7 +254,7 @@ typedef struct SOCK_sockaddr char sa_data[SOCK_MAX_ADDR_SIZE]; /* up to SOCK_MAX_ADDR_SIZE bytes of direct address */ } SOCK_sockaddr; -CT_ASSERT_UNIQUE_NAME(sizeof(SOCK_sockaddr) == (16), SOCK_SOCKADDR) +CT_ASSERT_UNIQUE_NAME(sizeof(SOCK_sockaddr) == (SOCK_MAX_ADDR_SIZE + 2), SOCK_SOCKADDR) typedef struct GNU_PACKED SOCK_in_addr { @@ -275,6 +283,28 @@ typedef struct GNU_PACKED SOCK_sockaddr_in CT_ASSERT_UNIQUE_NAME(sizeof(SOCK_sockaddr_in) == 16, SOCK_SOCKADDR_IN) +#if defined(LWIP_IPV6) && LWIP_IPV6 +typedef struct GNU_PACKED SOCK_in_addr6 +{ + union { + u32_t u32_addr[4]; + u16_t u16_addr[8]; + u8_t u8_addr[16]; + } un; +} SOCK_in_addr6; + +typedef struct GNU_PACKED SOCK_sockaddr_in6 +{ + short sin_family; + u_short sin_port; + SOCK_in_addr6 sin_addr; + u32_t scopeId; +} SOCK_sockaddr_in6; + +CT_ASSERT_UNIQUE_NAME(sizeof(SOCK_sockaddr_in6) == 24, SOCK_SOCKADDR_IN6) + +#endif + typedef struct SOCK_addrinfo { int ai_flags; @@ -635,8 +665,12 @@ HRESULT SOCK_CONFIGURATION_UpdateAdapterConfiguration( uint32_t updateFlags); HRESULT SOCK_CONFIGURATION_LoadConfiguration(HAL_Configuration_NetworkInterface *config, uint32_t interfaceIndex); HRESULT SOCK_CONFIGURATION_LinkStatus(uint32_t interfaceIndex, bool *status); -HRESULT SOCK_IPAddressFromString(const char *ipString, uint64_t *address); -const char *SOCK_IPAddressToString(uint32_t address); +HRESULT SOCK_IPV4AddressFromString(const char *ipString, uint64_t *address); +const char *SOCK_IPV4AddressToString(uint32_t address); +#if defined(LWIP_IPV6) && LWIP_IPV6 +const char *SOCK_IPV6AddressToString(uint16_t *address); +HRESULT SOCK_IPV6AddressFromString(const char *ipString, uint16_t *address); +#endif //--// SSL @@ -729,9 +763,12 @@ HRESULT HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration( uint32_t interfaceIndex, uint32_t updateFlags); HRESULT HAL_SOCK_CONFIGURATION_Link_status(uint32_t interfaceIndex, bool *status); -HRESULT HAL_SOCK_IPAddressFromString(const char *ipString, uint64_t *address); -const char *HAL_SOCK_IPAddressToString(uint32_t address); - +HRESULT HAL_SOCK_IPV4AddressFromString(const char *ipString, uint64_t *address); +const char *HAL_SOCK_IPV4AddressToString(uint32_t address); +#if defined(LWIP_IPV6) && LWIP_IPV6 +HRESULT HAL_SOCK_IPV6AddressFromString(const char *ipString, uint16_t *address); +const char *HAL_SOCK_IPV6AddressToString(uint16_t *address); +#endif void *HAL_SOCK_GlobalLockContext(); void HAL_SOCK_EventsSet(uint32_t events); diff --git a/src/PAL/Lwip/lwIP_Sockets.cpp b/src/PAL/Lwip/lwIP_Sockets.cpp index 971c0c5084..30f33942b8 100644 --- a/src/PAL/Lwip/lwIP_Sockets.cpp +++ b/src/PAL/Lwip/lwIP_Sockets.cpp @@ -92,20 +92,14 @@ HRESULT LWIP_SOCKETS_Driver::Link_status(uint32_t interfaceIndex, bool *status) return S_OK; } -HRESULT LWIP_SOCKETS_Driver::IPAddressFromString(const char *ipString, uint64_t *address) +HRESULT LWIP_SOCKETS_Driver::IPV4AddressFromString(const char *ipString, uint64_t *address) { ip4_addr_t ipv4Address; - // FIXME IPV6 - // ip6_addr_t ipv6Address if (ip4addr_aton(ipString, &ipv4Address)) { *address = ipv4Address.addr; } - // FIXME IPV6 - // else if(ip6addr_aton(ipString, &ipv6Address)) - // { - // } else { return CLR_E_INVALID_PARAMETER; @@ -114,15 +108,51 @@ HRESULT LWIP_SOCKETS_Driver::IPAddressFromString(const char *ipString, uint64_t return S_OK; } -const char *LWIP_SOCKETS_Driver::IPAddressToString(uint32_t address) +const char *LWIP_SOCKETS_Driver::IP4AddressToString(uint32_t address) { // get IP v4 address in numeric format - // FIXME IPV6 const ip4_addr_t ip4Address = {address}; return ip4addr_ntoa(&ip4Address); } +#if LWIP_IPV6 +HRESULT LWIP_SOCKETS_Driver::IPV6AddressFromString(const char *ipString, uint16_t *address) +{ + ip6_addr_t ipv6Address; + + if (ip6addr_aton(ipString, &ipv6Address)) + { + address[0] = IP6_ADDR_BLOCK1(&ipv6Address); + address[1] = IP6_ADDR_BLOCK2(&ipv6Address); + address[2] = IP6_ADDR_BLOCK3(&ipv6Address); + address[3] = IP6_ADDR_BLOCK4(&ipv6Address); + address[4] = IP6_ADDR_BLOCK5(&ipv6Address); + address[5] = IP6_ADDR_BLOCK6(&ipv6Address); + address[6] = IP6_ADDR_BLOCK7(&ipv6Address); + address[7] = IP6_ADDR_BLOCK8(&ipv6Address); + } + else + { + return CLR_E_INVALID_PARAMETER; + } + return S_OK; +} + +const char *LWIP_SOCKETS_Driver::IP6AddressToString(uint16_t *address) +{ + // get IP v6 address in numeric format + ip6_addr_t ip6Address; + + ip6Address.addr[0] = lwip_htonl((address[0] << 16) + address[1]); + ip6Address.addr[1] = lwip_htonl((address[2] << 16) + address[3]); + ip6Address.addr[2] = lwip_htonl((address[4] << 16) + address[5]); + ip6Address.addr[3] = lwip_htonl((address[6] << 16) + address[7]); + + return ip6addr_ntoa(&ip6Address); +} +#endif + #if LWIP_NETIF_LINK_CALLBACK == 1 void LWIP_SOCKETS_Driver::Link_callback(struct netif *netif) { @@ -315,14 +345,31 @@ SOCK_SOCKET LWIP_SOCKETS_Driver::Socket(int family, int type, int protocol) { NATIVE_PROFILE_PAL_NETWORK(); + switch (family) + { + case SOCK_AF_INET: + family = AF_INET; + break; + + case SOCK_AF_INET6: + family = AF_INET6; + break; + + default: + family = AF_UNSPEC; + break; + } + switch (protocol) { case SOCK_IPPROTO_TCP: protocol = IPPROTO_TCP; break; + case SOCK_IPPROTO_UDP: protocol = IPPROTO_UDP; break; + case SOCK_IPPROTO_ICMP: protocol = IP_PROTO_ICMP; break; @@ -330,29 +377,119 @@ SOCK_SOCKET LWIP_SOCKETS_Driver::Socket(int family, int type, int protocol) case SOCK_IPPROTO_IGMP: protocol = IP_PROTO_IGMP; break; + + case SOCK_IPPROTO_RAW: + protocol = IPPROTO_RAW; + break; } return lwip_socket(family, type, protocol); } +sockaddr *Sock_SockaddrToSockaddrV4(const SOCK_sockaddr *ssa, sockaddr_in *sai, int *addrLen) +{ + // IPV4 + sai->sin_len = (u8_t)sizeof(sockaddr_in); + sai->sin_family = AF_INET; + sai->sin_port = ((SOCK_sockaddr_in *)ssa)->sin_port; + sai->sin_addr.s_addr = ((SOCK_sockaddr_in *)ssa)->sin_addr.S_un.S_addr; + + memcpy(sai->sin_zero, ((SOCK_sockaddr_in *)ssa)->sin_zero, sizeof(sai->sin_zero)); + + *addrLen = sizeof(sockaddr_in); + + return (sockaddr *)sai; +} + +#if LWIP_IPV6 +sockaddr *Sock_SockaddrToSockaddrV6(const SOCK_sockaddr *ssa, sockaddr_in6 *sai, int *addrLen) +{ + // IPV6 + sai->sin6_len = (u8_t)sizeof(sockaddr_in6); + sai->sin6_family = AF_INET6; + sai->sin6_port = ((SOCK_sockaddr_in6 *)ssa)->sin_port; + + for (int i = 0; i < 4; i++) + { + sai->sin6_addr.un.u32_addr[i] = ((SOCK_sockaddr_in6 *)ssa)->sin_addr.un.u32_addr[i]; + } + + sai->sin6_scope_id = ((SOCK_sockaddr_in6 *)ssa)->scopeId; + + *addrLen = sizeof(sockaddr_in6); + return (sockaddr *)sai; +} +#endif + +sockaddr *Sock_SockaddrToSockaddr(const SOCK_sockaddr *ssa, sockaddr *sai, int *addrLen) +{ +#if LWIP_IPV6 + if (ssa->sa_family == SOCK_AF_INET6) + { + return Sock_SockaddrToSockaddrV6(ssa, (sockaddr_in6 *)sai, addrLen); + } +#endif + + return Sock_SockaddrToSockaddrV4(ssa, (sockaddr_in *)sai, addrLen); +} + +void sockaddrToSock_SockAddr(SOCK_sockaddr *ssa, sockaddr *sa, int *addrLen) +{ +#if LWIP_IPV6 + if (sa->sa_family == AF_INET6) + { + sockaddr_in6 *sa6 = (sockaddr_in6 *)sa; + ((SOCK_sockaddr_in6 *)ssa)->sin_port = sa6->sin6_port; + ((SOCK_sockaddr_in6 *)ssa)->sin_family = SOCK_AF_INET6; + + for (int i = 0; i < 4; i++) + { + ((SOCK_sockaddr_in6 *)ssa)->sin_addr.un.u32_addr[i] = sa6->sin6_addr.un.u32_addr[i]; + } + + ((SOCK_sockaddr_in6 *)ssa)->scopeId = sa6->sin6_scope_id; + *addrLen = sizeof(SOCK_sockaddr_in6); + } + else +#endif + { + sockaddr_in *sa4 = (sockaddr_in *)sa; + ((SOCK_sockaddr_in *)ssa)->sin_port = sa4->sin_port; + ((SOCK_sockaddr_in *)ssa)->sin_addr.S_un.S_addr = sa4->sin_addr.s_addr; + ((SOCK_sockaddr_in *)ssa)->sin_family = SOCK_AF_INET; + memcpy(((SOCK_sockaddr_in *)ssa)->sin_zero, sa4->sin_zero, sizeof(((SOCK_sockaddr_in *)ssa)->sin_zero)); + *addrLen = sizeof(SOCK_sockaddr_in); + } +} + int LWIP_SOCKETS_Driver::Bind(SOCK_SOCKET socket, const SOCK_sockaddr *address, int addressLen) { NATIVE_PROFILE_PAL_NETWORK(); +#if LWIP_IPV6 + sockaddr_in6 addr; +#else sockaddr_in addr; +#endif + + Sock_SockaddrToSockaddr(address, (sockaddr *)&addr, &addressLen); - SOCK_SOCKADDR_TO_SOCKADDR(address, addr, &addressLen); + int ret = lwip_bind(socket, (sockaddr *)&addr, addressLen); - return lwip_bind(socket, (sockaddr *)&addr, addressLen); + return ret; } int LWIP_SOCKETS_Driver::Connect(SOCK_SOCKET socket, const SOCK_sockaddr *address, int addressLen) { NATIVE_PROFILE_PAL_NETWORK(); +#if LWIP_IPV6 + sockaddr_in6 addr; +#else sockaddr_in addr; +#endif - SOCK_SOCKADDR_TO_SOCKADDR(address, addr, &addressLen); + Sock_SockaddrToSockaddr(address, (sockaddr *)&addr, &addressLen); return lwip_connect(socket, (sockaddr *)&addr, addressLen); } @@ -401,18 +538,22 @@ SOCK_SOCKET LWIP_SOCKETS_Driver::Accept(SOCK_SOCKET socket, SOCK_sockaddr *addre NATIVE_PROFILE_PAL_NETWORK(); SOCK_SOCKET ret; +#if LWIP_IPV6 + sockaddr_in6 addr; +#else sockaddr_in addr; +#endif if (address) { - SOCK_SOCKADDR_TO_SOCKADDR(address, addr, addressLen); + Sock_SockaddrToSockaddr(address, (sockaddr *)&addr, addressLen); } ret = lwip_accept(socket, address ? (sockaddr *)&addr : NULL, (u32_t *)addressLen); if (address) { - SOCKADDR_TO_SOCK_SOCKADDR(address, addr, addressLen); + sockaddrToSock_SockAddr(address, (sockaddr *)&addr, addressLen); } return ret; @@ -425,13 +566,27 @@ int LWIP_SOCKETS_Driver::Shutdown(SOCK_SOCKET socket, int how) return lwip_shutdown(socket, how); } -SOCK_addrinfo *CreateAddressRecord(u_long addr, short family, u_short port, char *canonname, const SOCK_addrinfo *hints) +SOCK_addrinfo *CreateAddressRecord( + short family, + ip_addr_t &addr, + u_short port, + char *canonname, + const SOCK_addrinfo *hints) { SOCK_addrinfo *ai; SOCK_sockaddr_in *sa = NULL; - int total_size = sizeof(SOCK_addrinfo) + sizeof(SOCK_sockaddr_in); +#if LWIP_IPV6 + SOCK_sockaddr_in6 *sa6 = NULL; +#endif + int total_size = sizeof(SOCK_addrinfo); int canonNameSize; - void *dummyPtr; + void *saPtr; + +#if LWIP_IPV6 + total_size += (family == SOCK_AF_INET6) ? sizeof(SOCK_sockaddr_in6) : sizeof(SOCK_sockaddr_in); +#else + total_size += sizeof(SOCK_sockaddr_in); +#endif // Allow for canon name if available if (canonname != NULL) @@ -449,12 +604,41 @@ SOCK_addrinfo *CreateAddressRecord(u_long addr, short family, u_short port, char } memset(ai, 0, total_size); - sa = (SOCK_sockaddr_in *)((u8_t *)ai + sizeof(SOCK_addrinfo)); - // set up sockaddr - sa->sin_addr.S_un.S_addr = addr; - sa->sin_family = family; - sa->sin_port = port; +#if LWIP_IPV6 + if (family == SOCK_AF_INET6) + { + // IPV6 address + sa6 = (SOCK_sockaddr_in6 *)((u8_t *)ai + sizeof(SOCK_addrinfo)); + + // set up sockaddr + sa6->sin_family = family; + sa6->sin_port = port; + sa6->sin_addr.un.u32_addr[0] = addr.u_addr.ip6.addr[0]; + sa6->sin_addr.un.u32_addr[1] = addr.u_addr.ip6.addr[1]; + sa6->sin_addr.un.u32_addr[2] = addr.u_addr.ip6.addr[2]; + sa6->sin_addr.un.u32_addr[3] = addr.u_addr.ip6.addr[3]; + + saPtr = sa6; + ai->ai_addrlen = sizeof(SOCK_sockaddr_in6); + } + else +#endif + { + // IPV4 address + sa = (SOCK_sockaddr_in *)((u8_t *)ai + sizeof(SOCK_addrinfo)); + + // set up sockaddr + sa->sin_family = family; + sa->sin_port = port; +#if LWIP_IPV6 + sa->sin_addr.S_un.S_addr = (u_long)addr.u_addr.ip4.addr; +#else + sa->sin_addr.S_un.S_addr = (u_long)addr.addr; +#endif + saPtr = sa; + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + } // set up addrinfo ai->ai_family = family; @@ -473,12 +657,7 @@ SOCK_addrinfo *CreateAddressRecord(u_long addr, short family, u_short port, char memcpy(ai->ai_canonname, canonname, canonNameSize); } - // need this to keep the compiler happy about the cast to SOCK_sockaddr - // which is intended and perfectly safe - dummyPtr = sa; - - ai->ai_addrlen = sizeof(SOCK_sockaddr_in); - ai->ai_addr = (SOCK_sockaddr *)dummyPtr; + ai->ai_addr = (SOCK_sockaddr *)saPtr; return ai; } @@ -518,20 +697,39 @@ int LWIP_SOCKETS_Driver::GetAddrInfo( } #if LWIP_IPV6 - u_long addr = networkInterface->ip_addr.u_addr.ip4.addr; + int numadrs = 4; #else - u_long addr = networkInterface->ip_addr.addr; + int numadrs = 1; #endif - ai = CreateAddressRecord(addr, AF_INET, 0, NULL, hints); - if (ai == NULL) + + for (int addresses = (numadrs - 1); addresses >= 0; addresses--) { - // Out of memory ? - return SOCK_SOCKET_ERROR; - } + short family = SOCK_AF_INET; + ip_addr_t addr; + + if (addresses == 0) + { + addr = networkInterface->ip_addr; + } +#if LWIP_IPV6 + else + { + // IPv6 interfaces + family = SOCK_AF_INET6; + addr = networkInterface->ip6_addr[addresses - 1]; + } +#endif + ai = CreateAddressRecord(family, addr, 0, NULL, hints); + if (ai == NULL) + { + // Out of memory ? + return SOCK_SOCKET_ERROR; + } - // Link SOCK_addrinfo + records together - ai->ai_next = nextAi; - nextAi = ai; + // Link SOCK_addrinfo + records together + ai->ai_next = nextAi; + nextAi = ai; + } } if (ai == NULL) @@ -552,10 +750,17 @@ int LWIP_SOCKETS_Driver::GetAddrInfo( /// Marshal addrinfo data /// struct sockaddr_in *lwip_sockaddr_in = ((struct sockaddr_in *)lwipAddrinfo->ai_addr); + ip_addr_t addr; + +#if LWIP_IPV6 + addr.u_addr.ip4.addr = lwip_sockaddr_in->sin_addr.s_addr; +#else + addr.addr = lwip_sockaddr_in->sin_addr.s_addr; +#endif ai = CreateAddressRecord( - lwip_sockaddr_in->sin_addr.s_addr, - lwip_sockaddr_in->sin_family, + (lwip_sockaddr_in->sin_family == AF_INET6) ? SOCK_AF_INET6 : SOCK_AF_INET, + addr, lwip_sockaddr_in->sin_port, lwipAddrinfo->ai_canonname, hints); @@ -889,13 +1094,15 @@ int LWIP_SOCKETS_Driver::GetPeerName(SOCK_SOCKET socket, SOCK_sockaddr *name, in NATIVE_PROFILE_PAL_NETWORK(); int ret; +#if LWIP_IPV6 + sockaddr_in6 addr; +#else sockaddr_in addr; - - SOCK_SOCKADDR_TO_SOCKADDR(name, addr, namelen); +#endif ret = lwip_getpeername(socket, (sockaddr *)&addr, (u32_t *)namelen); - SOCKADDR_TO_SOCK_SOCKADDR(name, addr, namelen); + sockaddrToSock_SockAddr(name, (sockaddr *)&addr, namelen); return ret; } @@ -905,13 +1112,15 @@ int LWIP_SOCKETS_Driver::GetSockName(SOCK_SOCKET socket, SOCK_sockaddr *name, in NATIVE_PROFILE_PAL_NETWORK(); int ret; +#if LWIP_IPV6 + sockaddr_in6 addr; +#else sockaddr_in addr; - - SOCK_SOCKADDR_TO_SOCKADDR(name, addr, namelen); +#endif ret = lwip_getsockname(socket, (sockaddr *)&addr, (u32_t *)namelen); - SOCKADDR_TO_SOCK_SOCKADDR(name, addr, namelen); + sockaddrToSock_SockAddr(name, (sockaddr *)&addr, namelen); return ret; } @@ -919,13 +1128,19 @@ int LWIP_SOCKETS_Driver::GetSockName(SOCK_SOCKET socket, SOCK_sockaddr *name, in int LWIP_SOCKETS_Driver::RecvFrom(SOCK_SOCKET socket, char *buf, int len, int flags, SOCK_sockaddr *from, int *fromlen) { NATIVE_PROFILE_PAL_NETWORK(); - sockaddr_in addr; sockaddr *pFrom = NULL; int ret; +#if LWIP_IPV6 + sockaddr_in6 addr; +#else + sockaddr_in addr; +#endif + if (from) { - SOCK_SOCKADDR_TO_SOCKADDR(from, addr, fromlen); + Sock_SockaddrToSockaddr(from, (sockaddr *)&addr, fromlen); + pFrom = (sockaddr *)&addr; } @@ -933,7 +1148,7 @@ int LWIP_SOCKETS_Driver::RecvFrom(SOCK_SOCKET socket, char *buf, int len, int fl if (from && ret != SOCK_SOCKET_ERROR) { - SOCKADDR_TO_SOCK_SOCKADDR(from, addr, fromlen); + sockaddrToSock_SockAddr(from, (sockaddr *)&addr, fromlen); } return ret; diff --git a/src/PAL/Lwip/lwIP_Sockets.h b/src/PAL/Lwip/lwIP_Sockets.h index 6839359376..76c52c7e0c 100644 --- a/src/PAL/Lwip/lwIP_Sockets.h +++ b/src/PAL/Lwip/lwIP_Sockets.h @@ -101,9 +101,14 @@ struct LWIP_SOCKETS_Driver static HRESULT Link_status(uint32_t interfaceIndex, bool *status); - static HRESULT IPAddressFromString(const char *ipString, uint64_t *address); + static HRESULT IPV4AddressFromString(const char *ipString, uint64_t *address); - static const char *IPAddressToString(uint32_t address); + static const char *IP4AddressToString(uint32_t address); + +#if LWIP_IPV6 + static HRESULT IPV6AddressFromString(const char *ipString, uint16_t *address); + static const char *IP6AddressToString(uint16_t *addr); +#endif static HRESULT LoadAdapterConfiguration(HAL_Configuration_NetworkInterface *config, uint32_t interfaceIndex); diff --git a/src/PAL/Lwip/lwIP_Sockets_functions.cpp b/src/PAL/Lwip/lwIP_Sockets_functions.cpp index af188b50b6..0f22ff8e60 100644 --- a/src/PAL/Lwip/lwIP_Sockets_functions.cpp +++ b/src/PAL/Lwip/lwIP_Sockets_functions.cpp @@ -156,18 +156,32 @@ HRESULT HAL_SOCK_CONFIGURATION_Link_status(uint32_t interfaceIndex, bool *status return LWIP_SOCKETS_Driver::Link_status(interfaceIndex, status); } -HRESULT HAL_SOCK_IPAddressFromString(const char *ipString, uint64_t *address) +HRESULT HAL_SOCK_IPV4AddressFromString(const char *ipString, uint64_t *address) { NATIVE_PROFILE_PAL_NETWORK(); - return LWIP_SOCKETS_Driver::IPAddressFromString(ipString, address); + return LWIP_SOCKETS_Driver::IPV4AddressFromString(ipString, address); } -const char *HAL_SOCK_IPAddressToString(uint32_t address) +const char *HAL_SOCK_IPV4AddressToString(uint32_t address) { NATIVE_PROFILE_PAL_NETWORK(); - return LWIP_SOCKETS_Driver::IPAddressToString(address); + return LWIP_SOCKETS_Driver::IP4AddressToString(address); } +#if LWIP_IPV6 +HRESULT HAL_SOCK_IPV6AddressFromString(const char *ipString, uint16_t *address) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::IPV6AddressFromString(ipString, address); +} + +const char *HAL_SOCK_IPV6AddressToString(uint16_t *addr) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::IP6AddressToString(addr); +} +#endif + void HAL_SOCK_EventsSet(uint32_t events) { #ifdef BUILD_RTM diff --git a/targets/AzureRTOS/_common/NetX/netx_sockets.cpp b/targets/AzureRTOS/_common/NetX/netx_sockets.cpp index 253be83289..e8bfc875fb 100644 --- a/targets/AzureRTOS/_common/NetX/netx_sockets.cpp +++ b/targets/AzureRTOS/_common/NetX/netx_sockets.cpp @@ -76,7 +76,7 @@ HRESULT NETX_SOCKETS_Driver::Link_status(uint32_t interfaceIndex, bool *status) return S_OK; } -HRESULT NETX_SOCKETS_Driver::IPAddressFromString(const char *ipString, uint64_t *address) +HRESULT NETX_SOCKETS_Driver::IPV4AddressFromString(const char *ipString, uint64_t *address) { struct in_addr ipv4_addr; @@ -92,7 +92,7 @@ HRESULT NETX_SOCKETS_Driver::IPAddressFromString(const char *ipString, uint64_t return S_OK; } -const char *NETX_SOCKETS_Driver::IPAddressToString(uint32_t address) +const char *NETX_SOCKETS_Driver::IPV4AddressToString(uint32_t address) { // get IP v4 address in numeric format // FIXME IPV6 @@ -189,7 +189,7 @@ bool NETX_SOCKETS_Driver::Initialize() int interfaceCount = g_TargetConfiguration.NetworkInterfaceConfigs->Count; // sanity check for any interfaces - if(interfaceCount > 0) + if (interfaceCount > 0) { g_NETX_SOCKETS_Driver.m_interfaces = (NETX_DRIVER_INTERFACE_DATA *)platform_malloc(interfaceCount * sizeof(NETX_DRIVER_INTERFACE_DATA)); @@ -212,7 +212,7 @@ bool NETX_SOCKETS_Driver::Initialize() } // sanity check - if(networkConfiguration.StartupAddressMode == 0) + if (networkConfiguration.StartupAddressMode == 0) { return FALSE; } @@ -321,9 +321,9 @@ int NETX_SOCKETS_Driver::Bind(SOCK_SOCKET socket, const SOCK_sockaddr *address, SOCK_SOCKADDR_TO_SOCKADDR(address, addr, &addressLen); -errorCode = bind(socket, (sockaddr *)&addr, addressLen); + errorCode = bind(socket, (sockaddr *)&addr, addressLen); -return errorCode; + return errorCode; } int NETX_SOCKETS_Driver::Connect(SOCK_SOCKET socket, const SOCK_sockaddr *address, int addressLen) @@ -372,7 +372,7 @@ int NETX_SOCKETS_Driver::Close(SOCK_SOCKET socket) { NATIVE_PROFILE_PAL_NETWORK(); - errorCode = soc_close(socket); + errorCode = soc_close(socket); return errorCode; } @@ -381,9 +381,9 @@ int NETX_SOCKETS_Driver::Listen(SOCK_SOCKET socket, int backlog) { NATIVE_PROFILE_PAL_NETWORK(); -errorCode = listen(socket, backlog); + errorCode = listen(socket, backlog); -return errorCode; + return errorCode; } SOCK_SOCKET NETX_SOCKETS_Driver::Accept(SOCK_SOCKET socket, SOCK_sockaddr *address, int *addressLen) @@ -580,7 +580,7 @@ int NETX_SOCKETS_Driver::GetLastError() int NETX_SOCKETS_Driver::GetSockLastError(SOCK_SOCKET socket) { (void)socket; - + NATIVE_PROFILE_PAL_NETWORK(); // get last error number from socket @@ -884,10 +884,9 @@ int NETX_SOCKETS_Driver::SendTo( return sendto(socket, (CHAR *)buf, len, flags, (sockaddr *)&addr, tolen); } -// this implementation it's weak so it can be replaced at plaftorm level -__nfweak HRESULT NETX_SOCKETS_Driver::LoadAdapterConfiguration( - HAL_Configuration_NetworkInterface *config, - uint32_t interfaceIndex) +// this implementation it's weak so it can be replaced at plaftorm level +__nfweak HRESULT + NETX_SOCKETS_Driver::LoadAdapterConfiguration(HAL_Configuration_NetworkInterface *config, uint32_t interfaceIndex) { (void)interfaceIndex; @@ -950,13 +949,13 @@ struct dhcp_client_id uint8_t clientId[6]; }; -// this implementation it's weak so it can be replaced at plaftorm level +// this implementation it's weak so it can be replaced at plaftorm level __nfweak HRESULT NETX_SOCKETS_Driver::UpdateAdapterConfiguration( uint32_t interfaceIndex, uint32_t updateFlags, HAL_Configuration_NetworkInterface *config) { - (void) interfaceIndex; + (void)interfaceIndex; NATIVE_PROFILE_PAL_NETWORK(); @@ -1102,7 +1101,7 @@ int NETX_SOCKETS_Driver::GetNativeSockOption(int optname) nativeOptionName = SO_SNDBUF; break; // not supported - //case SOCK_SOCKO_ACCEPTCONNECTION: + // case SOCK_SOCKO_ACCEPTCONNECTION: // case SOCK_SOCKO_USELOOPBACK: case SOCK_SOCKO_DONTROUTE: nativeOptionName = SO_DONTROUTE; @@ -1146,9 +1145,9 @@ int NETX_SOCKETS_Driver::GetNativeIPOption(int optname) switch (optname) { - // not supported - // case SOCK_IPO_TTL: - // case SOCK_IPO_TOS: + // not supported + // case SOCK_IPO_TTL: + // case SOCK_IPO_TOS: case SOCK_IPO_MULTICAST_IF: nativeOptionName = IP_MULTICAST_IF; diff --git a/targets/AzureRTOS/_common/NetX/netx_sockets.h b/targets/AzureRTOS/_common/NetX/netx_sockets.h index ef37099613..e1fc80d71d 100644 --- a/targets/AzureRTOS/_common/NetX/netx_sockets.h +++ b/targets/AzureRTOS/_common/NetX/netx_sockets.h @@ -109,9 +109,9 @@ struct NETX_SOCKETS_Driver static HRESULT Link_status(uint32_t interfaceIndex, bool *status); - static HRESULT IPAddressFromString(const char *ipString, uint64_t *address); + static HRESULT IPV4AddressFromString(const char *ipString, uint64_t *address); - static const char *IPAddressToString(uint32_t address); + static const char *IPV4AddressToString(uint32_t address); static HRESULT LoadAdapterConfiguration(HAL_Configuration_NetworkInterface *config, uint32_t interfaceIndex); diff --git a/targets/AzureRTOS/_common/NetX/netx_sockets_functions.cpp b/targets/AzureRTOS/_common/NetX/netx_sockets_functions.cpp index 95c34d1fe2..9516db4e79 100644 --- a/targets/AzureRTOS/_common/NetX/netx_sockets_functions.cpp +++ b/targets/AzureRTOS/_common/NetX/netx_sockets_functions.cpp @@ -156,16 +156,16 @@ HRESULT HAL_SOCK_CONFIGURATION_Link_status(uint32_t interfaceIndex, bool *status return NETX_SOCKETS_Driver::Link_status(interfaceIndex, status); } -HRESULT HAL_SOCK_IPAddressFromString(const char *ipString, uint64_t *address) +HRESULT HAL_SOCK_IPV4AddressFromString(const char *ipString, uint64_t *address) { NATIVE_PROFILE_PAL_NETWORK(); - return NETX_SOCKETS_Driver::IPAddressFromString(ipString, address); + return NETX_SOCKETS_Driver::IPV4AddressFromString(ipString, address); } -const char *HAL_SOCK_IPAddressToString(uint32_t address) +const char *HAL_SOCK_IPV4AddressToString(uint32_t address) { NATIVE_PROFILE_PAL_NETWORK(); - return NETX_SOCKETS_Driver::IPAddressToString(address); + return NETX_SOCKETS_Driver::IPV4AddressToString(address); } void HAL_SOCK_EventsSet(uint32_t events) diff --git a/targets/AzureRTOS/_common/NetX/sockets_netx.cpp b/targets/AzureRTOS/_common/NetX/sockets_netx.cpp index 51afb68623..1d4d2dd138 100644 --- a/targets/AzureRTOS/_common/NetX/sockets_netx.cpp +++ b/targets/AzureRTOS/_common/NetX/sockets_netx.cpp @@ -206,18 +206,18 @@ HRESULT SOCK_CONFIGURATION_LinkStatus(uint32_t interfaceIndex, bool *status) return HAL_SOCK_CONFIGURATION_Link_status(interfaceIndex, status); } -HRESULT SOCK_IPAddressFromString(const char *ipString, uint64_t *address) +HRESULT SOCK_IPV4AddressFromString(const char *ipString, uint64_t *address) { NATIVE_PROFILE_PAL_COM(); - return HAL_SOCK_IPAddressFromString(ipString, address); + return HAL_SOCK_IPV4AddressFromString(ipString, address); } -const char *SOCK_IPAddressToString(uint32_t address) +const char *SOCK_IPV4AddressToString(uint32_t address) { NATIVE_PROFILE_PAL_COM(); - return HAL_SOCK_IPAddressToString(address); + return HAL_SOCK_IPV4AddressToString(address); } #define SOCKET_SHUTDOWN_READ 0 diff --git a/targets/ESP32/CMakePresets.json b/targets/ESP32/CMakePresets.json index 3254092df0..08f603621b 100644 --- a/targets/ESP32/CMakePresets.json +++ b/targets/ESP32/CMakePresets.json @@ -60,6 +60,28 @@ "API_nanoFramework.System.Text": "ON" } }, + { + "name": "ESP32_PSRAM_REV3_IPV6", + "inherits": [ + "xtensa-esp32-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "${presetName}", + "SDK_CONFIG_FILE": "sdkconfig.default_rev3_ipv6.esp32", + "NF_BUILD_RTM": "OFF", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "ON", + "API_System.IO.FileSystem": "ON", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON" + } + }, { "name": "ESP32_REV0", "inherits": [ diff --git a/targets/ESP32/_IDF/sdkconfig.default_rev3_ipv6.esp32 b/targets/ESP32/_IDF/sdkconfig.default_rev3_ipv6.esp32 new file mode 100644 index 0000000000..af5337ac7d --- /dev/null +++ b/targets/ESP32/_IDF/sdkconfig.default_rev3_ipv6.esp32 @@ -0,0 +1,1127 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_TARGET="esp32" +CONFIG_IDF_TARGET_ESP32=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000 + +# +# SDK tool configuration +# +CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-" +# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set +# end of SDK tool configuration + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# end of Build type + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_SUPPORTS_RSA=y +CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +# end of Security features + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B=y +# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_MONITOR_BAUD=921600 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +# default to 4mb partition table for nanoCLR +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/partitions_nanoclr_4mb.csv" +# CONFIG_PARTITION_TABLE_FILENAME is not set +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_TRAX is not set +CONFIG_APPTRACE_DEST_NONE=y +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + +CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 +CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 +CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 +CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 +CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 +CONFIG_BT_CTRL_MODE_EFF=1 +CONFIG_BT_CTRL_BLE_MAX_ACT=10 +CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 +CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 +CONFIG_BT_CTRL_PINNED_TO_CORE=0 +CONFIG_BT_CTRL_HCI_TL=1 +CONFIG_BT_CTRL_ADV_DUP_FILT_MAX=30 +CONFIG_BT_CTRL_HW_CCA_EFF=0 +CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF=0 +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP=y +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM=100 +CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 +CONFIG_BT_CTRL_BLE_SCAN_DUPL=y +CONFIG_BT_CTRL_SCAN_DUPL_TYPE=0 +CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE=100 +CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF=0 +CONFIG_BT_CTRL_SLEEP_MODE_EFF=0 +CONFIG_BT_CTRL_SLEEP_CLOCK_EFF=0 +CONFIG_BT_CTRL_HCI_TL_EFF=1 +CONFIG_BT_RESERVE_DRAM=0 +CONFIG_BT_NIMBLE_USE_ESP_TIMER=y + +# +# CoAP Configuration +# +CONFIG_COAP_MBEDTLS_PSK=y +# CONFIG_COAP_MBEDTLS_PKI is not set +# CONFIG_COAP_MBEDTLS_DEBUG is not set +CONFIG_COAP_LOG_DEFAULT_LEVEL=0 +# end of CoAP Configuration + +# +# Driver configurations +# + +# +# ADC configuration +# +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC_DISABLE_DAC=y +# end of ADC configuration + +# +# SPI configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI configuration + +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI configuration + +# +# UART configuration +# +CONFIG_UART_ISR_IN_IRAM=y +# end of UART configuration +# end of Driver configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP32-specific +# +CONFIG_ESP32_REV_MIN_3=y +CONFIG_ESP32_SPIRAM_SUPPORT=y +CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +CONFIG_SPIRAM_USE_MEMMAP=n +CONFIG_SPIRAM_USE_CAPS_ALLOC=n +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32=n +CONFIG_SPIRAM_TYPE_ESPPSRAM64=n +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +# CONFIG_SPIRAM_MEMTEST is not set +# CONFIG_SPIRAM_CACHE_WORKAROUND is not set +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=n +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=n + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# Cache config +# +CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set +# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S2_DATA_CACHE_0KB=y +# CONFIG_ESP32S2_DATA_CACHE_8KB is not set +# CONFIG_ESP32S2_DATA_CACHE_16KB is not set +# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set +# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set +# end of Cache config + +# CONFIG_ESP32S2_SPIRAM_SUPPORT is not set +# CONFIG_ESP32S2_TRAX is not set +CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2 +# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set +CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32S2_DEBUG_OCDAWARE=y +# CONFIG_ESP32S2_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S2_BROWNOUT_DET=y +CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP32S2_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 +# CONFIG_ESP32S2_NO_BLOBS is not set +# CONFIG_ESP32S2_KEEP_USB_ALIVE is not set +# CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set +# end of ESP32S2-specific + +# +# ADC-Calibration +# +# end of ADC-Calibration + +# config for XTAL freq +# adding it here, so it can be overriden by our CMake +CONFIG_ESP32_XTAL_FREQ_40=y + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_CDC is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +# CONFIG_ESP_TASK_WDT is not set +# CONFIG_ESP_TASK_WDT_PANIC is not set +# CONFIG_ESP_TASK_WDT_TIMEOUT_S is not set +# CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +# end of Common ESP-related + +# +# Ethernet +# +# Parameters configured in binutils.ESP32.CMAKE +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_ESP32_EMAC=y + +CONFIG_ETH_PHY_INTERFACE_RMII=y +# CONFIG_ETH_PHY_INTERFACE_MII is not set + +#CONFIG_ETH_RMII_CLK_OUTPUT=y +#CONFIG_ETH_RMII_CLK_OUT_GPIO=n +#CONFIG_ETH_RMII_CLK_INPUT=y +#CONFIG_ETH_RMII_CLK_IN_GPIO=n + +CONFIG_ETH_DMA_BUFFER_SIZE=512 +CONFIG_ETH_DMA_RX_BUFFER_NUM=10 +CONFIG_ETH_DMA_TX_BUFFER_NUM=10 + +# Include SPI drivers in case used in build +CONFIG_ETH_USE_SPI_ETHERNET=y +CONFIG_ETH_SPI_ETHERNET_DM9051=y +CONFIG_ETH_SPI_ETHERNET_W5500=y +CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL=y +#CONFIG_ETH_USE_OPENETH=n +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +# CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER is not set +# end of ESP NETIF Adapter + +# +# Power Management +# +CONFIG_PM_ENABLE=y +# end of Power Management + +# +# ESP System Settings +# +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=n +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y +CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_WIFI_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# end of Wi-Fi + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# end of PHY + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +# CONFIG_FATFS_LFN_NONE is not set +CONFIG_FATFS_LFN_HEAP=y +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +# end of FAT Filesystem support + +# +# Modbus configuration +# +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 +CONFIG_FMB_COMM_MODE_RTU_EN=y +CONFIG_FMB_COMM_MODE_ASCII_EN=y +CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_FMB_QUEUE_LENGTH=20 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 +CONFIG_FMB_SERIAL_BUF_SIZE=256 +CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 +CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 +CONFIG_FMB_PORT_TASK_PRIO=10 +CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 +CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_FMB_TIMER_PORT_ENABLED=y +CONFIG_FMB_TIMER_GROUP=0 +CONFIG_FMB_TIMER_INDEX=0 +# CONFIG_FMB_TIMER_ISR_IN_IRAM is not set +# end of Modbus configuration + +# +# FreeRTOS +# +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=5 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# end of Heap memory debugging + +# +# jsmn +# +# CONFIG_JSMN_PARENT_LINKS is not set +# CONFIG_JSMN_STRICT is not set +# end of jsmn + +# +# libsodium +# +# end of libsodium + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="nanodevice" +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=16 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +CONFIG_LWIP_SO_LINGER=y +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF=y +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=80 + +# +# DHCP server +# +# CONFIG_LWIP_DHCPS is not set +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=8 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +# CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC is not set +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=y +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +CONFIG_MBEDTLS_DYNAMIC_BUFFER=y +# CONFIG_MBEDTLS_DEBUG is not set +CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH=y +CONFIG_MBEDTLS_DYNAMIC_FREE_PEER_CERT=y +# CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE is not set + +# +# Certificate Bundle +# +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=n +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE=y +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_GCM=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE=y +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +CONFIG_MBEDTLS_SSL_PROTO_DTLS=y +CONFIG_MBEDTLS_SSL_ALPN=y +# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set +CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y +CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +CONFIG_MBEDTLS_DES_C=y +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +CONFIG_MBEDTLS_XTEA_C=y +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C=y + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +# CONFIG_MBEDTLS_PEM_WRITE_C is not set +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MDNS_TASK_PRIORITY=1 +CONFIG_MDNS_TASK_STACK_SIZE=4096 +# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_MDNS_TASK_AFFINITY_CPU0=y +CONFIG_MDNS_TASK_AFFINITY=0x0 +CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 +# CONFIG_MDNS_STRICT_MODE is not set +CONFIG_MDNS_TIMER_PERIOD_MS=100 +# end of mDNS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +# end of Newlib + +# +# NVS +# +# end of NVS + +# +# OpenSSL +# +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y +# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set +CONFIG_OPENSSL_ASSERT_EXIT=y +# end of OpenSSL + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=512 +CONFIG_SPIFFS_OBJ_NAME_LEN=256 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# end of Websocket +# end of TCP Transport + +# +# TinyUSB +# +# CONFIG_USB_ENABLED is not set +# end of TinyUSB + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# end of Supplicant +# end of Component config diff --git a/targets/ESP32/_common/targetHAL_Network.cpp b/targets/ESP32/_common/targetHAL_Network.cpp index c9d1ca6408..3e39a64dda 100644 --- a/targets/ESP32/_common/targetHAL_Network.cpp +++ b/targets/ESP32/_common/targetHAL_Network.cpp @@ -155,6 +155,15 @@ static void event_handler(void *arg, esp_event_base_t event_base, int32_t event_ case WIFI_EVENT_STA_CONNECTED: #ifdef PRINT_NET_EVENT ets_printf("WIFI_EVENT_STA_CONNECTED\n"); +#endif +#if LWIP_IPV6 + { + // Note: Did use esp_netif_create_ip6_linklocal originally but this failed because + // it tests for Netif to be up and didn't seem to be. Calling netif_create_ip6_linklocal_address + // directly seems to work fine. + struct netif *netif = esp_netif_get_handle_from_ifkey("WIFI_STA_DEF")->lwip_netif; + netif_create_ip6_linklocal_address(netif, 1); + } #endif if (NF_ESP32_ConnectInProgress) { @@ -304,6 +313,18 @@ static void event_handler(void *arg, esp_event_base_t event_base, int32_t event_ PostAddressChanged(IDF_ETH_DEF); initialize_sntp(); break; +#if LWIP_IPV6 + case IP_EVENT_GOT_IP6: +#ifdef PRINT_NET_EVENT + ip_event_got_ip6_t *event = (ip_event_got_ip6_t *)event_data; + esp_ip6_addr_type_t ipv6_type = esp_netif_ip6_get_addr_type(&event->ip6_info.ip); + ets_printf( + "IP_EVENT_ETH_GOT_IP6 type %d Adr %X:%X:%X:%X:%X:%X:%X:%X\n", + ipv6_type, + IPV62STR(event->ip6_info.ip)); +#endif + break; +#endif } } else if (event_base == ETH_EVENT) diff --git a/targets/TI_SimpleLink/_common/simplelink_sockets_functions.cpp b/targets/TI_SimpleLink/_common/simplelink_sockets_functions.cpp index 91bfae6864..ba9c6cb4c2 100644 --- a/targets/TI_SimpleLink/_common/simplelink_sockets_functions.cpp +++ b/targets/TI_SimpleLink/_common/simplelink_sockets_functions.cpp @@ -192,7 +192,13 @@ HRESULT HAL_SOCK_IPAddressFromString(const char *ipString, uint64_t *address) const char *HAL_SOCK_IPAddressToString(uint32_t address) { NATIVE_PROFILE_PAL_NETWORK(); - return LWIP_SOCKETS_Driver::IPAddressToString(address); + return LWIP_SOCKETS_Driver::IP4AddressToString(address); +} + +const char *HAL_SOCK_IP6AddressToString(uint16_t *address) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::IP6AddressToString(address); } void HAL_SOCK_EventsSet(uint32_t events) From aee9fd8d36255ddace2058c230bf33df45d5af74 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 17 Jan 2024 14:21:39 +0000 Subject: [PATCH 515/572] Improve devcontainer file structure (#2854) --- .devcontainer/{ => All}/Dockerfile.All | 0 .../Dockerfile.All => All/Dockerfile.All.SRC} | 0 .devcontainer/{ => All}/devcontainer.json | 10 +--- .../{ => All}/scripts/git-pull-repos.sh | 0 .../{ => All}/scripts/non-root-user.sh | 0 .../{ => AzureRTOS}/Dockerfile.AzureRTOS | 0 .../Dockerfile.AzureRTOS.SRC} | 0 .devcontainer/AzureRTOS/devcontainer.json | 48 +++++++++++++++++++ .../{ => ChibiOS}/Dockerfile.ChibiOS | 0 .../Dockerfile.ChibiOS.SRC} | 0 .devcontainer/ChibiOS/devcontainer.json | 48 +++++++++++++++++++ .devcontainer/{ => ESP32}/Dockerfile.ESP32 | 2 +- .../Dockerfile.ESP32.SRC} | 0 .devcontainer/ESP32/devcontainer.json | 48 +++++++++++++++++++ .devcontainer/README.md | 29 ++++++----- .devcontainer/{ => TI}/Dockerfile.TI | 0 .../Dockerfile.TI => TI/Dockerfile.TI.SRC} | 0 .devcontainer/TI/devcontainer.json | 48 +++++++++++++++++++ .github/workflows/devcontainer-all.yaml | 13 ++--- .github/workflows/devcontainer-azurertos.yaml | 13 ++--- .github/workflows/devcontainer-chibios.yaml | 13 ++--- .github/workflows/devcontainer-esp32.yml | 13 ++--- .github/workflows/devcontainer-smoketest.yaml | 10 ++-- .github/workflows/devcontainer-ti.yaml | 13 ++--- 24 files changed, 251 insertions(+), 57 deletions(-) rename .devcontainer/{ => All}/Dockerfile.All (100%) rename .devcontainer/{sources/Dockerfile.All => All/Dockerfile.All.SRC} (100%) rename .devcontainer/{ => All}/devcontainer.json (79%) rename .devcontainer/{ => All}/scripts/git-pull-repos.sh (100%) rename .devcontainer/{ => All}/scripts/non-root-user.sh (100%) rename .devcontainer/{ => AzureRTOS}/Dockerfile.AzureRTOS (100%) rename .devcontainer/{sources/Dockerfile.AzureRTOS => AzureRTOS/Dockerfile.AzureRTOS.SRC} (100%) create mode 100644 .devcontainer/AzureRTOS/devcontainer.json rename .devcontainer/{ => ChibiOS}/Dockerfile.ChibiOS (100%) rename .devcontainer/{sources/Dockerfile.ChibiOS => ChibiOS/Dockerfile.ChibiOS.SRC} (100%) create mode 100644 .devcontainer/ChibiOS/devcontainer.json rename .devcontainer/{ => ESP32}/Dockerfile.ESP32 (98%) rename .devcontainer/{sources/Dockerfile.ESP32 => ESP32/Dockerfile.ESP32.SRC} (100%) create mode 100644 .devcontainer/ESP32/devcontainer.json rename .devcontainer/{ => TI}/Dockerfile.TI (100%) rename .devcontainer/{sources/Dockerfile.TI => TI/Dockerfile.TI.SRC} (100%) create mode 100644 .devcontainer/TI/devcontainer.json diff --git a/.devcontainer/Dockerfile.All b/.devcontainer/All/Dockerfile.All similarity index 100% rename from .devcontainer/Dockerfile.All rename to .devcontainer/All/Dockerfile.All diff --git a/.devcontainer/sources/Dockerfile.All b/.devcontainer/All/Dockerfile.All.SRC similarity index 100% rename from .devcontainer/sources/Dockerfile.All rename to .devcontainer/All/Dockerfile.All.SRC diff --git a/.devcontainer/devcontainer.json b/.devcontainer/All/devcontainer.json similarity index 79% rename from .devcontainer/devcontainer.json rename to .devcontainer/All/devcontainer.json index 8b3b1617e4..2e10fe7514 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/All/devcontainer.json @@ -1,13 +1,7 @@ { - "name": "nanoFramework", - // Adjust this file to choose the platform you want using the prebuild containers: - // - Dockerfile.All = you can build anything but it's a very large container - // - Dockerfile.AzureRTOS = for AzureRTOS targets - // - Dockerfile.ChibiOS = for ChibiOS based targets (ex: STM32, Netduino, Orgpal) - // - Dockerfile.ESP32 = for ESP32 targets - // - Dockerfile.TI = for TI targets + "name": "nanoFramework-All", // If you prefer, you can use the source files and adjust them where they are located, - // To do this, prefix 'sources'. e.g. 'sources/Dockerfile.All'. + // To do this, change the "dockerFile" to use 'Dockerfile.All.SRC'. // This will allow you to customize and build the container source and add anything you may need on top. "dockerFile": "Dockerfile.All", "context": ".", diff --git a/.devcontainer/scripts/git-pull-repos.sh b/.devcontainer/All/scripts/git-pull-repos.sh similarity index 100% rename from .devcontainer/scripts/git-pull-repos.sh rename to .devcontainer/All/scripts/git-pull-repos.sh diff --git a/.devcontainer/scripts/non-root-user.sh b/.devcontainer/All/scripts/non-root-user.sh similarity index 100% rename from .devcontainer/scripts/non-root-user.sh rename to .devcontainer/All/scripts/non-root-user.sh diff --git a/.devcontainer/Dockerfile.AzureRTOS b/.devcontainer/AzureRTOS/Dockerfile.AzureRTOS similarity index 100% rename from .devcontainer/Dockerfile.AzureRTOS rename to .devcontainer/AzureRTOS/Dockerfile.AzureRTOS diff --git a/.devcontainer/sources/Dockerfile.AzureRTOS b/.devcontainer/AzureRTOS/Dockerfile.AzureRTOS.SRC similarity index 100% rename from .devcontainer/sources/Dockerfile.AzureRTOS rename to .devcontainer/AzureRTOS/Dockerfile.AzureRTOS.SRC diff --git a/.devcontainer/AzureRTOS/devcontainer.json b/.devcontainer/AzureRTOS/devcontainer.json new file mode 100644 index 0000000000..3d99e0e14b --- /dev/null +++ b/.devcontainer/AzureRTOS/devcontainer.json @@ -0,0 +1,48 @@ +{ + "name": "nanoFramework-AzureRTOS", + // If you prefer, you can use the source files and adjust them where they are located, + // To do this, change the "dockerFile" to use 'Dockerfile.AzureRTOS.SRC'. + // This will allow you to customize and build the container source and add anything you may need on top. + "dockerFile": "Dockerfile.AzureRTOS", + "context": ".", + "mounts": [ + // Bind the Unix socket the Docker daemon listens on by default + "source=/var/run/docker.sock,target=/var/run/docker.sock,type=bind", + // Keep command history + "source=nano-bashhistory,target=/home/vscode/commandhistory,type=volume", + // OPTIONAL: Mount .azure folder for seamless az cli auth + // "source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind" + ], + // Set the *default* container specific settings.json values on container create. + "customizations": { + "vscode": { + "settings": { + "cmake.preferredGenerators": [ + "Ninja" + ], + "cmake.generator": "Ninja", + "cmake.autoRestartBuild" : true, + "cmake.configureSettings": { + "CMAKE_MAKE_PROGRAM":"/usr/bin/ninja" + }, + "cmake.configureOnOpen": false + }, + // Add the IDs of extensions you want installed when the container is created. + "extensions": [ + "ms-vsliveshare.vsliveshare-pack", + "streetsidesoftware.code-spell-checker", + "twxs.cmake", + "ms-vscode.cmake-tools", + "xaver.clang-format" + ] + } + } + // You can pull all the repos with the latest changes, this is only valid if you are using the ./sources/Dockerfile.All containers + // "postAttachCommand": "/usr/local/git-pull-repos.sh" + // Use 'forwardPorts' to make a list of ports inside the container available locally. + // "forwardPorts": [], + // Use 'postCreateCommand' to run commands after the container is created. + // "postCreateCommand": "terraform --version", + // Uncomment to connect as a non-root user. See https: //aka.ms/vscode-remote/containers/non-root. + // ,"remoteUser": "vscode" +} diff --git a/.devcontainer/Dockerfile.ChibiOS b/.devcontainer/ChibiOS/Dockerfile.ChibiOS similarity index 100% rename from .devcontainer/Dockerfile.ChibiOS rename to .devcontainer/ChibiOS/Dockerfile.ChibiOS diff --git a/.devcontainer/sources/Dockerfile.ChibiOS b/.devcontainer/ChibiOS/Dockerfile.ChibiOS.SRC similarity index 100% rename from .devcontainer/sources/Dockerfile.ChibiOS rename to .devcontainer/ChibiOS/Dockerfile.ChibiOS.SRC diff --git a/.devcontainer/ChibiOS/devcontainer.json b/.devcontainer/ChibiOS/devcontainer.json new file mode 100644 index 0000000000..27f71f2f7f --- /dev/null +++ b/.devcontainer/ChibiOS/devcontainer.json @@ -0,0 +1,48 @@ +{ + "name": "nanoFramework-ChibiOS", + // Adjust this file to choose the platform you want using the prebuild containers: + // To do this, change the "dockerFile" to use 'Dockerfile.ChibiOS.SRC'. + // This will allow you to customize and build the container source and add anything you may need on top. + "dockerFile": "Dockerfile.ChibiOS", + "context": ".", + "mounts": [ + // Bind the Unix socket the Docker daemon listens on by default + "source=/var/run/docker.sock,target=/var/run/docker.sock,type=bind", + // Keep command history + "source=nano-bashhistory,target=/home/vscode/commandhistory,type=volume", + // OPTIONAL: Mount .azure folder for seamless az cli auth + // "source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind" + ], + // Set the *default* container specific settings.json values on container create. + "customizations": { + "vscode": { + "settings": { + "cmake.preferredGenerators": [ + "Ninja" + ], + "cmake.generator": "Ninja", + "cmake.autoRestartBuild" : true, + "cmake.configureSettings": { + "CMAKE_MAKE_PROGRAM":"/usr/bin/ninja" + }, + "cmake.configureOnOpen": false + }, + // Add the IDs of extensions you want installed when the container is created. + "extensions": [ + "ms-vsliveshare.vsliveshare-pack", + "streetsidesoftware.code-spell-checker", + "twxs.cmake", + "ms-vscode.cmake-tools", + "xaver.clang-format" + ] + } + } + // You can pull all the repos with the latest changes, this is only valid if you are using the ./sources/Dockerfile.All containers + // "postAttachCommand": "/usr/local/git-pull-repos.sh" + // Use 'forwardPorts' to make a list of ports inside the container available locally. + // "forwardPorts": [], + // Use 'postCreateCommand' to run commands after the container is created. + // "postCreateCommand": "terraform --version", + // Uncomment to connect as a non-root user. See https: //aka.ms/vscode-remote/containers/non-root. + // ,"remoteUser": "vscode" +} diff --git a/.devcontainer/Dockerfile.ESP32 b/.devcontainer/ESP32/Dockerfile.ESP32 similarity index 98% rename from .devcontainer/Dockerfile.ESP32 rename to .devcontainer/ESP32/Dockerfile.ESP32 index 64c9733403..71bde7bad9 100644 --- a/.devcontainer/Dockerfile.ESP32 +++ b/.devcontainer/ESP32/Dockerfile.ESP32 @@ -1 +1 @@ -FROM ghcr.io/nanoframework/dev-container-esp32:v2.28 +FROM ghcr.io/nanoframework/dev-container-esp32:v2.28 diff --git a/.devcontainer/sources/Dockerfile.ESP32 b/.devcontainer/ESP32/Dockerfile.ESP32.SRC similarity index 100% rename from .devcontainer/sources/Dockerfile.ESP32 rename to .devcontainer/ESP32/Dockerfile.ESP32.SRC diff --git a/.devcontainer/ESP32/devcontainer.json b/.devcontainer/ESP32/devcontainer.json new file mode 100644 index 0000000000..987eac7827 --- /dev/null +++ b/.devcontainer/ESP32/devcontainer.json @@ -0,0 +1,48 @@ +{ + "name": "nanoFramework-ESP32", + // Adjust this file to choose the platform you want using the prebuild containers: + // To do this, change the "dockerFile" to use 'Dockerfile.ESP32.SRC'. + // This will allow you to customize and build the container source and add anything you may need on top. + "dockerFile": "Dockerfile.ESP32", + "context": ".", + "mounts": [ + // Bind the Unix socket the Docker daemon listens on by default + "source=/var/run/docker.sock,target=/var/run/docker.sock,type=bind", + // Keep command history + "source=nano-bashhistory,target=/home/vscode/commandhistory,type=volume", + // OPTIONAL: Mount .azure folder for seamless az cli auth + // "source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind" + ], + // Set the *default* container specific settings.json values on container create. + "customizations": { + "vscode": { + "settings": { + "cmake.preferredGenerators": [ + "Ninja" + ], + "cmake.generator": "Ninja", + "cmake.autoRestartBuild" : true, + "cmake.configureSettings": { + "CMAKE_MAKE_PROGRAM":"/usr/bin/ninja" + }, + "cmake.configureOnOpen": false + }, + // Add the IDs of extensions you want installed when the container is created. + "extensions": [ + "ms-vsliveshare.vsliveshare-pack", + "streetsidesoftware.code-spell-checker", + "twxs.cmake", + "ms-vscode.cmake-tools", + "xaver.clang-format" + ] + } + } + // You can pull all the repos with the latest changes, this is only valid if you are using the ./sources/Dockerfile.All containers + // "postAttachCommand": "/usr/local/git-pull-repos.sh" + // Use 'forwardPorts' to make a list of ports inside the container available locally. + // "forwardPorts": [], + // Use 'postCreateCommand' to run commands after the container is created. + // "postCreateCommand": "terraform --version", + // Uncomment to connect as a non-root user. See https: //aka.ms/vscode-remote/containers/non-root. + // ,"remoteUser": "vscode" +} diff --git a/.devcontainer/README.md b/.devcontainer/README.md index 92a186a354..d380bc9bec 100644 --- a/.devcontainer/README.md +++ b/.devcontainer/README.md @@ -1,4 +1,4 @@ -# This folder contains all the elements used for .NET nanoFramework dev container +# This folder contains all the elements used for .NET nanoFramework dev containers You'll find Docker files for .NET nanoFramework. They are used to facilitate building images. @@ -10,18 +10,21 @@ The available pre build images are: * ghcr.io/nanoframework/dev-container-esp32: contains all elements to build a firmware image for any of the ESP32 targets * ghcr.io/nanoframework/dev-container-azure-rtos: contains all elements to build a firmware image for any of the Azure RTOS targets -To choose the dev container you want to use, adjust `devcontainer.json` and change the `"dockerFile": "Dockerfile"` elements for the image you'd liked to use: - -* `Dockerfile.All` to use the pre build container with all the elements to build a firmware image for any of the targets -* `Dockerfile.AzureRTOS` to use the pre build container with all the elements to build Azure RTOS targets -* `Dockerfile.ChibiOS` to use the pre build container with all the elements to build ChibiOS targets -* `Dockerfile.ESP32` to use the pre build container with all the elements to build ESP32 targets -* `Dockerfile.TI` to use the pre build container with all the elements to build TI SimpleLink targets -* `./sources/Dockerfile.All` to build the container image from the source with all the elements to build all the images -* `./sources/Dockerfile.AzureRTOS` to build the container image from the source with all the elements to build Azure RTOS based devices -* `./sources/Dockerfile.ChibiOS` to build the container image from the source with all the elements to build ChibiOS based devices -* `./sources/Dockerfile.ESP32` to build the container image from the source with all the elements to build ESP32 based devices -* `./sources/Dockerfile.TI` to build the container image from the source with all the elements to build TI SimpleLink based devices +You can choose the dev container needed when opening a remote container in VSCode. The options are: + +* `nanoFramework-All` to use the pre build container with all the elements to build a firmware image for any of the targets +* `nanoFramework-AzureRTOS` to use the pre build container with all the elements to build Azure RTOS targets +* `nanoFramework-ChibiOS` to use the pre build container with all the elements to build ChibiOS targets +* `nanoFramework-ESP32` to use the pre build container with all the elements to build ESP32 targets +* `nanoFramework-TI` to use the pre build container with all the elements to build TI SimpleLink targets + +To use the source dockerfile for the respective platform adjust its `devcontainer.json` file and change the `"dockerFile": "Dockerfile."` element for the image you would like to use: + +* `Dockerfile.All.SRC` to build the container image from the source with all the elements to build all the images +* `Dockerfile.AzureRTOS.SRC` to build the container image from the source with all the elements to build Azure RTOS based devices +* `Dockerfile.ChibiOS.SRC` to build the container image from the source with all the elements to build ChibiOS based devices +* `Dockerfile.ESP32.SRC` to build the container image from the source with all the elements to build ESP32 based devices +* `Dockerfile.TI.SRC` to build the container image from the source with all the elements to build TI SimpleLink based devices ## Building and releasing Docker images in a fork diff --git a/.devcontainer/Dockerfile.TI b/.devcontainer/TI/Dockerfile.TI similarity index 100% rename from .devcontainer/Dockerfile.TI rename to .devcontainer/TI/Dockerfile.TI diff --git a/.devcontainer/sources/Dockerfile.TI b/.devcontainer/TI/Dockerfile.TI.SRC similarity index 100% rename from .devcontainer/sources/Dockerfile.TI rename to .devcontainer/TI/Dockerfile.TI.SRC diff --git a/.devcontainer/TI/devcontainer.json b/.devcontainer/TI/devcontainer.json new file mode 100644 index 0000000000..7aa3122ef3 --- /dev/null +++ b/.devcontainer/TI/devcontainer.json @@ -0,0 +1,48 @@ +{ + "name": "nanoFramework-TI", + // Adjust this file to choose the platform you want using the prebuild containers: + // To do this, change the "dockerFile" to use 'Dockerfile.TI.SRC'. + // This will allow you to customize and build the container source and add anything you may need on top. + "dockerFile": "Dockerfile.TI", + "context": ".", + "mounts": [ + // Bind the Unix socket the Docker daemon listens on by default + "source=/var/run/docker.sock,target=/var/run/docker.sock,type=bind", + // Keep command history + "source=nano-bashhistory,target=/home/vscode/commandhistory,type=volume", + // OPTIONAL: Mount .azure folder for seamless az cli auth + // "source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind" + ], + // Set the *default* container specific settings.json values on container create. + "customizations": { + "vscode": { + "settings": { + "cmake.preferredGenerators": [ + "Ninja" + ], + "cmake.generator": "Ninja", + "cmake.autoRestartBuild" : true, + "cmake.configureSettings": { + "CMAKE_MAKE_PROGRAM":"/usr/bin/ninja" + }, + "cmake.configureOnOpen": false + }, + // Add the IDs of extensions you want installed when the container is created. + "extensions": [ + "ms-vsliveshare.vsliveshare-pack", + "streetsidesoftware.code-spell-checker", + "twxs.cmake", + "ms-vscode.cmake-tools", + "xaver.clang-format" + ] + } + } + // You can pull all the repos with the latest changes, this is only valid if you are using the ./sources/Dockerfile.All containers + // "postAttachCommand": "/usr/local/git-pull-repos.sh" + // Use 'forwardPorts' to make a list of ports inside the container available locally. + // "forwardPorts": [], + // Use 'postCreateCommand' to run commands after the container is created. + // "postCreateCommand": "terraform --version", + // Uncomment to connect as a non-root user. See https: //aka.ms/vscode-remote/containers/non-root. + // ,"remoteUser": "vscode" +} diff --git a/.github/workflows/devcontainer-all.yaml b/.github/workflows/devcontainer-all.yaml index 4f58abe8ad..a05b31a963 100644 --- a/.github/workflows/devcontainer-all.yaml +++ b/.github/workflows/devcontainer-all.yaml @@ -4,8 +4,9 @@ name: Build Dev Container for all platforms env: - GCR_IMAGE: ghcr.io/nanoframework/dev-container-all - GCR_FILE: .devcontainer/sources/Dockerfile.All + CONTAINER_REPO: ghcr.io + CONTAINER_NAME: dev-container-all + CONTAINER_SRC_FILE: .devcontainer/All/Dockerfile.All.SRC on: push: @@ -27,7 +28,7 @@ jobs: - name: Get container version run: | - $dockerfileContent = Get-Content(".devcontainer/Dockerfile.All") + $dockerfileContent = Get-Content(".devcontainer/All/Dockerfile.All") $dockerfileContent -match '(?<=\:)(?:[v]\d+.\d+)' $containerVersion = $Matches[0].ToString() echo "GCR_VERSION=$containerVersion" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append @@ -46,8 +47,8 @@ jobs: - name: Build and Push Docker Image uses: docker/build-push-action@v5 with: - file: ${{ env.GCR_FILE }} + file: ${{ env.CONTAINER_SRC_FILE }} push: true # Will only build if this is not here tags: | - ${{ env.GCR_IMAGE }}:${{ env.GCR_VERSION }} - ${{ env.GCR_IMAGE }}:latest + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:${{ env.GCR_VERSION }} + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:latest diff --git a/.github/workflows/devcontainer-azurertos.yaml b/.github/workflows/devcontainer-azurertos.yaml index a7bbd3256a..a843611501 100644 --- a/.github/workflows/devcontainer-azurertos.yaml +++ b/.github/workflows/devcontainer-azurertos.yaml @@ -4,8 +4,9 @@ name: Build Dev Container for Azure RTOS env: - GCR_IMAGE: ghcr.io/nanoframework/dev-container-azure-rtos - GCR_FILE: .devcontainer/sources/Dockerfile.AzureRTOS + CONTAINER_REPO: ghcr.io + CONTAINER_NAME: dev-container-azure-rtos + CONTAINER_SRC_FILE: .devcontainer/AzureRTOS/Dockerfile.AzureRTOS.SRC on: push: @@ -27,7 +28,7 @@ jobs: - name: Get container version run: | - $dockerfileContent = Get-Content(".devcontainer/Dockerfile.AzureRTOS") + $dockerfileContent = Get-Content(".devcontainer/AzureRTOS/Dockerfile.AzureRTOS") $dockerfileContent -match '(?<=\:)(?:[v]\d+.\d+)' $containerVersion = $Matches[0].ToString() echo "GCR_VERSION=$containerVersion" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append @@ -46,9 +47,9 @@ jobs: - name: Build and Push Docker Image uses: docker/build-push-action@v5 with: - file: ${{ env.GCR_FILE }} + file: ${{ env.CONTAINER_SRC_FILE }} push: true # Will only build if this is not here tags: | - ${{ env.GCR_IMAGE }}:${{ env.GCR_VERSION }} - ${{ env.GCR_IMAGE }}:latest + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:${{ env.GCR_VERSION }} + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:latest \ No newline at end of file diff --git a/.github/workflows/devcontainer-chibios.yaml b/.github/workflows/devcontainer-chibios.yaml index ba220c5562..52f4bf4471 100644 --- a/.github/workflows/devcontainer-chibios.yaml +++ b/.github/workflows/devcontainer-chibios.yaml @@ -4,8 +4,9 @@ name: Build Dev Container for ChibiOS env: - GCR_IMAGE: ghcr.io/nanoframework/dev-container-chibios - GCR_FILE: .devcontainer/sources/Dockerfile.ChibiOS + CONTAINER_REPO: ghcr.io + CONTAINER_NAME: dev-container-chibios + CONTAINER_SRC_FILE: .devcontainer/ChibiOS/Dockerfile.ChibiOS.SRC on: push: @@ -27,7 +28,7 @@ jobs: - name: Get container version run: | - $dockerfileContent = Get-Content(".devcontainer/Dockerfile.ChibiOS") + $dockerfileContent = Get-Content(".devcontainer/ChibiOS/Dockerfile.ChibiOS") $dockerfileContent -match '(?<=\:)(?:[v]\d+.\d+)' $containerVersion = $Matches[0].ToString() echo "GCR_VERSION=$containerVersion" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append @@ -46,8 +47,8 @@ jobs: - name: Build and Push Docker Image uses: docker/build-push-action@v5 with: - file: ${{ env.GCR_FILE }} + file: ${{ env.CONTAINER_SRC_FILE }} push: true # Will only build if this is not here tags: | - ${{ env.GCR_IMAGE }}:${{ env.GCR_VERSION }} - ${{ env.GCR_IMAGE }}:latest + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:${{ env.GCR_VERSION }} + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:latest diff --git a/.github/workflows/devcontainer-esp32.yml b/.github/workflows/devcontainer-esp32.yml index c904c8623c..327c3fb794 100644 --- a/.github/workflows/devcontainer-esp32.yml +++ b/.github/workflows/devcontainer-esp32.yml @@ -4,8 +4,9 @@ name: Build Dev Container for ESP32 env: - GCR_IMAGE: ghcr.io/nanoframework/dev-container-esp32 - GCR_FILE: .devcontainer/sources/Dockerfile.ESP32 + CONTAINER_REPO: ghcr.io + CONTAINER_NAME: dev-container-esp32 + CONTAINER_SRC_FILE: .devcontainer/ESP32/Dockerfile.ESP32.SRC on: push: @@ -27,7 +28,7 @@ jobs: - name: Get container version run: | - $dockerfileContent = Get-Content(".devcontainer/Dockerfile.ESP32") + $dockerfileContent = Get-Content(".devcontainer/ESP32/Dockerfile.ESP32") $dockerfileContent -match '(?<=\:)(?:[v]\d+.\d+)' $containerVersion = $Matches[0].ToString() echo "GCR_VERSION=$containerVersion" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append @@ -46,8 +47,8 @@ jobs: - name: Build and Push Docker Image uses: docker/build-push-action@v5 with: - file: ${{ env.GCR_FILE }} + file: ${{ env.CONTAINER_SRC_FILE }} push: true # Will only build if this is not here tags: | - ${{ env.GCR_IMAGE }}:${{ env.GCR_VERSION }} - ${{ env.GCR_IMAGE }}:latest + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:${{ env.GCR_VERSION }} + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:latest diff --git a/.github/workflows/devcontainer-smoketest.yaml b/.github/workflows/devcontainer-smoketest.yaml index 34297c39b2..1c7863d17f 100644 --- a/.github/workflows/devcontainer-smoketest.yaml +++ b/.github/workflows/devcontainer-smoketest.yaml @@ -3,11 +3,11 @@ name: Smoketest Dockerfile builds for selected targets on: pull_request: paths: - - '.devcontainer/sources/*' + - '.devcontainer/**/*' - '.github/workflows/*' # push: # paths: - # - '.devcontainer/sources/*' + # - '.devcontainer/**/*' # - '.github/workflows/*' jobs: @@ -61,10 +61,10 @@ jobs: - name: Adjust devcontainer.json for ${{ matrix.container }} source run: | # Move into the .devcontainer directory - pushd .devcontainer + pushd .devcontainer/${{ matrix.container }} # Target the dockerfile source. - sed -i -- 's|"dockerFile": "Dockerfile.All"|"dockerFile": "sources/Dockerfile.${{ matrix.container }}"|g' devcontainer.json + sed -i -- 's|"dockerFile": "Dockerfile.${{ matrix.container }}"|"dockerFile": "Dockerfile.${{ matrix.container }}.SRC"|g' devcontainer.json # Move out of the .devcontainer directory popd @@ -72,9 +72,9 @@ jobs: - name: Build ${{ matrix.target }} ${{ matrix.build-type }} Firmware uses: devcontainers/ci@v0.3 with: + configFile: ./.devcontainer/${{ matrix.container }}/devcontainer.json push: never runCmd: | # Build target: cmake --preset=${{ matrix.target }} -DCMAKE_BUILD_TYPE=${{ matrix.build-type }} cmake --build build - diff --git a/.github/workflows/devcontainer-ti.yaml b/.github/workflows/devcontainer-ti.yaml index 2b483ad17a..4baf392cd2 100644 --- a/.github/workflows/devcontainer-ti.yaml +++ b/.github/workflows/devcontainer-ti.yaml @@ -4,8 +4,9 @@ name: Build Dev Container for TI env: - GCR_IMAGE: ghcr.io/nanoframework/dev-container-ti - GCR_FILE: .devcontainer/sources/Dockerfile.TI + CONTAINER_REPO: ghcr.io + CONTAINER_NAME: dev-container-ti + CONTAINER_SRC_FILE: .devcontainer/TI/Dockerfile.TI.SRC on: push: @@ -27,7 +28,7 @@ jobs: - name: Get container version run: | - $dockerfileContent = Get-Content(".devcontainer/Dockerfile.TI") + $dockerfileContent = Get-Content(".devcontainer/TI/Dockerfile.TI") $dockerfileContent -match '(?<=\:)(?:[v]\d+.\d+)' $containerVersion = $Matches[0].ToString() echo "GCR_VERSION=$containerVersion" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append @@ -46,8 +47,8 @@ jobs: - name: Build and Push Docker Image uses: docker/build-push-action@v5 with: - file: ${{ env.GCR_FILE }} + file: ${{ env.CONTAINER_SRC_FILE }} push: true # Will only build if this is not here tags: | - ${{ env.GCR_IMAGE }}:${{ env.GCR_VERSION }} - ${{ env.GCR_IMAGE }}:latest + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:${{ env.GCR_VERSION }} + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:latest From e34bd690e217657c8208d3ca546e1f41fd283d05 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 17 Jan 2024 15:46:45 +0000 Subject: [PATCH 516/572] Add FreeRTOS NXP container (#2855) --- .../FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP | 3 + .../FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP.SRC | 86 +++++++++++++++++++ .devcontainer/FreeRTOS-NXP/devcontainer.json | 48 +++++++++++ .devcontainer/README.md | 3 + .../workflows/devcontainer-freertos-nxp.yaml | 59 +++++++++++++ .github/workflows/devcontainer-smoketest.yaml | 2 +- 6 files changed, 200 insertions(+), 1 deletion(-) create mode 100644 .devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP create mode 100644 .devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP.SRC create mode 100644 .devcontainer/FreeRTOS-NXP/devcontainer.json create mode 100644 .github/workflows/devcontainer-freertos-nxp.yaml diff --git a/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP b/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP new file mode 100644 index 0000000000..7d6b9c33ef --- /dev/null +++ b/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP @@ -0,0 +1,3 @@ +FROM ghcr.io/nanoframework/dev-container-freertos-nxp:v1.01 +LABEL org.website="https://nanoframework.net/" +LABEL description="This is dockerfile image for NXP targets" diff --git a/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP.SRC b/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP.SRC new file mode 100644 index 0000000000..a9ea4281fe --- /dev/null +++ b/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP.SRC @@ -0,0 +1,86 @@ +FROM ubuntu:latest AS downloader +RUN apt-get update \ + && apt-get -y install --no-install-recommends apt-utils \ + && apt-get install -y \ + curl \ + xz-utils \ + unzip \ + wget + +RUN mkdir -p /tmp/dc-downloads /tmp/dc-extracted + +ARG GCC_VERSION=13.2.rel1 +ARG GCC_URI=https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu/$GCC_VERSION/binrel/arm-gnu-toolchain-$GCC_VERSION-x86_64-arm-none-eabi.tar.xz +RUN mkdir -p /tmp/dc-downloads /tmp/dc-extracted/gcc \ + && curl -o /tmp/dc-downloads/gcc-arm.tar.xz $GCC_URI \ + && xz -d /tmp/dc-downloads/gcc-arm.tar.xz \ + && tar -xvf /tmp/dc-downloads/gcc-arm.tar -C /tmp/dc-extracted/gcc --strip-components 1 \ + && rm -rf /tmp/dc-extracted/gcc/share/doc/ /tmp/dc-extracted/gcc/share/gcc-arm-none-eabi/samples/ + +ARG CMAKE_VERSION=3.27.6 +ARG CMAKE_SCRIPT=https://github.com/Kitware/CMake/releases/download/v$CMAKE_VERSION/cmake-$CMAKE_VERSION-linux-x86_64.sh +RUN wget $CMAKE_SCRIPT \ + -q -O /tmp/dc-downloads/cmake-install.sh \ + && chmod u+x /tmp/dc-downloads/cmake-install.sh \ + && mkdir -p /tmp/dc-extracted/cmake \ + && /tmp/dc-downloads/cmake-install.sh --skip-license --prefix=/tmp/dc-extracted/cmake \ + && rm /tmp/dc-downloads/cmake-install.sh + +FROM python:3.10 AS devcontainer + +# Avoid warnings by switching to noninteractive +ENV DEBIAN_FRONTEND=noninteractive + +# You can set up non-root user +# ARG USERNAME=vscode +# ARG USER_UID=1000 +# ARG USER_GID=$USER_UID + +# Configure apt and install packages +RUN apt-get update \ + && apt-get -y install --no-install-recommends apt-utils dialog icu-devtools 2>&1 \ + && apt-get install -y \ + git \ + git-lfs \ + git-svn \ + subversion \ + clang-format \ + curl \ + ninja-build \ + srecord \ + nodejs \ + libffi-dev + +# Create needed directories +RUN mkdir -p /usr/local/bin/gcc + +# Clone libs mbedtls and fatfs etc. +RUN git clone --branch mbedtls-2.28.5 https://github.com/ARMmbed/mbedtls.git --depth 1 ./sources/mbedtls \ + && git clone --branch R0.15 https://github.com/abbrev/fatfs.git --depth 1 ./sources/fatfs \ + && git clone --branch STABLE-2_1_3_RELEASE https://github.com/lwip-tcpip/lwip.git --depth 1 ./sources/lwip + +# Clone FreeRTOS +RUN git clone --branch V10.4.1-kernel-only https://github.com/FreeRTOS/FreeRTOS-Kernel.git --depth 1 ./sources/FreeRTOS \ + && git clone --branch 5.5.1 https://github.com/ARM-software/CMSIS_5.git --depth 1 ./sources/CMSIS_5 + +# set gcc location +ARG TMP_GCC_PATH=/usr/local/bin/gcc +ENV ARM_GCC_PATH=$TMP_GCC_PATH/bin + +# Copy from our other container +COPY --from=downloader /tmp/dc-extracted/gcc $TMP_GCC_PATH +COPY --from=downloader /tmp/dc-extracted/cmake /usr/bin/cmake + +ENV PATH=/usr/bin/cmake/bin:${PATH} + +# Creating static link python for pyhton3 +RUN ln -fs /usr/bin/python3 /usr/bin/python \ + && pip3 install pyserial + +# Clean up downloaded files +RUN apt-get autoremove -y \ + && apt-get clean -y \ + && rm -rf /var/lib/apt/lists/* + +# Switch back to dialog for any ad-hoc use of apt-get +ENV DEBIAN_FRONTEND=dialog diff --git a/.devcontainer/FreeRTOS-NXP/devcontainer.json b/.devcontainer/FreeRTOS-NXP/devcontainer.json new file mode 100644 index 0000000000..7be0828ab6 --- /dev/null +++ b/.devcontainer/FreeRTOS-NXP/devcontainer.json @@ -0,0 +1,48 @@ +{ + "name": "nanoFramework-FreeRTOS-NXP", + // If you prefer, you can use the source files and adjust them where they are located, + // To do this, change the "dockerFile" to use 'Dockerfile.NXP.SRC'. + // This will allow you to customize and build the container source and add anything you may need on top. + "dockerFile": "Dockerfile.FreeRTOS-NXP", + "context": ".", + "mounts": [ + // Bind the Unix socket the Docker daemon listens on by default + "source=/var/run/docker.sock,target=/var/run/docker.sock,type=bind", + // Keep command history + "source=nano-bashhistory,target=/home/vscode/commandhistory,type=volume", + // OPTIONAL: Mount .azure folder for seamless az cli auth + // "source=${env:HOME}${env:USERPROFILE}/.azure,target=/home/vscode/.azure,type=bind" + ], + // Set the *default* container specific settings.json values on container create. + "customizations": { + "vscode": { + "settings": { + "cmake.preferredGenerators": [ + "Ninja" + ], + "cmake.generator": "Ninja", + "cmake.autoRestartBuild" : true, + "cmake.configureSettings": { + "CMAKE_MAKE_PROGRAM":"/usr/bin/ninja" + }, + "cmake.configureOnOpen": false + }, + // Add the IDs of extensions you want installed when the container is created. + "extensions": [ + "ms-vsliveshare.vsliveshare-pack", + "streetsidesoftware.code-spell-checker", + "twxs.cmake", + "ms-vscode.cmake-tools", + "xaver.clang-format" + ] + } + } + // You can pull all the repos with the latest changes, this is only valid if you are using the ./sources/Dockerfile.All containers + // "postAttachCommand": "/usr/local/git-pull-repos.sh" + // Use 'forwardPorts' to make a list of ports inside the container available locally. + // "forwardPorts": [], + // Use 'postCreateCommand' to run commands after the container is created. + // "postCreateCommand": "terraform --version", + // Uncomment to connect as a non-root user. See https: //aka.ms/vscode-remote/containers/non-root. + // ,"remoteUser": "vscode" +} diff --git a/.devcontainer/README.md b/.devcontainer/README.md index d380bc9bec..ed849679ac 100644 --- a/.devcontainer/README.md +++ b/.devcontainer/README.md @@ -9,6 +9,7 @@ The available pre build images are: * ghcr.io/nanoframework/dev-container-ti: contains all elements to build a firmware image for any of the TI SimpleLink targets * ghcr.io/nanoframework/dev-container-esp32: contains all elements to build a firmware image for any of the ESP32 targets * ghcr.io/nanoframework/dev-container-azure-rtos: contains all elements to build a firmware image for any of the Azure RTOS targets +* ghcr.io/nanoframework/dev-container-freertos-nxp: contains all elements to build a firmware image for any of the NXP targets You can choose the dev container needed when opening a remote container in VSCode. The options are: @@ -17,6 +18,7 @@ You can choose the dev container needed when opening a remote container in VSCod * `nanoFramework-ChibiOS` to use the pre build container with all the elements to build ChibiOS targets * `nanoFramework-ESP32` to use the pre build container with all the elements to build ESP32 targets * `nanoFramework-TI` to use the pre build container with all the elements to build TI SimpleLink targets +* `nanoFramework-FreeRTOS-NXP` to use the pre build container with all the elements to build TI SimpleLink targets To use the source dockerfile for the respective platform adjust its `devcontainer.json` file and change the `"dockerFile": "Dockerfile."` element for the image you would like to use: @@ -25,6 +27,7 @@ To use the source dockerfile for the respective platform adjust its `devcontaine * `Dockerfile.ChibiOS.SRC` to build the container image from the source with all the elements to build ChibiOS based devices * `Dockerfile.ESP32.SRC` to build the container image from the source with all the elements to build ESP32 based devices * `Dockerfile.TI.SRC` to build the container image from the source with all the elements to build TI SimpleLink based devices +* `Dockerfile.FreeRTOS.NXP.SRC` to build the container image from the source with all the elements to build NXP based devices ## Building and releasing Docker images in a fork diff --git a/.github/workflows/devcontainer-freertos-nxp.yaml b/.github/workflows/devcontainer-freertos-nxp.yaml new file mode 100644 index 0000000000..20baaf3216 --- /dev/null +++ b/.github/workflows/devcontainer-freertos-nxp.yaml @@ -0,0 +1,59 @@ +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. + +name: Push Docker image [FreeRTOS-NXP] + +env: + CONTAINER_REPO: ghcr.io + CONTAINER_NAME: dev-container-freertos-nxp + CONTAINER_SOURCE_FILE: .devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP.SRC + CONTAINER_VERSION_FILE: .devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP + +on: + push: + branches: + - main + paths: + - '**Dockerfile.FreeRTOS-NXP' # We only care if the version has changed! + + workflow_dispatch: + +jobs: + build: + if: ${{ vars.PUBLISH_DOCKER_IMAGE == 'true' }} + runs-on: ubuntu-latest + permissions: + contents: read + packages: write + + steps: + - name: Checkout Repository + uses: actions/checkout@v4 + + - name: Get container version + shell: pwsh + run: | + $dockerfileContent = Get-Content("${{ env.CONTAINER_VERSION_FILE }}") + $dockerfileContent -match '(?<=\:)(?:[v]\d+.\d+)' + $containerVersion = $Matches[0].ToString() + echo "GCR_VERSION=$containerVersion" | Out-File -FilePath $Env:GITHUB_ENV -Encoding utf-8 -Append + + - name: Set up Docker Buildx + uses: docker/setup-buildx-action@v3 + + - name: Login to GitHub Container Registry + if: ${{ github.event_name != 'pull_request' }} + uses: docker/login-action@v3 + with: + registry: ${{ env.CONTAINER_REPO }} + username: ${{ github.repository_owner }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Build and Push Docker Image + uses: docker/build-push-action@v5 + with: + file: ${{ env.CONTAINER_SOURCE_FILE }} + push: ${{ github.event_name != 'pull_request' }} + tags: | + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:${{ env.GCR_VERSION }} + ${{ env.CONTAINER_REPO }}/${{ github.repository_owner }}/${{ env.CONTAINER_NAME }}:latest diff --git a/.github/workflows/devcontainer-smoketest.yaml b/.github/workflows/devcontainer-smoketest.yaml index 1c7863d17f..aaa8a03eb8 100644 --- a/.github/workflows/devcontainer-smoketest.yaml +++ b/.github/workflows/devcontainer-smoketest.yaml @@ -23,7 +23,7 @@ jobs: { target: ST_STM32F769I_DISCOVERY, build-type: Debug, container: All }, { target: M5Core2, build-type: Debug, container: ESP32 }, { target: M5Core2, build-type: Debug, container: All }, - # { target: NXP_MIMXRT1060_EVK, build-type: Debug, container: FreeRTOS }, # No FreeRTOS container yet. + { target: NXP_MIMXRT1060_EVK, build-type: Debug, container: FreeRTOS-NXP }, { target: NXP_MIMXRT1060_EVK, build-type: Debug, container: All }, { target: TI_CC1352R1_LAUNCHXL, build-type: Debug, container: TI, radio-freq: 915 }, { target: TI_CC1352R1_LAUNCHXL, build-type: Debug, container: All, radio-freq: 915 }, From f0a24b5f0ec086769b6a3ac24fa06199892fbdba Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Wed, 17 Jan 2024 16:09:13 +0000 Subject: [PATCH 517/572] Remove meta labels from Dockerfile.FreeRTOS-NXP (#2869) --- .devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP | 2 -- 1 file changed, 2 deletions(-) diff --git a/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP b/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP index 7d6b9c33ef..6d7262c824 100644 --- a/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP +++ b/.devcontainer/FreeRTOS-NXP/Dockerfile.FreeRTOS-NXP @@ -1,3 +1 @@ FROM ghcr.io/nanoframework/dev-container-freertos-nxp:v1.01 -LABEL org.website="https://nanoframework.net/" -LABEL description="This is dockerfile image for NXP targets" From f655db579a19bf21e50a5547b272330008d71fb9 Mon Sep 17 00:00:00 2001 From: alberk8 Date: Mon, 22 Jan 2024 21:42:51 +0800 Subject: [PATCH 518/572] Fix PWM for esp32 (#2870) Co-authored-by: nfbot --- ...wm_native_System_Device_Pwm_PwmChannel.cpp | 189 +++++++++++++----- 1 file changed, 136 insertions(+), 53 deletions(-) diff --git a/targets/ESP32/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp b/targets/ESP32/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp index 17fd618c1c..f64d5b7477 100644 --- a/targets/ESP32/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp +++ b/targets/ESP32/_nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp @@ -46,8 +46,10 @@ namespace sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers uint32_t PwmController_Timer_resolution[8]; int GetChannel(int pin, int timerId, bool create); -uint32_t CalculateDuty(int timerId, uint32_t dutyCycle, PwmPulsePolarity polarity); +uint32_t CalculateDuty(int timerId, uint32_t dutyCycle); HRESULT ConfigureAndStart(CLR_RT_HeapBlock *pThis, bool create, bool noStart); +int32_t GetOptimumResolution(int32_t desiredFrequency); +esp_err_t SetDutyCycle(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t dutyCycle); } // namespace sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers using namespace sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers; @@ -94,20 +96,13 @@ int sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::GetChannel(int pin, // // Work out the duty Cycle for the current duty resolution and polarity // -uint32_t sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::CalculateDuty( - int timerId, - uint32_t dutyCycle, - PwmPulsePolarity polarity) +uint32_t sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::CalculateDuty(int timerId, uint32_t dutyCycle) { - // if polarity Active low then reverse duty cycle - if (polarity == PwmPulsePolarity::PwmPulsePolarity_ActiveLow) + uint32_t calculatedDuty = 0; + if (PwmController_Timer_resolution[timerId] > 0) { - dutyCycle = 10000 - dutyCycle; + calculatedDuty = PwmController_Timer_resolution[timerId] * dutyCycle / 10000; } - - // Return a duty cycle in the range of the current timer duty resolution - uint32_t calculatedDuty = PwmController_Timer_resolution[timerId] * dutyCycle / 10000; - return calculatedDuty; } @@ -126,6 +121,11 @@ HRESULT sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::ConfigureAndStar ledc_channel_t channel; ledc_timer_t timer_sel; ledc_channel_config_t ledc_conf; + ledc_timer_config_t timer_conf; + esp_err_t result; + int32_t desiredFrequency; + int32_t optimumDutyResolution; + ledc_timer_bit_t duty_res; NANOCLR_HEADER(); @@ -136,6 +136,8 @@ HRESULT sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::ConfigureAndStar polarity = (PwmPulsePolarity)(pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___polarity] .NumericByRef() .u4); + desiredFrequency = + pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___frequency].NumericByRef().u4; // Configure channel mode = GetSpeedMode(timerId); @@ -149,10 +151,26 @@ HRESULT sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::ConfigureAndStar timer_sel = (ledc_timer_t)(timerId & 0x03); + optimumDutyResolution = GetOptimumResolution(desiredFrequency); + + // Save resolution for working out values for percent duty cycle + PwmController_Timer_resolution[timerId] = (0x1 << optimumDutyResolution); + + duty_res = (ledc_timer_bit_t)optimumDutyResolution; + + timer_conf = {mode, duty_res, timer_sel, (uint32_t)desiredFrequency, LEDC_AUTO_CLK}; + + result = ledc_timer_config(&timer_conf); + + if (result != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + // Work out the duty Cycle for the current duty resolution - dutyCycle = CalculateDuty(timerId, dutyCycle, polarity); + dutyCycle = CalculateDuty(timerId, dutyCycle); - ledc_conf = {pinNumber, mode, channel, LEDC_INTR_DISABLE, timer_sel, dutyCycle, 0, 0}; + ledc_conf = {pinNumber, mode, channel, LEDC_INTR_DISABLE, timer_sel, dutyCycle, 0, (unsigned int)polarity}; // Configure Channel which will also start it IDF_ERROR(ledc_channel_config(&ledc_conf)); @@ -166,9 +184,53 @@ HRESULT sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::ConfigureAndStar NANOCLR_NOCLEANUP(); } +int32_t sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::GetOptimumResolution(int32_t desiredFrequency) +{ + uint64_t divParam; + int32_t optimumDutyResolution; + uint32_t precision; + + optimumDutyResolution = 1; + + for (int dutyResolution = SOC_LEDC_TIMER_BIT_WIDE_NUM - 1; dutyResolution > 0; dutyResolution--) + { + precision = (0x1 << dutyResolution); // 2**depth + + divParam = ((uint64_t)LEDC_APB_CLK_HZ << 8) / desiredFrequency / precision; + + if (divParam > 256) + { + optimumDutyResolution = dutyResolution; + break; + } + } + + return optimumDutyResolution; +} + +esp_err_t sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::SetDutyCycle( + ledc_mode_t speed_mode, + ledc_channel_t channel, + uint32_t dutyCycle) +{ + esp_err_t err; + + err = ledc_set_duty(speed_mode, channel, dutyCycle); + if (err != ESP_OK) + { + return err; + } + // Activate duty on channel + err = ledc_update_duty(speed_mode, channel); + + return err; +} + HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeInit___VOID(CLR_RT_StackFrame &stack) { int32_t pinNumber; + int32_t timerId; + ledc_channel_t channel; NANOCLR_HEADER(); @@ -178,14 +240,18 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeInit___VO // Check pin number is a valid for output pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; if (!GPIO_IS_VALID_OUTPUT_GPIO(pinNumber)) { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // Create a new entry in channel table and configure channel which will also start channel - NANOCLR_CHECK_HRESULT(ConfigureAndStart(pThis, true, true)); + channel = (ledc_channel_t)GetChannel(pinNumber, timerId, true); + if (channel == -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } NANOCLR_NOCLEANUP(); } @@ -196,14 +262,15 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetDesire int32_t timerId; int32_t desiredFrequency; int32_t optimumDutyResolution; - uint32_t precision; - uint64_t divParam; esp_err_t result; ledc_timer_t timer; ledc_mode_t mode; ledc_timer_bit_t duty_res; ledc_timer_config_t timer_conf; + int32_t pinNumber; + ledc_channel_t channel; + uint32_t dutyCycle; NANOCLR_HEADER(); @@ -214,6 +281,18 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetDesire // Retrieves the needed parameters from private class properties ( 0 - 7 ) timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; desiredFrequency = stack.Arg1().NumericByRef().s4; + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + mode = GetSpeedMode(timerId); + channel = (ledc_channel_t)GetChannel(pinNumber, timerId, false); + dutyCycle = pThis[FIELD___dutyCycle].NumericByRef().u4; + + // Set the backing frequency field when it is zero and return + // We need this as this native function is called before Init + if (channel == -1) + { + pThis[FIELD___frequency].NumericByRef().s4 = desiredFrequency; + NANOCLR_SET_AND_LEAVE(S_OK); + } // parameter check if (desiredFrequency < 0) @@ -229,36 +308,31 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetDesire mode = LEDC_LOW_SPEED_MODE; #endif - // Work out the optimal duty resolution based on current frequency, default to 1 if not found - // Working from 15 bit duty resolution down until we have a valid divisor - optimumDutyResolution = 1; - - for (int dutyResolution = SOC_LEDC_TIMER_BIT_WIDE_NUM - 1; dutyResolution > 0; dutyResolution--) - { - precision = (0x1 << dutyResolution); // 2**depth - - divParam = ((uint64_t)LEDC_APB_CLK_HZ << 8) / desiredFrequency / precision; - - if (divParam > 256) - { - optimumDutyResolution = dutyResolution; - break; - } - } + optimumDutyResolution = GetOptimumResolution(desiredFrequency); duty_res = (ledc_timer_bit_t)optimumDutyResolution; - // Save resolution for working out values for percent duty cycle - PwmController_Timer_resolution[timerId] = (0x1 << optimumDutyResolution); - timer_conf = {mode, duty_res, timer, (uint32_t)desiredFrequency, LEDC_AUTO_CLK}; result = ledc_timer_config(&timer_conf); + if (result != ESP_OK) { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } + // Save resolution for working out values for percent duty cycle + if (PwmController_Timer_resolution[timerId] != (uint32_t)(0x1 << optimumDutyResolution)) + { + PwmController_Timer_resolution[timerId] = (0x1 << optimumDutyResolution); + dutyCycle = CalculateDuty(timerId, dutyCycle); //, polarity); + + // Set Duty Cycle; + if (SetDutyCycle(mode, channel, dutyCycle) != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } // store the frequency pThis[FIELD___frequency].NumericByRef().s4 = desiredFrequency; @@ -274,8 +348,11 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetActive ledc_channel_t channel; - PwmPulsePolarity polarity; ledc_mode_t speed_mode; + int32_t desiredFrequency; + int32_t optimumDutyResolution; + int32_t privateDutyCycle; + uint32_t calDutyCycle; NANOCLR_HEADER(); @@ -286,7 +363,8 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetActive // Retrieves the needed parameters from private class properties or method parameters timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; - polarity = (PwmPulsePolarity)(pThis[FIELD___polarity].NumericByRef().u4); + privateDutyCycle = pThis[FIELD___dutyCycle].NumericByRef().u4; + desiredFrequency = pThis[FIELD___frequency].NumericByRef().s4; // parameter check if (stack.Arg1().NumericByRef().r8 < 0 || stack.Arg1().NumericByRef().r8 > 1.0) @@ -294,26 +372,33 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetActive NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } - // retrieve percentage as 0 to 10000 (0% to 100%) + channel = (ledc_channel_t)GetChannel(pinNumber, timerId, false); + dutyCycle = (uint32_t)(stack.Arg1().NumericByRef().r8 * CONST_DutyCycleFactor); - // Get channel number used for this pinNumber - // FIXME check result - channel = (ledc_channel_t)GetChannel(pinNumber, timerId, false); + // Set the backing duty cycle field when it is zero and return + // We need this as this native function is called before Init + if (privateDutyCycle == 0) + { + pThis[FIELD___dutyCycle].NumericByRef().u4 = dutyCycle; + NANOCLR_SET_AND_LEAVE(S_OK); + } // Get speed mode based on Timer used speed_mode = GetSpeedMode(timerId); - // Work out the duty Cycle for the current duty resolution - dutyCycle = CalculateDuty(timerId, dutyCycle, polarity); + optimumDutyResolution = GetOptimumResolution(desiredFrequency); - // Update duty on channel - IDF_ERROR(ledc_set_duty(speed_mode, channel, dutyCycle)); + PwmController_Timer_resolution[timerId] = (0x1 << optimumDutyResolution); - // Activate duty on channel - IDF_ERROR(ledc_update_duty(speed_mode, channel)); + // Work out the duty Cycle for the current duty resolution + calDutyCycle = CalculateDuty(timerId, dutyCycle); //, polarity); + + if (SetDutyCycle(speed_mode, channel, calDutyCycle) != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } - // store the new duty cycle pThis[FIELD___dutyCycle].NumericByRef().u4 = dutyCycle; NANOCLR_NOCLEANUP(); @@ -322,13 +407,11 @@ HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetActive HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeStart___VOID(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - - // get a pointer to the managed object instance and check that it's not NULL CLR_RT_HeapBlock *pThis = stack.This(); FAULT_ON_NULL(pThis); // Call configure to start PWM channel - NANOCLR_CHECK_HRESULT(ConfigureAndStart(pThis, false, false)); + NANOCLR_CHECK_HRESULT(ConfigureAndStart(pThis, true, false)); NANOCLR_NOCLEANUP(); } From a17b7157235cd7a8ef35dc9e61258e3286a9e0ef Mon Sep 17 00:00:00 2001 From: Adrian Soundy Date: Wed, 24 Jan 2024 18:14:05 +1300 Subject: [PATCH 519/572] CLR not starting on ESP32-C3 (XIAO_ESP32C3 firmware) when VS not connected (#2871) Small change so merging --- targets/ESP32/_IDF/esp32c3/app_main.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/targets/ESP32/_IDF/esp32c3/app_main.c b/targets/ESP32/_IDF/esp32c3/app_main.c index de37f30e2e..73214fccc8 100644 --- a/targets/ESP32/_IDF/esp32c3/app_main.c +++ b/targets/ESP32/_IDF/esp32c3/app_main.c @@ -44,14 +44,18 @@ void main_task(void *pvParameter) // Called from Esp32 IDF start up code before scheduler starts void app_main() { + UBaseType_t taskPriority = 5; + // Switch off logging so as not to interfere with WireProtocol over Uart0 esp_log_level_set("*", ESP_LOG_NONE); ESP_ERROR_CHECK(nvs_flash_init()); + vTaskPrioritySet(NULL, taskPriority); + // start receiver task - xTaskCreate(&receiver_task, "ReceiverThread", 3072, NULL, 5, &ReceiverTask); + xTaskCreate(&receiver_task, "ReceiverThread", 3072, NULL, taskPriority, &ReceiverTask); // start the CLR main task - xTaskCreate(&main_task, "main_task", 15000, NULL, 5, NULL); + xTaskCreate(&main_task, "main_task", 15000, NULL, taskPriority, NULL); } From 034d01ffaa462ca0a76da7ae4039ec41129c2a85 Mon Sep 17 00:00:00 2001 From: Cory Charlton Date: Fri, 26 Jan 2024 02:48:33 -0800 Subject: [PATCH 520/572] Update declaration for System.Net (#2831) --- .../System.Net/sys_net_native.cpp | 7 +++-- .../System.Net/sys_net_native.h | 30 ++++++++++--------- 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/src/DeviceInterfaces/System.Net/sys_net_native.cpp b/src/DeviceInterfaces/System.Net/sys_net_native.cpp index d63570de86..50829f9135 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native.cpp @@ -92,6 +92,9 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, + NULL, + NULL, Library_sys_net_native_System_Net_IPAddress::IPv4ToString___STATIC__STRING__U4, Library_sys_net_native_System_Net_IPAddress::IPv6ToString___STATIC__STRING__SZARRAY_U2, NULL, @@ -342,8 +345,8 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Net = { "System.Net", - 0xA6875261, + 0xD82C1452, method_lookup, - { 100, 2, 0, 0 } + { 100, 2, 0, 1 } }; // clang-format on diff --git a/src/DeviceInterfaces/System.Net/sys_net_native.h b/src/DeviceInterfaces/System.Net/sys_net_native.h index 3f2d1195cc..7b88164688 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native.h +++ b/src/DeviceInterfaces/System.Net/sys_net_native.h @@ -161,8 +161,10 @@ struct Library_sys_net_native_System_Net_IPAddress { static const int FIELD_STATIC__Any = 8; static const int FIELD_STATIC__Loopback = 9; - static const int FIELD_STATIC__IPv6Any = 10; - static const int FIELD_STATIC__IPv6Loopback = 11; + static const int FIELD_STATIC__Broadcast = 10; + static const int FIELD_STATIC__None = 11; + static const int FIELD_STATIC__IPv6Any = 12; + static const int FIELD_STATIC__IPv6Loopback = 13; static const int FIELD__Address = 1; static const int FIELD___family = 2; @@ -215,9 +217,9 @@ struct Library_sys_net_native_System_Net_NetworkInformation_NetworkAvailabilityE struct Library_sys_net_native_System_Net_NetworkInformation_NetworkChange { - static const int FIELD_STATIC__NetworkAddressChanged = 10; - static const int FIELD_STATIC__NetworkAvailabilityChanged = 11; - static const int FIELD_STATIC__NetworkAPStationChanged = 12; + static const int FIELD_STATIC__NetworkAddressChanged = 14; + static const int FIELD_STATIC__NetworkAvailabilityChanged = 15; + static const int FIELD_STATIC__NetworkAPStationChanged = 16; //--// }; @@ -346,10 +348,10 @@ struct Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509 struct Library_sys_net_native_System_Net_Security_SslStream { - static const int FIELD___sslVerification = 7; - static const int FIELD___useStoredDeviceCertificate = 8; - static const int FIELD___sslContext = 9; - static const int FIELD___isServer = 10; + static const int FIELD___sslVerification = 6; + static const int FIELD___useStoredDeviceCertificate = 7; + static const int FIELD___sslContext = 8; + static const int FIELD___isServer = 9; //--// }; @@ -412,11 +414,11 @@ struct Library_sys_net_native_System_Net_Sockets_NativeSocket struct Library_sys_net_native_System_Net_Sockets_NetworkStream { - static const int FIELD___socket = 2; - static const int FIELD___socketType = 3; - static const int FIELD___remoteEndPoint = 4; - static const int FIELD___ownsSocket = 5; - static const int FIELD___disposed = 6; + static const int FIELD___socket = 1; + static const int FIELD___socketType = 2; + static const int FIELD___remoteEndPoint = 3; + static const int FIELD___ownsSocket = 4; + static const int FIELD___disposed = 5; //--// }; From 1ac61c9e8b8686e2141102344b336a77676fb522 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 29 Jan 2024 13:10:29 +0000 Subject: [PATCH 521/572] Code style fix ***NO_CI*** --- src/DeviceInterfaces/System.Net/sys_net_native.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/DeviceInterfaces/System.Net/sys_net_native.cpp b/src/DeviceInterfaces/System.Net/sys_net_native.cpp index 50829f9135..79b5f3026b 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native.cpp @@ -349,4 +349,6 @@ const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Net = method_lookup, { 100, 2, 0, 1 } }; + // clang-format on + From 430fa41dffcce56b696e6e7336309bbd7b33ead1 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 20 Feb 2024 16:01:46 -0600 Subject: [PATCH 522/572] Add SKY_CEVB1 target, a generic CLR for use with current batch of CEVBs --- .../SiliconLabs/SKY_CEVB1/CMakeLists.txt | 76 ++++ .../SiliconLabs/SKY_CEVB1/CMakePresets.json | 85 +++++ .../AzureRTOS/SiliconLabs/SKY_CEVB1/README.md | 30 ++ .../SKY_CEVB1/autogen/sl_device_init_clocks.c | 28 ++ .../SKY_CEVB1/autogen/sl_event_handler.c | 48 +++ .../SKY_CEVB1/autogen/sl_uartdrv_init.c | 91 +++++ .../SKY_CEVB1/autogen/sl_uartdrv_instances.h | 35 ++ .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 ++++++++ .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 ++ .../autogen/sl_usbd_class_hid_instances.c | 277 ++++++++++++++ .../autogen/sl_usbd_class_hid_instances.h | 32 ++ .../autogen/sl_usbd_configuration_instances.c | 61 ++++ .../autogen/sl_usbd_configuration_instances.h | 18 + .../SiliconLabs/SKY_CEVB1/bspconfig.h | 9 + .../SKY_CEVB1/common/CMakeLists.txt | 10 + .../common/Device_BlockStorage-DEBUG.c | 123 +++++++ .../SKY_CEVB1/common/Device_BlockStorage.c | 123 +++++++ .../common/tx_initialize_low_level.S | 239 ++++++++++++ .../SiliconLabs/SKY_CEVB1/config/pin_config.h | 259 +++++++++++++ .../config/sl_board_control_config.h | 112 ++++++ .../config/sl_device_init_hfrco_config.h | 27 ++ .../config/sl_device_init_hfxo_config.h | 43 +++ .../config/sl_device_init_lfrco_config.h | 34 ++ .../config/sl_device_init_lfxo_config.h | 37 ++ .../config/sl_iostream_usart_onewire_config.h | 103 ++++++ .../config/sl_iostream_usart_vcom_config.h | 112 ++++++ .../SKY_CEVB1/config/sl_memory_config.h | 13 + .../config/sl_uartdrv_usart_vcom_config.h | 85 +++++ .../config/sl_usbd_class_acm0_config.h | 53 +++ .../config/sl_usbd_class_hid0_config.h | 143 ++++++++ .../config/sl_usbd_class_winusb_config.h | 59 +++ .../SKY_CEVB1/config/sl_usbd_config0_config.h | 51 +++ .../SKY_CEVB1/config/sl_usbd_core_config.h | 199 ++++++++++ .../SKY_CEVB1/config/sl_usbd_device_config.h | 60 +++ .../SKY_CEVB1/config/uartdrv_config.h | 114 ++++++ .../SiliconLabs/SKY_CEVB1/launch.json | 83 +++++ .../SKY_CEVB1/nanoBooter/CMakeLists.txt | 10 + .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ++++++++++++ .../SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld | 235 ++++++++++++ .../SiliconLabs/SKY_CEVB1/nanoBooter/main.c | 180 +++++++++ .../SKY_CEVB1/nanoBooter/target_board.h.in | 18 + .../SKY_CEVB1/nanoCLR/CMakeLists.txt | 15 + .../SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 +++++++++++++ .../SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld | 246 +++++++++++++ .../SiliconLabs/SKY_CEVB1/nanoCLR/main.c | 210 +++++++++++ .../SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp | 8 + .../SKY_CEVB1/nanoCLR/target_board.h.in | 18 + .../SKY_CEVB1/nanoCLR/usb_hid_app.c | 244 +++++++++++++ .../SKY_CEVB1/target_BlockStorage.c | 19 + .../SKY_CEVB1/target_BlockStorage.h | 12 + .../target_com_sky_nf_dev_i2c_config.cpp | 26 ++ .../target_com_sky_nf_dev_i2c_config.h | 4 + .../target_com_sky_nf_dev_spi_config.cpp | 48 +++ .../target_com_sky_nf_dev_spi_config.h | 8 + .../SiliconLabs/SKY_CEVB1/target_common.c | 27 ++ .../SiliconLabs/SKY_CEVB1/target_common.h.in | 52 +++ .../SKY_CEVB1/target_nano_gg_adc_config.cpp | 52 +++ .../SKY_CEVB1/target_nano_gg_adc_config.h | 9 + .../target_nf_dev_onewire_config.cpp | 8 + .../SKY_CEVB1/target_nf_dev_onewire_config.h | 13 + .../SKY_CEVB1/target_stdio_config.c | 7 + .../SKY_CEVB1/target_stdio_config.h | 5 + .../target_system_device_adc_config.cpp | 6 + .../target_system_device_adc_config.h | 6 + .../target_system_device_i2c_config.cpp | 32 ++ .../target_system_device_i2c_config.h | 8 + .../target_system_device_pwm_config.cpp | 17 + .../target_system_device_spi_config.cpp | 35 ++ .../target_system_device_spi_config.h | 7 + .../target_system_io_ports_config.cpp | 4 + .../SKY_CEVB1/target_system_io_ports_config.h | 5 + .../SiliconLabs/SKY_CEVB1/target_tx_user.h | 206 +++++++++++ .../SiliconLabs/SKY_CEVB1/target_ux_user.h | 345 ++++++++++++++++++ 73 files changed, 5679 insertions(+) create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h create mode 100644 targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt new file mode 100644 index 0000000000..bab63d4097 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakeLists.txt @@ -0,0 +1,76 @@ + +include(FetchContent) +include(binutils.common) +include(binutils.AzureRTOS) +include(AzureRTOS_${TARGET_SERIES}_GCC_options) + +# Azure RTOS settings and inclusion of build system +set(THREADX_ARCH "cortex_m4" ) +set(THREADX_TOOLCHAIN "gnu" ) +# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") +# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") + +set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) + +add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) +# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) +# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) +# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) + +nf_setup_target_build( + HAS_NANOBOOTER + + BOOTER_LINKER_FILE + efm32gg11b_booter + + CLR_LINKER_FILE + efm32gg11b_CLR + + BOOTER_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x2000 + SL_HEAP_SIZE=0x2000 + + CLR_EXTRA_COMPILE_DEFINITIONS + EFM32GG11B820F2048GQ100=1 + SL_COMPONENT_CATALOG_PRESENT=1 + _SILICON_LABS_32B_SERIES_2_CONFIG=0 + BSP_LF_CLK_SEL=99 + I2CSPM_TRANSFER_TIMEOUT=3000 + SL_STACK_SIZE=0x7000 + SL_HEAP_SIZE=0x10000 + + BOOTER_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" + + CLR_EXTRA_LINKMAP_PROPERTIES + ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" +) + +# generate bin file for deployment +if(SRECORD_TOOL_AVAILABLE) + + ############################################################################################################ + ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + ############################################################################################################ + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + 13000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + else() + nf_generate_bin_package( + ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin + ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin + C000 + ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) + endif() + +endif() diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json new file mode 100644 index 0000000000..2e222252a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json @@ -0,0 +1,85 @@ +{ + "version": 4, + "include": [ + "../../../../CMake/arm-gcc.json", + "../../../../config/user-tools-repos.json", + "../../../../config/user-prefs.json" + ], + "configurePresets": [ + { + "name": "SKY_CEVB1_Debug", + "inherits": [ + "arm-gcc-cortex-preset", + "user-tools-repos", + "user-prefs" + ], + "hidden": false, + "cacheVariables": { + "TARGET_BOARD": "SKY_CEVB1", + "TARGET_NAME": "SKY_CEVB1_Debug", + "RTOS": "AzureRTOS", + "TARGET_SERIES": "EFM32GG11", + "SUPPORT_ANY_BASE_CONVERSION": "OFF", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_WATCHDOG": "OFF", + "NF_PROFILE_NEW_ALLOCATIONS": "ON", + "NF_TRACE_MEMORY_STATS": "ON", + "API_System.Math": "ON", + "API_Hardware.GiantGecko": "ON", + "API_System.Device.Gpio": "ON", + "API_System.Device.Pwm": "ON", + "API_System.IO.Ports": "OFF", + "API_System.Device.Adc": "OFF", + "API_System.Device.Dac": "OFF", + "API_System.Net": "OFF", + "API_nanoFramework.Device.OneWire": "ON", + "API_nanoFramework.Devices.Can": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON", + "API_nanoFramework.GiantGecko.Adc": "OFF", + "API_Windows.Storage": "OFF", + "API_nanoFramework.Graphics": "OFF", + "TARGET_SERIAL_BAUDRATE": "921600", + "HAL_WP_USE_SERIAL": "OFF", + "HAL_WP_USE_USB_CDC": "ON", + "API_System.Device.Spi": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", + "API_System.Device.I2c": "OFF", + "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", + "API_System.Device.UsbStream": "ON", + "API_nanoFramework.System.IO.Hashing": "ON" + } + }, + { + "name": "SKY_CEVB1_Release", + "inherits": [ + "SKY_CEVB1_Debug" + ], + "hidden": false, + "cacheVariables": { + "TARGET_NAME": "SKY_CEVB1_Release", + "NF_BUILD_RTM": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF" + } + } + ], + "buildPresets": [ + { + "inherits": "base-user", + "name": "SKY_CEVB1_Debug", + "displayName": "SKY_CEVB1_Debug", + "configurePreset": "SKY_CEVB1_Debug" + }, + { + "inherits": "base-user", + "name": "SKY_CEVB1_Release", + "displayName": "SKY_CEVB1_Release", + "configurePreset": "SKY_CEVB1_Release" + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md new file mode 100644 index 0000000000..a6a28e8c83 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/README.md @@ -0,0 +1,30 @@ +# Skyworks CEVB Scheme #1 featuring SiLabs EFM32 Giant Gecko GG11 + +This is used for Si5575 CEVB, Si5400 CEVB, and Si5500 8x8 CEVB as of Feb 2024. + +## See +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8175353962/Si5575+CEVB+Software+Control + +https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB + +## Key Files + +CMakePresets.json + Enable packages, targets, naming, etc. + +target_system_device_spi_config.h +target_system_device_spi_config.cpp + SPI + +target_system_device_i2c_config.h +target_system_device_i2c_config.cpp + I2C + +target_nano_gg_adc_config.h +target_nano_gg_adc_config.cpp + ADC + +nanoBooter\main.c +nanoCLR\main.c + Bootloader Mode / Ready LED + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c new file mode 100644 index 0000000000..5e12163b4b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_device_init_clocks.c @@ -0,0 +1,28 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2019 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + + CMU_ClockEnable(cmuClock_HFLE, true); + CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_CLOCK_SELECT_SET(LFA, LFRCO); + CMU_CLOCK_SELECT_SET(LFB, LFRCO); +#if defined(_CMU_LFCCLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFC, LFRCO); +#endif +#if defined(_CMU_LFECLKSEL_MASK) + CMU_CLOCK_SELECT_SET(LFE, LFRCO); +#endif + + return SL_STATUS_OK; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c new file mode 100644 index 0000000000..c0d02691c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_event_handler.c @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Copyright 2020 Silicon Laboratories Inc. www.silabs.com +// See LICENSE file in the project root for full license information. +// + +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfrco.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "gpiointerrupt.h" +#include "sl_uartdrv_instances.h" +#include "sl_iostream_init_usart_instances.h" +#include "sl_iostream_init_instances.h" +#include "sl_i2cspm_instances.h" +#include "sl_power_manager.h" + +#include +#include + +extern void InitGpCrc(void); + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + // sl_device_init_hfxo(); + sl_device_init_hfrco(); + // sl_device_init_lfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_power_manager_init(); + InitGpCrc(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c new file mode 100644 index 0000000000..ab0bb51bee --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_init.c @@ -0,0 +1,91 @@ +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h new file mode 100644 index 0000000000..894c73f803 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_uartdrv_instances.h @@ -0,0 +1,35 @@ +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c new file mode 100644 index 0000000000..12f715438d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.c @@ -0,0 +1,154 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_cdc_acm_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for acm0 instance */ + +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); + +//**************************************************************************** +// Global variables. + +/* variables for acm0 instance */ + +uint8_t sl_usbd_cdc_acm_acm0_number = 0; + +sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { + sli_usbd_cdc_acm_acm0_enable, + sli_usbd_cdc_acm_acm0_disable, + sli_usbd_cdc_acm_acm0_line_control_changed, + sli_usbd_cdc_acm_acm0_line_coding_changed, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for acm0 instance */ +void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_enable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) +{ + (void)&subclass_nbr; + sl_usbd_cdc_acm_acm0_on_disable_event(); + return; +} + +void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) +{ + (void)&subclass_nbr; + (void)&event; + (void)&event_chngd; + sl_usbd_cdc_acm_acm0_on_line_control_event(); + return; +} + +bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) +{ + (void)&subclass_nbr; + (void)&p_line_coding; + sl_usbd_cdc_acm_acm0_on_line_coding_event(); + return true; +} + +//**************************************************************************** +// Global functions. + +/* initialize acm0 instance */ +void sli_usbd_cdc_acm_acm0_init() +{ + uint16_t interval = 0; + uint16_t capabilities = 0; + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; + + /* line state notification interval for that instance */ + interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; + + /* call management capabilities */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; + } + + /* call management DCI interface */ + if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) + { + capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; + } + + /* create CDC ACM instance */ + sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); + + /* store class number globally */ + sl_usbd_cdc_acm_acm0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) +{ +} + +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) +{ +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h new file mode 100644 index 0000000000..dd62731af5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_cdc_acm_instances.h @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT +#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT + +#include + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_cdc_acm_acm0_number; + +/* event handlers for all CDC ACM instances */ + +__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); +__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); + +/* init functions for all CDC ACM instances */ + +void sli_usbd_cdc_acm_acm0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c new file mode 100644 index 0000000000..18d550951b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.c @@ -0,0 +1,277 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include +#include "sl_usbd_class_hid.h" + +/* template headers */ +#include "sl_usbd_configuration_instances.h" +#include "sl_usbd_class_hid_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Function declarations. + +/* callback prototypes for hid0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr); + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len); + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); + +//**************************************************************************** +// Global variables. + +/* variables for mouse0 instance */ + +uint8_t sl_usbd_hid_hid0_number = 0; + +uint8_t sl_usbd_hid_hid0_default_protocol = 0; + +static const uint8_t sli_usbd_hid_hid0_default_desc[] = { + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, 0x00, + SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, + SL_USBD_HID_LOCAL_USAGE + 1, 0x09, + SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, + SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, + SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, + SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, + SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, + SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, + SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, + SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, + SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, + SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, + SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; + +sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { + sli_usbd_hid_hid0_enable, + sli_usbd_hid_hid0_disable, + sli_usbd_hid_hid0_get_report_desc, + sli_usbd_hid_hid0_get_phy_desc, + sli_usbd_hid_hid0_set_output_report, + sli_usbd_hid_hid0_get_feature_report, + sli_usbd_hid_hid0_set_feature_report, + sli_usbd_hid_hid0_get_protocol, + sli_usbd_hid_hid0_set_protocol, +}; + +//**************************************************************************** +// Callback functions. + +/* callback functions for mouse0 instance */ +void sli_usbd_hid_hid0_enable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_enable_event(); + + return; +} + +void sli_usbd_hid_hid0_disable(uint8_t class_nbr) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_disable_event(); + + return; +} + +void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = sli_usbd_hid_hid0_default_desc; + *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); + + sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + (void)&class_nbr; + + *p_report_ptr = NULL; + *p_report_len = 0; + + sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); + + return; +} + +void sli_usbd_hid_hid0_set_output_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + memset(p_report_buf, 0, report_len); + + sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_set_feature_report( + uint8_t class_nbr, + uint8_t report_id, + uint8_t *p_report_buf, + uint16_t report_len) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); + + return; +} + +void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) +{ + (void)&class_nbr; + + *p_protocol = sl_usbd_hid_hid0_default_protocol; + + sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); + + return; +} + +void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) +{ + (void)&class_nbr; + + sl_usbd_hid_hid0_default_protocol = protocol; + + sl_usbd_hid_hid0_on_set_protocol_event(protocol); + + return; +} + +//**************************************************************************** +// Global functions. + +/* initialize hid0 instance */ +void sli_usbd_hid_hid0_init() +{ + sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; + + uint8_t subclass = 0; + uint8_t protocol = 0; + + uint16_t interval_in = 0; + uint16_t interval_out = 0; + bool ctrl_rd_en = true; + + uint8_t class_number = 0; + uint8_t config_number = 0; + char *configs = NULL; + char *token = NULL; + + /* configs to attach the class instance to */ + configs = SL_USBD_HID_HID0_CONFIGURATIONS; + + /* read subclass, protocol, and country codes */ + subclass = SL_USBD_HID_HID0_SUBCLASS; + protocol = SL_USBD_HID_HID0_PROTOCOL; + country = SL_USBD_HID_HID0_COUNTRY_CODE; + + /* read endpoint parameters */ + interval_in = SL_USBD_HID_HID0_INTERVAL_IN; + interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; + ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; + + /* create HID instance */ + sl_usbd_hid_create_instance( + subclass, + protocol, + country, + interval_in, + interval_out, + ctrl_rd_en, + &sli_usbd_hid_hid0_callbacks, + &class_number); + + /* store class number globally */ + sl_usbd_hid_hid0_number = class_number; + + /* tokenize configs by "," and spaces */ + token = strtok(configs, ", "); + + /* loop over tokens */ + while (token != NULL) + { + + /* add to config0? */ + if (!strcmp(token, "config0") || !strcmp(token, "all")) + { + config_number = sl_usbd_configuration_config0_number; + sl_usbd_hid_add_to_configuration(class_number, config_number); + } + + /* next token */ + token = strtok(NULL, ", "); + } +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h new file mode 100644 index 0000000000..fa9e5b853a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_class_hid_instances.h @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT +#define SL_USBD_CLASS_HID_INSTANCES_INIT + +#include "sl_usbd_class_hid.h" + +/* class numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_hid_hid0_number; + +/* event handlers for all HID instances */ + +__WEAK void sl_usbd_hid_hid0_on_enable_event(void); +__WEAK void sl_usbd_hid_hid0_on_disable_event(void); +__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); +__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); +__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); +__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); + +/* init functions for all HID instances */ + +void sli_usbd_hid_hid0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c new file mode 100644 index 0000000000..0a865bccfc --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.c @@ -0,0 +1,61 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//**************************************************************************** +// Includes. + +#include +#include + +/* template headers */ +#include "sl_usbd_configuration_instances.h" + +/* include config file for the instances */ + +#include + +//**************************************************************************** +// Global variables. + +/* configuration numbers assigned by the USB stack after init */ + +uint8_t sl_usbd_configuration_config0_number = 0; + +//**************************************************************************** +// Global functions. + +/* initialize config0 instance */ +void sli_usbd_configuration_config0_init() +{ + uint8_t attrib = 0; + uint16_t power = 0; + sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; + const char *name = NULL; + uint8_t number = 0; + + /* configuration attributes */ +#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 + attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; +#endif +#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 + attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; +#endif + + /* configuration maximum power (mA) */ + power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; + + /* configuration speed */ + speed = SL_USBD_DEVICE_SPEED_FULL; + + /* configuration name */ + name = SL_USB_CONFIGURATION_CONFIG0_NAME; + + /* create the configuration descriptor */ + sl_usbd_core_add_configuration(attrib, power, speed, name, &number); + + /* store the configuration number globally */ + sl_usbd_configuration_config0_number = number; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h new file mode 100644 index 0000000000..07726e93fe --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/autogen/sl_usbd_configuration_instances.h @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT +#define SL_USBD_CONFIGURATION_INSTANCES_INIT + +/* configuration numbers assigned by the USB stack after init */ + +extern uint8_t sl_usbd_configuration_config0_number; + +/* init functions for all configuration instances */ + +void sli_usbd_configuration_config0_init(void); + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h new file mode 100644 index 0000000000..09c0ff4989 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/bspconfig.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt new file mode 100644 index 0000000000..8ea7907f60 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..5ae69920e9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, + + // 00013000 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 19, 237}, + + // 000EE000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // GG11 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c new file mode 100644 index 0000000000..09982097e3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c @@ -0,0 +1,123 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 66}, + + // 00043000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S new file mode 100644 index 0000000000..39ad790f18 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/tx_initialize_low_level.S @@ -0,0 +1,239 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 38000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/GNU */ +@/* 6.0 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =__Vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =__Vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h new file mode 100644 index 0000000000..158edf847a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/pin_config.h @@ -0,0 +1,259 @@ +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[ACMP2] +// [ACMP2]$ + +// $[ACMP3] +// [ACMP3]$ + +// $[ADC0] +// [ADC0]$ + +// $[ADC1] +// [ADC1]$ + +// $[BU] +// [BU]$ + +// $[CAN0] +// [CAN0]$ + +// $[CAN1] +// [CAN1]$ + +// $[CMU] +// [CMU]$ + +// $[DBG] +// [DBG]$ + +// $[EBI] +// [EBI]$ + +// $[ETH] +// [ETH]$ + +// $[ETM] +// [ETM]$ + +// $[GPIO] +// [GPIO]$ + +// $[I2C0] +// [I2C0]$ + +// $[I2C1] +// [I2C1]$ + +// $[I2C2] +// [I2C2]$ + +// $[IDAC0] +// [IDAC0]$ + +// $[LCD] +// [LCD]$ + +// $[LESENSE] +// [LESENSE]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[LETIMER1] +// [LETIMER1]$ + +// $[LEUART0] +// [LEUART0]$ + +// $[LEUART1] +// [LEUART1]$ + +// $[LFXO] +// [LFXO]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[PCNT1] +// [PCNT1]$ + +// $[PCNT2] +// [PCNT2]$ + +// $[PRS.CH0] +// [PRS.CH0]$ + +// $[PRS.CH1] +// [PRS.CH1]$ + +// $[PRS.CH2] +// [PRS.CH2]$ + +// $[PRS.CH3] +// [PRS.CH3]$ + +// $[PRS.CH4] +// [PRS.CH4]$ + +// $[PRS.CH5] +// [PRS.CH5]$ + +// $[PRS.CH6] +// [PRS.CH6]$ + +// $[PRS.CH7] +// [PRS.CH7]$ + +// $[PRS.CH8] +// [PRS.CH8]$ + +// $[PRS.CH9] +// [PRS.CH9]$ + +// $[PRS.CH10] +// [PRS.CH10]$ + +// $[PRS.CH11] +// [PRS.CH11]$ + +// $[PRS.CH12] +// [PRS.CH12]$ + +// $[PRS.CH13] +// [PRS.CH13]$ + +// $[PRS.CH14] +// [PRS.CH14]$ + +// $[PRS.CH15] +// [PRS.CH15]$ + +// $[PRS.CH16] +// [PRS.CH16]$ + +// $[PRS.CH17] +// [PRS.CH17]$ + +// $[PRS.CH18] +// [PRS.CH18]$ + +// $[PRS.CH19] +// [PRS.CH19]$ + +// $[PRS.CH20] +// [PRS.CH20]$ + +// $[PRS.CH21] +// [PRS.CH21]$ + +// $[PRS.CH22] +// [PRS.CH22]$ + +// $[PRS.CH23] +// [PRS.CH23]$ + +// $[QSPI0] +// [QSPI0]$ + +// $[SDIO] +// [SDIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[TIMER5] +// [TIMER5]$ + +// $[TIMER6] +// [TIMER6]$ + +// $[UART0] +// [UART0]$ + +// $[UART1] +// [UART1]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// [USART1]$ + +// $[USART2] +// [USART2]$ + +// $[USART3] +// [USART3]$ + +// $[USART4] +// USART4 CTS on PH8 +#define USART4_CTS_PORT gpioPortH +#define USART4_CTS_PIN 8 +#define USART4_CTS_LOC 4 + +// USART4 RTS on PH9 +#define USART4_RTS_PORT gpioPortH +#define USART4_RTS_PIN 9 +#define USART4_RTS_LOC 4 + +// USART4 RX on PH5 +#define USART4_RX_PORT gpioPortH +#define USART4_RX_PIN 5 +#define USART4_RX_LOC 4 + +// USART4 TX on PH4 +#define USART4_TX_PORT gpioPortH +#define USART4_TX_PIN 4 +#define USART4_TX_LOC 4 + +// [USART4]$ + +// $[USART5] +// [USART5]$ + +// $[USB] +// [USB]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[WFXO] +// [WFXO]$ + +// $[WTIMER0] +// [WTIMER0]$ + +// $[WTIMER1] +// [WTIMER1]$ + +// $[WTIMER2] +// [WTIMER2]$ + +// $[WTIMER3] +// [WTIMER3]$ + +// $[CUSTOM_PIN_NAME] +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h new file mode 100644 index 0000000000..5796117234 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_board_control_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 1 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 1 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 1 + +// Enable Hall Effect sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_HALL 0 + +// Enable Microphone +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 + +// Enable QSPI Flash +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_QSPI 0 + +// Enable SD Card +// Default: 0 +#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE +#define SL_BOARD_ENABLE_VCOM_PIN 1 +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// SL_BOARD_ENABLE_SENSOR_HALL +// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] +#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB +#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 +// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ + +// SL_BOARD_ENABLE_SENSOR_MICROPHONE +// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD +#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 +// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ + +// SL_BOARD_ENABLE_MEMORY_QSPI +// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] +#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG +#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 +// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ + +// SL_BOARD_ENABLE_MEMORY_SDCARD +// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE +#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 +// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h new file mode 100644 index 0000000000..8ec8d17100 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfrco_config.h @@ -0,0 +1,27 @@ +#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H +#define SL_DEVICE_INIT_HFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Frequency Band +// RC Oscillator Frequency Band +// 1 MHz +// 2 MHz +// 4 MHz +// 7 MHz +// 13 MHz +// 16 MHz +// 19 MHz +// 26 MHz +// 32 MHz +// 38 MHz +// 48 MHz +// 56 MHz +// 64 MHz +// 72 MHz +// Default: cmuHFRCOFreq_72M0Hz +#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h new file mode 100644 index 0000000000..8f04091ef4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_hfxo_config.h @@ -0,0 +1,43 @@ +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal + +// Frequency <4000000-48000000> +// Default: 50000000 +#define SL_DEVICE_INIT_HFXO_FREQ 50000000 + +// HFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_HFXO_PRECISION 500 + +// CTUNE <0-511> +// Default: 360 +#define SL_DEVICE_INIT_HFXO_CTUNE 132 + +// Advanced Configurations +// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSTART false + +// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED +// True +// False +// Default: false +#define SL_DEVICE_INIT_HFXO_AUTOSELECT false + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h new file mode 100644 index 0000000000..79b1541af8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfrco_config.h @@ -0,0 +1,34 @@ +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Duty Cycling of Vref +// Default: 0 +// Setting this configuration to 1 puts the LFRCO in duty cycle mode by +// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// This helps reduce current consumption by ~100nA in EM2, but will result +// in slightly worse accuracy especially at high temperatures. +// To improve the average LFRCO frequency accuracy, make sure ENCHOP +// and ENDEM configs are also set. +#define SL_DEVICE_INIT_LFRCO_ENVREF 0 + +// Enable Comparator Chopping +// Default: 1 +// Setting this configuration to 1 enables LFRCO comparator chopping by +// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENDEM, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 + +// Enable Dynamic Element Matching +// Default: 1 +// Setting this configuration to 1 enables dynamic element matching by +// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. +// Setting this bit, along with ENCHOP, helps improve the average LFRCO +// frequency accuracy. +#define SL_DEVICE_INIT_LFRCO_ENDEM 1 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h new file mode 100644 index 0000000000..46c38725c1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_device_init_lfxo_config.h @@ -0,0 +1,37 @@ +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 70 + +// LFXO precision in PPM <0-65535> +// Default: 500 +#define SL_DEVICE_INIT_LFXO_PRECISION 100 + +// Startup Timeout Delay +// +// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles +// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles +// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles +// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles +// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles +// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles +// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles +// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles +// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default +// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT +#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h new file mode 100644 index 0000000000..41622d2e20 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_onewire_config.h @@ -0,0 +1,103 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H +#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_ONEWIRE +// $[USART_SL_IOSTREAM_USART_ONEWIRE] +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 +#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 + +// USART0 TX on PC11 +#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 +#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 + +// USART0 RX on PC10 +#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE +#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 +#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 + +// [USART_SL_IOSTREAM_USART_ONEWIRE]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h new file mode 100644 index 0000000000..59d33b8885 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_iostream_usart_vcom_config.h @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief IOSTREAM_USART Config. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H +#define SL_IOSTREAM_USART_VCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// USART settings + +// Baud rate +// Default: 115200 +#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control +// None +// CTS +// RTS +// CTS/RTS +// Software Flow control (XON/XOFF) +// Default: usartHwFlowControlNone +#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone + +// Receive buffer size +// Default: 32 +#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 + +// Convert \n to \r\n +// It can be changed at runtime using the C API. +// Default: 0 +#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 + +// Restrict the energy mode to allow the reception. +// Default: 1 +// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. +#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 + +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_IOSTREAM_USART_VCOM +// $[USART_SL_IOSTREAM_USART_VCOM] +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 +#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 +#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 +#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 +#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH +#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 +#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 +// [USART_SL_IOSTREAM_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h new file mode 100644 index 0000000000..4f20db4a24 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_memory_config.h @@ -0,0 +1,13 @@ +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// These parameters are meant to be set in the target CMakeLists.txt file +#ifndef SL_STACK_SIZE +#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" +#endif + +#ifndef SL_HEAP_SIZE +#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" +#endif + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h new file mode 100644 index 0000000000..b9b92ff77c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_uartdrv_usart_vcom_config.h @@ -0,0 +1,85 @@ +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHw +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 + +// USART4 TX on PH4 +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_TX_PIN 4 +#define SL_UARTDRV_USART_VCOM_TX_LOC 4 + +// USART4 RX on PH5 +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RX_PIN 5 +#define SL_UARTDRV_USART_VCOM_RX_LOC 4 + +// USART4 CTS on PH8 +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 + +// USART4 RTS on PH9 +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH +#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 +#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h new file mode 100644 index 0000000000..9c1ac2d7b1 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_acm0_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H +#define SL_USBD_CDC_ACM_ACM0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this CDC ACM class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Line State Notification Interval (ms) +// Default: 64 +// Line State Notification Interval (ms). +#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 + +// + +// Call Management + +// Enable call management +// Default: 1 +// If set to 1, the host is informed that this ACM instance +// has call management capabilities. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 + +// Call management interface +// <1=> Over DCI +// <0=> Over CCI +// Default: 1 +// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created +// along with the CCI interface. Otherwise, only the CCI will be created +// and it will be used for both data and call management. +#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h new file mode 100644 index 0000000000..9e480375d0 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_hid0_config.h @@ -0,0 +1,143 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_HID_HID0_CONFIG_H +#define SL_USBD_HID_HID0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this HID class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_HID_HID0_CONFIGURATIONS "all" + +// + +// Type Codes + +// Subclass code +// None +// Boot +// Default: SL_USBD_HID_SUBCLASS_BOOT +// This defines the standard USB subclass code for this interface. +// For most use cases, you can just select "Boot". +#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT + +// Protocol code +// None +// Keyboard +// Mouse +// Default: SL_USBD_HID_PROTOCOL_MOUSE +// You can choose "Mouse" or "Keyboard" depending on what functionality +// this HID class instance will provide. +#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE + +// Country code +// Not supported +// Arabic +// Belgian +// Canadian Multilingual +// Canadian French +// Czech Republic +// Danish +// Finnish +// French +// German +// Greek +// Hebrew +// Hungary +// International +// Italian +// Japan Katakana +// Korean +// Latin American +// Netherlands Dutch +// Norwegian +// Persian Farsi +// Poland +// Portuguese +// Russia +// Slovakia +// Spanish +// Swedish +// Swiss French +// Swiss German +// Switzerland +// Taiwan +// Turkish Q +// Turkish F +// United Kingdom +// United States +// Yugoslavia +// Default: SL_USBD_HID_COUNTRY_CODE_US +// If this instance is implementing a keyboard interface, this +// field helps the host operating system know which layout/language +// the keyboard is manufactured for, or which country/localization +// setting to use by default. +#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US + +// + +// Protocol Details + +// IN polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_IN 2 + +// OUT polling interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_HID_HID0_INTERVAL_OUT 2 + +// Enable Control Read +// Default: 1 +// Enable read operations through the control transfers. +#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h new file mode 100644 index 0000000000..53ccff0cd9 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_class_winusb_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H +#define SL_USBD_VENDOR_WINUSB_CONFIG_H + +//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Class Configuration + +// Configuration(s) to add this class instance to +// Default: all +// Comma separated list of configuration instances (like inst0, inst1) +// that this vendor class instance will be attached to. You can +// use "all" to attach the class to all configs, or use an empty +// string if you do not want to attach the interface to any configuration. +#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" + +// + +// Protocol Details + +// Add interrupt endpoints +// Default: 0 +// Specifies whether we should add IN and OUT endpoints to this +// vendor class interface. +#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 + +// Endpoint interval +// <1=> 1ms +// <2=> 2ms +// <4=> 4ms +// <8=> 8ms +// <16=> 16ms +// <32=> 32ms +// <64=> 64ms +// <128=> 128ms +// <256=> 256ms +// <512=> 512ms +// <1024=> 1024ms +// <2048=> 2048ms +// <4096=> 4096ms +// <8192=> 8192ms +// <16384=> 16384ms +// <32768=> 32768ms +// Default: 2 +// Polling interval for input/output transfers, in milliseconds. +// It must be a power of 2. +#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h new file mode 100644 index 0000000000..a70da59041 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_config0_config.h @@ -0,0 +1,51 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H +#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Configuration Settings + +// Configuration Name +// Default: "Main Configuration" +// This creates a string descriptor that the USB host +// can use to retrieve the name of this USB configuration descriptor. +// It can be scanned with "sudo lsusb -vv" on Linux. It appears next +// to iConfiguration field. +#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" + +// Power Source +// <0=> Bus-Powered +// <1=> Self-Powered +// Default: 1 +// Indicates whether the device will be powered using USB bus or +// or using a self-power source (like battery or a debugger) +// if the host configures the device using this configuration. +#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 + +// Enable Remote Wakeup +// Default: 0 +// Enables or disables remote wakeup feature. +#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 + +// Maximum Power (mA) +// <100=> 100 mA +// <500=> 500 mA +// Default: 100 +// Specifies the maximum current that the device will draw. +// Most USB devices consume 100mA at most, but the USB standard +// allows the device to consume up to 500mA. When the host +// operating system scans this value, it will configure the USB port +// on the host controller to allow the device to consume the +// configured current. +#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 + +// + +// <<< end of configuration section >>> +#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h new file mode 100644 index 0000000000..1058079e4f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_core_config.h @@ -0,0 +1,199 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_CONFIG_H +#define SL_USBD_CONFIG_H + +extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Configuration + +// Auto-start USB device +// Default: 1 +// If enabled, the USB device will be automatically started up, +// using sl_usbd_core_start_device(), by the core task (which starts +// running after kernel scheduler is ready) when the USB stack is all +// initialized. You can disable this config if you want to call +// sl_usbd_core_start_device() manually from your code. This might +// be helpful if you do not want USB to start anytime before all +// your initializations are complete, or if you want to enable/disable +// USB on demand. +#define SL_USBD_AUTO_START_USB_DEVICE 1 + +// Enable SCSI 64-Bit LBA +// Default: 0 +// MSC SCSI Configuration for enabling 64-bit LBA support. +#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 + +// + +// USB Core Configuration + +// Core Pools + +// Number of configurations <1-255> +// Default: 1 +// The total number of configurations. +#define SL_USBD_CONFIGURATION_QUANTITY 1 + +// Number of interfaces <1-255> +// Default: 10 +// The total number of interfaces (for all of your USB configurations). +#define SL_USBD_INTERFACE_QUANTITY 10 + +// Number of alternate interfaces <1-255> +// Default: 10 +// The total number of alternate interfaces (for all of your USB configurations). +// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY +#define SL_USBD_ALT_INTERFACE_QUANTITY 10 + +// Number of interface groups <0-255> +// Default: 20 +// The total number of interface groups (for all of your USB configurations). +#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 + +// Number of endpoint descriptors <1-255> +// Default: 20 +// The total number of endpoint descriptors (for all of your USB configurations). +#define SL_USBD_DESCRIPTOR_QUANTITY 20 + +// Number of strings <0-100> +// Default: 30 +// The total number of strings per device. +#define SL_USBD_STRING_QUANTITY 30 + +// Number of opened endpoints <2-255> +// Default: 20 +// The total number of opened endpoints per device. +#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 + +// + +// Core Task + +// Stack size of USBD core task in bytes +// Default: 4096 +// Stack size in bytes of the USBD core task. +#define SL_USBD_TASK_STACK_SIZE 4096U + +// Priority of USBD core task +#define SL_USBD_TASK_PRIORITY 5 + +// USB CDC Configuration + +// CDC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 + +// Number of subclass instances <1-255> +// Default: 2 +// Number of subclass instances. +#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 + +// Number of data interfaces <1-255> +// Default: 2 +// Number of data interfaces. +#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 + +// + +// + +// USB HID Configuration + +// HID Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 + +// Number of report ids <0-255> +// Default: 2 +// Number of report ids. +#define SL_USBD_HID_REPORT_ID_QUANTITY 2 + +// Number of push/pop items <0-255> +// Default: 0 +// Number of push/pop items. +#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 + +// + +// HID Task + +// Stack size of USBD HID timer task in bytes +// Default: 2048 +// HID Timer task stack size in bytes. +#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 + +// Priority of USBD HID timer task +#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 + +// USB MSC Configuration + +// MSC Pools + +// Number of class instances <1-255> +// Default: 2 +// Number of class instances. +#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Default: 1 +// Number of configurations. +#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 + +// Number of Logical Units per class instance <1-255> +// Default: 2 +// Number of Logical Units. +#define SL_USBD_MSC_LUN_QUANTITY 2 + +// Size of data buffer per class instance in bytes <1-4294967295> +// Default: 512 +// Size of data buffer in bytes. +#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 + +// + +// + +// USB Vendor Configuration + +// Vendor Pools + +// Number of class instances <1-255> +// Number of class instances. +#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 + +// Number of configurations <1-255> +// Number of configurations. +#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 + +// pointer to USB Class Vendor description +#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription + +// + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h new file mode 100644 index 0000000000..1b672dc998 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/sl_usbd_device_config.h @@ -0,0 +1,60 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SL_USBD_DEVICE_CONFIG_H +#define SL_USBD_DEVICE_CONFIG_H + +extern char *UsbSerialNumber[]; + +// <<< Use Configuration Wizard in Context Menu >>> + +// USB Device Configuration + +// Device Vendor ID +// Device vendor ID: Silabs. +#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 + +// Device Product ID +// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board +#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC + +// Device Release Number +// Default: 0x0100 +// Device release number. +#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 + +// Device Manufacturer Name +// Device manufacturer string. +#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" + +// Device Product Name +// Device product string. +// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen +#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" + +// Device Serial Number +// Device serial number string. +#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber + +// Device Language ID +// Arabic +// Chinese +// US English +// UK English +// French +// German +// Greek +// Italian +// Portuguese +// Sanskrit +// ID of language of strings of device. +// Default: USBD_LANG_ID_ENGLISH_US +#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US + +// + +// <<< end of configuration section >>> +#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h new file mode 100644 index 0000000000..118a7c901a --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/config/uartdrv_config.h @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json new file mode 100644 index 0000000000..a4a945a94e --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/launch.json @@ -0,0 +1,83 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "SL_STK3701A nanoBooter", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoBooter.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + }, + { + "name": "SL_STK3701A nanoCLR", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", + "program": "${workspaceRoot}/build/nanoCLR.elf", + "MIMode": "gdb", + "debugServerPath": "/JLinkGDBServerCL.exe", + "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", + "stopAtEntry": false, + "serverStarted": "Connected to target", + "cwd": "${cwd}", + "setupCommands": [ + { + "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " + }, + { + "text": "target extended-remote localhost:2331" + }, + { + "text": "monitor halt" + }, + { + "text": "monitor reset" + }, + { + "text": "load" + } + ], + "launchCompleteCommand": "None", + "logging": { + "moduleLoad": false, + "trace": true, + "engineLogging": false, + "programOutput": false, + "traceResponse": false, + "exceptions": true + } + } + ] +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..0b7c048e56 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld new file mode 100644 index 0000000000..8941c58e5c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter-DEBUG.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld new file mode 100644 index 0000000000..98793699a7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/efm32gg11b_booter.ld @@ -0,0 +1,235 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ + deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if flash0 usage exceeds flash0 size */ + ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") +} + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c new file mode 100644 index 0000000000..0787f4a6a5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c @@ -0,0 +1,180 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include + +#include + +#include +// #include + +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; + +// byte pool configuration and definitions +#define DEFAULT_BYTE_POOL_SIZE 4096 +TX_BYTE_POOL byte_pool_0; +ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; + +// threads definitions and configurations + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// blink thread +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + // ConfigurationManager_Initialize(); + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + (uint8_t *)blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_init(); + sli_usbd_configuration_config0_init(); + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif + + // report successfull nanoBooter execution + ReportSuccessfullNanoBooter(); +} + +// Application entry point. +int main(void) +{ + // Initialize the board + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // configure + GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); + + // init boot clipboard + InitBootClipboard(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // check if there is a request to remain on nanoBooter + if (!IsToRemainInBooter()) + { + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + if (GPIO_PinInGet(gpioPortE, 8) != 0) + { + // check for valid CLR image + // we are checking for a valid image at the deployment address, which is pointing to the CLR address + if (CheckValidCLRImage((uint32_t)&__deployment_start__)) + { + // there seems to be a valid CLR image + + // need to change HF clock to internal RCO so the CLR can boot smoothly + CMU_CLOCK_SELECT_SET(HF, HFRCO); + + // launch nanoCLR + LaunchCLR((uint32_t)&__deployment_start__); + } + } + } + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in new file mode 100644 index 0000000000..ec5e9be940 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..966b5a01c7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) +list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) + +if(GECKO_FEATURE_USBD_HID) + list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) +endif() + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld new file mode 100644 index 0000000000..e4ef8fc200 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR-DEBUG.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld new file mode 100644 index 0000000000..d17abebca3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld @@ -0,0 +1,246 @@ +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c new file mode 100644 index 0000000000..2b709b5441 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -0,0 +1,210 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = false; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..be11ba01ad --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" + +#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c new file mode 100644 index 0000000000..f058c33353 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/usb_hid_app.c @@ -0,0 +1,244 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +#include +#include "sl_usbd_class_hid.h" +#include + +// Task configuration +#define TASK_STACK_SIZE 512u +#define TASK_PRIO 5u +#define TASK_DELAY_MS 100u + +#define USB_HID_REPORT_LEN 4u + +// FreeRTOS Task handle +static TX_THREAD task_handle; +uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; + +// Mouse report buffer. +__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; + +static void hid_task(uint32_t p_arg); + +// Initialize application. +void usb_device_hid_app_init(void) +{ + uint16_t status; + + // Create application task + status = tx_thread_create( + &task_handle, + "USB HID task", + hid_task, + (uint32_t)&sl_usbd_hid_hid0_number, + hidThreadStack, + TASK_STACK_SIZE, + TASK_PRIO, + TASK_PRIO, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + _ASSERTE(status == TX_SUCCESS); +} + +// hid_task() +// Perform HID writes to host. +// @param p_arg Task argument pointer. Class number in this case. +static void hid_task(uint32_t p_arg) +{ + uint8_t class_nbr = *(uint8_t *)p_arg; + bool x_is_pos = true; + bool y_is_pos = true; + bool conn; + sl_status_t status; + uint32_t xfer_len = 0; + const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); + + usb_hid_report_buffer[0u] = 0u; + usb_hid_report_buffer[1u] = 0u; + + while (true) + { + + // Wait for device connection. + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + _ASSERTE(status == SL_STATUS_OK); + + while (conn != true) + { + tx_thread_sleep(xDelay); + + status = sl_usbd_hid_is_enabled(class_nbr, &conn); + + _ASSERTE(status == SL_STATUS_OK); + } + + // Emulates back and fourth movement. + ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; + ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; + + x_is_pos = !x_is_pos; + y_is_pos = !y_is_pos; + + // Send report. + status = + sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); + + // Delay Task + tx_thread_sleep(xDelay); + } +} + +// USB bus events. +void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) +{ + switch (event) + { + case SL_USBD_EVENT_BUS_CONNECT: + // called when usb cable is inserted in a host controller + break; + + case SL_USBD_EVENT_BUS_DISCONNECT: + // called when usb cable is removed from a host controller + break; + + case SL_USBD_EVENT_BUS_RESET: + // called when the host sends reset command + break; + + case SL_USBD_EVENT_BUS_SUSPEND: + // called when the host sends suspend command + break; + + case SL_USBD_EVENT_BUS_RESUME: + // called when the host sends wake up command + break; + + default: + break; + } +} + +// USB configuration events. +void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) +{ + (void)config_nbr; + + switch (event) + { + case SL_USBD_EVENT_CONFIG_SET: + // called when the host sets a configuration after reset + break; + + case SL_USBD_EVENT_CONFIG_UNSET: + // called when a configuration is unset due to reset command + break; + + default: + break; + } +} + +// HID mouse0 instance Enable event. +void sl_usbd_hid_hid0_on_enable_event(void) +{ + // Called when the HID device is connected to the USB host and a + // RESET transfer succeeded. +} + +// HID mouse0 instance Disable event. +void sl_usbd_hid_hid0_on_disable_event(void) +{ + // Called when the HID device is disconnected to the USB host (cable removed). +} + +// Hook function to pass the HID descriptor of the mouse0 instance. +void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve its HID descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Hook function to pass the HID PHY descriptor. +void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) +{ + // Called during the HID mouse0 instance initialization so the USB stack + // can retrieve the its HID physical descriptor. + (void)p_report_ptr; + (void)p_report_len; +} + +// Notification of a new set report received on control endpoint. +// @param report_id Report ID. +// @param p_report_buf Pointer to report buffer. +// @param report_len Length of report, in octets. +void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport request. + // The application can take action in function of the report content. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Get HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID must not be written into the feature report buffer. +void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a GetReport(feature) request. + // The application can provide the report to send by copying it in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Set HID feature report corresponding to report ID. +// @param report_id Report ID. +// @param p_report_buf Pointer to feature report buffer. +// @param report_len Length of report, in octets. +// @note (1) Report ID is not present in the feature report buffer. +void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) +{ + // This function is called when host issues a SetReport(Feature) request. + // The application can take action in function of the provided report in p_report_buf. + + (void)report_id; + (void)p_report_buf; + (void)report_len; +} + +// Retrieve active protocol: BOOT or REPORT protocol. +// @param p_protocol Pointer to variable that will receive the protocol type. +void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) +{ + // This function is called when host issues a GetProtocol request. + // The application should return the current protocol. + (void)p_protocol; +} + +// Store active protocol: BOOT or REPORT protocol. +// @param protocol Protocol. +void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) +{ + // This function is called when host issues a SetProtocol request. + // The application should apply the new protocol. + (void)protocol; +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c new file mode 100644 index 0000000000..ad32a4cff7 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &SL_MscFlash_BlockStorageInterface, + &Device_BlockStorageConfig, + false); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h new file mode 100644 index 0000000000..0771bccc7b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp new file mode 100644 index 0000000000..45f236e7a8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C0 // +////////// + +// SCL: PA1 +// SDA: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// SCL: PC5 +// SDA: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h new file mode 100644 index 0000000000..ff99df51a3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_i2c_config.h @@ -0,0 +1,4 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp new file mode 100644 index 0000000000..6c5b724749 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) +// num is the USART index. For example, if using USART0 use 0. + +////////// +// SPI0 // +////////// + +// USART0 +// SCK: PE12 +// MOSI: PE10 +// MISO: PE11 +// CS: PE13 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(0, 0, 0, 0, 0) + +////////// +// SPI1 // +////////// + +// USART1 +// SCK: PD2 +// MOSI: PD0 +// MISO: PD1 +// CS: PD3 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// USART2 +// SCK: PB5 +// MOSI: PB3 +// MISO: PB4 +// CS: PB6 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h new file mode 100644 index 0000000000..bdfea3503d --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_com_sky_nf_dev_spi_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI0 TRUE +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c new file mode 100644 index 0000000000..c2100dc5c5 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.c @@ -0,0 +1,27 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target can use J-Link for updates +inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); +inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in new file mode 100644 index 0000000000..e5a3715d66 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_common.h.in @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x000080000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "GGECKO_S1" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 512U +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp new file mode 100644 index 0000000000..a2de5db33c --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.cpp @@ -0,0 +1,52 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on SKY_CEVB1; CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +/* + +#include + +// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel +// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel +// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel +// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel +// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel +// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel +// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel +// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel +// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel +// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) +// PE6 (Gecko APORT3X CH6) ADC Cal Channel + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // IMON0 + {0, adcPosSelAPORT1XCH6}, + // + {0, adcPosSelAPORT2XCH7}, + // + {0, adcPosSelAPORT1XCH8}, + // + {0, adcPosSelAPORT2XCH9}, + // + {0, adcPosSelAPORT1XCH10}, + // + {0, adcPosSelAPORT2XCH11}, + // + {0, adcPosSelAPORT1XCH12}, + // + {0, adcPosSelAPORT2XCH13}, + // + {0, adcPosSelAPORT1XCH14}, + // + {0, adcPosSelAPORT2XCH15}, + // + {0, adcPosSelAPORT3XCH6}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h new file mode 100644 index 0000000000..e203cd7428 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nano_gg_adc_config.h @@ -0,0 +1,9 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// No ADC on SKY_CEVB1; CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF + +#define GECKO_USE_ADC0 FALSE +#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..b5d0ffb355 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_nf_dev_onewire_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART0 // +/////////// + +// enable USART0 +#define NF_ONEWIRE_USE_USART0 TRUE + +// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c new file mode 100644 index 0000000000..efb9bced52 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.c @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h new file mode 100644 index 0000000000..d560ea678f --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_stdio_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.cpp @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h new file mode 100644 index 0000000000..370059f6f8 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_adc_config.h @@ -0,0 +1,6 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..6e7b275464 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* + +////////// +// I2C0 // +////////// + +// pin configuration for I2C0 +// port for I2C0_SCL is: PA1 +// port for I2C0_SDA is: PA0 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for I2C1_SCL is: PC5 +// port for I2C1_SDA is: PC4 + +// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h new file mode 100644 index 0000000000..c81f83afe3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_i2c_config.h @@ -0,0 +1,8 @@ +// Copyright Skyworks Solutions, Inc. All Rights Reserved. + +/* + +#define GECKO_USE_I2C0 TRUE +#define GECKO_USE_I2C1 TRUE + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp new file mode 100644 index 0000000000..7653e6d1c4 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_pwm_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { + + // using WTIMER0, CC0, PC1, location 7 + {0, 0, gpioPortC, 1, 7}, + // using WTIMER1, CC2, PI1, location 5 + {1, 2, gpioPortI, 1, 5}, + +}; + +const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..3bf95a0eb3 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/* +////////// +// SPI1 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI1_SCK: PD2, location 1 +// SPI1_MOSI: PD0, location 1 +// SPI1_MISO: PD1, location 1 +// SPI1_CS: PD3, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(1, 1, 1, 1) + +////////// +// SPI2 // +////////// + +// pin configuration for SPI1 (mapped to USART1 on this device) +// SPI2_SCK: PF8, location 1 +// SPI2_MOSI: PF6, location 1 +// SPI2_MISO: PF7, location 1 +// SPI2_CS: PF9, location 1 +// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet + +INIT_SPI_CONFIG(2, 4, 4, 4) + +*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h new file mode 100644 index 0000000000..409945557b --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_device_spi_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#define GECKO_USE_SPI1 TRUE +#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..b7c0d87a23 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.cpp @@ -0,0 +1,4 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h new file mode 100644 index 0000000000..b2d2dec961 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_system_io_ports_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h new file mode 100644 index 0000000000..40c92111ed --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_tx_user.h @@ -0,0 +1,206 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef TX_USER_H +#define TX_USER_H + +#define TX_TIMER_TICKS_PER_SECOND 1000 + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +#define TX_REACTIVATE_INLINE + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +#define TX_DISABLE_REDUNDANT_CLEARING + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +#define TX_DISABLE_NOTIFY_CALLBACKS + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h new file mode 100644 index 0000000000..f655c33739 --- /dev/null +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/target_ux_user.h @@ -0,0 +1,345 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////// +// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file +// for nanoBooter and another for nanoCLR. +/////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +#define UX_MAX_CLASSES 1 + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 512 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + From 3291dc4a87d53beeeb3e1356ac156ae0afe848a3 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 20 Feb 2024 16:06:46 -0600 Subject: [PATCH 523/572] Add SKY_CEVB1 target, a generic CLR for use with current batch of CEVBs --- .github/workflows/Build_SKY_CEVB1_Debug.yaml | 11 +++++++++++ .github/workflows/Build_SKY_CEVB1_Release.yaml | 11 +++++++++++ 2 files changed, 22 insertions(+) create mode 100644 .github/workflows/Build_SKY_CEVB1_Debug.yaml create mode 100644 .github/workflows/Build_SKY_CEVB1_Release.yaml diff --git a/.github/workflows/Build_SKY_CEVB1_Debug.yaml b/.github/workflows/Build_SKY_CEVB1_Debug.yaml new file mode 100644 index 0000000000..285e70da19 --- /dev/null +++ b/.github/workflows/Build_SKY_CEVB1_Debug.yaml @@ -0,0 +1,11 @@ +name: Build SKY_CEVB1_Debug + +on: + workflow_dispatch + +jobs: + build_SKY_CEVB1_Debug: + name: Build SKY_CEVB1_Debug + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_CEVB1_Debug' diff --git a/.github/workflows/Build_SKY_CEVB1_Release.yaml b/.github/workflows/Build_SKY_CEVB1_Release.yaml new file mode 100644 index 0000000000..7efe3363b3 --- /dev/null +++ b/.github/workflows/Build_SKY_CEVB1_Release.yaml @@ -0,0 +1,11 @@ +name: Build SKY_CEVB1_Release + +on: + workflow_dispatch + +jobs: + build_SKY_CEVB1_Release: + name: Build SKY_CEVB1_Release + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: 'SKY_CEVB1_Release' From 628fea10e0bc775493b16bfda98ce35c5cc64251 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 20 Feb 2024 16:37:05 -0600 Subject: [PATCH 524/572] Add SKY_CEVB1 target, a generic CLR for use with current batch of CEVBs --- targets/AzureRTOS/CMakePresets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 966e8655b2..83a0579817 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -5,6 +5,7 @@ "SiliconLabs/SKY_EEVB/CMakePresets.json", "SiliconLabs/Si5575_CEVB/CMakePresets.json", "SiliconLabs/Si5400_CEVB/CMakePresets.json", + "SiliconLabs/SKY_CEVB1/CMakePresets.json", "SiliconLabs/STB_Interposer/CMakePresets.json", "SiliconLabs/FIELD_PROG/CMakePresets.json", "ST/ORGPAL_PALTHREE/CMakePresets.json", From a172e0a2247ef3636da8af8978d33614fae197e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Feb 2024 23:33:55 +0000 Subject: [PATCH 525/572] Increase block storage size for CLR --- .../SKY_CEVB1/common/Device_BlockStorage.c | 246 ++++----- .../SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld | 492 +++++++++--------- 2 files changed, 369 insertions(+), 369 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c index 09982097e3..08dd3b69c5 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c @@ -1,123 +1,123 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - - // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 66}, - - // 00043000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld index d17abebca3..ea35d0f4ad 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld @@ -1,246 +1,246 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld From 33eb053e093cc05e5a80dccabf64aad836b9621e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 20 Feb 2024 23:51:11 +0000 Subject: [PATCH 526/572] Increase size of storage block --- .../Si5400_CEVB/common/Device_BlockStorage.c | 246 ++++----- .../Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld | 492 +++++++++--------- 2 files changed, 369 insertions(+), 369 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c index 09982097e3..08dd3b69c5 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c @@ -1,123 +1,123 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - - // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 66}, - - // 00043000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld index d17abebca3..1eab59a72b 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld @@ -1,246 +1,246 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00042000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld From b9b52f23f7a26d1608aa0b286ee9f976e6e12c9a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 21 Feb 2024 07:59:05 -0600 Subject: [PATCH 527/572] Archive some Github actions for CLRs that will no longer be used --- .github/workflows/{ => Archived}/Build_SKY_EEVB_Release.yaml | 0 .../workflows/{ => Archived}/Build_SKY_EEVB_Watchdog_Debug.yaml | 0 .github/workflows/{ => Archived}/Build_Si5400_CEVB_Debug.yaml | 0 .github/workflows/{ => Archived}/Build_Si5400_CEVB_Release.yaml | 0 .github/workflows/{ => Archived}/Build_Si5575_CEVB_Debug.yaml | 0 .github/workflows/{ => Archived}/Build_Si5575_CEVB_Release.yaml | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename .github/workflows/{ => Archived}/Build_SKY_EEVB_Release.yaml (100%) rename .github/workflows/{ => Archived}/Build_SKY_EEVB_Watchdog_Debug.yaml (100%) rename .github/workflows/{ => Archived}/Build_Si5400_CEVB_Debug.yaml (100%) rename .github/workflows/{ => Archived}/Build_Si5400_CEVB_Release.yaml (100%) rename .github/workflows/{ => Archived}/Build_Si5575_CEVB_Debug.yaml (100%) rename .github/workflows/{ => Archived}/Build_Si5575_CEVB_Release.yaml (100%) diff --git a/.github/workflows/Build_SKY_EEVB_Release.yaml b/.github/workflows/Archived/Build_SKY_EEVB_Release.yaml similarity index 100% rename from .github/workflows/Build_SKY_EEVB_Release.yaml rename to .github/workflows/Archived/Build_SKY_EEVB_Release.yaml diff --git a/.github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml b/.github/workflows/Archived/Build_SKY_EEVB_Watchdog_Debug.yaml similarity index 100% rename from .github/workflows/Build_SKY_EEVB_Watchdog_Debug.yaml rename to .github/workflows/Archived/Build_SKY_EEVB_Watchdog_Debug.yaml diff --git a/.github/workflows/Build_Si5400_CEVB_Debug.yaml b/.github/workflows/Archived/Build_Si5400_CEVB_Debug.yaml similarity index 100% rename from .github/workflows/Build_Si5400_CEVB_Debug.yaml rename to .github/workflows/Archived/Build_Si5400_CEVB_Debug.yaml diff --git a/.github/workflows/Build_Si5400_CEVB_Release.yaml b/.github/workflows/Archived/Build_Si5400_CEVB_Release.yaml similarity index 100% rename from .github/workflows/Build_Si5400_CEVB_Release.yaml rename to .github/workflows/Archived/Build_Si5400_CEVB_Release.yaml diff --git a/.github/workflows/Build_Si5575_CEVB_Debug.yaml b/.github/workflows/Archived/Build_Si5575_CEVB_Debug.yaml similarity index 100% rename from .github/workflows/Build_Si5575_CEVB_Debug.yaml rename to .github/workflows/Archived/Build_Si5575_CEVB_Debug.yaml diff --git a/.github/workflows/Build_Si5575_CEVB_Release.yaml b/.github/workflows/Archived/Build_Si5575_CEVB_Release.yaml similarity index 100% rename from .github/workflows/Build_Si5575_CEVB_Release.yaml rename to .github/workflows/Archived/Build_Si5575_CEVB_Release.yaml From 0e85c56e40f0847c26dc8629a3719d2f7566f71d Mon Sep 17 00:00:00 2001 From: Laurent Ellerbach Date: Thu, 18 Apr 2024 09:18:46 -0400 Subject: [PATCH 528/572] Fixing disk size limitation when building large dev containers (#2913) ***NO_CI*** --- .github/workflows/devcontainer-all.yaml | 7 +++++++ .github/workflows/devcontainer-azurertos.yaml | 9 ++++++++- .github/workflows/devcontainer-chibios.yaml | 7 +++++++ .github/workflows/devcontainer-esp32.yml | 7 +++++++ .github/workflows/devcontainer-freertos-nxp.yaml | 8 ++++++++ .github/workflows/devcontainer-smoketest.yaml | 7 +++++++ .github/workflows/devcontainer-ti.yaml | 7 +++++++ 7 files changed, 51 insertions(+), 1 deletion(-) diff --git a/.github/workflows/devcontainer-all.yaml b/.github/workflows/devcontainer-all.yaml index a05b31a963..2056a4bcfc 100644 --- a/.github/workflows/devcontainer-all.yaml +++ b/.github/workflows/devcontainer-all.yaml @@ -25,6 +25,13 @@ jobs: - name: Checkout Repository uses: actions/checkout@v4 + + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true - name: Get container version run: | diff --git a/.github/workflows/devcontainer-azurertos.yaml b/.github/workflows/devcontainer-azurertos.yaml index a843611501..c2772935b8 100644 --- a/.github/workflows/devcontainer-azurertos.yaml +++ b/.github/workflows/devcontainer-azurertos.yaml @@ -22,10 +22,17 @@ jobs: if: ${{ vars.PUBLISH_DOCKER_IMAGE == 'true' }} runs-on: ubuntu-latest steps: - + - name: Checkout Repository uses: actions/checkout@v4 + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true + - name: Get container version run: | $dockerfileContent = Get-Content(".devcontainer/AzureRTOS/Dockerfile.AzureRTOS") diff --git a/.github/workflows/devcontainer-chibios.yaml b/.github/workflows/devcontainer-chibios.yaml index 52f4bf4471..5a2449b46a 100644 --- a/.github/workflows/devcontainer-chibios.yaml +++ b/.github/workflows/devcontainer-chibios.yaml @@ -26,6 +26,13 @@ jobs: - name: Checkout Repository uses: actions/checkout@v4 + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true + - name: Get container version run: | $dockerfileContent = Get-Content(".devcontainer/ChibiOS/Dockerfile.ChibiOS") diff --git a/.github/workflows/devcontainer-esp32.yml b/.github/workflows/devcontainer-esp32.yml index 327c3fb794..7bff46d2be 100644 --- a/.github/workflows/devcontainer-esp32.yml +++ b/.github/workflows/devcontainer-esp32.yml @@ -26,6 +26,13 @@ jobs: - name: Checkout Repository uses: actions/checkout@v4 + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true + - name: Get container version run: | $dockerfileContent = Get-Content(".devcontainer/ESP32/Dockerfile.ESP32") diff --git a/.github/workflows/devcontainer-freertos-nxp.yaml b/.github/workflows/devcontainer-freertos-nxp.yaml index 20baaf3216..94f49bc76f 100644 --- a/.github/workflows/devcontainer-freertos-nxp.yaml +++ b/.github/workflows/devcontainer-freertos-nxp.yaml @@ -27,8 +27,16 @@ jobs: packages: write steps: + - name: Checkout Repository uses: actions/checkout@v4 + + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true - name: Get container version shell: pwsh diff --git a/.github/workflows/devcontainer-smoketest.yaml b/.github/workflows/devcontainer-smoketest.yaml index aaa8a03eb8..97adcde9ba 100644 --- a/.github/workflows/devcontainer-smoketest.yaml +++ b/.github/workflows/devcontainer-smoketest.yaml @@ -36,6 +36,13 @@ jobs: with: submodules: true + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true + - name: Update repo submodules run: | git submodule update --init diff --git a/.github/workflows/devcontainer-ti.yaml b/.github/workflows/devcontainer-ti.yaml index 4baf392cd2..6231c15b97 100644 --- a/.github/workflows/devcontainer-ti.yaml +++ b/.github/workflows/devcontainer-ti.yaml @@ -26,6 +26,13 @@ jobs: - name: Checkout Repository uses: actions/checkout@v4 + - name: Free Disk Space (Ubuntu) + uses: jlumbroso/free-disk-space@main + with: + # this might remove tools that are actually needed, + # when set to "true" but frees about 6 GB + tool-cache: true + - name: Get container version run: | $dockerfileContent = Get-Content(".devcontainer/TI/Dockerfile.TI") From b1815ea64a806da2decfec678bb91128cde95768 Mon Sep 17 00:00:00 2001 From: Laurent Ellerbach Date: Thu, 18 Apr 2024 11:11:13 -0400 Subject: [PATCH 529/572] Fixing DevContainer cleaning image too deep (#2914) --- .github/workflows/devcontainer-all.yaml | 1 + .github/workflows/devcontainer-azurertos.yaml | 1 + .github/workflows/devcontainer-chibios.yaml | 1 + .github/workflows/devcontainer-esp32.yml | 1 + .github/workflows/devcontainer-freertos-nxp.yaml | 1 + .github/workflows/devcontainer-smoketest.yaml | 1 + .github/workflows/devcontainer-ti.yaml | 1 + 7 files changed, 7 insertions(+) diff --git a/.github/workflows/devcontainer-all.yaml b/.github/workflows/devcontainer-all.yaml index 2056a4bcfc..6419e8cf84 100644 --- a/.github/workflows/devcontainer-all.yaml +++ b/.github/workflows/devcontainer-all.yaml @@ -32,6 +32,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Get container version run: | diff --git a/.github/workflows/devcontainer-azurertos.yaml b/.github/workflows/devcontainer-azurertos.yaml index c2772935b8..2c88eff37f 100644 --- a/.github/workflows/devcontainer-azurertos.yaml +++ b/.github/workflows/devcontainer-azurertos.yaml @@ -32,6 +32,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Get container version run: | diff --git a/.github/workflows/devcontainer-chibios.yaml b/.github/workflows/devcontainer-chibios.yaml index 5a2449b46a..e7d889cb7f 100644 --- a/.github/workflows/devcontainer-chibios.yaml +++ b/.github/workflows/devcontainer-chibios.yaml @@ -32,6 +32,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Get container version run: | diff --git a/.github/workflows/devcontainer-esp32.yml b/.github/workflows/devcontainer-esp32.yml index 7bff46d2be..615fbe127e 100644 --- a/.github/workflows/devcontainer-esp32.yml +++ b/.github/workflows/devcontainer-esp32.yml @@ -32,6 +32,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Get container version run: | diff --git a/.github/workflows/devcontainer-freertos-nxp.yaml b/.github/workflows/devcontainer-freertos-nxp.yaml index 94f49bc76f..55fb97e48a 100644 --- a/.github/workflows/devcontainer-freertos-nxp.yaml +++ b/.github/workflows/devcontainer-freertos-nxp.yaml @@ -37,6 +37,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Get container version shell: pwsh diff --git a/.github/workflows/devcontainer-smoketest.yaml b/.github/workflows/devcontainer-smoketest.yaml index 97adcde9ba..fc60fc15f8 100644 --- a/.github/workflows/devcontainer-smoketest.yaml +++ b/.github/workflows/devcontainer-smoketest.yaml @@ -42,6 +42,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Update repo submodules run: | diff --git a/.github/workflows/devcontainer-ti.yaml b/.github/workflows/devcontainer-ti.yaml index 6231c15b97..54e4392b39 100644 --- a/.github/workflows/devcontainer-ti.yaml +++ b/.github/workflows/devcontainer-ti.yaml @@ -32,6 +32,7 @@ jobs: # this might remove tools that are actually needed, # when set to "true" but frees about 6 GB tool-cache: true + large-packages: false - name: Get container version run: | From e9f8d941598019f41ba01723954bfaebc6dc6867 Mon Sep 17 00:00:00 2001 From: Cory Charlton Date: Wed, 24 Apr 2024 01:01:22 -0700 Subject: [PATCH 530/572] Properly offset managed SPI bus ID to native for ESP32C3 and S3 (#2915) --- targets/ESP32/_common/Target_Windows_Storage.c | 4 +++- targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/targets/ESP32/_common/Target_Windows_Storage.c b/targets/ESP32/_common/Target_Windows_Storage.c index 5ceb9a2bf2..9303b5d629 100644 --- a/targets/ESP32/_common/Target_Windows_Storage.c +++ b/targets/ESP32/_common/Target_Windows_Storage.c @@ -160,8 +160,10 @@ bool Storage_MountSpi(int spiBus, uint32_t csPin, int driveIndex) sdmmc_host_t host = SDSPI_HOST_DEFAULT(); #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) - host.slot = spiBus; + // First available bus on ESP32_C3/S3 is SPI2_HOST + host.slot = spiBus + SPI2_HOST; #else + // First available bus on ESP32 is HSPI_HOST(1) host.slot = spiBus + HSPI_HOST; #endif diff --git a/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 260e0da772..abffbececc 100644 --- a/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -189,8 +189,10 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev if (ret != ESP_OK) { #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) - ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex, ret); + // First available bus on ESP32_C3/S3 is SPI2_HOST + ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + SPI2_HOST, ret); #else + // First available bus on ESP32 is HSPI_HOST(1) ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + HSPI_HOST, ret); #endif return false; @@ -208,16 +210,20 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev bool CPU_SPI_Uninitialize(uint8_t busIndex) { #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) - esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex)); + // First available bus on ESP32_C3/S3 is SPI2_HOST + esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + SPI2_HOST)); #else + // First available bus on ESP32 is HSPI_HOST(1) esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + HSPI_HOST)); #endif if (ret != ESP_OK) { #if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) - ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex, ret); + // First available bus on ESP32_C3/S3 is SPI2_HOST + ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + SPI2_HOST, ret); #else + // First available bus on ESP32 is HSPI_HOST(1) ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + HSPI_HOST, ret); #endif From 3990335a8690d6dbef4dd7f0b563639c5fe00c3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 24 Apr 2024 15:18:36 +0100 Subject: [PATCH 531/572] Add call to WP PrepareReception to allow target specific code (#2917) ***NO_CI*** --- targets/ChibiOS/_common/WireProtocol_ReceiverThread.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/targets/ChibiOS/_common/WireProtocol_ReceiverThread.c b/targets/ChibiOS/_common/WireProtocol_ReceiverThread.c index 4a2ba7954a..cbb4b0c5e6 100644 --- a/targets/ChibiOS/_common/WireProtocol_ReceiverThread.c +++ b/targets/ChibiOS/_common/WireProtocol_ReceiverThread.c @@ -19,8 +19,6 @@ __attribute__((noreturn)) void ReceiverThread(void const *argument) { (void)argument; - osDelay(500); - WP_Message_PrepareReception(); // loop until thread receives a request to terminate @@ -53,7 +51,12 @@ __attribute__((noreturn)) void ReceiverThread(void const *argument) // this function never returns } +__nfweak void WP_Message_PrepareReception_Target() +{ + // empty on purpose, to be implemented by target if needed +} + void WP_Message_PrepareReception_Platform() { - // empty on purpose, nothing to configure + WP_Message_PrepareReception_Target(); } From 551c0fb7d47f7b17bb037d19e47de60f474db47d Mon Sep 17 00:00:00 2001 From: josesimoes Date: Fri, 26 Apr 2024 19:45:09 +0100 Subject: [PATCH 532/572] Maintenance of Skyworks github action - Bump all actions to latest available (required because of deprecation and/or security warnings from runner). --- .github/workflows/merge-upstream-skyworks-evb.yml | 2 +- .github/workflows/merge-upstream.yml | 2 +- .github/workflows/skyworks_evb_build.yaml | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/merge-upstream-skyworks-evb.yml b/.github/workflows/merge-upstream-skyworks-evb.yml index 050bea6594..5311eab17f 100644 --- a/.github/workflows/merge-upstream-skyworks-evb.yml +++ b/.github/workflows/merge-upstream-skyworks-evb.yml @@ -11,7 +11,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: ref: skyworks-evb fetch-depth: 0 diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml index 3a3b54193c..c863fb7cfe 100644 --- a/.github/workflows/merge-upstream.yml +++ b/.github/workflows/merge-upstream.yml @@ -11,7 +11,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: ref: main fetch-depth: 0 diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 7862cd84cf..126420537c 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -15,7 +15,7 @@ jobs: runs-on: windows-latest steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 with: fetch-depth: 0 ref: 'skyworks-evb' @@ -104,7 +104,7 @@ jobs: $metadata | Out-File -FilePath $file -Encoding utf-8 -Append - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@v4 with: name: '${{ inputs.targetName }}-v${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}' path: | @@ -114,7 +114,7 @@ jobs: - name: Tag the build if: ${{ github.event.pull_request.number == null }} - uses: actions/github-script@v6 + uses: actions/github-script@v7 with: script: | const {DIST_VERSION} = process.env From 358036c16def9cd61c5c7c754cffb61f913d3ce3 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 6 May 2024 16:10:32 +0100 Subject: [PATCH 533/572] Update Gecko SDK to v4.4.3 - Changes in CMake files. - Adjust header files as required. --- CMake/Modules/FindGecko_SDK.cmake | 2 +- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 42993d59a6..08f0d79e9c 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -129,7 +129,7 @@ set(gecko_sdk_srcs sl_event_handler.c sl_board_default_init_stub.c sl_i2cspm_init.c - sli_crypto_trng_driver.c + sli_crypto_driver_trng.c # candidate for replacement with RTOS friendly version sl_i2cspm.c sl_string.c diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 951fcdfd2e..f5e29715ea 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -71,7 +71,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.4.0") + set(GECKO_SDK_VERSION "v4.4.3") endif() if(NO_GECKO_SDK_SOURCE) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp index b80ceeb883..5d4843ab4d 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetRandom.cpp @@ -4,7 +4,7 @@ // #include "Core.h" #include -#include +#include void CLR_RT_Random::Initialize() { From fb29ba65304cc0fe22c37e15159d19fcae1ca3cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 15 May 2024 15:42:48 +0100 Subject: [PATCH 534/572] Improve booter run conditions check (#8) --- .../SiliconLabs/FIELD_PROG/nanoBooter/main.c | 27 ++++++++++++++++--- .../SiliconLabs/SKY_EEVB/nanoBooter/main.c | 26 +++++++++++++++--- .../SiliconLabs/SKY_EEVB/nanoCLR/main.c | 2 +- .../STB_Interposer/nanoBooter/main.c | 26 +++++++++++++++--- .../SiliconLabs/STB_Interposer/nanoCLR/main.c | 2 +- .../SiliconLabs/Si5575_CEVB/nanoBooter/main.c | 26 +++++++++++++++--- .../SiliconLabs/Si5575_CEVB/nanoCLR/main.c | 2 +- 7 files changed, 92 insertions(+), 19 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c index 0787f4a6a5..a7beef37d6 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c @@ -21,6 +21,9 @@ extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -151,12 +154,28 @@ int main(void) // init boot clipboard InitBootClipboard(); - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // check if there is a request to remain on nanoBooter - if (!IsToRemainInBooter()) + if (IsToRemainInBooter()) { + // check if error code is for a missing deployment image + if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // yes, remain on booter waiting for a deployment image to be flashed + } + else + { + // some other error, proceed with usual workflow + goto checkRemainBooter; + } + } + else + { + + checkRemainBooter: + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c index 0787f4a6a5..ae8dc77a3e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c @@ -21,6 +21,9 @@ extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -151,12 +154,27 @@ int main(void) // init boot clipboard InitBootClipboard(); - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // check if there is a request to remain on nanoBooter - if (!IsToRemainInBooter()) + if (IsToRemainInBooter()) + { + // check if error code is for a missing deployment image + if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // yes, remain on booter waiting for a deployment image to be flashed + } + else + { + // some other error, proceed with usual workflow + goto checkRemainBooter; + } + } + else { + + checkRemainBooter: + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c index 2b709b5441..78bd76d0f1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c @@ -138,7 +138,7 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = false; + clrSettings.RevertToBooterOnFault = true; // do NOT enter debugger loop on RTM builds // this will cause the board to keep rebooting until there is an application deployed diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c index 0787f4a6a5..ae8dc77a3e 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c @@ -21,6 +21,9 @@ extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -151,12 +154,27 @@ int main(void) // init boot clipboard InitBootClipboard(); - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // check if there is a request to remain on nanoBooter - if (!IsToRemainInBooter()) + if (IsToRemainInBooter()) + { + // check if error code is for a missing deployment image + if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // yes, remain on booter waiting for a deployment image to be flashed + } + else + { + // some other error, proceed with usual workflow + goto checkRemainBooter; + } + } + else { + + checkRemainBooter: + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c index 2b709b5441..78bd76d0f1 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c @@ -138,7 +138,7 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = false; + clrSettings.RevertToBooterOnFault = true; // do NOT enter debugger loop on RTM builds // this will cause the board to keep rebooting until there is an application deployed diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c index 0787f4a6a5..ae8dc77a3e 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c @@ -21,6 +21,9 @@ extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -151,12 +154,27 @@ int main(void) // init boot clipboard InitBootClipboard(); - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // check if there is a request to remain on nanoBooter - if (!IsToRemainInBooter()) + if (IsToRemainInBooter()) + { + // check if error code is for a missing deployment image + if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // yes, remain on booter waiting for a deployment image to be flashed + } + else + { + // some other error, proceed with usual workflow + goto checkRemainBooter; + } + } + else { + + checkRemainBooter: + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c index 2b709b5441..78bd76d0f1 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c @@ -138,7 +138,7 @@ void tx_application_define(void *first_unused_memory) clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = false; + clrSettings.RevertToBooterOnFault = true; // do NOT enter debugger loop on RTM builds // this will cause the board to keep rebooting until there is an application deployed From 87f40b5f0043010dcf7a4a824e888e10134cfcb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 15 May 2024 15:39:59 +0100 Subject: [PATCH 535/572] Enable CLR startup option to remain on booter --- .../SiliconLabs/FIELD_PROG/nanoCLR/main.c | 420 +++++++++--------- .../SiliconLabs/SKY_CEVB1/nanoCLR/main.c | 420 +++++++++--------- .../SiliconLabs/Si5400_CEVB/nanoCLR/main.c | 420 +++++++++--------- 3 files changed, 630 insertions(+), 630 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c index 2b709b5441..fbf36d4be1 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c @@ -1,210 +1,210 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = false; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c index 2b709b5441..fbf36d4be1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -1,210 +1,210 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = false; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c index 2b709b5441..fbf36d4be1 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c @@ -1,210 +1,210 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = false; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} From 667386643be9df68a4ed0808b8ed83e3bf0d890a Mon Sep 17 00:00:00 2001 From: josesimoes Date: Wed, 15 May 2024 16:25:51 +0100 Subject: [PATCH 536/572] Add missing processing for remaining in nanobooter --- .../SiliconLabs/SKY_CEVB1/nanoBooter/main.c | 26 ++++++++++++++++--- .../SiliconLabs/Si5400_CEVB/nanoBooter/main.c | 26 ++++++++++++++++--- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c index 0787f4a6a5..ae8dc77a3e 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c @@ -21,6 +21,9 @@ extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -151,12 +154,27 @@ int main(void) // init boot clipboard InitBootClipboard(); - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // check if there is a request to remain on nanoBooter - if (!IsToRemainInBooter()) + if (IsToRemainInBooter()) + { + // check if error code is for a missing deployment image + if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // yes, remain on booter waiting for a deployment image to be flashed + } + else + { + // some other error, proceed with usual workflow + goto checkRemainBooter; + } + } + else { + + checkRemainBooter: + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c index 0787f4a6a5..ae8dc77a3e 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c @@ -21,6 +21,9 @@ extern void sli_usbd_configuration_config0_init(void); extern void sli_usbd_cdc_acm_acm0_init(void); extern void usb_device_cdc_acm_app_init(void); +// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND +#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) + // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -151,12 +154,27 @@ int main(void) // init boot clipboard InitBootClipboard(); - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // check if there is a request to remain on nanoBooter - if (!IsToRemainInBooter()) + if (IsToRemainInBooter()) + { + // check if error code is for a missing deployment image + if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) + { + // yes, remain on booter waiting for a deployment image to be flashed + } + else + { + // some other error, proceed with usual workflow + goto checkRemainBooter; + } + } + else { + + checkRemainBooter: + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { From 5ef19a2db1c0f6bd8fabb7b3166664ea014e20ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 31 May 2024 13:21:48 +0100 Subject: [PATCH 537/572] Rework check to remain on booter (#13) --- .../SiliconLabs/FIELD_PROG/nanoBooter/main.c | 26 +++++-------------- .../SiliconLabs/SKY_CEVB1/nanoBooter/main.c | 24 +++++------------ .../SiliconLabs/SKY_EEVB/nanoBooter/main.c | 24 +++++------------ .../STB_Interposer/nanoBooter/main.c | 24 +++++------------ .../SiliconLabs/Si5400_CEVB/nanoBooter/main.c | 24 +++++------------ .../SiliconLabs/Si5575_CEVB/nanoBooter/main.c | 24 +++++------------ 6 files changed, 37 insertions(+), 109 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c index a7beef37d6..c31008e084 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoBooter/main.c @@ -148,36 +148,24 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - // configure + // configure S2 switch for input GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); // init boot clipboard InitBootClipboard(); // check if there is a request to remain on nanoBooter - if (IsToRemainInBooter()) + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) { - // check if error code is for a missing deployment image - if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // yes, remain on booter waiting for a deployment image to be flashed - } - else - { - // some other error, proceed with usual workflow - goto checkRemainBooter; - } + // do not load CLR, remain in nanoBooter } else { - - checkRemainBooter: - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - - // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) + { // check for valid CLR image // we are checking for a valid image at the deployment address, which is pointing to the CLR address diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c index ae8dc77a3e..e0a0dcde98 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoBooter/main.c @@ -148,34 +148,22 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - // configure + // configure S2 switch for input GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); // init boot clipboard InitBootClipboard(); // check if there is a request to remain on nanoBooter - if (IsToRemainInBooter()) + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) { - // check if error code is for a missing deployment image - if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // yes, remain on booter waiting for a deployment image to be flashed - } - else - { - // some other error, proceed with usual workflow - goto checkRemainBooter; - } + // do not load CLR, remain in nanoBooter } else { - - checkRemainBooter: - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { // check for valid CLR image diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c index ae8dc77a3e..e0a0dcde98 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoBooter/main.c @@ -148,34 +148,22 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - // configure + // configure S2 switch for input GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); // init boot clipboard InitBootClipboard(); // check if there is a request to remain on nanoBooter - if (IsToRemainInBooter()) + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) { - // check if error code is for a missing deployment image - if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // yes, remain on booter waiting for a deployment image to be flashed - } - else - { - // some other error, proceed with usual workflow - goto checkRemainBooter; - } + // do not load CLR, remain in nanoBooter } else { - - checkRemainBooter: - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { // check for valid CLR image diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c index ae8dc77a3e..e0a0dcde98 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoBooter/main.c @@ -148,34 +148,22 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - // configure + // configure S2 switch for input GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); // init boot clipboard InitBootClipboard(); // check if there is a request to remain on nanoBooter - if (IsToRemainInBooter()) + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) { - // check if error code is for a missing deployment image - if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // yes, remain on booter waiting for a deployment image to be flashed - } - else - { - // some other error, proceed with usual workflow - goto checkRemainBooter; - } + // do not load CLR, remain in nanoBooter } else { - - checkRemainBooter: - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { // check for valid CLR image diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c index ae8dc77a3e..e0a0dcde98 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c @@ -148,34 +148,22 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - // configure + // configure S2 switch for input GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); // init boot clipboard InitBootClipboard(); // check if there is a request to remain on nanoBooter - if (IsToRemainInBooter()) + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) { - // check if error code is for a missing deployment image - if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // yes, remain on booter waiting for a deployment image to be flashed - } - else - { - // some other error, proceed with usual workflow - goto checkRemainBooter; - } + // do not load CLR, remain in nanoBooter } else { - - checkRemainBooter: - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { // check for valid CLR image diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c index ae8dc77a3e..e0a0dcde98 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c @@ -148,34 +148,22 @@ int main(void) // configure LED READY for output GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - // configure + // configure S2 switch for input GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); // init boot clipboard InitBootClipboard(); // check if there is a request to remain on nanoBooter - if (IsToRemainInBooter()) + // or if there is an error code for a missing deployment + if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) { - // check if error code is for a missing deployment image - if (g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // yes, remain on booter waiting for a deployment image to be flashed - } - else - { - // some other error, proceed with usual workflow - goto checkRemainBooter; - } + // do not load CLR, remain in nanoBooter } else { - - checkRemainBooter: - - // the following IF is not mandatory, it's just providing a way for a user to 'force' - // the board to remain in nanoBooter and not launching nanoCLR - // if the BTN0 is pressed, skip the check for a valid CLR image and remain in booter + // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR + // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter if (GPIO_PinInGet(gpioPortE, 8) != 0) { // check for valid CLR image From c76345d8f7e0d0c634adad7d524a4331b9492d75 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Jun 2024 08:38:11 -0500 Subject: [PATCH 538/572] Commit to try to rev build # --- CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 63428947dc..461dbc58f7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -3,6 +3,8 @@ # See LICENSE file in the project root for full license information. # +# Update to see if CLR build # changes + cmake_minimum_required(VERSION 3.24) include(CMakeToolsHelpers OPTIONAL) From c113c76ab514925d1ec634062ea7ba1b9faea76a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Jun 2024 08:40:25 -0500 Subject: [PATCH 539/572] Revert "Commit to try to rev build #" This reverts commit c76345d8f7e0d0c634adad7d524a4331b9492d75. --- CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 461dbc58f7..63428947dc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -3,8 +3,6 @@ # See LICENSE file in the project root for full license information. # -# Update to see if CLR build # changes - cmake_minimum_required(VERSION 3.24) include(CMakeToolsHelpers OPTIONAL) From bd1a6a2f423c8f59ab7cf07b4eed29df50080d75 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Jun 2024 08:43:22 -0500 Subject: [PATCH 540/572] Force 999 CLR build # in version for CLR flash testing --- .github/workflows/skyworks_evb_build.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 126420537c..9379389d01 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -86,7 +86,8 @@ jobs: - uses: lukka/run-cmake@v10 with: configurePreset: '${{ inputs.targetName }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.999','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + # configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" buildPreset: '${{ inputs.targetName }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" From 8ea81c5daf657c41fa798937b80743179202e6ec Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Tue, 4 Jun 2024 16:50:20 -0500 Subject: [PATCH 541/572] Revert "Force 999 CLR build # in version for CLR flash testing" This reverts commit bd1a6a2f423c8f59ab7cf07b4eed29df50080d75. --- .github/workflows/skyworks_evb_build.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 9379389d01..126420537c 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -86,8 +86,7 @@ jobs: - uses: lukka/run-cmake@v10 with: configurePreset: '${{ inputs.targetName }}' - configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.999','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" - # configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" + configurePresetAdditionalArgs: "['-DBUILD_VERSION=${{env.NBGV_VersionMajor}}.${{env.NBGV_VersionMinor}}.${{env.NBGV_BuildNumber}}.${{env.NBGV_VersionHeight}}','-DCMAKE_BUILD_TYPE=MinSizeRel','-DTOOL_SRECORD_PREFIX=${{ env.SRECORD_PATH }}']" buildPreset: '${{ inputs.targetName }}' buildPresetAdditionalArgs: "['--config MinSizeRel']" From 9735d410923b85dd14f71aced1cfa2e0361edffa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Wed, 5 Jun 2024 15:03:13 +0100 Subject: [PATCH 542/572] Increase CLR block storage for FIELD_PROG --- .../SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c | 6 +++--- .../SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c index 09982097e3..e4792d9bb0 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/common/Device_BlockStorage.c @@ -13,10 +13,10 @@ const BlockRange BlockRange1[] = { {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 66}, + {BlockRange_BLOCKTYPE_CODE, 12, 67}, - // 00043000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, /////////////////////////////////////////////////////////////////////////////////////// // because this target is using a configuration block need to add the diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld index d17abebca3..75f91c7370 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/efm32gg11b_CLR.ld @@ -32,8 +32,8 @@ __RAM_segment_used_end__ = 0; MEMORY { - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ From 5ffadc02ca0fca9993014eb3774e28d50ddf3eda Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 13 Jun 2024 14:06:54 +0100 Subject: [PATCH 543/572] Improvements in Gecko USB stack usage - Remove nano hacks. - Revert to official SDK code. *** PR upstream *** --- CMake/Modules/FindGecko_SDK.cmake | 4 ++-- .../SiliconLabs/_common/nano_sl_usbd_core.c | 17 ++++++++++------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 08f0d79e9c..1404436a4f 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -184,7 +184,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_class_cdc.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) - list(APPEND gecko_sdk_srcs nano_sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_init.c) list(APPEND gecko_sdk_srcs sl_malloc.c) @@ -196,7 +196,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_class_vendor_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) - list(APPEND gecko_sdk_srcs nano_sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) list(APPEND gecko_sdk_srcs nano_sl_usbd_class_vendor.c) diff --git a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c index a9b9ad67ef..09cc6b135f 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c +++ b/targets/AzureRTOS/SiliconLabs/_common/nano_sl_usbd_core.c @@ -986,12 +986,12 @@ sl_status_t sl_usbd_core_add_interface(uint8_t cfg_nbr, p_dev = &usbd_ptr->device; // [NF_CHANGE] +// Following SDKv4.4.0 is now OK to perform this check here // Chk curr dev state. -// { -// if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { -// *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; -// return SL_STATUS_INVALID_STATE; -// } + if ((p_dev->state != SL_USBD_DEVICE_STATE_NONE) && (p_dev->state != SL_USBD_DEVICE_STATE_INIT)) { + *p_if_nbr = SL_USBD_INTERFACE_NBR_NONE; + return SL_STATUS_INVALID_STATE; +} // [END_NF_CHANGE] // Get cfg struct. @@ -5543,8 +5543,11 @@ void sli_usbd_core_task_handler(void) sl_status_t status; #if SL_USBD_AUTO_START_USB_DEVICE == 1 - sl_usbd_core_stop_device(); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(50)); +// [NF_CHANGE] + // Starting at SDK 4.4.0 it's OK to start the USB device without stopping it first + // sl_usbd_core_stop_device(); + // tx_thread_sleep(TX_TICKS_PER_MILLISEC(50)); +// [END_NF_CHANGE] sl_usbd_core_start_device(); #endif From dab3ebfd7e25a3407fd0059106a8a9f778addffb Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 13 Jun 2024 17:20:17 +0100 Subject: [PATCH 544/572] Missing file rename --- CMake/Modules/FindGecko_SDK.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMake/Modules/FindGecko_SDK.cmake b/CMake/Modules/FindGecko_SDK.cmake index 1404436a4f..bbedcbad34 100644 --- a/CMake/Modules/FindGecko_SDK.cmake +++ b/CMake/Modules/FindGecko_SDK.cmake @@ -156,7 +156,7 @@ if("${TARGET_SERIES}" STREQUAL "EFM32GG11") list(APPEND gecko_sdk_srcs sl_usbd_class_hid.c) list(APPEND gecko_sdk_srcs sl_usbd_core_ep.c) list(APPEND gecko_sdk_srcs sl_usbd_core_azuretos.c) - list(APPEND gecko_sdk_srcs nano_sl_usbd_core.c) + list(APPEND gecko_sdk_srcs sl_usbd_core.c) list(APPEND gecko_sdk_srcs sl_usbd_driver_dwc_otg_fs.c) list(APPEND gecko_sdk_srcs sl_usbd_class_hid_instances.c) list(APPEND gecko_sdk_srcs sl_usbd_configuration_instances.c) From 7e8be52d7d4788a7138b1261c554ac6f973c6c9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 13 Jun 2024 16:53:32 +0100 Subject: [PATCH 545/572] Improve check to create stack trace for exception (#2963) ***NO_CI*** --- .../CorLib/corlib_native_System_Exception.cpp | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/CLR/CorLib/corlib_native_System_Exception.cpp b/src/CLR/CorLib/corlib_native_System_Exception.cpp index 912407df60..ea56c19fb2 100644 --- a/src/CLR/CorLib/corlib_native_System_Exception.cpp +++ b/src/CLR/CorLib/corlib_native_System_Exception.cpp @@ -12,10 +12,7 @@ struct ExceptionLookup }; static const ExceptionLookup c_ExceptionLookup[] = { -#define EL(hr, fld) \ - { \ - hr, &g_CLR_RT_WellKnownTypes.fld \ - } +#define EL(hr, fld) {hr, &g_CLR_RT_WellKnownTypes.fld} EL(CLR_E_APPDOMAIN_EXITED, m_AppDomainUnloadedException), EL(CLR_E_INVALID_PARAMETER, m_ArgumentException), EL(CLR_E_ARGUMENT_NULL, m_ArgumentNullException), @@ -196,18 +193,15 @@ HRESULT Library_corlib_native_System_Exception::SetStackTrace(CLR_RT_HeapBlock & #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (CLR_EE_DBG_IS(NoStackTraceInExceptions)) + if (CLR_EE_DBG_IS(NoStackTraceInExceptions) || CLR_EE_DBG_IS_NOT(Enabled)) { - // stack trace is DISABLED + // stack trace is DISABLED or no debugger is attached (void)dst; (void)array; - // create an empty array for the stack trace - NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( - obj[FIELD___stackTrace], - depth, - g_CLR_RT_WellKnownTypes.m_UInt8)); + // null the array that would hold the stack trace + obj[FIELD___stackTrace].SetObjectReference(NULL); } else { @@ -245,7 +239,7 @@ HRESULT Library_corlib_native_System_Exception::SetStackTrace(CLR_RT_HeapBlock & if (!g_CLR_RT_ExecutionEngine.m_fShuttingDown) #endif { - if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions)) + if (CLR_EE_DBG_IS_NOT(NoStackTraceInExceptions) && CLR_EE_DBG_IS(Enabled)) { CLR_RT_DUMP::EXCEPTION(*stack, ref); } From 005efa05a06adea34b4fd152cdd464d8925a767b Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 17 Jun 2024 14:41:07 +0100 Subject: [PATCH 546/572] More work on OOM exception --- .../CorLib/corlib_native_System_Exception.cpp | 17 +++++++--- src/CLR/Core/Execution.cpp | 6 ++-- src/CLR/Core/GarbageCollector.cpp | 1 - src/CLR/Core/TypeSystem.cpp | 34 ++++++------------- src/CLR/Diagnostics/Profiler.cpp | 7 ++-- src/CLR/Include/nanoCLR_Runtime.h | 6 ++-- 6 files changed, 30 insertions(+), 41 deletions(-) diff --git a/src/CLR/CorLib/corlib_native_System_Exception.cpp b/src/CLR/CorLib/corlib_native_System_Exception.cpp index ea56c19fb2..39a9162c44 100644 --- a/src/CLR/CorLib/corlib_native_System_Exception.cpp +++ b/src/CLR/CorLib/corlib_native_System_Exception.cpp @@ -12,7 +12,10 @@ struct ExceptionLookup }; static const ExceptionLookup c_ExceptionLookup[] = { -#define EL(hr, fld) {hr, &g_CLR_RT_WellKnownTypes.fld} +#define EL(hr, fld) \ + { \ + hr, &g_CLR_RT_WellKnownTypes.fld \ + } EL(CLR_E_APPDOMAIN_EXITED, m_AppDomainUnloadedException), EL(CLR_E_INVALID_PARAMETER, m_ArgumentException), EL(CLR_E_ARGUMENT_NULL, m_ArgumentNullException), @@ -125,9 +128,9 @@ HRESULT Library_corlib_native_System_Exception::CreateInstance( if (FAILED(hr = g_CLR_RT_ExecutionEngine.NewObjectFromIndex(ref, cls))) { #if defined(NANOCLR_APPDOMAINS) - ref.SetObjectReference(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->m_outOfMemoryException); + ref.SetObjectReference(&g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->m_outOfMemoryException); #else - ref.SetObjectReference(g_CLR_RT_ExecutionEngine.m_outOfMemoryException); + ref.SetObjectReference(&g_CLR_RT_ExecutionEngine.m_outOfMemoryException); #endif hrIn = CLR_E_OUT_OF_MEMORY; @@ -193,9 +196,13 @@ HRESULT Library_corlib_native_System_Exception::SetStackTrace(CLR_RT_HeapBlock & #if defined(NANOCLR_TRACE_EXCEPTIONS) - if (CLR_EE_DBG_IS(NoStackTraceInExceptions) || CLR_EE_DBG_IS_NOT(Enabled)) + if (CLR_EE_DBG_IS(NoStackTraceInExceptions) || CLR_EE_DBG_IS_NOT(Enabled) || CLR_EE_IS(Compaction_Pending) || + g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection) { - // stack trace is DISABLED or no debugger is attached + // stack trace is DISABLED or... + // no debugger is attached or... + // compaction is pending so better not mess around or... + // GC is requested or in progress so better not mess around (void)dst; (void)array; diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp index da81ac3ccf..a15143f427 100644 --- a/src/CLR/Core/Execution.cpp +++ b/src/CLR/Core/Execution.cpp @@ -86,9 +86,8 @@ HRESULT CLR_RT_ExecutionEngine::ExecutionEngine_Initialize() // CLR_RT_Thread* m_cctorThread; // #if !defined(NANOCLR_APPDOMAINS) - m_globalLock = NULL; // CLR_RT_HeapBlock* m_globalLock; - m_outOfMemoryException = NULL; // CLR_RT_HeapBlock* m_outOfMemoryException; -#endif // + m_globalLock = NULL; // CLR_RT_HeapBlock* m_globalLock; +#endif // m_currentUICulture = NULL; // CLR_RT_HeapBlock* m_currentUICulture; @@ -438,7 +437,6 @@ void CLR_RT_ExecutionEngine::Relocate() #if !defined(NANOCLR_APPDOMAINS) CLR_RT_GarbageCollector::Heap_Relocate((void **)&m_globalLock); - // CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_outOfMemoryException ); #endif CLR_RT_GarbageCollector::Heap_Relocate((void **)&m_currentUICulture); diff --git a/src/CLR/Core/GarbageCollector.cpp b/src/CLR/Core/GarbageCollector.cpp index 91693ca41e..64d4737f3c 100644 --- a/src/CLR/Core/GarbageCollector.cpp +++ b/src/CLR/Core/GarbageCollector.cpp @@ -662,7 +662,6 @@ void CLR_RT_GarbageCollector::AppDomain_Mark() CheckSingleBlock_Force(appDomain->m_globalLock); CheckSingleBlock_Force(appDomain->m_strName); - CheckSingleBlock_Force(appDomain->m_outOfMemoryException); } NANOCLR_FOREACH_NODE_END(); } diff --git a/src/CLR/Core/TypeSystem.cpp b/src/CLR/Core/TypeSystem.cpp index 47da8aea56..c7365ab2d9 100644 --- a/src/CLR/Core/TypeSystem.cpp +++ b/src/CLR/Core/TypeSystem.cpp @@ -2215,7 +2215,6 @@ void CLR_RT_AppDomain::AppDomain_Initialize() m_id = g_CLR_RT_ExecutionEngine.m_appDomainIdNext++; m_globalLock = NULL; m_strName = NULL; - m_outOfMemoryException = NULL; m_appDomainAssemblyLastAccess = NULL; } @@ -2268,19 +2267,14 @@ HRESULT CLR_RT_AppDomain::LoadAssembly(CLR_RT_Assembly *assm) NANOCLR_CHECK_HRESULT(CLR_RT_AppDomainAssembly::CreateInstance(this, assm, appDomainAssembly)); - if (m_outOfMemoryException == NULL) - { - // Allocate an out of memory exception. We should never get into a case where an out of memory exception - // cannot be thrown. - CLR_RT_HeapBlock exception; + // Preemptively allocate an out of memory exception. + // We can never get into a case where an out of memory exception cannot be thrown. - _ASSERTE(!strcmp(assm->m_szName, "mscorlib")); // always the first assembly to be loaded + _ASSERTE(!strcmp(assm->m_szName, "mscorlib")); // always the first assembly to be loaded - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.NewObjectFromIndex(exception, g_CLR_RT_WellKnownTypes.m_OutOfMemoryException)); - - m_outOfMemoryException = exception.Dereference(); - } + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( + m_outOfMemoryException, + g_CLR_RT_WellKnownTypes.m_OutOfMemoryException)); NANOCLR_CLEANUP(); @@ -2374,7 +2368,6 @@ void CLR_RT_AppDomain::Relocate() NATIVE_PROFILE_CLR_CORE(); CLR_RT_GarbageCollector::Heap_Relocate((void **)&m_globalLock); CLR_RT_GarbageCollector::Heap_Relocate((void **)&m_strName); - CLR_RT_GarbageCollector::Heap_Relocate((void **)&m_outOfMemoryException); } HRESULT CLR_RT_AppDomain::VerifyTypeIsLoaded(const CLR_RT_TypeDef_Index &idx) @@ -4091,17 +4084,12 @@ HRESULT CLR_RT_TypeSystem::PrepareForExecution() #endif // #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) #if !defined(NANOCLR_APPDOMAINS) - if (g_CLR_RT_ExecutionEngine.m_outOfMemoryException == NULL) - { - CLR_RT_HeapBlock exception; - memset(&exception, 0, sizeof(struct CLR_RT_HeapBlock)); - - NANOCLR_CHECK_HRESULT( - g_CLR_RT_ExecutionEngine.NewObjectFromIndex(exception, g_CLR_RT_WellKnownTypes.m_OutOfMemoryException)); - - g_CLR_RT_ExecutionEngine.m_outOfMemoryException = exception.Dereference(); - } + // Preemptively create an out of memory exception. + // We can never get into a case where an out of memory exception cannot be thrown. + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( + g_CLR_RT_ExecutionEngine.m_outOfMemoryException, + g_CLR_RT_WellKnownTypes.m_OutOfMemoryException)); #endif // Load Runtime.Events to setup EventSink for other assemblies using it diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index 4d0d026d0e..b8eaa9f628 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -17,8 +17,7 @@ HRESULT CLR_PRF_Profiler::CreateInstance() g_CLR_PRF_Profiler.m_packetSeqId = 0; g_CLR_PRF_Profiler.m_stream = NULL; g_CLR_PRF_Profiler.m_lastTimestamp = - (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) >> - CLR_PRF_CMDS::Bits::TimestampShift); + (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) >> CLR_PRF_CMDS::Bits::TimestampShift); g_CLR_PRF_Profiler.m_currentAssembly = 0; g_CLR_PRF_Profiler.m_currentThreadPID = 0; NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance(g_CLR_PRF_Profiler.m_stream, NULL, 0)); @@ -439,7 +438,6 @@ void CLR_PRF_Profiler::DumpObject(CLR_RT_HeapBlock *ptr) DumpListOfReferences(appDomain->m_appDomainAssemblies); DumpSingleReference(appDomain->m_globalLock); DumpSingleReference(appDomain->m_strName); - DumpSingleReference(appDomain->m_outOfMemoryException); break; } @@ -544,8 +542,7 @@ void CLR_PRF_Profiler::Timestamp() NATIVE_PROFILE_CLR_DIAGNOSTICS(); // Send Profiling Timestamp CLR_UINT32 time = - (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) >> - CLR_PRF_CMDS::Bits::TimestampShift); + (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) >> CLR_PRF_CMDS::Bits::TimestampShift); if (time > m_lastTimestamp) { m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Timestamp, CLR_PRF_CMDS::Bits::CommandHeader); diff --git a/src/CLR/Include/nanoCLR_Runtime.h b/src/CLR/Include/nanoCLR_Runtime.h index 35cd3e22e8..7aaa81ef8c 100644 --- a/src/CLR/Include/nanoCLR_Runtime.h +++ b/src/CLR/Include/nanoCLR_Runtime.h @@ -1437,7 +1437,7 @@ struct CLR_RT_AppDomain : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP CLR_RT_DblLinkedList m_appDomainAssemblies; CLR_RT_HeapBlock *m_globalLock; // OBJECT HEAP - DO RELOCATION - CLR_RT_HeapBlock_String *m_strName; // OBJECT HEAP - DO RELOCATION - - CLR_RT_HeapBlock *m_outOfMemoryException; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock m_outOfMemoryException; // NO RELOCATION - CLR_RT_AppDomainAssembly *m_appDomainAssemblyLastAccess; // EVENT HEAP - NO RELOCATION - bool m_fCanBeUnloaded; @@ -3651,8 +3651,8 @@ struct CLR_RT_ExecutionEngine CLR_RT_Thread *m_cctorThread; // EVENT HEAP - NO RELOCATION - #if !defined(NANOCLR_APPDOMAINS) - CLR_RT_HeapBlock *m_globalLock; // OBJECT HEAP - DO RELOCATION - - CLR_RT_HeapBlock *m_outOfMemoryException; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock *m_globalLock; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock m_outOfMemoryException; // NO RELOCATION - #endif CLR_RT_HeapBlock *m_currentUICulture; // OBJECT HEAP - DO RELOCATION - From bba315cc01f59888a01aba68c1cfdc9c57a5920c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 20 Jun 2024 13:26:08 +0100 Subject: [PATCH 547/572] Work CI-CD (#2971) ***NO_CI*** --- azure-pipelines-templates/download-install-llvm.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/azure-pipelines-templates/download-install-llvm.yml b/azure-pipelines-templates/download-install-llvm.yml index a8ae374f60..816739f29b 100644 --- a/azure-pipelines-templates/download-install-llvm.yml +++ b/azure-pipelines-templates/download-install-llvm.yml @@ -6,7 +6,7 @@ steps: condition: ne(variables['System.PullRequest.PullRequestId'], '') displayName: Cache LLVM inputs: - key: 'llvm_15_0_6_0 | llvmUpdateKey' + key: 'llvm_18_1_7_0 | llvmUpdateKey' restoreKeys: llvmUpdateKey path: $(Agent.TempDirectory)\llvm cacheHitVar: LLVM_CACHE_RESTORED @@ -21,8 +21,8 @@ steps: inputs: targetType: 'inline' script: | - $url = "https://github.com/llvm/llvm-project/releases/download/llvmorg-15.0.6/LLVM-15.0.6-win64.exe" - $output = "$(Agent.TempDirectory)\LLVM-15.0.6-win64.exe" + $url = "https://github.com/llvm/llvm-project/releases/download/llvmorg-18.1.7/LLVM-18.1.7-win64.exe" + $output = "$(Agent.TempDirectory)\LLVM-18.1.7-win64.exe" (New-Object Net.WebClient).DownloadFile($url, $output) errorActionPreference: 'stop' failOnStderr: 'true' @@ -35,7 +35,7 @@ steps: ne(variables.LLVM_CACHE_RESTORED, 'true') ) inputs: - archiveFilePatterns: '$(Agent.TempDirectory)\LLVM-15.0.6-win64.exe' + archiveFilePatterns: '$(Agent.TempDirectory)\LLVM-18.1.7-win64.exe' destinationFolder: '$(Agent.TempDirectory)\llvm' - script: echo "##vso[task.prependpath]$(Agent.TempDirectory)\llvm\bin" From f69a581ee64ba6c87d16a6656126584c6800c636 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 20 Jun 2024 13:27:37 +0100 Subject: [PATCH 548/572] Code style formatting ***NO_CI*** --- .../CorLib/corlib_native_System_Exception.cpp | 5 +- src/CLR/Core/TypeSystem.cpp | 51 ++++++++++--------- src/CLR/Diagnostics/Profiler.cpp | 6 ++- 3 files changed, 32 insertions(+), 30 deletions(-) diff --git a/src/CLR/CorLib/corlib_native_System_Exception.cpp b/src/CLR/CorLib/corlib_native_System_Exception.cpp index 39a9162c44..a1118df4f1 100644 --- a/src/CLR/CorLib/corlib_native_System_Exception.cpp +++ b/src/CLR/CorLib/corlib_native_System_Exception.cpp @@ -12,10 +12,7 @@ struct ExceptionLookup }; static const ExceptionLookup c_ExceptionLookup[] = { -#define EL(hr, fld) \ - { \ - hr, &g_CLR_RT_WellKnownTypes.fld \ - } +#define EL(hr, fld) {hr, &g_CLR_RT_WellKnownTypes.fld} EL(CLR_E_APPDOMAIN_EXITED, m_AppDomainUnloadedException), EL(CLR_E_INVALID_PARAMETER, m_ArgumentException), EL(CLR_E_ARGUMENT_NULL, m_ArgumentNullException), diff --git a/src/CLR/Core/TypeSystem.cpp b/src/CLR/Core/TypeSystem.cpp index c7365ab2d9..610830f602 100644 --- a/src/CLR/Core/TypeSystem.cpp +++ b/src/CLR/Core/TypeSystem.cpp @@ -1535,27 +1535,36 @@ void CLR_RT_Assembly::Assembly_Initialize(CLR_RT_Assembly::Offsets &offsets) //--// - {ITERATE_THROUGH_RECORDS(this, i, TypeDef, TYPEDEF){dst->m_flags = 0; - dst->m_totalFields = 0; - dst->m_hash = 0; -} -} + { + ITERATE_THROUGH_RECORDS(this, i, TypeDef, TYPEDEF) + { + dst->m_flags = 0; + dst->m_totalFields = 0; + dst->m_hash = 0; + } + } -{ITERATE_THROUGH_RECORDS(this, i, FieldDef, FIELDDEF){dst->m_offset = CLR_EmptyIndex; -} -} + { + ITERATE_THROUGH_RECORDS(this, i, FieldDef, FIELDDEF) + { + dst->m_offset = CLR_EmptyIndex; + } + } -{ITERATE_THROUGH_RECORDS(this, i, MethodDef, METHODDEF){dst->m_data = CLR_EmptyIndex; -} -} + { + ITERATE_THROUGH_RECORDS(this, i, MethodDef, METHODDEF) + { + dst->m_data = CLR_EmptyIndex; + } + } #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) -{ - m_pDebuggingInfo_MethodDef = (CLR_RT_MethodDef_DebuggingInfo *)buffer; - buffer += offsets.iDebuggingInfoMethods; + { + m_pDebuggingInfo_MethodDef = (CLR_RT_MethodDef_DebuggingInfo *)buffer; + buffer += offsets.iDebuggingInfoMethods; - memset(m_pDebuggingInfo_MethodDef, 0, offsets.iDebuggingInfoMethods); -} + memset(m_pDebuggingInfo_MethodDef, 0, offsets.iDebuggingInfoMethods); + } #endif // #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) } @@ -2758,10 +2767,7 @@ struct TypeIndexLookup }; static const TypeIndexLookup c_TypeIndexLookup[] = { -#define TIL(ns, nm, fld) \ - { \ - ns, nm, &g_CLR_RT_WellKnownTypes.fld \ - } +#define TIL(ns, nm, fld) {ns, nm, &g_CLR_RT_WellKnownTypes.fld} TIL("System", "Boolean", m_Boolean), TIL("System", "Char", m_Char), TIL("System", "SByte", m_Int8), @@ -2857,10 +2863,7 @@ struct MethodIndexLookup }; static const MethodIndexLookup c_MethodIndexLookup[] = { -#define MIL(nm, type, method) \ - { \ - nm, &g_CLR_RT_WellKnownTypes.type, &g_CLR_RT_WellKnownMethods.method \ - } +#define MIL(nm, type, method) {nm, &g_CLR_RT_WellKnownTypes.type, &g_CLR_RT_WellKnownMethods.method} MIL("GetObjectFromId", m_ResourceManager, m_ResourceManager_GetObjectFromId), MIL("GetObjectChunkFromId", m_ResourceManager, m_ResourceManager_GetObjectChunkFromId), diff --git a/src/CLR/Diagnostics/Profiler.cpp b/src/CLR/Diagnostics/Profiler.cpp index b8eaa9f628..192899e26e 100644 --- a/src/CLR/Diagnostics/Profiler.cpp +++ b/src/CLR/Diagnostics/Profiler.cpp @@ -17,7 +17,8 @@ HRESULT CLR_PRF_Profiler::CreateInstance() g_CLR_PRF_Profiler.m_packetSeqId = 0; g_CLR_PRF_Profiler.m_stream = NULL; g_CLR_PRF_Profiler.m_lastTimestamp = - (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) >> CLR_PRF_CMDS::Bits::TimestampShift); + (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) >> + CLR_PRF_CMDS::Bits::TimestampShift); g_CLR_PRF_Profiler.m_currentAssembly = 0; g_CLR_PRF_Profiler.m_currentThreadPID = 0; NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance(g_CLR_PRF_Profiler.m_stream, NULL, 0)); @@ -542,7 +543,8 @@ void CLR_PRF_Profiler::Timestamp() NATIVE_PROFILE_CLR_DIAGNOSTICS(); // Send Profiling Timestamp CLR_UINT32 time = - (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) >> CLR_PRF_CMDS::Bits::TimestampShift); + (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) >> + CLR_PRF_CMDS::Bits::TimestampShift); if (time > m_lastTimestamp) { m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Timestamp, CLR_PRF_CMDS::Bits::CommandHeader); From 1a429ad47f920ab9ea0341fe31ad7f3eaa91e3b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 20 Jun 2024 14:51:45 +0100 Subject: [PATCH 549/572] Work CI-CD (#2972) ***NO_CI*** --- azure-pipelines-nightly.yml | 1300 ++++---- .../build-azurertos-targets.yml | 21 +- .../build-chibios-stm32-targets.yml | 21 +- .../build-espressif-esp32-targets.yml | 15 +- .../build-freertos-nxp-targets.yml | 9 +- .../build-preparations.yml | 29 +- .../build-ti-simplelink-targets.yml | 9 +- .../check-code-style.yml | 11 +- azure-pipelines-templates/download-hexdfu.yml | 20 +- .../download-install-arm-gcc-toolchain.yml | 12 +- ...ownload-install-esp32-build-components.yml | 19 +- .../download-install-llvm.yml | 12 +- .../download-install-ninja.yml | 10 +- .../download-srecord.yml | 12 +- .../nb-gitversioning.yml | 16 +- .../pack-publish-managed-helpers.yml | 11 +- .../pack-publish-ti-sl-managed-helpers.yml | 9 +- .../publish-cloudsmith.yml | 108 +- azure-pipelines-templates/publish-nanoclr.yml | 65 +- .../setup-cmake-user-presets.yml | 9 +- azure-pipelines.yml | 2656 ++++++++--------- 21 files changed, 2180 insertions(+), 2194 deletions(-) diff --git a/azure-pipelines-nightly.yml b/azure-pipelines-nightly.yml index cc52f2ba37..cb14fd50bb 100644 --- a/azure-pipelines-nightly.yml +++ b/azure-pipelines-nightly.yml @@ -1,3 +1,6 @@ +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. + trigger: none pr: @@ -15,694 +18,691 @@ resources: name: espressif/esp-idf endpoint: nanoframework ref: refs/tags/v5.1.3 - + # scheduled build # the schedule is defined at the AZDO web interface because of inconsistencies with time zones jobs: + ############################## + - job: Check_Build_Options + pool: + vmImage: "windows-latest" -############################## -- job: Check_Build_Options - pool: - vmImage: 'windows-latest' - - variables: - DOTNET_NOLOGO: true - - steps: - - checkout: self - fetchDepth: 1 + variables: + DOTNET_NOLOGO: true - - template: azure-pipelines-templates/get-commit-details.yml@templates + steps: + - checkout: self + fetchDepth: 1 - # check build options - - powershell: | + - template: azure-pipelines-templates/get-commit-details.yml@templates - if($env:Build_Reason -eq "Schedule") - { - # scheduled daily build - $now = [System.DateTime]::UtcNow.Date - "Today is $now" | Write-Host + # check build options + - powershell: | - # get commit date - $commitDate = git show -s --format=%cd --date=short - $commitDate = [DateTime]$commitDate - - "Last commit dated $commitDate" | Write-Host - - $yesterdayDate = [System.DateTime]::UtcNow.AddDays(-1).Date - "Comparing with $yesterdayDate" | Write-Host - - # shceduled build is at start of day, so check if commit date was from yesterday - if($commitDate -ge $yesterdayDate) + if($env:Build_Reason -eq "Schedule") { - # last commit was yesterday, build images - echo "##vso[task.setvariable variable=CHECK_CHANGES;isOutput=true]true" - "**Commits from today. Go and check what changed.**" | Write-Host + # scheduled daily build + $now = [System.DateTime]::UtcNow.Date + "Today is $now" | Write-Host + + # get commit date + $commitDate = git show -s --format=%cd --date=short + $commitDate = [DateTime]$commitDate + + "Last commit dated $commitDate" | Write-Host + + $yesterdayDate = [System.DateTime]::UtcNow.AddDays(-1).Date + "Comparing with $yesterdayDate" | Write-Host + + # shceduled build is at start of day, so check if commit date was from yesterday + if($commitDate -ge $yesterdayDate) + { + # last commit was yesterday, build images + echo "##vso[task.setvariable variable=CHECK_CHANGES;isOutput=true]true" + "**Commits from today. Go and check what changed.**" | Write-Host + } + else + { + # last commit is not from yesterday, skip build + "***************************************************" | Write-Host + "* Last commit is older than today, skipping build *" | Write-Host + "***************************************************" | Write-Host + echo "##vso[task.setvariable variable=CHECK_CHANGES;isOutput=true]false" + } } else { - # last commit is not from yesterday, skip build - "***************************************************" | Write-Host - "* Last commit is older than today, skipping build *" | Write-Host - "***************************************************" | Write-Host - echo "##vso[task.setvariable variable=CHECK_CHANGES;isOutput=true]false" + # build for other reasons: build depending on target tag + echo "##vso[task.setvariable variable=CHECK_CHANGES;isOutput=true]true" + + if ($env:System_PullRequest_PullRequestId -ne $null) + { + "**This is a PR build**" | Write-Host + } + else + { + "**build for other reasons**" | Write-Host + } } - } - else - { - # build for other reasons: build depending on target tag - echo "##vso[task.setvariable variable=CHECK_CHANGES;isOutput=true]true" - if ($env:System_PullRequest_PullRequestId -ne $null) - { - "**This is a PR build**" | Write-Host - } - else - { - "**build for other reasons**" | Write-Host - } - } - - name: BuildOptions - displayName: Get build options - - # check what changed - - powershell: | - git config --global user.email "nfbot" - git config --global user.name "nanoframework@outlook.com" - - $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)")))" - - $buildingPr = $env:System_PullRequest_PullRequestId -ne $null - - # set default values - echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]false" - - if($env:StartReleaseCandidate -like "true") - { - # this is a release prep so NO build - Write-host "##[command] Start Release candidate build, don't build" - } - else - { - # check if this build was triggered by the pipeline itself - if($env:Build_Reason -eq "Manual") + name: BuildOptions + displayName: Get build options + + # check what changed + - powershell: | + git config --global user.email "nfbot" + git config --global user.name "nanoframework@outlook.com" + + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)")))" + + $buildingPr = $env:System_PullRequest_PullRequestId -ne $null + + # set default values + echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]false" + + if($env:StartReleaseCandidate -like "true") { - # this is a manual build, no need to check anything - Write-host "##[command] Manual build" + # this is a release prep so NO build + Write-host "##[command] Start Release candidate build, don't build" } else { - if($buildingPr) - { - # get files changed in PR, if this is a PR - $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/pulls/$env:System_PullRequest_PullRequestNumber/files" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET - - # filter removed files - $files = $commit.where{$_.status -ne 'removed'} - - # get file names only - $files = $files | % {$_.filename} - } - else - { - # scheduled build, grab repo history for the last day - $commitHistory = git log --name-status --since=1.day --format= - - # filter removed files - $files = $commitHistory.where{$_[0] -ne 'D'} - - # get file names only - $files = $files | % {$_.SubString(2)} - } - - Write-host "##[group] Files changed:" - $files | % { Write-host $_ } - Write-host "##[endgroup]" - - if( - (($files.where{$_.Contains('/')}).Count -eq 0) -Or - (($files.where{$_.StartsWith('azure-pipelines-templates')}).Count -gt 0) -Or - (($files.where{$_.StartsWith('CMake')}).Count -gt 0) -Or - (($files.where{$_.StartsWith('src')}).Count -gt 0) - ) - { - # files at: - # - repo root - # - azure-pipelines-templates - # - CMake - # - src - + # check if this build was triggered by the pipeline itself + if($env:Build_Reason -eq "Manual") + { + # this is a manual build, no need to check anything + Write-host "##[command] Manual build" + } + else + { if($buildingPr) { - # ChibiOS targets are the only ones needing to be build on a global change - echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" - Write-host "##[command] Building ChibiOS targets" + # get files changed in PR, if this is a PR + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/pulls/$env:System_PullRequest_PullRequestNumber/files" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + + # filter removed files + $files = $commit.where{$_.status -ne 'removed'} + + # get file names only + $files = $files | % {$_.filename} } else { - echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]true" - Write-host "##[command] Building ALL targets" - } - } + # scheduled build, grab repo history for the last day + $commitHistory = git log --name-status --since=1.day --format= - if($buildingPr) - { - if( - ($files.where{$_.Contains('targets/ChibiOS/_common')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_FatFS')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_include')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_Lwip')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_nanoBooter')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_nanoCLR')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_FatFS')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_nf-overlay')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/_littlefs')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/ORGPAL_PALTHREE')}).Count -gt 0 -Or - ($files.where{$_.Contains('targets/ChibiOS/ST_NUCLEO64_F091RC')}).Count -gt 0 + # filter removed files + $files = $commitHistory.where{$_[0] -ne 'D'} + + # get file names only + $files = $files | % {$_.SubString(2)} + } + + Write-host "##[group] Files changed:" + $files | % { Write-host $_ } + Write-host "##[endgroup]" + + if( + (($files.where{$_.Contains('/')}).Count -eq 0) -Or + (($files.where{$_.StartsWith('azure-pipelines-templates')}).Count -gt 0) -Or + (($files.where{$_.StartsWith('CMake')}).Count -gt 0) -Or + (($files.where{$_.StartsWith('src')}).Count -gt 0) ) { - # files at ChibiOS global folders or targets being built with this pipeline - echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + # files at: + # - repo root + # - azure-pipelines-templates + # - CMake + # - src + + if($buildingPr) + { + # ChibiOS targets are the only ones needing to be build on a global change + echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + Write-host "##[command] Building ChibiOS targets" + } + else + { + echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]true" + Write-host "##[command] Building ALL targets" + } + } - Write-host "##[command] Building ChibiOS targets" + if($buildingPr) + { + if( + ($files.where{$_.Contains('targets/ChibiOS/_common')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_FatFS')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_include')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_Lwip')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_nanoBooter')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_nanoCLR')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_FatFS')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_nf-overlay')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/_littlefs')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/ORGPAL_PALTHREE')}).Count -gt 0 -Or + ($files.where{$_.Contains('targets/ChibiOS/ST_NUCLEO64_F091RC')}).Count -gt 0 + ) + { + # files at ChibiOS global folders or targets being built with this pipeline + echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + + Write-host "##[command] Building ChibiOS targets" + } + } + else + { + if( ($files.where{$_.Contains('targets/ChibiOS')}).Count -gt 0) + { + # files at ChibiOS folder + echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + + Write-host "##[command] Building ChibiOS targets" + } + } + + if( + !$buildingPr -And + ($files.where{$_.Contains('targets/ESP32')}).Count -gt 0) + { + # files at ESP32 folder + echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]true" + + Write-host "##[command] Building ESP32 targets" + } + + if( + !$buildingPr -And + ($files.where{$_.Contains('targets/TI_SimpleLink')}).Count -gt 0) + { + # files at TI_SimpleLink folder + echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]true" + + Write-host "##[command] Building TI SimpleLink targets" } - } - else - { - if( ($files.where{$_.Contains('targets/ChibiOS')}).Count -gt 0) + + if( + !$buildingPr -And + ($files.where{$_.Contains('targets/AzureRTOS')}).Count -gt 0) { - # files at ChibiOS folder - echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + # files at AzureRTOS folder + echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]true" - Write-host "##[command] Building ChibiOS targets" + Write-host "##[command] Building Azure RTOS targets" } - } - - if( - !$buildingPr -And - ($files.where{$_.Contains('targets/ESP32')}).Count -gt 0) - { - # files at ESP32 folder - echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]true" - - Write-host "##[command] Building ESP32 targets" - } - - if( - !$buildingPr -And - ($files.where{$_.Contains('targets/TI_SimpleLink')}).Count -gt 0) - { - # files at TI_SimpleLink folder - echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]true" - - Write-host "##[command] Building TI SimpleLink targets" - } - - if( - !$buildingPr -And - ($files.where{$_.Contains('targets/AzureRTOS')}).Count -gt 0) - { - # files at AzureRTOS folder - echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]true" - - Write-host "##[command] Building Azure RTOS targets" - } + } } - } - - name: TargetsToBuild - displayName: Get targets to build - condition: eq(variables['BuildOptions.CHECK_CHANGES'], 'True') - -################ -# STM32 -- job: Build_STM32_targets - condition: >- - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_CHIBIOS'], true), - contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_CHIBIOS__'], 'true') + + name: TargetsToBuild + displayName: Get targets to build + condition: eq(variables['BuildOptions.CHECK_CHANGES'], 'True') + + ################ + # STM32 + - job: Build_STM32_targets + condition: >- + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_CHIBIOS'], true), + contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_CHIBIOS__'], 'true') + ) ) ) - ) - dependsOn: - - Check_Build_Options - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - ORGPAL_PALTHREE: - TargetBoard: ORGPAL_PALTHREE - TargetSeries: 'stm32f7xx' - BuildOptions: - NeedsDFU: true - NeedsSRECORD: false - CMakePreset: ORGPAL_PALTHREE - - ORGPAL_PALX: - TargetBoard: ORGPAL_PALX - TargetSeries: 'stm32f7xx' - BuildOptions: - NeedsDFU: true - NeedsSRECORD: false - CMakePreset: ORGPAL_PALX - - ST_NUCLEO64_F091RC: - TargetBoard: ST_NUCLEO64_F091RC - TargetSeries: 'stm32f0xx' - BuildOptions: - NeedsDFU: false - NeedsSRECORD: true - CMakePreset: ST_NUCLEO64_F091RC - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('STM32_1_9_1_versioncounter', 0)] - HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] - TargetPlatform: 'stm32' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/download-srecord.yml - - template: azure-pipelines-templates/download-hexdfu.yml - - template: azure-pipelines-templates/build-chibios-stm32-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-managed-helpers.yml - -################# -# ESP32 targets -- job: Build_ESP32_targets - condition: >- - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ESP32'], true), - contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_ESP32__'], 'true') + dependsOn: + - Check_Build_Options + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + ORGPAL_PALTHREE: + TargetBoard: ORGPAL_PALTHREE + TargetSeries: "stm32f7xx" + BuildOptions: + NeedsDFU: true + NeedsSRECORD: false + CMakePreset: ORGPAL_PALTHREE + + ORGPAL_PALX: + TargetBoard: ORGPAL_PALX + TargetSeries: "stm32f7xx" + BuildOptions: + NeedsDFU: true + NeedsSRECORD: false + CMakePreset: ORGPAL_PALX + + ST_NUCLEO64_F091RC: + TargetBoard: ST_NUCLEO64_F091RC + TargetSeries: "stm32f0xx" + BuildOptions: + NeedsDFU: false + NeedsSRECORD: true + CMakePreset: ST_NUCLEO64_F091RC + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('STM32_1_9_1_versioncounter', 0)] + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + TargetPlatform: "stm32" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/download-srecord.yml + - template: azure-pipelines-templates/download-hexdfu.yml + - template: azure-pipelines-templates/build-chibios-stm32-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + + ################# + # ESP32 targets + - job: Build_ESP32_targets + condition: >- + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ESP32'], true), + contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_ESP32__'], 'true') + ) ) ) - ) - - dependsOn: - - Check_Build_Options - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - ESP32_REV0: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - SDK_config: sdkconfig.default_nopsram.esp32 - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_REV0 - CMakePreset: ESP32_REV0 - - ESP32_PSRAM_REV3: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_PSRAM_REV3 - CMakePreset: ESP32_PSRAM_REV3 - - ESP32_PSRAM_XTAL26_REV0: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_PSRAM_XTAL26_REV0 - CMakePreset: ESP32_PSRAM_XTAL26_REV0 - - ESP32_REV3: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_REV3 - CMakePreset: ESP32_REV3 - - ESP32_PICO: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_PICO - PackageName: ESP32_PICO - CMakePreset: ESP32_PICO - - KALUGA_1: - TargetBoard: ESP32_S2 - TargetSeries: 'esp32_s2' - BuildOptions: - IDF_Target: esp32s2 - TargetName: KALUGA_1 - PackageName: KALUGA_1 - CMakePreset: KALUGA_1 - - ESP32_BLE_REV3: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_BLE_REV3 - CMakePreset: ESP32_BLE_REV3 - - ESP32_OLIMEX: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_OLIMEX - PackageName: ESP32_OLIMEX - CMakePreset: ESP32_OLIMEX - - ESP32_OLIMEX_WROVER: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_OLIMEX_WROVER - PackageName: ESP32_OLIMEX_WROVER - CMakePreset: ESP32_OLIMEX_WROVER - - M5StickC: - TargetBoard: ESP32 - TargetPlatform: 'esp32' - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: M5StickC - PackageName: M5StickC - CMakePreset: M5StickC - - M5StickCPlus: - TargetBoard: ESP32 - TargetPlatform: 'esp32' - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: M5StickCPlus - PackageName: M5StickCPlus - CMakePreset: M5StickCPlus - - M5Core: - TargetBoard: ESP32 - TargetPlatform: 'esp32' - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: M5Core - PackageName: M5Core - CMakePreset: M5Core - - M5Core2: - TargetBoard: ESP32 - TargetPlatform: 'esp32' - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: M5Core2 - PackageName: M5Core2 - CMakePreset: M5Core2 - - AtomS3: - TargetBoard: ESP32_S3 - TargetPlatform: 'esp32' - TargetSeries: 'esp32s3' - BuildOptions: - IDF_Target: esp32s3 - TargetName: AtomS3 - PackageName: AtomS3 - CMakePreset: AtomS3 - - ESP32_C3_REV3: - TargetBoard: ESP32_C3 - TargetSeries: 'esp32c3' - BuildOptions: - IDF_Target: esp32c3 - TargetName: ESP32_C3_REV3 - PackageName: ESP32_C3_REV3 - CMakePreset: ESP32_C3_REV3 - - ESP32_GenericDisplay_REV0: - TargetBoard: ESP32 - TargetPlatform: 'esp32' - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_GenericDisplay_REV0 - PackageName: ESP32_GenericDisplay_REV0 - CMakePreset: ESP32_GenericDisplay_REV0 - - ESP32_PSRAM_BLE_GenericGraphic_REV3: - TargetBoard: ESP32 - TargetPlatform: 'esp32' - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_PSRAM_BLE_GenericGraphic_REV3 - PackageName: ESP32_PSRAM_BLE_GenericGraphic_REV3 - CMakePreset: ESP32_PSRAM_BLE_GenericGraphic_REV3 - - XIAO_ESP32C3: - TargetBoard: ESP32_C3 - TargetSeries: 'esp32c3' - BuildOptions: - IDF_Target: esp32c3 - TargetName: XIAO_ESP32C3 - PackageName: XIAO_ESP32C3 - CMakePreset: XIAO_ESP32C3 - - ESP32_S3_BLE: - TargetBoard: ESP32_S3 - TargetSeries: 'esp32s3' - BuildOptions: - IDF_Target: esp32s3 - TargetName: ESP32_S3_BLE - PackageName: ESP32_S3_BLE - CMakePreset: ESP32_S3_BLE - - ESP32_WESP32: - TargetSeries: 'esp32' - TargetBoard: ESP32 - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_WESP32 - PackageName: ESP32_WESP32 - CMakePreset: ESP32_WESP32 - - ESP32_WT32_ETH01: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - TargetName: ESP32_WT32_ETH01 - IDF_Target: esp32 - PackageName: ESP32_WT32_ETH01 - CMakePreset: ESP32_WT32_ETH01 - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('ESP32_1_9_1_versioncounter', 0)] - IDF_PATH: 'D:/a/1/s/esp-idf' - PIP_CACHE_DIR: $(Pipeline.Workspace)/.pip - TargetPlatform: 'esp32' - - steps: - - checkout: self - - checkout: esp32_idf - fetchDepth: 1 - - - template: azure-pipelines-templates/build-preparations.yml - parameters: - repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' - - template: azure-pipelines-templates/nb-gitversioning.yml - parameters: - repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' - - template: azure-pipelines-templates/download-install-esp32-build-components.yml - - template: azure-pipelines-templates/download-install-ninja.yml - parameters: - repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' - - template: azure-pipelines-templates/build-espressif-esp32-targets.yml - - - task: CopyFiles@2 - condition: succeeded() - displayName: Copying bootloader - inputs: - sourceFolder: '$(Build.SourcesDirectory)\nf-interpreter\build\bootloader' - Contents: | - bootloader.bin - TargetFolder: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' - flattenFolders: true - ignoreMakeDirErrors: true - - - template: azure-pipelines-templates/copy-sdkconfig.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - parameters: - buildDirectory: '$(Build.SourcesDirectory)\nf-interpreter\build' - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/publish-sdkconfig.yml - -################# -# TI SimpleLink -- job: Build_TI_SimpleLink_targets - condition: >- - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_TI'], true), - contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_TI__'], 'true') + + dependsOn: + - Check_Build_Options + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + ESP32_REV0: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + SDK_config: sdkconfig.default_nopsram.esp32 + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_REV0 + CMakePreset: ESP32_REV0 + + ESP32_PSRAM_REV3: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_PSRAM_REV3 + CMakePreset: ESP32_PSRAM_REV3 + + ESP32_PSRAM_XTAL26_REV0: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_PSRAM_XTAL26_REV0 + CMakePreset: ESP32_PSRAM_XTAL26_REV0 + + ESP32_REV3: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_REV3 + CMakePreset: ESP32_REV3 + + ESP32_PICO: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_PICO + PackageName: ESP32_PICO + CMakePreset: ESP32_PICO + + KALUGA_1: + TargetBoard: ESP32_S2 + TargetSeries: "esp32_s2" + BuildOptions: + IDF_Target: esp32s2 + TargetName: KALUGA_1 + PackageName: KALUGA_1 + CMakePreset: KALUGA_1 + + ESP32_BLE_REV3: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_BLE_REV3 + CMakePreset: ESP32_BLE_REV3 + + ESP32_OLIMEX: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_OLIMEX + PackageName: ESP32_OLIMEX + CMakePreset: ESP32_OLIMEX + + ESP32_OLIMEX_WROVER: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_OLIMEX_WROVER + PackageName: ESP32_OLIMEX_WROVER + CMakePreset: ESP32_OLIMEX_WROVER + + M5StickC: + TargetBoard: ESP32 + TargetPlatform: "esp32" + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: M5StickC + PackageName: M5StickC + CMakePreset: M5StickC + + M5StickCPlus: + TargetBoard: ESP32 + TargetPlatform: "esp32" + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: M5StickCPlus + PackageName: M5StickCPlus + CMakePreset: M5StickCPlus + + M5Core: + TargetBoard: ESP32 + TargetPlatform: "esp32" + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: M5Core + PackageName: M5Core + CMakePreset: M5Core + + M5Core2: + TargetBoard: ESP32 + TargetPlatform: "esp32" + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: M5Core2 + PackageName: M5Core2 + CMakePreset: M5Core2 + + AtomS3: + TargetBoard: ESP32_S3 + TargetPlatform: "esp32" + TargetSeries: "esp32s3" + BuildOptions: + IDF_Target: esp32s3 + TargetName: AtomS3 + PackageName: AtomS3 + CMakePreset: AtomS3 + + ESP32_C3_REV3: + TargetBoard: ESP32_C3 + TargetSeries: "esp32c3" + BuildOptions: + IDF_Target: esp32c3 + TargetName: ESP32_C3_REV3 + PackageName: ESP32_C3_REV3 + CMakePreset: ESP32_C3_REV3 + + ESP32_GenericDisplay_REV0: + TargetBoard: ESP32 + TargetPlatform: "esp32" + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_GenericDisplay_REV0 + PackageName: ESP32_GenericDisplay_REV0 + CMakePreset: ESP32_GenericDisplay_REV0 + + ESP32_PSRAM_BLE_GenericGraphic_REV3: + TargetBoard: ESP32 + TargetPlatform: "esp32" + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_PSRAM_BLE_GenericGraphic_REV3 + PackageName: ESP32_PSRAM_BLE_GenericGraphic_REV3 + CMakePreset: ESP32_PSRAM_BLE_GenericGraphic_REV3 + + XIAO_ESP32C3: + TargetBoard: ESP32_C3 + TargetSeries: "esp32c3" + BuildOptions: + IDF_Target: esp32c3 + TargetName: XIAO_ESP32C3 + PackageName: XIAO_ESP32C3 + CMakePreset: XIAO_ESP32C3 + + ESP32_S3_BLE: + TargetBoard: ESP32_S3 + TargetSeries: "esp32s3" + BuildOptions: + IDF_Target: esp32s3 + TargetName: ESP32_S3_BLE + PackageName: ESP32_S3_BLE + CMakePreset: ESP32_S3_BLE + + ESP32_WESP32: + TargetSeries: "esp32" + TargetBoard: ESP32 + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_WESP32 + PackageName: ESP32_WESP32 + CMakePreset: ESP32_WESP32 + + ESP32_WT32_ETH01: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + TargetName: ESP32_WT32_ETH01 + IDF_Target: esp32 + PackageName: ESP32_WT32_ETH01 + CMakePreset: ESP32_WT32_ETH01 + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ESP32_1_9_1_versioncounter', 0)] + IDF_PATH: "D:/a/1/s/esp-idf" + PIP_CACHE_DIR: $(Pipeline.Workspace)/.pip + TargetPlatform: "esp32" + + steps: + - checkout: self + - checkout: esp32_idf + fetchDepth: 1 + + - template: azure-pipelines-templates/build-preparations.yml + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/nb-gitversioning.yml + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/download-install-esp32-build-components.yml + - template: azure-pipelines-templates/download-install-ninja.yml + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/build-espressif-esp32-targets.yml + + - task: CopyFiles@2 + condition: succeeded() + displayName: Copying bootloader + inputs: + sourceFolder: '$(Build.SourcesDirectory)\nf-interpreter\build\bootloader' + Contents: | + bootloader.bin + TargetFolder: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' + flattenFolders: true + ignoreMakeDirErrors: true + + - template: azure-pipelines-templates/copy-sdkconfig.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + parameters: + buildDirectory: '$(Build.SourcesDirectory)\nf-interpreter\build' + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/publish-sdkconfig.yml + + ################# + # TI SimpleLink + - job: Build_TI_SimpleLink_targets + condition: >- + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_TI'], true), + contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_TI__'], 'true') + ) ) ) - ) - - dependsOn: - - Check_Build_Options - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - TI_CC1352R1_LAUNCHXL_868: - TargetBoard: TI_CC1352R1_LAUNCHXL - PackageName: TI_CC1352R1_LAUNCHXL_868 - TargetSeries: 'CC13X2' - BuildOptions: >- - -DRADIO_FREQUENCY=868 - CMakePreset: TI_CC1352R1_LAUNCHXL - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('TI_1_9_1_versioncounter', 0)] - HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] - TargetPlatform: 'ti_simplelink' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/build-ti-simplelink-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml - -################# -# Azure RTOS -- job: Build_Azure_RTOS_targets - condition: >- - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_AZURERTOS'], true), - contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_AZURERTOS__'], 'true') + + dependsOn: + - Check_Build_Options + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + TI_CC1352R1_LAUNCHXL_868: + TargetBoard: TI_CC1352R1_LAUNCHXL + PackageName: TI_CC1352R1_LAUNCHXL_868 + TargetSeries: "CC13X2" + BuildOptions: >- + -DRADIO_FREQUENCY=868 + CMakePreset: TI_CC1352R1_LAUNCHXL + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('TI_1_9_1_versioncounter', 0)] + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + TargetPlatform: "ti_simplelink" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/build-ti-simplelink-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml + + ################# + # Azure RTOS + - job: Build_Azure_RTOS_targets + condition: >- + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_AZURERTOS'], true), + contains(dependencies.Check_Build_Options.outputs['GetCommitDetails.COMMIT_MESSAGE'], '***BUILD_ALL***'), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_AZURERTOS__'], 'true') + ) ) ) - ) - - dependsOn: - - Check_Build_Options - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - - SL_STK3701A_REVB: - TargetBoard: SL_STK3701A_REVB - TargetSeries: 'efm32gg11' - BuildOptions: - NeedsDFU: false - NeedsSRECORD: false - TargetName: SL_STK3701A_REVB - PackageName: SL_STK3701A_REVB - CMakePreset: SL_STK3701A_REVB - - variables: - # creates a counter and assigns it to the revision variable - REVISION: $[counter('AZURERTOS_1_9_1_versioncounter', 0)] - HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] - TargetPlatform: 'azure_rtos' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/download-hexdfu.yml - - template: azure-pipelines-templates/download-srecord.yml - - template: azure-pipelines-templates/build-azurertos-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-managed-helpers.yml - -################################# -# report build failure to Discord -- job: Report_Build_Failure - dependsOn: - - Build_STM32_targets - - Build_ESP32_targets - - Build_TI_SimpleLink_targets - - Build_Azure_RTOS_targets - condition: >- - or( - failed('Build_STM32_targets'), - failed('Build_ESP32_targets'), - failed('Build_TI_SimpleLink_targets'), - failed('Build_Azure_RTOS_targets') - ) - - pool: - vmImage: 'windows-latest' - - steps: - - - checkout: self - fetchDepth: 1 - - # step from template @ nf-tools repo - - template: azure-pipelines-templates/discord-webhook.yml@templates - parameters: - status: 'failure' - webhookUrl: '$(DiscordWebhook)' - message: '' + + dependsOn: + - Check_Build_Options + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + SL_STK3701A_REVB: + TargetBoard: SL_STK3701A_REVB + TargetSeries: "efm32gg11" + BuildOptions: + NeedsDFU: false + NeedsSRECORD: false + TargetName: SL_STK3701A_REVB + PackageName: SL_STK3701A_REVB + CMakePreset: SL_STK3701A_REVB + + variables: + # creates a counter and assigns it to the revision variable + REVISION: $[counter('AZURERTOS_1_9_1_versioncounter', 0)] + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + TargetPlatform: "azure_rtos" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/download-hexdfu.yml + - template: azure-pipelines-templates/download-srecord.yml + - template: azure-pipelines-templates/build-azurertos-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + + ################################# + # report build failure to Discord + - job: Report_Build_Failure + dependsOn: + - Build_STM32_targets + - Build_ESP32_targets + - Build_TI_SimpleLink_targets + - Build_Azure_RTOS_targets + condition: >- + or( + failed('Build_STM32_targets'), + failed('Build_ESP32_targets'), + failed('Build_TI_SimpleLink_targets'), + failed('Build_Azure_RTOS_targets') + ) + + pool: + vmImage: "windows-latest" + + steps: + - checkout: self + fetchDepth: 1 + + # step from template @ nf-tools repo + - template: azure-pipelines-templates/discord-webhook.yml@templates + parameters: + status: "failure" + webhookUrl: "$(DiscordWebhook)" + message: "" diff --git a/azure-pipelines-templates/build-azurertos-targets.yml b/azure-pipelines-templates/build-azurertos-targets.yml index 70a3d6b78c..fb4f3db41f 100644 --- a/azure-pipelines-templates/build-azurertos-targets.yml +++ b/azure-pipelines-templates/build-azurertos-targets.yml @@ -7,7 +7,6 @@ parameters: default: $(Build.SourcesDirectory) steps: - - template: setup-cmake-user-presets.yml parameters: repoDirectory: ${{ parameters.repoDirectory }} @@ -16,32 +15,32 @@ steps: displayName: Setup CMake (DFU, no SRecord) condition: and(eq(variables['NeedsDFU'], true), eq(variables['NeedsSRECORD'], 'false')) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Setup CMake build (SRecord, no DFU) condition: and(eq(variables['NeedsSRECORD'], true), eq(variables['NeedsDFU'], false)) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Setup CMake build (DFU and SRecord) condition: and(eq(variables['NeedsDFU'], true), eq(variables['NeedsSRECORD'], true)) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Setup CMake build (no DFU, no SRecord) condition: and(eq(variables['NeedsDFU'], false), eq(variables['NeedsSRECORD'], false)) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Build with CMake inputs: - cmakeArgs: '--build --preset $(CMakePreset) --target all --config MinSizeRel' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--build --preset $(CMakePreset) --target all --config MinSizeRel" + workingDirectory: ${{ parameters.repoDirectory }} diff --git a/azure-pipelines-templates/build-chibios-stm32-targets.yml b/azure-pipelines-templates/build-chibios-stm32-targets.yml index 70a3d6b78c..fb4f3db41f 100644 --- a/azure-pipelines-templates/build-chibios-stm32-targets.yml +++ b/azure-pipelines-templates/build-chibios-stm32-targets.yml @@ -7,7 +7,6 @@ parameters: default: $(Build.SourcesDirectory) steps: - - template: setup-cmake-user-presets.yml parameters: repoDirectory: ${{ parameters.repoDirectory }} @@ -16,32 +15,32 @@ steps: displayName: Setup CMake (DFU, no SRecord) condition: and(eq(variables['NeedsDFU'], true), eq(variables['NeedsSRECORD'], 'false')) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Setup CMake build (SRecord, no DFU) condition: and(eq(variables['NeedsSRECORD'], true), eq(variables['NeedsDFU'], false)) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Setup CMake build (DFU and SRecord) condition: and(eq(variables['NeedsDFU'], true), eq(variables['NeedsSRECORD'], true)) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Setup CMake build (no DFU, no SRecord) condition: and(eq(variables['NeedsDFU'], false), eq(variables['NeedsSRECORD'], false)) inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions) ' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions) " + workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Build with CMake inputs: - cmakeArgs: '--build --preset $(CMakePreset) --target all --config MinSizeRel' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--build --preset $(CMakePreset) --target all --config MinSizeRel" + workingDirectory: ${{ parameters.repoDirectory }} diff --git a/azure-pipelines-templates/build-espressif-esp32-targets.yml b/azure-pipelines-templates/build-espressif-esp32-targets.yml index 337ac34f82..7ae9c3be61 100644 --- a/azure-pipelines-templates/build-espressif-esp32-targets.yml +++ b/azure-pipelines-templates/build-espressif-esp32-targets.yml @@ -10,7 +10,6 @@ parameters: default: $(Build.SourcesDirectory)\nf-interpreter\targets\ESP32\_IDF\$(IDF_Target) steps: - - template: setup-cmake-user-presets.yml parameters: repoDirectory: ${{ parameters.repoDirectory }} @@ -19,15 +18,15 @@ steps: condition: succeeded() displayName: Setup build with CMake inputs: - cmakeArgs: '--preset $(CMakePreset) -DESP32_IDF_PATH=$(IDF_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions)' + cmakeArgs: "--preset $(CMakePreset) -DESP32_IDF_PATH=$(IDF_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions)" workingDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 displayName: Build with CMake condition: succeeded() inputs: - cmakeArgs: '--build --preset $(CMakePreset) --target all --config MinSizeRel' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--build --preset $(CMakePreset) --target all --config MinSizeRel" + workingDirectory: ${{ parameters.repoDirectory }} # because of permission issues (the python script isn't allowed to write on the output folder) # we need to perform these steps by calling directly the python scripts @@ -46,7 +45,7 @@ steps: ) displayName: Generate ESP32 Partition tables for 16MB flash inputs: - scriptSource: 'filePath' + scriptSource: "filePath" scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_16mb.csv ${{ parameters.repoDirectory }}\build\partitions_16mb.bin' @@ -61,7 +60,7 @@ steps: ) displayName: Generate ESP32 Partition tables for 8MB flash inputs: - scriptSource: 'filePath' + scriptSource: "filePath" scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_8mb.csv ${{ parameters.repoDirectory }}\build\partitions_8mb.bin' @@ -69,7 +68,7 @@ steps: condition: succeeded() displayName: Generate ESP32 Partition tables for 4MB flash inputs: - scriptSource: 'filePath' + scriptSource: "filePath" scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_4mb.csv ${{ parameters.repoDirectory }}\build\partitions_4mb.bin' @@ -84,7 +83,7 @@ steps: ) displayName: Generate ESP32 Partition tables for 2MB flash inputs: - scriptSource: 'filePath' + scriptSource: "filePath" scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_2mb.csv ${{ parameters.repoDirectory }}\build\partitions_2mb.bin' diff --git a/azure-pipelines-templates/build-freertos-nxp-targets.yml b/azure-pipelines-templates/build-freertos-nxp-targets.yml index d5234dc469..25c20196d7 100644 --- a/azure-pipelines-templates/build-freertos-nxp-targets.yml +++ b/azure-pipelines-templates/build-freertos-nxp-targets.yml @@ -7,19 +7,18 @@ parameters: default: $(Build.SourcesDirectory) steps: - - template: setup-cmake-user-presets.yml parameters: repoDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 inputs: - cmakeArgs: '--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions)' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--preset $(CMakePreset) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_NAME=$(TargetPublishName) -DTOOL_SRECORD_PREFIX=$(SRECORD_PATH)/srecord/ $(BuildOptions)" + workingDirectory: ${{ parameters.repoDirectory }} displayName: Setup build with CMake - task: CMake@1 inputs: - cmakeArgs: '--build --preset $(CMakePreset) --target all --config MinSizeRel' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--build --preset $(CMakePreset) --target all --config MinSizeRel" + workingDirectory: ${{ parameters.repoDirectory }} displayName: Build with CMake diff --git a/azure-pipelines-templates/build-preparations.yml b/azure-pipelines-templates/build-preparations.yml index 1c2b279571..b6090b08f9 100644 --- a/azure-pipelines-templates/build-preparations.yml +++ b/azure-pipelines-templates/build-preparations.yml @@ -7,27 +7,26 @@ parameters: default: $(Build.SourcesDirectory) steps: - - task: PowerShell@2 displayName: Set target publish package name inputs: - targetType: 'inline' - script: | - if($env:PackageName -eq $null) - { - Write-Host "$("##vso[task.setvariable variable=TargetPublishName]")$env:TargetBoard" - } - else - { - Write-Host "$("##vso[task.setvariable variable=TargetPublishName]")$env:PackageName" - } - errorActionPreference: 'stop' - failOnStderr: 'true' + targetType: "inline" + script: | + if($env:PackageName -eq $null) + { + Write-Host "$("##vso[task.setvariable variable=TargetPublishName]")$env:TargetBoard" + } + else + { + Write-Host "$("##vso[task.setvariable variable=TargetPublishName]")$env:PackageName" + } + errorActionPreference: "stop" + failOnStderr: true - task: PowerShell@2 displayName: Enable long paths inputs: - targetType: 'inline' + targetType: "inline" script: New-ItemProperty -Path "HKLM:\SYSTEM\CurrentControlSet\Control\FileSystem" -Name "LongPathsEnabled" -Value 1 -PropertyType DWORD -Force - task: PowerShell@2 @@ -35,6 +34,6 @@ steps: condition: ne(variables['Build.Repository.Name'], 'nanoframework/nf-Community-Targets') inputs: workingDirectory: ${{ parameters.repoDirectory }}\targets-community - targetType: 'inline' + targetType: "inline" script: | New-Item -Path . -Name "CMakePresets.json" -ItemType "file" -Value "{`n""version"": 4,`n""include"": []`n}" diff --git a/azure-pipelines-templates/build-ti-simplelink-targets.yml b/azure-pipelines-templates/build-ti-simplelink-targets.yml index 8e20100e00..ba5677613e 100644 --- a/azure-pipelines-templates/build-ti-simplelink-targets.yml +++ b/azure-pipelines-templates/build-ti-simplelink-targets.yml @@ -7,19 +7,18 @@ parameters: default: $(Build.SourcesDirectory) steps: - - template: setup-cmake-user-presets.yml parameters: repoDirectory: ${{ parameters.repoDirectory }} - task: CMake@1 inputs: - cmakeArgs: ' --preset $(TargetBoard) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_BOARD=$(TargetBoard) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions)' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: " --preset $(TargetBoard) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER) -DTARGET_BOARD=$(TargetBoard) -DTARGET_NAME=$(TargetPublishName) $(BuildOptions)" + workingDirectory: ${{ parameters.repoDirectory }} displayName: Setup build with CMake - task: CMake@1 inputs: - cmakeArgs: '--build --preset $(TargetBoard) --target all --config MinSizeRel' - workingDirectory: ${{ parameters.repoDirectory }} + cmakeArgs: "--build --preset $(TargetBoard) --target all --config MinSizeRel" + workingDirectory: ${{ parameters.repoDirectory }} displayName: Build with CMake diff --git a/azure-pipelines-templates/check-code-style.yml b/azure-pipelines-templates/check-code-style.yml index dc60e963f1..d111ae5e72 100644 --- a/azure-pipelines-templates/check-code-style.yml +++ b/azure-pipelines-templates/check-code-style.yml @@ -2,14 +2,13 @@ # See LICENSE file in the project root for full license information. steps: - - task: PowerShell@2 name: Check_Code_Style displayName: Check code style condition: ne(variables['System.PullRequest.PullRequestId'], '') inputs: failOnStderr: false - targetType: 'inline' + targetType: "inline" script: | # need this to remove definition of redirect stdErr (only on Azure Pipelines image fo VS2019) $env:GIT_REDIRECT_STDERR = '2>&1' @@ -34,7 +33,7 @@ steps: # fetch GitHub repo & branches Write-Debug "##[debug] Fetch GitHub repo & branches" - + # add remote for PR head "Adding remote: $($pr.head.repo.html_url)..." | Write-Host -ForegroundColor White @@ -56,7 +55,7 @@ steps: $prFiles = Invoke-WebRequest "https://api.github.com/repos/$env:Build_Repository_Name/pulls/$env:System_PullRequest_PullRequestNumber/files" | ConvertFrom-Json "Starting file check..." | Write-Host -ForegroundColor White - + # find clang-format $clangFormat = "clang-format.exe" if(!(Get-Command $clangFormat -ErrorAction SilentlyContinue)) @@ -106,7 +105,7 @@ steps: # commit changed files git add -A 2>&1 git commit -m "Code style fixes" -m "Automated fixes for code style." > $null - + "Pushing changes..." | Write-Host -ForegroundColor White # push to nf-interpreter repo @@ -167,5 +166,5 @@ steps: displayName: Check code style (SKIP) condition: eq(variables['System.PullRequest.PullRequestId'], '') inputs: - targetType: 'inline' + targetType: "inline" script: exit 0 diff --git a/azure-pipelines-templates/download-hexdfu.yml b/azure-pipelines-templates/download-hexdfu.yml index 4223a29c4a..5b3667ced5 100644 --- a/azure-pipelines-templates/download-hexdfu.yml +++ b/azure-pipelines-templates/download-hexdfu.yml @@ -4,7 +4,7 @@ steps: - task: Cache@2 inputs: - key: '3-0 | hex2dfuKey' + key: "3-0 | hex2dfuKey" restoreKeys: hex2dfuKey path: $(Agent.TempDirectory)/hex2dfu cacheHitVar: HEX2DFU_CACHE_RESTORED @@ -15,17 +15,17 @@ steps: condition: and( eq(variables['NeedsDFU'], true), ne(variables.HEX2DFU_CACHE_RESTORED, 'true')) displayName: Install HEX2DFU inputs: - targetType: 'filePath' - filePath: '$(Build.Repository.LocalPath)\install-scripts\install-nf-hex2dfu.ps1' - failOnStderr: 'true' + targetType: "filePath" + filePath: '$(Build.Repository.LocalPath)\install-scripts\install-nf-hex2dfu.ps1' + failOnStderr: true - task: PowerShell@2 inputs: - targetType: 'inline' - script: | - $newPath = "$env:Agent_TempDirectory".Replace('\','/') + "/hex2dfu" - Write-Host "$("##vso[task.setvariable variable=HEX2DFU_PATH]")$newPath" - errorActionPreference: 'stop' - failOnStderr: 'true' + targetType: "inline" + script: | + $newPath = "$env:Agent_TempDirectory".Replace('\','/') + "/hex2dfu" + Write-Host "$("##vso[task.setvariable variable=HEX2DFU_PATH]")$newPath" + errorActionPreference: "stop" + failOnStderr: true condition: eq(variables['NeedsDFU'], true) displayName: Adjust HexDFU path diff --git a/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml b/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml index b9071ba92a..e99ffa925a 100644 --- a/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml +++ b/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml @@ -11,7 +11,7 @@ steps: condition: eq(variables.GccArm_Version, '') displayName: Cache latest ARM GCC toolchain inputs: - key: 'gcc-13_2_rel1 | gccUpdateKey' + key: "gcc-13_2_rel1 | gccUpdateKey" restoreKeys: gccUpdateKey path: $(Agent.TempDirectory)\arm-gnu-toolchain-${{ parameters.gccArmVersion }}-mingw-w64-i686-arm-none-eabi cacheHitVar: GCC_CACHE_RESTORED @@ -20,17 +20,17 @@ steps: condition: ne(variables.GCC_CACHE_RESTORED, 'true') displayName: Downloading ARM GCC toolchain inputs: - targetType: 'filePath' - filePath: '$(Build.Repository.LocalPath)\install-scripts\install-arm-gcc-toolchain.ps1' - arguments: '-Version "${{ parameters.gccArmVersion }}"' - failOnStderr: true + targetType: "filePath" + filePath: '$(Build.Repository.LocalPath)\install-scripts\install-arm-gcc-toolchain.ps1' + arguments: '-Version "${{ parameters.gccArmVersion }}"' + failOnStderr: true - task: ExtractFiles@1 displayName: Extracting ARM GCC toolchain condition: ne(variables.GCC_CACHE_RESTORED, 'true') inputs: archiveFilePatterns: '$(Agent.TempDirectory)\arm-gnu-toolchain-${{ parameters.gccArmVersion }}-mingw-w64-i686-arm-none-eabi.zip' - destinationFolder: '$(Agent.TempDirectory)' + destinationFolder: "$(Agent.TempDirectory)" cleanDestinationFolder: false - script: echo "##vso[task.prependpath]$(Agent.TempDirectory)\arm-gnu-toolchain-${{ parameters.gccArmVersion }}-mingw-w64-i686-arm-none-eabi\bin" diff --git a/azure-pipelines-templates/download-install-esp32-build-components.yml b/azure-pipelines-templates/download-install-esp32-build-components.yml index a0fd7e24fd..5c5878736d 100644 --- a/azure-pipelines-templates/download-install-esp32-build-components.yml +++ b/azure-pipelines-templates/download-install-esp32-build-components.yml @@ -2,12 +2,11 @@ # See LICENSE file in the project root for full license information. steps: - # cache IDF tools folder - task: Cache@2 displayName: Cache ESP32 tools inputs: - key: 'esp32_tools | 5_1_3' + key: "esp32_tools | 5_1_3" restoreKeys: 5_1_3 path: $(UserProfile)\.espressif\tools cacheHitVar: ESP32_TOOLS_CACHE_RESTORED @@ -25,31 +24,31 @@ steps: - task: UsePythonVersion@0 displayName: Set Python to v3.11 inputs: - versionSpec: '3.11' + versionSpec: "3.11" addToPath: true - task: PowerShell@2 displayName: Fix install.ps1 inputs: - targetType: 'inline' + targetType: "inline" workingDirectory: $(Agent.BuildDirectory)\s\esp-idf script: | $filecontent = Get-Content('install.ps1') attrib $file -r $filecontent -replace '--features=${FEATURES}' , ' ' | Out-File 'install.ps1' -Encoding utf8 - + # run IDF installers - task: PowerShell@2 displayName: Install IDF (step 1) inputs: - targetType: 'filePath' + targetType: "filePath" filePath: $(Agent.BuildDirectory)\s\esp-idf\install.ps1 workingDirectory: $(Agent.BuildDirectory)\s\esp-idf - task: PowerShell@2 displayName: Install IDF (step 2) inputs: - targetType: 'inline' + targetType: "inline" workingDirectory: $(Agent.BuildDirectory)\s\esp-idf\tools\requirements script: | python -m pip install -r requirements.core.txt @@ -57,19 +56,19 @@ steps: - task: PowerShell@2 displayName: Install IDF (step 3) inputs: - targetType: 'filePath' + targetType: "filePath" filePath: $(Agent.BuildDirectory)\s\esp-idf\export.ps1 workingDirectory: $(Agent.BuildDirectory)\s\esp-idf - task: PowerShell@2 displayName: Update PATH with IDF tools inputs: - targetType: 'inline' + targetType: "inline" workingDirectory: $(Agent.BuildDirectory)\s\esp-idf script: | $ErrorActionPreference = 'SilentlyContinue' $envars_raw = python tools/idf_tools.py export --format key-value 2>$null - + # find element the PATH collection $pathElement = 0 diff --git a/azure-pipelines-templates/download-install-llvm.yml b/azure-pipelines-templates/download-install-llvm.yml index 816739f29b..b26dc030f4 100644 --- a/azure-pipelines-templates/download-install-llvm.yml +++ b/azure-pipelines-templates/download-install-llvm.yml @@ -6,7 +6,7 @@ steps: condition: ne(variables['System.PullRequest.PullRequestId'], '') displayName: Cache LLVM inputs: - key: 'llvm_18_1_7_0 | llvmUpdateKey' + key: "llvm_18_1_7_0 | llvmUpdateKey" restoreKeys: llvmUpdateKey path: $(Agent.TempDirectory)\llvm cacheHitVar: LLVM_CACHE_RESTORED @@ -19,13 +19,13 @@ steps: ne(variables.LLVM_CACHE_RESTORED, 'true') ) inputs: - targetType: 'inline' + targetType: "inline" script: | $url = "https://github.com/llvm/llvm-project/releases/download/llvmorg-18.1.7/LLVM-18.1.7-win64.exe" $output = "$(Agent.TempDirectory)\LLVM-18.1.7-win64.exe" (New-Object Net.WebClient).DownloadFile($url, $output) - errorActionPreference: 'stop' - failOnStderr: 'true' + errorActionPreference: "stop" + failOnStderr: true - task: ExtractFiles@1 displayName: Install LLVM @@ -35,9 +35,9 @@ steps: ne(variables.LLVM_CACHE_RESTORED, 'true') ) inputs: - archiveFilePatterns: '$(Agent.TempDirectory)\LLVM-18.1.7-win64.exe' + archiveFilePatterns: '$(Agent.TempDirectory)\LLVM-18.1.7-win64.exe' destinationFolder: '$(Agent.TempDirectory)\llvm' - + - script: echo "##vso[task.prependpath]$(Agent.TempDirectory)\llvm\bin" displayName: Add LLVM to PATH condition: ne(variables['System.PullRequest.PullRequestId'], '') diff --git a/azure-pipelines-templates/download-install-ninja.yml b/azure-pipelines-templates/download-install-ninja.yml index a2a10a3d3f..8891327331 100644 --- a/azure-pipelines-templates/download-install-ninja.yml +++ b/azure-pipelines-templates/download-install-ninja.yml @@ -9,7 +9,7 @@ parameters: steps: - task: Cache@2 inputs: - key: '1-10-0 | ninjaKey' + key: "1-10-0 | ninjaKey" restoreKeys: ninjaKey path: $(Agent.TempDirectory)/ninja cacheHitVar: NINJA_CACHE_RESTORED @@ -19,14 +19,14 @@ steps: condition: ne(variables.NINJA_CACHE_RESTORED, 'true') displayName: Download Ninja inputs: - targetType: 'filePath' + targetType: "filePath" filePath: '${{ parameters.repoDirectory }}\install-scripts\install-ninja.ps1' - failOnStderr: 'true' + failOnStderr: true - task: ExtractFiles@1 inputs: - archiveFilePatterns: '$(Agent.TempDirectory)\ninja.zip' - destinationFolder: '$(Agent.TempDirectory)\ninja' + archiveFilePatterns: '$(Agent.TempDirectory)\ninja.zip' + destinationFolder: '$(Agent.TempDirectory)\ninja' condition: ne(variables.NINJA_CACHE_RESTORED, 'true') displayName: Extract Ninja diff --git a/azure-pipelines-templates/download-srecord.yml b/azure-pipelines-templates/download-srecord.yml index 7280209bb4..a559a4d395 100644 --- a/azure-pipelines-templates/download-srecord.yml +++ b/azure-pipelines-templates/download-srecord.yml @@ -6,7 +6,7 @@ steps: condition: eq(variables['NeedsSRECORD'], true) displayName: Cache SRECORD inputs: - key: '1-0 | srecordKey' + key: "1-0 | srecordKey" restoreKeys: srecordKey path: $(Agent.TempDirectory)/srecord cacheHitVar: SRECORD_CACHE_RESTORED @@ -15,13 +15,13 @@ steps: condition: eq(variables['NeedsSRECORD'], true) displayName: Install SRECORD inputs: - targetType: 'filePath' - filePath: '$(Build.Repository.LocalPath)\install-scripts\install-srecord.ps1' - failOnStderr: true + targetType: "filePath" + filePath: '$(Build.Repository.LocalPath)\install-scripts\install-srecord.ps1' + failOnStderr: true - task: ExtractFiles@1 condition: and( eq(variables['NeedsSRECORD'], true), ne(variables.SRECORD_CACHE_RESTORED, 'true')) displayName: Extract SRECORD inputs: - archiveFilePatterns: '$(Agent.TempDirectory)\srecord.zip' - destinationFolder: '$(Agent.TempDirectory)\srecord' + archiveFilePatterns: '$(Agent.TempDirectory)\srecord.zip' + destinationFolder: '$(Agent.TempDirectory)\srecord' diff --git a/azure-pipelines-templates/nb-gitversioning.yml b/azure-pipelines-templates/nb-gitversioning.yml index d807b5e762..7610382108 100644 --- a/azure-pipelines-templates/nb-gitversioning.yml +++ b/azure-pipelines-templates/nb-gitversioning.yml @@ -17,18 +17,18 @@ steps: condition: ne(variables['system.pullrequest.pullRequestId'], '') displayName: Set temporary build number inputs: - targetType: 'inline' - script: | - Write-Host "$("##vso[task.setvariable variable=NBGV_Version]")0.0.0" - Write-Host "$("##vso[task.setvariable variable=NBGV_VersionMajor]")0" - Write-Host "$("##vso[task.setvariable variable=NBGV_VersionMinor]")$env:System_PullRequest_PullRequestNumber" - Write-Host "$("##vso[task.setvariable variable=NBGV_AssemblyInformationalVersion]")00000000000" - Write-Host "$("##vso[task.setvariable variable=NBGV_NuGetPackageVersion]")0.0.$env:System_PullRequest_PullRequestNumber-alpha.$env:NBGV_BuildNumber" + targetType: "inline" + script: | + Write-Host "$("##vso[task.setvariable variable=NBGV_Version]")0.0.0" + Write-Host "$("##vso[task.setvariable variable=NBGV_VersionMajor]")0" + Write-Host "$("##vso[task.setvariable variable=NBGV_VersionMinor]")$env:System_PullRequest_PullRequestNumber" + Write-Host "$("##vso[task.setvariable variable=NBGV_AssemblyInformationalVersion]")00000000000" + Write-Host "$("##vso[task.setvariable variable=NBGV_NuGetPackageVersion]")0.0.$env:System_PullRequest_PullRequestNumber-alpha.$env:NBGV_BuildNumber" - task: PowerShell@2 displayName: Get target build counter inputs: - targetType: 'inline' + targetType: "inline" script: | $counter = $env:REVISION $version = ([int]$counter).ToString() diff --git a/azure-pipelines-templates/pack-publish-managed-helpers.yml b/azure-pipelines-templates/pack-publish-managed-helpers.yml index 6b24b08c98..02d6498f19 100644 --- a/azure-pipelines-templates/pack-publish-managed-helpers.yml +++ b/azure-pipelines-templates/pack-publish-managed-helpers.yml @@ -2,7 +2,6 @@ # See LICENSE file in the project root for full license information. steps: - # check if managed helper files where changed # - powershell: | # git config --global user.email "nanoframework@outlook.com" @@ -28,7 +27,7 @@ steps: # } # else # { - # echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]False" + # echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]False" # } # condition: succeeded() @@ -36,7 +35,7 @@ steps: - task: NuGetCommand@2 inputs: - command: 'custom' + command: "custom" arguments: 'pack targets\ChibiOS\$(TargetBoard)\managed_helpers\package.nuspec -Version $(PACKAGE_NUGET_VERSION)' condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) displayName: Pack managed helpers NuGet @@ -48,7 +47,7 @@ steps: sourceFolder: $(Build.SourcesDirectory) Contents: | **\nanoFramework.Targets*.nupkg - TargetFolder: '$(Build.ArtifactStagingDirectory)' + TargetFolder: "$(Build.ArtifactStagingDirectory)" flattenFolders: true ignoreMakeDirErrors: true @@ -57,7 +56,7 @@ steps: inputs: command: push nuGetFeedType: external - packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' - publishFeedCredentials: 'NuGet-$(System.TeamProject)' + packagesToPush: "$(Build.ArtifactStagingDirectory)/*.nupkg" + publishFeedCredentials: "NuGet-$(System.TeamProject)" condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true), eq(variables['System.PullRequest.PullRequestId'], '') ) displayName: Push managed helpers NuGet packages to NuGet diff --git a/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml b/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml index 3da24a241c..9f18016386 100644 --- a/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml +++ b/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml @@ -2,7 +2,6 @@ # See LICENSE file in the project root for full license information. steps: - # check if managed helper files where changed - powershell: | git config --global user.email "nanoframework@outlook.com" @@ -36,7 +35,7 @@ steps: - task: NuGetCommand@2 inputs: - command: 'custom' + command: "custom" arguments: 'pack targets\TI_SimpleLink\$(TargetBoard)\managed_helpers\package.nuspec -Version $(PACKAGE_NUGET_VERSION)' condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) displayName: Pack managed helpers NuGet @@ -48,7 +47,7 @@ steps: sourceFolder: $(Build.SourcesDirectory) Contents: | **\nanoFramework.Targets*.nupkg - TargetFolder: '$(Build.ArtifactStagingDirectory)' + TargetFolder: "$(Build.ArtifactStagingDirectory)" flattenFolders: true ignoreMakeDirErrors: true @@ -57,7 +56,7 @@ steps: inputs: command: push nuGetFeedType: external - packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' - publishFeedCredentials: 'NuGet-$(System.TeamProject)' + packagesToPush: "$(Build.ArtifactStagingDirectory)/*.nupkg" + publishFeedCredentials: "NuGet-$(System.TeamProject)" condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true), eq(variables['System.PullRequest.PullRequestId'], '') ) displayName: Push managed helpers NuGet packages to NuGet diff --git a/azure-pipelines-templates/publish-cloudsmith.yml b/azure-pipelines-templates/publish-cloudsmith.yml index a173df3fd3..099496aaeb 100644 --- a/azure-pipelines-templates/publish-cloudsmith.yml +++ b/azure-pipelines-templates/publish-cloudsmith.yml @@ -5,7 +5,6 @@ # set 'ForceUpload' variable to true on target matrix steps: - - task: ArchiveFiles@2 condition: >- and( @@ -19,9 +18,9 @@ steps: ) displayName: Zip binary files (release & PR) inputs: - rootFolderOrFile: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' + rootFolderOrFile: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' includeRootFolder: false - archiveType: 'zip' + archiveType: "zip" archiveFile: '$(Agent.TempDirectory)\$(TargetPublishName)-$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER).zip' replaceExistingArchive: true @@ -57,9 +56,9 @@ steps: ) displayName: Zip binary files (preview) inputs: - rootFolderOrFile: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' + rootFolderOrFile: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' includeRootFolder: false - archiveType: 'zip' + archiveType: "zip" archiveFile: '$(Agent.TempDirectory)\$(TargetPublishName)-$(NBGV_SimpleVersion)-preview.$(TARGET_BUILD_COUNTER).zip' replaceExistingArchive: true @@ -102,60 +101,59 @@ steps: ) displayName: Set Cloudsmith repo path inputs: - targetType: 'inline' + targetType: "inline" script: | - $repoName = $env:Build_Repository_Name - $branchName = $env:Build_SourceBranchName - $forceUpload = $env:ForceUpload - - Write-Host "repo name is: $repoName" - Write-Host "branch name is: $branchName" - - if( $env:Build_Repository_Name -like "*nf-Community-Targets" ) + $repoName = $env:Build_Repository_Name + $branchName = $env:Build_SourceBranchName + $forceUpload = $env:ForceUpload + + Write-Host "repo name is: $repoName" + Write-Host "branch name is: $branchName" + + if( $env:Build_Repository_Name -like "*nf-Community-Targets" ) + { + # this is a build for a community target + $cloudsmithRepo = "nanoframework-images-community-targets" + # set publishing package name + $publishingPackageName = "$(TargetPublishName)-$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" + # set version + $packageVersion = "$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" + } + else + { + if( $env:Build_SourceBranchName -match "develop" -or + $env:Build_SourceBranchName -match "^release*" -or + $env:ForceUpload -eq "true") { - # this is a build for a community target - $cloudsmithRepo = "nanoframework-images-community-targets" + # this a dev, release branch or force upload, publish to Cloudsmith dev repo + $cloudsmithRepo = "nanoframework-images-dev" # set publishing package name - $publishingPackageName = "$(TargetPublishName)-$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" + $publishingPackageName = "$(TargetPublishName)-$(NBGV_SimpleVersion)-preview.$(TARGET_BUILD_COUNTER)" # set version - $packageVersion = "$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" + $packageVersion = "$(NBGV_SimpleVersion)-preview.$(TARGET_BUILD_COUNTER)" } - else + else { - if( $env:Build_SourceBranchName -match "develop" -or - $env:Build_SourceBranchName -match "^release*" -or - $env:ForceUpload -eq "true") - { - # this a dev, release branch or force upload, publish to Cloudsmith dev repo - $cloudsmithRepo = "nanoframework-images-dev" - # set publishing package name - $publishingPackageName = "$(TargetPublishName)-$(NBGV_SimpleVersion)-preview.$(TARGET_BUILD_COUNTER)" - # set version - $packageVersion = "$(NBGV_SimpleVersion)-preview.$(TARGET_BUILD_COUNTER)" - } - else - { - # this main branch, publish to Cloudsmith stable repo - $cloudsmithRepo = "nanoframework-images" - # set publishing package name - $publishingPackageName = "$(TargetPublishName)-$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" - # set version - $packageVersion = "$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" - } + # this main branch, publish to Cloudsmith stable repo + $cloudsmithRepo = "nanoframework-images" + # set publishing package name + $publishingPackageName = "$(TargetPublishName)-$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" + # set version + $packageVersion = "$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" } + } - Write-Host "$("##vso[task.setvariable variable=CLOUDSMITH_REPO]")$cloudsmithRepo" - Write-Host "$("##vso[task.setvariable variable=PUBLISHING_PACKAGE_NAME]")$publishingPackageName" - Write-Host "$("##vso[task.setvariable variable=PACKAGE_VERSION]")$packageVersion" + Write-Host "$("##vso[task.setvariable variable=CLOUDSMITH_REPO]")$cloudsmithRepo" + Write-Host "$("##vso[task.setvariable variable=PUBLISHING_PACKAGE_NAME]")$publishingPackageName" + Write-Host "$("##vso[task.setvariable variable=PACKAGE_VERSION]")$packageVersion" - Write-Host "Cloudsmith repo: $cloudsmithRepo" - Write-Host "Cloudsmith package: $publishingPackageName" - Write-Host "Cloudsmith package version: $packageVersion" + Write-Host "Cloudsmith repo: $cloudsmithRepo" + Write-Host "Cloudsmith package: $publishingPackageName" + Write-Host "Cloudsmith package version: $packageVersion" - - errorActionPreference: 'stop' - failOnStderr: 'true' + errorActionPreference: "stop" + failOnStderr: true - task: PowerShell@2 condition: >- @@ -171,15 +169,15 @@ steps: ) displayName: Upload package to Cloudsmith inputs: - targetType: 'inline' + targetType: "inline" script: | - # install Cloudsmith CLI - python -m pip install --upgrade cloudsmith-cli --quiet + # install Cloudsmith CLI + python -m pip install --upgrade cloudsmith-cli --quiet - Write-Host "Uploading $(PUBLISHING_PACKAGE_NAME) v$(PACKAGE_VERSION) to $(CLOUDSMITH_REPO)" + Write-Host "Uploading $(PUBLISHING_PACKAGE_NAME) v$(PACKAGE_VERSION) to $(CLOUDSMITH_REPO)" - cloudsmith push raw net-nanoframework/$(CLOUDSMITH_REPO) $(Agent.TempDirectory)\$(PUBLISHING_PACKAGE_NAME).zip --name $(TargetPublishName) --version $(PACKAGE_VERSION) --tags $(TargetPlatform),$(TargetSeries) --republish -k $(CLOUDSMITH_KEY) + cloudsmith push raw net-nanoframework/$(CLOUDSMITH_REPO) $(Agent.TempDirectory)\$(PUBLISHING_PACKAGE_NAME).zip --name $(TargetPublishName) --version $(PACKAGE_VERSION) --tags $(TargetPlatform),$(TargetSeries) --republish -k $(CLOUDSMITH_KEY) - errorActionPreference: 'stop' - failOnStderr: 'false' + errorActionPreference: "stop" + failOnStderr: false diff --git a/azure-pipelines-templates/publish-nanoclr.yml b/azure-pipelines-templates/publish-nanoclr.yml index 08a5e6e086..216643895f 100644 --- a/azure-pipelines-templates/publish-nanoclr.yml +++ b/azure-pipelines-templates/publish-nanoclr.yml @@ -5,7 +5,6 @@ # set 'ForceUpload' variable to true on target matrix steps: - # execute on 'ForceUpload' parameter - task: PowerShell@2 condition: >- @@ -18,33 +17,33 @@ steps: ) displayName: Set Cloudsmith repo path inputs: - targetType: 'inline' + targetType: "inline" script: | - $repoName = $env:Build_Repository_Name - $branchName = $env:Build_SourceBranchName - $forceUpload = $env:ForceUpload + $repoName = $env:Build_Repository_Name + $branchName = $env:Build_SourceBranchName + $forceUpload = $env:ForceUpload - Write-Host "repo name is: $repoName" - Write-Host "branch name is: $branchName" + Write-Host "repo name is: $repoName" + Write-Host "branch name is: $branchName" - if( $env:Build_SourceBranchName -match "develop" -or - $env:Build_SourceBranchName -match "^release*" -or - $forceUpload -eq "true") - { - # this a dev, release branch or force upload, publish to Cloudsmith dev repo - Write-Host "$("##vso[task.setvariable variable=CLOUDSMITH_REPO]")nanoframework-images-dev" - # set version - Write-Host "$("##vso[task.setvariable variable=PACKAGE_VERSION]")$(NBGV_NuGetPackageVersion)" - } - else - { - # this main branch, publish to Cloudsmith stable repo - Write-Host "$("##vso[task.setvariable variable=CLOUDSMITH_REPO]")nanoframework-images" - # set version - Write-Host "$("##vso[task.setvariable variable=PACKAGE_VERSION]")$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" - } - errorActionPreference: 'stop' - failOnStderr: 'true' + if( $env:Build_SourceBranchName -match "develop" -or + $env:Build_SourceBranchName -match "^release*" -or + $forceUpload -eq "true") + { + # this a dev, release branch or force upload, publish to Cloudsmith dev repo + Write-Host "$("##vso[task.setvariable variable=CLOUDSMITH_REPO]")nanoframework-images-dev" + # set version + Write-Host "$("##vso[task.setvariable variable=PACKAGE_VERSION]")$(NBGV_NuGetPackageVersion)" + } + else + { + # this main branch, publish to Cloudsmith stable repo + Write-Host "$("##vso[task.setvariable variable=CLOUDSMITH_REPO]")nanoframework-images" + # set version + Write-Host "$("##vso[task.setvariable variable=PACKAGE_VERSION]")$(NBGV_SimpleVersion).$(TARGET_BUILD_COUNTER)" + } + errorActionPreference: "stop" + failOnStderr: true - task: PowerShell@2 condition: >- @@ -60,17 +59,17 @@ steps: ) displayName: Upload nanoCLR to Cloudsmith inputs: - targetType: 'inline' + targetType: "inline" script: | - # install Cloudsmith CLI - python -m pip install --upgrade cloudsmith-cli --quiet + # install Cloudsmith CLI + python -m pip install --upgrade cloudsmith-cli --quiet - Write-Host "Uploading nanoCLR v$(WINCLR_PACKAGE_VERSION) to Cloudsmith" + Write-Host "Uploading nanoCLR v$(WINCLR_PACKAGE_VERSION) to Cloudsmith" - cloudsmith push raw net-nanoframework/$(CLOUDSMITH_REPO) $(Build.ArtifactStagingDirectory)\WIN32_nanoCLR\nanoFramework.nanoCLR.exe --name WIN32_nanoCLR --version $(WINCLR_PACKAGE_VERSION) -k $(CLOUDSMITH_KEY) + cloudsmith push raw net-nanoframework/$(CLOUDSMITH_REPO) $(Build.ArtifactStagingDirectory)\WIN32_nanoCLR\nanoFramework.nanoCLR.exe --name WIN32_nanoCLR --version $(WINCLR_PACKAGE_VERSION) -k $(CLOUDSMITH_KEY) - cloudsmith push raw net-nanoframework/$(CLOUDSMITH_REPO) $(Build.ArtifactStagingDirectory)\WIN_DLL_nanoCLR\nanoFramework.nanoCLR.dll --name WIN_DLL_nanoCLR --version $(WINCLR_PACKAGE_VERSION) -k $(CLOUDSMITH_KEY) + cloudsmith push raw net-nanoframework/$(CLOUDSMITH_REPO) $(Build.ArtifactStagingDirectory)\WIN_DLL_nanoCLR\nanoFramework.nanoCLR.dll --name WIN_DLL_nanoCLR --version $(WINCLR_PACKAGE_VERSION) -k $(CLOUDSMITH_KEY) - errorActionPreference: 'stop' - failOnStderr: 'false' + errorActionPreference: "stop" + failOnStderr: false diff --git a/azure-pipelines-templates/setup-cmake-user-presets.yml b/azure-pipelines-templates/setup-cmake-user-presets.yml index 83f6c8c458..dde16daeb4 100644 --- a/azure-pipelines-templates/setup-cmake-user-presets.yml +++ b/azure-pipelines-templates/setup-cmake-user-presets.yml @@ -7,12 +7,11 @@ parameters: default: $(Build.SourcesDirectory) steps: - - task: PowerShell@2 displayName: Compose CMakeUserPresets inputs: - workingDirectory: ${{ parameters.repoDirectory }}/config - targetType: 'inline' + workingDirectory: ${{ parameters.repoDirectory }}/config + targetType: "inline" script: | $file = "user-tools-repos.json" @@ -20,11 +19,11 @@ steps: [regex]$pattern='user-tools-repos-cloud' $pattern.replace([IO.File]::ReadAllText($file), 'user-tools-repos', 1) | Out-File $file -Encoding UTF8 - + $file = "user-prefs.json" Rename-Item -Path "user-prefs.TEMPLATE.json" -NewName $file - + $filecontent = Get-Content($file) attrib $file -r $filecontent -replace 'Debug', 'MinSizeRel' | Out-File $file -Encoding UTF8 diff --git a/azure-pipelines.yml b/azure-pipelines.yml index cff71d3e77..d48bca72ae 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -1,6 +1,9 @@ +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. + trigger: branches: - include: + include: - main - develop* - release-* @@ -45,1415 +48,1412 @@ resources: type: github name: espressif/esp-idf endpoint: nanoframework - ref: refs/tags/v5.1.3 + ref: 'refs/tags/v5.1.3' - repository: mscorlib type: github name: nanoframework/CoreLibrary endpoint: nanoframework - + jobs: + ############################## + - job: Check_Build_Options + pool: + vmImage: "windows-latest" + + variables: + DOTNET_NOLOGO: true + + steps: + - checkout: self + fetchDepth: 1 -############################## -- job: Check_Build_Options - pool: - vmImage: 'windows-latest' - - variables: - DOTNET_NOLOGO: true - - steps: - - checkout: self - fetchDepth: 1 - - # get commit message - - powershell: | - - # set default values - echo "##vso[task.setvariable variable=RUN_MSCORLIB_TESTS;isOutput=true]false" - - if($env:StartReleaseCandidate -like "true") - { - # this is a release prep so NO build - echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" - - Write-Host "##[command] Release preparation, skipping build." - } - else - { - # get commit details, if this is a PR - if($env:System_PullRequest_PullRequestId -ne $null) - { - Write-Host "##[command] **This is a PR build**" - - $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -ContentType "application/json" -Method GET - - if( ($commit.commit.author.name -eq "nfbot") -and ($commit.commit.message -like "*[version update]*") ) + # get commit message + - powershell: | + + # set default values + echo "##vso[task.setvariable variable=RUN_MSCORLIB_TESTS;isOutput=true]false" + + if($env:StartReleaseCandidate -like "true") { - echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" + # this is a release prep so NO build + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" + + Write-Host "##[command] Release preparation, skipping build." } else { - echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]false" + # get commit details, if this is a PR + if($env:System_PullRequest_PullRequestId -ne $null) + { + Write-Host "##[command] **This is a PR build**" + + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -ContentType "application/json" -Method GET + + if( ($commit.commit.author.name -eq "nfbot") -and ($commit.commit.message -like "*[version update]*") ) + { + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" + } + else + { + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]false" + } + + # check if Unit Tests for mscorlib should be run + if($commit.commit.message -like "*[run mscorlib tests]*") + { + echo "##vso[task.setvariable variable=RUN_MSCORLIB_TESTS;isOutput=true]true" + } + + } + else + { + Write-Host "##[command] **build for other reasons**" + + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]false" + } } - # check if Unit Tests for mscorlib should be run - if($commit.commit.message -like "*[run mscorlib tests]*") + name: BuildOptions + displayName: Get build options + + # check what changed + - powershell: | + git config --global user.email "nfbot" + git config --global user.name "nanoframework@outlook.com" + + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)")))" + + if($env:StartReleaseCandidate -like "true") { - echo "##vso[task.setvariable variable=RUN_MSCORLIB_TESTS;isOutput=true]true" + # this is a release prep so NO build } - - } - else - { - Write-Host "##[command] **build for other reasons**" - - echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]false" - } - } - - name: BuildOptions - displayName: Get build options - - # check what changed - - powershell: | - git config --global user.email "nfbot" - git config --global user.name "nanoframework@outlook.com" - - $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)")))" - - if($env:StartReleaseCandidate -like "true") - { - # this is a release prep so NO build - } - elseif($env:Build_Reason -eq "Manual") - { - # this is a manual build, no need to check anything - Write-host "##[command] Manual build" - } - else - { - # check if this build was triggered by the pipeline itself - if($env:Build_Reason -eq "Manual") + elseif($env:Build_Reason -eq "Manual") { # this is a manual build, no need to check anything Write-host "##[command] Manual build" - } - if($env:System_PullRequest_PullRequestId -ne $null) - { - # get files changed in PR, if this is a PR - $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/pulls/$env:System_PullRequest_PullRequestNumber/files" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET - - # filter removed files - $files = $commit.where{$_.status -ne 'removed'} - } + } else { - # get files changed in the commit, if this is NOT a PR - $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + # check if this build was triggered by the pipeline itself + if($env:Build_Reason -eq "Manual") + { + # this is a manual build, no need to check anything + Write-host "##[command] Manual build" + } + if($env:System_PullRequest_PullRequestId -ne $null) + { + # get files changed in PR, if this is a PR + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/pulls/$env:System_PullRequest_PullRequestNumber/files" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + + # filter removed files + $files = $commit.where{$_.status -ne 'removed'} + } + else + { + # get files changed in the commit, if this is NOT a PR + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + + # filter removed files + $files = $commit.files.where{$_.status -ne 'removed'} + } + + # get file names only + $files = $files | % {$_.filename} + + Write-host "##[group] Files changed:" + $files | % { Write-host $_ } + Write-host "##[endgroup]" + + # set default values + echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_FREERTOS;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_WIN32;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_NANOCLR_CLI;isOutput=true]false" + echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]false" + + if( + (($files.where{$_.Contains('/')}).Count -eq 0) -Or + (($files.where{$_.StartsWith('azure-pipelines-templates')}).Count -gt 0) -Or + (($files.where{$_.StartsWith('CMake')}).Count -gt 0) -Or + (($files.where{$_.StartsWith('src')}).Count -gt 0) + ) + { + # files at: + # - repo root + # - azure-pipelines-templates + # - CMake + # - src + + echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]true" + + Write-host "##[command] Building ALL targets" + } + + if( ($files.where{$_.Contains('targets/ChibiOS')}).Count -gt 0) + { + # files at ChibiOS folder + echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + + Write-host "##[command] Building ChibiOS targets" + } + + if( ($files.where{$_.Contains('targets/FreeRTOS')}).Count -gt 0) + { + # files at FreeRTOS folder + echo "##vso[task.setvariable variable=BUILD_FREERTOS;isOutput=true]true" + + Write-host "##[command] Building FreeRTOS targets" + } + + if( ($files.where{$_.Contains('targets/ESP32')}).Count -gt 0) + { + # files at ESP32 folder + echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]true" + + Write-host "##[command] Building ESP32 targets" + } + + if( ($files.where{$_.Contains('targets/TI_SimpleLink')}).Count -gt 0) + { + # files at TI_SimpleLink folder + echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]true" + + Write-host "##[command] Building TI SimpleLink targets" + } + + if( ($files.where{$_.Contains('targets/AzureRTOS')}).Count -gt 0) + { + # files at AzureRTOS folder + echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]true" + + Write-host "##[command] Building Azure RTOS targets" + } + + if( + (($files.where{$_.Contains('targets/netcore/nanoFramework.nanoCLR')}).Count -gt 0) -Or + (($files.where{$_.Contains('targets/netcore/nanoCLR.sln')}).Count -gt 0) -Or + (($files.where{$_.Contains('targets/win32')}).Count -gt 0) + ) + { + # files at win32 or netcore folders + echo "##vso[task.setvariable variable=BUILD_WIN32;isOutput=true]true" + + Write-host "##[command] Building nanoCLR target" + } + + if( + (($files.where{$_.Contains('targets/netcore/nanoFramework.nanoCLR.CLI')}).Count -gt 0) -Or + (($files.where{$_.Contains('targets/netcore/nanoCLR.sln')}).Count -gt 0) -Or + (($files.where{$_.Contains('targets/netcore/nanoFramework.nanoCLR.Host')}).Count -gt 0) + ) + { + # files at nanoCLR CLI or Host folders + echo "##vso[task.setvariable variable=BUILD_NANOCLR_CLI;isOutput=true]true" + + Write-host "##[command] Building nanoCLR CLI target" + } - # filter removed files - $files = $commit.files.where{$_.status -ne 'removed'} } - # get file names only - $files = $files | % {$_.filename} - - Write-host "##[group] Files changed:" - $files | % { Write-host $_ } - Write-host "##[endgroup]" - - # set default values - echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_FREERTOS;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_WIN32;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_NANOCLR_CLI;isOutput=true]false" - echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]false" - - if( - (($files.where{$_.Contains('/')}).Count -eq 0) -Or - (($files.where{$_.StartsWith('azure-pipelines-templates')}).Count -gt 0) -Or - (($files.where{$_.StartsWith('CMake')}).Count -gt 0) -Or - (($files.where{$_.StartsWith('src')}).Count -gt 0) - ) - { - # files at: - # - repo root - # - azure-pipelines-templates - # - CMake - # - src + name: TargetsToBuild + displayName: Get targets to build - echo "##vso[task.setvariable variable=BUILD_ALL;isOutput=true]true" - - Write-host "##[command] Building ALL targets" - } + - task: DotNetCoreCLI@2 + condition: eq( variables['StartReleaseCandidate'], true ) + displayName: Install NBGV tool + inputs: + command: custom + custom: tool + arguments: install -g nbgv - if( ($files.where{$_.Contains('targets/ChibiOS')}).Count -gt 0) - { - # files at ChibiOS folder - echo "##vso[task.setvariable variable=BUILD_CHIBIOS;isOutput=true]true" + - powershell: | - Write-host "##[command] Building ChibiOS targets" - } + # compute authorization header in format "AUTHORIZATION: basic 'encoded token'" + # 'encoded token' is the Base64 of the string "nfbot:personal-token" + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes("nfbot:$(GitHubToken)")))" - if( ($files.where{$_.Contains('targets/FreeRTOS')}).Count -gt 0) - { - # files at FreeRTOS folder - echo "##vso[task.setvariable variable=BUILD_FREERTOS;isOutput=true]true" + cd "$env:Agent_TempDirectory" > $null - Write-host "##[command] Building FreeRTOS targets" - } + git init "$env:Agent_TempDirectory\repo" + cd repo > $null + git remote add origin "$env:Build_Repository_Uri" + git config --global gc.auto 0 + git config --global user.name nfbot + git config --global user.email nanoframework@outlook.com + git config --global core.autocrlf true + git -c http.extraheader="AUTHORIZATION: $auth" fetch --progress origin - if( ($files.where{$_.Contains('targets/ESP32')}).Count -gt 0) - { - # files at ESP32 folder - echo "##vso[task.setvariable variable=BUILD_ESP32;isOutput=true]true" + git checkout develop - Write-host "##[command] Building ESP32 targets" - } + # prepare release and capture output + $release = nbgv prepare-release - if( ($files.where{$_.Contains('targets/TI_SimpleLink')}).Count -gt 0) - { - # files at TI_SimpleLink folder - echo "##vso[task.setvariable variable=BUILD_TI;isOutput=true]true" + # push all changes to github + git -c http.extraheader="AUTHORIZATION: $auth" push --all origin - Write-host "##[command] Building TI SimpleLink targets" - } + # get release branch name + $branch = $release.Split(' ')[0] - if( ($files.where{$_.Contains('targets/AzureRTOS')}).Count -gt 0) - { - # files at AzureRTOS folder - echo "##vso[task.setvariable variable=BUILD_AZURERTOS;isOutput=true]true" + # start PR for release + $prRequestBody = @{title="Release $branch";body="";head="$branch";base="main"} | ConvertTo-Json + $githubApiEndpoint = "https://api.github.com/repos/$env:Build_Repository_Name/pulls" + [Net.ServicePointManager]::SecurityProtocol = [Net.SecurityProtocolType]::Tls12 - Write-host "##[command] Building Azure RTOS targets" - } + $headers = @{} + $headers.Add("Authorization","$auth") + $headers.Add("Accept","application/vnd.github.symmetra-preview+json") - if( - (($files.where{$_.Contains('targets/netcore/nanoFramework.nanoCLR')}).Count -gt 0) -Or - (($files.where{$_.Contains('targets/netcore/nanoCLR.sln')}).Count -gt 0) -Or - (($files.where{$_.Contains('targets/win32')}).Count -gt 0) - ) + try { - # files at win32 or netcore folders - echo "##vso[task.setvariable variable=BUILD_WIN32;isOutput=true]true" - - Write-host "##[command] Building nanoCLR target" + $result = Invoke-RestMethod -Method Post -UserAgent [Microsoft.PowerShell.Commands.PSUserAgent]::InternetExplorer -Uri $githubApiEndpoint -Header $headers -ContentType "application/json" -Body $prRequestBody + 'Started PR for new release...' | Write-Host -NoNewline + '##[error] OK' | Write-Host -ForegroundColor Green } - - if( - (($files.where{$_.Contains('targets/netcore/nanoFramework.nanoCLR.CLI')}).Count -gt 0) -Or - (($files.where{$_.Contains('targets/netcore/nanoCLR.sln')}).Count -gt 0) -Or - (($files.where{$_.Contains('targets/netcore/nanoFramework.nanoCLR.Host')}).Count -gt 0) - ) + catch { - # files at nanoCLR CLI or Host folders - echo "##vso[task.setvariable variable=BUILD_NANOCLR_CLI;isOutput=true]true" + $result = $_.Exception.Response.GetResponseStream() + $reader = New-Object System.IO.StreamReader($result) + $reader.BaseStream.Position = 0 + $reader.DiscardBufferedData() + $responseBody = $reader.ReadToEnd(); - Write-host "##[command] Building nanoCLR CLI target" + "##[error] Error starting PR: $responseBody" | Write-Host -ForegroundColor Red } - } - - name: TargetsToBuild - displayName: Get targets to build - - - task: DotNetCoreCLI@2 - condition: eq( variables['StartReleaseCandidate'], true ) - displayName: Install NBGV tool - inputs: - command: custom - custom: tool - arguments: install -g nbgv - - - powershell: | - - # compute authorization header in format "AUTHORIZATION: basic 'encoded token'" - # 'encoded token' is the Base64 of the string "nfbot:personal-token" - $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes("nfbot:$(GitHubToken)")))" - - cd "$env:Agent_TempDirectory" > $null - - git init "$env:Agent_TempDirectory\repo" - cd repo > $null - git remote add origin "$env:Build_Repository_Uri" - git config --global gc.auto 0 - git config --global user.name nfbot - git config --global user.email nanoframework@outlook.com - git config --global core.autocrlf true - git -c http.extraheader="AUTHORIZATION: $auth" fetch --progress origin - - git checkout develop - - # prepare release and capture output - $release = nbgv prepare-release - - # push all changes to github - git -c http.extraheader="AUTHORIZATION: $auth" push --all origin - - # get release branch name - $branch = $release.Split(' ')[0] - - # start PR for release - $prRequestBody = @{title="Release $branch";body="";head="$branch";base="main"} | ConvertTo-Json - $githubApiEndpoint = "https://api.github.com/repos/$env:Build_Repository_Name/pulls" - [Net.ServicePointManager]::SecurityProtocol = [Net.SecurityProtocolType]::Tls12 - - $headers = @{} - $headers.Add("Authorization","$auth") - $headers.Add("Accept","application/vnd.github.symmetra-preview+json") - - try - { - $result = Invoke-RestMethod -Method Post -UserAgent [Microsoft.PowerShell.Commands.PSUserAgent]::InternetExplorer -Uri $githubApiEndpoint -Header $headers -ContentType "application/json" -Body $prRequestBody - 'Started PR for new release...' | Write-Host -NoNewline - '##[error] OK' | Write-Host -ForegroundColor Green - } - catch - { - $result = $_.Exception.Response.GetResponseStream() - $reader = New-Object System.IO.StreamReader($result) - $reader.BaseStream.Position = 0 - $reader.DiscardBufferedData() - $responseBody = $reader.ReadToEnd(); - - "##[error] Error starting PR: $responseBody" | Write-Host -ForegroundColor Red - } - - condition: eq( variables['StartReleaseCandidate'], true ) - displayName: NBGV prepare release - -############################## -- job: Check_Code_Style - condition: >- - and( - ne(dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true), - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_CHIBIOS'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ESP32'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_FREERTOS'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_TI'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_AZURERTOS'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_WIN32'], true) - ) - ) - - dependsOn: - - Check_Build_Options - - pool: - vmImage: 'windows-latest' - - steps: - - checkout: self - fetchDepth: 1 - condition: ne(variables['System.PullRequest.PullRequestId'], '') - - - template: azure-pipelines-templates/download-install-llvm.yml - - template: azure-pipelines-templates/check-code-style.yml + condition: eq( variables['StartReleaseCandidate'], true ) + displayName: NBGV prepare release -################ -# STM32 -- job: Build_STM32_targets - condition: >- - or( - and( - succeeded('Check_Code_Style'), - ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_CHIBIOS'], true) - ) - ), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_CHIBIOS__'], 'true') - ) - ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - ST_STM32F429I_DISCOVERY: - TargetBoard: ST_STM32F429I_DISCOVERY - TargetSeries: 'stm32f4xx' - BuildOptions: - NeedsDFU: false - NeedsSRECORD: false - CMakePreset: ST_STM32F429I_DISCOVERY - - ST_STM32F769I_DISCOVERY: - TargetBoard: ST_STM32F769I_DISCOVERY - TargetSeries: 'stm32f7xx' - BuildOptions: - NeedsDFU: false - NeedsSRECORD: true - CMakePreset: ST_STM32F769I_DISCOVERY - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('STM32_1_9_1_versioncounter', 0)] - HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] - TargetPlatform: 'stm32' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/download-srecord.yml - - template: azure-pipelines-templates/download-hexdfu.yml - - template: azure-pipelines-templates/build-chibios-stm32-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-managed-helpers.yml - -################# -# ESP32 targets -- job: Build_ESP32_targets - condition: >- - or( + ############################## + - job: Check_Code_Style + condition: >- and( - succeeded('Check_Code_Style'), - ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + ne(dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true), or( eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ESP32'], true) - ) - ), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_ESP32__'], 'true') + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_CHIBIOS'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ESP32'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_FREERTOS'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_TI'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_AZURERTOS'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_WIN32'], true) ) ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - # there is only a single ESP32 target, but this is already config as a matrix to make it easy to add new ones - strategy: - matrix: - ESP32_PSRAM_REV0: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_PSRAM_REV0 - CMakePreset: ESP32_PSRAM_REV0 - - ESP32_BLE_REV0: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32 - PackageName: ESP32_BLE_REV0 - CMakePreset: ESP32_BLE_REV0 - - ESP_WROVER_KIT: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP_WROVER_KIT - PackageName: ESP_WROVER_KIT - CMakePreset: ESP_WROVER_KIT - - ESP32_LILYGO: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_LILYGO - PackageName: ESP32_LILYGO - CMakePreset: ESP32_LILYGO - - FEATHER_S2: - TargetBoard: ESP32_S2 - TargetSeries: 'esp32_s2' - BuildOptions: - IDF_Target: esp32s2 - TargetName: FEATHER_S2 - PackageName: FEATHER_S2 - CMakePreset: FEATHER_S2 - - ESP32_C3: - TargetBoard: ESP32_C3 - TargetSeries: 'esp32c3' - BuildOptions: - IDF_Target: esp32c3 - TargetName: ESP32_C3 - PackageName: ESP32_C3 - CMakePreset: ESP32_C3 - - ESP32_C6_THREAD: - TargetBoard: ESP32_C6 - TargetSeries: 'esp32c6' - BuildOptions: - IDF_Target: esp32c6 - TargetName: ESP32_C6_THREAD - PackageName: ESP32_C6_THREAD - CMakePreset: ESP32_C6_THREAD - - ESP32_H2_THREAD: - TargetBoard: ESP32_H2 - TargetSeries: 'esp32h2' - BuildOptions: - IDF_Target: esp32h2 - TargetName: ESP32_H2_THREAD - PackageName: ESP32_H2_THREAD - CMakePreset: ESP32_H2_THREAD - - ESP32_S3: - TargetBoard: ESP32_S3 - TargetSeries: 'esp32s3' - BuildOptions: - IDF_Target: esp32s3 - TargetName: ESP32_S3 - PackageName: ESP32_S3 - CMakePreset: ESP32_S3 - - ESP32_S3_ALL: - TargetBoard: ESP32_S3 - TargetSeries: 'esp32s3' - BuildOptions: - IDF_Target: esp32s3 - TargetName: ESP32_S3_ALL - PackageName: ESP32_S3_ALL - CMakePreset: ESP32_S3_ALL - - ESP32_ETHERNET_KIT_1.2: - TargetBoard: ESP32 - TargetSeries: 'esp32' - BuildOptions: - IDF_Target: esp32 - TargetName: ESP32_ETHERNET_KIT_1.2 - PackageName: ESP32_ETHERNET_KIT_1.2 - CMakePreset: ESP32_ETHERNET_KIT_1.2 - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('ESP32_1_9_1_versioncounter', 0)] - IDF_PATH: 'D:/a/1/s/esp-idf' - PIP_CACHE_DIR: $(Pipeline.Workspace)/.pip - TargetPlatform: 'esp32' - - steps: - - checkout: self - - checkout: esp32_idf - fetchDepth: 1 - - - template: azure-pipelines-templates/build-preparations.yml - parameters: - repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' - - template: azure-pipelines-templates/nb-gitversioning.yml - parameters: - repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' - - template: azure-pipelines-templates/download-install-esp32-build-components.yml - - template: azure-pipelines-templates/download-install-ninja.yml - parameters: - repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' - - template: azure-pipelines-templates/build-espressif-esp32-targets.yml - - - task: CopyFiles@2 - condition: succeeded() - displayName: Copying bootloader - inputs: - sourceFolder: '$(Build.SourcesDirectory)\nf-interpreter\build\bootloader' - Contents: | - bootloader.bin - TargetFolder: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' - flattenFolders: true - ignoreMakeDirErrors: true - - - template: azure-pipelines-templates/copy-sdkconfig.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - parameters: - buildDirectory: '$(Build.SourcesDirectory)\nf-interpreter\build' - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/publish-sdkconfig.yml - -################# -# NXP -- job: Build_NXP_targets - condition: >- - or( - and( - succeeded('Check_Code_Style'), - ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_FREERTOS'], true) - ) - ), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_NXP__'], 'true') + + dependsOn: + - Check_Build_Options + + pool: + vmImage: "windows-latest" + + steps: + - checkout: self + fetchDepth: 1 + condition: ne(variables['System.PullRequest.PullRequestId'], '') + + - template: azure-pipelines-templates/download-install-llvm.yml + - template: azure-pipelines-templates/check-code-style.yml + + ################ + # STM32 + - job: Build_STM32_targets + condition: >- + or( + and( + succeeded('Check_Code_Style'), + ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_CHIBIOS'], true) + ) + ), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_CHIBIOS__'], 'true') + ) ) ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - NXP_MIMXRT1060_EVK: - TargetBoard: NXP_MIMXRT1060_EVK - TargetSeries: 'imxrt10xx' - BuildOptions: - NeedsSRECORD: true - CMakePreset: NXP_MIMXRT1060_EVK - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('NXP_1_9_1_versioncounter', 0)] - GIT_LFS_SKIP_SMUDGE: 1 - TargetPlatform: 'freertos' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/download-srecord.yml - - template: azure-pipelines-templates/build-freertos-nxp-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-managed-helpers.yml - -################# -# TI SimpleLink -- job: Build_TI_SimpleLink_targets - condition: >- - or( - and( - succeeded('Check_Code_Style'), - ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_TI'], true) - ) - ), - and( + + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + ST_STM32F429I_DISCOVERY: + TargetBoard: ST_STM32F429I_DISCOVERY + TargetSeries: "stm32f4xx" + BuildOptions: + NeedsDFU: false + NeedsSRECORD: false + CMakePreset: ST_STM32F429I_DISCOVERY + + ST_STM32F769I_DISCOVERY: + TargetBoard: ST_STM32F769I_DISCOVERY + TargetSeries: "stm32f7xx" + BuildOptions: + NeedsDFU: false + NeedsSRECORD: true + CMakePreset: ST_STM32F769I_DISCOVERY + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('STM32_1_9_1_versioncounter', 0)] + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + TargetPlatform: "stm32" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/download-srecord.yml + - template: azure-pipelines-templates/download-hexdfu.yml + - template: azure-pipelines-templates/build-chibios-stm32-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + + ################# + # ESP32 targets + - job: Build_ESP32_targets + condition: >- + or( + and( + succeeded('Check_Code_Style'), + ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ESP32'], true) + ) + ), + and( eq(variables['Build.Reason'], 'Manual'), or( eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_TI__'], 'true') + eq(variables['BUILD_ESP32__'], 'true') ) - ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - # disabled: waiting to update SDK to latest version with Sys Config - # TI_CC3220SF_LAUNCHXL: - # TargetBoard: TI_CC3220SF_LAUNCHXL - # TargetSeries: 'cc32xx' - # BuildOptions: >- - # -DTARGET_SERIES=CC32xx - # -DRTOS=TI_SimpleLink - # -DSUPPORT_ANY_BASE_CONVERSION=OFF - # -DNF_FEATURE_DEBUGGER=ON - # -DNF_FEATURE_RTC=ON - # -DNF_FEATURE_WATCHDOG=OFF - # -DNF_FEATURE_HAS_CONFIG_BLOCK=ON - # -DAPI_System.Device.Gpio=ON - # -DAPI_System.Device.Spi=ON - # -DAPI_System.Device.I2c=ON - # -DAPI_System.Device.Pwm=ON - # -DAPI_System.Device.Adc=ON - # -DAPI_System.Net=ON - # -DAPI_nanoFramework.System.Collections=ON - # -DAPI_nanoFramework.System.Text=ON - - TI_CC1352R1_LAUNCHXL_915: - TargetBoard: TI_CC1352R1_LAUNCHXL - PackageName: TI_CC1352R1_LAUNCHXL_915 - TargetSeries: 'CC13X2' - BuildOptions: >- - -DRADIO_FREQUENCY=915 - CMakePreset: TI_CC1352R1_LAUNCHXL - - variables: - DOTNET_NOLOGO: true - # creates a counter and assigns it to the revision variable - REVISION: $[counter('TI_1_9_1_versioncounter', 0)] - HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] - TargetPlatform: 'ti_simplelink' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/build-ti-simplelink-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml - -################# -# Azure RTOS -- job: Build_Azure_RTOS_targets - condition: >- - or( - and( - succeeded('Check_Code_Style'), - ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_AZURERTOS'], true) - ) - ), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_AZURERTOS__'], 'true') ) ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - strategy: - matrix: - # ST_B_L475E_IOT01A: - # TargetBoard: ST_B_L475E_IOT01A - # TargetSeries: 'stm32l4xx' - # BuildOptions: - # NeedsDFU: true - # NeedsSRECORD: false - # CMakePreset: ST_B_L475E_IOT01A - - # ORGPAL_PALTHREE: - # TargetBoard: ORGPAL_PALTHREE - # TargetSeries: 'stm32f7xx' - # BuildOptions: - # NeedsDFU: true - # NeedsSRECORD: false - # CMakePreset: ORGPAL_PALTHREE - - SL_STK3701A: - TargetBoard: SL_STK3701A - TargetSeries: 'efm32gg11' - BuildOptions: - NeedsDFU: false - NeedsSRECORD: false - CMakePreset: SL_STK3701A - - variables: - # creates a counter and assigns it to the revision variable - REVISION: $[counter('AZURERTOS_1_9_1_versioncounter', 0)] - HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] - TargetPlatform: 'azure_rtos' - - steps: - - template: azure-pipelines-templates/build-preparations.yml - - template: azure-pipelines-templates/nb-gitversioning.yml - - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml - - template: azure-pipelines-templates/download-install-ninja.yml - - template: azure-pipelines-templates/download-hexdfu.yml - - template: azure-pipelines-templates/download-srecord.yml - - template: azure-pipelines-templates/build-azurertos-targets.yml - - template: azure-pipelines-templates/pack-publish-artifacts.yml - - template: azure-pipelines-templates/publish-cloudsmith.yml - - template: azure-pipelines-templates/pack-publish-managed-helpers.yml - -################# -# WIN32 executable -- job: Build_WIN32_nanoCLR - condition: >- - or( - and( - succeeded('Check_Code_Style'), - ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), - or( - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_WIN32'], true) - ) - ), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_WINDOWS_NANOCLR__'], 'true') + + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + # there is only a single ESP32 target, but this is already config as a matrix to make it easy to add new ones + strategy: + matrix: + ESP32_PSRAM_REV0: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_PSRAM_REV0 + CMakePreset: ESP32_PSRAM_REV0 + + ESP32_BLE_REV0: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32 + PackageName: ESP32_BLE_REV0 + CMakePreset: ESP32_BLE_REV0 + + ESP_WROVER_KIT: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP_WROVER_KIT + PackageName: ESP_WROVER_KIT + CMakePreset: ESP_WROVER_KIT + + ESP32_LILYGO: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_LILYGO + PackageName: ESP32_LILYGO + CMakePreset: ESP32_LILYGO + + FEATHER_S2: + TargetBoard: ESP32_S2 + TargetSeries: "esp32_s2" + BuildOptions: + IDF_Target: esp32s2 + TargetName: FEATHER_S2 + PackageName: FEATHER_S2 + CMakePreset: FEATHER_S2 + + ESP32_C3: + TargetBoard: ESP32_C3 + TargetSeries: "esp32c3" + BuildOptions: + IDF_Target: esp32c3 + TargetName: ESP32_C3 + PackageName: ESP32_C3 + CMakePreset: ESP32_C3 + + ESP32_C6_THREAD: + TargetBoard: ESP32_C6 + TargetSeries: "esp32c6" + BuildOptions: + IDF_Target: esp32c6 + TargetName: ESP32_C6_THREAD + PackageName: ESP32_C6_THREAD + CMakePreset: ESP32_C6_THREAD + + ESP32_H2_THREAD: + TargetBoard: ESP32_H2 + TargetSeries: "esp32h2" + BuildOptions: + IDF_Target: esp32h2 + TargetName: ESP32_H2_THREAD + PackageName: ESP32_H2_THREAD + CMakePreset: ESP32_H2_THREAD + + ESP32_S3: + TargetBoard: ESP32_S3 + TargetSeries: "esp32s3" + BuildOptions: + IDF_Target: esp32s3 + TargetName: ESP32_S3 + PackageName: ESP32_S3 + CMakePreset: ESP32_S3 + + ESP32_S3_ALL: + TargetBoard: ESP32_S3 + TargetSeries: "esp32s3" + BuildOptions: + IDF_Target: esp32s3 + TargetName: ESP32_S3_ALL + PackageName: ESP32_S3_ALL + CMakePreset: ESP32_S3_ALL + + ESP32_ETHERNET_KIT_1.2: + TargetBoard: ESP32 + TargetSeries: "esp32" + BuildOptions: + IDF_Target: esp32 + TargetName: ESP32_ETHERNET_KIT_1.2 + PackageName: ESP32_ETHERNET_KIT_1.2 + CMakePreset: ESP32_ETHERNET_KIT_1.2 + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ESP32_1_9_1_versioncounter', 0)] + IDF_PATH: "D:/a/1/s/esp-idf" + PIP_CACHE_DIR: $(Pipeline.Workspace)/.pip + TargetPlatform: "esp32" + + steps: + - checkout: self + - checkout: esp32_idf + fetchDepth: 1 + + - template: azure-pipelines-templates/build-preparations.yml + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/nb-gitversioning.yml + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/download-install-esp32-build-components.yml + - template: azure-pipelines-templates/download-install-ninja.yml + parameters: + repoDirectory: '$(Build.SourcesDirectory)\nf-interpreter' + - template: azure-pipelines-templates/build-espressif-esp32-targets.yml + + - task: CopyFiles@2 + condition: succeeded() + displayName: Copying bootloader + inputs: + sourceFolder: '$(Build.SourcesDirectory)\nf-interpreter\build\bootloader' + Contents: | + bootloader.bin + TargetFolder: '$(Build.ArtifactStagingDirectory)\$(TargetPublishName)' + flattenFolders: true + ignoreMakeDirErrors: true + + - template: azure-pipelines-templates/copy-sdkconfig.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + parameters: + buildDirectory: '$(Build.SourcesDirectory)\nf-interpreter\build' + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/publish-sdkconfig.yml + + ################# + # NXP + - job: Build_NXP_targets + condition: >- + or( + and( + succeeded('Check_Code_Style'), + ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_FREERTOS'], true) + ) + ), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_NXP__'], 'true') + ) ) ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - variables: - - group: sign-client-credentials - - name: DOTNET_NOLOGO - value: true - # creates a counter and assigns it to the revision variable - - name: REVISION - value: $[counter('WIN32_1_9_1_versioncounter', 0)] - - steps: - - template: azure-pipelines-templates/nb-gitversioning.yml - - - task: PowerShell@2 - displayName: Store package version - inputs: - targetType: 'inline' - script: | - Write-Host "$("##vso[task.setvariable variable=WINCLR_PACKAGE_VERSION]")$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER)" - Write-Host "$("##vso[task.setvariable variable=WINCLR_AssemblyInformationalVersion]")$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER)$(NBGV_BuildMetadataFragment)" - - - template: azure-pipelines-templates/install-nuget.yml@templates - - - task: DotNetCoreCLI@2 - displayName: Restore NuGet packages - inputs: - command: restore - restoreArguments: '--locked-mode' - verbosityRestore: minimal - projects: targets\netcore\nanoCLR.sln - feedsToUse: select - includeNuGetOrg: true - - - task: VSBuild@1 - displayName: Build WIN32 EXE target - inputs: - solution: 'targets\win32\nanoCLR.sln' - platform: 'x86' - maximumCpuCount: true - msbuildArgs: '/p:PublicRelease=true' - configuration: 'Release' - - - task: VSBuild@1 - displayName: Build WIN DLL target - inputs: - solution: 'targets\netcore\nanoCLR.sln' - platform: 'Any CPU' - maximumCpuCount: true - msbuildArgs: '/p:PublicRelease=true' - configuration: 'Release' - - - task: DotNetCoreCLI@2 - displayName: Install Sign Client CLI + + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + NXP_MIMXRT1060_EVK: + TargetBoard: NXP_MIMXRT1060_EVK + TargetSeries: "imxrt10xx" + BuildOptions: + NeedsSRECORD: true + CMakePreset: NXP_MIMXRT1060_EVK + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('NXP_1_9_1_versioncounter', 0)] + GIT_LFS_SKIP_SMUDGE: 1 + TargetPlatform: "freertos" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/download-srecord.yml + - template: azure-pipelines-templates/build-freertos-nxp-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + + ################# + # TI SimpleLink + - job: Build_TI_SimpleLink_targets condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], '') + or( + and( + succeeded('Check_Code_Style'), + ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_TI'], true) + ) + ), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_TI__'], 'true') + ) + ) ) - inputs: - command: custom - custom: tool - arguments: install --tool-path . sign --version 0.9.1-beta.23530.1 - - - pwsh: | - .\sign code azure-key-vault ` - "**/nanoFramework.nanoCLR.*" ` - --base-directory "$(Build.Repository.LocalPath)\build\bin\Release" ` - --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` - --publisher-name ".NET nanoFramework" ` - --description "nanoFramework.nanoCLR" ` - --description-url "https://github.com/$env:Build_Repository_Name" ` - --azure-key-vault-tenant-id "$(SignTenantId)" ` - --azure-key-vault-client-id "$(SignClientId)" ` - --azure-key-vault-client-secret "$(SignClientSecret)" ` - --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` - --azure-key-vault-url "$(SignKeyVaultUrl)" ` - --timestamp-url http://timestamp.digicert.com - displayName: Sign nanoCLR assemblies - continueOnError: true + + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + # disabled: waiting to update SDK to latest version with Sys Config + # TI_CC3220SF_LAUNCHXL: + # TargetBoard: TI_CC3220SF_LAUNCHXL + # TargetSeries: 'cc32xx' + # BuildOptions: >- + # -DTARGET_SERIES=CC32xx + # -DRTOS=TI_SimpleLink + # -DSUPPORT_ANY_BASE_CONVERSION=OFF + # -DNF_FEATURE_DEBUGGER=ON + # -DNF_FEATURE_RTC=ON + # -DNF_FEATURE_WATCHDOG=OFF + # -DNF_FEATURE_HAS_CONFIG_BLOCK=ON + # -DAPI_System.Device.Gpio=ON + # -DAPI_System.Device.Spi=ON + # -DAPI_System.Device.I2c=ON + # -DAPI_System.Device.Pwm=ON + # -DAPI_System.Device.Adc=ON + # -DAPI_System.Net=ON + # -DAPI_nanoFramework.System.Collections=ON + # -DAPI_nanoFramework.System.Text=ON + + TI_CC1352R1_LAUNCHXL_915: + TargetBoard: TI_CC1352R1_LAUNCHXL + PackageName: TI_CC1352R1_LAUNCHXL_915 + TargetSeries: "CC13X2" + BuildOptions: >- + -DRADIO_FREQUENCY=915 + CMakePreset: TI_CC1352R1_LAUNCHXL + + variables: + DOTNET_NOLOGO: true + # creates a counter and assigns it to the revision variable + REVISION: $[counter('TI_1_9_1_versioncounter', 0)] + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + TargetPlatform: "ti_simplelink" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/build-ti-simplelink-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml + + ################# + # Azure RTOS + - job: Build_Azure_RTOS_targets condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], '') + or( + and( + succeeded('Check_Code_Style'), + ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_AZURERTOS'], true) + ) + ), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_AZURERTOS__'], 'true') + ) + ) ) - - task: NuGetCommand@2 - condition: succeeded() - displayName: Pack nanoCLR WIN32 - inputs: - command: 'custom' - arguments: 'pack targets\win32\nanoFramework.nanoCLR.Win32.nuspec -Version $(NBGV_NuGetPackageVersion)' - - - task: CopyFiles@2 - condition: succeeded() - displayName: Collecting NuGet packages - inputs: - sourceFolder: $(Build.SourcesDirectory) - Contents: | - **\nanoFramework.nanoCLR.Win32*.nupkg - TargetFolder: '$(Build.ArtifactStagingDirectory)' - flattenFolders: true - ignoreMakeDirErrors: true - - - task: CopyFiles@2 - condition: succeeded() - displayName: Adding nanoCLR WIN32 to deployable artifacts - inputs: - sourceFolder: $(Build.SourcesDirectory) - Contents: | - **\nanoFramework.nanoCLR.exe - TargetFolder: '$(Build.ArtifactStagingDirectory)\WIN32_nanoCLR' - flattenFolders: true - ignoreMakeDirErrors: true - - - task: CopyFiles@2 - condition: succeeded() - displayName: Adding nanoCLR DLL to deployable artifacts - inputs: - sourceFolder: $(Build.SourcesDirectory) - Contents: | - **\nanoFramework.nanoCLR.dll - TargetFolder: '$(Build.ArtifactStagingDirectory)\WIN_DLL_nanoCLR' - flattenFolders: true - ignoreMakeDirErrors: true - - - pwsh: | - .\sign code azure-key-vault ` - "**/*.nupkg" ` - --base-directory "$(Build.ArtifactStagingDirectory)" ` - --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` - --publisher-name ".NET nanoFramework" ` - --description "nanoFramework.nanoCLR NuGets" ` - --description-url "https://github.com/$env:Build_Repository_Name" ` - --azure-key-vault-tenant-id "$(SignTenantId)" ` - --azure-key-vault-client-id "$(SignClientId)" ` - --azure-key-vault-client-secret "$(SignClientSecret)" ` - --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` - --azure-key-vault-url "$(SignKeyVaultUrl)" ` - --timestamp-url http://timestamp.digicert.com - displayName: Sign packages - continueOnError: true + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + strategy: + matrix: + # ST_B_L475E_IOT01A: + # TargetBoard: ST_B_L475E_IOT01A + # TargetSeries: 'stm32l4xx' + # BuildOptions: + # NeedsDFU: true + # NeedsSRECORD: false + # CMakePreset: ST_B_L475E_IOT01A + + # ORGPAL_PALTHREE: + # TargetBoard: ORGPAL_PALTHREE + # TargetSeries: 'stm32f7xx' + # BuildOptions: + # NeedsDFU: true + # NeedsSRECORD: false + # CMakePreset: ORGPAL_PALTHREE + + SL_STK3701A: + TargetBoard: SL_STK3701A + TargetSeries: "efm32gg11" + BuildOptions: + NeedsDFU: false + NeedsSRECORD: false + CMakePreset: SL_STK3701A + + variables: + # creates a counter and assigns it to the revision variable + REVISION: $[counter('AZURERTOS_1_9_1_versioncounter', 0)] + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + TargetPlatform: "azure_rtos" + + steps: + - template: azure-pipelines-templates/build-preparations.yml + - template: azure-pipelines-templates/nb-gitversioning.yml + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + - template: azure-pipelines-templates/download-install-ninja.yml + - template: azure-pipelines-templates/download-hexdfu.yml + - template: azure-pipelines-templates/download-srecord.yml + - template: azure-pipelines-templates/build-azurertos-targets.yml + - template: azure-pipelines-templates/pack-publish-artifacts.yml + - template: azure-pipelines-templates/publish-cloudsmith.yml + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + + ################# + # WIN32 executable + - job: Build_WIN32_nanoCLR condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], '') + or( + and( + succeeded('Check_Code_Style'), + ne( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_WIN32'], true) + ) + ), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_WINDOWS_NANOCLR__'], 'true') + ) + ) ) - - # publish artifacts - - task: PublishPipelineArtifact@1 - condition: succeeded() - displayName: Publish deployables artifacts - inputs: - targetPath: '$(Build.ArtifactStagingDirectory)' - artifactName: nanoclr_win32 - artifactType: pipeline - - # push NuGet packages to Azure Artifacts feed (always happens when building from main, except on PR builds) - - task: NuGetCommand@2 + + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + variables: + - group: sign-client-credentials + - name: DOTNET_NOLOGO + value: true + # creates a counter and assigns it to the revision variable + - name: REVISION + value: $[counter('WIN32_1_9_1_versioncounter', 0)] + + steps: + - template: azure-pipelines-templates/nb-gitversioning.yml + + - task: PowerShell@2 + displayName: Store package version + inputs: + targetType: "inline" + script: | + Write-Host "$("##vso[task.setvariable variable=WINCLR_PACKAGE_VERSION]")$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER)" + Write-Host "$("##vso[task.setvariable variable=WINCLR_AssemblyInformationalVersion]")$(NBGV_VersionMajor).$(NBGV_VersionMinor).$(NBGV_BuildNumber).$(TARGET_BUILD_COUNTER)$(NBGV_BuildMetadataFragment)" + + - template: azure-pipelines-templates/install-nuget.yml@templates + + - task: DotNetCoreCLI@2 + displayName: Restore NuGet packages + inputs: + command: restore + restoreArguments: "--locked-mode" + verbosityRestore: minimal + projects: targets\netcore\nanoCLR.sln + feedsToUse: select + includeNuGetOrg: true + + - task: VSBuild@1 + displayName: Build WIN32 EXE target + inputs: + solution: 'targets\win32\nanoCLR.sln' + platform: "x86" + maximumCpuCount: true + msbuildArgs: "/p:PublicRelease=true" + configuration: "Release" + + - task: VSBuild@1 + displayName: Build WIN DLL target + inputs: + solution: 'targets\netcore\nanoCLR.sln' + platform: "Any CPU" + maximumCpuCount: true + msbuildArgs: "/p:PublicRelease=true" + configuration: "Release" + + - task: DotNetCoreCLI@2 + displayName: Install Sign Client CLI + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], '') + ) + inputs: + command: custom + custom: tool + arguments: install --tool-path . sign --version 0.9.1-beta.23530.1 + + - pwsh: | + .\sign code azure-key-vault ` + "**/nanoFramework.nanoCLR.*" ` + --base-directory "$(Build.Repository.LocalPath)\build\bin\Release" ` + --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` + --publisher-name ".NET nanoFramework" ` + --description "nanoFramework.nanoCLR" ` + --description-url "https://github.com/$env:Build_Repository_Name" ` + --azure-key-vault-tenant-id "$(SignTenantId)" ` + --azure-key-vault-client-id "$(SignClientId)" ` + --azure-key-vault-client-secret "$(SignClientSecret)" ` + --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` + --azure-key-vault-url "$(SignKeyVaultUrl)" ` + --timestamp-url http://timestamp.digicert.com + displayName: Sign nanoCLR assemblies + continueOnError: true + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], '') + ) + + - task: NuGetCommand@2 + condition: succeeded() + displayName: Pack nanoCLR WIN32 + inputs: + command: "custom" + arguments: 'pack targets\win32\nanoFramework.nanoCLR.Win32.nuspec -Version $(NBGV_NuGetPackageVersion)' + + - task: CopyFiles@2 + condition: succeeded() + displayName: Collecting NuGet packages + inputs: + sourceFolder: $(Build.SourcesDirectory) + Contents: | + **\nanoFramework.nanoCLR.Win32*.nupkg + TargetFolder: "$(Build.ArtifactStagingDirectory)" + flattenFolders: true + ignoreMakeDirErrors: true + + - task: CopyFiles@2 + condition: succeeded() + displayName: Adding nanoCLR WIN32 to deployable artifacts + inputs: + sourceFolder: $(Build.SourcesDirectory) + Contents: | + **\nanoFramework.nanoCLR.exe + TargetFolder: '$(Build.ArtifactStagingDirectory)\WIN32_nanoCLR' + flattenFolders: true + ignoreMakeDirErrors: true + + - task: CopyFiles@2 + condition: succeeded() + displayName: Adding nanoCLR DLL to deployable artifacts + inputs: + sourceFolder: $(Build.SourcesDirectory) + Contents: | + **\nanoFramework.nanoCLR.dll + TargetFolder: '$(Build.ArtifactStagingDirectory)\WIN_DLL_nanoCLR' + flattenFolders: true + ignoreMakeDirErrors: true + + - pwsh: | + .\sign code azure-key-vault ` + "**/*.nupkg" ` + --base-directory "$(Build.ArtifactStagingDirectory)" ` + --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` + --publisher-name ".NET nanoFramework" ` + --description "nanoFramework.nanoCLR NuGets" ` + --description-url "https://github.com/$env:Build_Repository_Name" ` + --azure-key-vault-tenant-id "$(SignTenantId)" ` + --azure-key-vault-client-id "$(SignClientId)" ` + --azure-key-vault-client-secret "$(SignClientSecret)" ` + --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` + --azure-key-vault-url "$(SignKeyVaultUrl)" ` + --timestamp-url http://timestamp.digicert.com + displayName: Sign packages + continueOnError: true + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], '') + ) + + # publish artifacts + - task: PublishPipelineArtifact@1 + condition: succeeded() + displayName: Publish deployables artifacts + inputs: + targetPath: "$(Build.ArtifactStagingDirectory)" + artifactName: nanoclr_win32 + artifactType: pipeline + + # push NuGet packages to Azure Artifacts feed (always happens when building from main, except on PR builds) + - task: NuGetCommand@2 + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + or( + eq(variables['ForceUpload'], true), + eq(variables['Build.SourceBranchName'], 'main') + ) + ) + continueOnError: true + displayName: Push NuGet packages to Azure Artifacts + inputs: + command: push + nuGetFeedType: external + packagesToPush: "$(Build.ArtifactStagingDirectory)/*.nupkg" + publishFeedCredentials: "AzureArtifacts-nf-interpreter" + allowPackageConflicts: true + + # push NuGet packages to NuGet (always happens when building from main, except on PR builds) + - task: NuGetCommand@2 + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + or( + eq(variables['ForceUpload'], true), + eq(variables['Build.SourceBranchName'], 'main') + ) + ) + continueOnError: true + displayName: Push NuGet packages to NuGet + inputs: + command: push + nuGetFeedType: external + allowPackageConflicts: true + packagesToPush: "$(Build.ArtifactStagingDirectory)/*.nupkg" + publishFeedCredentials: "NuGet-nf-interpreter" + + - template: azure-pipelines-templates/publish-nanoclr.yml + + ################# + # nanoCLR CLI tool + - job: Build_nanoCLR_CLI condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), - or( - eq(variables['ForceUpload'], true), - eq(variables['Build.SourceBranchName'], 'main') + or( + and( + succeeded('Check_Code_Style'), + ne(dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true), + or( + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_NANOCLR_CLI'], true) + ) + ), + and( + eq(variables['Build.Reason'], 'Manual'), + or( + eq(variables['BUILD_ALL__'], 'true'), + eq(variables['BUILD_NANOCLR_CLI__'], 'true') + ) ) - ) - continueOnError: true - displayName: Push NuGet packages to Azure Artifacts - inputs: - command: push - nuGetFeedType: external - packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' - publishFeedCredentials: 'AzureArtifacts-nf-interpreter' - allowPackageConflicts: true - - # push NuGet packages to NuGet (always happens when building from main, except on PR builds) - - task: NuGetCommand@2 + ) + + dependsOn: + - Check_Build_Options + - Check_Code_Style + + pool: + vmImage: "windows-latest" + + variables: + - group: sign-client-credentials + - name: DOTNET_NOLOGO + value: true + + steps: + - template: azure-pipelines-templates/nb-gitversioning.yml + + - template: azure-pipelines-templates/install-nuget.yml@templates + + - task: DotNetCoreCLI@2 + displayName: Restore NuGet packages + inputs: + command: restore + verbosityRestore: minimal + projects: targets\netcore\nanoCLR.sln + feedsToUse: select + includeNuGetOrg: true + + - task: VSBuild@1 + displayName: Build .NET tool + condition: succeeded() + inputs: + solution: 'targets\netcore\nanoCLR.sln' + platform: "Any CPU" + maximumCpuCount: true + msbuildArgs: "/p:PublicRelease=true" + configuration: "Release" + + - task: DotNetCoreCLI@2 + displayName: Install Sign Client CLI + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], '') + ) + inputs: + command: custom + custom: tool + arguments: install --tool-path . sign --version 0.9.1-beta.23530.1 + + - pwsh: | + .\sign code azure-key-vault ` + "**/nanoFramework.nanoCLR.*" ` + --base-directory "$(Build.Repository.LocalPath)\build\bin\Release" ` + --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` + --publisher-name ".NET nanoFramework" ` + --description "nanoFramework.nanoCLR.CLI" ` + --description-url "https://github.com/$env:Build_Repository_Name" ` + --azure-key-vault-tenant-id "$(SignTenantId)" ` + --azure-key-vault-client-id "$(SignClientId)" ` + --azure-key-vault-client-secret "$(SignClientSecret)" ` + --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` + --azure-key-vault-url "$(SignKeyVaultUrl)" ` + --timestamp-url http://timestamp.digicert.com + displayName: Sign nanoCLR assemblies + continueOnError: true + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], '') + ) + + - task: MSBuild@1 + condition: succeeded() + displayName: Pack nanoCLR CLI + inputs: + solution: 'targets\netcore\nanoFramework.nanoCLR.CLI\nanoFramework.nanoCLR.CLI.csproj' + platform: "Any CPU" + msbuildArguments: "/p:PublicRelease=true /t:pack /p:PackageOutputPath=$(Build.ArtifactStagingDirectory) " + configuration: "Release" + maximumCpuCount: true + + - pwsh: | + .\sign code azure-key-vault ` + "**/*.nupkg" ` + --base-directory "$(Build.ArtifactStagingDirectory)" ` + --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` + --publisher-name ".NET nanoFramework" ` + --description "nanoFramework.nanoCLR.CLI NuGet" ` + --description-url "https://github.com/$env:Build_Repository_Name" ` + --azure-key-vault-tenant-id "$(SignTenantId)" ` + --azure-key-vault-client-id "$(SignClientId)" ` + --azure-key-vault-client-secret "$(SignClientSecret)" ` + --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` + --azure-key-vault-url "$(SignKeyVaultUrl)" ` + --timestamp-url http://timestamp.digicert.com + displayName: Sign packages + continueOnError: true + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], '') + ) + + - task: CopyFiles@2 + condition: succeeded() + displayName: Copy nanoclr + inputs: + SourceFolder: '$(Build.Repository.LocalPath)\build\bin\Release' + Contents: "nanoFramework.nanoCLR.dll" + TargetFolder: "$(Build.ArtifactStagingDirectory)/nanoclr" + + - task: PublishPipelineArtifact@1 + condition: succeeded() + displayName: Publish nanoclr + inputs: + targetPath: "$(Build.ArtifactStagingDirectory)/nanoclr" + artifactName: nanoclr_cli + artifactType: pipeline + + # push NuGet packages to Azure Artifacts feed (always happens when building from main, except on PR builds) + - task: NuGetCommand@2 + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + or( + eq(variables['ForceUpload'], true), + eq(variables['Build.SourceBranchName'], 'main') + ) + ) + continueOnError: true + displayName: Push NuGet packages to Azure Artifacts + inputs: + command: push + nuGetFeedType: external + packagesToPush: "$(Build.ArtifactStagingDirectory)/*.nupkg" + publishFeedCredentials: "AzureArtifacts-nf-interpreter" + allowPackageConflicts: true + + # push NuGet packages to NuGet (always happens when building from main, except on PR builds) + - task: NuGetCommand@2 + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + or( + eq(variables['ForceUpload'], true), + eq(variables['Build.SourceBranchName'], 'main') + ) + ) + continueOnError: true + displayName: Push NuGet packages to NuGet + inputs: + command: push + nuGetFeedType: external + allowPackageConflicts: true + packagesToPush: "$(Build.ArtifactStagingDirectory)/*.nupkg" + publishFeedCredentials: "NuGet-nf-interpreter" + + ######################### + # Run mscorlib Unit Tests + + - job: Run_UnitTests_mscorlib condition: >- and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), - or( - eq(variables['ForceUpload'], true), - eq(variables['Build.SourceBranchName'], 'main') - ) - ) - continueOnError: true - displayName: Push NuGet packages to NuGet - inputs: - command: push - nuGetFeedType: external - allowPackageConflicts: true - packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' - publishFeedCredentials: 'NuGet-nf-interpreter' - - - template: azure-pipelines-templates/publish-nanoclr.yml - -################# -# nanoCLR CLI tool -- job: Build_nanoCLR_CLI - condition: >- - or( - and( - succeeded('Check_Code_Style'), + succeeded('Build_nanoCLR_CLI'), ne(dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true), or( + eq(variables['BUILD_NANOCLR_CLI__'], true), eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_NANOCLR_CLI'], true) - ) - ), - and( - eq(variables['Build.Reason'], 'Manual'), - or( - eq(variables['BUILD_ALL__'], 'true'), - eq(variables['BUILD_NANOCLR_CLI__'], 'true') + eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_NANOCLR_CLI'], true), + eq(dependencies.Check_Build_Options.outputs['BuildOptions.RUN_MSCORLIB_TESTS'], true) ) ) - ) - - dependsOn: - - Check_Build_Options - - Check_Code_Style - - pool: - vmImage: 'windows-latest' - - variables: - - group: sign-client-credentials - - name: DOTNET_NOLOGO - value: true - - steps: - - template: azure-pipelines-templates/nb-gitversioning.yml - - - template: azure-pipelines-templates/install-nuget.yml@templates - - - task: DotNetCoreCLI@2 - displayName: Restore NuGet packages - inputs: - command: restore - verbosityRestore: minimal - projects: targets\netcore\nanoCLR.sln - feedsToUse: select - includeNuGetOrg: true - - - task: VSBuild@1 - displayName: Build .NET tool - condition: succeeded() - inputs: - solution: 'targets\netcore\nanoCLR.sln' - platform: 'Any CPU' - maximumCpuCount: true - msbuildArgs: '/p:PublicRelease=true' - configuration: 'Release' - - - task: DotNetCoreCLI@2 - displayName: Install Sign Client CLI - condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], '') - ) - inputs: - command: custom - custom: tool - arguments: install --tool-path . sign --version 0.9.1-beta.23530.1 - - - pwsh: | - .\sign code azure-key-vault ` - "**/nanoFramework.nanoCLR.*" ` - --base-directory "$(Build.Repository.LocalPath)\build\bin\Release" ` - --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` - --publisher-name ".NET nanoFramework" ` - --description "nanoFramework.nanoCLR.CLI" ` - --description-url "https://github.com/$env:Build_Repository_Name" ` - --azure-key-vault-tenant-id "$(SignTenantId)" ` - --azure-key-vault-client-id "$(SignClientId)" ` - --azure-key-vault-client-secret "$(SignClientSecret)" ` - --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` - --azure-key-vault-url "$(SignKeyVaultUrl)" ` - --timestamp-url http://timestamp.digicert.com - displayName: Sign nanoCLR assemblies - continueOnError: true - condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], '') - ) - - task: MSBuild@1 - condition: succeeded() - displayName: Pack nanoCLR CLI - inputs: - solution: 'targets\netcore\nanoFramework.nanoCLR.CLI\nanoFramework.nanoCLR.CLI.csproj' - platform: 'Any CPU' - msbuildArguments: '/p:PublicRelease=true /t:pack /p:PackageOutputPath=$(Build.ArtifactStagingDirectory) ' - configuration: 'Release' - maximumCpuCount: true - - - pwsh: | - .\sign code azure-key-vault ` - "**/*.nupkg" ` - --base-directory "$(Build.ArtifactStagingDirectory)" ` - --file-list "$(Build.Repository.LocalPath)\config\filelist.txt" ` - --publisher-name ".NET nanoFramework" ` - --description "nanoFramework.nanoCLR.CLI NuGet" ` - --description-url "https://github.com/$env:Build_Repository_Name" ` - --azure-key-vault-tenant-id "$(SignTenantId)" ` - --azure-key-vault-client-id "$(SignClientId)" ` - --azure-key-vault-client-secret "$(SignClientSecret)" ` - --azure-key-vault-certificate "$(SignKeyVaultCertificate)" ` - --azure-key-vault-url "$(SignKeyVaultUrl)" ` - --timestamp-url http://timestamp.digicert.com - displayName: Sign packages - continueOnError: true + dependsOn: + - Build_nanoCLR_CLI + + pool: + vmImage: "windows-latest" + + variables: + DOTNET_NOLOGO: true + solution: "nanoFramework.CoreLibrary.sln" + buildPlatform: "Any CPU" + buildConfiguration: "Release" + + steps: + - checkout: self + fetchDepth: 1 + - checkout: mscorlib + fetchDepth: 100 + submodules: true + + # Download nanoclr from build artifacts + - task: DownloadBuildArtifacts@1 + inputs: + buildType: "current" + artifactName: "nanoclr_cli" + downloadPath: "$(Agent.TempDirectory)/nanoclr_cli" + + # build mscorlib + + - task: InstallNanoMSBuildComponents@1 + condition: succeeded() + displayName: Install .NET nanoFramework MSBuild components + inputs: + GitHubToken: $(GitHubToken) + + - template: azure-pipelines-templates/install-nuget.yml@templates + + - task: NuGetCommand@2 + condition: succeeded() + displayName: NuGet restore + retryCountOnTaskFailure: 5 + inputs: + restoreSolution: "**/nanoFramework.CoreLibrary.sln" + feedsToUse: select + + - task: VSBuild@1 + condition: succeeded() + inputs: + solution: "**/nanoFramework.CoreLibrary.sln" + platform: "Any CPU" + msbuildArgs: "/p:PublicRelease=true" + configuration: "Release" + msbuildArchitecture: "x64" + maximumCpuCount: true + + # run tests + - template: azure-pipelines-templates/run-unit-tests.yml@templates + parameters: + runUnitTests: true + unitTestRunsettings: '$(System.DefaultWorkingDirectory)\nf-interpreter\targets\netcore\pipeline_tests.runsettings' + packagesDirectory: "$(Build.SourcesDirectory)/CoreLibrary/packages" + + - task: CopyFiles@2 + condition: succeededOrFailed() + displayName: Copy vstest dump files + inputs: + SourceFolder: 'D:\a\_temp\' + Contents: "**/*.dmp" + TargetFolder: "$(Build.ArtifactStagingDirectory)/vstest_dumps" + flattenFolders: true + + - powershell: | + $dumpPath = "$(Build.ArtifactStagingDirectory)/vstest_dumps" + $hasFiles = $false + + if (Test-Path $dumpPath -PathType Container) { + $fileCount = (Get-ChildItem $dumpPath -File | Measure-Object).Count + $hasFiles = $fileCount -gt 0 + } + echo "##vso[task.setvariable variable=hasFiles;isOutput=true]$hasFiles" + displayName: "Check for dump files" + name: checkFiles + + - task: PublishPipelineArtifact@1 + condition: eq(variables['hasFiles'], 'true') + displayName: Publish vstest dump files + inputs: + targetPath: "$(Build.ArtifactStagingDirectory)/vstest_dumps" + artifactName: VsTestCrashDumps + artifactType: pipeline + + ###################### + # generate change log + - job: Generate_change_log + dependsOn: + - Build_STM32_targets + - Build_ESP32_targets + - Build_NXP_targets + - Build_TI_SimpleLink_targets + - Build_Azure_RTOS_targets + # skip build if this is a PR, submitted by nfbot and the commit message contains [version update] condition: >- and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], '') + succeeded('Build_STM32_targets'), + succeeded('Build_ESP32_targets'), + succeeded('Build_NXP_targets'), + succeeded('Build_TI_SimpleLink_targets'), + succeeded('Build_Azure_RTOS_targets'), + not( eq(variables['Build.Reason'], 'PullRequest') + ), + or( + eq(variables['Build.SourceBranchName'], 'main'), + startsWith(variables['Build.SourceBranch'], 'refs/tags/v') ), + ne( variables['StartReleaseCandidate'], true ) ) - - task: CopyFiles@2 - condition: succeeded() - displayName: Copy nanoclr - inputs: - SourceFolder: '$(Build.Repository.LocalPath)\build\bin\Release' - Contents: 'nanoFramework.nanoCLR.dll' - TargetFolder: '$(Build.ArtifactStagingDirectory)/nanoclr' - - - task: PublishPipelineArtifact@1 - condition: succeeded() - displayName: Publish nanoclr - inputs: - targetPath: '$(Build.ArtifactStagingDirectory)/nanoclr' - artifactName: nanoclr_cli - artifactType: pipeline - - # push NuGet packages to Azure Artifacts feed (always happens when building from main, except on PR builds) - - task: NuGetCommand@2 - condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), - or( - eq(variables['ForceUpload'], true), - eq(variables['Build.SourceBranchName'], 'main') - ) - ) - continueOnError: true - displayName: Push NuGet packages to Azure Artifacts - inputs: - command: push - nuGetFeedType: external - packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' - publishFeedCredentials: 'AzureArtifacts-nf-interpreter' - allowPackageConflicts: true - - # push NuGet packages to NuGet (always happens when building from main, except on PR builds) - - task: NuGetCommand@2 + pool: + vmImage: "windows-latest" + + steps: + - task: DotNetCoreCLI@2 + condition: succeeded() + displayName: Install NBGV tool + inputs: + command: custom + custom: tool + arguments: install --tool-path . nbgv + + - script: nbgv cloud -a -c + condition: succeeded() + displayName: Set build number + + - task: UseRubyVersion@0 + condition: succeeded() + inputs: + versionSpec: "= 3.0" + addToPath: true + + # Cache change log cache files + - task: Cache@2 + displayName: Cache change log cache files + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + startsWith(variables['Build.SourceBranch'], 'refs/tags/v') + ) + inputs: + key: "changeLogCacheFiles" + restoreKeys: 1_0 + path: | + $(Agent.TempDirectory)/github-changelog-logger.log + $(Agent.TempDirectory)/github-changelog-http-cache + + # generate change log including future version + - powershell: | + gem install github_changelog_generator --quiet --no-document + # need to call it passing both cache options with full path otherwise it won't work + github_changelog_generator --token $(GitHubToken) --cache-log $env:AGENT_TEMPDIRECTORY\github-changelog-logger.log --cache-file $env:AGENT_TEMPDIRECTORY\github-changelog-http-cache --pr-wo-labels --future-release "v$env:NBGV_AssemblyVersion" + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + startsWith(variables['Build.SourceBranch'], 'refs/tags/v') + ) + displayName: Generate change log + + # push new changelog to GitHub repo + - powershell: | + git config --global gc.auto 0 + git config --global user.name nfbot + git config --global user.email nanoframework@outlook.com + git config --global core.autocrlf true + + git add CHANGELOG.md + git commit -m "Update CHANGELOG" -m"***NO_CI***" + + # compute authorization header in format "AUTHORIZATION: basic 'encoded token'" + # 'encoded token' is the Base64 of the string "nfbot:personal-token" + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes("nfbot:$(GitHubToken)")))" + + git -c http.extraheader="AUTHORIZATION: $auth" push origin "HEAD:$(Build.SourceBranchName)" + condition: >- + and( + succeeded(), + eq(variables['System.PullRequest.PullRequestId'], ''), + not( + startsWith(variables['Build.SourceBranch'], 'refs/tags/v') + ), + eq( variables['StartReleaseCandidate'], false ) + ) + continueOnError: true + displayName: Push changelog to GitHub + + ################################# + # report build failure to Discord + - job: Report_Build_Failure + dependsOn: + - Build_STM32_targets + - Build_ESP32_targets + - Build_NXP_targets + - Build_TI_SimpleLink_targets + - Build_Azure_RTOS_targets + - Build_WIN32_nanoCLR + - Build_nanoCLR_CLI + - Generate_change_log + - Check_Code_Style condition: >- and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), + ne( dependencies.Check_Code_Style.outputs['Check_Code_Style.CODE_STYLE_CHECK_FAILED'], true), or( - eq(variables['ForceUpload'], true), - eq(variables['Build.SourceBranchName'], 'main') + failed('Build_STM32_targets'), + failed('Build_ESP32_targets'), + failed('Build_NXP_targets'), + failed('Build_TI_SimpleLink_targets'), + failed('Build_Azure_RTOS_targets'), + failed('Build_WIN32_nanoCLR'), + failed('Build_nanoCLR_CLI'), + failed('Generate_change_log') ) - ) - continueOnError: true - displayName: Push NuGet packages to NuGet - inputs: - command: push - nuGetFeedType: external - allowPackageConflicts: true - packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' - publishFeedCredentials: 'NuGet-nf-interpreter' - -######################### -# Run mscorlib Unit Tests - -- job: Run_UnitTests_mscorlib - condition: >- - and( - succeeded('Build_nanoCLR_CLI'), - ne(dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true), - or( - eq(variables['BUILD_NANOCLR_CLI__'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_ALL'], true), - eq(dependencies.Check_Build_Options.outputs['TargetsToBuild.BUILD_NANOCLR_CLI'], true), - eq(dependencies.Check_Build_Options.outputs['BuildOptions.RUN_MSCORLIB_TESTS'], true) - ) - ) - - dependsOn: - - Build_nanoCLR_CLI - - pool: - vmImage: 'windows-latest' - - variables: - DOTNET_NOLOGO: true - solution: 'nanoFramework.CoreLibrary.sln' - buildPlatform: 'Any CPU' - buildConfiguration: 'Release' - - steps: - - - checkout: self - fetchDepth: 1 - - checkout: mscorlib - fetchDepth: 100 - submodules: true - - # Download nanoclr from build artifacts - - task: DownloadBuildArtifacts@1 - inputs: - buildType: 'current' - artifactName: 'nanoclr_cli' - downloadPath: '$(Agent.TempDirectory)/nanoclr_cli' - - # build mscorlib - - - task: InstallNanoMSBuildComponents@1 - condition: succeeded() - displayName: Install .NET nanoFramework MSBuild components - inputs: - GitHubToken: $(GitHubToken) - - - template: azure-pipelines-templates/install-nuget.yml@templates - - - task: NuGetCommand@2 - condition: succeeded() - displayName: NuGet restore - retryCountOnTaskFailure: 5 - inputs: - restoreSolution: '**/nanoFramework.CoreLibrary.sln' - feedsToUse: select - - - task: VSBuild@1 - condition: succeeded() - inputs: - solution: '**/nanoFramework.CoreLibrary.sln' - platform: 'Any CPU' - msbuildArgs: '/p:PublicRelease=true' - configuration: 'Release' - msbuildArchitecture: 'x64' - maximumCpuCount: true - - # run tests - - template: azure-pipelines-templates/run-unit-tests.yml@templates - parameters: - runUnitTests: true - unitTestRunsettings: '$(System.DefaultWorkingDirectory)\nf-interpreter\targets\netcore\pipeline_tests.runsettings' - packagesDirectory: '$(Build.SourcesDirectory)/CoreLibrary/packages' - - - task: CopyFiles@2 - condition: succeededOrFailed() - displayName: Copy vstest dump files - inputs: - SourceFolder: 'D:\a\_temp\' - Contents: '**/*.dmp' - TargetFolder: '$(Build.ArtifactStagingDirectory)/vstest_dumps' - flattenFolders: true - - - powershell: | - $dumpPath = "$(Build.ArtifactStagingDirectory)/vstest_dumps" - $hasFiles = $false - - if (Test-Path $dumpPath -PathType Container) { - $fileCount = (Get-ChildItem $dumpPath -File | Measure-Object).Count - $hasFiles = $fileCount -gt 0 - } - echo "##vso[task.setvariable variable=hasFiles;isOutput=true]$hasFiles" - displayName: 'Check for dump files' - name: checkFiles - - - task: PublishPipelineArtifact@1 - condition: eq(variables['hasFiles'], 'true') - displayName: Publish vstest dump files - inputs: - targetPath: '$(Build.ArtifactStagingDirectory)/vstest_dumps' - artifactName: VsTestCrashDumps - artifactType: pipeline - -###################### -# generate change log -- job: Generate_change_log - dependsOn: - - Build_STM32_targets - - Build_ESP32_targets - - Build_NXP_targets - - Build_TI_SimpleLink_targets - - Build_Azure_RTOS_targets - # skip build if this is a PR, submitted by nfbot and the commit message contains [version update] - condition: >- - and( - succeeded('Build_STM32_targets'), - succeeded('Build_ESP32_targets'), - succeeded('Build_NXP_targets'), - succeeded('Build_TI_SimpleLink_targets'), - succeeded('Build_Azure_RTOS_targets'), - not( eq(variables['Build.Reason'], 'PullRequest') - ), - or( - eq(variables['Build.SourceBranchName'], 'main'), - startsWith(variables['Build.SourceBranch'], 'refs/tags/v') ), - ne( variables['StartReleaseCandidate'], true ) - ) - - pool: - vmImage: 'windows-latest' - - steps: - - task: DotNetCoreCLI@2 - condition: succeeded() - displayName: Install NBGV tool - inputs: - command: custom - custom: tool - arguments: install --tool-path . nbgv - - - script: nbgv cloud -a -c - condition: succeeded() - displayName: Set build number - - - task: UseRubyVersion@0 - condition: succeeded() - inputs: - versionSpec: '= 3.0' - addToPath: true - - # Cache change log cache files - - task: Cache@2 - displayName: Cache change log cache files - condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), - startsWith(variables['Build.SourceBranch'], 'refs/tags/v') - ) - inputs: - key: 'changeLogCacheFiles' - restoreKeys: 1_0 - path: | - $(Agent.TempDirectory)/github-changelog-logger.log - $(Agent.TempDirectory)/github-changelog-http-cache - - # generate change log including future version - - powershell: | - gem install github_changelog_generator --quiet --no-document - # need to call it passing both cache options with full path otherwise it won't work - github_changelog_generator --token $(GitHubToken) --cache-log $env:AGENT_TEMPDIRECTORY\github-changelog-logger.log --cache-file $env:AGENT_TEMPDIRECTORY\github-changelog-http-cache --pr-wo-labels --future-release "v$env:NBGV_AssemblyVersion" - condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), - startsWith(variables['Build.SourceBranch'], 'refs/tags/v') ) - displayName: Generate change log - - # push new changelog to GitHub repo - - powershell: | - git config --global gc.auto 0 - git config --global user.name nfbot - git config --global user.email nanoframework@outlook.com - git config --global core.autocrlf true - - git add CHANGELOG.md - git commit -m "Update CHANGELOG" -m"***NO_CI***" - - # compute authorization header in format "AUTHORIZATION: basic 'encoded token'" - # 'encoded token' is the Base64 of the string "nfbot:personal-token" - $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes("nfbot:$(GitHubToken)")))" - - git -c http.extraheader="AUTHORIZATION: $auth" push origin "HEAD:$(Build.SourceBranchName)" - condition: >- - and( - succeeded(), - eq(variables['System.PullRequest.PullRequestId'], ''), - not( - startsWith(variables['Build.SourceBranch'], 'refs/tags/v') - ), - eq( variables['StartReleaseCandidate'], false ) - ) - continueOnError: true - displayName: Push changelog to GitHub - -################################# -# report build failure to Discord -- job: Report_Build_Failure - dependsOn: - - Build_STM32_targets - - Build_ESP32_targets - - Build_NXP_targets - - Build_TI_SimpleLink_targets - - Build_Azure_RTOS_targets - - Build_WIN32_nanoCLR - - Build_nanoCLR_CLI - - Generate_change_log - - Check_Code_Style - condition: >- - and( - ne( dependencies.Check_Code_Style.outputs['Check_Code_Style.CODE_STYLE_CHECK_FAILED'], true), - or( - failed('Build_STM32_targets'), - failed('Build_ESP32_targets'), - failed('Build_NXP_targets'), - failed('Build_TI_SimpleLink_targets'), - failed('Build_Azure_RTOS_targets'), - failed('Build_WIN32_nanoCLR'), - failed('Build_nanoCLR_CLI'), - failed('Generate_change_log') - ) - ) - - pool: - vmImage: 'windows-latest' - steps: + pool: + vmImage: "windows-latest" - - checkout: self - fetchDepth: 1 + steps: + - checkout: self + fetchDepth: 1 - # step from template @ nf-tools repo - - template: azure-pipelines-templates/discord-webhook.yml@templates - parameters: - status: 'failure' - webhookUrl: '$(DiscordWebhook)' - message: '' + # step from template @ nf-tools repo + - template: azure-pipelines-templates/discord-webhook.yml@templates + parameters: + status: "failure" + webhookUrl: "$(DiscordWebhook)" + message: "" From a53096dd6da5242a9993f05b4eefd54d59b65965 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Fri, 21 Jun 2024 18:17:13 +0100 Subject: [PATCH 550/572] Fix line endings ***NO_CI*** --- .../workflows/build_skyworks_evb.yml.template | 22 +- .../SiliconLabs/FIELD_PROG/nanoCLR/main.c | 420 +++++++-------- .../SKY_CEVB1/common/Device_BlockStorage.c | 246 ++++----- .../SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld | 492 +++++++++--------- .../SiliconLabs/SKY_CEVB1/nanoCLR/main.c | 420 +++++++-------- .../Si5400_CEVB/common/Device_BlockStorage.c | 246 ++++----- .../Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld | 492 +++++++++--------- .../SiliconLabs/Si5400_CEVB/nanoCLR/main.c | 420 +++++++-------- 8 files changed, 1379 insertions(+), 1379 deletions(-) diff --git a/.github/workflows/build_skyworks_evb.yml.template b/.github/workflows/build_skyworks_evb.yml.template index 411d7955ab..4522c68e21 100644 --- a/.github/workflows/build_skyworks_evb.yml.template +++ b/.github/workflows/build_skyworks_evb.yml.template @@ -1,11 +1,11 @@ -name: Build @PRESET@ - -on: - workflow_dispatch - -jobs: - build_@PRESET@: - name: Build @PRESET@ - uses: ./.github/workflows/skyworks_evb_build.yaml - with: - targetName: '@PRESET@' +name: Build @PRESET@ + +on: + workflow_dispatch + +jobs: + build_@PRESET@: + name: Build @PRESET@ + uses: ./.github/workflows/skyworks_evb_build.yaml + with: + targetName: '@PRESET@' diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c index fbf36d4be1..78bd76d0f1 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c @@ -1,210 +1,210 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = true; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c index 08dd3b69c5..e4792d9bb0 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/common/Device_BlockStorage.c @@ -1,123 +1,123 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - - // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 67}, - - // 00044000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld index ea35d0f4ad..75f91c7370 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/efm32gg11b_CLR.ld @@ -1,246 +1,246 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00044000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c index fbf36d4be1..78bd76d0f1 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -1,210 +1,210 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = true; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c index 08dd3b69c5..e4792d9bb0 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c @@ -1,123 +1,123 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - - // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 67}, - - // 00044000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2kB blocks +const BlockRange BlockRange1[] = { + + // 00000000 nanoBooter + {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, + + // 0000C00 nanoCLR + {BlockRange_BLOCKTYPE_CODE, 12, 67}, + + // 00044000 deployment + {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + // 001FF000 configuration block + {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, + /////////////////////////////////////////////////////////////////////////////////////// +}; + +const BlockRegionInfo BlockRegions[] = { + { + (0), + + // start address for block region + 0x00000000, + + // total number of blocks in this region + 512, + + // total number of bytes per block + 0x1000, + + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = { + + // STM32 flash memory is XIP + (MediaAttribute_SupportsXIP), + + // UINT32 BytesPerSector + 2, + + // UINT32 NumRegions; + ARRAYSIZE_CONST_EXPR(BlockRegions), + + // const BlockRegionInfo* pRegions; + (BlockRegionInfo *)BlockRegions, +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { + { + // BLOCK_CONFIG + { + // GPIO_PIN Pin; + 0, + + // BOOL ActiveState + + false, + }, + + // BlockDeviceinfo + (DeviceBlockInfo *)&Device_BlockInfo, + }, + + { + // CPU_MEMORY_CONFIG + // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + 0, + + // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + true, + + // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, + + // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 0, + + // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 16, + + // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x08000000, + + // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0x00200000, + + // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, + + // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, + + // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + 0, + }, + + // UINT32 ChipProtection; + 0, + + // UINT32 ManufacturerCode; + 0, + + // UINT32 DeviceCode; + 0, +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld index 1eab59a72b..98d83797d3 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld @@ -1,246 +1,246 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00042000, len = 1772k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld +/***************************************************************************//** + * Linker script for Silicon Labs EFM32GG11B devices + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* Set the RAM segment used end for threadx */ +__RAM_segment_used_end__ = 0; + +MEMORY +{ + flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + deployment (rx) : org = 0x00042000, len = 1772k /* space reserved for application deployment */ + config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ + RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ + bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions flash0 and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +/* RAM region to be used for the boot clipboard.*/ +REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > flash0 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + __copy_table_end__ = .; + } > flash0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + __zero_table_end__ = .; + } > flash0 + + /* + * + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + . = ALIGN (4); + PROVIDE (__ram_func_section_start = .); + *(.ram) + PROVIDE (__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY) : + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = .; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = .); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* boot clipboard rules inclusion.*/ +INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c index fbf36d4be1..78bd76d0f1 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c @@ -1,210 +1,210 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = true; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +// #include + +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + +// flags for hardware events +TX_EVENT_FLAGS_GROUP nanoHardwareEvents; +extern CLR_SETTINGS clrSettings; + +// byte pool configuration and definitions +// need to be at least as big as the config sector +#define DEFAULT_BYTE_POOL_SIZE 0x2000 +TX_BYTE_POOL byte_pool_0; +uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; + +// threads definitions and configurations +#define BLINK_THREAD_STACK_SIZE 1024 +#define BLINK_THREAD_PRIORITY 5 + +TX_THREAD blinkThread; +uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; + +// receiver thread +#define RECEIVER_THREAD_STACK_SIZE 2048 +#define RECEIVER_THREAD_PRIORITY 5 + +TX_THREAD receiverThread; +uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ReceiverThread_entry(uint32_t parameter); + +// CLR thread +#define CLR_THREAD_STACK_SIZE 4092 +#define CLR_THREAD_PRIORITY 5 + +TX_THREAD clrStartupThread; +uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; +extern void ClrStartupThread_entry(uint32_t parameter); + +extern sl_status_t sl_usbd_vendor_read_bulk_sync( + uint8_t class_nbr, + void *p_buf, + uint32_t buf_len, + uint16_t timeout, + uint32_t *p_xfer_len); +extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); + +void BlinkThread_entry(uint32_t parameter) +{ + (void)parameter; + + while (1) + { + GPIO_PinOutToggle(gpioPortB, 12); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); + } +} + +void tx_application_define(void *first_unused_memory) +{ + (void)first_unused_memory; + uint16_t status; + + // Create a byte memory pool from which to allocate the thread stacks. + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); + + // start watchdog + Watchdog_Init(); + +#if (TRACE_TO_STDIO == TRUE) + StdioPort_Init(); +#endif + + // Create blink thread + status = tx_thread_create( + &blinkThread, + "Blink Thread", + BlinkThread_entry, + 0, + blinkThreadStack, + BLINK_THREAD_STACK_SIZE, + BLINK_THREAD_PRIORITY, + BLINK_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // Create receiver thread + status = tx_thread_create( + &receiverThread, + "Receiver Thread", + ReceiverThread_entry, + 0, + receiverThreadStack, + RECEIVER_THREAD_STACK_SIZE, + RECEIVER_THREAD_PRIORITY, + RECEIVER_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // CLR settings to launch CLR thread + memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.RevertToBooterOnFault = true; + + // do NOT enter debugger loop on RTM builds + // this will cause the board to keep rebooting until there is an application deployed +#if defined(BUILD_RTM) + clrSettings.EnterDebuggerLoopAfterExit = false; +#else + clrSettings.EnterDebuggerLoopAfterExit = true; +#endif + + // Create CLR startup thread + status = tx_thread_create( + &clrStartupThread, + "CLR Thread", + ClrStartupThread_entry, + (uint32_t)&clrSettings, + clrStartupThreadStack, + CLR_THREAD_STACK_SIZE, + CLR_THREAD_PRIORITY, + CLR_THREAD_PRIORITY, + TX_NO_TIME_SLICE, + TX_AUTO_START); + + if (status != TX_SUCCESS) + { + while (1) + { + } + } + + // create HW event group + status = tx_event_flags_create(&nanoHardwareEvents, ""); + if (status != TX_SUCCESS) + { + while (1) + { + } + } + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} + +// Application entry point. +int main(void) +{ + sl_system_init(); + + // configure LED READY for output + GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); + + // init boot clipboard + InitBootClipboard(); + + // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running + sl_system_kernel_start(); +} From 42cd6f3966876827f4bb41f2af54aa6be7a7702a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ant=C3=B3nio=20Fagundes?= Date: Mon, 24 Jun 2024 15:38:09 +0100 Subject: [PATCH 551/572] UsbStream read doesnt trhow exception on timeout *** CHANGE TO BE TESTED *** --- .../sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp index 7344734546..336ebc1007 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.UsbStream/sys_dev_usbstream_native_System_Device_Usb_UsbStream.cpp @@ -188,8 +188,8 @@ HRESULT Library_sys_dev_usbstream_native_System_Device_Usb_UsbStream::Read___I4_ // cancel the async operation... sl_usbd_vendor_abort_read_bulk(sl_usbd_vendor_winusb_number); - // ... return exception - NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + // clear RX counter + UsbStream_PAL.RxBytesReceived = 0; } } From fc168ed4ba38be01088ef1263f9ea00828898804 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Tue, 23 Jul 2024 16:01:57 +0100 Subject: [PATCH 552/572] Work CI-CD - Replace deprecated CMake API. ***NO_CI*** --- CMake/Modules/STM32_CubePackage.cmake | 6 +++--- CMake/binutils.common.cmake | 4 ++-- targets/AzureRTOS/CMakeLists.txt | 8 ++++---- targets/AzureRTOS/Maxim/CMakeLists.txt | 4 ++-- targets/AzureRTOS/MicroBit/CMakeLists.txt | 8 ++++---- targets/AzureRTOS/Nordic/CMakeLists.txt | 2 +- targets/AzureRTOS/RaspberryPi/CMakeLists.txt | 2 +- targets/AzureRTOS/ST/CMakeLists.txt | 2 +- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- targets/ChibiOS/CMakeLists.txt | 8 ++++---- targets/ESP32/CMakeLists.txt | 2 +- targets/FreeRTOS/CMakeLists.txt | 6 +++--- targets/FreeRTOS/NXP/CMakeLists.txt | 2 +- targets/TI_SimpleLink/CMakeLists.txt | 10 +++++----- 14 files changed, 33 insertions(+), 33 deletions(-) diff --git a/CMake/Modules/STM32_CubePackage.cmake b/CMake/Modules/STM32_CubePackage.cmake index ca2d0f1524..22aa7d57ab 100644 --- a/CMake/Modules/STM32_CubePackage.cmake +++ b/CMake/Modules/STM32_CubePackage.cmake @@ -153,13 +153,13 @@ macro(ProcessSTM32CubePackage) endif() FetchContent_GetProperties(stm32${TARGET_SERIES_SHORT_LOWER}_hal_driver) - FetchContent_Populate(stm32${TARGET_SERIES_SHORT_LOWER}_hal_driver) + FetchContent_MakeAvailable(stm32${TARGET_SERIES_SHORT_LOWER}_hal_driver) FetchContent_GetProperties(cmsis_device_${TARGET_SERIES_SHORT_LOWER}) - FetchContent_Populate(cmsis_device_${TARGET_SERIES_SHORT_LOWER}) + FetchContent_MakeAvailable(cmsis_device_${TARGET_SERIES_SHORT_LOWER}) FetchContent_GetProperties(cmsis_core) - FetchContent_Populate(cmsis_core) + FetchContent_MakeAvailable(cmsis_core) endmacro() diff --git a/CMake/binutils.common.cmake b/CMake/binutils.common.cmake index 552ab97641..1726bec69c 100644 --- a/CMake/binutils.common.cmake +++ b/CMake/binutils.common.cmake @@ -743,7 +743,7 @@ function(nf_add_mbedtls_library) FetchContent_GetProperties(mbedtls) if(NOT mbedtls_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(mbedtls) + FetchContent_MakeAvailable(mbedtls) endif() # don't include tests or programs, only build libraries @@ -803,7 +803,7 @@ function(nf_add_lwip_library) if(NOT lwip_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(lwip) + FetchContent_MakeAvailable(lwip) endif() endfunction() diff --git a/targets/AzureRTOS/CMakeLists.txt b/targets/AzureRTOS/CMakeLists.txt index cbfca05874..3aa7181c78 100644 --- a/targets/AzureRTOS/CMakeLists.txt +++ b/targets/AzureRTOS/CMakeLists.txt @@ -109,7 +109,7 @@ else() endif() -FetchContent_Populate(azure_rtos) +FetchContent_MakeAvailable(azure_rtos) ########################### # Azure RTOS USBX @@ -168,7 +168,7 @@ if(AZURERTOS_USBX_REQUIRED) endif() - FetchContent_Populate(azure_rtos_usbx) + FetchContent_MakeAvailable(azure_rtos_usbx) endif() @@ -229,7 +229,7 @@ if(AZURERTOS_FILEX_REQUIRED) endif() - FetchContent_Populate(azure_rtos_filex) + FetchContent_MakeAvailable(azure_rtos_filex) endif() @@ -293,7 +293,7 @@ if(AZURERTOS_NETXDUO_REQUIRED) # enable BSD layer in NetX Duo set(NXD_ENABLE_BSD TRUE) - FetchContent_Populate(azure_rtos_netxduo) + FetchContent_MakeAvailable(azure_rtos_netxduo) endif() diff --git a/targets/AzureRTOS/Maxim/CMakeLists.txt b/targets/AzureRTOS/Maxim/CMakeLists.txt index 185070cab2..b8eff15b1a 100644 --- a/targets/AzureRTOS/Maxim/CMakeLists.txt +++ b/targets/AzureRTOS/Maxim/CMakeLists.txt @@ -62,7 +62,7 @@ else() endif() -FetchContent_Populate(maxim_micros_sdk) +FetchContent_MakeAvailable(maxim_micros_sdk) # make vars global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") @@ -125,7 +125,7 @@ else() endif() FetchContent_GetProperties(cmsis) -FetchContent_Populate(cmsis) +FetchContent_MakeAvailable(cmsis) # add platform dirs add_subdirectory(_include) diff --git a/targets/AzureRTOS/MicroBit/CMakeLists.txt b/targets/AzureRTOS/MicroBit/CMakeLists.txt index 2183d7a578..3cef5bd643 100644 --- a/targets/AzureRTOS/MicroBit/CMakeLists.txt +++ b/targets/AzureRTOS/MicroBit/CMakeLists.txt @@ -60,7 +60,7 @@ else() endif() -FetchContent_Populate(CODALMicroBitV2) +FetchContent_MakeAvailable(CODALMicroBitV2) #################### # CODAL Core @@ -116,7 +116,7 @@ else() endif() -FetchContent_Populate(CodalCore) +FetchContent_MakeAvailable(CodalCore) #################### # CODAL NRF52 @@ -172,7 +172,7 @@ else() endif() -FetchContent_Populate(CodalNrf52) +FetchContent_MakeAvailable(CodalNrf52) ######################## # CODAL Micro Bit NRF52 SDK @@ -228,7 +228,7 @@ else() endif() -FetchContent_Populate(CodalMicrobitNrf5Sdk) +FetchContent_MakeAvailable(CodalMicrobitNrf5Sdk) # make vars global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/Nordic/CMakeLists.txt b/targets/AzureRTOS/Nordic/CMakeLists.txt index 0ff58ba341..e571ca3624 100644 --- a/targets/AzureRTOS/Nordic/CMakeLists.txt +++ b/targets/AzureRTOS/Nordic/CMakeLists.txt @@ -57,7 +57,7 @@ else() endif() -FetchContent_Populate(nRFConnectSdk) +FetchContent_MakeAvailable(nRFConnectSdk) # Point to NCS root directory set(NRF_DIR ${nRFConnectSdk_SOURCE_DIR} CACHE PATH "NCS root directory") diff --git a/targets/AzureRTOS/RaspberryPi/CMakeLists.txt b/targets/AzureRTOS/RaspberryPi/CMakeLists.txt index 58b60948af..2c10177349 100644 --- a/targets/AzureRTOS/RaspberryPi/CMakeLists.txt +++ b/targets/AzureRTOS/RaspberryPi/CMakeLists.txt @@ -60,7 +60,7 @@ else() endif() -FetchContent_Populate(pico_sdk) +FetchContent_MakeAvailable(pico_sdk) # set these to help Pico SDK set(PICO_TOOLCHAIN_PATH ${TOOLCHAIN_PREFIX}) diff --git a/targets/AzureRTOS/ST/CMakeLists.txt b/targets/AzureRTOS/ST/CMakeLists.txt index a0a49cfdcd..93be746a9d 100644 --- a/targets/AzureRTOS/ST/CMakeLists.txt +++ b/targets/AzureRTOS/ST/CMakeLists.txt @@ -81,7 +81,7 @@ else() endif() FetchContent_GetProperties(chibios) -FetchContent_Populate(chibios) +FetchContent_MakeAvailable(chibios) list(APPEND TARGET_AZURERTOS_COMMON_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/_include) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index f5e29715ea..001850b444 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -114,7 +114,7 @@ else() endif() FetchContent_GetProperties(gecko_sdk) -FetchContent_Populate(gecko_sdk) +FetchContent_MakeAvailable(gecko_sdk) # including here the CMake files for the source files specific to the target series include(AzureRTOS_${TARGET_SERIES}_sources) diff --git a/targets/ChibiOS/CMakeLists.txt b/targets/ChibiOS/CMakeLists.txt index d9e49a3715..dff6aae770 100644 --- a/targets/ChibiOS/CMakeLists.txt +++ b/targets/ChibiOS/CMakeLists.txt @@ -106,7 +106,7 @@ endif() FetchContent_GetProperties(chibios) if(NOT chibios_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(chibios) + FetchContent_MakeAvailable(chibios) endif() if(CHIBIOS_CONTRIB_REQUIRED) @@ -137,7 +137,7 @@ if(CHIBIOS_CONTRIB_REQUIRED) FetchContent_GetProperties(chibios-contrib) if(NOT chibios-contrib_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(chibios-contrib) + FetchContent_MakeAvailable(chibios-contrib) endif() endif() @@ -199,7 +199,7 @@ if(NF_FEATURE_HAS_SDCARD OR NF_FEATURE_HAS_USB_MSD) FetchContent_GetProperties(fatfs) if(NOT fatfs_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(fatfs) + FetchContent_MakeAvailable(fatfs) endif() # have to delete the ffconf.h template from the repo @@ -373,7 +373,7 @@ if(NF_FEATURE_USE_LITTLEFS_OPTION) FetchContent_GetProperties(littlefs) if(NOT littlefs_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(littlefs) + FetchContent_MakeAvailable(littlefs) endif() endif() diff --git a/targets/ESP32/CMakeLists.txt b/targets/ESP32/CMakeLists.txt index e047b8292a..1e12e1da56 100644 --- a/targets/ESP32/CMakeLists.txt +++ b/targets/ESP32/CMakeLists.txt @@ -88,7 +88,7 @@ endif() FetchContent_GetProperties(esp32_idf) if(NOT esp32_idf_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(esp32_idf) + FetchContent_MakeAvailable(esp32_idf) endif() # add IDF CMake dir to modules path diff --git a/targets/FreeRTOS/CMakeLists.txt b/targets/FreeRTOS/CMakeLists.txt index a82e68ad0f..6d97146771 100644 --- a/targets/FreeRTOS/CMakeLists.txt +++ b/targets/FreeRTOS/CMakeLists.txt @@ -75,7 +75,7 @@ endif() FetchContent_GetProperties(freertos) if(NOT freertos_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(freertos) + FetchContent_MakeAvailable(freertos) endif() # check if CMSIS_SOURCE was specified or if it's empty (default is empty) @@ -129,10 +129,10 @@ else() endif() FetchContent_GetProperties(cmsis) -FetchContent_Populate(cmsis) +FetchContent_MakeAvailable(cmsis) if(NOT cmsis_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(cmsis) + FetchContent_MakeAvailable(cmsis) endif() # FreeRTOS common directories diff --git a/targets/FreeRTOS/NXP/CMakeLists.txt b/targets/FreeRTOS/NXP/CMakeLists.txt index 6cbe02181e..3ece9c0928 100644 --- a/targets/FreeRTOS/NXP/CMakeLists.txt +++ b/targets/FreeRTOS/NXP/CMakeLists.txt @@ -58,7 +58,7 @@ endif() FetchContent_GetProperties(fatfs) if(NOT fatfs_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(fatfs) + FetchContent_MakeAvailable(fatfs) endif() # have to delete the ffconf.h template from the repo diff --git a/targets/TI_SimpleLink/CMakeLists.txt b/targets/TI_SimpleLink/CMakeLists.txt index 51ad74fa24..af8a302396 100644 --- a/targets/TI_SimpleLink/CMakeLists.txt +++ b/targets/TI_SimpleLink/CMakeLists.txt @@ -58,7 +58,7 @@ if("${TARGET_SERIES}" STREQUAL "CC32xx") FetchContent_GetProperties(simplelinkcc32xxsdk) if(NOT simplelinkcc32xxsdk_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(simplelinkcc32xxsdk) + FetchContent_MakeAvailable(simplelinkcc32xxsdk) endif() # check if TI_XDCTOOLS_SOURCE was specified or if it's empty (default is empty) @@ -108,7 +108,7 @@ if("${TARGET_SERIES}" STREQUAL "CC32xx") FetchContent_GetProperties(ti_xdctools) if(NOT ti_xdctools_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(ti_xdctools) + FetchContent_MakeAvailable(ti_xdctools) endif() set(TI_XDCTools_INCLUDE_DIR ${ti_xdctools_SOURCE_DIR}/packages/ PARENT_SCOPE) @@ -159,7 +159,7 @@ elseif( "${TARGET_SERIES}" STREQUAL "CC13X2" ) FetchContent_GetProperties(simplelinkcc13xx_26xxsdk) if(NOT simplelinkcc13xx_26xxsdk_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(simplelinkcc13xx_26xxsdk) + FetchContent_MakeAvailable(simplelinkcc13xx_26xxsdk) endif() # check if TI_SYSCONFIG_SOURCE was specified or if it's empty (default is empty) @@ -209,7 +209,7 @@ elseif( "${TARGET_SERIES}" STREQUAL "CC13X2" ) FetchContent_GetProperties(ti_sysconfig) if(NOT ti_sysconfig_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(ti_sysconfig) + FetchContent_MakeAvailable(ti_sysconfig) endif() # check if TI_XDCTOOLS_SOURCE was specified or if it's empty (default is empty) @@ -259,7 +259,7 @@ elseif( "${TARGET_SERIES}" STREQUAL "CC13X2" ) FetchContent_GetProperties(ti_xdctools) if(NOT ti_xdctools_POPULATED) # Fetch the content using previously declared details - FetchContent_Populate(ti_xdctools) + FetchContent_MakeAvailable(ti_xdctools) endif() set(TI_XDCTools_INCLUDE_DIR ${ti_xdctools_SOURCE_DIR}/packages/ PARENT_SCOPE) From a01463f0d509da6d0b4e23c6506ae2f8590b3118 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 23 Sep 2024 14:19:37 +0100 Subject: [PATCH 553/572] Work CI-CD - Update github actions to latest versions. ***NO_CI*** [no ci] --- .github/workflows/merge-upstream-skyworks-evb.yml | 3 ++- .github/workflows/merge-upstream.yml | 4 ++-- .github/workflows/skyworks_evb_build.yaml | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.github/workflows/merge-upstream-skyworks-evb.yml b/.github/workflows/merge-upstream-skyworks-evb.yml index 5311eab17f..d48dbbcd57 100644 --- a/.github/workflows/merge-upstream-skyworks-evb.yml +++ b/.github/workflows/merge-upstream-skyworks-evb.yml @@ -18,11 +18,12 @@ jobs: token: ${{ secrets.GITHUB_TOKEN }} - name: Merge from upstream repo - uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4.1 with: target_sync_branch: skyworks-evb upstream_sync_branch: main upstream_sync_repo: Skyworks-Timing-Software/nf-interpreter + target_repo_token: ${{ secrets.GITHUB_TOKEN }} - name: New commits found if: steps.sync.outputs.has_new_commits == 'true' diff --git a/.github/workflows/merge-upstream.yml b/.github/workflows/merge-upstream.yml index c863fb7cfe..5d9d245909 100644 --- a/.github/workflows/merge-upstream.yml +++ b/.github/workflows/merge-upstream.yml @@ -18,11 +18,12 @@ jobs: token: ${{ secrets.GITHUB_TOKEN }} - name: Merge from upstream repo - uses: aormsby/Fork-Sync-With-Upstream-action@v3.4 + uses: aormsby/Fork-Sync-With-Upstream-action@v3.4.1 with: target_sync_branch: main upstream_sync_branch: main upstream_sync_repo: nanoframework/nf-interpreter + target_repo_token: ${{ secrets.GITHUB_TOKEN }} - name: New commits found if: steps.sync.outputs.has_new_commits == 'true' @@ -34,4 +35,3 @@ jobs: - name: Show value of 'has_new_commits' run: echo ${{ steps.sync.outputs.has_new_commits }} - diff --git a/.github/workflows/skyworks_evb_build.yaml b/.github/workflows/skyworks_evb_build.yaml index 126420537c..1a22ad8486 100644 --- a/.github/workflows/skyworks_evb_build.yaml +++ b/.github/workflows/skyworks_evb_build.yaml @@ -53,7 +53,7 @@ jobs: - name: Install arm-none-eabi-gcc uses: carlosperate/arm-none-eabi-gcc-action@v1 with: - release: '13.2.Rel1' + release: '13.3.Rel1' - name: Tweak GCC path run: | From 719b751ce7c3504e5a857f7ff45866bf31cdb914 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Fri, 25 Oct 2024 15:10:08 +0100 Subject: [PATCH 554/572] Add extra delay before config and start USB layer --- targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c | 3 +++ targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c | 3 +++ targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c | 3 +++ targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c | 3 +++ targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c | 3 +++ targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c | 3 +++ 6 files changed, 18 insertions(+) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c index 78bd76d0f1..75712ffb64 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c @@ -178,6 +178,9 @@ void tx_application_define(void *first_unused_memory) } #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c index 78bd76d0f1..1c74ed40a6 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -178,6 +178,9 @@ void tx_application_define(void *first_unused_memory) } #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c index 78bd76d0f1..75712ffb64 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c @@ -178,6 +178,9 @@ void tx_application_define(void *first_unused_memory) } #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c index 78bd76d0f1..75712ffb64 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c @@ -178,6 +178,9 @@ void tx_application_define(void *first_unused_memory) } #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c index 78bd76d0f1..75712ffb64 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c @@ -178,6 +178,9 @@ void tx_application_define(void *first_unused_memory) } #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c index 78bd76d0f1..75712ffb64 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c @@ -178,6 +178,9 @@ void tx_application_define(void *first_unused_memory) } #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + // can't call USBD init twice sli_usbd_init(); sli_usbd_configuration_config0_init(); From 5226117ecd142a3ed95983c3e61e4e2b1804ac8a Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Thu, 31 Oct 2024 14:04:51 -0500 Subject: [PATCH 555/572] SKY_CEVB1: experiment with even longer delay before sli_usbd_init() --- targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c index 1c74ed40a6..b493a7b7e9 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -179,7 +179,7 @@ void tx_application_define(void *first_unused_memory) #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(6000)); // can't call USBD init twice sli_usbd_init(); From b8c9a48f8cfdb0e689edbec2b5911466c538427f Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 7 Nov 2024 14:00:15 +0000 Subject: [PATCH 556/572] Move USB init to target PAL - Remove all USB stack init from CLR main. - Update code accordingly. --- .../SiliconLabs/SKY_CEVB1/nanoCLR/main.c | 33 +++-------------- .../SiliconLabs/SKY_EEVB/nanoCLR/main.c | 33 +++-------------- .../SiliconLabs/STB_Interposer/nanoCLR/main.c | 33 +++-------------- .../SiliconLabs/Si5400_CEVB/nanoCLR/main.c | 32 +++-------------- .../SiliconLabs/Si5575_CEVB/nanoCLR/main.c | 33 +++-------------- .../SiliconLabs/_nanoCLR/targetPAL.c | 36 +++++++++++++++++++ 6 files changed, 61 insertions(+), 139 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c index b493a7b7e9..54ca65223c 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/nanoCLR/main.c @@ -16,15 +16,6 @@ #include #include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -66,11 +57,16 @@ extern sl_status_t sl_usbd_vendor_read_bulk_sync( uint16_t timeout, uint32_t *p_xfer_len); extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); void BlinkThread_entry(uint32_t parameter) { (void)parameter; + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + while (1) { GPIO_PinOutToggle(gpioPortB, 12); @@ -176,25 +172,6 @@ void tx_application_define(void *first_unused_memory) { } } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(6000)); - - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c index 75712ffb64..54ca65223c 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/nanoCLR/main.c @@ -16,15 +16,6 @@ #include #include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -66,11 +57,16 @@ extern sl_status_t sl_usbd_vendor_read_bulk_sync( uint16_t timeout, uint32_t *p_xfer_len); extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); void BlinkThread_entry(uint32_t parameter) { (void)parameter; + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + while (1) { GPIO_PinOutToggle(gpioPortB, 12); @@ -176,25 +172,6 @@ void tx_application_define(void *first_unused_memory) { } } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); - - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c index 75712ffb64..54ca65223c 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/nanoCLR/main.c @@ -16,15 +16,6 @@ #include #include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -66,11 +57,16 @@ extern sl_status_t sl_usbd_vendor_read_bulk_sync( uint16_t timeout, uint32_t *p_xfer_len); extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); void BlinkThread_entry(uint32_t parameter) { (void)parameter; + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + while (1) { GPIO_PinOutToggle(gpioPortB, 12); @@ -176,25 +172,6 @@ void tx_application_define(void *first_unused_memory) { } } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); - - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c index 75712ffb64..b455443582 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c @@ -18,14 +18,6 @@ #include // #include -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; extern CLR_SETTINGS clrSettings; @@ -66,11 +58,16 @@ extern sl_status_t sl_usbd_vendor_read_bulk_sync( uint16_t timeout, uint32_t *p_xfer_len); extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); void BlinkThread_entry(uint32_t parameter) { (void)parameter; + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + while (1) { GPIO_PinOutToggle(gpioPortB, 12); @@ -176,25 +173,6 @@ void tx_application_define(void *first_unused_memory) { } } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); - - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c index 75712ffb64..54ca65223c 100644 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c @@ -16,15 +16,6 @@ #include #include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -66,11 +57,16 @@ extern sl_status_t sl_usbd_vendor_read_bulk_sync( uint16_t timeout, uint32_t *p_xfer_len); extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); void BlinkThread_entry(uint32_t parameter) { (void)parameter; + GPIO_PinOutToggle(gpioPortB, 12); + + UsbStackInit(); + while (1) { GPIO_PinOutToggle(gpioPortB, 12); @@ -176,25 +172,6 @@ void tx_application_define(void *first_unused_memory) { } } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); - - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c index 9043c3db0f..a77c685ecf 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c @@ -6,5 +6,41 @@ #include #include +#include +#include + +// need to declare these as extern instead of including the header files +extern void usb_device_hid_app_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_hid_hid0_init(void); +extern void sli_usbd_init(void); +extern void sli_usbd_configuration_config0_init(void); +extern void sli_usbd_cdc_acm_acm0_init(void); +extern void usb_device_cdc_acm_app_init(void); + // required for Azure RTOS TX_INTERRUPT_SAVE_AREA implementation at platform level unsigned int interrupt_save; + +// common code used to start USB stack and various components +void UsbStackInit() +{ + +#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE + // wait a couple of seconds to allow all other threads to init + tx_thread_sleep(TX_TICKS_PER_MILLISEC(4000)); + + // can't call USBD init twice + sli_usbd_init(); + sli_usbd_configuration_config0_init(); +#endif + +#if GECKO_FEATURE_USBD_HID == TRUE + sli_usbd_hid_hid0_init(); + usb_device_hid_app_init(); +#endif + +#if HAL_WP_USE_USB_CDC == TRUE + sli_usbd_cdc_acm_acm0_init(); + usb_device_cdc_acm_app_init(); +#endif +} From bc7b08d9dcea08fe20c5664b2cc3da652d9b9e18 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 13 Nov 2024 13:05:56 -0600 Subject: [PATCH 557/572] Skyworks EVBs: remove old now unused Si5575_CEVB and Si5400_CEVB targets; decrease delayt of USB delay; update FIELD_PROG with new USB init code --- .../SiliconLabs/FIELD_PROG/nanoCLR/main.c | 30 +- .../SiliconLabs/Si5400_CEVB/CMakeLists.txt | 76 ---- .../SiliconLabs/Si5400_CEVB/CMakePresets.json | 85 ----- .../SiliconLabs/Si5400_CEVB/README.md | 28 -- .../autogen/sl_device_init_clocks.c | 28 -- .../Si5400_CEVB/autogen/sl_event_handler.c | 48 --- .../Si5400_CEVB/autogen/sl_uartdrv_init.c | 91 ----- .../autogen/sl_uartdrv_instances.h | 35 -- .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 -------- .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 -- .../autogen/sl_usbd_class_hid_instances.c | 277 -------------- .../autogen/sl_usbd_class_hid_instances.h | 32 -- .../autogen/sl_usbd_configuration_instances.c | 61 ---- .../autogen/sl_usbd_configuration_instances.h | 18 - .../SiliconLabs/Si5400_CEVB/bspconfig.h | 9 - .../Si5400_CEVB/common/CMakeLists.txt | 10 - .../common/Device_BlockStorage-DEBUG.c | 123 ------- .../Si5400_CEVB/common/Device_BlockStorage.c | 123 ------- .../common/tx_initialize_low_level.S | 239 ------------ .../Si5400_CEVB/config/pin_config.h | 259 ------------- .../config/sl_board_control_config.h | 112 ------ .../config/sl_device_init_hfrco_config.h | 27 -- .../config/sl_device_init_hfxo_config.h | 43 --- .../config/sl_device_init_lfrco_config.h | 34 -- .../config/sl_device_init_lfxo_config.h | 37 -- .../config/sl_iostream_usart_onewire_config.h | 103 ------ .../config/sl_iostream_usart_vcom_config.h | 112 ------ .../Si5400_CEVB/config/sl_memory_config.h | 13 - .../config/sl_uartdrv_usart_vcom_config.h | 85 ----- .../config/sl_usbd_class_acm0_config.h | 53 --- .../config/sl_usbd_class_hid0_config.h | 143 -------- .../config/sl_usbd_class_winusb_config.h | 59 --- .../config/sl_usbd_config0_config.h | 51 --- .../Si5400_CEVB/config/sl_usbd_core_config.h | 199 ---------- .../config/sl_usbd_device_config.h | 60 --- .../Si5400_CEVB/config/uartdrv_config.h | 114 ------ .../SiliconLabs/Si5400_CEVB/launch.json | 83 ----- .../Si5400_CEVB/nanoBooter/CMakeLists.txt | 10 - .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ------------ .../nanoBooter/efm32gg11b_booter.ld | 235 ------------ .../SiliconLabs/Si5400_CEVB/nanoBooter/main.c | 186 ---------- .../Si5400_CEVB/nanoBooter/target_board.h.in | 18 - .../Si5400_CEVB/nanoCLR/CMakeLists.txt | 15 - .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 ------------- .../Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld | 246 ------------- .../SiliconLabs/Si5400_CEVB/nanoCLR/main.c | 191 ---------- .../Si5400_CEVB/nanoCLR/nanoHAL.cpp | 8 - .../Si5400_CEVB/nanoCLR/target_board.h.in | 18 - .../Si5400_CEVB/nanoCLR/usb_hid_app.c | 244 ------------- .../Si5400_CEVB/target_BlockStorage.c | 19 - .../Si5400_CEVB/target_BlockStorage.h | 12 - .../target_com_sky_nf_dev_i2c_config.cpp | 26 -- .../target_com_sky_nf_dev_i2c_config.h | 4 - .../target_com_sky_nf_dev_spi_config.cpp | 48 --- .../target_com_sky_nf_dev_spi_config.h | 8 - .../SiliconLabs/Si5400_CEVB/target_common.c | 27 -- .../Si5400_CEVB/target_common.h.in | 52 --- .../Si5400_CEVB/target_nano_gg_adc_config.cpp | 52 --- .../Si5400_CEVB/target_nano_gg_adc_config.h | 9 - .../target_nf_dev_onewire_config.cpp | 8 - .../target_nf_dev_onewire_config.h | 13 - .../Si5400_CEVB/target_stdio_config.c | 7 - .../Si5400_CEVB/target_stdio_config.h | 5 - .../target_system_device_adc_config.cpp | 6 - .../target_system_device_adc_config.h | 6 - .../target_system_device_i2c_config.cpp | 32 -- .../target_system_device_i2c_config.h | 8 - .../target_system_device_pwm_config.cpp | 17 - .../target_system_device_spi_config.cpp | 35 -- .../target_system_device_spi_config.h | 7 - .../target_system_io_ports_config.cpp | 4 - .../target_system_io_ports_config.h | 5 - .../SiliconLabs/Si5400_CEVB/target_tx_user.h | 206 ----------- .../SiliconLabs/Si5400_CEVB/target_ux_user.h | 345 ------------------ .../SiliconLabs/Si5575_CEVB/CMakeLists.txt | 76 ---- .../SiliconLabs/Si5575_CEVB/CMakePresets.json | 85 ----- .../SiliconLabs/Si5575_CEVB/README.md | 28 -- .../autogen/sl_device_init_clocks.c | 28 -- .../Si5575_CEVB/autogen/sl_event_handler.c | 48 --- .../Si5575_CEVB/autogen/sl_uartdrv_init.c | 91 ----- .../autogen/sl_uartdrv_instances.h | 35 -- .../autogen/sl_usbd_class_cdc_acm_instances.c | 154 -------- .../autogen/sl_usbd_class_cdc_acm_instances.h | 27 -- .../autogen/sl_usbd_class_hid_instances.c | 277 -------------- .../autogen/sl_usbd_class_hid_instances.h | 32 -- .../autogen/sl_usbd_configuration_instances.c | 61 ---- .../autogen/sl_usbd_configuration_instances.h | 18 - .../SiliconLabs/Si5575_CEVB/bspconfig.h | 9 - .../Si5575_CEVB/common/CMakeLists.txt | 10 - .../common/Device_BlockStorage-DEBUG.c | 123 ------- .../Si5575_CEVB/common/Device_BlockStorage.c | 123 ------- .../common/tx_initialize_low_level.S | 239 ------------ .../Si5575_CEVB/config/pin_config.h | 259 ------------- .../config/sl_board_control_config.h | 112 ------ .../config/sl_device_init_hfrco_config.h | 27 -- .../config/sl_device_init_hfxo_config.h | 43 --- .../config/sl_device_init_lfrco_config.h | 34 -- .../config/sl_device_init_lfxo_config.h | 37 -- .../config/sl_iostream_usart_onewire_config.h | 103 ------ .../config/sl_iostream_usart_vcom_config.h | 112 ------ .../Si5575_CEVB/config/sl_memory_config.h | 13 - .../config/sl_uartdrv_usart_vcom_config.h | 85 ----- .../config/sl_usbd_class_acm0_config.h | 53 --- .../config/sl_usbd_class_hid0_config.h | 143 -------- .../config/sl_usbd_class_winusb_config.h | 59 --- .../config/sl_usbd_config0_config.h | 51 --- .../Si5575_CEVB/config/sl_usbd_core_config.h | 199 ---------- .../config/sl_usbd_device_config.h | 60 --- .../Si5575_CEVB/config/uartdrv_config.h | 114 ------ .../SiliconLabs/Si5575_CEVB/launch.json | 83 ----- .../Si5575_CEVB/nanoBooter/CMakeLists.txt | 10 - .../nanoBooter/efm32gg11b_booter-DEBUG.ld | 235 ------------ .../nanoBooter/efm32gg11b_booter.ld | 235 ------------ .../SiliconLabs/Si5575_CEVB/nanoBooter/main.c | 186 ---------- .../Si5575_CEVB/nanoBooter/target_board.h.in | 18 - .../Si5575_CEVB/nanoCLR/CMakeLists.txt | 15 - .../nanoCLR/efm32gg11b_CLR-DEBUG.ld | 246 ------------- .../Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld | 246 ------------- .../SiliconLabs/Si5575_CEVB/nanoCLR/main.c | 190 ---------- .../Si5575_CEVB/nanoCLR/nanoHAL.cpp | 8 - .../Si5575_CEVB/nanoCLR/target_board.h.in | 18 - .../Si5575_CEVB/nanoCLR/usb_hid_app.c | 244 ------------- .../Si5575_CEVB/target_BlockStorage.c | 19 - .../Si5575_CEVB/target_BlockStorage.h | 12 - .../target_com_sky_nf_dev_i2c_config.cpp | 26 -- .../target_com_sky_nf_dev_i2c_config.h | 4 - .../target_com_sky_nf_dev_spi_config.cpp | 48 --- .../target_com_sky_nf_dev_spi_config.h | 8 - .../SiliconLabs/Si5575_CEVB/target_common.c | 27 -- .../Si5575_CEVB/target_common.h.in | 52 --- .../Si5575_CEVB/target_nano_gg_adc_config.cpp | 52 --- .../Si5575_CEVB/target_nano_gg_adc_config.h | 9 - .../target_nf_dev_onewire_config.cpp | 8 - .../target_nf_dev_onewire_config.h | 13 - .../Si5575_CEVB/target_stdio_config.c | 7 - .../Si5575_CEVB/target_stdio_config.h | 5 - .../target_system_device_adc_config.cpp | 6 - .../target_system_device_adc_config.h | 6 - .../target_system_device_i2c_config.cpp | 32 -- .../target_system_device_i2c_config.h | 8 - .../target_system_device_pwm_config.cpp | 17 - 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targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_tx_user.h delete mode 100644 targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_ux_user.h diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c index 75712ffb64..d2db3a36b0 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/nanoCLR/main.c @@ -16,15 +16,6 @@ #include #include -// #include - -extern void usb_device_hid_app_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_hid_hid0_init(void); -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); // flags for hardware events TX_EVENT_FLAGS_GROUP nanoHardwareEvents; @@ -66,10 +57,12 @@ extern sl_status_t sl_usbd_vendor_read_bulk_sync( uint16_t timeout, uint32_t *p_xfer_len); extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); +extern void UsbStackInit(); void BlinkThread_entry(uint32_t parameter) { (void)parameter; + UsbStackInit(); while (1) { @@ -176,25 +169,6 @@ void tx_application_define(void *first_unused_memory) { } } - -#if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE - // wait a couple of seconds to allow all threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); - - // can't call USBD init twice - sli_usbd_init(); - sli_usbd_configuration_config0_init(); -#endif - -#if GECKO_FEATURE_USBD_HID == TRUE - sli_usbd_hid_hid0_init(); - usb_device_hid_app_init(); -#endif - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif } // Application entry point. diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt deleted file mode 100644 index bab63d4097..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakeLists.txt +++ /dev/null @@ -1,76 +0,0 @@ - -include(FetchContent) -include(binutils.common) -include(binutils.AzureRTOS) -include(AzureRTOS_${TARGET_SERIES}_GCC_options) - -# Azure RTOS settings and inclusion of build system -set(THREADX_ARCH "cortex_m4" ) -set(THREADX_TOOLCHAIN "gnu" ) -# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") -# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") - -set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) - -add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) -# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) -# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) -# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) - -nf_setup_target_build( - HAS_NANOBOOTER - - BOOTER_LINKER_FILE - efm32gg11b_booter - - CLR_LINKER_FILE - efm32gg11b_CLR - - BOOTER_EXTRA_COMPILE_DEFINITIONS - EFM32GG11B820F2048GQ100=1 - SL_COMPONENT_CATALOG_PRESENT=1 - _SILICON_LABS_32B_SERIES_2_CONFIG=0 - BSP_LF_CLK_SEL=99 - I2CSPM_TRANSFER_TIMEOUT=3000 - SL_STACK_SIZE=0x2000 - SL_HEAP_SIZE=0x2000 - - CLR_EXTRA_COMPILE_DEFINITIONS - EFM32GG11B820F2048GQ100=1 - SL_COMPONENT_CATALOG_PRESENT=1 - _SILICON_LABS_32B_SERIES_2_CONFIG=0 - BSP_LF_CLK_SEL=99 - I2CSPM_TRANSFER_TIMEOUT=3000 - SL_STACK_SIZE=0x7000 - SL_HEAP_SIZE=0x10000 - - BOOTER_EXTRA_LINKMAP_PROPERTIES - ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" - - CLR_EXTRA_LINKMAP_PROPERTIES - ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" -) - -# generate bin file for deployment -if(SRECORD_TOOL_AVAILABLE) - - ############################################################################################################ - ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## - ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## - ############################################################################################################ - - if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) - nf_generate_bin_package( - ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin - ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 13000 - ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) - else() - nf_generate_bin_package( - ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin - ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - C000 - ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) - endif() - -endif() diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json deleted file mode 100644 index b9f6e1728f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/CMakePresets.json +++ /dev/null @@ -1,85 +0,0 @@ -{ - "version": 4, - "include": [ - "../../../../CMake/arm-gcc.json", - "../../../../config/user-tools-repos.json", - "../../../../config/user-prefs.json" - ], - "configurePresets": [ - { - "name": "Si5400_CEVB_Debug", - "inherits": [ - "arm-gcc-cortex-preset", - "user-tools-repos", - "user-prefs" - ], - "hidden": false, - "cacheVariables": { - "TARGET_BOARD": "Si5400_CEVB", - "TARGET_NAME": "Si5400_CEVB_Debug", - "RTOS": "AzureRTOS", - "TARGET_SERIES": "EFM32GG11", - "SUPPORT_ANY_BASE_CONVERSION": "OFF", - "NF_FEATURE_RTC": "ON", - "NF_FEATURE_DEBUGGER": "ON", - "NF_FEATURE_HAS_SDCARD": "OFF", - "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", - "API_System.Math": "ON", - "API_Hardware.GiantGecko": "ON", - "API_System.Device.Gpio": "ON", - "API_System.Device.Pwm": "ON", - "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", - "API_System.Device.Dac": "OFF", - "API_System.Net": "OFF", - "API_nanoFramework.Device.OneWire": "ON", - "API_nanoFramework.Devices.Can": "OFF", - "API_nanoFramework.ResourceManager": "ON", - "API_nanoFramework.System.Collections": "ON", - "API_nanoFramework.System.Text": "ON", - "API_nanoFramework.GiantGecko.Adc": "OFF", - "API_Windows.Storage": "OFF", - "API_nanoFramework.Graphics": "OFF", - "TARGET_SERIAL_BAUDRATE": "921600", - "HAL_WP_USE_SERIAL": "OFF", - "HAL_WP_USE_USB_CDC": "ON", - "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", - "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON", - "API_nanoFramework.System.IO.Hashing": "ON" - } - }, - { - "name": "Si5400_CEVB_Release", - "inherits": [ - "Si5400_CEVB_Debug" - ], - "hidden": false, - "cacheVariables": { - "TARGET_NAME": "Si5400_CEVB_Release", - "NF_BUILD_RTM": "ON", - "NF_PROFILE_NEW_ALLOCATIONS": "OFF", - "NF_TRACE_MEMORY_STATS": "OFF" - } - } - ], - "buildPresets": [ - { - "inherits": "base-user", - "name": "Si5400_CEVB_Debug", - "displayName": "Si5400_CEVB_Debug", - "configurePreset": "Si5400_CEVB_Debug" - }, - { - "inherits": "base-user", - "name": "Si5400_CEVB_Release", - "displayName": "Si5400_CEVB_Release", - "configurePreset": "Si5400_CEVB_Release" - } - ] -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md deleted file mode 100644 index c35099a766..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/README.md +++ /dev/null @@ -1,28 +0,0 @@ -# Skyworks Si5400 CEVB featuring SiLabs EFM32 Giant Gecko GG11 - -## See -https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8175353962/Si5400+CEVB+Software+Control - -https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB - -## Key Files - -CMakePresets.json - Enable packages, targets, naming, etc. - -target_system_device_spi_config.h -target_system_device_spi_config.cpp - SPI - -target_system_device_i2c_config.h -target_system_device_i2c_config.cpp - I2C - -target_nano_gg_adc_config.h -target_nano_gg_adc_config.cpp - ADC - -nanoBooter\main.c -nanoCLR\main.c - Bootloader Mode / Ready LED - diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c deleted file mode 100644 index 5e12163b4b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_device_init_clocks.c +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Copyright 2019 Silicon Laboratories Inc. www.silabs.com -// See LICENSE file in the project root for full license information. -// - -#include "sl_device_init_clocks.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_clocks(void) -{ - CMU_CLOCK_SELECT_SET(HF, USHFRCO); - - CMU_ClockEnable(cmuClock_HFLE, true); - CMU_ClockEnable(cmuClock_HFPER, true); - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_CLOCK_SELECT_SET(LFA, LFRCO); - CMU_CLOCK_SELECT_SET(LFB, LFRCO); -#if defined(_CMU_LFCCLKSEL_MASK) - CMU_CLOCK_SELECT_SET(LFC, LFRCO); -#endif -#if defined(_CMU_LFECLKSEL_MASK) - CMU_CLOCK_SELECT_SET(LFE, LFRCO); -#endif - - return SL_STATUS_OK; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c deleted file mode 100644 index c0d02691c1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_event_handler.c +++ /dev/null @@ -1,48 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Copyright 2020 Silicon Laboratories Inc. www.silabs.com -// See LICENSE file in the project root for full license information. -// - -#include "sl_event_handler.h" - -#include "em_chip.h" -#include "sl_device_init_nvic.h" -#include "sl_board_init.h" -#include "sl_device_init_dcdc.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_lfxo.h" -#include "sl_device_init_hfrco.h" -#include "sl_device_init_lfrco.h" -#include "sl_device_init_clocks.h" -#include "sl_device_init_emu.h" -#include "sl_board_control.h" -#include "sl_sleeptimer.h" -#include "gpiointerrupt.h" -#include "sl_uartdrv_instances.h" -#include "sl_iostream_init_usart_instances.h" -#include "sl_iostream_init_instances.h" -#include "sl_i2cspm_instances.h" -#include "sl_power_manager.h" - -#include -#include - -extern void InitGpCrc(void); - -void sl_platform_init(void) -{ - CHIP_Init(); - sl_device_init_nvic(); - sl_board_preinit(); - sl_device_init_dcdc(); - // sl_device_init_hfxo(); - sl_device_init_hfrco(); - // sl_device_init_lfxo(); - sl_device_init_lfrco(); - sl_device_init_clocks(); - sl_device_init_emu(); - sl_board_init(); - sl_power_manager_init(); - InitGpCrc(); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c deleted file mode 100644 index ab0bb51bee..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_init.c +++ /dev/null @@ -1,91 +0,0 @@ -#include "uartdrv.h" -#include "sl_uartdrv_instances.h" -#include - -#include "sl_uartdrv_usart_vcom_config.h" - -UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; -UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; - -static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; - -/* If CTS and RTS not defined, define a default value to avoid errors */ -#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 -#endif -#endif - -#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 -#endif -#endif - - -/* Define RX and TX buffer queues */ -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); - - -/* Create uartdrv initialization structs */ -UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { - .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, - .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, -#if defined(_USART_ROUTELOC0_MASK) - .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, - .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, -#elif defined(_USART_ROUTE_MASK) - .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, -#elif defined(_GPIO_USART_ROUTEEN_MASK) - .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, - .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, - .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, - .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, - .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, -#endif - .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, - .parity = SL_UARTDRV_USART_VCOM_PARITY, - .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, -#if defined(USART_CTRL_MVDIS) - .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, -#endif - .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, - .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, - .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, - .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, - .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, - .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, - .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, -#if defined(_USART_ROUTELOC1_MASK) - .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, - .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, -#endif -}; - - -void sl_uartdrv_init_instances(void){ - UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); - sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); -} - -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) -{ - sl_status_t status = SL_STATUS_INVALID_HANDLE; - - if (handle != NULL) { - sli_uartdrv_default_handle = handle; - status = SL_STATUS_OK; - } - - return status; -} - -UARTDRV_Handle_t sl_uartdrv_get_default(void) -{ - return sli_uartdrv_default_handle; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h deleted file mode 100644 index 894c73f803..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_uartdrv_instances.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef SL_UARTDRV_INSTANCES_H -#define SL_UARTDRV_INSTANCES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sl_status.h" -#include "uartdrv.h" - -extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; - -void sl_uartdrv_init_instances(void); - -/***************************************************************************//** - * Set the handle as the default UARTDRV handle. - * - * @param[in] handle UARTDRV handle to set as default. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); - -/***************************************************************************//** - * Get the default UARTDRV handle configured. - * - * @return UARTDRV handle - ******************************************************************************/ -UARTDRV_Handle_t sl_uartdrv_get_default(void); - -#ifdef __cplusplus -} -#endif - -#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c deleted file mode 100644 index 12f715438d..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c +++ /dev/null @@ -1,154 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include -#include -#include - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_cdc_acm_instances.h" - -/* include config file for the instances */ - -#include - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for acm0 instance */ - -void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); - -void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); - -void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); - -bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); - -//**************************************************************************** -// Global variables. - -/* variables for acm0 instance */ - -uint8_t sl_usbd_cdc_acm_acm0_number = 0; - -sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { - sli_usbd_cdc_acm_acm0_enable, - sli_usbd_cdc_acm_acm0_disable, - sli_usbd_cdc_acm_acm0_line_control_changed, - sli_usbd_cdc_acm_acm0_line_coding_changed, -}; - -//**************************************************************************** -// Callback functions. - -/* callback functions for acm0 instance */ -void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) -{ - (void)&subclass_nbr; - sl_usbd_cdc_acm_acm0_on_enable_event(); - return; -} - -void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) -{ - (void)&subclass_nbr; - sl_usbd_cdc_acm_acm0_on_disable_event(); - return; -} - -void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) -{ - (void)&subclass_nbr; - (void)&event; - (void)&event_chngd; - sl_usbd_cdc_acm_acm0_on_line_control_event(); - return; -} - -bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) -{ - (void)&subclass_nbr; - (void)&p_line_coding; - sl_usbd_cdc_acm_acm0_on_line_coding_event(); - return true; -} - -//**************************************************************************** -// Global functions. - -/* initialize acm0 instance */ -void sli_usbd_cdc_acm_acm0_init() -{ - uint16_t interval = 0; - uint16_t capabilities = 0; - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; - - /* line state notification interval for that instance */ - interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; - - /* call management capabilities */ - if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) - { - capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; - } - - /* call management DCI interface */ - if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) - { - capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; - } - - /* create CDC ACM instance */ - sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); - - /* store class number globally */ - sl_usbd_cdc_acm_acm0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) -{ -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) -{ -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) -{ -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) -{ -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h deleted file mode 100644 index dd62731af5..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h +++ /dev/null @@ -1,27 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT -#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT - -#include - -/* class numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_cdc_acm_acm0_number; - -/* event handlers for all CDC ACM instances */ - -__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); -__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); -__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); -__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); - -/* init functions for all CDC ACM instances */ - -void sli_usbd_cdc_acm_acm0_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c deleted file mode 100644 index 18d550951b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.c +++ /dev/null @@ -1,277 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include -#include -#include "sl_usbd_class_hid.h" - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_hid_instances.h" - -/* include config file for the instances */ - -#include - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for hid0 instance */ -void sli_usbd_hid_hid0_enable(uint8_t class_nbr); - -void sli_usbd_hid_hid0_disable(uint8_t class_nbr); - -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); - -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); - -void sli_usbd_hid_hid0_set_output_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); - -void sli_usbd_hid_hid0_get_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); - -void sli_usbd_hid_hid0_set_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); - -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); - -//**************************************************************************** -// Global variables. - -/* variables for mouse0 instance */ - -uint8_t sl_usbd_hid_hid0_number = 0; - -uint8_t sl_usbd_hid_hid0_default_protocol = 0; - -static const uint8_t sli_usbd_hid_hid0_default_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, 0x00, - SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, - SL_USBD_HID_LOCAL_USAGE + 1, 0x09, - SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, - SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, - SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, - SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; - -sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { - sli_usbd_hid_hid0_enable, - sli_usbd_hid_hid0_disable, - sli_usbd_hid_hid0_get_report_desc, - sli_usbd_hid_hid0_get_phy_desc, - sli_usbd_hid_hid0_set_output_report, - sli_usbd_hid_hid0_get_feature_report, - sli_usbd_hid_hid0_set_feature_report, - sli_usbd_hid_hid0_get_protocol, - sli_usbd_hid_hid0_set_protocol, -}; - -//**************************************************************************** -// Callback functions. - -/* callback functions for mouse0 instance */ -void sli_usbd_hid_hid0_enable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_enable_event(); - - return; -} - -void sli_usbd_hid_hid0_disable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_disable_event(); - - return; -} - -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - (void)&class_nbr; - - *p_report_ptr = sli_usbd_hid_hid0_default_desc; - *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); - - sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); - - return; -} - -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - (void)&class_nbr; - - *p_report_ptr = NULL; - *p_report_len = 0; - - sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); - - return; -} - -void sli_usbd_hid_hid0_set_output_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); - - return; -} - -void sli_usbd_hid_hid0_get_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) -{ - (void)&class_nbr; - - memset(p_report_buf, 0, report_len); - - sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); - - return; -} - -void sli_usbd_hid_hid0_set_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); - - return; -} - -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) -{ - (void)&class_nbr; - - *p_protocol = sl_usbd_hid_hid0_default_protocol; - - sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); - - return; -} - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_default_protocol = protocol; - - sl_usbd_hid_hid0_on_set_protocol_event(protocol); - - return; -} - -//**************************************************************************** -// Global functions. - -/* initialize hid0 instance */ -void sli_usbd_hid_hid0_init() -{ - sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; - - uint8_t subclass = 0; - uint8_t protocol = 0; - - uint16_t interval_in = 0; - uint16_t interval_out = 0; - bool ctrl_rd_en = true; - - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_HID_HID0_CONFIGURATIONS; - - /* read subclass, protocol, and country codes */ - subclass = SL_USBD_HID_HID0_SUBCLASS; - protocol = SL_USBD_HID_HID0_PROTOCOL; - country = SL_USBD_HID_HID0_COUNTRY_CODE; - - /* read endpoint parameters */ - interval_in = SL_USBD_HID_HID0_INTERVAL_IN; - interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; - ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; - - /* create HID instance */ - sl_usbd_hid_create_instance( - subclass, - protocol, - country, - interval_in, - interval_out, - ctrl_rd_en, - &sli_usbd_hid_hid0_callbacks, - &class_number); - - /* store class number globally */ - sl_usbd_hid_hid0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_hid_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h deleted file mode 100644 index fa9e5b853a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_class_hid_instances.h +++ /dev/null @@ -1,32 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT -#define SL_USBD_CLASS_HID_INSTANCES_INIT - -#include "sl_usbd_class_hid.h" - -/* class numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_hid_hid0_number; - -/* event handlers for all HID instances */ - -__WEAK void sl_usbd_hid_hid0_on_enable_event(void); -__WEAK void sl_usbd_hid_hid0_on_disable_event(void); -__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); -__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); - -/* init functions for all HID instances */ - -void sli_usbd_hid_hid0_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c deleted file mode 100644 index 0a865bccfc..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.c +++ /dev/null @@ -1,61 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include -#include - -/* template headers */ -#include "sl_usbd_configuration_instances.h" - -/* include config file for the instances */ - -#include - -//**************************************************************************** -// Global variables. - -/* configuration numbers assigned by the USB stack after init */ - -uint8_t sl_usbd_configuration_config0_number = 0; - -//**************************************************************************** -// Global functions. - -/* initialize config0 instance */ -void sli_usbd_configuration_config0_init() -{ - uint8_t attrib = 0; - uint16_t power = 0; - sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; - const char *name = NULL; - uint8_t number = 0; - - /* configuration attributes */ -#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 - attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; -#endif -#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 - attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; -#endif - - /* configuration maximum power (mA) */ - power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; - - /* configuration speed */ - speed = SL_USBD_DEVICE_SPEED_FULL; - - /* configuration name */ - name = SL_USB_CONFIGURATION_CONFIG0_NAME; - - /* create the configuration descriptor */ - sl_usbd_core_add_configuration(attrib, power, speed, name, &number); - - /* store the configuration number globally */ - sl_usbd_configuration_config0_number = number; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h deleted file mode 100644 index 07726e93fe..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/autogen/sl_usbd_configuration_instances.h +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT -#define SL_USBD_CONFIGURATION_INSTANCES_INIT - -/* configuration numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_configuration_config0_number; - -/* init functions for all configuration instances */ - -void sli_usbd_configuration_config0_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h deleted file mode 100644 index 09c0ff4989..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/bspconfig.h +++ /dev/null @@ -1,9 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt deleted file mode 100644 index 8ea7907f60..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append common source files -list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) - -# make var global -set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c deleted file mode 100644 index 5ae69920e9..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage-DEBUG.c +++ /dev/null @@ -1,123 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, - - // 00013000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 19, 237}, - - // 000EE000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // GG11 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c deleted file mode 100644 index e4792d9bb0..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/Device_BlockStorage.c +++ /dev/null @@ -1,123 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - - // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 67}, - - // 00044000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 68, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S deleted file mode 100644 index 39ad790f18..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/common/tx_initialize_low_level.S +++ /dev/null @@ -1,239 +0,0 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Initialize */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ - .global _tx_thread_system_stack_ptr - .global _tx_initialize_unused_memory - .global __RAM_segment_used_end__ - .global _tx_timer_interrupt - .global __main - .global __tx_SVCallHandler - .global __tx_PendSVHandler - .global _vectors - .global __tx_NMIHandler @ NMI - .global __tx_BadHandler @ HardFault - .global __tx_SVCallHandler @ SVCall - .global __tx_DBGHandler @ Monitor - .global __tx_PendSVHandler @ PendSV - .global __tx_SysTickHandler @ SysTick - .global __tx_IntHandler @ Int 0 -@ -@ -SYSTEM_CLOCK = 38000000 -SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) - - .text 32 - .align 4 - .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-M7/GNU */ -@/* 6.0 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_initialize_low_level(VOID) -@{ - .global _tx_initialize_low_level - .thumb_func -_tx_initialize_low_level: -@ -@ /* Disable interrupts during ThreadX initialization. */ -@ - CPSID i -@ -@ /* Set base of available memory to end of non-initialised RAM area. */ -@ - LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ - STR r1, [r0] @ Setup first unused memory pointer -@ -@ /* Setup Vector Table Offset Register. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =__Vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address -@ -@ /* Set system stack pointer from vector value. */ -@ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =__Vectors @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer -@ -@ /* Enable the cycle count register. */ -@ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register -@ -@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] @ Setup SysTick Reload Value - MOV r1, #0x7 @ Build SysTick Control Enable Value - STR r1, [r0, #0x10] @ Setup SysTick Control -@ -@ /* Configure handler priorities. */ -@ - LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers - - LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers - @ Note: SVC must be lowest priority, which is 0xFF - - LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers - @ Note: PnSV must be lowest priority, which is 0xFF - -@ -@ /* Return to caller. */ -@ - BX lr -@} -@ - -@/* Define shells for each of the unused vectors. */ -@ - .global __tx_BadHandler - .thumb_func -__tx_BadHandler: - B __tx_BadHandler - -@ /* added to catch the hardfault */ - - .global __tx_HardfaultHandler - .thumb_func -__tx_HardfaultHandler: - B __tx_HardfaultHandler - - -@ /* added to catch the SVC */ - - .global __tx_SVCallHandler - .thumb_func -__tx_SVCallHandler: - B __tx_SVCallHandler - - -@ /* Generic interrupt handler template */ - .global __tx_IntHandler - .thumb_func -__tx_IntHandler: -@ VOID InterruptHandler (VOID) -@ { - PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function -#endif - -@ /* Do interrupt handler work here */ -@ /* BL .... */ - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function -#endif - POP {r0, lr} - BX LR -@ } - -@ /* System Tick timer interrupt handler */ - .global __tx_SysTickHandler - .global SysTick_Handler - .thumb_func -__tx_SysTickHandler: - .thumb_func -SysTick_Handler: -@ VOID TimerInterruptHandler (VOID) -@ { -@ - PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function -#endif - BL _tx_timer_interrupt -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function -#endif - POP {r0, lr} - BX LR -@ } - - -@ /* NMI, DBG handlers */ - .global __tx_NMIHandler - .thumb_func -__tx_NMIHandler: - B __tx_NMIHandler - - .global __tx_DBGHandler - .thumb_func -__tx_DBGHandler: - B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h deleted file mode 100644 index 158edf847a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/pin_config.h +++ /dev/null @@ -1,259 +0,0 @@ -#ifndef PIN_CONFIG_H -#define PIN_CONFIG_H - -// $[ACMP0] -// [ACMP0]$ - -// $[ACMP1] -// [ACMP1]$ - -// $[ACMP2] -// [ACMP2]$ - -// $[ACMP3] -// [ACMP3]$ - -// $[ADC0] -// [ADC0]$ - -// $[ADC1] -// [ADC1]$ - -// $[BU] -// [BU]$ - -// $[CAN0] -// [CAN0]$ - -// $[CAN1] -// [CAN1]$ - -// $[CMU] -// [CMU]$ - -// $[DBG] -// [DBG]$ - -// $[EBI] -// [EBI]$ - -// $[ETH] -// [ETH]$ - -// $[ETM] -// [ETM]$ - -// $[GPIO] -// [GPIO]$ - -// $[I2C0] -// [I2C0]$ - -// $[I2C1] -// [I2C1]$ - -// $[I2C2] -// [I2C2]$ - -// $[IDAC0] -// [IDAC0]$ - -// $[LCD] -// [LCD]$ - -// $[LESENSE] -// [LESENSE]$ - -// $[LETIMER0] -// [LETIMER0]$ - -// $[LETIMER1] -// [LETIMER1]$ - -// $[LEUART0] -// [LEUART0]$ - -// $[LEUART1] -// [LEUART1]$ - -// $[LFXO] -// [LFXO]$ - -// $[PCNT0] -// [PCNT0]$ - -// $[PCNT1] -// [PCNT1]$ - -// $[PCNT2] -// [PCNT2]$ - -// $[PRS.CH0] -// [PRS.CH0]$ - -// $[PRS.CH1] -// [PRS.CH1]$ - -// $[PRS.CH2] -// [PRS.CH2]$ - -// $[PRS.CH3] -// [PRS.CH3]$ - -// $[PRS.CH4] -// [PRS.CH4]$ - -// $[PRS.CH5] -// [PRS.CH5]$ - -// $[PRS.CH6] -// [PRS.CH6]$ - -// $[PRS.CH7] -// [PRS.CH7]$ - -// $[PRS.CH8] -// [PRS.CH8]$ - -// $[PRS.CH9] -// [PRS.CH9]$ - -// $[PRS.CH10] -// [PRS.CH10]$ - -// $[PRS.CH11] -// [PRS.CH11]$ - -// $[PRS.CH12] -// [PRS.CH12]$ - -// $[PRS.CH13] -// [PRS.CH13]$ - -// $[PRS.CH14] -// [PRS.CH14]$ - -// $[PRS.CH15] -// [PRS.CH15]$ - -// $[PRS.CH16] -// [PRS.CH16]$ - -// $[PRS.CH17] -// [PRS.CH17]$ - -// $[PRS.CH18] -// [PRS.CH18]$ - -// $[PRS.CH19] -// [PRS.CH19]$ - -// $[PRS.CH20] -// [PRS.CH20]$ - -// $[PRS.CH21] -// [PRS.CH21]$ - -// $[PRS.CH22] -// [PRS.CH22]$ - -// $[PRS.CH23] -// [PRS.CH23]$ - -// $[QSPI0] -// [QSPI0]$ - -// $[SDIO] -// [SDIO]$ - -// $[TIMER0] -// [TIMER0]$ - -// $[TIMER1] -// [TIMER1]$ - -// $[TIMER2] -// [TIMER2]$ - -// $[TIMER3] -// [TIMER3]$ - -// $[TIMER4] -// [TIMER4]$ - -// $[TIMER5] -// [TIMER5]$ - -// $[TIMER6] -// [TIMER6]$ - -// $[UART0] -// [UART0]$ - -// $[UART1] -// [UART1]$ - -// $[USART0] -// [USART0]$ - -// $[USART1] -// [USART1]$ - -// $[USART2] -// [USART2]$ - -// $[USART3] -// [USART3]$ - -// $[USART4] -// USART4 CTS on PH8 -#define USART4_CTS_PORT gpioPortH -#define USART4_CTS_PIN 8 -#define USART4_CTS_LOC 4 - -// USART4 RTS on PH9 -#define USART4_RTS_PORT gpioPortH -#define USART4_RTS_PIN 9 -#define USART4_RTS_LOC 4 - -// USART4 RX on PH5 -#define USART4_RX_PORT gpioPortH -#define USART4_RX_PIN 5 -#define USART4_RX_LOC 4 - -// USART4 TX on PH4 -#define USART4_TX_PORT gpioPortH -#define USART4_TX_PIN 4 -#define USART4_TX_LOC 4 - -// [USART4]$ - -// $[USART5] -// [USART5]$ - -// $[USB] -// [USB]$ - -// $[VDAC0] -// [VDAC0]$ - -// $[WFXO] -// [WFXO]$ - -// $[WTIMER0] -// [WTIMER0]$ - -// $[WTIMER1] -// [WTIMER1]$ - -// $[WTIMER2] -// [WTIMER2]$ - -// $[WTIMER3] -// [WTIMER3]$ - -// $[CUSTOM_PIN_NAME] -// [CUSTOM_PIN_NAME]$ - -#endif // PIN_CONFIG_H - diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h deleted file mode 100644 index 5796117234..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_board_control_config.h +++ /dev/null @@ -1,112 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 1 - -// Enable Display -// Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 1 - -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 1 - -// Enable Hall Effect sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_HALL 0 - -// Enable Microphone -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 - -// Enable QSPI Flash -// Default: 0 -#define SL_BOARD_ENABLE_MEMORY_QSPI 0 - -// Enable SD Card -// Default: 0 -#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE -#define SL_BOARD_ENABLE_VCOM_PIN 1 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// SL_BOARD_ENABLE_DISPLAY -// $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA -#define SL_BOARD_ENABLE_DISPLAY_PIN 9 -// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ - -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - -// SL_BOARD_ENABLE_SENSOR_HALL -// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] -#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB -#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 -// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ - -// SL_BOARD_ENABLE_SENSOR_MICROPHONE -// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 -// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ - -// SL_BOARD_ENABLE_MEMORY_QSPI -// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] -#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG -#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 -// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ - -// SL_BOARD_ENABLE_MEMORY_SDCARD -// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] -#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE -#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 -// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h deleted file mode 100644 index 8ec8d17100..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfrco_config.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H -#define SL_DEVICE_INIT_HFRCO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 72 MHz -// Default: cmuHFRCOFreq_72M0Hz -#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h deleted file mode 100644 index 8f04091ef4..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal - -// Frequency <4000000-48000000> -// Default: 50000000 -#define SL_DEVICE_INIT_HFXO_FREQ 50000000 - -// HFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_HFXO_PRECISION 500 - -// CTUNE <0-511> -// Default: 360 -#define SL_DEVICE_INIT_HFXO_CTUNE 132 - -// Advanced Configurations -// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED -// True -// False -// Default: false -#define SL_DEVICE_INIT_HFXO_AUTOSTART false - -// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED -// True -// False -// Default: false -#define SL_DEVICE_INIT_HFXO_AUTOSELECT false - -// - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h deleted file mode 100644 index 79b1541af8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfrco_config.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H -#define SL_DEVICE_INIT_LFRCO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Duty Cycling of Vref -// Default: 0 -// Setting this configuration to 1 puts the LFRCO in duty cycle mode by -// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. -// This helps reduce current consumption by ~100nA in EM2, but will result -// in slightly worse accuracy especially at high temperatures. -// To improve the average LFRCO frequency accuracy, make sure ENCHOP -// and ENDEM configs are also set. -#define SL_DEVICE_INIT_LFRCO_ENVREF 0 - -// Enable Comparator Chopping -// Default: 1 -// Setting this configuration to 1 enables LFRCO comparator chopping by -// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. -// Setting this bit, along with ENDEM, helps improve the average LFRCO -// frequency accuracy. -#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 - -// Enable Dynamic Element Matching -// Default: 1 -// Setting this configuration to 1 enables dynamic element matching by -// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. -// Setting this bit, along with ENCHOP, helps improve the average LFRCO -// frequency accuracy. -#define SL_DEVICE_INIT_LFRCO_ENDEM 1 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h deleted file mode 100644 index 46c38725c1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 70 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles -// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles -// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles -// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles -// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles -// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles -// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles -// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles -// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default -// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT -#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h deleted file mode 100644 index 41622d2e20..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_onewire_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H -#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_ONEWIRE -// $[USART_SL_IOSTREAM_USART_ONEWIRE] -#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 - -// USART0 TX on PC11 -#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE -#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 -#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 - -// USART0 RX on PC10 -#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE -#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 -#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 - -// [USART_SL_IOSTREAM_USART_ONEWIRE]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h deleted file mode 100644 index 59d33b8885..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,112 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 - -// USART4 TX on PH4 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 -#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 - -// USART4 RX on PH5 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 -#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 - -// USART4 CTS on PH8 -#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 -#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 - -// USART4 RTS on PH9 -#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 -#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h deleted file mode 100644 index 4f20db4a24..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_memory_config.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef SL_MEMORY_CONFIG_H -#define SL_MEMORY_CONFIG_H - -// These parameters are meant to be set in the target CMakeLists.txt file -#ifndef SL_STACK_SIZE -#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" -#endif - -#ifndef SL_HEAP_SIZE -#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" -#endif - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index b9b92ff77c..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 - -// USART4 TX on PH4 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_TX_PIN 4 -#define SL_UARTDRV_USART_VCOM_TX_LOC 4 - -// USART4 RX on PH5 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_RX_PIN 5 -#define SL_UARTDRV_USART_VCOM_RX_LOC 4 - -// USART4 CTS on PH8 -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 -#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 - -// USART4 RTS on PH9 -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 -#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h deleted file mode 100644 index 9c1ac2d7b1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_acm0_config.h +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H -#define SL_USBD_CDC_ACM_ACM0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Class Configuration - -// Configuration(s) to add this class instance to -// Default: all -// Comma separated list of configuration instances (like inst0, inst1) -// that this CDC ACM class instance will be attached to. You can -// use "all" to attach the class to all configs, or use an empty -// string if you do not want to attach the interface to any configuration. -#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" - -// - -// Protocol Details - -// Line State Notification Interval (ms) -// Default: 64 -// Line State Notification Interval (ms). -#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 - -// - -// Call Management - -// Enable call management -// Default: 1 -// If set to 1, the host is informed that this ACM instance -// has call management capabilities. -#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 - -// Call management interface -// <1=> Over DCI -// <0=> Over CCI -// Default: 1 -// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created -// along with the CCI interface. Otherwise, only the CCI will be created -// and it will be used for both data and call management. -#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h deleted file mode 100644 index 9e480375d0..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_hid0_config.h +++ /dev/null @@ -1,143 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_HID_HID0_CONFIG_H -#define SL_USBD_HID_HID0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Class Configuration - -// Configuration(s) to add this class instance to -// Default: all -// Comma separated list of configuration instances (like inst0, inst1) -// that this HID class instance will be attached to. You can -// use "all" to attach the class to all configs, or use an empty -// string if you do not want to attach the interface to any configuration. -#define SL_USBD_HID_HID0_CONFIGURATIONS "all" - -// - -// Type Codes - -// Subclass code -// None -// Boot -// Default: SL_USBD_HID_SUBCLASS_BOOT -// This defines the standard USB subclass code for this interface. -// For most use cases, you can just select "Boot". -#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT - -// Protocol code -// None -// Keyboard -// Mouse -// Default: SL_USBD_HID_PROTOCOL_MOUSE -// You can choose "Mouse" or "Keyboard" depending on what functionality -// this HID class instance will provide. -#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE - -// Country code -// Not supported -// Arabic -// Belgian -// Canadian Multilingual -// Canadian French -// Czech Republic -// Danish -// Finnish -// French -// German -// Greek -// Hebrew -// Hungary -// International -// Italian -// Japan Katakana -// Korean -// Latin American -// Netherlands Dutch -// Norwegian -// Persian Farsi -// Poland -// Portuguese -// Russia -// Slovakia -// Spanish -// Swedish -// Swiss French -// Swiss German -// Switzerland -// Taiwan -// Turkish Q -// Turkish F -// United Kingdom -// United States -// Yugoslavia -// Default: SL_USBD_HID_COUNTRY_CODE_US -// If this instance is implementing a keyboard interface, this -// field helps the host operating system know which layout/language -// the keyboard is manufactured for, or which country/localization -// setting to use by default. -#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US - -// - -// Protocol Details - -// IN polling interval -// <1=> 1ms -// <2=> 2ms -// <4=> 4ms -// <8=> 8ms -// <16=> 16ms -// <32=> 32ms -// <64=> 64ms -// <128=> 128ms -// <256=> 256ms -// <512=> 512ms -// <1024=> 1024ms -// <2048=> 2048ms -// <4096=> 4096ms -// <8192=> 8192ms -// <16384=> 16384ms -// <32768=> 32768ms -// Default: 2 -// Polling interval for input transfers, in milliseconds. -// It must be a power of 2. -#define SL_USBD_HID_HID0_INTERVAL_IN 2 - -// OUT polling interval -// <1=> 1ms -// <2=> 2ms -// <4=> 4ms -// <8=> 8ms -// <16=> 16ms -// <32=> 32ms -// <64=> 64ms -// <128=> 128ms -// <256=> 256ms -// <512=> 512ms -// <1024=> 1024ms -// <2048=> 2048ms -// <4096=> 4096ms -// <8192=> 8192ms -// <16384=> 16384ms -// <32768=> 32768ms -// Default: 2 -// Polling interval for input transfers, in milliseconds. -// It must be a power of 2. -#define SL_USBD_HID_HID0_INTERVAL_OUT 2 - -// Enable Control Read -// Default: 1 -// Enable read operations through the control transfers. -#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h deleted file mode 100644 index 53ccff0cd9..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_class_winusb_config.h +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H -#define SL_USBD_VENDOR_WINUSB_CONFIG_H - -//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" - -// <<< Use Configuration Wizard in Context Menu >>> - -// Class Configuration - -// Configuration(s) to add this class instance to -// Default: all -// Comma separated list of configuration instances (like inst0, inst1) -// that this vendor class instance will be attached to. You can -// use "all" to attach the class to all configs, or use an empty -// string if you do not want to attach the interface to any configuration. -#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" - -// - -// Protocol Details - -// Add interrupt endpoints -// Default: 0 -// Specifies whether we should add IN and OUT endpoints to this -// vendor class interface. -#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 - -// Endpoint interval -// <1=> 1ms -// <2=> 2ms -// <4=> 4ms -// <8=> 8ms -// <16=> 16ms -// <32=> 32ms -// <64=> 64ms -// <128=> 128ms -// <256=> 256ms -// <512=> 512ms -// <1024=> 1024ms -// <2048=> 2048ms -// <4096=> 4096ms -// <8192=> 8192ms -// <16384=> 16384ms -// <32768=> 32768ms -// Default: 2 -// Polling interval for input/output transfers, in milliseconds. -// It must be a power of 2. -#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h deleted file mode 100644 index a70da59041..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_config0_config.h +++ /dev/null @@ -1,51 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H -#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Configuration Settings - -// Configuration Name -// Default: "Main Configuration" -// This creates a string descriptor that the USB host -// can use to retrieve the name of this USB configuration descriptor. -// It can be scanned with "sudo lsusb -vv" on Linux. It appears next -// to iConfiguration field. -#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" - -// Power Source -// <0=> Bus-Powered -// <1=> Self-Powered -// Default: 1 -// Indicates whether the device will be powered using USB bus or -// or using a self-power source (like battery or a debugger) -// if the host configures the device using this configuration. -#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 - -// Enable Remote Wakeup -// Default: 0 -// Enables or disables remote wakeup feature. -#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 - -// Maximum Power (mA) -// <100=> 100 mA -// <500=> 500 mA -// Default: 100 -// Specifies the maximum current that the device will draw. -// Most USB devices consume 100mA at most, but the USB standard -// allows the device to consume up to 500mA. When the host -// operating system scans this value, it will configure the USB port -// on the host controller to allow the device to consume the -// configured current. -#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 - -// - -// <<< end of configuration section >>> -#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h deleted file mode 100644 index 1058079e4f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_core_config.h +++ /dev/null @@ -1,199 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CONFIG_H -#define SL_USBD_CONFIG_H - -extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; - -// <<< Use Configuration Wizard in Context Menu >>> - -// USB Configuration - -// Auto-start USB device -// Default: 1 -// If enabled, the USB device will be automatically started up, -// using sl_usbd_core_start_device(), by the core task (which starts -// running after kernel scheduler is ready) when the USB stack is all -// initialized. You can disable this config if you want to call -// sl_usbd_core_start_device() manually from your code. This might -// be helpful if you do not want USB to start anytime before all -// your initializations are complete, or if you want to enable/disable -// USB on demand. -#define SL_USBD_AUTO_START_USB_DEVICE 1 - -// Enable SCSI 64-Bit LBA -// Default: 0 -// MSC SCSI Configuration for enabling 64-bit LBA support. -#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 - -// - -// USB Core Configuration - -// Core Pools - -// Number of configurations <1-255> -// Default: 1 -// The total number of configurations. -#define SL_USBD_CONFIGURATION_QUANTITY 1 - -// Number of interfaces <1-255> -// Default: 10 -// The total number of interfaces (for all of your USB configurations). -#define SL_USBD_INTERFACE_QUANTITY 10 - -// Number of alternate interfaces <1-255> -// Default: 10 -// The total number of alternate interfaces (for all of your USB configurations). -// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY -#define SL_USBD_ALT_INTERFACE_QUANTITY 10 - -// Number of interface groups <0-255> -// Default: 20 -// The total number of interface groups (for all of your USB configurations). -#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 - -// Number of endpoint descriptors <1-255> -// Default: 20 -// The total number of endpoint descriptors (for all of your USB configurations). -#define SL_USBD_DESCRIPTOR_QUANTITY 20 - -// Number of strings <0-100> -// Default: 30 -// The total number of strings per device. -#define SL_USBD_STRING_QUANTITY 30 - -// Number of opened endpoints <2-255> -// Default: 20 -// The total number of opened endpoints per device. -#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 - -// - -// Core Task - -// Stack size of USBD core task in bytes -// Default: 4096 -// Stack size in bytes of the USBD core task. -#define SL_USBD_TASK_STACK_SIZE 4096U - -// Priority of USBD core task -#define SL_USBD_TASK_PRIORITY 5 - -// USB CDC Configuration - -// CDC Pools - -// Number of class instances <1-255> -// Default: 2 -// Number of class instances. -#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Default: 1 -// Number of configurations. -#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 - -// Number of subclass instances <1-255> -// Default: 2 -// Number of subclass instances. -#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 - -// Number of data interfaces <1-255> -// Default: 2 -// Number of data interfaces. -#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 - -// - -// - -// USB HID Configuration - -// HID Pools - -// Number of class instances <1-255> -// Default: 2 -// Number of class instances. -#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Default: 1 -// Number of configurations. -#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 - -// Number of report ids <0-255> -// Default: 2 -// Number of report ids. -#define SL_USBD_HID_REPORT_ID_QUANTITY 2 - -// Number of push/pop items <0-255> -// Default: 0 -// Number of push/pop items. -#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 - -// - -// HID Task - -// Stack size of USBD HID timer task in bytes -// Default: 2048 -// HID Timer task stack size in bytes. -#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 - -// Priority of USBD HID timer task -#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 - -// USB MSC Configuration - -// MSC Pools - -// Number of class instances <1-255> -// Default: 2 -// Number of class instances. -#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Default: 1 -// Number of configurations. -#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 - -// Number of Logical Units per class instance <1-255> -// Default: 2 -// Number of Logical Units. -#define SL_USBD_MSC_LUN_QUANTITY 2 - -// Size of data buffer per class instance in bytes <1-4294967295> -// Default: 512 -// Size of data buffer in bytes. -#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 - -// - -// - -// USB Vendor Configuration - -// Vendor Pools - -// Number of class instances <1-255> -// Number of class instances. -#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Number of configurations. -#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 - -// pointer to USB Class Vendor description -#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription - -// - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h deleted file mode 100644 index 1b672dc998..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/sl_usbd_device_config.h +++ /dev/null @@ -1,60 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_DEVICE_CONFIG_H -#define SL_USBD_DEVICE_CONFIG_H - -extern char *UsbSerialNumber[]; - -// <<< Use Configuration Wizard in Context Menu >>> - -// USB Device Configuration - -// Device Vendor ID -// Device vendor ID: Silabs. -#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 - -// Device Product ID -// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board -#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC - -// Device Release Number -// Default: 0x0100 -// Device release number. -#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 - -// Device Manufacturer Name -// Device manufacturer string. -#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" - -// Device Product Name -// Device product string. -// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen -#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" - -// Device Serial Number -// Device serial number string. -#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber - -// Device Language ID -// Arabic -// Chinese -// US English -// UK English -// French -// German -// Greek -// Italian -// Portuguese -// Sanskrit -// ID of language of strings of device. -// Default: USBD_LANG_ID_ENGLISH_US -#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h deleted file mode 100644 index 118a7c901a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/config/uartdrv_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV configuration file. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ -#define __SILICON_LABS_UARTDRV_CONFIG_H__ - -/***************************************************************************//** - * @addtogroup uartdrv - * @{ - ******************************************************************************/ -/// Size of the receive operation queue. -/// @details -/// The maximum number of receive operations that can be queued up for one -/// driver instance before @ref UARTDRV_Receive() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 -#endif - -/// Size of the transmit operation queue. -/// @details -/// The maximum number of transmit operations that can be queued up for one -/// driver instance before @ref UARTDRV_Transmit() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 -#endif - -// <<< Use Configuration Wizard in Context Menu >>> -// UARTDRV Settings - -/// Set to 1 to include flow control support -#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -// Flow control support -// <1=> Enable -// <0=> Disable -// Default: 1 -#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 -#endif - -/// Maximum number of driver instances. -#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) -// Maximum number of driver instances -// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 -// Default: 4 -#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 -#endif - -/// UART software flow control code: request peer to start TX -#if !defined(UARTDRV_FC_SW_XON) -// UART software flow control code: request peer to start TX -// Default: 0x11 -#define UARTDRV_FC_SW_XON 0x11 -#endif - -/// UART software flow control code: request peer to stop TX -#if !defined(UARTDRV_FC_SW_XOFF) -// UART software flow control code: request peer to stop TX -// Default: 0x13 -#define UARTDRV_FC_SW_XOFF 0x13 -#endif - -/// UART enable reception when sleeping. -#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) -// Enable reception when sleeping -// Enable reception when sleeping will use the power manager and add EM1 -// requirement during receive operations that use DMA. -// <1=> Enable -// <0=> Disable -// Default: 1 -#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 -#endif - -// - -// <<< end of configuration section >>> - -/** @} (end addtogroup uartdrv) */ - -#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json deleted file mode 100644 index a4a945a94e..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/launch.json +++ /dev/null @@ -1,83 +0,0 @@ -{ - "version": "0.2.0", - "configurations": [ - { - "name": "SL_STK3701A nanoBooter", - "type": "cppdbg", - "request": "launch", - "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "program": "${workspaceRoot}/build/nanoBooter.elf", - "MIMode": "gdb", - "debugServerPath": "/JLinkGDBServerCL.exe", - "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", - "stopAtEntry": false, - "serverStarted": "Connected to target", - "cwd": "${cwd}", - "setupCommands": [ - { - "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " - }, - { - "text": "target extended-remote localhost:2331" - }, - { - "text": "monitor halt" - }, - { - "text": "monitor reset" - }, - { - "text": "load" - } - ], - "launchCompleteCommand": "None", - "logging": { - "moduleLoad": false, - "trace": true, - "engineLogging": false, - "programOutput": false, - "traceResponse": false, - "exceptions": true - } - }, - { - "name": "SL_STK3701A nanoCLR", - "type": "cppdbg", - "request": "launch", - "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "program": "${workspaceRoot}/build/nanoCLR.elf", - "MIMode": "gdb", - "debugServerPath": "/JLinkGDBServerCL.exe", - "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", - "stopAtEntry": false, - "serverStarted": "Connected to target", - "cwd": "${cwd}", - "setupCommands": [ - { - "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " - }, - { - "text": "target extended-remote localhost:2331" - }, - { - "text": "monitor halt" - }, - { - "text": "monitor reset" - }, - { - "text": "load" - } - ], - "launchCompleteCommand": "None", - "logging": { - "moduleLoad": false, - "trace": true, - "engineLogging": false, - "programOutput": false, - "traceResponse": false, - "exceptions": true - } - } - ] -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt deleted file mode 100644 index 0b7c048e56..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoBooter source files -list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) - -# make var global -set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld deleted file mode 100644 index 8941c58e5c..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ /dev/null @@ -1,235 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if flash0 usage exceeds flash0 size */ - ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") -} - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld deleted file mode 100644 index 98793699a7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/efm32gg11b_booter.ld +++ /dev/null @@ -1,235 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if flash0 usage exceeds flash0 size */ - ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") -} - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c deleted file mode 100644 index e0a0dcde98..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/main.c +++ /dev/null @@ -1,186 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include - -#include - -#include -// #include - -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND -#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; - -// byte pool configuration and definitions -#define DEFAULT_BYTE_POOL_SIZE 4096 -TX_BYTE_POOL byte_pool_0; -ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; - -// threads definitions and configurations - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// blink thread -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // initialize block storage list and devices - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - BlockStorageList_Initialize(); - BlockStorage_AddDevices(); - - // initialize configuration manager - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it here to have access to network configuration blocks - // ConfigurationManager_Initialize(); - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - (uint8_t *)blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_init(); - sli_usbd_configuration_config0_init(); - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif - - // report successfull nanoBooter execution - ReportSuccessfullNanoBooter(); -} - -// Application entry point. -int main(void) -{ - // Initialize the board - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // configure S2 switch for input - GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); - - // init boot clipboard - InitBootClipboard(); - - // check if there is a request to remain on nanoBooter - // or if there is an error code for a missing deployment - if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // do not load CLR, remain in nanoBooter - } - else - { - // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR - // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter - if (GPIO_PinInGet(gpioPortE, 8) != 0) - { - // check for valid CLR image - // we are checking for a valid image at the deployment address, which is pointing to the CLR address - if (CheckValidCLRImage((uint32_t)&__deployment_start__)) - { - // there seems to be a valid CLR image - - // need to change HF clock to internal RCO so the CLR can boot smoothly - CMU_CLOCK_SELECT_SET(HF, HFRCO); - - // launch nanoCLR - LaunchCLR((uint32_t)&__deployment_start__); - } - } - } - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in deleted file mode 100644 index ec5e9be940..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoBooter/target_board.h.in +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOBOOTER_H_ -#define _TARGET_BOARD_NANOBOOTER_H_ - -#include - -#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" - -#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt deleted file mode 100644 index 966b5a01c7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoCLR source files -list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) -list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) - -if(GECKO_FEATURE_USBD_HID) - list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) -endif() - -# make var global -set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld deleted file mode 100644 index e4ef8fc200..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ /dev/null @@ -1,246 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld deleted file mode 100644 index 98d83797d3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/efm32gg11b_CLR.ld +++ /dev/null @@ -1,246 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1772k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00042000, len = 1772k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c deleted file mode 100644 index b455443582..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/main.c +++ /dev/null @@ -1,191 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -// #include - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); -extern void UsbStackInit(); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - GPIO_PinOutToggle(gpioPortB, 12); - - UsbStackInit(); - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = true; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp deleted file mode 100644 index e754dd5f80..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/nanoHAL.cpp +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in deleted file mode 100644 index be11ba01ad..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/target_board.h.in +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOCLR_H_ -#define _TARGET_BOARD_NANOCLR_H_ - -#include - -#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" - -#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c deleted file mode 100644 index f058c33353..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/nanoCLR/usb_hid_app.c +++ /dev/null @@ -1,244 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include -#include -#include - -#include -#include - -#include -#include "sl_usbd_class_hid.h" -#include - -// Task configuration -#define TASK_STACK_SIZE 512u -#define TASK_PRIO 5u -#define TASK_DELAY_MS 100u - -#define USB_HID_REPORT_LEN 4u - -// FreeRTOS Task handle -static TX_THREAD task_handle; -uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; - -// Mouse report buffer. -__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; - -static void hid_task(uint32_t p_arg); - -// Initialize application. -void usb_device_hid_app_init(void) -{ - uint16_t status; - - // Create application task - status = tx_thread_create( - &task_handle, - "USB HID task", - hid_task, - (uint32_t)&sl_usbd_hid_hid0_number, - hidThreadStack, - TASK_STACK_SIZE, - TASK_PRIO, - TASK_PRIO, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - _ASSERTE(status == TX_SUCCESS); -} - -// hid_task() -// Perform HID writes to host. -// @param p_arg Task argument pointer. Class number in this case. -static void hid_task(uint32_t p_arg) -{ - uint8_t class_nbr = *(uint8_t *)p_arg; - bool x_is_pos = true; - bool y_is_pos = true; - bool conn; - sl_status_t status; - uint32_t xfer_len = 0; - const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); - - usb_hid_report_buffer[0u] = 0u; - usb_hid_report_buffer[1u] = 0u; - - while (true) - { - - // Wait for device connection. - status = sl_usbd_hid_is_enabled(class_nbr, &conn); - _ASSERTE(status == SL_STATUS_OK); - - while (conn != true) - { - tx_thread_sleep(xDelay); - - status = sl_usbd_hid_is_enabled(class_nbr, &conn); - - _ASSERTE(status == SL_STATUS_OK); - } - - // Emulates back and fourth movement. - ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; - ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; - - x_is_pos = !x_is_pos; - y_is_pos = !y_is_pos; - - // Send report. - status = - sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); - - // Delay Task - tx_thread_sleep(xDelay); - } -} - -// USB bus events. -void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) -{ - switch (event) - { - case SL_USBD_EVENT_BUS_CONNECT: - // called when usb cable is inserted in a host controller - break; - - case SL_USBD_EVENT_BUS_DISCONNECT: - // called when usb cable is removed from a host controller - break; - - case SL_USBD_EVENT_BUS_RESET: - // called when the host sends reset command - break; - - case SL_USBD_EVENT_BUS_SUSPEND: - // called when the host sends suspend command - break; - - case SL_USBD_EVENT_BUS_RESUME: - // called when the host sends wake up command - break; - - default: - break; - } -} - -// USB configuration events. -void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) -{ - (void)config_nbr; - - switch (event) - { - case SL_USBD_EVENT_CONFIG_SET: - // called when the host sets a configuration after reset - break; - - case SL_USBD_EVENT_CONFIG_UNSET: - // called when a configuration is unset due to reset command - break; - - default: - break; - } -} - -// HID mouse0 instance Enable event. -void sl_usbd_hid_hid0_on_enable_event(void) -{ - // Called when the HID device is connected to the USB host and a - // RESET transfer succeeded. -} - -// HID mouse0 instance Disable event. -void sl_usbd_hid_hid0_on_disable_event(void) -{ - // Called when the HID device is disconnected to the USB host (cable removed). -} - -// Hook function to pass the HID descriptor of the mouse0 instance. -void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - // Called during the HID mouse0 instance initialization so the USB stack - // can retrieve its HID descriptor. - (void)p_report_ptr; - (void)p_report_len; -} - -// Hook function to pass the HID PHY descriptor. -void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - // Called during the HID mouse0 instance initialization so the USB stack - // can retrieve the its HID physical descriptor. - (void)p_report_ptr; - (void)p_report_len; -} - -// Notification of a new set report received on control endpoint. -// @param report_id Report ID. -// @param p_report_buf Pointer to report buffer. -// @param report_len Length of report, in octets. -void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) -{ - // This function is called when host issues a SetReport request. - // The application can take action in function of the report content. - - (void)report_id; - (void)p_report_buf; - (void)report_len; -} - -// Get HID feature report corresponding to report ID. -// @param report_id Report ID. -// @param p_report_buf Pointer to feature report buffer. -// @param report_len Length of report, in octets. -// @note (1) Report ID must not be written into the feature report buffer. -void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) -{ - // This function is called when host issues a GetReport(feature) request. - // The application can provide the report to send by copying it in p_report_buf. - - (void)report_id; - (void)p_report_buf; - (void)report_len; -} - -// Set HID feature report corresponding to report ID. -// @param report_id Report ID. -// @param p_report_buf Pointer to feature report buffer. -// @param report_len Length of report, in octets. -// @note (1) Report ID is not present in the feature report buffer. -void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) -{ - // This function is called when host issues a SetReport(Feature) request. - // The application can take action in function of the provided report in p_report_buf. - - (void)report_id; - (void)p_report_buf; - (void)report_len; -} - -// Retrieve active protocol: BOOT or REPORT protocol. -// @param p_protocol Pointer to variable that will receive the protocol type. -void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) -{ - // This function is called when host issues a GetProtocol request. - // The application should return the current protocol. - (void)p_protocol; -} - -// Store active protocol: BOOT or REPORT protocol. -// @param protocol Protocol. -void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) -{ - // This function is called when host issues a SetProtocol request. - // The application should apply the new protocol. - (void)protocol; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c deleted file mode 100644 index ad32a4cff7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.c +++ /dev/null @@ -1,19 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -extern struct BlockStorageDevice Device_BlockStorage; -extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; -extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; - -void BlockStorage_AddDevices() -{ - BlockStorageList_AddDevice( - (BlockStorageDevice *)&Device_BlockStorage, - &SL_MscFlash_BlockStorageInterface, - &Device_BlockStorageConfig, - false); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h deleted file mode 100644 index 0771bccc7b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_BlockStorage.h +++ /dev/null @@ -1,12 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef _TARGETPAL_BLOCKSTORAGE_H_ -#define _TARGETPAL_BLOCKSTORAGE_H_ 1 - -// this device has 1 block storage devices -#define TARGET_BLOCKSTORAGE_COUNT 1 - -#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp deleted file mode 100644 index 45f236e7a8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.cpp +++ /dev/null @@ -1,26 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -////////// -// I2C0 // -////////// - -// SCL: PA1 -// SDA: PA0 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) - -////////// -// I2C1 // -////////// - -// SCL: PC5 -// SDA: PC4 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h deleted file mode 100644 index ff99df51a3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_i2c_config.h +++ /dev/null @@ -1,4 +0,0 @@ -// Copyright Skyworks Solutions, Inc. All Rights Reserved. - -#define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp deleted file mode 100644 index 6c5b724749..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.cpp +++ /dev/null @@ -1,48 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) -// num is the USART index. For example, if using USART0 use 0. - -////////// -// SPI0 // -////////// - -// USART0 -// SCK: PE12 -// MOSI: PE10 -// MISO: PE11 -// CS: PE13 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(0, 0, 0, 0, 0) - -////////// -// SPI1 // -////////// - -// USART1 -// SCK: PD2 -// MOSI: PD0 -// MISO: PD1 -// CS: PD3 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(1, 1, 1, 1, 1) - -////////// -// SPI2 // -////////// - -// USART2 -// SCK: PB5 -// MOSI: PB3 -// MISO: PB4 -// CS: PB6 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h deleted file mode 100644 index bdfea3503d..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_com_sky_nf_dev_spi_config.h +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#define GECKO_USE_SPI0 TRUE -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c deleted file mode 100644 index c2100dc5c5..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.c +++ /dev/null @@ -1,27 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include -#include "target_board.h" -#include -#include - -HAL_SYSTEM_CONFIG HalSystemConfig = { - {true}, // HAL_DRIVER_CONFIG_HEADER Header; - - 1, // ConvertCOM_DebugHandle(1), - 0, // ConvertCOM_DebugHandle(0), - 921600, - 0, // STDIO = COM2 or COM1 - - {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, - {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; - -HAL_TARGET_CONFIGURATION g_TargetConfiguration; - -// this target can use J-Link for updates -inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); -inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in deleted file mode 100644 index e5a3715d66..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_common.h.in +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_COMMON_H_ -#define _TARGET_COMMON_H_ - -#include - -///////////////////////////////////////////////////////////////////////////////////////// -// The following addresses and sizes should be filled in according to the SoC data-sheet -// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR - -// RAM base address -#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) -// RAM size -#define RAM1_MEMORY_Size ((uint32_t)0x000080000) - -// FLASH base address -#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) -// FLASH size -#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) - -///////////////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////// -#define TARGETNAMESTRING "@TARGET_NAME@" -#define PLATFORMNAMESTRING "GGECKO_S1" -////////////////////////////////////////////// - -////////////////////////////////////////////// -// set Wire Protocol packet size -// valid sizes are 1024, 512, 256, 128 -// check Monitor_Ping_Source_Flags enum -#define WP_PACKET_SIZE 512U -////////////////////////////////////////////// - -///////////////////////////////////// -#define PLATFORM_HAS_RNG TRUE -///////////////////////////////////// - -///////////////////////////////////// -//#define EVENTS_HEART_BEAT -///////////////////////////////////// - -#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp deleted file mode 100644 index 51d7628e5a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.cpp +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// No ADC on Si5400 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF - -/* - -#include - -// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel -// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel -// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel -// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel -// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel -// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel -// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel -// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel -// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel -// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) -// PE6 (Gecko APORT3X CH6) ADC Cal Channel - -const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - - // IMON0 - {0, adcPosSelAPORT1XCH6}, - // - {0, adcPosSelAPORT2XCH7}, - // - {0, adcPosSelAPORT1XCH8}, - // - {0, adcPosSelAPORT2XCH9}, - // - {0, adcPosSelAPORT1XCH10}, - // - {0, adcPosSelAPORT2XCH11}, - // - {0, adcPosSelAPORT1XCH12}, - // - {0, adcPosSelAPORT2XCH13}, - // - {0, adcPosSelAPORT1XCH14}, - // - {0, adcPosSelAPORT2XCH15}, - // - {0, adcPosSelAPORT3XCH6}, -}; - -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h deleted file mode 100644 index 03d414a5c1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nano_gg_adc_config.h +++ /dev/null @@ -1,9 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// No ADC on Si5400 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF - -#define GECKO_USE_ADC0 FALSE -#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp deleted file mode 100644 index 949567e829..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.cpp +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h deleted file mode 100644 index b5d0ffb355..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_nf_dev_onewire_config.h +++ /dev/null @@ -1,13 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////// -// UART0 // -/////////// - -// enable USART0 -#define NF_ONEWIRE_USE_USART0 TRUE - -// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c deleted file mode 100644 index efb9bced52..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.c +++ /dev/null @@ -1,7 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h deleted file mode 100644 index d560ea678f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_stdio_config.h +++ /dev/null @@ -1,5 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp deleted file mode 100644 index 370059f6f8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.cpp +++ /dev/null @@ -1,6 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h deleted file mode 100644 index 370059f6f8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_adc_config.h +++ /dev/null @@ -1,6 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp deleted file mode 100644 index 6e7b275464..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.cpp +++ /dev/null @@ -1,32 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -/* - -////////// -// I2C0 // -////////// - -// pin configuration for I2C0 -// port for I2C0_SCL is: PA1 -// port for I2C0_SDA is: PA0 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) - -////////// -// I2C1 // -////////// - -// pin configuration for I2C1 -// port for I2C1_SCL is: PC5 -// port for I2C1_SDA is: PC4 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h deleted file mode 100644 index c81f83afe3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_i2c_config.h +++ /dev/null @@ -1,8 +0,0 @@ -// Copyright Skyworks Solutions, Inc. All Rights Reserved. - -/* - -#define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp deleted file mode 100644 index 7653e6d1c4..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_pwm_config.cpp +++ /dev/null @@ -1,17 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { - - // using WTIMER0, CC0, PC1, location 7 - {0, 0, gpioPortC, 1, 7}, - // using WTIMER1, CC2, PI1, location 5 - {1, 2, gpioPortI, 1, 5}, - -}; - -const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp deleted file mode 100644 index 3bf95a0eb3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.cpp +++ /dev/null @@ -1,35 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -/* -////////// -// SPI1 // -////////// - -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI1_SCK: PD2, location 1 -// SPI1_MOSI: PD0, location 1 -// SPI1_MISO: PD1, location 1 -// SPI1_CS: PD3, location 1 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(1, 1, 1, 1) - -////////// -// SPI2 // -////////// - -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI2_SCK: PF8, location 1 -// SPI2_MOSI: PF6, location 1 -// SPI2_MISO: PF7, location 1 -// SPI2_CS: PF9, location 1 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(2, 4, 4, 4) - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h deleted file mode 100644 index 409945557b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_device_spi_config.h +++ /dev/null @@ -1,7 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp deleted file mode 100644 index b7c0d87a23..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.cpp +++ /dev/null @@ -1,4 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h deleted file mode 100644 index b2d2dec961..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_system_io_ports_config.h +++ /dev/null @@ -1,5 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h deleted file mode 100644 index 40c92111ed..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_tx_user.h +++ /dev/null @@ -1,206 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////// -// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file -// for nanoBooter and another for nanoCLR. -/////////////////////////////////////////////////////////////////////////////////////////// - -#ifndef TX_USER_H -#define TX_USER_H - -#define TX_TIMER_TICKS_PER_SECOND 1000 - -/* Define various build options for the ThreadX port. The application should either make changes - here by commenting or un-commenting the conditional compilation defined OR supply the defines - though the compiler's equivalent of the -D option. - - For maximum speed, the following should be defined: - - TX_MAX_PRIORITIES 32 - TX_DISABLE_PREEMPTION_THRESHOLD - TX_DISABLE_REDUNDANT_CLEARING - TX_DISABLE_NOTIFY_CALLBACKS - TX_NOT_INTERRUPTABLE - TX_TIMER_PROCESS_IN_ISR - TX_REACTIVATE_INLINE - TX_DISABLE_STACK_FILLING - TX_INLINE_THREAD_RESUME_SUSPEND - - For minimum size, the following should be defined: - - TX_MAX_PRIORITIES 32 - TX_DISABLE_PREEMPTION_THRESHOLD - TX_DISABLE_REDUNDANT_CLEARING - TX_DISABLE_NOTIFY_CALLBACKS - TX_NOT_INTERRUPTABLE - TX_TIMER_PROCESS_IN_ISR - - Of course, many of these defines reduce functionality and/or change the behavior of the - system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR - results in faster and smaller code, however, it increases the amount of processing in the ISR. - In addition, some services that are available in timers are not available from ISRs and will - therefore return an error if this option is used. This may or may not be desirable for a - given application. */ - -/* Override various options with default values already assigned in tx_port.h. Please also refer - to tx_port.h for descriptions on each of these options. */ - -/* -#define TX_MAX_PRIORITIES 32 -#define TX_MINIMUM_STACK ???? -#define TX_THREAD_USER_EXTENSION ???? -#define TX_TIMER_THREAD_STACK_SIZE ???? -#define TX_TIMER_THREAD_PRIORITY ???? -*/ - -/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls - should be processed within the a system timer thread or directly in the timer ISR. - By default, the timer thread is used. When the following is defined, the timer expiration - processing is done directly from the timer ISR, thereby eliminating the timer thread control - block, stack, and context switching to activate it. */ - -/* -#define TX_TIMER_PROCESS_IN_ISR -*/ - -/* Determine if in-line timer reactivation should be used within the timer expiration processing. - By default, this is disabled and a function call is used. When the following is defined, - reactivating is performed in-line resulting in faster timer processing but slightly larger - code size. */ - -#define TX_REACTIVATE_INLINE - -/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, - which places an 0xEF pattern in each byte of each thread's stack. This is used by - debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ - -/* -#define TX_DISABLE_STACK_FILLING -*/ - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -/* -#define TX_ENABLE_STACK_CHECKING -*/ - -/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is - enabled. If the application does not use preemption-threshold, it may be disabled to reduce - code size and improve performance. */ - -/* -#define TX_DISABLE_PREEMPTION_THRESHOLD -*/ - -/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears - the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary - clearing of ThreadX global variables. */ - -#define TX_DISABLE_REDUNDANT_CLEARING - -/* Determine if no timer processing is required. This option will help eliminate the timer - processing when not needed. The user will also have to comment out the call to - tx_timer_interrupt, which is typically made from assembly language in - tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR - must also be used. */ - -/* -#define TX_NO_TIMER -#ifndef TX_TIMER_PROCESS_IN_ISR -#define TX_TIMER_PROCESS_IN_ISR -#endif -*/ - -/* Determine if the notify callback option should be disabled. By default, notify callbacks are - enabled. If the application does not use notify callbacks, they may be disabled to reduce - code size and improve performance. */ - -#define TX_DISABLE_NOTIFY_CALLBACKS - -/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal - code in-line. This results in a larger image, but improves the performance of the thread - resume and suspend services. */ - -/* -#define TX_INLINE_THREAD_RESUME_SUSPEND -*/ - -/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code - size and less processing overhead, but increases the interrupt lockout time. */ - -/* -#define TX_NOT_INTERRUPTABLE -*/ - -/* Determine if the trace event logging code should be enabled. This causes slight increases in - code size and overhead, but provides the ability to generate system trace information which - is available for viewing in TraceX. */ - -/* -#define TX_ENABLE_EVENT_TRACE -*/ - -/* Determine if block pool performance gathering is required by the application. When the following is - defined, ThreadX gathers various block pool performance information. */ - -/* -#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if byte pool performance gathering is required by the application. When the following is - defined, ThreadX gathers various byte pool performance information. */ - -/* -#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if event flags performance gathering is required by the application. When the following is - defined, ThreadX gathers various event flags performance information. */ - -/* -#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if mutex performance gathering is required by the application. When the following is - defined, ThreadX gathers various mutex performance information. */ - -/* -#define TX_MUTEX_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if queue performance gathering is required by the application. When the following is - defined, ThreadX gathers various queue performance information. */ - -/* -#define TX_QUEUE_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if semaphore performance gathering is required by the application. When the following is - defined, ThreadX gathers various semaphore performance information. */ - -/* -#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if thread performance gathering is required by the application. When the following is - defined, ThreadX gathers various thread performance information. */ - -/* -#define TX_THREAD_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if timer performance gathering is required by the application. When the following is - defined, ThreadX gathers various timer performance information. */ - -/* -#define TX_TIMER_ENABLE_PERFORMANCE_INFO -*/ - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h deleted file mode 100644 index f655c33739..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5400_CEVB/target_ux_user.h +++ /dev/null @@ -1,345 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////// -// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file -// for nanoBooter and another for nanoCLR. -/////////////////////////////////////////////////////////////////////////////////////////// - -#ifndef UX_USER_H -#define UX_USER_H - -/* Define various build options for the USBX port. The application should either make changes - here by commenting or un-commenting the conditional compilation defined OR supply the defines - though the compiler's equivalent of the -D option. */ -/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ - -/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ -/* -#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE -*/ - - -/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ -/* -#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE -*/ - -/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ -/* -#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE -*/ - -/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please - also refer to ux_port.h for descriptions on each of these options. */ - -/* Defined, this value represents how many ticks per seconds for a specific hardware platform. - The default is 1000 indicating 1 tick per millisecond. */ - -/* #define UX_PERIODIC_RATE 1000 -*/ -#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) - -/* Define control transfer timeout value in millisecond. - The default is 10000 milliseconds. */ -/* -#define UX_CONTROL_TRANSFER_TIMEOUT 10000 -*/ - -/* Define non control transfer timeout value in millisecond. - The default is 50000 milliseconds. */ -/* -#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 -*/ - - -/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value - represents the class container and not the number of instances of a class. For instance, if a - particular implementation of USBX needs the hub class, the printer class, and the storage - class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices - that belong to these classes. */ - -#define UX_MAX_CLASSES 1 - - -/* Defined, this value is the maximum number of classes in the device stack that can be loaded by - USBX. */ - -/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 -*/ - -/* Defined, this value is the maximum number of interfaces in the device framework. */ - -/* #define UX_MAX_SLAVE_INTERFACES 16 -*/ - -/* Defined, this value represents the number of different host controllers available in the system. - For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more - than 1. This value represents the number of concurrent host controllers running at the same time. - If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller - running, the UX_MAX_HCD should be set to 2. */ - -/* #define UX_MAX_HCD 1 -*/ - - -/* Defined, this value represents the maximum number of devices that can be attached to the USB. - Normally, the theoretical maximum number on a single USB is 127 devices. This value can be - scaled down to conserve memory. Note that this value represents the total number of devices - regardless of the number of USB buses in the system. */ - -/* #define UX_MAX_DEVICES 127 -*/ - - -/* Defined, this value represents the current number of SCSI logical units represented in the device - storage class driver. */ - -/* #define UX_MAX_SLAVE_LUN 1 -*/ - - -/* Defined, this value represents the maximum number of SCSI logical units represented in the - host storage class driver. */ - -/* #define UX_MAX_HOST_LUN 1 -*/ - - -/* Defined, this value represents the maximum number of bytes received on a control endpoint in - the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ - -/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 -*/ - - -/* Defined, this value represents the maximum number of bytes that can be received or transmitted - on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default - is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage - class, this value cannot be less than 2048. */ - -#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) - - -/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. -*/ - -/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ - - -/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. - The default is 8K bytes but can be reduced in memory constrained environments. */ -#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) - -/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ - -/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE - */ - -/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values - depend on the type of host controller and can be reduced in memory constrained environments. */ - -#define UX_MAX_ED 80 -#define UX_MAX_TD 128 -#define UX_MAX_ISO_TD 1 - -/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined - in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse - it can be reduced a lot. */ - -#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 - -/* Defined, this value represents the maximum number of HID usages for a HID device. - Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ - -#define UX_HOST_CLASS_HID_USAGES 512 - - -/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get - (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed - or released. The report contains every key that is down). There are limitations to this method such as not being - able to determine when a key has been released. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses - and key releases. */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ - -/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; - key released/up changes are not reported. - */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ - -/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. - */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ - -/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. - */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ - - -/* Defined, this value represents the maximum number of media for the host storage class. - Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ - -#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 - -/* Defined, this value includes code to handle storage devices that use the CB - or CBI protocol (such as floppy disks). It is off by default because these - protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol - which virtually all modern storage devices use. -*/ - -/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ - -/* Defined, this value forces the memory allocation scheme to enforce alignment - of memory with the UX_SAFE_ALIGN field. -*/ - -/* #define UX_ENFORCE_SAFE_ALIGNMENT */ - -/* Defined, this value represents the number of packets in the CDC_ECM device class. - The default is 16. -*/ - -#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 - -/* Defined, this value represents the number of packets in the CDC_ECM host class. - The default is 16. -*/ - -/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ - -/* Defined, this value represents the number of milliseconds to wait for packet - allocation until invoking the application's error callback and retrying. - The default is 1000 milliseconds. -*/ - -/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ - -/* Defined, this value represents the number of milliseconds to wait for packet - pool availability checking loop. - The default is 100 milliseconds. -*/ - -/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ - -/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ - -/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ - -/* Defined, this value represents the number of milliseconds to wait for packet - allocation until invoking the application's error callback and retrying. -*/ - -/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ - -/* Defined, this value represents the the maximum length of HID reports on the - device. - */ - -/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ - -/* Defined, this value represents the the maximum number of HID events/reports - that can be queued at once. - */ - -/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ - - -/* Defined, this macro will disable DFU_UPLOAD support. */ - -/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ - -/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ - -/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ - -/* Defined, this macro will change status mode. - 0 - simple mode, - status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, - no bwPollTimeout. - 1 - status is queried from application once requested, - b0-3 : media status - b4-7 : bStatus - b8-31: bwPollTimeout - bwPollTimeout supported. -*/ - -/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ - -/* Defined, this value represents the default DFU status bwPollTimeout. - The value is 3 bytes long (max 0xFFFFFFu). - By default the bwPollTimeout is 1 (means 1ms). - */ - -/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ - -/* Defined, this macro will enable custom request process callback. */ - -/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ - -/* Defined, this macro disables CDC ACM non-blocking transmission support. */ - -/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ - -/* Defined, this macro enables device bi-directional-endpoint support. */ - -/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ - -/* Defined, this value will only enable the host side of usbx. */ -/* #define UX_HOST_SIDE_ONLY */ - -/* Defined, this value will only enable the device side of usbx. */ -/* #define UX_DEVICE_SIDE_ONLY */ - -/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. -*/ - -#ifndef UX_HOST_SIDE_ONLY -#ifndef UX_DEVICE_SIDE_ONLY - -/* #define UX_OTG_SUPPORT */ - -#endif -#endif - -/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. -*/ - -#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) - -/* Defined, this value represents the size of the log pool. -*/ -#define UX_DEBUG_LOG_SIZE (1024 * 16) - - -/* Defined, this enables the assert checks inside usbx. */ -#define UX_ENABLE_ASSERT - -/* Defined, this defines the assert action taken when failure detected. By default - it halts without any output. */ -/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ - - -/* DEBUG includes and macros for a specific platform go here. */ -#ifdef UX_INCLUDE_USER_DEFINE_BSP -#include "usb_bsp.h" -#include "usbh_hcs.h" -#include "usbh_stdreq.h" -#include "usbh_core.h" -#endif - -#endif - diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakeLists.txt deleted file mode 100644 index bab63d4097..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakeLists.txt +++ /dev/null @@ -1,76 +0,0 @@ - -include(FetchContent) -include(binutils.common) -include(binutils.AzureRTOS) -include(AzureRTOS_${TARGET_SERIES}_GCC_options) - -# Azure RTOS settings and inclusion of build system -set(THREADX_ARCH "cortex_m4" ) -set(THREADX_TOOLCHAIN "gnu" ) -# set(NX_USER_FILE ${TARGET_BASE_LOCATION}/target_nx_user.h CACHE STRING "Enable NX user configuration") -# set(NXD_ENABLE_FILE_SERVERS OFF CACHE BOOL "Disable fileX dependency by netxduo") - -set(SL_BOARD_NAME "BRD2204A" PARENT_SCOPE) - -add_subdirectory(${azure_rtos_SOURCE_DIR} threadx) -# add_subdirectory(${azure_rtos_filex_SOURCE_DIR} filex) -# add_subdirectory(${azure_rtos_netxduo_SOURCE_DIR} netxduo) -# add_subdirectory(${azure_rtos_usbx_SOURCE_DIR} usbx) - -nf_setup_target_build( - HAS_NANOBOOTER - - BOOTER_LINKER_FILE - efm32gg11b_booter - - CLR_LINKER_FILE - efm32gg11b_CLR - - BOOTER_EXTRA_COMPILE_DEFINITIONS - EFM32GG11B820F2048GQ100=1 - SL_COMPONENT_CATALOG_PRESENT=1 - _SILICON_LABS_32B_SERIES_2_CONFIG=0 - BSP_LF_CLK_SEL=99 - I2CSPM_TRANSFER_TIMEOUT=3000 - SL_STACK_SIZE=0x2000 - SL_HEAP_SIZE=0x2000 - - CLR_EXTRA_COMPILE_DEFINITIONS - EFM32GG11B820F2048GQ100=1 - SL_COMPONENT_CATALOG_PRESENT=1 - _SILICON_LABS_32B_SERIES_2_CONFIG=0 - BSP_LF_CLK_SEL=99 - I2CSPM_TRANSFER_TIMEOUT=3000 - SL_STACK_SIZE=0x7000 - SL_HEAP_SIZE=0x10000 - - BOOTER_EXTRA_LINKMAP_PROPERTIES - ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" - - CLR_EXTRA_LINKMAP_PROPERTIES - ",--library-path=${CMAKE_SOURCE_DIR}/targets/AzureRTOS/_common" -) - -# generate bin file for deployment -if(SRECORD_TOOL_AVAILABLE) - - ############################################################################################################ - ## when changing the linker file make sure to update the addresses below with the offset of the CLR image ## - ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## - ############################################################################################################ - - if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) - nf_generate_bin_package( - ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin - ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - 13000 - ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) - else() - nf_generate_bin_package( - ${CMAKE_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin - ${CMAKE_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin - C000 - ${CMAKE_SOURCE_DIR}/build/nanobooter-nanoclr.bin) - endif() - -endif() diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json deleted file mode 100644 index b35770bdc7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/CMakePresets.json +++ /dev/null @@ -1,85 +0,0 @@ -{ - "version": 4, - "include": [ - "../../../../CMake/arm-gcc.json", - "../../../../config/user-tools-repos.json", - "../../../../config/user-prefs.json" - ], - "configurePresets": [ - { - "name": "Si5575_CEVB_Debug", - "inherits": [ - "arm-gcc-cortex-preset", - "user-tools-repos", - "user-prefs" - ], - "hidden": false, - "cacheVariables": { - "TARGET_BOARD": "Si5575_CEVB", - "TARGET_NAME": "Si5575_CEVB_Debug", - "RTOS": "AzureRTOS", - "TARGET_SERIES": "EFM32GG11", - "SUPPORT_ANY_BASE_CONVERSION": "OFF", - "NF_FEATURE_RTC": "ON", - "NF_FEATURE_DEBUGGER": "ON", - "NF_FEATURE_HAS_SDCARD": "OFF", - "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", - "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", - "API_System.Math": "ON", - "API_Hardware.GiantGecko": "ON", - "API_System.Device.Gpio": "ON", - "API_System.Device.Pwm": "ON", - "API_System.IO.Ports": "OFF", - "API_System.Device.Adc": "OFF", - "API_System.Device.Dac": "OFF", - "API_System.Net": "OFF", - "API_nanoFramework.Device.OneWire": "ON", - "API_nanoFramework.Devices.Can": "OFF", - "API_nanoFramework.ResourceManager": "ON", - "API_nanoFramework.System.Collections": "ON", - "API_nanoFramework.System.Text": "ON", - "API_nanoFramework.GiantGecko.Adc": "OFF", - "API_Windows.Storage": "OFF", - "API_nanoFramework.Graphics": "OFF", - "TARGET_SERIAL_BAUDRATE": "921600", - "HAL_WP_USE_SERIAL": "OFF", - "HAL_WP_USE_USB_CDC": "ON", - "API_System.Device.Spi": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.Spi": "ON", - "API_System.Device.I2c": "OFF", - "API_Com.SkyworksInc.NanoFramework.Devices.I2c": "ON", - "API_System.Device.UsbStream": "ON", - "API_nanoFramework.System.IO.Hashing": "ON" - } - }, - { - "name": "Si5575_CEVB_Release", - "inherits": [ - "Si5575_CEVB_Debug" - ], - "hidden": false, - "cacheVariables": { - "TARGET_NAME": "Si5575_CEVB_Release", - "NF_BUILD_RTM": "ON", - "NF_PROFILE_NEW_ALLOCATIONS": "OFF", - "NF_TRACE_MEMORY_STATS": "OFF" - } - } - ], - "buildPresets": [ - { - "inherits": "base-user", - "name": "Si5575_CEVB_Debug", - "displayName": "Si5575_CEVB_Debug", - "configurePreset": "Si5575_CEVB_Debug" - }, - { - "inherits": "base-user", - "name": "Si5575_CEVB_Release", - "displayName": "Si5575_CEVB_Release", - "configurePreset": "Si5575_CEVB_Release" - } - ] -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/README.md b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/README.md deleted file mode 100644 index 2fa32a045f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/README.md +++ /dev/null @@ -1,28 +0,0 @@ -# Skyworks Si5575 CEVB featuring SiLabs EFM32 Giant Gecko GG11 - -## See -https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8175353962/Si5575+CEVB+Software+Control - -https://skyworksinc.atlassian.net/wiki/spaces/TimingSoftware/pages/8084916281/Modifying+nanoFramework+CLR+for+Skyworks+EVB - -## Key Files - -CMakePresets.json - Enable packages, targets, naming, etc. - -target_system_device_spi_config.h -target_system_device_spi_config.cpp - SPI - -target_system_device_i2c_config.h -target_system_device_i2c_config.cpp - I2C - -target_nano_gg_adc_config.h -target_nano_gg_adc_config.cpp - ADC - -nanoBooter\main.c -nanoCLR\main.c - Bootloader Mode / Ready LED - diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_device_init_clocks.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_device_init_clocks.c deleted file mode 100644 index 5e12163b4b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_device_init_clocks.c +++ /dev/null @@ -1,28 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Copyright 2019 Silicon Laboratories Inc. www.silabs.com -// See LICENSE file in the project root for full license information. -// - -#include "sl_device_init_clocks.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_clocks(void) -{ - CMU_CLOCK_SELECT_SET(HF, USHFRCO); - - CMU_ClockEnable(cmuClock_HFLE, true); - CMU_ClockEnable(cmuClock_HFPER, true); - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_CLOCK_SELECT_SET(LFA, LFRCO); - CMU_CLOCK_SELECT_SET(LFB, LFRCO); -#if defined(_CMU_LFCCLKSEL_MASK) - CMU_CLOCK_SELECT_SET(LFC, LFRCO); -#endif -#if defined(_CMU_LFECLKSEL_MASK) - CMU_CLOCK_SELECT_SET(LFE, LFRCO); -#endif - - return SL_STATUS_OK; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_event_handler.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_event_handler.c deleted file mode 100644 index c0d02691c1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_event_handler.c +++ /dev/null @@ -1,48 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Copyright 2020 Silicon Laboratories Inc. www.silabs.com -// See LICENSE file in the project root for full license information. -// - -#include "sl_event_handler.h" - -#include "em_chip.h" -#include "sl_device_init_nvic.h" -#include "sl_board_init.h" -#include "sl_device_init_dcdc.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_lfxo.h" -#include "sl_device_init_hfrco.h" -#include "sl_device_init_lfrco.h" -#include "sl_device_init_clocks.h" -#include "sl_device_init_emu.h" -#include "sl_board_control.h" -#include "sl_sleeptimer.h" -#include "gpiointerrupt.h" -#include "sl_uartdrv_instances.h" -#include "sl_iostream_init_usart_instances.h" -#include "sl_iostream_init_instances.h" -#include "sl_i2cspm_instances.h" -#include "sl_power_manager.h" - -#include -#include - -extern void InitGpCrc(void); - -void sl_platform_init(void) -{ - CHIP_Init(); - sl_device_init_nvic(); - sl_board_preinit(); - sl_device_init_dcdc(); - // sl_device_init_hfxo(); - sl_device_init_hfrco(); - // sl_device_init_lfxo(); - sl_device_init_lfrco(); - sl_device_init_clocks(); - sl_device_init_emu(); - sl_board_init(); - sl_power_manager_init(); - InitGpCrc(); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_init.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_init.c deleted file mode 100644 index ab0bb51bee..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_init.c +++ /dev/null @@ -1,91 +0,0 @@ -#include "uartdrv.h" -#include "sl_uartdrv_instances.h" -#include - -#include "sl_uartdrv_usart_vcom_config.h" - -UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; -UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; - -static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; - -/* If CTS and RTS not defined, define a default value to avoid errors */ -#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 -#endif -#endif - -#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 -#endif -#endif - - -/* Define RX and TX buffer queues */ -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); - - -/* Create uartdrv initialization structs */ -UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { - .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, - .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, -#if defined(_USART_ROUTELOC0_MASK) - .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, - .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, -#elif defined(_USART_ROUTE_MASK) - .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, -#elif defined(_GPIO_USART_ROUTEEN_MASK) - .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, - .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, - .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, - .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, - .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, -#endif - .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, - .parity = SL_UARTDRV_USART_VCOM_PARITY, - .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, -#if defined(USART_CTRL_MVDIS) - .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, -#endif - .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, - .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, - .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, - .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, - .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, - .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, - .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, -#if defined(_USART_ROUTELOC1_MASK) - .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, - .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, -#endif -}; - - -void sl_uartdrv_init_instances(void){ - UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); - sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); -} - -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) -{ - sl_status_t status = SL_STATUS_INVALID_HANDLE; - - if (handle != NULL) { - sli_uartdrv_default_handle = handle; - status = SL_STATUS_OK; - } - - return status; -} - -UARTDRV_Handle_t sl_uartdrv_get_default(void) -{ - return sli_uartdrv_default_handle; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_instances.h deleted file mode 100644 index 894c73f803..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_uartdrv_instances.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef SL_UARTDRV_INSTANCES_H -#define SL_UARTDRV_INSTANCES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sl_status.h" -#include "uartdrv.h" - -extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; - -void sl_uartdrv_init_instances(void); - -/***************************************************************************//** - * Set the handle as the default UARTDRV handle. - * - * @param[in] handle UARTDRV handle to set as default. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); - -/***************************************************************************//** - * Get the default UARTDRV handle configured. - * - * @return UARTDRV handle - ******************************************************************************/ -UARTDRV_Handle_t sl_uartdrv_get_default(void); - -#ifdef __cplusplus -} -#endif - -#endif // SL_UARTDRV_INSTANCES_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c deleted file mode 100644 index 12f715438d..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.c +++ /dev/null @@ -1,154 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include -#include -#include - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_cdc_acm_instances.h" - -/* include config file for the instances */ - -#include - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for acm0 instance */ - -void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr); - -void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr); - -void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd); - -bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding); - -//**************************************************************************** -// Global variables. - -/* variables for acm0 instance */ - -uint8_t sl_usbd_cdc_acm_acm0_number = 0; - -sl_usbd_cdc_acm_callbacks_t sli_usbd_cdc_acm_acm0_callbacks = { - sli_usbd_cdc_acm_acm0_enable, - sli_usbd_cdc_acm_acm0_disable, - sli_usbd_cdc_acm_acm0_line_control_changed, - sli_usbd_cdc_acm_acm0_line_coding_changed, -}; - -//**************************************************************************** -// Callback functions. - -/* callback functions for acm0 instance */ -void sli_usbd_cdc_acm_acm0_enable(uint8_t subclass_nbr) -{ - (void)&subclass_nbr; - sl_usbd_cdc_acm_acm0_on_enable_event(); - return; -} - -void sli_usbd_cdc_acm_acm0_disable(uint8_t subclass_nbr) -{ - (void)&subclass_nbr; - sl_usbd_cdc_acm_acm0_on_disable_event(); - return; -} - -void sli_usbd_cdc_acm_acm0_line_control_changed(uint8_t subclass_nbr, uint8_t event, uint8_t event_chngd) -{ - (void)&subclass_nbr; - (void)&event; - (void)&event_chngd; - sl_usbd_cdc_acm_acm0_on_line_control_event(); - return; -} - -bool sli_usbd_cdc_acm_acm0_line_coding_changed(uint8_t subclass_nbr, sl_usbd_cdc_acm_line_coding_t *p_line_coding) -{ - (void)&subclass_nbr; - (void)&p_line_coding; - sl_usbd_cdc_acm_acm0_on_line_coding_event(); - return true; -} - -//**************************************************************************** -// Global functions. - -/* initialize acm0 instance */ -void sli_usbd_cdc_acm_acm0_init() -{ - uint16_t interval = 0; - uint16_t capabilities = 0; - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS; - - /* line state notification interval for that instance */ - interval = SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL; - - /* call management capabilities */ - if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE == 1) - { - capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DEV; - } - - /* call management DCI interface */ - if (SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI == 1) - { - capabilities |= SL_USBD_CDC_ACM_CALL_MGMT_DATA_CCI_DCI; - } - - /* create CDC ACM instance */ - sl_usbd_cdc_acm_create_instance(interval, capabilities, &sli_usbd_cdc_acm_acm0_callbacks, &class_number); - - /* store class number globally */ - sl_usbd_cdc_acm_acm0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_cdc_acm_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void) -{ -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void) -{ -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void) -{ -} - -__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void) -{ -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h deleted file mode 100644 index dd62731af5..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_cdc_acm_instances.h +++ /dev/null @@ -1,27 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT -#define SL_USBD_CLASS_CDC_ACM_INSTANCES_INIT - -#include - -/* class numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_cdc_acm_acm0_number; - -/* event handlers for all CDC ACM instances */ - -__WEAK void sl_usbd_cdc_acm_acm0_on_enable_event(void); -__WEAK void sl_usbd_cdc_acm_acm0_on_disable_event(void); -__WEAK void sl_usbd_cdc_acm_acm0_on_line_control_event(void); -__WEAK void sl_usbd_cdc_acm_acm0_on_line_coding_event(void); - -/* init functions for all CDC ACM instances */ - -void sli_usbd_cdc_acm_acm0_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c deleted file mode 100644 index 18d550951b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.c +++ /dev/null @@ -1,277 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include -#include -#include "sl_usbd_class_hid.h" - -/* template headers */ -#include "sl_usbd_configuration_instances.h" -#include "sl_usbd_class_hid_instances.h" - -/* include config file for the instances */ - -#include - -//**************************************************************************** -// Function declarations. - -/* callback prototypes for hid0 instance */ -void sli_usbd_hid_hid0_enable(uint8_t class_nbr); - -void sli_usbd_hid_hid0_disable(uint8_t class_nbr); - -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); - -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len); - -void sli_usbd_hid_hid0_set_output_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); - -void sli_usbd_hid_hid0_get_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); - -void sli_usbd_hid_hid0_set_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len); - -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol); - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol); - -//**************************************************************************** -// Global variables. - -/* variables for mouse0 instance */ - -uint8_t sl_usbd_hid_hid0_number = 0; - -uint8_t sl_usbd_hid_hid0_default_protocol = 0; - -static const uint8_t sli_usbd_hid_hid0_default_desc[] = { - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, 0x00, - SL_USBD_HID_MAIN_COLLECTION + 1, 0xFF, - SL_USBD_HID_LOCAL_USAGE + 1, 0x09, - SL_USBD_HID_MAIN_COLLECTION + 1, 0x01, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, 0xA1, - SL_USBD_HID_LOCAL_USAGE_MIN + 1, 0x01, - SL_USBD_HID_LOCAL_USAGE_MAX + 1, 0x03, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x00, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x03, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x01, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_ABSOLUTE, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x01, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x0D, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_CONSTANT, - SL_USBD_HID_GLOBAL_USAGE_PAGE + 1, SL_USBD_HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_X, - SL_USBD_HID_LOCAL_USAGE + 1, SL_USBD_HID_DV_Y, - SL_USBD_HID_GLOBAL_LOG_MIN + 1, 0x81, - SL_USBD_HID_GLOBAL_LOG_MAX + 1, 0x7F, - SL_USBD_HID_GLOBAL_REPORT_SIZE + 1, 0x08, - SL_USBD_HID_GLOBAL_REPORT_COUNT + 1, 0x02, - SL_USBD_HID_MAIN_INPUT + 1, SL_USBD_HID_MAIN_DATA | SL_USBD_HID_MAIN_VARIABLE | SL_USBD_HID_MAIN_RELATIVE, - SL_USBD_HID_MAIN_ENDCOLLECTION, SL_USBD_HID_MAIN_ENDCOLLECTION}; - -sl_usbd_hid_callbacks_t sli_usbd_hid_hid0_callbacks = { - sli_usbd_hid_hid0_enable, - sli_usbd_hid_hid0_disable, - sli_usbd_hid_hid0_get_report_desc, - sli_usbd_hid_hid0_get_phy_desc, - sli_usbd_hid_hid0_set_output_report, - sli_usbd_hid_hid0_get_feature_report, - sli_usbd_hid_hid0_set_feature_report, - sli_usbd_hid_hid0_get_protocol, - sli_usbd_hid_hid0_set_protocol, -}; - -//**************************************************************************** -// Callback functions. - -/* callback functions for mouse0 instance */ -void sli_usbd_hid_hid0_enable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_enable_event(); - - return; -} - -void sli_usbd_hid_hid0_disable(uint8_t class_nbr) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_disable_event(); - - return; -} - -void sli_usbd_hid_hid0_get_report_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - (void)&class_nbr; - - *p_report_ptr = sli_usbd_hid_hid0_default_desc; - *p_report_len = sizeof(sli_usbd_hid_hid0_default_desc); - - sl_usbd_hid_hid0_on_get_report_desc_event(p_report_ptr, p_report_len); - - return; -} - -void sli_usbd_hid_hid0_get_phy_desc(uint8_t class_nbr, const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - (void)&class_nbr; - - *p_report_ptr = NULL; - *p_report_len = 0; - - sl_usbd_hid_hid0_on_get_phy_desc_event(p_report_ptr, p_report_len); - - return; -} - -void sli_usbd_hid_hid0_set_output_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_set_output_report_event(report_id, p_report_buf, report_len); - - return; -} - -void sli_usbd_hid_hid0_get_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) -{ - (void)&class_nbr; - - memset(p_report_buf, 0, report_len); - - sl_usbd_hid_hid0_on_get_feature_report_event(report_id, p_report_buf, report_len); - - return; -} - -void sli_usbd_hid_hid0_set_feature_report( - uint8_t class_nbr, - uint8_t report_id, - uint8_t *p_report_buf, - uint16_t report_len) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_on_set_feature_report_event(report_id, p_report_buf, report_len); - - return; -} - -void sli_usbd_hid_hid0_get_protocol(uint8_t class_nbr, uint8_t *p_protocol) -{ - (void)&class_nbr; - - *p_protocol = sl_usbd_hid_hid0_default_protocol; - - sl_usbd_hid_hid0_on_get_protocol_event(p_protocol); - - return; -} - -void sli_usbd_hid_hid0_set_protocol(uint8_t class_nbr, uint8_t protocol) -{ - (void)&class_nbr; - - sl_usbd_hid_hid0_default_protocol = protocol; - - sl_usbd_hid_hid0_on_set_protocol_event(protocol); - - return; -} - -//**************************************************************************** -// Global functions. - -/* initialize hid0 instance */ -void sli_usbd_hid_hid0_init() -{ - sl_usbd_hid_country_code_t country = SL_USBD_HID_COUNTRY_CODE_NOT_SUPPORTED; - - uint8_t subclass = 0; - uint8_t protocol = 0; - - uint16_t interval_in = 0; - uint16_t interval_out = 0; - bool ctrl_rd_en = true; - - uint8_t class_number = 0; - uint8_t config_number = 0; - char *configs = NULL; - char *token = NULL; - - /* configs to attach the class instance to */ - configs = SL_USBD_HID_HID0_CONFIGURATIONS; - - /* read subclass, protocol, and country codes */ - subclass = SL_USBD_HID_HID0_SUBCLASS; - protocol = SL_USBD_HID_HID0_PROTOCOL; - country = SL_USBD_HID_HID0_COUNTRY_CODE; - - /* read endpoint parameters */ - interval_in = SL_USBD_HID_HID0_INTERVAL_IN; - interval_out = SL_USBD_HID_HID0_INTERVAL_OUT; - ctrl_rd_en = SL_USBD_HID_HID0_ENABLE_CTRL_RD; - - /* create HID instance */ - sl_usbd_hid_create_instance( - subclass, - protocol, - country, - interval_in, - interval_out, - ctrl_rd_en, - &sli_usbd_hid_hid0_callbacks, - &class_number); - - /* store class number globally */ - sl_usbd_hid_hid0_number = class_number; - - /* tokenize configs by "," and spaces */ - token = strtok(configs, ", "); - - /* loop over tokens */ - while (token != NULL) - { - - /* add to config0? */ - if (!strcmp(token, "config0") || !strcmp(token, "all")) - { - config_number = sl_usbd_configuration_config0_number; - sl_usbd_hid_add_to_configuration(class_number, config_number); - } - - /* next token */ - token = strtok(NULL, ", "); - } -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h deleted file mode 100644 index fa9e5b853a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_class_hid_instances.h +++ /dev/null @@ -1,32 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CLASS_HID_INSTANCES_INIT -#define SL_USBD_CLASS_HID_INSTANCES_INIT - -#include "sl_usbd_class_hid.h" - -/* class numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_hid_hid0_number; - -/* event handlers for all HID instances */ - -__WEAK void sl_usbd_hid_hid0_on_enable_event(void); -__WEAK void sl_usbd_hid_hid0_on_disable_event(void); -__WEAK void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len); -__WEAK void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len); -__WEAK void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol); -__WEAK void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol); - -/* init functions for all HID instances */ - -void sli_usbd_hid_hid0_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.c deleted file mode 100644 index 0a865bccfc..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.c +++ /dev/null @@ -1,61 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -//**************************************************************************** -// Includes. - -#include -#include - -/* template headers */ -#include "sl_usbd_configuration_instances.h" - -/* include config file for the instances */ - -#include - -//**************************************************************************** -// Global variables. - -/* configuration numbers assigned by the USB stack after init */ - -uint8_t sl_usbd_configuration_config0_number = 0; - -//**************************************************************************** -// Global functions. - -/* initialize config0 instance */ -void sli_usbd_configuration_config0_init() -{ - uint8_t attrib = 0; - uint16_t power = 0; - sl_usbd_device_speed_t speed = SL_USBD_DEVICE_SPEED_FULL; - const char *name = NULL; - uint8_t number = 0; - - /* configuration attributes */ -#if SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE == 1 - attrib |= SL_USBD_DEV_ATTRIB_SELF_POWERED; -#endif -#if SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP == 1 - attrib |= SL_USBD_DEV_ATTRIB_REMOTE_WAKEUP; -#endif - - /* configuration maximum power (mA) */ - power = SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER; - - /* configuration speed */ - speed = SL_USBD_DEVICE_SPEED_FULL; - - /* configuration name */ - name = SL_USB_CONFIGURATION_CONFIG0_NAME; - - /* create the configuration descriptor */ - sl_usbd_core_add_configuration(attrib, power, speed, name, &number); - - /* store the configuration number globally */ - sl_usbd_configuration_config0_number = number; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.h deleted file mode 100644 index 07726e93fe..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/autogen/sl_usbd_configuration_instances.h +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CONFIGURATION_INSTANCES_INIT -#define SL_USBD_CONFIGURATION_INSTANCES_INIT - -/* configuration numbers assigned by the USB stack after init */ - -extern uint8_t sl_usbd_configuration_config0_number; - -/* init functions for all configuration instances */ - -void sli_usbd_configuration_config0_init(void); - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/bspconfig.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/bspconfig.h deleted file mode 100644 index 09c0ff4989..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/bspconfig.h +++ /dev/null @@ -1,9 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/CMakeLists.txt deleted file mode 100644 index 8ea7907f60..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append common source files -list(APPEND COMMON_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c) - -# make var global -set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage-DEBUG.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage-DEBUG.c deleted file mode 100644 index 5ae69920e9..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage-DEBUG.c +++ /dev/null @@ -1,123 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 18}, - - // 00013000 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 19, 237}, - - // 000EE000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 238, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // GG11 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage.c deleted file mode 100644 index 09982097e3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/Device_BlockStorage.c +++ /dev/null @@ -1,123 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -// 2kB blocks -const BlockRange BlockRange1[] = { - - // 00000000 nanoBooter - {BlockRange_BLOCKTYPE_BOOTSTRAP, 0, 11}, - - // 0000C00 nanoCLR - {BlockRange_BLOCKTYPE_CODE, 12, 66}, - - // 00043000 deployment - {BlockRange_BLOCKTYPE_DEPLOYMENT, 67, 510}, - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - // 001FF000 configuration block - {BlockRange_BLOCKTYPE_CONFIG, 511, 511}, - /////////////////////////////////////////////////////////////////////////////////////// -}; - -const BlockRegionInfo BlockRegions[] = { - { - (0), - - // start address for block region - 0x00000000, - - // total number of blocks in this region - 512, - - // total number of bytes per block - 0x1000, - - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, -}; - -const DeviceBlockInfo Device_BlockInfo = { - - // STM32 flash memory is XIP - (MediaAttribute_SupportsXIP), - - // UINT32 BytesPerSector - 2, - - // UINT32 NumRegions; - ARRAYSIZE_CONST_EXPR(BlockRegions), - - // const BlockRegionInfo* pRegions; - (BlockRegionInfo *)BlockRegions, -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = { - { - // BLOCK_CONFIG - { - // GPIO_PIN Pin; - 0, - - // BOOL ActiveState - - false, - }, - - // BlockDeviceinfo - (DeviceBlockInfo *)&Device_BlockInfo, - }, - - { - // CPU_MEMORY_CONFIG - // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - 0, - - // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - true, - - // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, - - // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 0, - - // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 16, - - // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x08000000, - - // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0x00200000, - - // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, - - // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, - - // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - 0, - }, - - // UINT32 ChipProtection; - 0, - - // UINT32 ManufacturerCode; - 0, - - // UINT32 DeviceCode; - 0, -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/tx_initialize_low_level.S b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/tx_initialize_low_level.S deleted file mode 100644 index 39ad790f18..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/common/tx_initialize_low_level.S +++ /dev/null @@ -1,239 +0,0 @@ -@/**************************************************************************/ -@/* */ -@/* Copyright (c) Microsoft Corporation. All rights reserved. */ -@/* */ -@/* This software is licensed under the Microsoft Software License */ -@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -@/* and in the root directory of this software. */ -@/* */ -@/**************************************************************************/ -@ -@ -@/**************************************************************************/ -@/**************************************************************************/ -@/** */ -@/** ThreadX Component */ -@/** */ -@/** Initialize */ -@/** */ -@/**************************************************************************/ -@/**************************************************************************/ -@ -@#define TX_SOURCE_CODE -@ -@ -@/* Include necessary system files. */ -@ -@#include "tx_api.h" -@#include "tx_initialize.h" -@#include "tx_thread.h" -@#include "tx_timer.h" -@ -@ - .global _tx_thread_system_stack_ptr - .global _tx_initialize_unused_memory - .global __RAM_segment_used_end__ - .global _tx_timer_interrupt - .global __main - .global __tx_SVCallHandler - .global __tx_PendSVHandler - .global _vectors - .global __tx_NMIHandler @ NMI - .global __tx_BadHandler @ HardFault - .global __tx_SVCallHandler @ SVCall - .global __tx_DBGHandler @ Monitor - .global __tx_PendSVHandler @ PendSV - .global __tx_SysTickHandler @ SysTick - .global __tx_IntHandler @ Int 0 -@ -@ -SYSTEM_CLOCK = 38000000 -SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) - - .text 32 - .align 4 - .syntax unified -@/**************************************************************************/ -@/* */ -@/* FUNCTION RELEASE */ -@/* */ -@/* _tx_initialize_low_level Cortex-M7/GNU */ -@/* 6.0 */ -@/* AUTHOR */ -@/* */ -@/* William E. Lamie, Microsoft Corporation */ -@/* */ -@/* DESCRIPTION */ -@/* */ -@/* This function is responsible for any low-level processor */ -@/* initialization, including setting up interrupt vectors, setting */ -@/* up a periodic timer interrupt source, saving the system stack */ -@/* pointer for use in ISR processing later, and finding the first */ -@/* available RAM memory address for tx_application_define. */ -@/* */ -@/* INPUT */ -@/* */ -@/* None */ -@/* */ -@/* OUTPUT */ -@/* */ -@/* None */ -@/* */ -@/* CALLS */ -@/* */ -@/* None */ -@/* */ -@/* CALLED BY */ -@/* */ -@/* _tx_initialize_kernel_enter ThreadX entry function */ -@/* */ -@/* RELEASE HISTORY */ -@/* */ -@/* DATE NAME DESCRIPTION */ -@/* */ -@/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* */ -@/**************************************************************************/ -@VOID _tx_initialize_low_level(VOID) -@{ - .global _tx_initialize_low_level - .thumb_func -_tx_initialize_low_level: -@ -@ /* Disable interrupts during ThreadX initialization. */ -@ - CPSID i -@ -@ /* Set base of available memory to end of non-initialised RAM area. */ -@ - LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer - LDR r1, =__RAM_segment_used_end__ @ Build first free address - ADD r1, r1, #4 @ - STR r1, [r0] @ Setup first unused memory pointer -@ -@ /* Setup Vector Table Offset Register. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =__Vectors @ Pickup address of vector table - STR r1, [r0, #0xD08] @ Set vector table address -@ -@ /* Set system stack pointer from vector value. */ -@ - LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer - LDR r1, =__Vectors @ Pickup address of vector table - LDR r1, [r1] @ Pickup reset stack pointer - STR r1, [r0] @ Save system stack pointer -@ -@ /* Enable the cycle count register. */ -@ - LDR r0, =0xE0001000 @ Build address of DWT register - LDR r1, [r0] @ Pickup the current value - ORR r1, r1, #1 @ Set the CYCCNTENA bit - STR r1, [r0] @ Enable the cycle count register -@ -@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ -@ - MOV r0, #0xE000E000 @ Build address of NVIC registers - LDR r1, =SYSTICK_CYCLES - STR r1, [r0, #0x14] @ Setup SysTick Reload Value - MOV r1, #0x7 @ Build SysTick Control Enable Value - STR r1, [r0, #0x10] @ Setup SysTick Control -@ -@ /* Configure handler priorities. */ -@ - LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM - STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers - - LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv - STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers - @ Note: SVC must be lowest priority, which is 0xFF - - LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM - STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers - @ Note: PnSV must be lowest priority, which is 0xFF - -@ -@ /* Return to caller. */ -@ - BX lr -@} -@ - -@/* Define shells for each of the unused vectors. */ -@ - .global __tx_BadHandler - .thumb_func -__tx_BadHandler: - B __tx_BadHandler - -@ /* added to catch the hardfault */ - - .global __tx_HardfaultHandler - .thumb_func -__tx_HardfaultHandler: - B __tx_HardfaultHandler - - -@ /* added to catch the SVC */ - - .global __tx_SVCallHandler - .thumb_func -__tx_SVCallHandler: - B __tx_SVCallHandler - - -@ /* Generic interrupt handler template */ - .global __tx_IntHandler - .thumb_func -__tx_IntHandler: -@ VOID InterruptHandler (VOID) -@ { - PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function -#endif - -@ /* Do interrupt handler work here */ -@ /* BL .... */ - -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function -#endif - POP {r0, lr} - BX LR -@ } - -@ /* System Tick timer interrupt handler */ - .global __tx_SysTickHandler - .global SysTick_Handler - .thumb_func -__tx_SysTickHandler: - .thumb_func -SysTick_Handler: -@ VOID TimerInterruptHandler (VOID) -@ { -@ - PUSH {r0, lr} -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter @ Call the ISR enter function -#endif - BL _tx_timer_interrupt -#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit @ Call the ISR exit function -#endif - POP {r0, lr} - BX LR -@ } - - -@ /* NMI, DBG handlers */ - .global __tx_NMIHandler - .thumb_func -__tx_NMIHandler: - B __tx_NMIHandler - - .global __tx_DBGHandler - .thumb_func -__tx_DBGHandler: - B __tx_DBGHandler diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/pin_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/pin_config.h deleted file mode 100644 index 158edf847a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/pin_config.h +++ /dev/null @@ -1,259 +0,0 @@ -#ifndef PIN_CONFIG_H -#define PIN_CONFIG_H - -// $[ACMP0] -// [ACMP0]$ - -// $[ACMP1] -// [ACMP1]$ - -// $[ACMP2] -// [ACMP2]$ - -// $[ACMP3] -// [ACMP3]$ - -// $[ADC0] -// [ADC0]$ - -// $[ADC1] -// [ADC1]$ - -// $[BU] -// [BU]$ - -// $[CAN0] -// [CAN0]$ - -// $[CAN1] -// [CAN1]$ - -// $[CMU] -// [CMU]$ - -// $[DBG] -// [DBG]$ - -// $[EBI] -// [EBI]$ - -// $[ETH] -// [ETH]$ - -// $[ETM] -// [ETM]$ - -// $[GPIO] -// [GPIO]$ - -// $[I2C0] -// [I2C0]$ - -// $[I2C1] -// [I2C1]$ - -// $[I2C2] -// [I2C2]$ - -// $[IDAC0] -// [IDAC0]$ - -// $[LCD] -// [LCD]$ - -// $[LESENSE] -// [LESENSE]$ - -// $[LETIMER0] -// [LETIMER0]$ - -// $[LETIMER1] -// [LETIMER1]$ - -// $[LEUART0] -// [LEUART0]$ - -// $[LEUART1] -// [LEUART1]$ - -// $[LFXO] -// [LFXO]$ - -// $[PCNT0] -// [PCNT0]$ - -// $[PCNT1] -// [PCNT1]$ - -// $[PCNT2] -// [PCNT2]$ - -// $[PRS.CH0] -// [PRS.CH0]$ - -// $[PRS.CH1] -// [PRS.CH1]$ - -// $[PRS.CH2] -// [PRS.CH2]$ - -// $[PRS.CH3] -// [PRS.CH3]$ - -// $[PRS.CH4] -// [PRS.CH4]$ - -// $[PRS.CH5] -// [PRS.CH5]$ - -// $[PRS.CH6] -// [PRS.CH6]$ - -// $[PRS.CH7] -// [PRS.CH7]$ - -// $[PRS.CH8] -// [PRS.CH8]$ - -// $[PRS.CH9] -// [PRS.CH9]$ - -// $[PRS.CH10] -// [PRS.CH10]$ - -// $[PRS.CH11] -// [PRS.CH11]$ - -// $[PRS.CH12] -// [PRS.CH12]$ - -// $[PRS.CH13] -// [PRS.CH13]$ - -// $[PRS.CH14] -// [PRS.CH14]$ - -// $[PRS.CH15] -// [PRS.CH15]$ - -// $[PRS.CH16] -// [PRS.CH16]$ - -// $[PRS.CH17] -// [PRS.CH17]$ - -// $[PRS.CH18] -// [PRS.CH18]$ - -// $[PRS.CH19] -// [PRS.CH19]$ - -// $[PRS.CH20] -// [PRS.CH20]$ - -// $[PRS.CH21] -// [PRS.CH21]$ - -// $[PRS.CH22] -// [PRS.CH22]$ - -// $[PRS.CH23] -// [PRS.CH23]$ - -// $[QSPI0] -// [QSPI0]$ - -// $[SDIO] -// [SDIO]$ - -// $[TIMER0] -// [TIMER0]$ - -// $[TIMER1] -// [TIMER1]$ - -// $[TIMER2] -// [TIMER2]$ - -// $[TIMER3] -// [TIMER3]$ - -// $[TIMER4] -// [TIMER4]$ - -// $[TIMER5] -// [TIMER5]$ - -// $[TIMER6] -// [TIMER6]$ - -// $[UART0] -// [UART0]$ - -// $[UART1] -// [UART1]$ - -// $[USART0] -// [USART0]$ - -// $[USART1] -// [USART1]$ - -// $[USART2] -// [USART2]$ - -// $[USART3] -// [USART3]$ - -// $[USART4] -// USART4 CTS on PH8 -#define USART4_CTS_PORT gpioPortH -#define USART4_CTS_PIN 8 -#define USART4_CTS_LOC 4 - -// USART4 RTS on PH9 -#define USART4_RTS_PORT gpioPortH -#define USART4_RTS_PIN 9 -#define USART4_RTS_LOC 4 - -// USART4 RX on PH5 -#define USART4_RX_PORT gpioPortH -#define USART4_RX_PIN 5 -#define USART4_RX_LOC 4 - -// USART4 TX on PH4 -#define USART4_TX_PORT gpioPortH -#define USART4_TX_PIN 4 -#define USART4_TX_LOC 4 - -// [USART4]$ - -// $[USART5] -// [USART5]$ - -// $[USB] -// [USB]$ - -// $[VDAC0] -// [VDAC0]$ - -// $[WFXO] -// [WFXO]$ - -// $[WTIMER0] -// [WTIMER0]$ - -// $[WTIMER1] -// [WTIMER1]$ - -// $[WTIMER2] -// [WTIMER2]$ - -// $[WTIMER3] -// [WTIMER3]$ - -// $[CUSTOM_PIN_NAME] -// [CUSTOM_PIN_NAME]$ - -#endif // PIN_CONFIG_H - diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_board_control_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_board_control_config.h deleted file mode 100644 index 5796117234..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_board_control_config.h +++ /dev/null @@ -1,112 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 1 - -// Enable Display -// Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 1 - -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 1 - -// Enable Hall Effect sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_HALL 0 - -// Enable Microphone -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE 0 - -// Enable QSPI Flash -// Default: 0 -#define SL_BOARD_ENABLE_MEMORY_QSPI 0 - -// Enable SD Card -// Default: 0 -#define SL_BOARD_ENABLE_MEMORY_SDCARD 0 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortE -#define SL_BOARD_ENABLE_VCOM_PIN 1 -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// SL_BOARD_ENABLE_DISPLAY -// $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortA -#define SL_BOARD_ENABLE_DISPLAY_PIN 9 -// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ - -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortB -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - -// SL_BOARD_ENABLE_SENSOR_HALL -// $[GPIO_SL_BOARD_ENABLE_SENSOR_HALL] -#define SL_BOARD_ENABLE_SENSOR_HALL_PORT gpioPortB -#define SL_BOARD_ENABLE_SENSOR_HALL_PIN 3 -// [GPIO_SL_BOARD_ENABLE_SENSOR_HALL]$ - -// SL_BOARD_ENABLE_SENSOR_MICROPHONE -// $[GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE] -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT gpioPortD -#define SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN 0 -// [GPIO_SL_BOARD_ENABLE_SENSOR_MICROPHONE]$ - -// SL_BOARD_ENABLE_MEMORY_QSPI -// $[GPIO_SL_BOARD_ENABLE_MEMORY_QSPI] -#define SL_BOARD_ENABLE_MEMORY_QSPI_PORT gpioPortG -#define SL_BOARD_ENABLE_MEMORY_QSPI_PIN 13 -// [GPIO_SL_BOARD_ENABLE_MEMORY_QSPI]$ - -// SL_BOARD_ENABLE_MEMORY_SDCARD -// $[GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD] -#define SL_BOARD_ENABLE_MEMORY_SDCARD_PORT gpioPortE -#define SL_BOARD_ENABLE_MEMORY_SDCARD_PIN 7 -// [GPIO_SL_BOARD_ENABLE_MEMORY_SDCARD]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfrco_config.h deleted file mode 100644 index 8ec8d17100..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfrco_config.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef SL_DEVICE_INIT_HFRCO_CONFIG_H -#define SL_DEVICE_INIT_HFRCO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 72 MHz -// Default: cmuHFRCOFreq_72M0Hz -#define SL_DEVICE_INIT_HFRCO_BAND cmuHFRCOFreq_48M0Hz - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfxo_config.h deleted file mode 100644 index 8f04091ef4..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_hfxo_config.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuOscMode_Crystal - -// Frequency <4000000-48000000> -// Default: 50000000 -#define SL_DEVICE_INIT_HFXO_FREQ 50000000 - -// HFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_HFXO_PRECISION 500 - -// CTUNE <0-511> -// Default: 360 -#define SL_DEVICE_INIT_HFXO_CTUNE 132 - -// Advanced Configurations -// Auto-start HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED -// True -// False -// Default: false -#define SL_DEVICE_INIT_HFXO_AUTOSTART false - -// Auto-select HFXO. This feature is incompatible with Power Manager and can only be enabled in applications that do not use Power Manager or a radio protocol stack. - DEPRECATED -// True -// False -// Default: false -#define SL_DEVICE_INIT_HFXO_AUTOSELECT false - -// - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfrco_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfrco_config.h deleted file mode 100644 index 79b1541af8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfrco_config.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H -#define SL_DEVICE_INIT_LFRCO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Duty Cycling of Vref -// Default: 0 -// Setting this configuration to 1 puts the LFRCO in duty cycle mode by -// setting the ENVREF bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. -// This helps reduce current consumption by ~100nA in EM2, but will result -// in slightly worse accuracy especially at high temperatures. -// To improve the average LFRCO frequency accuracy, make sure ENCHOP -// and ENDEM configs are also set. -#define SL_DEVICE_INIT_LFRCO_ENVREF 0 - -// Enable Comparator Chopping -// Default: 1 -// Setting this configuration to 1 enables LFRCO comparator chopping by -// setting the ENCHOP bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. -// Setting this bit, along with ENDEM, helps improve the average LFRCO -// frequency accuracy. -#define SL_DEVICE_INIT_LFRCO_ENCHOP 1 - -// Enable Dynamic Element Matching -// Default: 1 -// Setting this configuration to 1 enables dynamic element matching by -// setting the ENDEM bit in CMU_LFRCOCTRL to 1 before starting the LFRCO. -// Setting this bit, along with ENCHOP, helps improve the average LFRCO -// frequency accuracy. -#define SL_DEVICE_INIT_LFRCO_ENDEM 1 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfxo_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfxo_config.h deleted file mode 100644 index 46c38725c1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_device_init_lfxo_config.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 70 - -// LFXO precision in PPM <0-65535> -// Default: 500 -#define SL_DEVICE_INIT_LFXO_PRECISION 100 - -// Startup Timeout Delay -// -// <_CMU_LFXOCTRL_TIMEOUT_2CYCLES=> 2 cycles -// <_CMU_LFXOCTRL_TIMEOUT_256CYCLES=> 256 cycles -// <_CMU_LFXOCTRL_TIMEOUT_1KCYCLES=> 1K cycles -// <_CMU_LFXOCTRL_TIMEOUT_2KCYCLES=> 2K cycles -// <_CMU_LFXOCTRL_TIMEOUT_4KCYCLES=> 4K cycles -// <_CMU_LFXOCTRL_TIMEOUT_8KCYCLES=> 8K cycles -// <_CMU_LFXOCTRL_TIMEOUT_16KCYCLES=> 16K cycles -// <_CMU_LFXOCTRL_TIMEOUT_32KCYCLES=> 32K cycles -// <_CMU_LFXOCTRL_TIMEOUT_DEFAULT=> Default -// Default: _CMU_LFXOCTRL_TIMEOUT_DEFAULT -#define SL_DEVICE_INIT_LFXO_TIMEOUT _CMU_LFXOCTRL_TIMEOUT_DEFAULT -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_onewire_config.h deleted file mode 100644 index 41622d2e20..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_onewire_config.h +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_ONEWIRE_CONFIG_H -#define SL_IOSTREAM_USART_ONEWIRE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_ONEWIRE_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_ONEWIRE_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_ONEWIRE_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_ONEWIRE_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_ONEWIRE_RX_BUFFER_SIZE 32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_ONEWIRE_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_ONEWIRE_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_ONEWIRE -// $[USART_SL_IOSTREAM_USART_ONEWIRE] -#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL USART0 -#define SL_IOSTREAM_USART_ONEWIRE_PERIPHERAL_NO 0 - -// USART0 TX on PC11 -#define SL_IOSTREAM_USART_ONEWIRE_TX_PORT gpioPortE -#define SL_IOSTREAM_USART_ONEWIRE_TX_PIN 10 -#define SL_IOSTREAM_USART_ONEWIRE_TX_LOC 0 - -// USART0 RX on PC10 -#define SL_IOSTREAM_USART_ONEWIRE_RX_PORT gpioPortE -#define SL_IOSTREAM_USART_ONEWIRE_RX_PIN 11 -#define SL_IOSTREAM_USART_ONEWIRE_RX_LOC 0 - -// [USART_SL_IOSTREAM_USART_ONEWIRE]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_vcom_config.h deleted file mode 100644 index 59d33b8885..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_iostream_usart_vcom_config.h +++ /dev/null @@ -1,112 +0,0 @@ -/***************************************************************************//** - * @file - * @brief IOSTREAM_USART Config. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_USART_VCOM_CONFIG_H -#define SL_IOSTREAM_USART_VCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// USART settings - -// Baud rate -// Default: 115200 -#define SL_IOSTREAM_USART_VCOM_BAUDRATE 921600 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_IOSTREAM_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_IOSTREAM_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control -// None -// CTS -// RTS -// CTS/RTS -// Software Flow control (XON/XOFF) -// Default: usartHwFlowControlNone -#define SL_IOSTREAM_USART_VCOM_FLOW_CONTROL_TYPE usartHwFlowControlNone - -// Receive buffer size -// Default: 32 -#define SL_IOSTREAM_USART_VCOM_RX_BUFFER_SIZE 512+32 - -// Convert \n to \r\n -// It can be changed at runtime using the C API. -// Default: 0 -#define SL_IOSTREAM_USART_VCOM_CONVERT_BY_DEFAULT_LF_TO_CRLF 0 - -// Restrict the energy mode to allow the reception. -// Default: 1 -// Limits the lowest energy mode the system can sleep to in order to keep the reception on. May cause higher power consumption. -#define SL_IOSTREAM_USART_VCOM_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 - -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_IOSTREAM_USART_VCOM -// $[USART_SL_IOSTREAM_USART_VCOM] -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL USART4 -#define SL_IOSTREAM_USART_VCOM_PERIPHERAL_NO 4 - -// USART4 TX on PH4 -#define SL_IOSTREAM_USART_VCOM_TX_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_TX_PIN 4 -#define SL_IOSTREAM_USART_VCOM_TX_LOC 4 - -// USART4 RX on PH5 -#define SL_IOSTREAM_USART_VCOM_RX_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_RX_PIN 5 -#define SL_IOSTREAM_USART_VCOM_RX_LOC 4 - -// USART4 CTS on PH8 -#define SL_IOSTREAM_USART_VCOM_CTS_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_CTS_PIN 8 -#define SL_IOSTREAM_USART_VCOM_CTS_LOC 4 - -// USART4 RTS on PH9 -#define SL_IOSTREAM_USART_VCOM_RTS_PORT gpioPortH -#define SL_IOSTREAM_USART_VCOM_RTS_PIN 9 -#define SL_IOSTREAM_USART_VCOM_RTS_LOC 4 -// [USART_SL_IOSTREAM_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_memory_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_memory_config.h deleted file mode 100644 index 4f20db4a24..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_memory_config.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef SL_MEMORY_CONFIG_H -#define SL_MEMORY_CONFIG_H - -// These parameters are meant to be set in the target CMakeLists.txt file -#ifndef SL_STACK_SIZE -#error "Missing compiler define for SL_STACK_SIZE in target CMakeLists.txt" -#endif - -#ifndef SL_HEAP_SIZE -#error "Missing compiler define for SL_HEAP_SIZE in target CMakeLists.txt" -#endif - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h deleted file mode 100644 index b9b92ff77c..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_uartdrv_usart_vcom_config.h +++ /dev/null @@ -1,85 +0,0 @@ -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 115200 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHw -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 2 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 2 -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART4 -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 4 - -// USART4 TX on PH4 -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_TX_PIN 4 -#define SL_UARTDRV_USART_VCOM_TX_LOC 4 - -// USART4 RX on PH5 -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_RX_PIN 5 -#define SL_UARTDRV_USART_VCOM_RX_LOC 4 - -// USART4 CTS on PH8 -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 -#define SL_UARTDRV_USART_VCOM_CTS_LOC 4 - -// USART4 RTS on PH9 -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortH -#define SL_UARTDRV_USART_VCOM_RTS_PIN 9 -#define SL_UARTDRV_USART_VCOM_RTS_LOC 4 -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_acm0_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_acm0_config.h deleted file mode 100644 index 9c1ac2d7b1..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_acm0_config.h +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CDC_ACM_ACM0_CONFIG_H -#define SL_USBD_CDC_ACM_ACM0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Class Configuration - -// Configuration(s) to add this class instance to -// Default: all -// Comma separated list of configuration instances (like inst0, inst1) -// that this CDC ACM class instance will be attached to. You can -// use "all" to attach the class to all configs, or use an empty -// string if you do not want to attach the interface to any configuration. -#define SL_USBD_CDC_ACM_ACM0_CONFIGURATIONS "all" - -// - -// Protocol Details - -// Line State Notification Interval (ms) -// Default: 64 -// Line State Notification Interval (ms). -#define SL_USBD_CDC_ACM_ACM0_NOTIFY_INTERVAL 64 - -// - -// Call Management - -// Enable call management -// Default: 1 -// If set to 1, the host is informed that this ACM instance -// has call management capabilities. -#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_ENABLE 1 - -// Call management interface -// <1=> Over DCI -// <0=> Over CCI -// Default: 1 -// If set to 1 (i.e. Over DCI), a dedicated DCI interface will be created -// along with the CCI interface. Otherwise, only the CCI will be created -// and it will be used for both data and call management. -#define SL_USBD_CDC_ACM_ACM0_CALL_MGMT_DCI 1 - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_CDC_ACM_ACM0_CONFIG_H \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_hid0_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_hid0_config.h deleted file mode 100644 index 9e480375d0..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_hid0_config.h +++ /dev/null @@ -1,143 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_HID_HID0_CONFIG_H -#define SL_USBD_HID_HID0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Class Configuration - -// Configuration(s) to add this class instance to -// Default: all -// Comma separated list of configuration instances (like inst0, inst1) -// that this HID class instance will be attached to. You can -// use "all" to attach the class to all configs, or use an empty -// string if you do not want to attach the interface to any configuration. -#define SL_USBD_HID_HID0_CONFIGURATIONS "all" - -// - -// Type Codes - -// Subclass code -// None -// Boot -// Default: SL_USBD_HID_SUBCLASS_BOOT -// This defines the standard USB subclass code for this interface. -// For most use cases, you can just select "Boot". -#define SL_USBD_HID_HID0_SUBCLASS SL_USBD_HID_SUBCLASS_BOOT - -// Protocol code -// None -// Keyboard -// Mouse -// Default: SL_USBD_HID_PROTOCOL_MOUSE -// You can choose "Mouse" or "Keyboard" depending on what functionality -// this HID class instance will provide. -#define SL_USBD_HID_HID0_PROTOCOL SL_USBD_HID_PROTOCOL_NONE - -// Country code -// Not supported -// Arabic -// Belgian -// Canadian Multilingual -// Canadian French -// Czech Republic -// Danish -// Finnish -// French -// German -// Greek -// Hebrew -// Hungary -// International -// Italian -// Japan Katakana -// Korean -// Latin American -// Netherlands Dutch -// Norwegian -// Persian Farsi -// Poland -// Portuguese -// Russia -// Slovakia -// Spanish -// Swedish -// Swiss French -// Swiss German -// Switzerland -// Taiwan -// Turkish Q -// Turkish F -// United Kingdom -// United States -// Yugoslavia -// Default: SL_USBD_HID_COUNTRY_CODE_US -// If this instance is implementing a keyboard interface, this -// field helps the host operating system know which layout/language -// the keyboard is manufactured for, or which country/localization -// setting to use by default. -#define SL_USBD_HID_HID0_COUNTRY_CODE SL_USBD_HID_COUNTRY_CODE_US - -// - -// Protocol Details - -// IN polling interval -// <1=> 1ms -// <2=> 2ms -// <4=> 4ms -// <8=> 8ms -// <16=> 16ms -// <32=> 32ms -// <64=> 64ms -// <128=> 128ms -// <256=> 256ms -// <512=> 512ms -// <1024=> 1024ms -// <2048=> 2048ms -// <4096=> 4096ms -// <8192=> 8192ms -// <16384=> 16384ms -// <32768=> 32768ms -// Default: 2 -// Polling interval for input transfers, in milliseconds. -// It must be a power of 2. -#define SL_USBD_HID_HID0_INTERVAL_IN 2 - -// OUT polling interval -// <1=> 1ms -// <2=> 2ms -// <4=> 4ms -// <8=> 8ms -// <16=> 16ms -// <32=> 32ms -// <64=> 64ms -// <128=> 128ms -// <256=> 256ms -// <512=> 512ms -// <1024=> 1024ms -// <2048=> 2048ms -// <4096=> 4096ms -// <8192=> 8192ms -// <16384=> 16384ms -// <32768=> 32768ms -// Default: 2 -// Polling interval for input transfers, in milliseconds. -// It must be a power of 2. -#define SL_USBD_HID_HID0_INTERVAL_OUT 2 - -// Enable Control Read -// Default: 1 -// Enable read operations through the control transfers. -#define SL_USBD_HID_HID0_ENABLE_CTRL_RD 1 - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_HID_HID0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_winusb_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_winusb_config.h deleted file mode 100644 index 53ccff0cd9..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_class_winusb_config.h +++ /dev/null @@ -1,59 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2021 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_VENDOR_WINUSB_CONFIG_H -#define SL_USBD_VENDOR_WINUSB_CONFIG_H - -//#define DEVICE_CLASS_GUID_PROPERTY L"{432aeecd-f29b-48c7-a2ec-3261e85aca67}" - -// <<< Use Configuration Wizard in Context Menu >>> - -// Class Configuration - -// Configuration(s) to add this class instance to -// Default: all -// Comma separated list of configuration instances (like inst0, inst1) -// that this vendor class instance will be attached to. You can -// use "all" to attach the class to all configs, or use an empty -// string if you do not want to attach the interface to any configuration. -#define SL_USBD_VENDOR_WINUSB_CONFIGURATIONS "all" - -// - -// Protocol Details - -// Add interrupt endpoints -// Default: 0 -// Specifies whether we should add IN and OUT endpoints to this -// vendor class interface. -#define SL_USBD_VENDOR_WINUSB_INTERRUPT_ENDPOINTS 0 - -// Endpoint interval -// <1=> 1ms -// <2=> 2ms -// <4=> 4ms -// <8=> 8ms -// <16=> 16ms -// <32=> 32ms -// <64=> 64ms -// <128=> 128ms -// <256=> 256ms -// <512=> 512ms -// <1024=> 1024ms -// <2048=> 2048ms -// <4096=> 4096ms -// <8192=> 8192ms -// <16384=> 16384ms -// <32768=> 32768ms -// Default: 2 -// Polling interval for input/output transfers, in milliseconds. -// It must be a power of 2. -#define SL_USBD_VENDOR_WINUSB_INTERVAL 2 - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_VENDOR_WINUSB_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_config0_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_config0_config.h deleted file mode 100644 index a70da59041..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_config0_config.h +++ /dev/null @@ -1,51 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USB_CONFIGURATION_CONFIG0_CONFIG_H -#define SL_USB_CONFIGURATION_CONFIG0_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Configuration Settings - -// Configuration Name -// Default: "Main Configuration" -// This creates a string descriptor that the USB host -// can use to retrieve the name of this USB configuration descriptor. -// It can be scanned with "sudo lsusb -vv" on Linux. It appears next -// to iConfiguration field. -#define SL_USB_CONFIGURATION_CONFIG0_NAME "Main Configuration" - -// Power Source -// <0=> Bus-Powered -// <1=> Self-Powered -// Default: 1 -// Indicates whether the device will be powered using USB bus or -// or using a self-power source (like battery or a debugger) -// if the host configures the device using this configuration. -#define SL_USB_CONFIGURATION_CONFIG0_POWER_SOURCE 1 - -// Enable Remote Wakeup -// Default: 0 -// Enables or disables remote wakeup feature. -#define SL_USB_CONFIGURATION_CONFIG0_REMOTE_WAKEUP 0 - -// Maximum Power (mA) -// <100=> 100 mA -// <500=> 500 mA -// Default: 100 -// Specifies the maximum current that the device will draw. -// Most USB devices consume 100mA at most, but the USB standard -// allows the device to consume up to 500mA. When the host -// operating system scans this value, it will configure the USB port -// on the host controller to allow the device to consume the -// configured current. -#define SL_USB_CONFIGURATION_CONFIG0_MAXIMUM_POWER 100 - -// - -// <<< end of configuration section >>> -#endif // SL_USB_CONFIGURATION_CONFIG0_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h deleted file mode 100644 index 1058079e4f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_core_config.h +++ /dev/null @@ -1,199 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_CONFIG_H -#define SL_USBD_CONFIG_H - -extern char UsbClassVendorDescription[GECKO_DEVICE_CLASS_VENDOR_DESCRIPTION_PROPERTY_LEN + 1]; - -// <<< Use Configuration Wizard in Context Menu >>> - -// USB Configuration - -// Auto-start USB device -// Default: 1 -// If enabled, the USB device will be automatically started up, -// using sl_usbd_core_start_device(), by the core task (which starts -// running after kernel scheduler is ready) when the USB stack is all -// initialized. You can disable this config if you want to call -// sl_usbd_core_start_device() manually from your code. This might -// be helpful if you do not want USB to start anytime before all -// your initializations are complete, or if you want to enable/disable -// USB on demand. -#define SL_USBD_AUTO_START_USB_DEVICE 1 - -// Enable SCSI 64-Bit LBA -// Default: 0 -// MSC SCSI Configuration for enabling 64-bit LBA support. -#define SL_USBD_MSC_SCSI_64_BIT_LBA_EN 0 - -// - -// USB Core Configuration - -// Core Pools - -// Number of configurations <1-255> -// Default: 1 -// The total number of configurations. -#define SL_USBD_CONFIGURATION_QUANTITY 1 - -// Number of interfaces <1-255> -// Default: 10 -// The total number of interfaces (for all of your USB configurations). -#define SL_USBD_INTERFACE_QUANTITY 10 - -// Number of alternate interfaces <1-255> -// Default: 10 -// The total number of alternate interfaces (for all of your USB configurations). -// Must be equal to or bigger than SL_USBD_INTERFACE_QUANTITY -#define SL_USBD_ALT_INTERFACE_QUANTITY 10 - -// Number of interface groups <0-255> -// Default: 20 -// The total number of interface groups (for all of your USB configurations). -#define SL_USBD_INTERFACE_GROUP_QUANTITY 20 - -// Number of endpoint descriptors <1-255> -// Default: 20 -// The total number of endpoint descriptors (for all of your USB configurations). -#define SL_USBD_DESCRIPTOR_QUANTITY 20 - -// Number of strings <0-100> -// Default: 30 -// The total number of strings per device. -#define SL_USBD_STRING_QUANTITY 30 - -// Number of opened endpoints <2-255> -// Default: 20 -// The total number of opened endpoints per device. -#define SL_USBD_OPEN_ENDPOINTS_QUANTITY 20 - -// - -// Core Task - -// Stack size of USBD core task in bytes -// Default: 4096 -// Stack size in bytes of the USBD core task. -#define SL_USBD_TASK_STACK_SIZE 4096U - -// Priority of USBD core task -#define SL_USBD_TASK_PRIORITY 5 - -// USB CDC Configuration - -// CDC Pools - -// Number of class instances <1-255> -// Default: 2 -// Number of class instances. -#define SL_USBD_CDC_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Default: 1 -// Number of configurations. -#define SL_USBD_CDC_CONFIGURATION_QUANTITY 1 - -// Number of subclass instances <1-255> -// Default: 2 -// Number of subclass instances. -#define SL_USBD_CDC_ACM_SUBCLASS_INSTANCE_QUANTITY 2 - -// Number of data interfaces <1-255> -// Default: 2 -// Number of data interfaces. -#define SL_USBD_CDC_DATA_INTERFACE_QUANTITY 2 - -// - -// - -// USB HID Configuration - -// HID Pools - -// Number of class instances <1-255> -// Default: 2 -// Number of class instances. -#define SL_USBD_HID_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Default: 1 -// Number of configurations. -#define SL_USBD_HID_CONFIGURATION_QUANTITY 1 - -// Number of report ids <0-255> -// Default: 2 -// Number of report ids. -#define SL_USBD_HID_REPORT_ID_QUANTITY 2 - -// Number of push/pop items <0-255> -// Default: 0 -// Number of push/pop items. -#define SL_USBD_HID_PUSH_POP_ITEM_QUANTITY 0 - -// - -// HID Task - -// Stack size of USBD HID timer task in bytes -// Default: 2048 -// HID Timer task stack size in bytes. -#define SL_USBD_HID_TIMER_TASK_STACK_SIZE 2048 - -// Priority of USBD HID timer task -#define SL_USBD_HID_TIMER_TASK_PRIORITY 5 - -// USB MSC Configuration - -// MSC Pools - -// Number of class instances <1-255> -// Default: 2 -// Number of class instances. -#define SL_USBD_MSC_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Default: 1 -// Number of configurations. -#define SL_USBD_MSC_CONFIGURATION_QUANTITY 1 - -// Number of Logical Units per class instance <1-255> -// Default: 2 -// Number of Logical Units. -#define SL_USBD_MSC_LUN_QUANTITY 2 - -// Size of data buffer per class instance in bytes <1-4294967295> -// Default: 512 -// Size of data buffer in bytes. -#define SL_USBD_MSC_DATA_BUFFER_SIZE 512 - -// - -// - -// USB Vendor Configuration - -// Vendor Pools - -// Number of class instances <1-255> -// Number of class instances. -#define SL_USBD_VENDOR_CLASS_INSTANCE_QUANTITY 2 - -// Number of configurations <1-255> -// Number of configurations. -#define SL_USBD_VENDOR_CONFIGURATION_QUANTITY 2 - -// pointer to USB Class Vendor description -#define NANO_SL_USBD_CLASS_VENDOR_DESCRIPTION (const char *)&UsbClassVendorDescription - -// - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_device_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_device_config.h deleted file mode 100644 index 1b672dc998..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/sl_usbd_device_config.h +++ /dev/null @@ -1,60 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef SL_USBD_DEVICE_CONFIG_H -#define SL_USBD_DEVICE_CONFIG_H - -extern char *UsbSerialNumber[]; - -// <<< Use Configuration Wizard in Context Menu >>> - -// USB Device Configuration - -// Device Vendor ID -// Device vendor ID: Silabs. -#define SL_USBD_DEVICE_VENDOR_ID 0x10C4 - -// Device Product ID -// Device product ID. PID assigned to Skyworks Timing Gecko Dev Board -#define SL_USBD_DEVICE_PRODUCT_ID 0x8DAC - -// Device Release Number -// Default: 0x0100 -// Device release number. -#define SL_USBD_DEVICE_RELEASE_NUMBER 0x0100 - -// Device Manufacturer Name -// Device manufacturer string. -#define SL_USBD_DEVICE_MANUFACTURER_STRING "Skyworks" - -// Device Product Name -// Device product string. -// OK to have this one empty as it will be updated by the managed application when calling UsbStream::NativeOpen -#define SL_USBD_DEVICE_PRODUCT_STRING "Skyworks EVB" - -// Device Serial Number -// Device serial number string. -#define SL_USBD_DEVICE_SERIAL_NUMBER_STRING (const char *)&UsbSerialNumber - -// Device Language ID -// Arabic -// Chinese -// US English -// UK English -// French -// German -// Greek -// Italian -// Portuguese -// Sanskrit -// ID of language of strings of device. -// Default: USBD_LANG_ID_ENGLISH_US -#define SL_USBD_DEVICE_LANGUAGE_ID SL_USBD_LANG_ID_ENGLISH_US - -// - -// <<< end of configuration section >>> -#endif // SL_USBD_DEVICE_CONFIG_H diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/uartdrv_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/uartdrv_config.h deleted file mode 100644 index 118a7c901a..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/config/uartdrv_config.h +++ /dev/null @@ -1,114 +0,0 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV configuration file. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ -#define __SILICON_LABS_UARTDRV_CONFIG_H__ - -/***************************************************************************//** - * @addtogroup uartdrv - * @{ - ******************************************************************************/ -/// Size of the receive operation queue. -/// @details -/// The maximum number of receive operations that can be queued up for one -/// driver instance before @ref UARTDRV_Receive() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 2 -#endif - -/// Size of the transmit operation queue. -/// @details -/// The maximum number of transmit operations that can be queued up for one -/// driver instance before @ref UARTDRV_Transmit() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 2 -#endif - -// <<< Use Configuration Wizard in Context Menu >>> -// UARTDRV Settings - -/// Set to 1 to include flow control support -#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -// Flow control support -// <1=> Enable -// <0=> Disable -// Default: 1 -#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 -#endif - -/// Maximum number of driver instances. -#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) -// Maximum number of driver instances -// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 -// Default: 4 -#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 -#endif - -/// UART software flow control code: request peer to start TX -#if !defined(UARTDRV_FC_SW_XON) -// UART software flow control code: request peer to start TX -// Default: 0x11 -#define UARTDRV_FC_SW_XON 0x11 -#endif - -/// UART software flow control code: request peer to stop TX -#if !defined(UARTDRV_FC_SW_XOFF) -// UART software flow control code: request peer to stop TX -// Default: 0x13 -#define UARTDRV_FC_SW_XOFF 0x13 -#endif - -/// UART enable reception when sleeping. -#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) -// Enable reception when sleeping -// Enable reception when sleeping will use the power manager and add EM1 -// requirement during receive operations that use DMA. -// <1=> Enable -// <0=> Disable -// Default: 1 -#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 0 -#endif - -// - -// <<< end of configuration section >>> - -/** @} (end addtogroup uartdrv) */ - -#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/launch.json b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/launch.json deleted file mode 100644 index a4a945a94e..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/launch.json +++ /dev/null @@ -1,83 +0,0 @@ -{ - "version": "0.2.0", - "configurations": [ - { - "name": "SL_STK3701A nanoBooter", - "type": "cppdbg", - "request": "launch", - "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "program": "${workspaceRoot}/build/nanoBooter.elf", - "MIMode": "gdb", - "debugServerPath": "/JLinkGDBServerCL.exe", - "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", - "stopAtEntry": false, - "serverStarted": "Connected to target", - "cwd": "${cwd}", - "setupCommands": [ - { - "text": "file \"E:/GitHub/nf-interpreter/build/nanoBooter.elf\" " - }, - { - "text": "target extended-remote localhost:2331" - }, - { - "text": "monitor halt" - }, - { - "text": "monitor reset" - }, - { - "text": "load" - } - ], - "launchCompleteCommand": "None", - "logging": { - "moduleLoad": false, - "trace": true, - "engineLogging": false, - "programOutput": false, - "traceResponse": false, - "exceptions": true - } - }, - { - "name": "SL_STK3701A nanoCLR", - "type": "cppdbg", - "request": "launch", - "miDebuggerPath": "/bin/arm-none-eabi-gdb.exe", - "program": "${workspaceRoot}/build/nanoCLR.elf", - "MIMode": "gdb", - "debugServerPath": "/JLinkGDBServerCL.exe", - "debugServerArgs": "-if swd -speed auto -endian little -device EFM32GG11B820F2048 -localhostonly 1 -timeout 0 -vd -halt -reset -singlerun -strict -nogui", - "stopAtEntry": false, - "serverStarted": "Connected to target", - "cwd": "${cwd}", - "setupCommands": [ - { - "text": "file \"E:/GitHub/nf-interpreter/build/nanoCLR.elf\" " - }, - { - "text": "target extended-remote localhost:2331" - }, - { - "text": "monitor halt" - }, - { - "text": "monitor reset" - }, - { - "text": "load" - } - ], - "launchCompleteCommand": "None", - "logging": { - "moduleLoad": false, - "trace": true, - "engineLogging": false, - "programOutput": false, - "traceResponse": false, - "exceptions": true - } - } - ] -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/CMakeLists.txt deleted file mode 100644 index 0b7c048e56..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoBooter source files -list(APPEND NANOBOOTER_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) - -# make var global -set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld deleted file mode 100644 index 8941c58e5c..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter-DEBUG.ld +++ /dev/null @@ -1,235 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x00000000, len = 76k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x00013000, len = 0 /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if flash0 usage exceeds flash0 size */ - ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") -} - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld deleted file mode 100644 index 98793699a7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/efm32gg11b_booter.ld +++ /dev/null @@ -1,235 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x00000000, len = 48k /* space reserved for nanoBooter */ - deployment (rx) : org = 0x0000C000, len = 0 /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if flash0 usage exceeds flash0 size */ - ASSERT( LENGTH(flash0) >= (__etext + SIZEOF(.data)), "flash0 memory overflowed !") -} - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c deleted file mode 100644 index e0a0dcde98..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/main.c +++ /dev/null @@ -1,186 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include - -#include - -#include -// #include - -extern void sli_usbd_init(void); -extern void sli_usbd_configuration_config0_init(void); -extern void sli_usbd_cdc_acm_acm0_init(void); -extern void usb_device_cdc_acm_app_init(void); - -// copy from CLR define CLR_E_ENTRYPOINT_NOT_FOUND -#define CLR_E_ENTRYPOINT_NOT_FOUND ((int32_t)0xA2000000) - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; - -// byte pool configuration and definitions -#define DEFAULT_BYTE_POOL_SIZE 4096 -TX_BYTE_POOL byte_pool_0; -ALIGN_TYPE memory_area[DEFAULT_BYTE_POOL_SIZE / sizeof(ALIGN_TYPE)]; - -// threads definitions and configurations - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -ALIGN_TYPE receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// blink thread -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -ALIGN_TYPE blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(ALIGN_TYPE)]; - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // initialize block storage list and devices - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command - BlockStorageList_Initialize(); - BlockStorage_AddDevices(); - - // initialize configuration manager - // in CLR this is called in nanoHAL_Initialize() - // for nanoBooter we have to init it here to have access to network configuration blocks - // ConfigurationManager_Initialize(); - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - (uint8_t *)blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } - -#if HAL_WP_USE_USB_CDC == TRUE - sli_usbd_init(); - sli_usbd_configuration_config0_init(); - sli_usbd_cdc_acm_acm0_init(); - usb_device_cdc_acm_app_init(); -#endif - - // report successfull nanoBooter execution - ReportSuccessfullNanoBooter(); -} - -// Application entry point. -int main(void) -{ - // Initialize the board - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // configure S2 switch for input - GPIO_PinModeSet(gpioPortE, 8, gpioModeInput, 0); - - // init boot clipboard - InitBootClipboard(); - - // check if there is a request to remain on nanoBooter - // or if there is an error code for a missing deployment - if (IsToRemainInBooter() || g_BootClipboard.ErrorCode == CLR_E_ENTRYPOINT_NOT_FOUND) - { - // do not load CLR, remain in nanoBooter - } - else - { - // check if user is 'forcing' the board to remain in nanoBooter and not launching nanoCLR - // if S2 switch is pressed, skip the check for a valid CLR image and remain in booter - if (GPIO_PinInGet(gpioPortE, 8) != 0) - { - // check for valid CLR image - // we are checking for a valid image at the deployment address, which is pointing to the CLR address - if (CheckValidCLRImage((uint32_t)&__deployment_start__)) - { - // there seems to be a valid CLR image - - // need to change HF clock to internal RCO so the CLR can boot smoothly - CMU_CLOCK_SELECT_SET(HF, HFRCO); - - // launch nanoCLR - LaunchCLR((uint32_t)&__deployment_start__); - } - } - } - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/target_board.h.in deleted file mode 100644 index ec5e9be940..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoBooter/target_board.h.in +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOBOOTER_H_ -#define _TARGET_BOARD_NANOBOOTER_H_ - -#include - -#define OEMSYSTEMINFOSTRING "nanoBooter running @ @TARGET_NAME@" - -#endif // _TARGET_BOARD_NANOBOOTER_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/CMakeLists.txt deleted file mode 100644 index 966b5a01c7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) .NET Foundation and Contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoCLR source files -list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/main.c) -list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp) - -if(GECKO_FEATURE_USBD_HID) - list(APPEND NANOCLR_PROJECT_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/usb_hid_app.c) -endif() - -# make var global -set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld deleted file mode 100644 index e4ef8fc200..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR-DEBUG.ld +++ /dev/null @@ -1,246 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x00013000, len = 2M - 76k - 4k - 1092k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x000EE000, len = 1092k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld deleted file mode 100644 index d17abebca3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/efm32gg11b_CLR.ld +++ /dev/null @@ -1,246 +0,0 @@ -/***************************************************************************//** - * Linker script for Silicon Labs EFM32GG11B devices - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* Set the RAM segment used end for threadx */ -__RAM_segment_used_end__ = 0; - -MEMORY -{ - flash0 (rx) : org = 0x0000C000, len = 2M - 48k - 4k - 1776k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ - deployment (rx) : org = 0x00043000, len = 1776k /* space reserved for application deployment */ - config (rw) : org = 0x001FF000, len = 4k /* space reserved for configuration block */ - RAM (rwx): org = 0x20000000, len = 512k - 48 /* RAM */ - bootclpbrd (rwx): org = 0x2007FFD0, len = 48 /* boot clipboard area */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions flash0 and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapBase - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ -ENTRY(Reset_Handler) - -/* RAM region to be used for the boot clipboard.*/ -REGION_ALIAS("SECTION_FOR_BOOTCLIPBOARD", bootclpbrd); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", RAM); - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > flash0 - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash0 - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash0 - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - __copy_table_end__ = .; - } > flash0 - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - __zero_table_end__ = .; - } > flash0 - - /* - * - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - . = ALIGN (4); - PROVIDE (__ram_func_section_start = .); - *(.ram) - PROVIDE (__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (COPY) : - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - KEEP(*(.stack*)) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = .; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* nanoFramework CLR managed heap section at the specified RAM section.*/ - .clr_managed_heap (NOLOAD) : - { - . = ALIGN(8); - __clr_managed_heap_base__ = .; - PROVIDE(HeapBegin = .); - . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); - . = ALIGN(8); - __clr_managed_heap_end__ = .; - PROVIDE(HeapEnd = .); - } > CLR_MANAGED_HEAP_RAM - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* boot clipboard rules inclusion.*/ -INCLUDE rules_bootclipboard.ld diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c deleted file mode 100644 index 54ca65223c..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/main.c +++ /dev/null @@ -1,190 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include - -// flags for hardware events -TX_EVENT_FLAGS_GROUP nanoHardwareEvents; -extern CLR_SETTINGS clrSettings; - -// byte pool configuration and definitions -// need to be at least as big as the config sector -#define DEFAULT_BYTE_POOL_SIZE 0x2000 -TX_BYTE_POOL byte_pool_0; -uint8_t memory_area[DEFAULT_BYTE_POOL_SIZE]; - -// threads definitions and configurations -#define BLINK_THREAD_STACK_SIZE 1024 -#define BLINK_THREAD_PRIORITY 5 - -TX_THREAD blinkThread; -uint32_t blinkThreadStack[BLINK_THREAD_STACK_SIZE / sizeof(uint32_t)]; - -// receiver thread -#define RECEIVER_THREAD_STACK_SIZE 2048 -#define RECEIVER_THREAD_PRIORITY 5 - -TX_THREAD receiverThread; -uint32_t receiverThreadStack[RECEIVER_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ReceiverThread_entry(uint32_t parameter); - -// CLR thread -#define CLR_THREAD_STACK_SIZE 4092 -#define CLR_THREAD_PRIORITY 5 - -TX_THREAD clrStartupThread; -uint32_t clrStartupThreadStack[CLR_THREAD_STACK_SIZE / sizeof(uint32_t)]; -extern void ClrStartupThread_entry(uint32_t parameter); - -extern sl_status_t sl_usbd_vendor_read_bulk_sync( - uint8_t class_nbr, - void *p_buf, - uint32_t buf_len, - uint16_t timeout, - uint32_t *p_xfer_len); -extern sl_status_t sl_usbd_vendor_is_enabled(uint8_t class_nbr, bool *p_enabled); -extern void UsbStackInit(); - -void BlinkThread_entry(uint32_t parameter) -{ - (void)parameter; - - GPIO_PinOutToggle(gpioPortB, 12); - - UsbStackInit(); - - while (1) - { - GPIO_PinOutToggle(gpioPortB, 12); - tx_thread_sleep(TX_TICKS_PER_MILLISEC(1500)); - } -} - -void tx_application_define(void *first_unused_memory) -{ - (void)first_unused_memory; - uint16_t status; - - // Create a byte memory pool from which to allocate the thread stacks. - tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEFAULT_BYTE_POOL_SIZE); - - // start watchdog - Watchdog_Init(); - -#if (TRACE_TO_STDIO == TRUE) - StdioPort_Init(); -#endif - - // Create blink thread - status = tx_thread_create( - &blinkThread, - "Blink Thread", - BlinkThread_entry, - 0, - blinkThreadStack, - BLINK_THREAD_STACK_SIZE, - BLINK_THREAD_PRIORITY, - BLINK_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // Create receiver thread - status = tx_thread_create( - &receiverThread, - "Receiver Thread", - ReceiverThread_entry, - 0, - receiverThreadStack, - RECEIVER_THREAD_STACK_SIZE, - RECEIVER_THREAD_PRIORITY, - RECEIVER_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // CLR settings to launch CLR thread - memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); - - clrSettings.MaxContextSwitches = 50; - clrSettings.WaitForDebugger = false; - clrSettings.RevertToBooterOnFault = true; - - // do NOT enter debugger loop on RTM builds - // this will cause the board to keep rebooting until there is an application deployed -#if defined(BUILD_RTM) - clrSettings.EnterDebuggerLoopAfterExit = false; -#else - clrSettings.EnterDebuggerLoopAfterExit = true; -#endif - - // Create CLR startup thread - status = tx_thread_create( - &clrStartupThread, - "CLR Thread", - ClrStartupThread_entry, - (uint32_t)&clrSettings, - clrStartupThreadStack, - CLR_THREAD_STACK_SIZE, - CLR_THREAD_PRIORITY, - CLR_THREAD_PRIORITY, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - if (status != TX_SUCCESS) - { - while (1) - { - } - } - - // create HW event group - status = tx_event_flags_create(&nanoHardwareEvents, ""); - if (status != TX_SUCCESS) - { - while (1) - { - } - } -} - -// Application entry point. -int main(void) -{ - sl_system_init(); - - // configure LED READY for output - GPIO_PinModeSet(gpioPortB, 12, gpioModePushPull, 0); - - // init boot clipboard - InitBootClipboard(); - - // Enter the ThreadX kernel. Task(s) created in tx_application_define() will start running - sl_system_kernel_start(); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/nanoHAL.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/nanoHAL.cpp deleted file mode 100644 index e754dd5f80..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/nanoHAL.cpp +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/target_board.h.in b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/target_board.h.in deleted file mode 100644 index be11ba01ad..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/target_board.h.in +++ /dev/null @@ -1,18 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOCLR_H_ -#define _TARGET_BOARD_NANOCLR_H_ - -#include - -#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_NAME@" - -#endif // _TARGET_BOARD_NANOCLR_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/usb_hid_app.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/usb_hid_app.c deleted file mode 100644 index f058c33353..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/nanoCLR/usb_hid_app.c +++ /dev/null @@ -1,244 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright 2018 Silicon Laboratories Inc. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include -#include -#include - -#include -#include - -#include -#include "sl_usbd_class_hid.h" -#include - -// Task configuration -#define TASK_STACK_SIZE 512u -#define TASK_PRIO 5u -#define TASK_DELAY_MS 100u - -#define USB_HID_REPORT_LEN 4u - -// FreeRTOS Task handle -static TX_THREAD task_handle; -uint32_t hidThreadStack[TASK_STACK_SIZE / sizeof(uint32_t)]; - -// Mouse report buffer. -__ALIGNED(4) static uint8_t usb_hid_report_buffer[USB_HID_REPORT_LEN]; - -static void hid_task(uint32_t p_arg); - -// Initialize application. -void usb_device_hid_app_init(void) -{ - uint16_t status; - - // Create application task - status = tx_thread_create( - &task_handle, - "USB HID task", - hid_task, - (uint32_t)&sl_usbd_hid_hid0_number, - hidThreadStack, - TASK_STACK_SIZE, - TASK_PRIO, - TASK_PRIO, - TX_NO_TIME_SLICE, - TX_AUTO_START); - - _ASSERTE(status == TX_SUCCESS); -} - -// hid_task() -// Perform HID writes to host. -// @param p_arg Task argument pointer. Class number in this case. -static void hid_task(uint32_t p_arg) -{ - uint8_t class_nbr = *(uint8_t *)p_arg; - bool x_is_pos = true; - bool y_is_pos = true; - bool conn; - sl_status_t status; - uint32_t xfer_len = 0; - const uint32_t xDelay = TX_TICKS_PER_MILLISEC(TASK_DELAY_MS); - - usb_hid_report_buffer[0u] = 0u; - usb_hid_report_buffer[1u] = 0u; - - while (true) - { - - // Wait for device connection. - status = sl_usbd_hid_is_enabled(class_nbr, &conn); - _ASSERTE(status == SL_STATUS_OK); - - while (conn != true) - { - tx_thread_sleep(xDelay); - - status = sl_usbd_hid_is_enabled(class_nbr, &conn); - - _ASSERTE(status == SL_STATUS_OK); - } - - // Emulates back and fourth movement. - ((int8_t *)usb_hid_report_buffer)[2u] = (x_is_pos) ? 50 : -50; - ((int8_t *)usb_hid_report_buffer)[3u] = (y_is_pos) ? 50 : -50; - - x_is_pos = !x_is_pos; - y_is_pos = !y_is_pos; - - // Send report. - status = - sl_usbd_hid_write_sync(class_nbr, usb_hid_report_buffer, USB_HID_REPORT_LEN, 0u, &xfer_len); - - // Delay Task - tx_thread_sleep(xDelay); - } -} - -// USB bus events. -void sl_usbd_on_bus_event(sl_usbd_bus_event_t event) -{ - switch (event) - { - case SL_USBD_EVENT_BUS_CONNECT: - // called when usb cable is inserted in a host controller - break; - - case SL_USBD_EVENT_BUS_DISCONNECT: - // called when usb cable is removed from a host controller - break; - - case SL_USBD_EVENT_BUS_RESET: - // called when the host sends reset command - break; - - case SL_USBD_EVENT_BUS_SUSPEND: - // called when the host sends suspend command - break; - - case SL_USBD_EVENT_BUS_RESUME: - // called when the host sends wake up command - break; - - default: - break; - } -} - -// USB configuration events. -void sl_usbd_on_config_event(sl_usbd_config_event_t event, uint8_t config_nbr) -{ - (void)config_nbr; - - switch (event) - { - case SL_USBD_EVENT_CONFIG_SET: - // called when the host sets a configuration after reset - break; - - case SL_USBD_EVENT_CONFIG_UNSET: - // called when a configuration is unset due to reset command - break; - - default: - break; - } -} - -// HID mouse0 instance Enable event. -void sl_usbd_hid_hid0_on_enable_event(void) -{ - // Called when the HID device is connected to the USB host and a - // RESET transfer succeeded. -} - -// HID mouse0 instance Disable event. -void sl_usbd_hid_hid0_on_disable_event(void) -{ - // Called when the HID device is disconnected to the USB host (cable removed). -} - -// Hook function to pass the HID descriptor of the mouse0 instance. -void sl_usbd_hid_hid0_on_get_report_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - // Called during the HID mouse0 instance initialization so the USB stack - // can retrieve its HID descriptor. - (void)p_report_ptr; - (void)p_report_len; -} - -// Hook function to pass the HID PHY descriptor. -void sl_usbd_hid_hid0_on_get_phy_desc_event(const uint8_t **p_report_ptr, uint16_t *p_report_len) -{ - // Called during the HID mouse0 instance initialization so the USB stack - // can retrieve the its HID physical descriptor. - (void)p_report_ptr; - (void)p_report_len; -} - -// Notification of a new set report received on control endpoint. -// @param report_id Report ID. -// @param p_report_buf Pointer to report buffer. -// @param report_len Length of report, in octets. -void sl_usbd_hid_hid0_on_set_output_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) -{ - // This function is called when host issues a SetReport request. - // The application can take action in function of the report content. - - (void)report_id; - (void)p_report_buf; - (void)report_len; -} - -// Get HID feature report corresponding to report ID. -// @param report_id Report ID. -// @param p_report_buf Pointer to feature report buffer. -// @param report_len Length of report, in octets. -// @note (1) Report ID must not be written into the feature report buffer. -void sl_usbd_hid_hid0_on_get_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) -{ - // This function is called when host issues a GetReport(feature) request. - // The application can provide the report to send by copying it in p_report_buf. - - (void)report_id; - (void)p_report_buf; - (void)report_len; -} - -// Set HID feature report corresponding to report ID. -// @param report_id Report ID. -// @param p_report_buf Pointer to feature report buffer. -// @param report_len Length of report, in octets. -// @note (1) Report ID is not present in the feature report buffer. -void sl_usbd_hid_hid0_on_set_feature_report_event(uint8_t report_id, uint8_t *p_report_buf, uint16_t report_len) -{ - // This function is called when host issues a SetReport(Feature) request. - // The application can take action in function of the provided report in p_report_buf. - - (void)report_id; - (void)p_report_buf; - (void)report_len; -} - -// Retrieve active protocol: BOOT or REPORT protocol. -// @param p_protocol Pointer to variable that will receive the protocol type. -void sl_usbd_hid_hid0_on_get_protocol_event(uint8_t *p_protocol) -{ - // This function is called when host issues a GetProtocol request. - // The application should return the current protocol. - (void)p_protocol; -} - -// Store active protocol: BOOT or REPORT protocol. -// @param protocol Protocol. -void sl_usbd_hid_hid0_on_set_protocol_event(uint8_t protocol) -{ - // This function is called when host issues a SetProtocol request. - // The application should apply the new protocol. - (void)protocol; -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.c deleted file mode 100644 index ad32a4cff7..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.c +++ /dev/null @@ -1,19 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -extern struct BlockStorageDevice Device_BlockStorage; -extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; -extern IBlockStorageDevice SL_MscFlash_BlockStorageInterface; - -void BlockStorage_AddDevices() -{ - BlockStorageList_AddDevice( - (BlockStorageDevice *)&Device_BlockStorage, - &SL_MscFlash_BlockStorageInterface, - &Device_BlockStorageConfig, - false); -} diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.h deleted file mode 100644 index 0771bccc7b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_BlockStorage.h +++ /dev/null @@ -1,12 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef _TARGETPAL_BLOCKSTORAGE_H_ -#define _TARGETPAL_BLOCKSTORAGE_H_ 1 - -// this device has 1 block storage devices -#define TARGET_BLOCKSTORAGE_COUNT 1 - -#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp deleted file mode 100644 index 45f236e7a8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.cpp +++ /dev/null @@ -1,26 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -////////// -// I2C0 // -////////// - -// SCL: PA1 -// SDA: PA0 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) - -////////// -// I2C1 // -////////// - -// SCL: PC5 -// SDA: PC4 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h deleted file mode 100644 index ff99df51a3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_i2c_config.h +++ /dev/null @@ -1,4 +0,0 @@ -// Copyright Skyworks Solutions, Inc. All Rights Reserved. - -#define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp deleted file mode 100644 index 6c5b724749..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.cpp +++ /dev/null @@ -1,48 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -// INIT_SPI_CONFIG(num, sck_port_location, mosi_port_location, miso_port_location, cs_port_location) -// num is the USART index. For example, if using USART0 use 0. - -////////// -// SPI0 // -////////// - -// USART0 -// SCK: PE12 -// MOSI: PE10 -// MISO: PE11 -// CS: PE13 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(0, 0, 0, 0, 0) - -////////// -// SPI1 // -////////// - -// USART1 -// SCK: PD2 -// MOSI: PD0 -// MISO: PD1 -// CS: PD3 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(1, 1, 1, 1, 1) - -////////// -// SPI2 // -////////// - -// USART2 -// SCK: PB5 -// MOSI: PB3 -// MISO: PB4 -// CS: PB6 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(2, 1, 1, 1, 1) \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.h deleted file mode 100644 index bdfea3503d..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_com_sky_nf_dev_spi_config.h +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#define GECKO_USE_SPI0 TRUE -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.c deleted file mode 100644 index c2100dc5c5..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.c +++ /dev/null @@ -1,27 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include -#include "target_board.h" -#include -#include - -HAL_SYSTEM_CONFIG HalSystemConfig = { - {true}, // HAL_DRIVER_CONFIG_HEADER Header; - - 1, // ConvertCOM_DebugHandle(1), - 0, // ConvertCOM_DebugHandle(0), - 921600, - 0, // STDIO = COM2 or COM1 - - {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, - {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; - -HAL_TARGET_CONFIGURATION g_TargetConfiguration; - -// this target can use J-Link for updates -inline GET_TARGET_CAPABILITIES(TargetCapabilities_JlinkUpdate); -inline TARGET_HAS_PROPRIETARY_BOOTER(false); diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.h.in b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.h.in deleted file mode 100644 index e5a3715d66..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_common.h.in +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_COMMON_H_ -#define _TARGET_COMMON_H_ - -#include - -///////////////////////////////////////////////////////////////////////////////////////// -// The following addresses and sizes should be filled in according to the SoC data-sheet -// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR - -// RAM base address -#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) -// RAM size -#define RAM1_MEMORY_Size ((uint32_t)0x000080000) - -// FLASH base address -#define FLASH1_MEMORY_StartAddress ((uint32_t)0x00000000) -// FLASH size -#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) - -///////////////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////// -#define TARGETNAMESTRING "@TARGET_NAME@" -#define PLATFORMNAMESTRING "GGECKO_S1" -////////////////////////////////////////////// - -////////////////////////////////////////////// -// set Wire Protocol packet size -// valid sizes are 1024, 512, 256, 128 -// check Monitor_Ping_Source_Flags enum -#define WP_PACKET_SIZE 512U -////////////////////////////////////////////// - -///////////////////////////////////// -#define PLATFORM_HAS_RNG TRUE -///////////////////////////////////// - -///////////////////////////////////// -//#define EVENTS_HEART_BEAT -///////////////////////////////////// - -#endif // _TARGET_COMMON_H_ diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp deleted file mode 100644 index c6b9aca497..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.cpp +++ /dev/null @@ -1,52 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF - -/* - -#include - -// PA6 (Gecko APORT1X CH6) ADC IMON0 Channel -// PA7 (Gecko APORT2X CH7) ADC IMON1 Channel -// PA8 (Gecko APORT1X CH8) ADC IMON2 Channel -// PA9 (Gecko APORT2X CH9) ADC IMON3 Channel -// PA10 (Gecko APORT1X CH10) ADC IMON4 Channel -// PA11 (Gecko APORT2X CH11) ADC IMON5 Channel -// PA12 (Gecko APORT1X CH12) ADC IMON6 Channel -// PA13 (Gecko APORT2X CH13) ADC IMON7 Channel -// PA14 (Gecko APORT1X CH14) ADC IMON8 Channel -// PA15 (Gecko APORT2X CH15) 16 analog channel ADC mux (see docs) -// PE6 (Gecko APORT3X CH6) ADC Cal Channel - -const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { - - // IMON0 - {0, adcPosSelAPORT1XCH6}, - // - {0, adcPosSelAPORT2XCH7}, - // - {0, adcPosSelAPORT1XCH8}, - // - {0, adcPosSelAPORT2XCH9}, - // - {0, adcPosSelAPORT1XCH10}, - // - {0, adcPosSelAPORT2XCH11}, - // - {0, adcPosSelAPORT1XCH12}, - // - {0, adcPosSelAPORT2XCH13}, - // - {0, adcPosSelAPORT1XCH14}, - // - {0, adcPosSelAPORT2XCH15}, - // - {0, adcPosSelAPORT3XCH6}, -}; - -const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h deleted file mode 100644 index 115d8a0324..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nano_gg_adc_config.h +++ /dev/null @@ -1,9 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// No ADC on Si5575 CEVB" CMakePresets.json sets API_nanoFramework.GiantGecko.Adc=OFF - -#define GECKO_USE_ADC0 FALSE -#define GECKO_USE_ADC1 FALSE diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.cpp deleted file mode 100644 index 949567e829..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.cpp +++ /dev/null @@ -1,8 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h deleted file mode 100644 index b5d0ffb355..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_nf_dev_onewire_config.h +++ /dev/null @@ -1,13 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////// -// UART0 // -/////////// - -// enable USART0 -#define NF_ONEWIRE_USE_USART0 TRUE - -// remaining configuration for 1-Wire lives in: config\sl_iostream_usart_onewire_config.h diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.c b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.c deleted file mode 100644 index efb9bced52..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.c +++ /dev/null @@ -1,7 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#include diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.h deleted file mode 100644 index d560ea678f..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_stdio_config.h +++ /dev/null @@ -1,5 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.cpp deleted file mode 100644 index 370059f6f8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.cpp +++ /dev/null @@ -1,6 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.h deleted file mode 100644 index 370059f6f8..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_adc_config.h +++ /dev/null @@ -1,6 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -// THIS BOARD HAS ADC SUPPORT THROUGH GECKO ADC LIBRARY. diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.cpp deleted file mode 100644 index 6e7b275464..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.cpp +++ /dev/null @@ -1,32 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -/* - -////////// -// I2C0 // -////////// - -// pin configuration for I2C0 -// port for I2C0_SCL is: PA1 -// port for I2C0_SDA is: PA0 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(0, gpioPortA, gpioPortA, 1, 0, 0, 0) - -////////// -// I2C1 // -////////// - -// pin configuration for I2C1 -// port for I2C1_SCL is: PC5 -// port for I2C1_SDA is: PC4 - -// GPIO alternate pin function is 0 for both pins (see alternate function mapping table in device datasheet) -I2C_CONFIG_PINS(1, gpioPortC, gpioPortC, 5, 4, 0, 0) - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.h deleted file mode 100644 index c81f83afe3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_i2c_config.h +++ /dev/null @@ -1,8 +0,0 @@ -// Copyright Skyworks Solutions, Inc. All Rights Reserved. - -/* - -#define GECKO_USE_I2C0 TRUE -#define GECKO_USE_I2C1 TRUE - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_pwm_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_pwm_config.cpp deleted file mode 100644 index 7653e6d1c4..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_pwm_config.cpp +++ /dev/null @@ -1,17 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -const NF_PAL_PWM_PORT_PIN_CONFIG PwmPortPinConfig[] = { - - // using WTIMER0, CC0, PC1, location 7 - {0, 0, gpioPortC, 1, 7}, - // using WTIMER1, CC2, PI1, location 5 - {1, 2, gpioPortI, 1, 5}, - -}; - -const int PwmConfigCount = ARRAYSIZE(PwmPortPinConfig); diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.cpp deleted file mode 100644 index 3bf95a0eb3..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.cpp +++ /dev/null @@ -1,35 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#include - -/* -////////// -// SPI1 // -////////// - -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI1_SCK: PD2, location 1 -// SPI1_MOSI: PD0, location 1 -// SPI1_MISO: PD1, location 1 -// SPI1_CS: PD3, location 1 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(1, 1, 1, 1) - -////////// -// SPI2 // -////////// - -// pin configuration for SPI1 (mapped to USART1 on this device) -// SPI2_SCK: PF8, location 1 -// SPI2_MOSI: PF6, location 1 -// SPI2_MISO: PF7, location 1 -// SPI2_CS: PF9, location 1 -// EMC encoded "port location", see Alternate Functionality Overview table in MCU datasheet - -INIT_SPI_CONFIG(2, 4, 4, 4) - -*/ \ No newline at end of file diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h deleted file mode 100644 index 409945557b..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_device_spi_config.h +++ /dev/null @@ -1,7 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -#define GECKO_USE_SPI1 TRUE -#define GECKO_USE_SPI2 TRUE diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.cpp b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.cpp deleted file mode 100644 index b7c0d87a23..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.cpp +++ /dev/null @@ -1,4 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.h deleted file mode 100644 index b2d2dec961..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_system_io_ports_config.h +++ /dev/null @@ -1,5 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_tx_user.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_tx_user.h deleted file mode 100644 index 40c92111ed..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_tx_user.h +++ /dev/null @@ -1,206 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////// -// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different tx_user file -// for nanoBooter and another for nanoCLR. -/////////////////////////////////////////////////////////////////////////////////////////// - -#ifndef TX_USER_H -#define TX_USER_H - -#define TX_TIMER_TICKS_PER_SECOND 1000 - -/* Define various build options for the ThreadX port. The application should either make changes - here by commenting or un-commenting the conditional compilation defined OR supply the defines - though the compiler's equivalent of the -D option. - - For maximum speed, the following should be defined: - - TX_MAX_PRIORITIES 32 - TX_DISABLE_PREEMPTION_THRESHOLD - TX_DISABLE_REDUNDANT_CLEARING - TX_DISABLE_NOTIFY_CALLBACKS - TX_NOT_INTERRUPTABLE - TX_TIMER_PROCESS_IN_ISR - TX_REACTIVATE_INLINE - TX_DISABLE_STACK_FILLING - TX_INLINE_THREAD_RESUME_SUSPEND - - For minimum size, the following should be defined: - - TX_MAX_PRIORITIES 32 - TX_DISABLE_PREEMPTION_THRESHOLD - TX_DISABLE_REDUNDANT_CLEARING - TX_DISABLE_NOTIFY_CALLBACKS - TX_NOT_INTERRUPTABLE - TX_TIMER_PROCESS_IN_ISR - - Of course, many of these defines reduce functionality and/or change the behavior of the - system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR - results in faster and smaller code, however, it increases the amount of processing in the ISR. - In addition, some services that are available in timers are not available from ISRs and will - therefore return an error if this option is used. This may or may not be desirable for a - given application. */ - -/* Override various options with default values already assigned in tx_port.h. Please also refer - to tx_port.h for descriptions on each of these options. */ - -/* -#define TX_MAX_PRIORITIES 32 -#define TX_MINIMUM_STACK ???? -#define TX_THREAD_USER_EXTENSION ???? -#define TX_TIMER_THREAD_STACK_SIZE ???? -#define TX_TIMER_THREAD_PRIORITY ???? -*/ - -/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls - should be processed within the a system timer thread or directly in the timer ISR. - By default, the timer thread is used. When the following is defined, the timer expiration - processing is done directly from the timer ISR, thereby eliminating the timer thread control - block, stack, and context switching to activate it. */ - -/* -#define TX_TIMER_PROCESS_IN_ISR -*/ - -/* Determine if in-line timer reactivation should be used within the timer expiration processing. - By default, this is disabled and a function call is used. When the following is defined, - reactivating is performed in-line resulting in faster timer processing but slightly larger - code size. */ - -#define TX_REACTIVATE_INLINE - -/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, - which places an 0xEF pattern in each byte of each thread's stack. This is used by - debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ - -/* -#define TX_DISABLE_STACK_FILLING -*/ - -/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is - disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack - checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING - define is negated, thereby forcing the stack fill which is necessary for the stack checking - logic. */ - -/* -#define TX_ENABLE_STACK_CHECKING -*/ - -/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is - enabled. If the application does not use preemption-threshold, it may be disabled to reduce - code size and improve performance. */ - -/* -#define TX_DISABLE_PREEMPTION_THRESHOLD -*/ - -/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears - the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary - clearing of ThreadX global variables. */ - -#define TX_DISABLE_REDUNDANT_CLEARING - -/* Determine if no timer processing is required. This option will help eliminate the timer - processing when not needed. The user will also have to comment out the call to - tx_timer_interrupt, which is typically made from assembly language in - tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR - must also be used. */ - -/* -#define TX_NO_TIMER -#ifndef TX_TIMER_PROCESS_IN_ISR -#define TX_TIMER_PROCESS_IN_ISR -#endif -*/ - -/* Determine if the notify callback option should be disabled. By default, notify callbacks are - enabled. If the application does not use notify callbacks, they may be disabled to reduce - code size and improve performance. */ - -#define TX_DISABLE_NOTIFY_CALLBACKS - -/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal - code in-line. This results in a larger image, but improves the performance of the thread - resume and suspend services. */ - -/* -#define TX_INLINE_THREAD_RESUME_SUSPEND -*/ - -/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code - size and less processing overhead, but increases the interrupt lockout time. */ - -/* -#define TX_NOT_INTERRUPTABLE -*/ - -/* Determine if the trace event logging code should be enabled. This causes slight increases in - code size and overhead, but provides the ability to generate system trace information which - is available for viewing in TraceX. */ - -/* -#define TX_ENABLE_EVENT_TRACE -*/ - -/* Determine if block pool performance gathering is required by the application. When the following is - defined, ThreadX gathers various block pool performance information. */ - -/* -#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if byte pool performance gathering is required by the application. When the following is - defined, ThreadX gathers various byte pool performance information. */ - -/* -#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if event flags performance gathering is required by the application. When the following is - defined, ThreadX gathers various event flags performance information. */ - -/* -#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if mutex performance gathering is required by the application. When the following is - defined, ThreadX gathers various mutex performance information. */ - -/* -#define TX_MUTEX_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if queue performance gathering is required by the application. When the following is - defined, ThreadX gathers various queue performance information. */ - -/* -#define TX_QUEUE_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if semaphore performance gathering is required by the application. When the following is - defined, ThreadX gathers various semaphore performance information. */ - -/* -#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if thread performance gathering is required by the application. When the following is - defined, ThreadX gathers various thread performance information. */ - -/* -#define TX_THREAD_ENABLE_PERFORMANCE_INFO -*/ - -/* Determine if timer performance gathering is required by the application. When the following is - defined, ThreadX gathers various timer performance information. */ - -/* -#define TX_TIMER_ENABLE_PERFORMANCE_INFO -*/ - -#endif diff --git a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_ux_user.h b/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_ux_user.h deleted file mode 100644 index f655c33739..0000000000 --- a/targets/AzureRTOS/SiliconLabs/Si5575_CEVB/target_ux_user.h +++ /dev/null @@ -1,345 +0,0 @@ -// -// Copyright (c) .NET Foundation and Contributors -// See LICENSE file in the project root for full license information. -// - -/////////////////////////////////////////////////////////////////////////////////////////// -// At this time(Azure RTOS v6.1.7_rel) it's not possible to have a different ux_user file -// for nanoBooter and another for nanoCLR. -/////////////////////////////////////////////////////////////////////////////////////////// - -#ifndef UX_USER_H -#define UX_USER_H - -/* Define various build options for the USBX port. The application should either make changes - here by commenting or un-commenting the conditional compilation defined OR supply the defines - though the compiler's equivalent of the -D option. */ -/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ - -/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ -/* -#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE -*/ - - -/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ -/* -#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE -*/ - -/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ -/* -#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE -*/ - -/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please - also refer to ux_port.h for descriptions on each of these options. */ - -/* Defined, this value represents how many ticks per seconds for a specific hardware platform. - The default is 1000 indicating 1 tick per millisecond. */ - -/* #define UX_PERIODIC_RATE 1000 -*/ -#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) - -/* Define control transfer timeout value in millisecond. - The default is 10000 milliseconds. */ -/* -#define UX_CONTROL_TRANSFER_TIMEOUT 10000 -*/ - -/* Define non control transfer timeout value in millisecond. - The default is 50000 milliseconds. */ -/* -#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 -*/ - - -/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value - represents the class container and not the number of instances of a class. For instance, if a - particular implementation of USBX needs the hub class, the printer class, and the storage - class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices - that belong to these classes. */ - -#define UX_MAX_CLASSES 1 - - -/* Defined, this value is the maximum number of classes in the device stack that can be loaded by - USBX. */ - -/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 -*/ - -/* Defined, this value is the maximum number of interfaces in the device framework. */ - -/* #define UX_MAX_SLAVE_INTERFACES 16 -*/ - -/* Defined, this value represents the number of different host controllers available in the system. - For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more - than 1. This value represents the number of concurrent host controllers running at the same time. - If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller - running, the UX_MAX_HCD should be set to 2. */ - -/* #define UX_MAX_HCD 1 -*/ - - -/* Defined, this value represents the maximum number of devices that can be attached to the USB. - Normally, the theoretical maximum number on a single USB is 127 devices. This value can be - scaled down to conserve memory. Note that this value represents the total number of devices - regardless of the number of USB buses in the system. */ - -/* #define UX_MAX_DEVICES 127 -*/ - - -/* Defined, this value represents the current number of SCSI logical units represented in the device - storage class driver. */ - -/* #define UX_MAX_SLAVE_LUN 1 -*/ - - -/* Defined, this value represents the maximum number of SCSI logical units represented in the - host storage class driver. */ - -/* #define UX_MAX_HOST_LUN 1 -*/ - - -/* Defined, this value represents the maximum number of bytes received on a control endpoint in - the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ - -/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 -*/ - - -/* Defined, this value represents the maximum number of bytes that can be received or transmitted - on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default - is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage - class, this value cannot be less than 2048. */ - -#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) - - -/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. -*/ - -/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ - - -/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. - The default is 8K bytes but can be reduced in memory constrained environments. */ -#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) - -/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ - -/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE - */ - -/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values - depend on the type of host controller and can be reduced in memory constrained environments. */ - -#define UX_MAX_ED 80 -#define UX_MAX_TD 128 -#define UX_MAX_ISO_TD 1 - -/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined - in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse - it can be reduced a lot. */ - -#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 1024 - -/* Defined, this value represents the maximum number of HID usages for a HID device. - Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ - -#define UX_HOST_CLASS_HID_USAGES 512 - - -/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get - (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed - or released. The report contains every key that is down). There are limitations to this method such as not being - able to determine when a key has been released. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses - and key releases. */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ - -/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; - key released/up changes are not reported. - */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ - -/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. - */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ - -/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. - - Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. - */ - -/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ - - -/* Defined, this value represents the maximum number of media for the host storage class. - Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ - -#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 - -/* Defined, this value includes code to handle storage devices that use the CB - or CBI protocol (such as floppy disks). It is off by default because these - protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol - which virtually all modern storage devices use. -*/ - -/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ - -/* Defined, this value forces the memory allocation scheme to enforce alignment - of memory with the UX_SAFE_ALIGN field. -*/ - -/* #define UX_ENFORCE_SAFE_ALIGNMENT */ - -/* Defined, this value represents the number of packets in the CDC_ECM device class. - The default is 16. -*/ - -#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 - -/* Defined, this value represents the number of packets in the CDC_ECM host class. - The default is 16. -*/ - -/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ - -/* Defined, this value represents the number of milliseconds to wait for packet - allocation until invoking the application's error callback and retrying. - The default is 1000 milliseconds. -*/ - -/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ - -/* Defined, this value represents the number of milliseconds to wait for packet - pool availability checking loop. - The default is 100 milliseconds. -*/ - -/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ - -/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ - -/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ - -/* Defined, this value represents the number of milliseconds to wait for packet - allocation until invoking the application's error callback and retrying. -*/ - -/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ - -/* Defined, this value represents the the maximum length of HID reports on the - device. - */ - -/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ - -/* Defined, this value represents the the maximum number of HID events/reports - that can be queued at once. - */ - -/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ - - -/* Defined, this macro will disable DFU_UPLOAD support. */ - -/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ - -/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ - -/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ - -/* Defined, this macro will change status mode. - 0 - simple mode, - status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, - no bwPollTimeout. - 1 - status is queried from application once requested, - b0-3 : media status - b4-7 : bStatus - b8-31: bwPollTimeout - bwPollTimeout supported. -*/ - -/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ - -/* Defined, this value represents the default DFU status bwPollTimeout. - The value is 3 bytes long (max 0xFFFFFFu). - By default the bwPollTimeout is 1 (means 1ms). - */ - -/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ - -/* Defined, this macro will enable custom request process callback. */ - -/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ - -/* Defined, this macro disables CDC ACM non-blocking transmission support. */ - -/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ - -/* Defined, this macro enables device bi-directional-endpoint support. */ - -/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ - -/* Defined, this value will only enable the host side of usbx. */ -/* #define UX_HOST_SIDE_ONLY */ - -/* Defined, this value will only enable the device side of usbx. */ -/* #define UX_DEVICE_SIDE_ONLY */ - -/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. -*/ - -#ifndef UX_HOST_SIDE_ONLY -#ifndef UX_DEVICE_SIDE_ONLY - -/* #define UX_OTG_SUPPORT */ - -#endif -#endif - -/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. -*/ - -#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) - -/* Defined, this value represents the size of the log pool. -*/ -#define UX_DEBUG_LOG_SIZE (1024 * 16) - - -/* Defined, this enables the assert checks inside usbx. */ -#define UX_ENABLE_ASSERT - -/* Defined, this defines the assert action taken when failure detected. By default - it halts without any output. */ -/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ - - -/* DEBUG includes and macros for a specific platform go here. */ -#ifdef UX_INCLUDE_USER_DEFINE_BSP -#include "usb_bsp.h" -#include "usbh_hcs.h" -#include "usbh_stdreq.h" -#include "usbh_core.h" -#endif - -#endif - diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c index a77c685ecf..4b2cfd6269 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/targetPAL.c @@ -27,7 +27,7 @@ void UsbStackInit() #if GECKO_FEATURE_USBD_HID == TRUE || HAL_WP_USE_USB_CDC == TRUE || GECKO_FEATURE_USBD_WINUSB == TRUE // wait a couple of seconds to allow all other threads to init - tx_thread_sleep(TX_TICKS_PER_MILLISEC(4000)); + tx_thread_sleep(TX_TICKS_PER_MILLISEC(2000)); // can't call USBD init twice sli_usbd_init(); From 4fcce71a5e29d5ad3628e2ce20b6e48d04f090f9 Mon Sep 17 00:00:00 2001 From: Mike Muegel Date: Wed, 13 Nov 2024 13:23:55 -0600 Subject: [PATCH 558/572] Skyworks EVBs: remove old now unused Si5575_CEVB and Si5400_CEVB targets: missed a needed change --- targets/AzureRTOS/CMakePresets.json | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/AzureRTOS/CMakePresets.json b/targets/AzureRTOS/CMakePresets.json index 83a0579817..3bc42da5af 100644 --- a/targets/AzureRTOS/CMakePresets.json +++ b/targets/AzureRTOS/CMakePresets.json @@ -3,8 +3,6 @@ "include": [ "SiliconLabs/SL_STK3701A/CMakePresets.json", "SiliconLabs/SKY_EEVB/CMakePresets.json", - "SiliconLabs/Si5575_CEVB/CMakePresets.json", - "SiliconLabs/Si5400_CEVB/CMakePresets.json", "SiliconLabs/SKY_CEVB1/CMakePresets.json", "SiliconLabs/STB_Interposer/CMakePresets.json", "SiliconLabs/FIELD_PROG/CMakePresets.json", From 3f4530c4e83bf448ad8c35af1ef5d96b9c450c70 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 21 Nov 2024 13:47:39 +0000 Subject: [PATCH 559/572] Turn OFF build options required by Profiler - Not needed anymore as debugging of GC and heap allocation issues has been completed. --- targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json | 4 ++-- targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json | 4 ++-- targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json | 4 ++-- .../AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json index 31167607ee..940675f6da 100644 --- a/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/FIELD_PROG/CMakePresets.json @@ -25,8 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", diff --git a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json index 2e222252a3..1aa84f401a 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_CEVB1/CMakePresets.json @@ -25,8 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", diff --git a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json index 9a6d2ed81e..f82c4f1465 100644 --- a/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/SKY_EEVB/CMakePresets.json @@ -25,8 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", "NF_CLR_NO_IL_INLINE": "ON", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", diff --git a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json index 21e007296b..273958d9fb 100644 --- a/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json +++ b/targets/AzureRTOS/SiliconLabs/STB_Interposer/CMakePresets.json @@ -25,8 +25,8 @@ "NF_FEATURE_HAS_SDCARD": "OFF", "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", "NF_FEATURE_WATCHDOG": "OFF", - "NF_PROFILE_NEW_ALLOCATIONS": "ON", - "NF_TRACE_MEMORY_STATS": "ON", + "NF_PROFILE_NEW_ALLOCATIONS": "OFF", + "NF_TRACE_MEMORY_STATS": "OFF", "API_System.Math": "ON", "API_Hardware.GiantGecko": "ON", "API_System.Device.Gpio": "ON", From d15c4e113da8fd9169fad0138915e2e9dae5783d Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 21 Nov 2024 17:35:28 +0000 Subject: [PATCH 560/572] Add new API DebugSessionIsActive() --- src/HAL/Include/nanoHAL_v2.h | 1 + src/HAL/nanoHAL_SystemInformation.cpp | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/HAL/Include/nanoHAL_v2.h b/src/HAL/Include/nanoHAL_v2.h index e18625b777..233a66ef94 100644 --- a/src/HAL/Include/nanoHAL_v2.h +++ b/src/HAL/Include/nanoHAL_v2.h @@ -227,6 +227,7 @@ extern "C" // target specific handler for power mode changes (may be empty) void CPU_SetPowerModeTarget(PowerLevel_type powerLevel); bool DebuggerIsConnected(); + bool DebugSessionIsActive(); #ifdef __cplusplus } diff --git a/src/HAL/nanoHAL_SystemInformation.cpp b/src/HAL/nanoHAL_SystemInformation.cpp index 7bc18c5de0..a5cfb524ad 100644 --- a/src/HAL/nanoHAL_SystemInformation.cpp +++ b/src/HAL/nanoHAL_SystemInformation.cpp @@ -69,3 +69,8 @@ bool DebuggerIsConnected() { return ((g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions & CLR_RT_ExecutionEngine::c_fDebugger_Enabled) != 0); } + +bool DebugSessionIsActive() +{ + return ((g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions & CLR_RT_ExecutionEngine::c_fDebugger_SourceLevelDebugging) != 0); +} From 2d8f2fbe7744fe1aaca128710bb50b69f030fc6f Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 21 Nov 2024 17:36:16 +0000 Subject: [PATCH 561/572] Replace API to check if USB code can be restarted --- .../_common/autogen/sl_usbd_class_vendor_instances.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c index 8f7215bd57..54d5cf0fc3 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c +++ b/targets/AzureRTOS/SiliconLabs/_common/autogen/sl_usbd_class_vendor_instances.c @@ -117,8 +117,8 @@ sl_status_t sli_usbd_vendor_winusb_init() if (deviceState > SL_USBD_DEVICE_STATE_INIT) { - // device is already initialized, stop USB core, **ONLY** if there isn't a debugger connected - if (!DebuggerIsConnected()) + // device is already initialized, stop USB core, **ONLY** if there isn't an active debug session + if (!DebugSessionIsActive()) { sl_usbd_core_stop_device(); From 8c6f558ec238c715cb17c48a999a503cadbf96cd Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 12 Dec 2024 11:58:48 +0000 Subject: [PATCH 562/572] Port improvements of STM32 hard fault handler - 1c9faa3a82caa7cbf2c09648a5ed5297793dba03 - Remove code sections of STM32 series, which do not belong here. --- .../SiliconLabs/_common/hard_fault_handler.c | 233 ++++++++++++------ 1 file changed, 160 insertions(+), 73 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c b/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c index a9f03e98e2..ada17d331a 100644 --- a/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c +++ b/targets/AzureRTOS/SiliconLabs/_common/hard_fault_handler.c @@ -6,8 +6,9 @@ #include #include -//See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html -typedef enum { +// See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html +typedef enum +{ Reset = 1, NMI = 2, HardFault = 3, @@ -20,23 +21,27 @@ typedef enum { typedef void *regarm_t; // This structure represents the stack frame saved during an interrupt handler. -struct port_extctx { - regarm_t spsr_irq; - regarm_t lr_irq; - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_usr; +struct port_extctx +{ + regarm_t spsr_irq; + regarm_t lr_irq; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_usr; }; -void NMI_Handler(void) { - while(1); +void NMI_Handler(void) +{ + while (1) + ; } -// dev note: on all the following the variables need to be declared as volatile so they don't get optimized out by the linker -// dev note: the pragma below is to ignore the warning because the variables aren't actually being used despite needing to remain there for debug +// dev note: on all the following the variables need to be declared as volatile so they don't get optimized out by the +// linker dev note: the pragma below is to ignore the warning because the variables aren't actually being used despite +// needing to remain there for debug #ifdef __GNUC__ #pragma GCC diagnostic push @@ -46,46 +51,77 @@ void NMI_Handler(void) { // hard fault handler for Cortex-M3 & M4 -void HardFault_Handler(void) { +void HardFault_Handler(void) +{ - //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + // Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info struct port_extctx ctx; - //Get thread context. Contains main registers including PC and LR - memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + // Get thread context. Contains main registers including PC and LR + memcpy(&ctx, (void *)__get_PSP(), sizeof(struct port_extctx)); (void)ctx; - //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + // Interrupt status register: Which interrupt have we encountered, e.g. HardFault? volatile FaultType faultType = (FaultType)__get_IPSR(); // these are not available in all the STM32 series - //Flags about hardfault / busfault - //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference - volatile bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false); - volatile bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false); - volatile bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false); - volatile bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false); - volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false); + // Flags about hardfault / busfault + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + // Configurable Fault Status Register + volatile uint32_t _CFSR = SCB->CFSR; + + // IACCVIOL: Instruction access violation + volatile bool isFaultInstructionAccessViolation = ((_CFSR & (1 << 0)) ? true : false); + // DACCVIOL: Data access violation + volatile bool isFaultDataAccessViolation = ((_CFSR & (1 << 1)) ? true : false); + // MUNSTKERR: Unstacking error + volatile bool isFaultUnstackingError = ((_CFSR & (1 << 3)) ? true : false); + // MSTKERR: Stacking error + volatile bool isFaultStackingError = ((_CFSR & (1 << 4)) ? true : false); + // MMARVALID: MMAR is valid + volatile bool isMarkedMemoryAddressValid = ((_CFSR & (1 << 7)) ? true : false); + // IBUSERR: Instruction bus error + volatile bool isFaultInstructionBusError = ((_CFSR & (1 << 8)) ? true : false); + // PRECISERR: Precise data bus error + volatile bool isFaultPreciseDataBusError = ((_CFSR & (1 << 9)) ? true : false); + // IMPRECISERR: Imprecise data bus error + volatile bool isFaultImpreciseDataBusError = ((_CFSR & (1 << 10)) ? true : false); + // LSPERR: Lazy state preservation error + volatile bool isFaultLazyStatePreservationError = ((_CFSR & (1 << 13)) ? true : false); + // BFARVALID: BFAR is valid + volatile bool isFaultBusFaultAddressValid = ((_CFSR & (1 << 15)) ? true : false); + // UNDEFINSTR: Undefined instruction usage fault + volatile bool isUndefinedInstructionUsageFault = ((_CFSR & (1 << 16)) ? true : false); + // INVSTATE: Invalid state usage fault + volatile bool isInvalidStateUsageFault = ((_CFSR & (1 << 17)) ? true : false); + // INVPC: Invalid PC load usage fault + volatile bool isInvalidPcLoadUsageFault = ((_CFSR & (1 << 18)) ? true : false); + // NOCP: No coprocessor usage fault + volatile bool isNoCoprocessorUsageFault = ((_CFSR & (1 << 19)) ? true : false); + // UNALIGNED: Unaligned access usage fault + volatile bool isUnalignedAccessUsageFault = ((_CFSR & (1 << 24)) ? true : false); + // DIVBYZERO: Divide by zero usage fault + volatile bool isDivideByZeroUsageFault = ((_CFSR & (1 << 25)) ? true : false); // Hard Fault Status Register - volatile unsigned long _HFSR = (*((volatile unsigned long *)(0xE000ED2C))) ; + volatile unsigned long _HFSR = (*((volatile unsigned long *)(0xE000ED2C))); // Debug Fault Status Register - volatile unsigned long _DFSR = (*((volatile unsigned long *)(0xE000ED30))) ; + volatile unsigned long _DFSR = (*((volatile unsigned long *)(0xE000ED30))); // Auxiliary Fault Status Register - volatile unsigned long _AFSR = (*((volatile unsigned long *)(0xE000ED3C))) ; + volatile unsigned long _AFSR = (*((volatile unsigned long *)(0xE000ED3C))); // Read the Fault Address Registers. These may not contain valid values. // Check BFARVALID/MMARVALID to see if they are valid values - + // MemManage Fault Address Register - volatile unsigned long _MMAR = (*((volatile unsigned long *)(0xE000ED34))) ; - - //For HardFault/BusFault this is the address that was accessed causing the error + volatile unsigned long _MMAR = (*((volatile unsigned long *)(0xE000ED34))); + + // For HardFault/BusFault this is the address that was accessed causing the error volatile uint32_t faultAddress = SCB->BFAR; - + // forces a breakpoint causing the debugger to stop // if no debugger is attached this is ignored __asm volatile("BKPT #0\n"); @@ -96,31 +132,56 @@ void HardFault_Handler(void) { void BusFault_Handler(void) __attribute__((alias("HardFault_Handler"))); -void UsageFault_Handler(void) { +void UsageFault_Handler(void) +{ - //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info - //Get thread context. Contains main registers including PC and LR + // Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + // Get thread context. Contains main registers including PC and LR struct port_extctx ctx; - memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + memcpy(&ctx, (void *)__get_PSP(), sizeof(struct port_extctx)); (void)ctx; - //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + // Interrupt status register: Which interrupt have we encountered, e.g. HardFault? FaultType faultType = (FaultType)__get_IPSR(); (void)faultType; - // these are not available in all the STM32 series - #if defined(STM32L4XX_HAL_VERSION) - - //Flags about hardfault / busfault - //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference - volatile bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false); - volatile bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false); - volatile bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false); - volatile bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false); - volatile bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false); - volatile bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false); - - #endif + // Flags about hardfault / busfault + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + // Configurable Fault Status Register + volatile uint32_t _CFSR = SCB->CFSR; + + // IACCVIOL: Instruction access violation + volatile bool isFaultInstructionAccessViolation = ((_CFSR & (1 << 0)) ? true : false); + // DACCVIOL: Data access violation + volatile bool isFaultDataAccessViolation = ((_CFSR & (1 << 1)) ? true : false); + // MUNSTKERR: Unstacking error + volatile bool isFaultUnstackingError = ((_CFSR & (1 << 3)) ? true : false); + // MSTKERR: Stacking error + volatile bool isFaultStackingError = ((_CFSR & (1 << 4)) ? true : false); + // MMARVALID: MMAR is valid + volatile bool isMarkedMemoryAddressValid = ((_CFSR & (1 << 7)) ? true : false); + // IBUSERR: Instruction bus error + volatile bool isFaultInstructionBusError = ((_CFSR & (1 << 8)) ? true : false); + // PRECISERR: Precise data bus error + volatile bool isFaultPreciseDataBusError = ((_CFSR & (1 << 9)) ? true : false); + // IMPRECISERR: Imprecise data bus error + volatile bool isFaultImpreciseDataBusError = ((_CFSR & (1 << 10)) ? true : false); + // LSPERR: Lazy state preservation error + volatile bool isFaultLazyStatePreservationError = ((_CFSR & (1 << 13)) ? true : false); + // BFARVALID: BFAR is valid + volatile bool isFaultBusFaultAddressValid = ((_CFSR & (1 << 15)) ? true : false); + // UNDEFINSTR: Undefined instruction usage fault + volatile bool isUndefinedInstructionUsageFault = ((_CFSR & (1 << 16)) ? true : false); + // INVSTATE: Invalid state usage fault + volatile bool isInvalidStateUsageFault = ((_CFSR & (1 << 17)) ? true : false); + // INVPC: Invalid PC load usage fault + volatile bool isInvalidPcLoadUsageFault = ((_CFSR & (1 << 18)) ? true : false); + // NOCP: No coprocessor usage fault + volatile bool isNoCoprocessorUsageFault = ((_CFSR & (1 << 19)) ? true : false); + // UNALIGNED: Unaligned access usage fault + volatile bool isUnalignedAccessUsageFault = ((_CFSR & (1 << 24)) ? true : false); + // DIVBYZERO: Divide by zero usage fault + volatile bool isDivideByZeroUsageFault = ((_CFSR & (1 << 25)) ? true : false); // forces a breakpoint causing the debugger to stop // if no debugger is attached this is ignored @@ -130,33 +191,59 @@ void UsageFault_Handler(void) { NVIC_SystemReset(); } -void MemManage_Handler(void) { +void MemManage_Handler(void) +{ - //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info - //Get thread context. Contains main registers including PC and LR + // Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + // Get thread context. Contains main registers including PC and LR struct port_extctx ctx; - memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + memcpy(&ctx, (void *)__get_PSP(), sizeof(struct port_extctx)); (void)ctx; - //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + // Interrupt status register: Which interrupt have we encountered, e.g. HardFault? FaultType faultType = (FaultType)__get_IPSR(); (void)faultType; - // these are not available in all the STM32 series - #if defined(STM32L4XX_HAL_VERSION) - - //For HardFault/BusFault this is the address that was accessed causing the error + // For HardFault/BusFault this is the address that was accessed causing the error volatile uint32_t faultAddress = SCB->MMFAR; - //Flags about hardfault / busfault - //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference - volatile bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false); - volatile bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false); - volatile bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false); - volatile bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false); - volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false); - - #endif + // Flags about hardfault / busfault + // See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + // Configurable Fault Status Register + volatile uint32_t _CFSR = SCB->CFSR; + + // IACCVIOL: Instruction access violation + volatile bool isFaultInstructionAccessViolation = ((_CFSR & (1 << 0)) ? true : false); + // DACCVIOL: Data access violation + volatile bool isFaultDataAccessViolation = ((_CFSR & (1 << 1)) ? true : false); + // MUNSTKERR: Unstacking error + volatile bool isFaultUnstackingError = ((_CFSR & (1 << 3)) ? true : false); + // MSTKERR: Stacking error + volatile bool isFaultStackingError = ((_CFSR & (1 << 4)) ? true : false); + // MMARVALID: MMAR is valid + volatile bool isMarkedMemoryAddressValid = ((_CFSR & (1 << 7)) ? true : false); + // IBUSERR: Instruction bus error + volatile bool isFaultInstructionBusError = ((_CFSR & (1 << 8)) ? true : false); + // PRECISERR: Precise data bus error + volatile bool isFaultPreciseDataBusError = ((_CFSR & (1 << 9)) ? true : false); + // IMPRECISERR: Imprecise data bus error + volatile bool isFaultImpreciseDataBusError = ((_CFSR & (1 << 10)) ? true : false); + // LSPERR: Lazy state preservation error + volatile bool isFaultLazyStatePreservationError = ((_CFSR & (1 << 13)) ? true : false); + // BFARVALID: BFAR is valid + volatile bool isFaultBusFaultAddressValid = ((_CFSR & (1 << 15)) ? true : false); + // UNDEFINSTR: Undefined instruction usage fault + volatile bool isUndefinedInstructionUsageFault = ((_CFSR & (1 << 16)) ? true : false); + // INVSTATE: Invalid state usage fault + volatile bool isInvalidStateUsageFault = ((_CFSR & (1 << 17)) ? true : false); + // INVPC: Invalid PC load usage fault + volatile bool isInvalidPcLoadUsageFault = ((_CFSR & (1 << 18)) ? true : false); + // NOCP: No coprocessor usage fault + volatile bool isNoCoprocessorUsageFault = ((_CFSR & (1 << 19)) ? true : false); + // UNALIGNED: Unaligned access usage fault + volatile bool isUnalignedAccessUsageFault = ((_CFSR & (1 << 24)) ? true : false); + // DIVBYZERO: Divide by zero usage fault + volatile bool isDivideByZeroUsageFault = ((_CFSR & (1 << 25)) ? true : false); // forces a breakpoint causing the debugger to stop // if no debugger is attached this is ignored @@ -175,9 +262,9 @@ void MemManage_Handler(void) { // Call this to cause a hard fault by accessing a nonexistent memory address @ 0xCCCCCCCC. void HardFaultTest() { - volatile uint32_t*p; + volatile uint32_t *p; uint32_t n; - p = (uint32_t*)0xCCCCCCCC; + p = (uint32_t *)0xCCCCCCCC; n = *p; (void)n; } From 8400d577bd1e5e5c1e6e010ff69cfdc0e56ba38f Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 16 Dec 2024 15:17:03 +0000 Subject: [PATCH 563/572] Improvements in WP packet header handler - Add code to handle edge cases that could run into buffer access issues in odd cases. - Remove ShiftBufferToLeft as it wasn't adding any value to the code, actually making it hard to read. --- src/CLR/WireProtocol/WireProtocol_Message.c | 45 +++++++++++++++------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/src/CLR/WireProtocol/WireProtocol_Message.c b/src/CLR/WireProtocol/WireProtocol_Message.c index 95ef1b7c47..9f164dd643 100644 --- a/src/CLR/WireProtocol/WireProtocol_Message.c +++ b/src/CLR/WireProtocol/WireProtocol_Message.c @@ -62,12 +62,7 @@ bool IsMarkerMatched(void *header, const void *marker, size_t len) return memcmp(header, marker, len) == 0; } -void ShiftBufferToLeft(void *buffer, uint32_t len) -{ - memmove((uint8_t *)buffer, ((uint8_t *)buffer + 1), len - 1); -} - -void SyncToMessageStart() +bool SyncToMessageStart() { uint32_t len; @@ -88,16 +83,33 @@ void SyncToMessageStart() break; } - ShiftBufferToLeft(&_inboundMessage.m_header, len); + // Calculate the source and destination pointers + uint8_t *src = (uint8_t *)&_inboundMessage.m_header + 1; + uint8_t *dst = (uint8_t *)&_inboundMessage.m_header; + size_t moveLength = len - 1; - // update pointer and expected size + // Ensure that the memory regions do not exceed allocated bounds + if ((src + moveLength > (uint8_t *)&_inboundMessage + sizeof(_inboundMessage)) || + (dst + moveLength > (uint8_t *)&_inboundMessage + sizeof(_inboundMessage))) + { + return false; + } + + // Perform the memory move + memmove(dst, src, moveLength); + + // Update pointer and expected size _pos--; _size++; - // sanity checks - _ASSERTE(_size <= sizeof(_inboundMessage.m_header)); - _ASSERTE(_pos >= (uint8_t *)&(_inboundMessage.m_header)); + // Sanity checks + if (_size > sizeof(_inboundMessage.m_header) || _pos < (uint8_t *)&_inboundMessage.m_header) + { + return false; + } } + + return true; } void WP_ReplyToCommand(WP_Message *message, uint8_t fSuccess, uint8_t fCritical, void *ptr, uint32_t size) @@ -357,7 +369,16 @@ void WP_Message_Process() } } - SyncToMessageStart(); + if(!SyncToMessageStart()) + { + // something went wrong + TRACE0(TRACE_ERRORS, "RxError: Failed to sync to message start\n"); + + RestartStateMachine(); + + // exit the loop to allow other RTOS threads to run + return; + } if (len >= sizeof(_inboundMessage.m_header.m_signature)) { From de2103c7960d84bd7c0564efaf79419bdd39183b Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 16 Dec 2024 15:18:10 +0000 Subject: [PATCH 564/572] Add asserts and sanity checks on HB Array handling --- src/CLR/Core/CLR_RT_HeapBlock_Array.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp b/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp index 928c73702b..dcde26a4d3 100644 --- a/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp +++ b/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp @@ -322,6 +322,20 @@ HRESULT CLR_RT_HeapBlock_Array::Copy( dataSrc += indexSrc * sizeElem; dataDst += indexDst * sizeElem; +#if !defined(BUILD_RTM) + // Validate pointers and memory ranges + if (dataSrc == nullptr || dataDst == nullptr || + dataSrc + length * sizeElem > arraySrc->GetFirstElement() + arraySrc->m_numOfElements * sizeElem || + dataDst + length * sizeElem > arrayDst->GetFirstElement() + arrayDst->m_numOfElements * sizeElem) + { +#ifdef DEBUG + _ASSERTE(FALSE); +#endif + + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } +#endif + if (!arraySrc->m_fReference) { memmove(dataDst, dataSrc, length * sizeElem); From 9ca8d9dbcac40e65f66c183c6b3b4077e573378b Mon Sep 17 00:00:00 2001 From: josesimoes Date: Mon, 16 Dec 2024 15:18:44 +0000 Subject: [PATCH 565/572] Add asserts on GC compaction - Addressing potential issues with heap compaction execution. --- src/CLR/Core/GarbageCollector_Compaction.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/CLR/Core/GarbageCollector_Compaction.cpp b/src/CLR/Core/GarbageCollector_Compaction.cpp index 1cb62d0b1c..bc1eba6cef 100644 --- a/src/CLR/Core/GarbageCollector_Compaction.cpp +++ b/src/CLR/Core/GarbageCollector_Compaction.cpp @@ -256,6 +256,16 @@ void CLR_RT_GarbageCollector::Heap_Compact() freeRegion->Unlink(); + #ifdef _DEBUG + + _ASSERTE(relocCurrent->m_destination >= (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode()); + _ASSERTE(relocCurrent->m_destination < (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.LastNode()); + _ASSERTE(relocCurrent->m_start >= (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode()); + _ASSERTE(relocCurrent->m_start < (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.LastNode()); + _ASSERTE(moveBytes <= freeRegion_Size); + + #endif + memmove(relocCurrent->m_destination, relocCurrent->m_start, moveBytes); if (freeRegion_Size) From f1baac118a24cfc3735559b2a8ed9a150595ba88 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Tue, 17 Dec 2024 15:09:39 +0000 Subject: [PATCH 566/572] Update Gecko SDK to 4.4.5 --- targets/AzureRTOS/SiliconLabs/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt index 1ab5db9536..5fd5e215ba 100644 --- a/targets/AzureRTOS/SiliconLabs/CMakeLists.txt +++ b/targets/AzureRTOS/SiliconLabs/CMakeLists.txt @@ -71,7 +71,7 @@ endif() if(GECKO_SDK_VERSION_EMPTY) # no Gecko SDK version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(GECKO_SDK_VERSION "v4.4.4") + set(GECKO_SDK_VERSION "v4.4.5") endif() if(NO_GECKO_SDK_SOURCE) From 89da363ec38a6f1b0a1565810781e8e634b6beb5 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 19 Dec 2024 17:49:03 +0000 Subject: [PATCH 567/572] Migrate SPI code to new Gecko SDK - Update nano implementation of Gecko SPI. - Port back code from Gecko SDK. - Update declarations. --- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 20 +- .../System.Device.Spi/nf_gecko_spi_driver.cpp | 3396 +++++++++++------ .../System.Device.Spi/nf_gecko_spi_driver.h | 46 +- 3 files changed, 2242 insertions(+), 1220 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 458bec7023..f3c12b9314 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -111,7 +111,7 @@ void SpiTransferCompleteCallback(NF_SpiDriver_Handle_t handle, Ecode_t transferS // // half duplex operation, clear output enable bit // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_Receive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + NF_SpiDriver_MReceive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); } else { @@ -325,7 +325,7 @@ HRESULT CPU_SPI_nWrite_nRead( { // Full duplex // Uses the largest buffer size as transfer size - NF_SpiDriver_TransferBlocking( + NF_SpiDriver_MTransferB( palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, @@ -340,7 +340,7 @@ HRESULT CPU_SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; // } - NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); // receive operation // TODO @@ -349,7 +349,7 @@ HRESULT CPU_SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } } else @@ -364,7 +364,7 @@ HRESULT CPU_SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } else { @@ -375,7 +375,7 @@ HRESULT CPU_SPI_nWrite_nRead( // half duplex operation, set output enable // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; } - NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); } } @@ -413,7 +413,7 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // Uses the largest buffer size as transfer size - NF_SpiDriver_Transfer( + NF_SpiDriver_MTransfer( palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, @@ -433,7 +433,7 @@ HRESULT CPU_SPI_nWrite_nRead( } // receive operation will be started in the callback after the above completes - NF_SpiDriver_Transmit( + NF_SpiDriver_MTransmit( palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize, @@ -449,7 +449,7 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start receive - NF_SpiDriver_Receive( + NF_SpiDriver_MReceive( palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, @@ -461,7 +461,7 @@ HRESULT CPU_SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start send - NF_SpiDriver_Transmit( + NF_SpiDriver_MTransmit( palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize, diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp index f8820dbbb7..ac2baf115e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.cpp @@ -1,13 +1,12 @@ // // Copyright (c) .NET Foundation and Contributors // See LICENSE file in the project root for full license information. +// code adapted from platform\emdrv\spidrv\src\spidrv.c from Gecko SDK // -#include "nf_gecko_spi_driver.h" +// clang-format off -#if defined(EUSART_PRESENT) -#error "Only USART type is supported. Drivar can't driver EUSART." -#endif +#include "nf_gecko_spi_driver.h" #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" @@ -15,19 +14,27 @@ #include "em_device.h" #include "em_gpio.h" #include "em_core.h" +#if defined (USART_PRESENT) #include "em_usart.h" +#endif +#if defined(EUSART_PRESENT) +#include "em_eusart.h" +#endif #include "dmadrv.h" #include "nf_gecko_spi_driver.h" #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) #include "sl_power_manager.h" +#if defined(EUSART_PRESENT) +#include "sl_slist.h" +#endif #endif #include #if defined(DMA_PRESENT) && (DMA_COUNT == 1) -#define SPI_DMA_IRQ DMA_IRQn +#define SPI_DMA_IRQ DMA_IRQn #elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) -#define SPI_DMA_IRQ LDMA_IRQn +#define SPI_DMA_IRQ LDMA_IRQn #else #error "No valid SPIDRV DMA engine defined." @@ -36,1493 +43,2498 @@ #define EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET (3U) #define EMDRV_SPIDRV_EUSART_FRAMELENGTH_REGVALUE_OFFSET (6U) -// SPI Pins structure used when mapping from location to gpio port+pin. -typedef struct -{ - uint8_t mosiPort; - uint8_t mosiPin; - uint8_t misoPort; - uint8_t misoPin; - uint8_t clkPort; - uint8_t clkPin; - uint8_t csPort; - uint8_t csPin; +//**************************************************************************** + +/** + * @brief SPI Pins structure used when mapping from location to gpio port+pin. + */ +typedef struct { + uint8_t mosiPort; + uint8_t mosiPin; + uint8_t misoPort; + uint8_t misoPin; + uint8_t clkPort; + uint8_t clkPin; + uint8_t csPort; + uint8_t csPin; } SPI_Pins_t; -static bool spidrvIsInitialized = false; +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(EUSART_PRESENT) +static sl_power_manager_em_transition_event_handle_t on_power_manager_event_handle; + +static void on_power_manager_event(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +static sl_power_manager_em_transition_event_info_t on_power_manager_event_info = +{ + .event_mask = (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ + | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3), + .on_event = on_power_manager_event, +}; + +// List of EUSART handles +sl_slist_node_t *eusart_handle_list = NULL; +#endif + +static bool spidrvIsInitialized = false; +#if defined(USART_PRESENT) static Ecode_t NF_SpiDriver_InitUsart(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData); +#endif + +#if defined(EUSART_PRESENT) +static Ecode_t NF_SpiDriver_InitEusart(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData); +#endif -static void BlockingComplete(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred); +static void BlockingComplete(NF_SpiDriver_Handle_t handle, + Ecode_t transferStatus, + int itemsTransferred); -static Ecode_t ConfigGPIO(NF_SpiDriver_Handle_t handle, bool enable); +static Ecode_t ConfigGPIO(NF_SpiDriver_Handle_t handle, bool enable); -static bool RxDMAComplete(unsigned int channel, unsigned int sequenceNo, void *userParam); +static bool RxDMAComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam); -static void StartReceiveDMA(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback); +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) +static void SlaveTimeout(sl_sleeptimer_timer_handle_t *handle, void *data); +#endif -static void StartTransferDMA( - NF_SpiDriver_Handle_t handle, - const void *txBuffer, - void *rxBuffer, - int count, - NF_SpiDriver_Callback_t callback); +static void StartReceiveDMA(NF_SpiDriver_Handle_t handle, + void *buffer, + int count, + NF_SpiDriver_Callback_t callback); -static void StartTransmitDMA( - NF_SpiDriver_Handle_t handle, - const void *buffer, - int count, - NF_SpiDriver_Callback_t callback); +static void StartTransferDMA(NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + NF_SpiDriver_Callback_t callback); -static Ecode_t TransferApiPrologue(NF_SpiDriver_Handle_t handle, void *buffer, int count); +static void StartTransmitDMA(NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback); -static Ecode_t TransferApiBlockingPrologue(NF_SpiDriver_Handle_t handle, void *buffer, int count); +static Ecode_t TransferApiPrologue(NF_SpiDriver_Handle_t handle, + void *buffer, + int count); -static void WaitForTransferCompletion(NF_SpiDriver_Handle_t handle); +static Ecode_t TransferApiBlockingPrologue(NF_SpiDriver_Handle_t handle, + void *buffer, + int count); -// -// Power management functions. -// +static void WaitForTransferCompletion(NF_SpiDriver_Handle_t handle); + +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) +static Ecode_t WaitForIdleLine(NF_SpiDriver_Handle_t handle); +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(EUSART_PRESENT) +static Ecode_t sli_spidrv_exit_em23(NF_SpiDriver_Handle_t handle); +static Ecode_t sli_spidrv_enter_em23(NF_SpiDriver_Handle_t handle); +#endif + +/// @endcond + +/***************************************************************************//** + * @brief Power management functions. + ******************************************************************************/ static void em1RequestAdd(NF_SpiDriver_Handle_t handle) { #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (handle->em1RequestCount == 0) - { - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); - } - handle->em1RequestCount++; - CORE_EXIT_ATOMIC(); + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (handle->em1RequestCount == 0) { + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + } + handle->em1RequestCount++; + CORE_EXIT_ATOMIC(); #else - handle->em1RequestCount++; + handle->em1RequestCount++; #endif } static void em1RequestRemove(NF_SpiDriver_Handle_t handle) { - EFM_ASSERT(handle->em1RequestCount > 0); + EFM_ASSERT(handle->em1RequestCount > 0); #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - handle->em1RequestCount--; - if (handle->em1RequestCount == 0) - { - sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); - } - CORE_EXIT_ATOMIC(); + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + handle->em1RequestCount--; + if (handle->em1RequestCount == 0) { + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + } + CORE_EXIT_ATOMIC(); #else - handle->em1RequestCount--; + handle->em1RequestCount--; #endif } static void emRequestInit(NF_SpiDriver_Handle_t handle) { - handle->em1RequestCount = 0; + handle->em1RequestCount = 0; } static void emRequestDeinit(NF_SpiDriver_Handle_t handle) { - if (handle->em1RequestCount > 0) - { - handle->em1RequestCount = 1; - em1RequestRemove(handle); - } + if (handle->em1RequestCount > 0) { + handle->em1RequestCount = 1; + em1RequestRemove(handle); + } } -// -// -// Initialize an SPI driver instance. -// -// @param[out] handle Pointer to an SPI driver handle; refer to @ref -// NF_SpiDriver_Handle_t. -// @param[in] initData Pointer to an initialization data structure; -// refer to @ref NF_SpiDriver_Init. -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate -// SPIDRV @ref Ecode_t is returned. -// +/***************************************************************************//** + * @brief + * Initialize an SPI driver instance. + * + * @param[out] handle Pointer to an SPI driver handle; refer to @ref + * NF_SpiDriver_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure; + * refer to @ref NF_SpiDriver_Init. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ Ecode_t NF_SpiDriver_Init(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData) { - return NF_SpiDriver_InitUsart(handle, initData); +#if defined (EUSART_PRESENT) + Ecode_t result = ECODE_EMDRV_SPIDRV_PARAM_ERROR; + + if (EUSART_NUM((EUSART_TypeDef*)initData->port) != -1) { + result = NF_SpiDriver_InitEusart(handle, initData); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + // Subscribe to notification to re-enable eusart after deepsleep. + if (eusart_handle_list == NULL) { + sl_power_manager_subscribe_em_transition_event(&on_power_manager_event_handle, &on_power_manager_event_info); + } + sl_slist_push(&eusart_handle_list, &handle->node); +#endif + + return result; + } +#endif + +#if defined (USART_PRESENT) + return NF_SpiDriver_InitUsart(handle, initData); +#else + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; +#endif } -// -// -// Initialize an SPI driver usart instance. -// -// @param[out] handle Pointer to an SPI driver handle; refer to @ref -// NF_SpiDriver_Handle_t. -// -// @param[in] initData Pointer to an initialization data structure; -// refer to @ref NF_SpiDriver_Init. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate -// SPIDRV @ref Ecode_t is returned. -// +#if defined (USART_PRESENT) +/***************************************************************************//** + * @brief + * Initialize an SPI driver usart instance. + * + * @param[out] handle Pointer to an SPI driver handle; refer to @ref + * NF_SpiDriver_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure; + * refer to @ref NF_SpiDriver_Init. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ static Ecode_t NF_SpiDriver_InitUsart(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData) { - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - USART_InitSync_TypeDef usartInit = USART_INITSYNC_DEFAULT; + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + USART_InitSync_TypeDef usartInit = USART_INITSYNC_DEFAULT; #if defined(_SILICON_LABS_32B_SERIES_2) - int8_t spiPortNum = -1; + int8_t spiPortNum = -1; #endif - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - if (initData == NULL) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if (initData == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - memset(handle, 0, sizeof(NF_SpiDriver_HandleData_t)); - emRequestInit(handle); + memset(handle, 0, sizeof(NF_SpiDriver_HandleData_t)); + emRequestInit(handle); - if (0) - { + if (0) { #if defined(USART0) - } - else if ((USART_TypeDef *)initData->port == USART0) - { - handle->usartClock = cmuClock_USART0; - handle->txDMASignal = dmadrvPeripheralSignal_USART0_TXBL; -#if defined(_SILICON_LABS_32B_SERIES_2) - handle->rxDMASignal = dmadrvPeripheralSignal_USART0_RXDATAV; - spiPortNum = 0; -#else - handle->rxDMASignal = dmadrvPeripheralSignal_USART0_RXDATAV; -#endif + } else if ((USART_TypeDef*)initData->port == USART0) { + handle->usartClock = cmuClock_USART0; + handle->txDMASignal = dmadrvPeripheralSignal_USART0_TXBL; + #if defined(_SILICON_LABS_32B_SERIES_2) + handle->rxDMASignal = dmadrvPeripheralSignal_USART0_RXDATAV; + spiPortNum = 0; + #else + handle->rxDMASignal = dmadrvPeripheralSignal_USART0_RXDATAV; + #endif #endif #if defined(USART1) - } - else if ((USART_TypeDef *)initData->port == USART1) - { - handle->usartClock = cmuClock_USART1; - handle->txDMASignal = dmadrvPeripheralSignal_USART1_TXBL; -#if defined(_SILICON_LABS_32B_SERIES_2) - handle->rxDMASignal = dmadrvPeripheralSignal_USART1_RXDATAV; - spiPortNum = 1; -#else - handle->rxDMASignal = dmadrvPeripheralSignal_USART1_RXDATAV; -#endif + } else if ((USART_TypeDef*)initData->port == USART1) { + handle->usartClock = cmuClock_USART1; + handle->txDMASignal = dmadrvPeripheralSignal_USART1_TXBL; + #if defined(_SILICON_LABS_32B_SERIES_2) + handle->rxDMASignal = dmadrvPeripheralSignal_USART1_RXDATAV; + spiPortNum = 1; + #else + handle->rxDMASignal = dmadrvPeripheralSignal_USART1_RXDATAV; + #endif #endif #if defined(USART2) - } - else if ((USART_TypeDef *)initData->port == USART2) - { - handle->usartClock = cmuClock_USART2; - handle->txDMASignal = dmadrvPeripheralSignal_USART2_TXBL; -#if defined(_SILICON_LABS_32B_SERIES_2) - handle->rxDMASignal = dmadrvPeripheralSignal_USART2_RXDATAV; - spiPortNum = 2; -#else - handle->rxDMASignal = dmadrvPeripheralSignal_USART2_RXDATAV; -#endif + } else if ((USART_TypeDef*)initData->port == USART2) { + handle->usartClock = cmuClock_USART2; + handle->txDMASignal = dmadrvPeripheralSignal_USART2_TXBL; + #if defined(_SILICON_LABS_32B_SERIES_2) + handle->rxDMASignal = dmadrvPeripheralSignal_USART2_RXDATAV; + spiPortNum = 2; + #else + handle->rxDMASignal = dmadrvPeripheralSignal_USART2_RXDATAV; + #endif #endif #if defined(USART3) - } - else if ((USART_TypeDef *)initData->port == USART3) - { - handle->usartClock = cmuClock_USART3; - handle->txDMASignal = dmadrvPeripheralSignal_USART3_TXBL; - handle->rxDMASignal = dmadrvPeripheralSignal_USART3_RXDATAV; -#if defined(_SILICON_LABS_32B_SERIES_2) - spiPortNum = 3; -#endif + } else if ((USART_TypeDef*)initData->port == USART3) { + handle->usartClock = cmuClock_USART3; + handle->txDMASignal = dmadrvPeripheralSignal_USART3_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USART3_RXDATAV; + #if defined(_SILICON_LABS_32B_SERIES_2) + spiPortNum = 3; + #endif #endif #if defined(USART4) - } - else if ((USART_TypeDef *)initData->port == USART4) - { - handle->usartClock = cmuClock_USART4; - handle->txDMASignal = dmadrvPeripheralSignal_USART4_TXBL; - handle->rxDMASignal = dmadrvPeripheralSignal_USART4_RXDATAV; -#if defined(_SILICON_LABS_32B_SERIES_2) - spiPortNum = 4; -#endif + } else if ((USART_TypeDef*)initData->port == USART4) { + handle->usartClock = cmuClock_USART4; + handle->txDMASignal = dmadrvPeripheralSignal_USART4_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USART4_RXDATAV; + #if defined(_SILICON_LABS_32B_SERIES_2) + spiPortNum = 4; + #endif #endif #if defined(USART5) - } - else if ((USART_TypeDef *)initData->port == USART5) - { - handle->usartClock = cmuClock_USART5; - handle->txDMASignal = dmadrvPeripheralSignal_USART5_TXBL; - handle->rxDMASignal = dmadrvPeripheralSignal_USART5_RXDATAV; -#if defined(_SILICON_LABS_32B_SERIES_2) - spiPortNum = 5; -#endif + } else if ((USART_TypeDef*)initData->port == USART5) { + handle->usartClock = cmuClock_USART5; + handle->txDMASignal = dmadrvPeripheralSignal_USART5_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USART5_RXDATAV; + #if defined(_SILICON_LABS_32B_SERIES_2) + spiPortNum = 5; + #endif #endif #if defined(USARTRF0) - } - else if ((USART_TypeDef *)initData->port == USARTRF0) - { - handle->usartClock = cmuClock_USARTRF0; - handle->txDMASignal = dmadrvPeripheralSignal_USARTRF0_TXBL; - handle->rxDMASignal = dmadrvPeripheralSignal_USARTRF0_RXDATAV; + } else if ((USART_TypeDef*)initData->port == USARTRF0) { + handle->usartClock = cmuClock_USARTRF0; + handle->txDMASignal = dmadrvPeripheralSignal_USARTRF0_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USARTRF0_RXDATAV; #endif #if defined(USARTRF1) - } - else if ((USART_TypeDef *)initData->port == USARTRF1) - { - handle->usartClock = cmuClock_USARTRF1; - handle->txDMASignal = dmadrvPeripheralSignal_USARTRF1_TXBL; - handle->rxDMASignal = dmadrvPeripheralSignal_USARTRF1_RXDATAV; + } else if ((USART_TypeDef*)initData->port == USARTRF1) { + handle->usartClock = cmuClock_USARTRF1; + handle->txDMASignal = dmadrvPeripheralSignal_USARTRF1_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_USARTRF1_RXDATAV; #endif - } - else - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } - - handle->peripheral.usartPort = (USART_TypeDef *)initData->port; - handle->peripheralType = spidrvPeripheralTypeUsart; - handle->initData = initData; - - if (initData->bitOrder == spidrvBitOrderMsbFirst) - { - usartInit.msbf = true; - } - - if (initData->clockMode == spidrvClockMode0) - { - usartInit.clockMode = usartClockMode0; - } - else if (initData->clockMode == spidrvClockMode1) - { - usartInit.clockMode = usartClockMode1; - } - else if (initData->clockMode == spidrvClockMode2) - { - usartInit.clockMode = usartClockMode2; - } - else if (initData->clockMode == spidrvClockMode3) - { - usartInit.clockMode = usartClockMode3; - } - else - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } - - usartInit.master = true; + } else { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + handle->peripheral.usartPort = (USART_TypeDef *)initData->port; + handle->peripheralType = spidrvPeripheralTypeUsart; + handle->initData = initData; + + if (initData->bitOrder == spidrvBitOrderMsbFirst) { + usartInit.msbf = true; + } + + if (initData->clockMode == spidrvClockMode0) { + usartInit.clockMode = usartClockMode0; + } else if (initData->clockMode == spidrvClockMode1) { + usartInit.clockMode = usartClockMode1; + } else if (initData->clockMode == spidrvClockMode2) { + usartInit.clockMode = usartClockMode2; + } else if (initData->clockMode == spidrvClockMode3) { + usartInit.clockMode = usartClockMode3; + } else { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + if (initData->type == spidrvSlave) { + usartInit.master = false; + usartInit.baudrate = 115200; // Dummy value needed by USART_InitSync() + } else { usartInit.baudrate = initData->bitRate; + } #if defined(_CMU_HFPERCLKEN0_MASK) - CMU_ClockEnable(cmuClock_HFPER, true); + CMU_ClockEnable(cmuClock_HFPER, true); #endif - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(handle->usartClock, true); - - if ((initData->frameLength < 4U) || (initData->frameLength > 16U)) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } - uint32_t databits = initData->frameLength - 4U + _USART_FRAME_DATABITS_FOUR; - usartInit.databits = (USART_Databits_TypeDef)databits; + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->usartClock, true); - USART_InitSync((USART_TypeDef *)initData->port, &usartInit); + if ((initData->frameLength < 4U) || (initData->frameLength > 16U)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + uint32_t databits = initData->frameLength - 4U + _USART_FRAME_DATABITS_FOUR; + usartInit.databits = (USART_Databits_TypeDef)databits; - if (initData->csControl == spidrvCsControlAuto) - { - handle->peripheral.usartPort->CTRL |= USART_CTRL_AUTOCS; - } + USART_InitSync((USART_TypeDef *)initData->port, &usartInit); - if (initData->isHalfDuplex) - { - handle->peripheral.usartPort->CTRL |= USART_CTRL_LOOPBK; - } + if ((initData->type == spidrvMaster) + && (initData->csControl == spidrvCsControlAuto)) { + handle->peripheral.usartPort->CTRL |= USART_CTRL_AUTOCS; + } - if (initData->csControl == spidrvCsControlAuto) - { + if (initData->csControl == spidrvCsControlAuto) { + // SPI 4 wire mode #if defined(USART_ROUTEPEN_TXPEN) - handle->peripheral.usartPort->ROUTELOC0 = - (handle->peripheral.usartPort->ROUTELOC0 & ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | - _USART_ROUTELOC0_CLKLOC_MASK | _USART_ROUTELOC0_CSLOC_MASK)) | - (initData->portLocationTx << _USART_ROUTELOC0_TXLOC_SHIFT) | - (initData->portLocationRx << _USART_ROUTELOC0_RXLOC_SHIFT) | - (initData->portLocationClk << _USART_ROUTELOC0_CLKLOC_SHIFT) | - (initData->portLocationCs << _USART_ROUTELOC0_CSLOC_SHIFT); - - handle->peripheral.usartPort->ROUTEPEN = - USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_CLKPEN | USART_ROUTEPEN_CSPEN; -#elif defined(_GPIO_USART_ROUTEEN_MASK) - GPIO->USARTROUTE[spiPortNum].ROUTEEN = - GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN | GPIO_USART_ROUTEEN_CLKPEN | GPIO_USART_ROUTEEN_CSPEN; - - GPIO->USARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx << _GPIO_USART_TXROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinTx << _GPIO_USART_TXROUTE_PIN_SHIFT); - - GPIO->USARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx << _GPIO_USART_RXROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinRx << _GPIO_USART_RXROUTE_PIN_SHIFT); - - GPIO->USARTROUTE[spiPortNum].CLKROUTE = ((uint32_t)initData->portClk << _GPIO_USART_CLKROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinClk << _GPIO_USART_CLKROUTE_PIN_SHIFT); - - GPIO->USARTROUTE[spiPortNum].CSROUTE = ((uint32_t)initData->portCs << _GPIO_USART_CSROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinCs << _GPIO_USART_CSROUTE_PIN_SHIFT); + handle->peripheral.usartPort->ROUTELOC0 = (handle->peripheral.usartPort->ROUTELOC0 + & ~(_USART_ROUTELOC0_TXLOC_MASK + | _USART_ROUTELOC0_RXLOC_MASK + | _USART_ROUTELOC0_CLKLOC_MASK + | _USART_ROUTELOC0_CSLOC_MASK)) + | (initData->portLocationTx << _USART_ROUTELOC0_TXLOC_SHIFT) + | (initData->portLocationRx << _USART_ROUTELOC0_RXLOC_SHIFT) + | (initData->portLocationClk << _USART_ROUTELOC0_CLKLOC_SHIFT) + | (initData->portLocationCs << _USART_ROUTELOC0_CSLOC_SHIFT); + + handle->peripheral.usartPort->ROUTEPEN = USART_ROUTEPEN_TXPEN + | USART_ROUTEPEN_RXPEN + | USART_ROUTEPEN_CLKPEN + | USART_ROUTEPEN_CSPEN; +#elif defined (_GPIO_USART_ROUTEEN_MASK) + GPIO->USARTROUTE[spiPortNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN + | GPIO_USART_ROUTEEN_RXPEN + | GPIO_USART_ROUTEEN_CLKPEN + | GPIO_USART_ROUTEEN_CSPEN; + + GPIO->USARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx + << _GPIO_USART_TXROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinTx + << _GPIO_USART_TXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx + << _GPIO_USART_RXROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinRx + << _GPIO_USART_RXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].CLKROUTE = ((uint32_t)initData->portClk + << _GPIO_USART_CLKROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinClk + << _GPIO_USART_CLKROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].CSROUTE = ((uint32_t)initData->portCs + << _GPIO_USART_CSROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinCs + << _GPIO_USART_CSROUTE_PIN_SHIFT); #else - handle->peripheral.usartPort->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | - USART_ROUTE_CSPEN | - (initData->portLocation << _USART_ROUTE_LOCATION_SHIFT); + handle->peripheral.usartPort->ROUTE = USART_ROUTE_TXPEN + | USART_ROUTE_RXPEN + | USART_ROUTE_CLKPEN + | USART_ROUTE_CSPEN + | (initData->portLocation + << _USART_ROUTE_LOCATION_SHIFT); #endif - } - else - { + } else { + // SPI 3 wire mode #if defined(USART_ROUTEPEN_TXPEN) - handle->peripheral.usartPort->ROUTELOC0 = - (handle->peripheral.usartPort->ROUTELOC0 & - ~(_USART_ROUTELOC0_TXLOC_MASK | _USART_ROUTELOC0_RXLOC_MASK | _USART_ROUTELOC0_CLKLOC_MASK)) | - (initData->portLocationTx << _USART_ROUTELOC0_TXLOC_SHIFT) | - (initData->portLocationRx << _USART_ROUTELOC0_RXLOC_SHIFT) | - (initData->portLocationClk << _USART_ROUTELOC0_CLKLOC_SHIFT); - - handle->peripheral.usartPort->ROUTEPEN = USART_ROUTEPEN_TXPEN | USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_CLKPEN; -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE[spiPortNum].ROUTEEN = - GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN | GPIO_USART_ROUTEEN_CLKPEN; + handle->peripheral.usartPort->ROUTELOC0 = (handle->peripheral.usartPort->ROUTELOC0 + & ~(_USART_ROUTELOC0_TXLOC_MASK + | _USART_ROUTELOC0_RXLOC_MASK + | _USART_ROUTELOC0_CLKLOC_MASK)) + | (initData->portLocationTx << _USART_ROUTELOC0_TXLOC_SHIFT) + | (initData->portLocationRx << _USART_ROUTELOC0_RXLOC_SHIFT) + | (initData->portLocationClk << _USART_ROUTELOC0_CLKLOC_SHIFT); + + handle->peripheral.usartPort->ROUTEPEN = USART_ROUTEPEN_TXPEN + | USART_ROUTEPEN_RXPEN + | USART_ROUTEPEN_CLKPEN; +#elif defined (GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE[spiPortNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN + | GPIO_USART_ROUTEEN_RXPEN + | GPIO_USART_ROUTEEN_CLKPEN; + + GPIO->USARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx + << _GPIO_USART_TXROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinTx + << _GPIO_USART_TXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx + << _GPIO_USART_RXROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinRx + << _GPIO_USART_RXROUTE_PIN_SHIFT); + + GPIO->USARTROUTE[spiPortNum].CLKROUTE = ((uint32_t)initData->portClk + << _GPIO_USART_CLKROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinClk + << _GPIO_USART_CLKROUTE_PIN_SHIFT); +#else + handle->peripheral.usartPort->ROUTE = USART_ROUTE_TXPEN + | USART_ROUTE_RXPEN + | USART_ROUTE_CLKPEN + | (initData->portLocation + << _USART_ROUTE_LOCATION_SHIFT); +#endif + } - GPIO->USARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx << _GPIO_USART_TXROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinTx << _GPIO_USART_TXROUTE_PIN_SHIFT); + if ((retVal = ConfigGPIO(handle, true)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } - GPIO->USARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx << _GPIO_USART_RXROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinRx << _GPIO_USART_RXROUTE_PIN_SHIFT); + CORE_ENTER_ATOMIC(); + if (!spidrvIsInitialized) { + spidrvIsInitialized = true; + CORE_EXIT_ATOMIC(); - GPIO->USARTROUTE[spiPortNum].CLKROUTE = ((uint32_t)initData->portClk << _GPIO_USART_CLKROUTE_PORT_SHIFT) | - ((uint32_t)initData->pinClk << _GPIO_USART_CLKROUTE_PIN_SHIFT); -#else - handle->peripheral.usartPort->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | - (initData->portLocation << _USART_ROUTE_LOCATION_SHIFT); +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) + sl_sleeptimer_init(); #endif - } + } else { + CORE_EXIT_ATOMIC(); + } - if ((retVal = ConfigGPIO(handle, true)) != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + // Initialize DMA. + DMADRV_Init(); - CORE_ENTER_ATOMIC(); - if (!spidrvIsInitialized) - { - spidrvIsInitialized = true; - CORE_EXIT_ATOMIC(); - } - else - { - CORE_EXIT_ATOMIC(); - } + if (DMADRV_AllocateChannel(&handle->txDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; + } - // Initialize DMA. - DMADRV_Init(); + if (DMADRV_AllocateChannel(&handle->rxDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; + } - if (DMADRV_AllocateChannel(&handle->txDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) - { - return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; - } + return ECODE_EMDRV_SPIDRV_OK; +} +#endif // defined USART_PRESENT - if (DMADRV_AllocateChannel(&handle->rxDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) - { - return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; - } +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * @brief + * Initialize an SPI driver eusart instance. + * + * @param[out] handle Pointer to an SPI driver handle; refer to @ref + * NF_SpiDriver_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure; + * refer to @ref NF_SpiDriver_Init. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ +static Ecode_t NF_SpiDriver_InitEusart(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + EUSART_SpiAdvancedInit_TypeDef eusartAdvancedSpiInit = EUSART_SPI_ADVANCED_INIT_DEFAULT; + EUSART_SpiInit_TypeDef eusartSpiInit = EUSART_SPI_MASTER_INIT_DEFAULT_HF; + int8_t spiPortNum = -1; + + eusartSpiInit.advancedSettings = &eusartAdvancedSpiInit; + + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if (initData == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(NF_SpiDriver_HandleData_t)); + emRequestInit(handle); + + if (0) { +#if defined(EUSART0) + } else if (initData->port == EUSART0) { + handle->usartClock = cmuClock_EUSART0; + handle->txDMASignal = dmadrvPeripheralSignal_EUSART0_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_EUSART0_RXDATAV; + spiPortNum = 0; +#endif +#if defined(EUSART1) + } else if (initData->port == EUSART1) { + handle->usartClock = cmuClock_EUSART1; + handle->txDMASignal = dmadrvPeripheralSignal_EUSART1_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_EUSART1_RXDATAV; + spiPortNum = 1; +#endif +#if defined(EUSART2) + } else if (initData->port == EUSART2) { + handle->usartClock = cmuClock_EUSART2; + handle->txDMASignal = dmadrvPeripheralSignal_EUSART2_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_EUSART2_RXDATAV; + spiPortNum = 2; +#endif +#if defined(EUSART3) + } else if (initData->port == EUSART3) { + handle->usartClock = cmuClock_EUSART3; + handle->txDMASignal = dmadrvPeripheralSignal_EUSART3_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_EUSART3_RXDATAV; + spiPortNum = 3; +#endif +#if defined(EUSART4) + } else if (initData->port == EUSART4) { + handle->usartClock = cmuClock_EUSART4; + handle->txDMASignal = dmadrvPeripheralSignal_EUSART4_TXBL; + handle->rxDMASignal = dmadrvPeripheralSignal_EUSART4_RXDATAV; + spiPortNum = 4; +#endif + } else { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + handle->peripheral.eusartPort = initData->port; + handle->peripheralType = spidrvPeripheralTypeEusart; + handle->initData = *initData; + + if (initData->bitOrder == spidrvBitOrderMsbFirst) { + eusartAdvancedSpiInit.msbFirst = true; + } + + if (initData->clockMode == spidrvClockMode0) { + eusartSpiInit.clockMode = eusartClockMode0; + } else if (initData->clockMode == spidrvClockMode1) { + eusartSpiInit.clockMode = eusartClockMode1; + } else if (initData->clockMode == spidrvClockMode2) { + eusartSpiInit.clockMode = eusartClockMode2; + } else if (initData->clockMode == spidrvClockMode3) { + eusartSpiInit.clockMode = eusartClockMode3; + } else { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + if (initData->type == spidrvSlave) { + if (initData->bitRate >= 5000000) { + // If baud-rate is more than 5MHz, a value of 4 is required + eusartSpiInit.advancedSettings->setupWindow = 4; + } else { + // If baud-rate is less than 5MHz, a value of 5 is required + eusartSpiInit.advancedSettings->setupWindow = 5; + } + eusartSpiInit.master = false; + eusartSpiInit.bitRate = 1000000; + } else { + eusartAdvancedSpiInit.forceLoad = false; + eusartSpiInit.bitRate = initData->bitRate; + } + // Leave eusartAdvancedSpiInit.defaultTxData = 0, not initData->dummyTxValue + // for EUSART compatibility with USART behavior. + + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->usartClock, true); + + if ((initData->frameLength < 7U) || (initData->frameLength > 16U)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + uint32_t databits = initData->frameLength - 7U + EUSART_FRAMECFG_DATABITS_SEVEN; + eusartSpiInit.databits = (EUSART_Databits_TypeDef)databits; + + if (initData->type == spidrvMaster) { + // Don't assume EUSART_SPI_ADVANCED_INIT_DEFAULT has desired autoCsEnable + eusartAdvancedSpiInit.autoCsEnable = (initData->csControl == spidrvCsControlAuto); + } + + if ((retVal = ConfigGPIO(handle, true)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + GPIO->EUSARTROUTE[spiPortNum].TXROUTE = ((uint32_t)initData->portTx + << _GPIO_EUSART_TXROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinTx + << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[spiPortNum].RXROUTE = ((uint32_t)initData->portRx + << _GPIO_EUSART_RXROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinRx + << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[spiPortNum].SCLKROUTE = ((uint32_t)initData->portClk + << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinClk + << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT); + + if (initData->csControl == spidrvCsControlAuto) { + // SPI 4 wire mode, Chip Select controled by the peripheral + GPIO->EUSARTROUTE[spiPortNum].CSROUTE = ((uint32_t)initData->portCs + << _GPIO_EUSART_CSROUTE_PORT_SHIFT) + | ((uint32_t)initData->pinCs + << _GPIO_EUSART_CSROUTE_PIN_SHIFT); + } + + // SPI 4 wire mode + if (initData->csControl == spidrvCsControlAuto) { + GPIO->EUSARTROUTE[spiPortNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN + | GPIO_EUSART_ROUTEEN_RXPEN + | GPIO_EUSART_ROUTEEN_SCLKPEN + | GPIO_EUSART_ROUTEEN_CSPEN; + } else { + GPIO->EUSARTROUTE[spiPortNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN + | GPIO_EUSART_ROUTEEN_RXPEN + | GPIO_EUSART_ROUTEEN_SCLKPEN; + } + + EUSART_SpiInit(initData->port, &eusartSpiInit); + + CORE_ENTER_ATOMIC(); + if (!spidrvIsInitialized) { + spidrvIsInitialized = true; + CORE_EXIT_ATOMIC(); + +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) + sl_sleeptimer_init(); +#endif + } else { + CORE_EXIT_ATOMIC(); + } + + // Initialize DMA. + DMADRV_Init(); + + if (DMADRV_AllocateChannel(&handle->txDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; + } - return ECODE_EMDRV_SPIDRV_OK; + if (DMADRV_AllocateChannel(&handle->rxDMACh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_SPIDRV_DMA_ALLOC_ERROR; + } + + return ECODE_EMDRV_SPIDRV_OK; } +#endif -// -// -// Deinitialize an SPI driver instance. -// -// This function should only be called with an initialized spidrv instance handle. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate -// SPIDRV @ref Ecode_t is returned. -// +/***************************************************************************//** + * @brief + * Deinitialize an SPI driver instance. + * + * @warning + * This function should only be called with an initialized spidrv instance handle. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ Ecode_t NF_SpiDriver_DeInit(NF_SpiDriver_Handle_t handle) { - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; +#if defined(USART_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) + int8_t USART_spiPortNum = -1; +#endif +#endif + +#if defined(EUSART_PRESENT) + int8_t EUSART_spiPortNum = -1; +#endif + + if (0) { + } +#if defined(USART_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { +#if (USART_COUNT == 1) && !defined(USART_NUM) + USART_spiPortNum = 0; +#else + USART_spiPortNum = USART_NUM((USART_TypeDef*)handle->peripheral.usartPort); +#endif + if (USART_spiPortNum == -1) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + } +#endif +#endif +#if defined (EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { +#if (EUSART_COUNT == 1) && !defined(EUSART_NUM) + EUSART_spiPortNum = 0; +#else + EUSART_spiPortNum = EUSART_NUM((EUSART_TypeDef*)handle->peripheral.eusartPort); +#endif + if (EUSART_spiPortNum == -1) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; } + } +#endif - // Stop DMAs. - DMADRV_StopTransfer(handle->rxDMACh); - DMADRV_StopTransfer(handle->txDMACh); + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - ConfigGPIO(handle, false); + // Stop DMAs. + DMADRV_StopTransfer(handle->rxDMACh); + DMADRV_StopTransfer(handle->txDMACh); - if (0) - { - } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - USART_Reset(handle->peripheral.usartPort); + ConfigGPIO(handle, false); + +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) + if (handle->initData->type == spidrvSlave) { + sl_sleeptimer_stop_timer(&handle->timer); + } +#endif + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + USART_Reset(handle->peripheral.usartPort); + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + EUSART_Reset(handle->peripheral.eusartPort); + } +#endif + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.usartPort->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; + handle->peripheral.usartPort->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE[USART_spiPortNum].ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE; + GPIO->USARTROUTE[USART_spiPortNum].TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE; + GPIO->USARTROUTE[USART_spiPortNum].RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE; + GPIO->USARTROUTE[USART_spiPortNum].CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE; + if (handle->initData->csControl == spidrvCsControlAuto) { + // SPI 4 wire mode + GPIO->USARTROUTE[USART_spiPortNum].CSROUTE = _GPIO_USART_CSROUTE_RESETVALUE; } +#else + handle->peripheral.usartPort->ROUTE = _USART_ROUTE_RESETVALUE; +#endif + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + GPIO->EUSARTROUTE[EUSART_spiPortNum].TXROUTE = _GPIO_EUSART_TXROUTE_RESETVALUE; + GPIO->EUSARTROUTE[EUSART_spiPortNum].RXROUTE = _GPIO_EUSART_RXROUTE_RESETVALUE; + GPIO->EUSARTROUTE[EUSART_spiPortNum].SCLKROUTE = _GPIO_EUSART_SCLKROUTE_RESETVALUE; + if (handle->initData->csControl == spidrvCsControlAuto) { + // SPI 4 wire mode, Chip Select controled by the peripheral + GPIO->EUSARTROUTE[EUSART_spiPortNum].CSROUTE = _GPIO_EUSART_CSROUTE_RESETVALUE; + } + GPIO->EUSARTROUTE[EUSART_spiPortNum].ROUTEEN = _GPIO_EUSART_ROUTEEN_RESETVALUE; + } +#endif + + CMU_ClockEnable(handle->usartClock, false); - CMU_ClockEnable(handle->usartClock, false); + DMADRV_FreeChannel(handle->txDMACh); + DMADRV_FreeChannel(handle->rxDMACh); + DMADRV_DeInit(); + emRequestDeinit(handle); - DMADRV_FreeChannel(handle->txDMACh); - DMADRV_FreeChannel(handle->rxDMACh); - DMADRV_DeInit(); - emRequestDeinit(handle); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(EUSART_PRESENT) + // Unsubscribe to notification to re-enable eusart after deepsleep. + sl_slist_remove(&eusart_handle_list, &handle->node); + if (eusart_handle_list == NULL) { + sl_power_manager_unsubscribe_em_transition_event(&on_power_manager_event_handle); + } +#endif - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Abort an ongoing SPI transfer. -// @param[in] handle Pointer to an SPI driver handle. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_IDLE if -// SPI is idle. On failure, an appropriate SPIDRV @ref Ecode_t is returned. -// +/***************************************************************************//** + * @brief + * Abort an ongoing SPI transfer. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_IDLE if + * SPI is idle. On failure, an appropriate SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ Ecode_t NF_SpiDriver_AbortTransfer(NF_SpiDriver_Handle_t handle) { - CORE_DECLARE_IRQ_STATE; + CORE_DECLARE_IRQ_STATE; - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - CORE_ENTER_ATOMIC(); - if (handle->state == spidrvStateIdle) - { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_IDLE; - } + CORE_ENTER_ATOMIC(); + if (handle->state == spidrvStateIdle) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_IDLE; + } - // Stop DMA's. - DMADRV_StopTransfer(handle->rxDMACh); - DMADRV_StopTransfer(handle->txDMACh); - DMADRV_TransferRemainingCount(handle->rxDMACh, &handle->remaining); - handle->transferStatus = ECODE_EMDRV_SPIDRV_ABORTED; - handle->state = spidrvStateIdle; - handle->transferStatus = ECODE_EMDRV_SPIDRV_ABORTED; - handle->blockingCompleted = true; - // signal RTOS event - tx_event_flags_set(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR); +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) + if (handle->initData->type == spidrvSlave) { + sl_sleeptimer_stop_timer(&handle->timer); + } +#endif - em1RequestRemove(handle); + // Stop DMA's. + DMADRV_StopTransfer(handle->rxDMACh); + DMADRV_StopTransfer(handle->txDMACh); + DMADRV_TransferRemainingCount(handle->rxDMACh, &handle->remaining); + handle->transferStatus = ECODE_EMDRV_SPIDRV_ABORTED; + handle->state = spidrvStateIdle; + handle->transferStatus = ECODE_EMDRV_SPIDRV_ABORTED; + handle->blockingCompleted = true; + + // signal RTOS event + tx_event_flags_set(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR); + + em1RequestRemove(handle); + + if (handle->userCallback != NULL) { + handle->userCallback(handle, + ECODE_EMDRV_SPIDRV_ABORTED, + handle->transferCount - handle->remaining); + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_SPIDRV_OK; +} - if (handle->userCallback != NULL) - { - handle->userCallback(handle, ECODE_EMDRV_SPIDRV_ABORTED, handle->transferCount - handle->remaining); - } - CORE_EXIT_ATOMIC(); +/***************************************************************************//** + * @brief + * Get current SPI bus bitrate. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] bitRate Current SPI bus bitrate. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_GetBitrate(NF_SpiDriver_Handle_t handle, uint32_t *bitRate) +{ + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if (bitRate == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + *bitRate = USART_BaudrateGet(handle->peripheral.usartPort); + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + *bitRate = EUSART_BaudrateGet(handle->peripheral.eusartPort); + } +#endif - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Get current SPI bus bitrate. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[out] bitRate Current SPI bus bitrate. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_GetBitrate(NF_SpiDriver_Handle_t handle, uint32_t *bitRate) +/***************************************************************************//** + * @brief + * Get current SPI framelength. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] frameLength Current SPI bus framelength. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_GetFramelength(NF_SpiDriver_Handle_t handle, uint32_t *frameLength) { - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - if (bitRate == NULL) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if (frameLength == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - if (0) - { - } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - *bitRate = USART_BaudrateGet(handle->peripheral.usartPort); - } + *frameLength = handle->initData->frameLength; - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Get current SPI framelength. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[out] frameLength Current SPI bus framelength. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_GetFramelength(NF_SpiDriver_Handle_t handle, uint32_t *frameLength) +/***************************************************************************//** + * @brief + * Get the status of an SPI transfer. + * + * @details + * Returns status of an ongoing transfer. If no transfer is in progress, + * the status of the last transfer is reported. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] itemsTransferred Number of items (frames) transferred. + * + * @param[out] itemsRemaining Number of items (frames) remaining. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_GetTransferStatus(NF_SpiDriver_Handle_t handle, + int *itemsTransferred, + int *itemsRemaining) { - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + int remaining; - if (frameLength == NULL) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } + + if ((itemsTransferred == NULL) || (itemsRemaining == NULL)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - *frameLength = handle->initData->frameLength; + CORE_ATOMIC_SECTION( + if (handle->state == spidrvStateIdle) { + remaining = handle->remaining; + } else { + DMADRV_TransferRemainingCount(handle->rxDMACh, &remaining); + } + ) - return ECODE_EMDRV_SPIDRV_OK; + * itemsTransferred = (handle->transferCount - remaining); + *itemsRemaining = remaining; + + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Get the status of an SPI transfer. -// -// @details -// Returns status of an ongoing transfer. If no transfer is in progress, -// the status of the last transfer is reported. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[out] itemsTransferred Number of items (frames) transferred. -// -// @param[out] itemsRemaining Number of items (frames) remaining. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_GetTransferStatus(NF_SpiDriver_Handle_t handle, int *itemsTransferred, int *itemsRemaining) +/***************************************************************************//** + * @brief + * Start an SPI master receive transfer. + * + * @note + * The MOSI wire will transmit @ref NF_SpiDriver_Init.dummyTxValue. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] buffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] callback Transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MReceive(NF_SpiDriver_Handle_t handle, + void *buffer, + int count, + NF_SpiDriver_Callback_t callback) { - int remaining; - - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + Ecode_t retVal; - if ((itemsTransferred == NULL) || (itemsRemaining == NULL)) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - CORE_ATOMIC_SECTION( - if (handle->state == spidrvStateIdle) { remaining = handle->remaining; } else { - DMADRV_TransferRemainingCount(handle->rxDMACh, &remaining); - }) + if ((retVal = TransferApiPrologue(handle, buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } - // itemsTransferred = (handle->transferCount - remaining); - *itemsRemaining = remaining; + StartReceiveDMA(handle, buffer, count, callback); - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Start an SPI master receive transfer. -// -// @note -// The MOSI wire will transmit @ref SPIDRV_Init.dummyTxValue. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[out] buffer Receive data buffer. -// -// @param[in] count Number of bytes in transfer. -// -// @param[in] callback Transfer completion callback. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_Receive(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback) +/***************************************************************************//** + * @brief + * Start an SPI master blocking receive transfer. + * + * @note + * The MOSI wire will transmit @ref NF_SpiDriver_Init.dummyTxValue. + * @n This function is blocking and returns when the transfer is complete + * or when @ref NF_SpiDriver_AbortTransfer() is called. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] buffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED + * if @ref NF_SpiDriver_AbortTransfer() has been called. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MReceiveB(NF_SpiDriver_Handle_t handle, + void *buffer, + int count) { - Ecode_t retVal; + Ecode_t retVal; - if ((retVal = TransferApiPrologue(handle, buffer, count)) != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } + + if ((retVal = TransferApiBlockingPrologue(handle, buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + StartReceiveDMA(handle, buffer, count, BlockingComplete); - StartReceiveDMA(handle, buffer, count, callback); + WaitForTransferCompletion(handle); - return ECODE_EMDRV_SPIDRV_OK; + return handle->transferStatus; } -// -// -// Start an SPI master blocking receive transfer. -// -// @note -// The MOSI wire will transmit @ref SPIDRV_Init.dummyTxValue. -// @n This function is blocking and returns when the transfer is complete -// or when @ref SPIDRV_AbortTransfer() is called. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[out] buffer Receive data buffer. -// -// @param[in] count Number of bytes in transfer. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED -// if @ref SPIDRV_AbortTransfer() has been called. On failure, an appropriate -// SPIDRV @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_ReceiveBlocking(NF_SpiDriver_Handle_t handle, void *buffer, int count) +/***************************************************************************//** + * @brief + * Start an SPI master transfer. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] txBuffer Transmit data buffer. + * + * @param[out] rxBuffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] callback Transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MTransfer(NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + NF_SpiDriver_Callback_t callback) { - Ecode_t retVal; + Ecode_t retVal; - if ((retVal = TransferApiBlockingPrologue(handle, buffer, count)) != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - StartReceiveDMA(handle, buffer, count, BlockingComplete); + if ((retVal = TransferApiPrologue(handle, (void*)txBuffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } - WaitForTransferCompletion(handle); + if (rxBuffer == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - return handle->transferStatus; + StartTransferDMA(handle, txBuffer, rxBuffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Start an SPI master transfer. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[in] txBuffer Transmit data buffer. -// -// @param[out] rxBuffer Receive data buffer. -// -// @param[in] count Number of bytes in transfer. -// -// @param[in] callback Transfer completion callback. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_Transfer( - NF_SpiDriver_Handle_t handle, - const void *txBuffer, - void *rxBuffer, - int count, - NF_SpiDriver_Callback_t callback) +/***************************************************************************//** + * @brief + * Start an SPI master blocking transfer. + * + * @note + * This function is blocking and returns when the transfer is complete + * or when @ref NF_SpiDriver_AbortTransfer() is called. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] txBuffer Transmit data buffer. + * + * @param[out] rxBuffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED + * if @ref NF_SpiDriver_AbortTransfer() has been called. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MTransferB(NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count) { - Ecode_t retVal; + Ecode_t retVal; - retVal = TransferApiPrologue(handle, (void *)txBuffer, count); + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - if (retVal != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + if ((retVal = TransferApiBlockingPrologue(handle, (void*)txBuffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } - if (rxBuffer == NULL) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if (rxBuffer == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - StartTransferDMA(handle, txBuffer, rxBuffer, count, callback); + StartTransferDMA(handle, txBuffer, rxBuffer, count, BlockingComplete); - return ECODE_EMDRV_SPIDRV_OK; + WaitForTransferCompletion(handle); + + return handle->transferStatus; } -// -// -// Start an SPI master blocking transfer. -// -// @note -// This function is blocking and returns when the transfer is complete -// or when @ref SPIDRV_AbortTransfer() is called. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[in] txBuffer Transmit data buffer. -// -// @param[out] rxBuffer Receive data buffer. -// -// @param[in] count Number of bytes in transfer. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED -// if @ref SPIDRV_AbortTransfer() has been called. On failure, an appropriate -// SPIDRV @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_TransferBlocking(NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count) +/***************************************************************************//** + * @brief + * Start an SPI master blocking single item (frame) transfer. + * + * @note + * This function is blocking and returns when the transfer is complete + * or when @ref NF_SpiDriver_AbortTransfer() is called. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] txValue Value to transmit. + * + * @param[out] rxValue Value received. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED + * if @ref NF_SpiDriver_AbortTransfer() has been called. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MTransferSingleItemB(NF_SpiDriver_Handle_t handle, + uint32_t txValue, + void *rxValue) { - Ecode_t retVal; + void *pRx; + CORE_DECLARE_IRQ_STATE; + uint32_t rxBuffer; - retVal = TransferApiBlockingPrologue(handle, (void *)txBuffer, count); + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - if (retVal != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - if (rxBuffer == NULL) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + handle->state = spidrvStateTransferring; + CORE_EXIT_ATOMIC(); - StartTransferDMA(handle, txBuffer, rxBuffer, count, BlockingComplete); + if ((pRx = rxValue) == NULL) { + pRx = &rxBuffer; + } - WaitForTransferCompletion(handle); + StartTransferDMA(handle, &txValue, pRx, 1, BlockingComplete); - return handle->transferStatus; + WaitForTransferCompletion(handle); + + return handle->transferStatus; } -// -// -// Start an SPI master transmit transfer. -// -// @note -// The data received on the MISO wire is discarded. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[in] buffer Transmit data buffer. -// -// @param[in] count Number of bytes in transfer. -// -// @param[in] callback Transfer completion callback. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_Transmit( - NF_SpiDriver_Handle_t handle, - const void *buffer, - int count, - NF_SpiDriver_Callback_t callback) +/***************************************************************************//** + * @brief + * Start an SPI master transmit transfer. + * + * @note + * The data received on the MISO wire is discarded. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] buffer Transmit data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] callback Transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MTransmit(NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback) { - Ecode_t retVal; + Ecode_t retVal; - retVal = TransferApiPrologue(handle, (void *)buffer, count); + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - if (retVal != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + if ((retVal = TransferApiPrologue(handle, (void*)buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } - StartTransmitDMA(handle, buffer, count, callback); + StartTransmitDMA(handle, buffer, count, callback); - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Start an SPI master blocking transmit transfer. -// -// @note -// The data received on the MISO wire is discarded. -// @n This function is blocking and returns when the transfer is complete. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[in] buffer Transmit data buffer. -// -// @param[in] count Number of bytes in transfer. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED -// if @ref SPIDRV_AbortTransfer() has been called. On failure, an appropriate -// SPIDRV @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_TransmitBlocking(NF_SpiDriver_Handle_t handle, const void *buffer, int count) +/***************************************************************************//** + * @brief + * Start an SPI master blocking transmit transfer. + * + * @note + * The data received on the MISO wire is discarded. + * @n This function is blocking and returns when the transfer is complete. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] buffer Transmit data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success or @ref ECODE_EMDRV_SPIDRV_ABORTED + * if @ref NF_SpiDriver_AbortTransfer() has been called. On failure, an appropriate + * SPIDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_MTransmitB(NF_SpiDriver_Handle_t handle, + const void *buffer, + int count) { - Ecode_t retVal; + Ecode_t retVal; - retVal = TransferApiBlockingPrologue(handle, (void *)buffer, count); + if (handle->initData->type == spidrvSlave) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - if (retVal != ECODE_EMDRV_SPIDRV_OK) - { - return retVal; - } + if ((retVal = TransferApiBlockingPrologue(handle, (void*)buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } - StartTransmitDMA(handle, buffer, count, BlockingComplete); + StartTransmitDMA(handle, buffer, count, BlockingComplete); - WaitForTransferCompletion(handle); + WaitForTransferCompletion(handle); - return handle->transferStatus; + return handle->transferStatus; } -// -// -// Set SPI bus bitrate. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[in] bitRate New SPI bus bitrate. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// +/***************************************************************************//** + * @brief + * Set SPI bus bitrate. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] bitRate New SPI bus bitrate. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ Ecode_t NF_SpiDriver_SetBitrate(NF_SpiDriver_Handle_t handle, uint32_t bitRate) { - CORE_DECLARE_IRQ_STATE; + CORE_DECLARE_IRQ_STATE; - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - CORE_ENTER_ATOMIC(); - if (handle->state != spidrvStateIdle) - { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_BUSY; - } + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + + handle->initData->bitRate = bitRate; + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + USART_BaudrateSyncSet(handle->peripheral.usartPort, 0, bitRate); + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + EUSART_BaudrateSet(handle->peripheral.eusartPort, 0, bitRate); + } +#endif + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_SPIDRV_OK; +} + +/***************************************************************************//** + * @brief + * Set SPI framelength. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] frameLength New SPI bus framelength. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_SetFramelength(NF_SpiDriver_Handle_t handle, uint32_t frameLength) +{ + CORE_DECLARE_IRQ_STATE; - handle->initData->bitRate = bitRate; + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - if (0) - { + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + frameLength -= EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET; + + if ((frameLength < _USART_FRAME_DATABITS_FOUR) || (frameLength > _USART_FRAME_DATABITS_SIXTEEN)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - USART_BaudrateSyncSet(handle->peripheral.usartPort, 0, bitRate); + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + frameLength -= EMDRV_SPIDRV_EUSART_FRAMELENGTH_REGVALUE_OFFSET; + + if ((frameLength < _EUSART_FRAMECFG_DATABITS_SEVEN) || (frameLength > _EUSART_FRAMECFG_DATABITS_SIXTEEN)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; } + } +#endif + + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) { CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + handle->initData->frameLength = frameLength + EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET; + + handle->peripheral.usartPort->FRAME = (handle->peripheral.usartPort->FRAME + & ~_USART_FRAME_DATABITS_MASK) + | (frameLength + << _USART_FRAME_DATABITS_SHIFT); + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + handle->initData->frameLength = frameLength + EMDRV_SPIDRV_EUSART_FRAMELENGTH_REGVALUE_OFFSET; + + EUSART_Enable(handle->peripheral.eusartPort, eusartDisable); + handle->peripheral.eusartPort->FRAMECFG = (handle->peripheral.eusartPort->FRAMECFG + & ~_EUSART_FRAMECFG_DATABITS_MASK) + | (frameLength + << _EUSART_FRAMECFG_DATABITS_SHIFT); + EUSART_Enable(handle->peripheral.eusartPort, eusartEnable); + } +#endif + CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// -// Set SPI framelength. -// -// @param[in] handle Pointer to an SPI driver handle. -// -// @param[in] frameLength New SPI bus framelength. -// -// @return -// @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV -// @ref Ecode_t is returned. -// -Ecode_t NF_SpiDriver_SetFramelength(NF_SpiDriver_Handle_t handle, uint32_t frameLength) +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) +/***************************************************************************//** + * @brief + * Start an SPI slave receive transfer. + * + * @note + * The MISO wire will transmit @ref NF_SpiDriver_Init.dummyTxValue. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] buffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] callback Transfer completion callback. + * + * @param[in] timeoutMs Transfer timeout in milliseconds. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_SReceive(NF_SpiDriver_Handle_t handle, + void *buffer, + int count, + NF_SpiDriver_Callback_t callback, + int timeoutMs) { - CORE_DECLARE_IRQ_STATE; + Ecode_t retVal; - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + if (handle->initData->type == spidrvMaster) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } + + if ((retVal = TransferApiPrologue(handle, buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + if (timeoutMs) { + sl_sleeptimer_start_timer_ms(&handle->timer, timeoutMs, SlaveTimeout, handle, 0, 0); + } + + if (handle->initData->slaveStartMode == spidrvSlaveStartDelayed) { + if ((retVal = WaitForIdleLine(handle)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; } + } + + StartReceiveDMA(handle, buffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start an SPI slave blocking receive transfer. + * + * @note + * The MISO wire will transmit @ref NF_SpiDriver_Init.dummyTxValue. + * @n This function is blocking and returns when the transfer is complete, + * on timeout, or when @ref NF_SpiDriver_AbortTransfer() is called. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[out] buffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] timeoutMs Transfer timeout in milliseconds. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_TIMEOUT on + * timeout or @ref ECODE_EMDRV_SPIDRV_ABORTED if @ref NF_SpiDriver_AbortTransfer() + * has been called. On failure, an appropriate SPIDRV @ref Ecode_t is + * returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_SReceiveB(NF_SpiDriver_Handle_t handle, + void *buffer, + int count, + int timeoutMs) +{ + Ecode_t retVal; - if (0) - { + if (handle->initData->type == spidrvMaster) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } + + if ((retVal = TransferApiBlockingPrologue(handle, buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + if (timeoutMs) { + sl_sleeptimer_start_timer_ms(&handle->timer, timeoutMs, SlaveTimeout, handle, 0, 0); + } + + if (handle->initData->slaveStartMode == spidrvSlaveStartDelayed) { + if ((retVal = WaitForIdleLine(handle)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - frameLength -= EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET; - - if ((frameLength < _USART_FRAME_DATABITS_FOUR) || (frameLength > _USART_FRAME_DATABITS_SIXTEEN)) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + } + + StartReceiveDMA(handle, buffer, count, BlockingComplete); + + WaitForTransferCompletion(handle); + + return handle->transferStatus; +} + +/***************************************************************************//** + * @brief + * Start an SPI slave transfer. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] txBuffer Transmit data buffer. + * + * @param[out] rxBuffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] callback Transfer completion callback. + * + * @param[in] timeoutMs Transfer timeout in milliseconds. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_STransfer(NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + NF_SpiDriver_Callback_t callback, + int timeoutMs) +{ + Ecode_t retVal; + + if (handle->initData->type == spidrvMaster) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } + + if ((retVal = TransferApiPrologue(handle, (void*)txBuffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + if (rxBuffer == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + if (timeoutMs) { + sl_sleeptimer_start_timer_ms(&handle->timer, timeoutMs, SlaveTimeout, handle, 0, 0); + } + + if (handle->initData->slaveStartMode == spidrvSlaveStartDelayed) { + if ((retVal = WaitForIdleLine(handle)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; } + } + + StartTransferDMA(handle, txBuffer, rxBuffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start an SPI slave blocking transfer. + * + * @note + * @n This function is blocking and returns when the transfer is complete, + * on timeout, or when @ref NF_SpiDriver_AbortTransfer() is called. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] txBuffer Transmit data buffer. + * + * @param[out] rxBuffer Receive data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] timeoutMs Transfer timeout in milliseconds. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_TIMEOUT on + * timeout or @ref ECODE_EMDRV_SPIDRV_ABORTED if @ref NF_SpiDriver_AbortTransfer() + * has been called. On failure, an appropriate SPIDRV @ref Ecode_t is + * returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_STransferB(NF_SpiDriver_Handle_t handle, + const void *txBuffer, + void *rxBuffer, + int count, + int timeoutMs) +{ + Ecode_t retVal; + + if (handle->initData->type == spidrvMaster) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } - CORE_ENTER_ATOMIC(); - if (handle->state != spidrvStateIdle) - { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_BUSY; + if ((retVal = TransferApiBlockingPrologue(handle, (void*)txBuffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + if (rxBuffer == NULL) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + + if (timeoutMs) { + sl_sleeptimer_start_timer_ms(&handle->timer, timeoutMs, SlaveTimeout, handle, 0, 0); + } + + if (handle->initData->slaveStartMode == spidrvSlaveStartDelayed) { + if ((retVal = WaitForIdleLine(handle)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; } + } + + StartTransferDMA(handle, txBuffer, rxBuffer, count, BlockingComplete); - if (0) - { + WaitForTransferCompletion(handle); + + return handle->transferStatus; +} + +/***************************************************************************//** + * @brief + * Start an SPI slave transmit transfer. + * + * @note + * The data received on the MOSI wire is discarded. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] buffer Transmit data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] callback Transfer completion callback. + * + * @param[in] timeoutMs Transfer timeout in milliseconds. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success. On failure, an appropriate SPIDRV + * @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_STransmit(NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback, + int timeoutMs) +{ + Ecode_t retVal; + + if (handle->initData->type == spidrvMaster) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } + + if ((retVal = TransferApiPrologue(handle, (void*)buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + if (timeoutMs) { + sl_sleeptimer_start_timer_ms(&handle->timer, timeoutMs, SlaveTimeout, handle, 0, 0); + } + + if (handle->initData->slaveStartMode == spidrvSlaveStartDelayed) { + if ((retVal = WaitForIdleLine(handle)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - handle->initData->frameLength = frameLength + EMDRV_SPIDRV_USART_FRAMELENGTH_REGVALUE_OFFSET; + } + + StartTransmitDMA(handle, buffer, count, callback); + + return ECODE_EMDRV_SPIDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start an SPI slave blocking transmit transfer. + * + * @note + * The data received on the MOSI wire is discarded. + * @n This function is blocking and returns when the transfer is complete, + * on timeout, or when @ref NF_SpiDriver_AbortTransfer() is called. + * + * @param[in] handle Pointer to an SPI driver handle. + * + * @param[in] buffer Transmit data buffer. + * + * @param[in] count Number of bytes in transfer. + * + * @param[in] timeoutMs Transfer timeout in milliseconds. + * + * @return + * @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_TIMEOUT on + * timeout or @ref ECODE_EMDRV_SPIDRV_ABORTED if @ref NF_SpiDriver_AbortTransfer() + * has been called. On failure, an appropriate SPIDRV @ref Ecode_t is + * returned. + ******************************************************************************/ +Ecode_t NF_SpiDriver_STransmitB(NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + int timeoutMs) +{ + Ecode_t retVal; + + if (handle->initData->type == spidrvMaster) { + return ECODE_EMDRV_SPIDRV_MODE_ERROR; + } + + if ((retVal = TransferApiBlockingPrologue(handle, (void*)buffer, count)) + != ECODE_EMDRV_SPIDRV_OK) { + return retVal; + } + + if (timeoutMs) { + sl_sleeptimer_start_timer_ms(&handle->timer, timeoutMs, SlaveTimeout, handle, 0, 0); + } - handle->peripheral.usartPort->FRAME = (handle->peripheral.usartPort->FRAME & ~_USART_FRAME_DATABITS_MASK) | - (frameLength << _USART_FRAME_DATABITS_SHIFT); + if (handle->initData->slaveStartMode == spidrvSlaveStartDelayed) { + if ((retVal = WaitForIdleLine(handle)) != ECODE_EMDRV_SPIDRV_OK) { + return retVal; } - CORE_EXIT_ATOMIC(); + } + + StartTransmitDMA(handle, buffer, count, BlockingComplete); - return ECODE_EMDRV_SPIDRV_OK; + WaitForTransferCompletion(handle); + + return handle->transferStatus; } +#endif -// -// -// Transfer complete callback function used by blocking transfer API -// functions. Called by DMA interrupt handler, timer timeout handler -// or @ref SPIDRV_AbortTransfer() function. -// -static void BlockingComplete(NF_SpiDriver_Handle_t handle, Ecode_t transferStatus, int itemsTransferred) +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * @brief + * Transfer complete callback function used by blocking transfer API + * functions. Called by DMA interrupt handler, timer timeout handler + * or @ref NF_SpiDriver_AbortTransfer() function. + ******************************************************************************/ +static void BlockingComplete(NF_SpiDriver_Handle_t handle, + Ecode_t transferStatus, + int itemsTransferred) { - (void)itemsTransferred; + (void)itemsTransferred; - handle->transferStatus = transferStatus; - handle->blockingCompleted = true; - // signal RTOS event - tx_event_flags_set(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR); + handle->transferStatus = transferStatus; + handle->blockingCompleted = true; + // signal RTOS event + tx_event_flags_set(&nanoHardwareEvents, NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, TX_OR); } +#if defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief Get SPI pins for Series 0 devices. + ******************************************************************************/ +static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t * pins) +{ + uint32_t location; + + location = handle->initData->portLocation; + + if (0) { +#if defined(USART0) + } else if (handle->peripheral.usartPort == USART0) { + pins->mosiPort = AF_USART0_TX_PORT(location); + pins->misoPort = AF_USART0_RX_PORT(location); + pins->clkPort = AF_USART0_CLK_PORT(location); + pins->csPort = AF_USART0_CS_PORT(location); + pins->mosiPin = AF_USART0_TX_PIN(location); + pins->misoPin = AF_USART0_RX_PIN(location); + pins->clkPin = AF_USART0_CLK_PIN(location); + pins->csPin = AF_USART0_CS_PIN(location); +#endif +#if defined(USART1) + } else if (handle->peripheral.usartPort == USART1) { + pins->mosiPort = AF_USART1_TX_PORT(location); + pins->misoPort = AF_USART1_RX_PORT(location); + pins->clkPort = AF_USART1_CLK_PORT(location); + pins->csPort = AF_USART1_CS_PORT(location); + pins->mosiPin = AF_USART1_TX_PIN(location); + pins->misoPin = AF_USART1_RX_PIN(location); + pins->clkPin = AF_USART1_CLK_PIN(location); + pins->csPin = AF_USART1_CS_PIN(location); +#endif +#if defined(USART2) + } else if (handle->peripheral.usartPort == USART2) { + pins->mosiPort = AF_USART2_TX_PORT(location); + pins->misoPort = AF_USART2_RX_PORT(location); + pins->clkPort = AF_USART2_CLK_PORT(location); + pins->csPort = AF_USART2_CS_PORT(location); + pins->mosiPin = AF_USART2_TX_PIN(location); + pins->misoPin = AF_USART2_RX_PIN(location); + pins->clkPin = AF_USART2_CLK_PIN(location); + pins->csPin = AF_USART2_CS_PIN(location); +#endif +#if defined(USARTRF0) + } else if (handle->peripheral.usartPort == USARTRF0) { + pins->mosiPort = AF_USARTRF0_TX_PORT(location); + pins->misoPort = AF_USARTRF0_RX_PORT(location); + pins->clkPort = AF_USARTRF0_CLK_PORT(location); + pins->csPort = AF_USARTRF0_CS_PORT(location); + pins->mosiPin = AF_USARTRF0_TX_PIN(location); + pins->misoPin = AF_USARTRF0_RX_PIN(location); + pins->clkPin = AF_USARTRF0_CLK_PIN(location); + pins->csPin = AF_USARTRF0_CS_PIN(location); +#endif +#if defined(USARTRF1) + } else if (handle->peripheral.usartPort == USARTRF1) { + pins->mosiPort = AF_USARTRF1_TX_PORT(location); + pins->misoPort = AF_USARTRF1_RX_PORT(location); + pins->clkPort = AF_USARTRF1_CLK_PORT(location); + pins->csPort = AF_USARTRF1_CS_PORT(location); + pins->mosiPin = AF_USARTRF1_TX_PIN(location); + pins->misoPin = AF_USARTRF1_RX_PIN(location); + pins->clkPin = AF_USARTRF1_CLK_PIN(location); + pins->csPin = AF_USARTRF1_CS_PIN(location); +#endif + } else { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + return ECODE_EMDRV_SPIDRV_OK; +} +#endif + #if defined(_SILICON_LABS_32B_SERIES_1) -// -// Get SPI pins for Series 1 devices. -// -static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t *pins) +/***************************************************************************//** + * @brief Get SPI pins for Series 1 devices. + ******************************************************************************/ +static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t * pins) { - if (0) - { + if (0) { #if defined(USART0) - } - else if (handle->peripheral.usartPort == USART0) - { - pins->mosiPort = AF_USART0_TX_PORT(handle->initData->portLocationTx); - pins->misoPort = AF_USART0_RX_PORT(handle->initData->portLocationRx); - pins->clkPort = AF_USART0_CLK_PORT(handle->initData->portLocationClk); - pins->csPort = AF_USART0_CS_PORT(handle->initData->portLocationCs); - pins->mosiPin = AF_USART0_TX_PIN(handle->initData->portLocationTx); - pins->misoPin = AF_USART0_RX_PIN(handle->initData->portLocationRx); - pins->clkPin = AF_USART0_CLK_PIN(handle->initData->portLocationClk); - pins->csPin = AF_USART0_CS_PIN(handle->initData->portLocationCs); + } else if (handle->peripheral.usartPort == USART0) { + pins->mosiPort = AF_USART0_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART0_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART0_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART0_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART0_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART0_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART0_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART0_CS_PIN(handle->initData->portLocationCs); #endif #if defined(USART1) - } - else if (handle->peripheral.usartPort == USART1) - { - pins->mosiPort = AF_USART1_TX_PORT(handle->initData->portLocationTx); - pins->misoPort = AF_USART1_RX_PORT(handle->initData->portLocationRx); - pins->clkPort = AF_USART1_CLK_PORT(handle->initData->portLocationClk); - pins->csPort = AF_USART1_CS_PORT(handle->initData->portLocationCs); - pins->mosiPin = AF_USART1_TX_PIN(handle->initData->portLocationTx); - pins->misoPin = AF_USART1_RX_PIN(handle->initData->portLocationRx); - pins->clkPin = AF_USART1_CLK_PIN(handle->initData->portLocationClk); - pins->csPin = AF_USART1_CS_PIN(handle->initData->portLocationCs); + } else if (handle->peripheral.usartPort == USART1) { + pins->mosiPort = AF_USART1_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART1_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART1_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART1_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART1_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART1_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART1_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART1_CS_PIN(handle->initData->portLocationCs); #endif #if defined(USART2) - } - else if (handle->peripheral.usartPort == USART2) - { - pins->mosiPort = AF_USART2_TX_PORT(handle->initData->portLocationTx); - pins->misoPort = AF_USART2_RX_PORT(handle->initData->portLocationRx); - pins->clkPort = AF_USART2_CLK_PORT(handle->initData->portLocationClk); - pins->csPort = AF_USART2_CS_PORT(handle->initData->portLocationCs); - pins->mosiPin = AF_USART2_TX_PIN(handle->initData->portLocationTx); - pins->misoPin = AF_USART2_RX_PIN(handle->initData->portLocationRx); - pins->clkPin = AF_USART2_CLK_PIN(handle->initData->portLocationClk); - pins->csPin = AF_USART2_CS_PIN(handle->initData->portLocationCs); + } else if (handle->peripheral.usartPort == USART2) { + pins->mosiPort = AF_USART2_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART2_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART2_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART2_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART2_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART2_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART2_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART2_CS_PIN(handle->initData->portLocationCs); #endif #if defined(USART3) - } - else if (handle->peripheral.usartPort == USART3) - { - pins->mosiPort = AF_USART3_TX_PORT(handle->initData->portLocationTx); - pins->misoPort = AF_USART3_RX_PORT(handle->initData->portLocationRx); - pins->clkPort = AF_USART3_CLK_PORT(handle->initData->portLocationClk); - pins->csPort = AF_USART3_CS_PORT(handle->initData->portLocationCs); - pins->mosiPin = AF_USART3_TX_PIN(handle->initData->portLocationTx); - pins->misoPin = AF_USART3_RX_PIN(handle->initData->portLocationRx); - pins->clkPin = AF_USART3_CLK_PIN(handle->initData->portLocationClk); - pins->csPin = AF_USART3_CS_PIN(handle->initData->portLocationCs); + } else if (handle->peripheral.usartPort == USART3) { + pins->mosiPort = AF_USART3_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART3_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART3_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART3_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART3_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART3_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART3_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART3_CS_PIN(handle->initData->portLocationCs); #endif #if defined(USART4) - } - else if (handle->peripheral.usartPort == USART4) - { - pins->mosiPort = AF_USART4_TX_PORT(handle->initData->portLocationTx); - pins->misoPort = AF_USART4_RX_PORT(handle->initData->portLocationRx); - pins->clkPort = AF_USART4_CLK_PORT(handle->initData->portLocationClk); - pins->csPort = AF_USART4_CS_PORT(handle->initData->portLocationCs); - pins->mosiPin = AF_USART4_TX_PIN(handle->initData->portLocationTx); - pins->misoPin = AF_USART4_RX_PIN(handle->initData->portLocationRx); - pins->clkPin = AF_USART4_CLK_PIN(handle->initData->portLocationClk); - pins->csPin = AF_USART4_CS_PIN(handle->initData->portLocationCs); + } else if (handle->peripheral.usartPort == USART4) { + pins->mosiPort = AF_USART4_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART4_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART4_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART4_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART4_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART4_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART4_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART4_CS_PIN(handle->initData->portLocationCs); #endif #if defined(USART5) - } - else if (handle->peripheral.usartPort == USART5) - { - pins->mosiPort = AF_USART5_TX_PORT(handle->initData->portLocationTx); - pins->misoPort = AF_USART5_RX_PORT(handle->initData->portLocationRx); - pins->clkPort = AF_USART5_CLK_PORT(handle->initData->portLocationClk); - pins->csPort = AF_USART5_CS_PORT(handle->initData->portLocationCs); - pins->mosiPin = AF_USART5_TX_PIN(handle->initData->portLocationTx); - pins->misoPin = AF_USART5_RX_PIN(handle->initData->portLocationRx); - pins->clkPin = AF_USART5_CLK_PIN(handle->initData->portLocationClk); - pins->csPin = AF_USART5_CS_PIN(handle->initData->portLocationCs); + } else if (handle->peripheral.usartPort == USART5) { + pins->mosiPort = AF_USART5_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USART5_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USART5_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USART5_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USART5_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USART5_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USART5_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USART5_CS_PIN(handle->initData->portLocationCs); #endif - } - else - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } - return ECODE_EMDRV_SPIDRV_OK; +#if defined(USARTRF0) + } else if (handle->peripheral.usartPort == USARTRF0) { + pins->mosiPort = AF_USARTRF0_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USARTRF0_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USARTRF0_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USARTRF0_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USARTRF0_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USARTRF0_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USARTRF0_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USARTRF0_CS_PIN(handle->initData->portLocationCs); +#endif +#if defined(USARTRF1) + } else if (handle->peripheral.usartPort == USARTRF1) { + pins->mosiPort = AF_USARTRF1_TX_PORT(handle->initData->portLocationTx); + pins->misoPort = AF_USARTRF1_RX_PORT(handle->initData->portLocationRx); + pins->clkPort = AF_USARTRF1_CLK_PORT(handle->initData->portLocationClk); + pins->csPort = AF_USARTRF1_CS_PORT(handle->initData->portLocationCs); + pins->mosiPin = AF_USARTRF1_TX_PIN(handle->initData->portLocationTx); + pins->misoPin = AF_USARTRF1_RX_PIN(handle->initData->portLocationRx); + pins->clkPin = AF_USARTRF1_CLK_PIN(handle->initData->portLocationClk); + pins->csPin = AF_USARTRF1_CS_PIN(handle->initData->portLocationCs); +#endif + } else { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } + return ECODE_EMDRV_SPIDRV_OK; } #endif #if defined(_SILICON_LABS_32B_SERIES_2) -// -// Get SPI pins for Series 2 devices. -// -static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t// pins) +/***************************************************************************//** + * @brief Get SPI pins for Series 2 devices. + ******************************************************************************/ +static Ecode_t GetSpiPins(NF_SpiDriver_Handle_t handle, SPI_Pins_t * pins) { - pins->mosiPort = handle->initData->portTx; - pins->misoPort = handle->initData->portRx; - pins->clkPort = handle->initData->portClk; - pins->csPort = handle->initData->portCs; - pins->mosiPin = handle->initData->pinTx; - pins->misoPin = handle->initData->pinRx; - pins->clkPin = handle->initData->pinClk; - pins->csPin = handle->initData->pinCs; - - return ECODE_EMDRV_SPIDRV_OK; + pins->mosiPort = handle->initData->portTx; + pins->misoPort = handle->initData->portRx; + pins->clkPort = handle->initData->portClk; + pins->csPort = handle->initData->portCs; + pins->mosiPin = handle->initData->pinTx; + pins->misoPin = handle->initData->pinRx; + pins->clkPin = handle->initData->pinClk; + pins->csPin = handle->initData->pinCs; + + return ECODE_EMDRV_SPIDRV_OK; } #endif -// -// Configure/deconfigure SPI GPIO pins. -// +/***************************************************************************//** + * @brief Configure/deconfigure SPI GPIO pins. + ******************************************************************************/ static Ecode_t ConfigGPIO(NF_SpiDriver_Handle_t handle, bool enable) { - SPI_Pins_t pins; - Ecode_t ret; - - ret = GetSpiPins(handle, &pins); - if (ret != ECODE_EMDRV_SPIDRV_OK) - { - return ret; - } - handle->portCs = (GPIO_Port_TypeDef)pins.csPort; - handle->pinCs = pins.csPin; - - if (enable) - { - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, gpioModePushPull, 0); - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, gpioModeInput, 0); - - if ((handle->initData->clockMode == spidrvClockMode0) || (handle->initData->clockMode == spidrvClockMode1)) - { - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModePushPull, 0); - } - else - { - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModePushPull, 1); - } - - if (handle->initData->csControl == spidrvCsControlAuto) - { - GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, gpioModePushPull, 1); - } - } - else - { - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, gpioModeInputPull, 0); - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, gpioModeInputPull, 0); - - if ((handle->initData->clockMode == spidrvClockMode0) || (handle->initData->clockMode == spidrvClockMode1)) - { - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModeInputPull, 0); - } - else - { - GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModeInputPull, 1); - } - - if (handle->initData->csControl == spidrvCsControlAuto) - { - GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, gpioModeDisabled, 0); - } - } - - return ECODE_EMDRV_SPIDRV_OK; + SPI_Pins_t pins; + Ecode_t ret; + + ret = GetSpiPins(handle, &pins); + if (ret != ECODE_EMDRV_SPIDRV_OK) { + return ret; + } + handle->portCs = (GPIO_Port_TypeDef)pins.csPort; + handle->pinCs = pins.csPin; + + if (enable) { + if (handle->initData->type == spidrvMaster) { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, + gpioModePushPull, 0); + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, + gpioModeInput, 0); + + if ((handle->initData->clockMode == spidrvClockMode0) + || (handle->initData->clockMode == spidrvClockMode1)) { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, + gpioModePushPull, 0); + } else { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, + gpioModePushPull, 1); + } + + if (handle->initData->csControl == spidrvCsControlAuto) { + GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, + gpioModePushPull, 1); + } + } else { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, + gpioModeInput, 0); + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, + gpioModePushPull, 0); + + if ((handle->initData->clockMode == spidrvClockMode0) + || (handle->initData->clockMode == spidrvClockMode1)) { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, + gpioModeInputPull, 0); + } else { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, + gpioModeInputPull, 1); + } + + if (handle->initData->csControl == spidrvCsControlAuto) { + GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, + gpioModeInputPull, 1); + } + } + } else { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.mosiPort, pins.mosiPin, gpioModeInputPull, 0); + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.misoPort, pins.misoPin, gpioModeInputPull, 0); + + if ((handle->initData->clockMode == spidrvClockMode0) + || (handle->initData->clockMode == spidrvClockMode1)) { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModeInputPull, 0); + } else { + GPIO_PinModeSet((GPIO_Port_TypeDef)pins.clkPort, pins.clkPin, gpioModeInputPull, 1); + } + + if (handle->initData->csControl == spidrvCsControlAuto) { + GPIO_PinModeSet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs, + gpioModeDisabled, 0); + } + } + + return ECODE_EMDRV_SPIDRV_OK; } -// -// DMA transfer completion callback. Called by the DMA interrupt handler. -// +/***************************************************************************//** + * @brief DMA transfer completion callback. Called by the DMA interrupt handler. + ******************************************************************************/ static bool RxDMAComplete(unsigned int channel, unsigned int sequenceNo, void *userParam) { - CORE_DECLARE_IRQ_STATE; - NF_SpiDriver_Handle_t handle; - (void)channel; - (void)sequenceNo; + CORE_DECLARE_IRQ_STATE; + NF_SpiDriver_Handle_t handle; + (void)channel; + (void)sequenceNo; - CORE_ENTER_ATOMIC(); + CORE_ENTER_ATOMIC(); - handle = (NF_SpiDriver_Handle_t)userParam; + handle = (NF_SpiDriver_Handle_t)userParam; - if (handle->initData->isHalfDuplex) - { - // Turn off TX tri-stating - handle->peripheral.usartPort->CMD = USART_CMD_TXTRIDIS; - } + handle->transferStatus = ECODE_EMDRV_SPIDRV_OK; + handle->state = spidrvStateIdle; + handle->remaining = 0; + +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) + if (handle->initData->type == spidrvSlave) { + sl_sleeptimer_stop_timer(&handle->timer); + } +#endif + + if (handle->userCallback != NULL) { + handle->userCallback(handle, ECODE_EMDRV_SPIDRV_OK, handle->transferCount); + } - handle->transferStatus = ECODE_EMDRV_SPIDRV_OK; - handle->state = spidrvStateIdle; - handle->remaining = 0; + CORE_EXIT_ATOMIC(); + em1RequestRemove(handle); - if (handle->userCallback != NULL) - { - handle->userCallback(handle, ECODE_EMDRV_SPIDRV_OK, handle->transferCount); + return true; +} + +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) +/***************************************************************************//** + * @brief Slave transfer timeout callback function. + ******************************************************************************/ +static void SlaveTimeout(sl_sleeptimer_timer_handle_t *sleepdriver_handle, void *user) +{ + bool active, pending; + NF_SpiDriver_Handle_t handle; + (void)sleepdriver_handle; + + handle = (NF_SpiDriver_Handle_t)user; + + if (handle->state == spidrvStateTransferring) { + DMADRV_TransferActive(handle->rxDMACh, &active); + if (active) { + // Stop running DMAs + DMADRV_StopTransfer(handle->rxDMACh); + DMADRV_StopTransfer(handle->txDMACh); + DMADRV_TransferRemainingCount(handle->rxDMACh, &handle->remaining); + } else { + // DMA is either completed or not yet started + DMADRV_TransferCompletePending(handle->txDMACh, &pending); + if (pending) { + // A DMA interrupt is pending; let the DMA handler do the rest + return; + } + handle->remaining = handle->transferCount; } + handle->transferStatus = ECODE_EMDRV_SPIDRV_TIMEOUT; + handle->state = spidrvStateIdle; - CORE_EXIT_ATOMIC(); - em1RequestRemove(handle); + if (handle->userCallback != NULL) { + handle->userCallback(handle, + ECODE_EMDRV_SPIDRV_TIMEOUT, + handle->transferCount - handle->remaining); + } + } +} +#endif - return true; +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * @brief Manually clear eusart Tx fifo. + ******************************************************************************/ +static void clearEusartFifos(EUSART_TypeDef *eusart) +{ + // EUSART_CMD_CLEARTX reportedly only affects UART, not SPI mode, + // and there is no EUSART_CMD_CLEARRX. Only way to clear the + // FIFOs is via the big hammer of disabling then reenabling it. + EUSART_Enable(eusart, eusartDisable); + EUSART_Enable(eusart, eusartEnable); } +#endif -// -// Start an SPI receive DMA. -// +/***************************************************************************//** + * @brief Start an SPI receive DMA. + ******************************************************************************/ static void StartReceiveDMA(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback) { - void *rxPort, *txPort; - DMADRV_DataSize_t size; - - handle->blockingCompleted = false; - handle->transferCount = count; - handle->userCallback = callback; - - if (0) - { - } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - if (handle->initData->isHalfDuplex) - { - // Block RX while sending from master - handle->peripheral.usartPort->CMD = USART_CMD_RXBLOCKEN; - } - - if (handle->initData->frameLength > 9) - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); - txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); - } - else if (handle->initData->frameLength == 9) - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); - txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); - } - else - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); - txPort = (void *)&(handle->peripheral.usartPort->TXDATA); - } - } - else - { - return; - } - - if (handle->initData->frameLength > 8) - { - size = dmadrvDataSize2; - } - else - { - size = dmadrvDataSize1; - } + void *rxPort, *txPort; + DMADRV_DataSize_t size; + + handle->blockingCompleted = false; + handle->transferCount = count; + handle->userCallback = callback; + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (handle->initData->frameLength > 9) { + rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); + txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); + } else if (handle->initData->frameLength == 9) { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); + txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); + } else { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); + txPort = (void *)&(handle->peripheral.usartPort->TXDATA); + } + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + clearEusartFifos(handle->peripheral.eusartPort); - em1RequestAdd(handle); - - // Start receive DMA. - DMADRV_PeripheralMemory( - handle->rxDMACh, - handle->rxDMASignal, - (void *)buffer, - rxPort, - true, - count, - size, - RxDMAComplete, - handle); - - // Start transmit DMA. - DMADRV_MemoryPeripheral( - handle->txDMACh, - handle->txDMASignal, - txPort, - (void *)&(handle->initData->dummyTxValue), - false, - count, - size, - NULL, - NULL); + rxPort = (void *)&(handle->peripheral.eusartPort->RXDATA); + txPort = (void *)&(handle->peripheral.eusartPort->TXDATA); + } +#endif + else { + return; + } + + if (handle->initData->frameLength > 8) { + size = dmadrvDataSize2; + } else { + size = dmadrvDataSize1; + } + + em1RequestAdd(handle); + + // Start receive DMA. + DMADRV_PeripheralMemory(handle->rxDMACh, + handle->rxDMASignal, + (void*)buffer, + rxPort, + true, + count, + size, + RxDMAComplete, + handle); + + // Start transmit DMA. + DMADRV_MemoryPeripheral(handle->txDMACh, + handle->txDMASignal, + txPort, + (void *)&(handle->initData->dummyTxValue), + false, + count, + size, + NULL, + NULL); } -// -// Start an SPI transmit/receive DMA. -// +/***************************************************************************//** + * @brief Start an SPI transmit/receive DMA. + ******************************************************************************/ static void StartTransferDMA(NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count, NF_SpiDriver_Callback_t callback) { - void *rxPort, *txPort; - DMADRV_DataSize_t size; - - handle->blockingCompleted = false; - handle->transferCount = count; - handle->userCallback = callback; - - if (0) - { - } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - if (handle->initData->frameLength > 9) - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); - txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); - } - else if (handle->initData->frameLength == 9) - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); - txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); - } - else - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); - txPort = (void *)&(handle->peripheral.usartPort->TXDATA); - } - } - else - { - return; - } - - if (handle->initData->frameLength > 8) - { - size = dmadrvDataSize2; - } - else - { - size = dmadrvDataSize1; - } + void *rxPort, *txPort; + DMADRV_DataSize_t size; + + handle->blockingCompleted = false; + handle->transferCount = count; + handle->userCallback = callback; + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (handle->initData->frameLength > 9) { + rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); + txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); + } else if (handle->initData->frameLength == 9) { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); + txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); + } else { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); + txPort = (void *)&(handle->peripheral.usartPort->TXDATA); + } + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + clearEusartFifos(handle->peripheral.eusartPort); - em1RequestAdd(handle); - - // Start receive DMA. - DMADRV_PeripheralMemory( - handle->rxDMACh, - handle->rxDMASignal, - rxBuffer, - rxPort, - true, - count, - size, - RxDMAComplete, - handle); - - // Start transmit DMA. - DMADRV_MemoryPeripheral( - handle->txDMACh, - handle->txDMASignal, - txPort, - (void *)txBuffer, - true, - count, - size, - NULL, - NULL); + rxPort = (void *)&(handle->peripheral.eusartPort->RXDATA); + txPort = (void *)&(handle->peripheral.eusartPort->TXDATA); + } +#endif + else { + return; + } + + if (handle->initData->frameLength > 8) { + size = dmadrvDataSize2; + } else { + size = dmadrvDataSize1; + } + + em1RequestAdd(handle); + + // Start receive DMA. + DMADRV_PeripheralMemory(handle->rxDMACh, + handle->rxDMASignal, + rxBuffer, + rxPort, + true, + count, + size, + RxDMAComplete, + handle); + + // Start transmit DMA. + DMADRV_MemoryPeripheral(handle->txDMACh, + handle->txDMASignal, + txPort, + (void*)txBuffer, + true, + count, + size, + NULL, + NULL); } -// -// Start an SPI transmit DMA. -// +/***************************************************************************//** + * @brief Start an SPI transmit DMA. + ******************************************************************************/ static void StartTransmitDMA(NF_SpiDriver_Handle_t handle, const void *buffer, int count, NF_SpiDriver_Callback_t callback) { - void *rxPort, *txPort; - DMADRV_DataSize_t size; - - handle->blockingCompleted = false; - handle->transferCount = count; - handle->userCallback = callback; - - if (0) - { - } - else if (handle->peripheralType == spidrvPeripheralTypeUsart) - { - handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - if (handle->initData->frameLength > 9) - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); - txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); - } - else if (handle->initData->frameLength == 9) - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); - txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); - } - else - { - rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); - txPort = (void *)&(handle->peripheral.usartPort->TXDATA); - } - } - else - { - return; - } - - if (handle->initData->frameLength > 8) - { - size = dmadrvDataSize2; - } - else - { - size = dmadrvDataSize1; - } + void *rxPort, *txPort; + DMADRV_DataSize_t size; + + handle->blockingCompleted = false; + handle->transferCount = count; + handle->userCallback = callback; + + if (0) { + } +#if defined(USART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeUsart) { + handle->peripheral.usartPort->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + if (handle->initData->frameLength > 9) { + rxPort = (void *)&(handle->peripheral.usartPort->RXDOUBLE); + txPort = (void *)&(handle->peripheral.usartPort->TXDOUBLE); + } else if (handle->initData->frameLength == 9) { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATAX); + txPort = (void *)&(handle->peripheral.usartPort->TXDATAX); + } else { + rxPort = (void *)&(handle->peripheral.usartPort->RXDATA); + txPort = (void *)&(handle->peripheral.usartPort->TXDATA); + } + } +#endif +#if defined(EUSART_PRESENT) + else if (handle->peripheralType == spidrvPeripheralTypeEusart) { + clearEusartFifos(handle->peripheral.eusartPort); - em1RequestAdd(handle); - - // Receive DMA runs only to get precise numbers for SPIDRV_GetTransferStatus() - // Start receive DMA. - DMADRV_PeripheralMemory( - handle->rxDMACh, - handle->rxDMASignal, - &(handle->dummyRx), - rxPort, - false, - count, - size, - RxDMAComplete, - handle); - - // Start transmit DMA. - DMADRV_MemoryPeripheral( - handle->txDMACh, - handle->txDMASignal, - txPort, - (void *)buffer, - true, - count, - size, - NULL, - NULL); + rxPort = (void *)&(handle->peripheral.eusartPort->RXDATA); + txPort = (void *)&(handle->peripheral.eusartPort->TXDATA); + } +#endif + else { + return; + } + + if (handle->initData->frameLength > 8) { + size = dmadrvDataSize2; + } else { + size = dmadrvDataSize1; + } + + em1RequestAdd(handle); + + // Receive DMA runs only to get precise numbers for NF_SpiDriver_GetTransferStatus() + // Start receive DMA. + DMADRV_PeripheralMemory(handle->rxDMACh, + handle->rxDMASignal, + &(handle->dummyRx), + rxPort, + false, + count, + size, + RxDMAComplete, + handle); + + // Start transmit DMA. + DMADRV_MemoryPeripheral(handle->txDMACh, + handle->txDMASignal, + txPort, + (void*)buffer, + true, + count, + size, + NULL, + NULL); } -// -// Parameter checking function for blocking transfer API functions. -// +/***************************************************************************//** + * @brief Parameter checking function for blocking transfer API functions. + ******************************************************************************/ static Ecode_t TransferApiBlockingPrologue(NF_SpiDriver_Handle_t handle, void *buffer, int count) { - CORE_DECLARE_IRQ_STATE; + CORE_DECLARE_IRQ_STATE; - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - if ((buffer == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if ((buffer == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - CORE_ENTER_ATOMIC(); - if (handle->state != spidrvStateIdle) - { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_BUSY; - } - handle->state = spidrvStateTransferring; + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) { CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + handle->state = spidrvStateTransferring; + CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// Parameter checking function for non-blocking transfer API functions. -// +/***************************************************************************//** + * @brief Parameter checking function for non-blocking transfer API functions. + ******************************************************************************/ static Ecode_t TransferApiPrologue(NF_SpiDriver_Handle_t handle, void *buffer, int count) { - CORE_DECLARE_IRQ_STATE; + CORE_DECLARE_IRQ_STATE; - if (handle == NULL) - { - return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; - } + if (handle == NULL) { + return ECODE_EMDRV_SPIDRV_ILLEGAL_HANDLE; + } - if ((buffer == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) - { - return ECODE_EMDRV_SPIDRV_PARAM_ERROR; - } + if ((buffer == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) { + return ECODE_EMDRV_SPIDRV_PARAM_ERROR; + } - CORE_ENTER_ATOMIC(); - if (handle->state != spidrvStateIdle) - { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_BUSY; - } - handle->state = spidrvStateTransferring; + CORE_ENTER_ATOMIC(); + if (handle->state != spidrvStateIdle) { CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_SPIDRV_BUSY; + } + handle->state = spidrvStateTransferring; + CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_SPIDRV_OK; + return ECODE_EMDRV_SPIDRV_OK; } -// -// @brief Wait for transfer completion. -// +/***************************************************************************//** + * @brief Wait for transfer completion. + ******************************************************************************/ static void WaitForTransferCompletion(NF_SpiDriver_Handle_t handle) { uint32_t dummy; - if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) - { - // Poll for completion by calling IRQ handler. - while (handle->blockingCompleted == false) - { + if (CORE_IrqIsBlocked(SPI_DMA_IRQ)) { + // Poll for completion by calling IRQ handler. + while (handle->blockingCompleted == false) { #if defined(DMA_PRESENT) && (DMA_COUNT == 1) - DMA_IRQHandler(); + DMA_IRQHandler(); #elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - LDMA_IRQHandler(); + LDMA_IRQHandler(); #else #error "No valid SPIDRV DMA engine defined." #endif - } } - else - { - // wait forever for the SPI event - tx_event_flags_get( - &nanoHardwareEvents, - NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, - TX_OR_CLEAR, - &dummy, - TX_WAIT_FOREVER); + } else { + // wait forever for the SPI event + tx_event_flags_get( + &nanoHardwareEvents, + NANO_HW_EVENTS_SPI_TRANSACTION_FLAG, + TX_OR_CLEAR, + &dummy, + TX_WAIT_FOREVER); + } +} + +#if defined(EMDRV_SPIDRV_INCLUDE_SLAVE) +/***************************************************************************//** + * @brief Wait for CS deassertion. Used by slave transfer API functions. + ******************************************************************************/ +static Ecode_t WaitForIdleLine(NF_SpiDriver_Handle_t handle) +{ + while (!GPIO_PinInGet((GPIO_Port_TypeDef)handle->portCs, handle->pinCs) + && (handle->state != spidrvStateIdle)) ; + + if (handle->state == spidrvStateIdle) { + return handle->transferStatus; + } + + return ECODE_EMDRV_SPIDRV_OK; +} +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(EUSART_PRESENT) +/***************************************************************************//** + * @brief Enable EUSART and SPI IOs after deepsleep + ******************************************************************************/ +static Ecode_t sli_spidrv_exit_em23(NF_SpiDriver_Handle_t handle) +{ + EUSART_TypeDef *eusart = handle->peripheral.eusartPort; + + EUSART_Enable(eusart, eusartEnable); + BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(eusart)].ROUTEEN, + _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, + GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN); + + return ECODE_EMDRV_SPIDRV_OK; +} + +/***************************************************************************//** + * @brief Disable SPIO IOs before deepsleep + ******************************************************************************/ +static Ecode_t sli_spidrv_enter_em23(NF_SpiDriver_Handle_t handle) +{ + EUSART_TypeDef *eusart = handle->peripheral.eusartPort; + + BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(eusart)].ROUTEEN, + _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, + 0); + + return ECODE_EMDRV_SPIDRV_OK; +} + +/***************************************************************************//** + * Power Manager callback notification for EUSART. + * It is used to prepare EUSART module before/after deepsleeping. + ******************************************************************************/ +static void on_power_manager_event(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + (void)from; + NF_SpiDriver_Handle_t handle; + + if (to == SL_POWER_MANAGER_EM1 + || to == SL_POWER_MANAGER_EM0) { + SL_SLIST_FOR_EACH_ENTRY(eusart_handle_list, handle, NF_SpiDriver_HandleData_t, node) { + sli_spidrv_exit_em23(handle); } + } + + if (to == SL_POWER_MANAGER_EM2 + || to == SL_POWER_MANAGER_EM3) { + SL_SLIST_FOR_EACH_ENTRY(eusart_handle_list, handle, NF_SpiDriver_HandleData_t, node) { + sli_spidrv_enter_em23(handle); + } + } } +#endif + +// clang-format on diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h index 39e17cbaf9..44cf1fd807 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/System.Device.Spi/nf_gecko_spi_driver.h @@ -58,6 +58,7 @@ extern "C" /// SPI driver instance type. SL_ENUM(NF_SpiDriver_Type_t){ spidrvMaster = 0, ///< Act as an SPI master. + spidrvSlave = 1 ///< Act as an SPI slave. }; /// SPI bus bit order. @@ -87,8 +88,7 @@ extern "C" }; /// Type of a USART peripheral - SL_ENUM(NF_SpiDriver_PeripheralType_t) - { + SL_ENUM(NF_SpiDriver_PeripheralType_t){ spidrvPeripheralTypeUsart = 0, ///< USART peripheral }; @@ -117,7 +117,8 @@ extern "C" * @ref ECODE_EMDRV_SPIDRV_OK on success, @ref ECODE_EMDRV_SPIDRV_TIMEOUT * on timeout. Timeouts are only relevant for slave mode transfers. */ - typedef void (*NF_SpiDriver_Callback_t)(struct NF_SpiDriver_HandleData *handle, Ecode_t transferStatus, int itemsTransferred); + typedef void ( + *NF_SpiDriver_Callback_t)(struct NF_SpiDriver_HandleData *handle, Ecode_t transferStatus, int itemsTransferred); /// An SPI driver instance initialization structure. /// Contains a number of SPIDRV configuration options. @@ -126,18 +127,19 @@ extern "C" /// @ref spidrv_init_structs typedef struct NF_SpiDriver_Init { - void *port; ///< The USART used for SPI. - uint8_t portLocationTx; ///< A location number for the SPI Tx pin. - uint8_t portLocationRx; ///< A location number for the SPI Rx pin. - uint8_t portLocationClk; ///< A location number for the SPI Clk pin. - uint8_t portLocationCs; ///< A location number for the SPI Cs pin. + void *port; ///< The USART used for SPI. + uint8_t portLocationTx; ///< A location number for the SPI Tx pin. + uint8_t portLocationRx; ///< A location number for the SPI Rx pin. + uint8_t portLocationClk; ///< A location number for the SPI Clk pin. + uint8_t portLocationCs; ///< A location number for the SPI Cs pin. uint32_t bitRate; ///< An SPI bitrate. uint32_t frameLength; ///< An SPI framelength, valid numbers are 4..16 uint32_t dummyTxValue; ///< The value to transmit when using SPI receive API functions. - NF_SpiDriver_BitOrder_t bitOrder; ///< A bit order on the SPI bus, MSB or LSB first. - NF_SpiDriver_ClockMode_t clockMode; ///< SPI mode, CLKPOL/CLKPHASE setting. - NF_SpiDriver_CsControl_t csControl; ///< A select master mode chip select (CS) control scheme. - bool isHalfDuplex; ///< True if the SPI is half duplex. + NF_SpiDriver_Type_t type; ///< An SPI type, master or slave. + NF_SpiDriver_BitOrder_t bitOrder; ///< A bit order on the SPI bus, MSB or LSB first. + NF_SpiDriver_ClockMode_t clockMode; ///< SPI mode, CLKPOL/CLKPHASE setting. + NF_SpiDriver_CsControl_t csControl; ///< A select master mode chip select (CS) control scheme. + bool isHalfDuplex; ///< True if the SPI is half duplex. } NF_SpiDriver_Init_t; /// An SPI driver instance handle data structure. @@ -186,22 +188,30 @@ extern "C" Ecode_t NF_SpiDriver_Init(NF_SpiDriver_Handle_t handle, NF_SpiDriver_Init_t *initData); - Ecode_t NF_SpiDriver_Receive(NF_SpiDriver_Handle_t handle, void *buffer, int count, NF_SpiDriver_Callback_t callback); + Ecode_t NF_SpiDriver_MReceive( + NF_SpiDriver_Handle_t handle, + void *buffer, + int count, + NF_SpiDriver_Callback_t callback); - Ecode_t NF_SpiDriver_ReceiveBlocking(NF_SpiDriver_Handle_t handle, void *buffer, int count); + Ecode_t NF_SpiDriver_MReceiveB(NF_SpiDriver_Handle_t handle, void *buffer, int count); - Ecode_t NF_SpiDriver_Transfer( + Ecode_t NF_SpiDriver_MTransfer( NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count, NF_SpiDriver_Callback_t callback); - Ecode_t NF_SpiDriver_TransferBlocking(NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count); + Ecode_t NF_SpiDriver_MTransferB(NF_SpiDriver_Handle_t handle, const void *txBuffer, void *rxBuffer, int count); - Ecode_t NF_SpiDriver_Transmit(NF_SpiDriver_Handle_t handle, const void *buffer, int count, NF_SpiDriver_Callback_t callback); + Ecode_t NF_SpiDriver_MTransmit( + NF_SpiDriver_Handle_t handle, + const void *buffer, + int count, + NF_SpiDriver_Callback_t callback); - Ecode_t NF_SpiDriver_TransmitBlocking(NF_SpiDriver_Handle_t handle, const void *buffer, int count); + Ecode_t NF_SpiDriver_MTransmitB(NF_SpiDriver_Handle_t handle, const void *buffer, int count); Ecode_t NF_SpiDriver_SetBitrate(NF_SpiDriver_Handle_t handle, uint32_t bitRate); From 1ac2a71177b2216e375c8bec063c8aee266d010d Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 19 Dec 2024 17:49:56 +0000 Subject: [PATCH 568/572] Update Skyworks SPI lib to new Gecko SPI API --- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 22 +++++++++++-------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 0e3c61d15f..17e232682e 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -382,7 +382,7 @@ static HRESULT SPI_nWrite_nRead( { // Full duplex // Uses the largest buffer size as transfer size - NF_SpiDriver_TransferBlocking( + NF_SpiDriver_MTransferB( palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, @@ -397,7 +397,7 @@ static HRESULT SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; // } - NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); // receive operation // TODO @@ -406,7 +406,7 @@ static HRESULT SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } } else @@ -421,7 +421,7 @@ static HRESULT SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_ReceiveBlocking(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } else { @@ -432,7 +432,7 @@ static HRESULT SPI_nWrite_nRead( // half duplex operation, set output enable // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; } - NF_SpiDriver_TransmitBlocking(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); } } } @@ -454,7 +454,7 @@ static HRESULT SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // Uses the largest buffer size as transfer size - NF_SpiDriver_Transfer( + NF_SpiDriver_MTransfer( palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, @@ -474,7 +474,7 @@ static HRESULT SPI_nWrite_nRead( } // receive operation will be started in the callback after the above completes - NF_SpiDriver_Transmit( + NF_SpiDriver_MTransmit( palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize, @@ -490,7 +490,11 @@ static HRESULT SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start receive - NF_SpiDriver_Receive(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize, SpiTransferCompleteCallback); + NF_SpiDriver_MReceive( + palSpi->Handle, + palSpi->ReadBuffer, + palSpi->ReadSize, + SpiTransferCompleteCallback); } else { @@ -498,7 +502,7 @@ static HRESULT SPI_nWrite_nRead( palSpi->SequentialTxRx = false; // start send - NF_SpiDriver_Transmit( + NF_SpiDriver_MTransmit( palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize, From 1e32aa4de3369453328b8a02caddbe650fcc2407 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Fri, 20 Dec 2024 11:28:55 +0000 Subject: [PATCH 569/572] Update Skyworks.Devices.Spi assembly declaration - Following Skyworks-Timing-Software/MCU#152. --- .../com_sky_nf_dev_spi_native.cpp | 5 +++-- .../com_sky_nf_dev_spi_native.h | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp index 9b3368fa06..047e91b910 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.cpp @@ -40,14 +40,15 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, + NULL, }; const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi = { "Com.SkyworksInc.NanoFramework.Devices.Spi", - 0xF287AE32, + 0x25E3D06E, method_lookup, - { 100, 0, 0, 9 } + { 100, 0, 0, 10 } }; // clang-format on diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index da68c7bfbd..791cc6f532 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -15,6 +15,13 @@ // DataFlow_LsbFirst = 1, // } DataFlow; +typedef enum __nfpack SpiError +{ + SpiError_Unknown = 0, + SpiError_Timeout = 1, + SpiError_Aborted = 2, +} SpiError; + // defined src\System.Device.Spi\sys_dev_spi_native.h typedef enum __nfpack SpiPhasePolarityMode { @@ -56,6 +63,16 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S NANOCLR_NATIVE_DECLARE(NativeGetBusSpeed___I4__I4__ComSkyworksIncNanoFrameworkDevicesSpiSpiBaseConfiguration); //--// + + static HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack); + static HRESULT ThrowError(CLR_RT_StackFrame &stack, CLR_INT32 errorCode); +}; + +struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiException +{ + static const int FIELD___errorCode = 5; + + //--// }; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Com_SkyworksInc_NanoFramework_Devices_Spi; From e74d66efd1cc09af3308743ad1bd727203277c8c Mon Sep 17 00:00:00 2001 From: josesimoes Date: Fri, 20 Dec 2024 11:34:41 +0000 Subject: [PATCH 570/572] Add error handling of SPI low level API - Now processing return result and throwing exception with encoded error code on failure. - Update declaration of ThrowError function. --- .../com_sky_nf_dev_spi_native.h | 2 +- ...ksInc_NanoFramework_Devices_Spi_SpiBus.cpp | 71 ++++++++++++++++--- 2 files changed, 64 insertions(+), 9 deletions(-) diff --git a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h index 791cc6f532..bcf610a248 100644 --- a/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h +++ b/src/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native.h @@ -65,7 +65,7 @@ struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_S //--// static HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack); - static HRESULT ThrowError(CLR_RT_StackFrame &stack, CLR_INT32 errorCode); + static HRESULT ThrowError(CLR_RT_StackFrame &stack, CLR_UINT32 errorCode); }; struct Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiException diff --git a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp index 17e232682e..cfc49d3039 100644 --- a/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp +++ b/targets/AzureRTOS/SiliconLabs/_nanoCLR/Com.SkyworksInc.NanoFramework.Devices.Spi/com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus.cpp @@ -13,6 +13,7 @@ typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBaseConfiguration SpiBaseConfiguration; typedef Library_corlib_native_System_SpanByte SpanByte; +typedef Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiException SpiException; static HRESULT SPI_nWrite_nRead( NF_PAL_SPI *palSpi, @@ -119,7 +120,8 @@ bool System_Device_IsLongRunningOperation( } } -HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::ExecuteTransfer( + CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); @@ -135,6 +137,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) int16_t readOffset = 0; int16_t writeOffset = 0; bool fullDuplex; + int32_t operationResult; bool isLongRunningOperation; uint32_t estimatedDurationMiliseconds; @@ -270,7 +273,7 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) // Start SPI transfer // We can ask for async transfer by setting callback but it depends if underlying supports it // return of CLR_E_BUSY means async started - hr = SPI_nWrite_nRead( + operationResult = SPI_nWrite_nRead( palSpi, SpiConfigs[busIndex - 1], rws, @@ -280,10 +283,15 @@ HRESULT ExecuteTransfer(CLR_RT_StackFrame &stack) (int32_t)readSize); // Async transfer started, go to custom 2 state (wait completion) - if (hr == CLR_E_BUSY) + if (operationResult == CLR_E_BUSY) { stack.m_customState = 2; } + else if (operationResult != S_OK) + { + // Something went wrong with SPI transfer + NANOCLR_CHECK_HRESULT(ThrowError(stack, operationResult)); + } } // Waiting for Async operation to complete @@ -327,6 +335,7 @@ static HRESULT SPI_nWrite_nRead( NANOCLR_HEADER(); bool busConfigIsHalfDuplex; + Ecode_t transferResult; // If callback then use async operation bool sync = (wrc.callback == 0); @@ -382,7 +391,7 @@ static HRESULT SPI_nWrite_nRead( { // Full duplex // Uses the largest buffer size as transfer size - NF_SpiDriver_MTransferB( + transferResult = NF_SpiDriver_MTransferB( palSpi->Handle, palSpi->WriteBuffer, palSpi->ReadBuffer, @@ -397,7 +406,13 @@ static HRESULT SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; // } - NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + transferResult = NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + + // bail out if the transmit operation failed + if (transferResult != ECODE_EMDRV_SPIDRV_OK) + { + NANOCLR_SET_AND_LEAVE(transferResult); + } // receive operation // TODO @@ -406,7 +421,7 @@ static HRESULT SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + transferResult = NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } } else @@ -421,7 +436,7 @@ static HRESULT SPI_nWrite_nRead( // // half duplex operation, set output enable // palSpi->Handle->spi->CR1 &= ~SPI_CR1_BIDIOE; // } - NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); + transferResult = NF_SpiDriver_MReceiveB(palSpi->Handle, palSpi->ReadBuffer, palSpi->ReadSize); } else { @@ -432,9 +447,11 @@ static HRESULT SPI_nWrite_nRead( // half duplex operation, set output enable // palSpi->Handle->spi->CR1 |= SPI_CR1_BIDIOE; } - NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); + transferResult = NF_SpiDriver_MTransmitB(palSpi->Handle, palSpi->WriteBuffer, palSpi->WriteSize); } } + + NANOCLR_SET_AND_LEAVE(transferResult); } else { @@ -658,3 +675,41 @@ HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_ NANOCLR_NOCLEANUP(); } + +HRESULT Library_com_sky_nf_dev_spi_native_Com_SkyworksInc_NanoFramework_Devices_Spi_SpiBus::ThrowError( + CLR_RT_StackFrame &stack, + CLR_UINT32 errorCode) +{ + NANOCLR_HEADER(); + + SpiError spiErrorCode; + + CLR_RT_HeapBlock &res = stack.m_owningThread->m_currentException; + + if ((Library_corlib_native_System_Exception::CreateInstance( + res, + g_CLR_RT_WellKnownTypes.m_SocketException, + CLR_E_FAIL, + &stack)) == S_OK) + { + // Set the error code + if (errorCode == ECODE_EMDRV_SPIDRV_TIMEOUT) + { + spiErrorCode = SpiError_Timeout; + } + else if (errorCode == ECODE_EMDRV_SPIDRV_ABORTED) + { + spiErrorCode = SpiError_Aborted; + } + else + { + spiErrorCode = SpiError_Unknown; + } + + res.Dereference()[SpiException::FIELD___errorCode].SetInteger((CLR_UINT32)spiErrorCode); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + + NANOCLR_NOCLEANUP(); +} From a6c6ff5970ed32f772ffe2fbf61cd73f030f69e5 Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 26 Dec 2024 10:32:13 +0000 Subject: [PATCH 571/572] Add bound and pointer checks to memmove calls --- .../CorLib/corlib_native_System_Number.cpp | 84 ++++++++++++++----- 1 file changed, 63 insertions(+), 21 deletions(-) diff --git a/src/CLR/CorLib/corlib_native_System_Number.cpp b/src/CLR/CorLib/corlib_native_System_Number.cpp index 34a9939a03..5ceeedba30 100644 --- a/src/CLR/CorLib/corlib_native_System_Number.cpp +++ b/src/CLR/CorLib/corlib_native_System_Number.cpp @@ -196,30 +196,45 @@ int Library_corlib_native_System_Number::GetDotIndex(char *buffer, int bufferCon void Library_corlib_native_System_Number::RoundUpNumStr(char *buffer, int *bufferContentLength) { char *c = &buffer[*bufferContentLength - 1]; + for (;;) { if (*c != '.' && *c != '-') { *c += 1; + if (*c <= '9') + { break; + } + *c = '0'; } + if (c == buffer) { if (*c == '-') { - memmove(&buffer[2], &buffer[1], *bufferContentLength + 1); - buffer[1] = '1'; + if (*bufferContentLength > 1) + { + memmove(&buffer[2], &buffer[1], *bufferContentLength + 1); + buffer[1] = '1'; + } } else { - memmove(&buffer[1], buffer, *bufferContentLength + 1); - buffer[0] = '1'; + if (*bufferContentLength > 0) + { + memmove(&buffer[1], buffer, *bufferContentLength + 1); + buffer[0] = '1'; + } } + (*bufferContentLength)++; + break; } + c--; } } @@ -232,9 +247,12 @@ int Library_corlib_native_System_Number::ReplaceNegativeSign(char *buffer, int b { int negativeSignLength = GetStrLen(negativeSign); - memmove(&buffer[negativeSignLength], &buffer[1], bufferContentLength); - memcpy(buffer, negativeSign, negativeSignLength); - ret += negativeSignLength - 1; + if (bufferContentLength > 1) + { + memmove(&buffer[negativeSignLength], &buffer[1], bufferContentLength); + memcpy(buffer, negativeSign, negativeSignLength); + ret += negativeSignLength - 1; + } } return ret; @@ -248,13 +266,22 @@ int Library_corlib_native_System_Number::ReplaceDecimalSeparator( int ret = bufferContentLength; int dotIndex = GetDotIndex(buffer, bufferContentLength); + if (dotIndex != -1) { int decimalSeparatorLength = GetStrLen(decimalSeparator); - memmove(&buffer[dotIndex + decimalSeparatorLength], &buffer[dotIndex + 1], bufferContentLength); - memcpy(&buffer[dotIndex], decimalSeparator, decimalSeparatorLength); - ret += decimalSeparatorLength - 1; + if (bufferContentLength > dotIndex + 1) + { + memmove( + &buffer[dotIndex + decimalSeparatorLength], + &buffer[dotIndex + 1], + bufferContentLength - dotIndex - 1); + + memcpy(&buffer[dotIndex], decimalSeparator, decimalSeparatorLength); + + ret += decimalSeparatorLength - 1; + } } return ret; @@ -271,10 +298,12 @@ int Library_corlib_native_System_Number::InsertGroupSeparators( int significantDigitsStartAtIndex = 0; int significantDigitCount = bufferContentLength - 1; int dotIndex = GetDotIndex(buffer, bufferContentLength); + if (dotIndex != -1) { significantDigitCount = dotIndex - 1; } + if (buffer[0] == '-') { significantDigitCount--; @@ -289,27 +318,40 @@ int Library_corlib_native_System_Number::InsertGroupSeparators( { ret = bufferContentLength + plusLength; - int srcIdx = bufferContentLength; - int tgtIdx = ret; + int sourceIdx = bufferContentLength; + int targetIdx = ret; if (dotIndex != -1) { int fractionPostfixWithDotLength = bufferContentLength - dotIndex; - memmove(&buffer[dotIndex + plusLength], &buffer[dotIndex], fractionPostfixWithDotLength); - srcIdx -= fractionPostfixWithDotLength; - tgtIdx -= fractionPostfixWithDotLength; + + if (bufferContentLength > dotIndex) + { + memmove(&buffer[dotIndex + plusLength], &buffer[dotIndex], fractionPostfixWithDotLength); + + sourceIdx -= fractionPostfixWithDotLength; + targetIdx -= fractionPostfixWithDotLength; + } } for (;;) { - if ((srcIdx - significantDigitsStartAtIndex) <= groupSize) + if ((sourceIdx - significantDigitsStartAtIndex) <= groupSize) + { break; + } + + targetIdx -= groupSize; + sourceIdx -= groupSize; - tgtIdx -= groupSize; - srcIdx -= groupSize; - memmove(&buffer[tgtIdx], &buffer[srcIdx], groupSize); - tgtIdx -= groupSepLength; - memcpy(&buffer[tgtIdx], groupSep, groupSepLength); + if (bufferContentLength > sourceIdx) + { + memmove(&buffer[targetIdx], &buffer[sourceIdx], groupSize); + + targetIdx -= groupSepLength; + + memcpy(&buffer[targetIdx], groupSep, groupSepLength); + } } } From 9664bd935c6e5c313aa00695e033189065e31d2b Mon Sep 17 00:00:00 2001 From: josesimoes Date: Thu, 26 Dec 2024 12:02:56 +0000 Subject: [PATCH 572/572] Fix ASSERT in GC heap compact - Fix compiler define conditional. - Fix assert for move size. --- src/CLR/Core/GarbageCollector_Compaction.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/CLR/Core/GarbageCollector_Compaction.cpp b/src/CLR/Core/GarbageCollector_Compaction.cpp index b7c681de08..cd16c5aa2a 100644 --- a/src/CLR/Core/GarbageCollector_Compaction.cpp +++ b/src/CLR/Core/GarbageCollector_Compaction.cpp @@ -256,13 +256,13 @@ void CLR_RT_GarbageCollector::Heap_Compact() freeRegion->Unlink(); -#ifdef _DEBUG +#ifdef DEBUG _ASSERTE(relocCurrent->m_destination >= (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode()); _ASSERTE(relocCurrent->m_destination < (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.LastNode()); _ASSERTE(relocCurrent->m_start >= (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.FirstNode()); _ASSERTE(relocCurrent->m_start < (CLR_UINT8 *)g_CLR_RT_ExecutionEngine.m_heap.LastNode()); - _ASSERTE(moveBytes <= freeRegion_Size); + _ASSERTE(moveBytes <= (move * sizeof(CLR_RT_HeapBlock))); #endif