Configure AIE through control packets

[jtuyls]

As enabling general AIE configuration through control packets will be a heavy lift, I intend to approach this in phases:

1. As an initial POC, use control packets to program shim DMAs.
2. Use control packets to program Memtile DMAs and cores (DMAs + PM) (in addition to shim)
3. Use control packets to program stream switches?? (in addition to shim, memtile, cores)

For the initial POC to program shim DMAs using control packets, I believe the following pieces will be needed:

1. Some initial support for packet routing (at least between L3 and L2) so channels can be shared between control packets and data. Without this, there won't be enough Shim channels to do both. This will require some changes to AMDAIEStatetfulTransform to enable packet flows. As we're trying to get rid of this pass and AIE dialect ops, I will try to extract the flow logic from it so that the necessary transformations for enabling packet flows can be done on AMDAIE ops. Therefore, the following changes will be needed:
   • Extracting flow logic from AMDAIEStatefulTransform and moving it up into AMDAIE transformations.
     • Refactor: lower DMAs to connection + controlcode DMA ops #745
     • [StatefulTransform] Extract aie.flow generation #749
   • Enabling (optional) generation of packet flow ops instead of flow ops and generating correct data packet configurations.
     • [DmaToNpu] Add packet support for NpuDmaMemcpyNdOp #785
     • Enable optional packet flow connections between L3 and L2 #797
2. A way of providing preconfigured control packet routes and taking the union of the control packet and data packet routes into account while assigning resources, routing, etc.
3. New logic to lower shim DMA instructions to control packets (see Configure AIE using control packets Xilinx/mlir-aie#1728)

After this initial POC, I will move on to phases 2 and 3.

Resources:

• Configure AIE using control packets Xilinx/mlir-aie#1728
• Add control packet op and control packet to binary translation Xilinx/mlir-aie#1709
• Add packet info (type and id) attribute to aiex.npu.dma_mempcy_nd Xilinx/mlir-aie#1671

[makslevental]

The router will need to be updated again (well depending on how much we're gonna copy paste from mlir-aie).

[jtuyls]

The router will need to be updated again (well depending on how much we're gonna copy paste from mlir-aie).

Yeah, I was wondering about this. What changes would be needed in the router?

[makslevental]

Yeah, I was wondering about this. What changes would be needed in the router?

Some of this stuff https://github.com/Xilinx/mlir-aie/pulls?q=is%3Apr+is%3Aclosed+author%3AYu-Zhewen (starting with Xilinx/mlir-aie#1643).