Exported svg is using "physical wiring connections" instead of "signal name association" (netlists)

[71GA]

I sucessfully converted my verilog .v electronics design to .json and then in a .svg file but I see that all the connections are drawn using the "physicall wiring connections" like this:

And this is extremely hard to read unlike "netlists":

Is there a way to add support for "netlists"? So that schematics will at least be useful in development. Currently I get this...

top.pdf

And I can't do much with this...

[nobodywasishere]

I'm not sure if there'd be an easy way to determine which wires to disconnect and replace with labels vs which wires to leave in place. One option could just be opening up the generated netlist in inkscape afterwards and changing it around to fit what you're looking for, but this would be more of a one-time thing.

Personally, I think the first image you linked is easier to read (and what I would refer to as a netlist), but that's just me. I don't have to make mental connections of how everything fits together.

[rjordans]

I could imagine having a list of nets that should be translated into labels wherever they are used. That might be useful for more 'global' nets like clock or reset lines that can go in all kinds of directions sometimes. For most of the other nets I'd prefer the first image version too.

[71GA]

@nobodywasishere 1st image is "easier to" read exclusively because it is a really small design. Try this still "small" design of mine.

top.pdf

Good luck...

Probably now you see... It is impossible to read it, because vertical wires clutter everything. Try to follow some wires... You might even get dizzy!

[71GA]

Also in large designs it is hard to follow a wire, but when you have a label, you can simply CTRL+F and be done. Maybee it is possible to at least somehow implement an algorythm that checks the length of the wires and replaces the long ones with the labels. The long ones are the ones that mess everything anyway...