diff --git a/pscx_emulator/pscx_bios.cpp b/pscx_emulator/pscx_bios.cpp index b0a819d..837cde9 100644 --- a/pscx_emulator/pscx_bios.cpp +++ b/pscx_emulator/pscx_bios.cpp @@ -1,14 +1,15 @@ #include "pscx_bios.h" +#include "pscx_common.h" #include #include -Bios::BiosState Bios::loadBios(std::string path) +Bios::BiosState Bios::loadBios(const std::string& path) { std::basic_ifstream biosFile(path, std::ios::in | std::ios::binary); if (!biosFile.good()) - return BIOS_STATE_INCORRECT_FILENAME; + return BiosState::BIOS_STATE_INCORRECT_FILENAME; const uint32_t biosSize = 512 * 1024; // 512 kb @@ -18,9 +19,9 @@ Bios::BiosState Bios::loadBios(std::string path) biosFile.close(); if (m_data.size() != biosSize) - return BIOS_STATE_INVALID_BIOS_SIZE; + return BiosState::BIOS_STATE_INVALID_BIOS_SIZE; - return BIOS_STATE_SUCCESS; + return BiosState::BIOS_STATE_SUCCESS; } template<> uint32_t Bios::load(uint32_t offset) const @@ -35,6 +36,7 @@ template<> uint32_t Bios::load(uint32_t offset) const template<> uint16_t Bios::load(uint32_t offset) const { + PCSX_UNUSED(offset); return 0; } diff --git a/pscx_emulator/pscx_bios.h b/pscx_emulator/pscx_bios.h index c0d24f4..1419df1 100644 --- a/pscx_emulator/pscx_bios.h +++ b/pscx_emulator/pscx_bios.h @@ -10,7 +10,7 @@ using namespace pscx_memory; // BIOS image struct Bios { - enum BiosState + enum class BiosState { BIOS_STATE_SUCCESS, BIOS_STATE_INCORRECT_FILENAME, @@ -22,7 +22,7 @@ struct Bios std::vector m_data; // Load a BIOS image from the file that is located in 'path' - BiosState loadBios(std::string path); + BiosState loadBios(const std::string& path); template T load(uint32_t offset) const; diff --git a/pscx_emulator/pscx_cdrom.cpp b/pscx_emulator/pscx_cdrom.cpp index d992590..ab44e5b 100644 --- a/pscx_emulator/pscx_cdrom.cpp +++ b/pscx_emulator/pscx_cdrom.cpp @@ -186,7 +186,7 @@ void CdRom::sync(TimeKeeper& timeKeeper, InterruptState& irqState) { Cycles delta = timeKeeper.sync(Peripheral::PERIPHERAL_CDROM); - CommandState newCommandState; + CommandState newCommandState{ CommandState::COMMAND_STATE_INVALID }; switch (m_commandState) { case CommandState::COMMAND_STATE_IDLE: @@ -248,6 +248,7 @@ void CdRom::sync(TimeKeeper& timeKeeper, InterruptState& irqState) } } + assert(("Invalid command state", newCommandState != CommandState::COMMAND_STATE_INVALID)); m_commandState = newCommandState; // See if we have a read pending. @@ -789,7 +790,7 @@ CommandState CdRom::ackGetId() { if (m_disc) { - uint8_t regionSymbol; + uint8_t regionSymbol{}; switch (m_disc->getRegion()) { case Region::REGION_JAPAN: diff --git a/pscx_emulator/pscx_cdrom.h b/pscx_emulator/pscx_cdrom.h index 37b2056..2db1977 100644 --- a/pscx_emulator/pscx_cdrom.h +++ b/pscx_emulator/pscx_cdrom.h @@ -11,7 +11,7 @@ // Various IRQ codes used by the CDROM controller and their // signification. -enum IrqCode +enum class IrqCode { // A CD sector has been read and is ready to be processed. IRQ_CODE_SECTOR_READY = 1, @@ -24,7 +24,7 @@ enum IrqCode }; // CDROM controller state machine. -enum CommandState +enum class CommandState { // Controller is idle. COMMAND_STATE_IDLE, @@ -45,7 +45,7 @@ enum CommandState }; // CDROM data read state machine. -enum ReadState +enum class ReadState { READ_STATE_IDLE, // We're expection a sector @@ -119,6 +119,7 @@ struct CdRom m_readPosition(MinuteSecondFrame::createZeroTimestamp()), m_doubleSpeed(false), m_xaAdpcmToSpu(false), + m_rxSector(nullptr), m_rxActive(false), m_rxIndex(0x0), m_rxOffset(0x0), diff --git a/pscx_emulator/pscx_common.h b/pscx_emulator/pscx_common.h index 5143134..8da4857 100644 --- a/pscx_emulator/pscx_common.h +++ b/pscx_emulator/pscx_common.h @@ -4,10 +4,15 @@ #if _DEBUG #define LOG(msg) \ - //std::cout << __FILE__ << "(" << __LINE__ << "): " << msg << std::endl + std::cout << __FILE__ << "(" << __LINE__ << "): " << msg << std::endl #else #define LOG(msg) #endif #define WARN(msg) \ - std::cerr << __FILE__ << "(" << __LINE__ << "): " << msg << std::endl + std::cerr << __FILE__ << "(" << __LINE__ << "): " << msg << std::endl + +template +void PCSX_UNUSED(Args&&...) +{ +} diff --git a/pscx_emulator/pscx_cop0.h b/pscx_emulator/pscx_cop0.h index 6788385..b17f25c 100644 --- a/pscx_emulator/pscx_cop0.h +++ b/pscx_emulator/pscx_cop0.h @@ -4,7 +4,7 @@ #include "pscx_interrupts.h" // Exception types ( sd stored in the 'CAUSE' register ) -enum Exception +enum class Exception { // Interrupt Request EXCEPTION_INTERRUPT = 0x0, diff --git a/pscx_emulator/pscx_cpu.cpp b/pscx_emulator/pscx_cpu.cpp index a66d27a..5bd17c5 100644 --- a/pscx_emulator/pscx_cpu.cpp +++ b/pscx_emulator/pscx_cpu.cpp @@ -14,7 +14,7 @@ const std::vector& Cpu::getInstructionsDump() const return m_debugInstructions; } -std::vector Cpu::getPadProfiles() +std::vector Cpu::getPadProfiles() const { return m_inter.getPadProfiles(); } @@ -70,7 +70,7 @@ Cpu::InstructionType Cpu::decodeAndExecute(const Instruction& instruction) // Simulate instruction execution time. m_timeKeeper.tick(1); - InstructionType instructionType = INSTRUCTION_TYPE_UNKNOWN; + InstructionType instructionType{ InstructionType::INSTRUCTION_TYPE_UNKNOWN }; switch (instruction.getInstructionCode()) { @@ -309,16 +309,16 @@ Cpu::InstructionType Cpu::runNextInstuction() { // PC is not correctly aligned ! exception(Exception::EXCEPTION_LOAD_ADDRESS_ERROR); - return INSTRUCTION_TYPE_UNALIGNED; + return InstructionType::INSTRUCTION_TYPE_UNALIGNED; } // Fetch instruction at PC //Instruction instruction = load(m_pc); Instruction instruction = fetchInstruction(); Instruction::InstructionStatus instructionStatus = instruction.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; // Increment next PC to point to the next instruction. // All instructions are 32 bit long. @@ -329,8 +329,8 @@ Cpu::InstructionType Cpu::runNextInstuction() m_delaySlot = m_branch; m_branch = false; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; // Execute the pending load ( if any, otherwise it will load $zero which is a NOP ) // setRegisterValue works only on m_outRegs so this operation won't be visible by the next instruction @@ -340,12 +340,12 @@ Cpu::InstructionType Cpu::runNextInstuction() // We reset the load to target register 0 for the next instruction m_load = RegisterData(RegisterIndex(0x0), 0x0); - InstructionType instructionType = INSTRUCTION_TYPE_UNKNOWN; + InstructionType instructionType{ InstructionType::INSTRUCTION_TYPE_UNKNOWN }; // Check for pending interrupts if (m_cop0.isIrqActive(m_inter.getIrqState())) { exception(Exception::EXCEPTION_INTERRUPT); - instructionType = INSTRUCTION_TYPE_EXCEPTION_INTERRUPT; + instructionType = InstructionType::INSTRUCTION_TYPE_EXCEPTION_INTERRUPT; } else { @@ -423,13 +423,13 @@ Cpu::InstructionType Cpu::opcodeLUI(const Instruction& instruction) { // Low 16 bits are set to 0 setRegisterValue(instruction.getRegisterTargetIndex(), instruction.getImmediateValue() << 16); - return INSTRUCTION_TYPE_LUI; + return InstructionType::INSTRUCTION_TYPE_LUI; } Cpu::InstructionType Cpu::opcodeORI(const Instruction& instruction) { setRegisterValue(instruction.getRegisterTargetIndex(), instruction.getImmediateValue() | getRegisterValue(instruction.getRegisterSourceIndex())); - return INSTRUCTION_TYPE_ORI; + return InstructionType::INSTRUCTION_TYPE_ORI; } Cpu::InstructionType Cpu::opcodeSW(const Instruction& instruction) @@ -447,46 +447,46 @@ Cpu::InstructionType Cpu::opcodeSW(const Instruction& instruction) else { exception(Exception::EXCEPTION_STORE_ADDRESS_ERROR); - return INSTRUCTION_TYPE_UNALIGNED; + return InstructionType::INSTRUCTION_TYPE_UNALIGNED; } - return INSTRUCTION_TYPE_SW; + return InstructionType::INSTRUCTION_TYPE_SW; } Cpu::InstructionType Cpu::opcodeSLL(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(instruction.getRegisterTargetIndex()) << instruction.getShiftImmediateValue()); - return INSTRUCTION_TYPE_SLL; + return InstructionType::INSTRUCTION_TYPE_SLL; } Cpu::InstructionType Cpu::opcodeADDIU(const Instruction& instruction) { setRegisterValue(instruction.getRegisterTargetIndex(), getRegisterValue(instruction.getRegisterSourceIndex()) + instruction.getSignExtendedImmediateValue()); - return INSTRUCTION_TYPE_ADDIU; + return InstructionType::INSTRUCTION_TYPE_ADDIU; } Cpu::InstructionType Cpu::opcodeJ(const Instruction& instruction) { m_nextPc = (m_pc & 0xf0000000) | (instruction.getJumpTargetValue() << 2); m_branch = true; - return INSTRUCTION_TYPE_J; + return InstructionType::INSTRUCTION_TYPE_J; } Cpu::InstructionType Cpu::opcodeOR(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(instruction.getRegisterSourceIndex()) | getRegisterValue(instruction.getRegisterTargetIndex())); - return INSTRUCTION_TYPE_OR; + return InstructionType::INSTRUCTION_TYPE_OR; } Cpu::InstructionType Cpu::opcodeAND(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(instruction.getRegisterSourceIndex()) & getRegisterValue(instruction.getRegisterTargetIndex())); - return INSTRUCTION_TYPE_AND; + return InstructionType::INSTRUCTION_TYPE_AND; } Cpu::InstructionType Cpu::opcodeCOP0(const Instruction& instruction) { - InstructionType instructionType = INSTRUCTION_TYPE_UNKNOWN; + InstructionType instructionType{ InstructionType::INSTRUCTION_TYPE_UNKNOWN }; switch (instruction.getCopOpcodeValue()) { @@ -548,7 +548,7 @@ Cpu::InstructionType Cpu::opcodeMTC0(const Instruction& instruction) LOG("Unhandled cop0 register 0x" << std::hex << cop0Register); } - return INSTRUCTION_TYPE_MTC0; + return InstructionType::INSTRUCTION_TYPE_MTC0; } Cpu::InstructionType Cpu::opcodeMFC0(const Instruction& instruction) @@ -574,7 +574,7 @@ Cpu::InstructionType Cpu::opcodeMFC0(const Instruction& instruction) LOG("Unhandled read from cop0Register 0x" << std::hex << cop0Register); } - return INSTRUCTION_TYPE_MFC0; + return InstructionType::INSTRUCTION_TYPE_MFC0; } // Branch to immediate value "offset" @@ -591,7 +591,7 @@ Cpu::InstructionType Cpu::opcodeBNE(const Instruction& instruction) if (getRegisterValue(instruction.getRegisterSourceIndex()) != getRegisterValue(instruction.getRegisterTargetIndex())) branch(instruction.getSignExtendedImmediateValue()); - return INSTRUCTION_TYPE_BNE; + return InstructionType::INSTRUCTION_TYPE_BNE; } Cpu::InstructionType Cpu::opcodeADDI(const Instruction& instruction) @@ -606,14 +606,14 @@ Cpu::InstructionType Cpu::opcodeADDI(const Instruction& instruction) { LOG("ADDI overflow"); exception(Exception::EXCEPTION_OVERFLOW); - return INSTRUCTION_TYPE_OVERFLOW; + return InstructionType::INSTRUCTION_TYPE_OVERFLOW; } else { setRegisterValue(instruction.getRegisterTargetIndex(), uint32_t(registerSourceValue + signExtendedImmediateValue)); } - return INSTRUCTION_TYPE_ADDI; + return InstructionType::INSTRUCTION_TYPE_ADDI; } Cpu::InstructionType Cpu::opcodeLW(const Instruction& instruction) @@ -629,11 +629,11 @@ Cpu::InstructionType Cpu::opcodeLW(const Instruction& instruction) { Instruction instructionLoaded = load(addr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; // Put the load in the delay slot m_load = RegisterData(registerTargetIndex, instructionLoaded.getInstructionOpcode()); @@ -641,10 +641,10 @@ Cpu::InstructionType Cpu::opcodeLW(const Instruction& instruction) else { exception(Exception::EXCEPTION_LOAD_ADDRESS_ERROR); - return INSTRUCTION_TYPE_UNALIGNED; + return InstructionType::INSTRUCTION_TYPE_UNALIGNED; } - return INSTRUCTION_TYPE_LW; + return InstructionType::INSTRUCTION_TYPE_LW; } Cpu::InstructionType Cpu::opcodeSLTU(const Instruction& instruction) @@ -655,7 +655,7 @@ Cpu::InstructionType Cpu::opcodeSLTU(const Instruction& instruction) uint32_t registerValueComparison = getRegisterValue(registerSourceIndex) < getRegisterValue(registerTargetIndex); setRegisterValue(instruction.getRegisterDestinationIndex(), registerValueComparison); - return INSTRUCTION_TYPE_SLTU; + return InstructionType::INSTRUCTION_TYPE_SLTU; } Cpu::InstructionType Cpu::opcodeADDU(const Instruction& instruction) @@ -664,7 +664,7 @@ Cpu::InstructionType Cpu::opcodeADDU(const Instruction& instruction) RegisterIndex registerTargetIndex = instruction.getRegisterTargetIndex(); setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(registerSourceIndex) + getRegisterValue(registerTargetIndex)); - return INSTRUCTION_TYPE_ADDU; + return InstructionType::INSTRUCTION_TYPE_ADDU; } Cpu::InstructionType Cpu::opcodeSH(const Instruction& instruction) @@ -682,10 +682,10 @@ Cpu::InstructionType Cpu::opcodeSH(const Instruction& instruction) else { exception(Exception::EXCEPTION_STORE_ADDRESS_ERROR); - return INSTRUCTION_TYPE_UNALIGNED; + return InstructionType::INSTRUCTION_TYPE_UNALIGNED; } - return INSTRUCTION_TYPE_SH; + return InstructionType::INSTRUCTION_TYPE_SH; } Cpu::InstructionType Cpu::opcodeJAL(const Instruction& instruction) @@ -701,7 +701,7 @@ Cpu::InstructionType Cpu::opcodeJAL(const Instruction& instruction) m_branch = true; - return INSTRUCTION_TYPE_JAL; + return InstructionType::INSTRUCTION_TYPE_JAL; } Cpu::InstructionType Cpu::opcodeANDI(const Instruction& instruction) @@ -710,7 +710,7 @@ Cpu::InstructionType Cpu::opcodeANDI(const Instruction& instruction) RegisterIndex registerTargetIndex = instruction.getRegisterTargetIndex(); setRegisterValue(registerTargetIndex, getRegisterValue(registerSourceIndex) & instruction.getImmediateValue()); - return INSTRUCTION_TYPE_ANDI; + return InstructionType::INSTRUCTION_TYPE_ANDI; } Cpu::InstructionType Cpu::opcodeSB(const Instruction& instruction) @@ -722,7 +722,7 @@ Cpu::InstructionType Cpu::opcodeSB(const Instruction& instruction) store(addr, getRegisterValue(registerTargetIndex)); - return INSTRUCTION_TYPE_SB; + return InstructionType::INSTRUCTION_TYPE_SB; } Cpu::InstructionType Cpu::opcodeJR(const Instruction& instruction) @@ -730,7 +730,7 @@ Cpu::InstructionType Cpu::opcodeJR(const Instruction& instruction) //m_pc = getRegisterValue(instruction.getRegisterSourceIndex()); m_nextPc = getRegisterValue(instruction.getRegisterSourceIndex()); m_branch = true; - return INSTRUCTION_TYPE_JR; + return InstructionType::INSTRUCTION_TYPE_JR; } Cpu::InstructionType Cpu::opcodeLB(const Instruction& instruction) @@ -742,16 +742,16 @@ Cpu::InstructionType Cpu::opcodeLB(const Instruction& instruction) Instruction instructionLoaded = load(addr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; int8_t register8Bit = (uint8_t)instructionLoaded.getInstructionOpcode(); m_load = RegisterData(registerTargetIndex, (uint32_t)register8Bit); - return INSTRUCTION_TYPE_LB; + return InstructionType::INSTRUCTION_TYPE_LB; } Cpu::InstructionType Cpu::opcodeBEQ(const Instruction& instruction) @@ -759,7 +759,7 @@ Cpu::InstructionType Cpu::opcodeBEQ(const Instruction& instruction) if (getRegisterValue(instruction.getRegisterSourceIndex()) == getRegisterValue(instruction.getRegisterTargetIndex())) branch(instruction.getSignExtendedImmediateValue()); - return INSTRUCTION_TYPE_BEQ; + return InstructionType::INSTRUCTION_TYPE_BEQ; } Cpu::InstructionType Cpu::opcodeADD(const Instruction& instruction) @@ -772,14 +772,14 @@ Cpu::InstructionType Cpu::opcodeADD(const Instruction& instruction) { LOG("ADD overflow"); exception(Exception::EXCEPTION_OVERFLOW); - return INSTRUCTION_TYPE_OVERFLOW; + return InstructionType::INSTRUCTION_TYPE_OVERFLOW; } else { setRegisterValue(instruction.getRegisterDestinationIndex(), uint32_t(registerSourceValue + registerTargetValue)); } - return INSTRUCTION_TYPE_ADD; + return InstructionType::INSTRUCTION_TYPE_ADD; } Cpu::InstructionType Cpu::opcodeBGTZ(const Instruction& instruction) @@ -791,7 +791,7 @@ Cpu::InstructionType Cpu::opcodeBGTZ(const Instruction& instruction) if (registerSourceValue > 0) branch(signExtendedImmediateValue); - return INSTRUCTION_TYPE_BGTZ; + return InstructionType::INSTRUCTION_TYPE_BGTZ; } Cpu::InstructionType Cpu::opcodeBLEZ(const Instruction& instruction) @@ -803,7 +803,7 @@ Cpu::InstructionType Cpu::opcodeBLEZ(const Instruction& instruction) if (registerSourceValue <= 0) branch(signExtendedImmediateValue); - return INSTRUCTION_TYPE_BLEZ; + return InstructionType::INSTRUCTION_TYPE_BLEZ; } Cpu::InstructionType Cpu::opcodeLBU(const Instruction& instruction) @@ -815,15 +815,15 @@ Cpu::InstructionType Cpu::opcodeLBU(const Instruction& instruction) Instruction instructionLoaded = load(addr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; m_load = RegisterData(registerTargetIndex, instructionLoaded.getInstructionOpcode()); - return INSTRUCTION_TYPE_LBU; + return InstructionType::INSTRUCTION_TYPE_LBU; } Cpu::InstructionType Cpu::opcodeJALR(const Instruction& instruction) @@ -837,7 +837,7 @@ Cpu::InstructionType Cpu::opcodeJALR(const Instruction& instruction) m_branch = true; - return INSTRUCTION_TYPE_JALR; + return InstructionType::INSTRUCTION_TYPE_JALR; } Cpu::InstructionType Cpu::opcodeBXX(const Instruction& instruction) @@ -867,7 +867,7 @@ Cpu::InstructionType Cpu::opcodeBXX(const Instruction& instruction) branch(signExtendedImmediateValue); } - return INSTRUCTION_TYPE_BXX; + return InstructionType::INSTRUCTION_TYPE_BXX; } Cpu::InstructionType Cpu::opcodeSLTI(const Instruction& instruction) @@ -877,7 +877,7 @@ Cpu::InstructionType Cpu::opcodeSLTI(const Instruction& instruction) setRegisterValue(instruction.getRegisterTargetIndex(), registerSourceValue < signExtendedImmediateValue); - return INSTRUCTION_TYPE_SLTI; + return InstructionType::INSTRUCTION_TYPE_SLTI; } Cpu::InstructionType Cpu::opcodeSUBU(const Instruction& instruction) @@ -887,7 +887,7 @@ Cpu::InstructionType Cpu::opcodeSUBU(const Instruction& instruction) setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(registerSourceIndex) - getRegisterValue(registerTargetIndex)); - return INSTRUCTION_TYPE_SUBU; + return InstructionType::INSTRUCTION_TYPE_SUBU; } Cpu::InstructionType Cpu::opcodeSRA(const Instruction& instruction) @@ -896,7 +896,7 @@ Cpu::InstructionType Cpu::opcodeSRA(const Instruction& instruction) setRegisterValue(instruction.getRegisterDestinationIndex(), (uint32_t)rightShiftedValue); - return INSTRUCTION_TYPE_SRA; + return InstructionType::INSTRUCTION_TYPE_SRA; } Cpu::InstructionType Cpu::opcodeDIV(const Instruction& instruction) @@ -922,25 +922,25 @@ Cpu::InstructionType Cpu::opcodeDIV(const Instruction& instruction) m_lo = numerator / denominator; } - return INSTRUCTION_TYPE_DIV; + return InstructionType::INSTRUCTION_TYPE_DIV; } Cpu::InstructionType Cpu::opcodeMFLO(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), m_lo); - return INSTRUCTION_TYPE_MFLO; + return InstructionType::INSTRUCTION_TYPE_MFLO; } Cpu::InstructionType Cpu::opcodeSRL(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(instruction.getRegisterTargetIndex()) >> instruction.getShiftImmediateValue()); - return INSTRUCTION_TYPE_SRL; + return InstructionType::INSTRUCTION_TYPE_SRL; } Cpu::InstructionType Cpu::opcodeSLTIU(const Instruction& instruction) { setRegisterValue(instruction.getRegisterTargetIndex(), getRegisterValue(instruction.getRegisterSourceIndex()) < instruction.getSignExtendedImmediateValue()); - return INSTRUCTION_TYPE_SLTIU; + return InstructionType::INSTRUCTION_TYPE_SLTIU; } Cpu::InstructionType Cpu::opcodeDIVU(const Instruction& instruction) @@ -960,19 +960,19 @@ Cpu::InstructionType Cpu::opcodeDIVU(const Instruction& instruction) m_lo = numerator / denominator; } - return INSTRUCTION_TYPE_DIVU; + return InstructionType::INSTRUCTION_TYPE_DIVU; } Cpu::InstructionType Cpu::opcodeSLT(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), (int32_t)getRegisterValue(instruction.getRegisterSourceIndex()) < (int32_t)getRegisterValue(instruction.getRegisterTargetIndex())); - return INSTRUCTION_TYPE_SLT; + return InstructionType::INSTRUCTION_TYPE_SLT; } Cpu::InstructionType Cpu::opcodeMFHI(const Instruction& instruction) { setRegisterValue(instruction.getRegisterDestinationIndex(), m_hi); - return INSTRUCTION_TYPE_MFHI; + return InstructionType::INSTRUCTION_TYPE_MFHI; } void Cpu::exception(Exception cause) @@ -987,20 +987,21 @@ void Cpu::exception(Exception cause) Cpu::InstructionType Cpu::opcodeSYSCALL(const Instruction& instruction) { + PCSX_UNUSED(instruction); exception(Exception::EXCEPTION_SYSCALL); - return INSTRUCTION_TYPE_SYSCALL; + return InstructionType::INSTRUCTION_TYPE_SYSCALL; } Cpu::InstructionType Cpu::opcodeMTLO(const Instruction& instruction) { m_lo = getRegisterValue(instruction.getRegisterSourceIndex()); - return INSTRUCTION_TYPE_MTLO; + return InstructionType::INSTRUCTION_TYPE_MTLO; } Cpu::InstructionType Cpu::opcodeMTHI(const Instruction& instruction) { m_hi = getRegisterValue(instruction.getRegisterSourceIndex()); - return INSTRUCTION_TYPE_MTHI; + return InstructionType::INSTRUCTION_TYPE_MTHI; } Cpu::InstructionType Cpu::opcodeRFE(const Instruction& instruction) @@ -1011,12 +1012,12 @@ Cpu::InstructionType Cpu::opcodeRFE(const Instruction& instruction) if ((instruction.getInstructionOpcode() & 0x3f) != 0b010000) { LOG("Invalid cop 0 instruction:" << std::hex << instruction.getInstructionOpcode()); - return INSTRUCTION_TYPE_UNKNOWN; + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; } m_cop0.returnFromException(); - return INSTRUCTION_TYPE_RFE; + return InstructionType::INSTRUCTION_TYPE_RFE; } Cpu::InstructionType Cpu::opcodeLHU(const Instruction& instruction) @@ -1032,10 +1033,10 @@ Cpu::InstructionType Cpu::opcodeLHU(const Instruction& instruction) else { exception(Exception::EXCEPTION_LOAD_ADDRESS_ERROR); - return INSTRUCTION_TYPE_UNALIGNED; + return InstructionType::INSTRUCTION_TYPE_UNALIGNED; } - return INSTRUCTION_TYPE_LHU; + return InstructionType::INSTRUCTION_TYPE_LHU; } Cpu::InstructionType Cpu::opcodeSLLV(const Instruction& instruction) @@ -1045,7 +1046,7 @@ Cpu::InstructionType Cpu::opcodeSLLV(const Instruction& instruction) // Shift amount is truncated to 5 bits setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(registerTargetIndex) << (getRegisterValue(registerSourceIndex) & 0x1f)); - return INSTRUCTION_TYPE_SLLV; + return InstructionType::INSTRUCTION_TYPE_SLLV; } Cpu::InstructionType Cpu::opcodeLH(const Instruction& instruction) @@ -1059,17 +1060,17 @@ Cpu::InstructionType Cpu::opcodeLH(const Instruction& instruction) // Cast as i16 to force sign extension Instruction instructionLoaded = load(addr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; int16_t instructionOpcode = instructionLoaded.getInstructionOpcode(); // Put the load in the delay slot m_load = RegisterData(registerTargetIndex, instructionOpcode); - return INSTRUCTION_TYPE_LH; + return InstructionType::INSTRUCTION_TYPE_LH; } Cpu::InstructionType Cpu::opcodeNOR(const Instruction& instruction) @@ -1078,7 +1079,7 @@ Cpu::InstructionType Cpu::opcodeNOR(const Instruction& instruction) RegisterIndex registerTargetIndex = instruction.getRegisterTargetIndex(); setRegisterValue(instruction.getRegisterDestinationIndex(), ~(getRegisterValue(registerSourceIndex) | getRegisterValue(registerTargetIndex))); - return INSTRUCTION_TYPE_NOR; + return InstructionType::INSTRUCTION_TYPE_NOR; } Cpu::InstructionType Cpu::opcodeSRAV(const Instruction& instruction) @@ -1088,7 +1089,7 @@ Cpu::InstructionType Cpu::opcodeSRAV(const Instruction& instruction) // Shift amount is truncated to 5 bits setRegisterValue(instruction.getRegisterDestinationIndex(), ((int32_t)getRegisterValue(registerTargetIndex)) >> (getRegisterValue(registerSourceIndex) & 0x1f)); - return INSTRUCTION_TYPE_SRAV; + return InstructionType::INSTRUCTION_TYPE_SRAV; } Cpu::InstructionType Cpu::opcodeSRLV(const Instruction& instruction) @@ -1098,7 +1099,7 @@ Cpu::InstructionType Cpu::opcodeSRLV(const Instruction& instruction) // Shift amount is truncated to 5 bits setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(registerTargetIndex) >> (getRegisterValue(registerSourceIndex) & 0x1f)); - return INSTRUCTION_TYPE_SRLV; + return InstructionType::INSTRUCTION_TYPE_SRLV; } Cpu::InstructionType Cpu::opcodeMULTU(const Instruction& instruction) @@ -1114,7 +1115,7 @@ Cpu::InstructionType Cpu::opcodeMULTU(const Instruction& instruction) m_hi = (multResult >> 32); m_lo = (uint32_t)multResult; - return INSTRUCTION_TYPE_MULTU; + return InstructionType::INSTRUCTION_TYPE_MULTU; } Cpu::InstructionType Cpu::opcodeXOR(const Instruction& instruction) @@ -1123,13 +1124,14 @@ Cpu::InstructionType Cpu::opcodeXOR(const Instruction& instruction) RegisterIndex registerTargetIndex = instruction.getRegisterTargetIndex(); setRegisterValue(instruction.getRegisterDestinationIndex(), getRegisterValue(registerSourceIndex) ^ getRegisterValue(registerTargetIndex)); - return INSTRUCTION_TYPE_XOR; + return InstructionType::INSTRUCTION_TYPE_XOR; } Cpu::InstructionType Cpu::opcodeBREAK(const Instruction& instruction) { + PCSX_UNUSED(instruction); exception(Exception::EXCEPTION_BREAK); - return INSTRUCTION_TYPE_BREAK; + return InstructionType::INSTRUCTION_TYPE_BREAK; } Cpu::InstructionType Cpu::opcodeMULT(const Instruction& instruction) @@ -1145,7 +1147,7 @@ Cpu::InstructionType Cpu::opcodeMULT(const Instruction& instruction) m_hi = (multResult >> 32); m_lo = (uint32_t)multResult; - return INSTRUCTION_TYPE_MULT; + return InstructionType::INSTRUCTION_TYPE_MULT; } Cpu::InstructionType Cpu::opcodeSUB(const Instruction& instruction) @@ -1168,7 +1170,7 @@ Cpu::InstructionType Cpu::opcodeSUB(const Instruction& instruction) setRegisterValue(instruction.getRegisterDestinationIndex(), registerSourceValue - registerTargetValue); //} - return INSTRUCTION_TYPE_SUB; + return InstructionType::INSTRUCTION_TYPE_SUB; } Cpu::InstructionType Cpu::opcodeXORI(const Instruction& instruction) @@ -1177,18 +1179,19 @@ Cpu::InstructionType Cpu::opcodeXORI(const Instruction& instruction) RegisterIndex registerTargetIndex = instruction.getRegisterTargetIndex(); setRegisterValue(registerTargetIndex, getRegisterValue(registerSourceIndex) ^ instruction.getImmediateValue()); - return INSTRUCTION_TYPE_XORI; + return InstructionType::INSTRUCTION_TYPE_XORI; } Cpu::InstructionType Cpu::opcodeCOP1(const Instruction& instruction) { + PCSX_UNUSED(instruction); exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_COP1; + return InstructionType::INSTRUCTION_TYPE_COP1; } Cpu::InstructionType Cpu::opcodeCOP2(const Instruction& instruction) { - InstructionType instructionType = INSTRUCTION_TYPE_UNKNOWN; + InstructionType instructionType{ InstructionType::INSTRUCTION_TYPE_UNKNOWN }; uint32_t copOpcode = instruction.getCopOpcodeValue(); @@ -1196,7 +1199,7 @@ Cpu::InstructionType Cpu::opcodeCOP2(const Instruction& instruction) { // GTE command. m_gte.command(instruction.getInstructionOpcode()); - instructionType = INSTRUCTION_TYPE_GTE_COMMAND; + instructionType = InstructionType::INSTRUCTION_TYPE_GTE_COMMAND; } else { @@ -1237,13 +1240,14 @@ Cpu::InstructionType Cpu::opcodeCTC2(const Instruction& instruction) uint32_t copRegister = instruction.getRegisterDestinationIndex().getRegisterIndex(); m_gte.setControl(copRegister, getRegisterValue(cpuRegisterIndex)); - return INSTRUCTION_TYPE_CTC2; + return InstructionType::INSTRUCTION_TYPE_CTC2; } Cpu::InstructionType Cpu::opcodeCOP3(const Instruction& instruction) { + PCSX_UNUSED(instruction); exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_COP3; + return InstructionType::INSTRUCTION_TYPE_COP3; } Cpu::InstructionType Cpu::opcodeLWL(const Instruction& instruction) @@ -1263,11 +1267,11 @@ Cpu::InstructionType Cpu::opcodeLWL(const Instruction& instruction) Instruction instructionLoaded = load(alignedAddr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; uint32_t alignedWord = instructionLoaded.getInstructionOpcode(); @@ -1292,7 +1296,7 @@ Cpu::InstructionType Cpu::opcodeLWL(const Instruction& instruction) // Put the load in the delay slot m_load = RegisterData(registerTargetIndex, alignedValue); - return INSTRUCTION_TYPE_LWL; + return InstructionType::INSTRUCTION_TYPE_LWL; } Cpu::InstructionType Cpu::opcodeLWR(const Instruction& instruction) @@ -1312,11 +1316,11 @@ Cpu::InstructionType Cpu::opcodeLWR(const Instruction& instruction) Instruction instructionLoaded = load(alignedAddr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; uint32_t alignedWord = instructionLoaded.getInstructionOpcode(); @@ -1341,7 +1345,7 @@ Cpu::InstructionType Cpu::opcodeLWR(const Instruction& instruction) // Put the load in the delay slot m_load = RegisterData(registerTargetIndex, alignedValue); - return INSTRUCTION_TYPE_LWR; + return InstructionType::INSTRUCTION_TYPE_LWR; } Cpu::InstructionType Cpu::opcodeSWL(const Instruction& instruction) @@ -1358,11 +1362,11 @@ Cpu::InstructionType Cpu::opcodeSWL(const Instruction& instruction) // Load the current value for the aligned word at the target address Instruction instructionLoaded = load(alignedAddr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; uint32_t currentMem = instructionLoaded.getInstructionOpcode(); @@ -1384,7 +1388,7 @@ Cpu::InstructionType Cpu::opcodeSWL(const Instruction& instruction) } store(alignedAddr, mem); - return INSTRUCTION_TYPE_SWL; + return InstructionType::INSTRUCTION_TYPE_SWL; } Cpu::InstructionType Cpu::opcodeSWR(const Instruction& instruction) @@ -1401,11 +1405,11 @@ Cpu::InstructionType Cpu::opcodeSWR(const Instruction& instruction) // Load the current value for the aligned word at the target address Instruction instructionLoaded = load(alignedAddr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; uint32_t currentMem = instructionLoaded.getInstructionOpcode(); @@ -1427,21 +1431,23 @@ Cpu::InstructionType Cpu::opcodeSWR(const Instruction& instruction) } store(alignedAddr, mem); - return INSTRUCTION_TYPE_SWR; + return InstructionType::INSTRUCTION_TYPE_SWR; } Cpu::InstructionType Cpu::opcodeLWC0(const Instruction& instruction) { + PCSX_UNUSED(instruction); // Not supported by this coprocessor exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_LWC0; + return InstructionType::INSTRUCTION_TYPE_LWC0; } Cpu::InstructionType Cpu::opcodeLWC1(const Instruction& instruction) { + PCSX_UNUSED(instruction); // Not supported by this coprocessor exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_LWC1; + return InstructionType::INSTRUCTION_TYPE_LWC1; } Cpu::InstructionType Cpu::opcodeLWC2(const Instruction& instruction) @@ -1453,11 +1459,11 @@ Cpu::InstructionType Cpu::opcodeLWC2(const Instruction& instruction) { Instruction instructionLoaded = load(addr); Instruction::InstructionStatus instructionStatus = instructionLoaded.getInstructionStatus(); - if (instructionStatus == Instruction::INSTRUCTION_STATUS_UNALIGNED_ACCESS || - instructionStatus == Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH) - return INSTRUCTION_TYPE_UNKNOWN; - if (instructionStatus == Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED) - return INSTRUCTION_TYPE_NOT_IMPLEMENTED; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNALIGNED_ACCESS || + instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH) + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; + if (instructionStatus == Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED) + return InstructionType::INSTRUCTION_TYPE_NOT_IMPLEMENTED; // Send to coprocessor. m_gte.setData(instruction.getRegisterTargetIndex().getRegisterIndex(), instructionLoaded.getInstructionOpcode()); @@ -1467,28 +1473,31 @@ Cpu::InstructionType Cpu::opcodeLWC2(const Instruction& instruction) exception(Exception::EXCEPTION_LOAD_ADDRESS_ERROR); } - return INSTRUCTION_TYPE_LWC2; + return InstructionType::INSTRUCTION_TYPE_LWC2; } Cpu::InstructionType Cpu::opcodeLWC3(const Instruction& instruction) { + PCSX_UNUSED(instruction); // Not supported by this coprocessor exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_LWC3; + return InstructionType::INSTRUCTION_TYPE_LWC3; } Cpu::InstructionType Cpu::opcodeSWC0(const Instruction& instruction) { + PCSX_UNUSED(instruction); // Not supported by this coprocessor exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_SWC0; + return InstructionType::INSTRUCTION_TYPE_SWC0; } Cpu::InstructionType Cpu::opcodeSWC1(const Instruction& instruction) { + PCSX_UNUSED(instruction); // Not supported by this coprocessor exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_SWC1; + return InstructionType::INSTRUCTION_TYPE_SWC1; } Cpu::InstructionType Cpu::opcodeSWC2(const Instruction& instruction) @@ -1502,39 +1511,41 @@ Cpu::InstructionType Cpu::opcodeSWC2(const Instruction& instruction) else exception(Exception::EXCEPTION_LOAD_ADDRESS_ERROR); - return INSTRUCTION_TYPE_SWC2; + return InstructionType::INSTRUCTION_TYPE_SWC2; } Cpu::InstructionType Cpu::opcodeSWC3(const Instruction& instruction) { + PCSX_UNUSED(instruction); // Not supported by this coprocessor exception(Exception::EXCEPTION_COPROCESSOR_ERROR); - return INSTRUCTION_TYPE_SWC3; + return InstructionType::INSTRUCTION_TYPE_SWC3; } Cpu::InstructionType Cpu::opcodeMFC2(const Instruction& instruction) { m_load = RegisterData(instruction.getRegisterTargetIndex(), m_gte.getData(instruction.getRegisterDestinationIndex().getRegisterIndex())); - return INSTRUCTION_TYPE_MFC2; + return InstructionType::INSTRUCTION_TYPE_MFC2; } Cpu::InstructionType Cpu::opcodeCFC2(const Instruction& instruction) { m_load = RegisterData(instruction.getRegisterTargetIndex(), m_gte.getControl(instruction.getRegisterDestinationIndex().getRegisterIndex())); - return INSTRUCTION_TYPE_CFC2; + return InstructionType::INSTRUCTION_TYPE_CFC2; } Cpu::InstructionType Cpu::opcodeMTC2(const Instruction& instruction) { m_gte.setData(instruction.getRegisterDestinationIndex().getRegisterIndex(), getRegisterValue(instruction.getRegisterTargetIndex())); - return INSTRUCTION_TYPE_MTC2; + return InstructionType::INSTRUCTION_TYPE_MTC2; } Cpu::InstructionType Cpu::opcodeIllegal(const Instruction& instruction) { + PCSX_UNUSED(instruction); LOG("Illegal instruction 0x" << std::hex << instruction.getInstructionOpcode()); exception(Exception::EXCEPTION_UNKNOWN_INSTRUCTION); - return INSTRUCTION_TYPE_UNKNOWN; + return InstructionType::INSTRUCTION_TYPE_UNKNOWN; } uint32_t Cpu::getRegisterValue(RegisterIndex registerIndex) const diff --git a/pscx_emulator/pscx_cpu.h b/pscx_emulator/pscx_cpu.h index b7f9610..3992c59 100644 --- a/pscx_emulator/pscx_cpu.h +++ b/pscx_emulator/pscx_cpu.h @@ -40,7 +40,7 @@ struct Cpu m_outRegs[0] = 0x0; } - enum InstructionType + enum class InstructionType { INSTRUCTION_TYPE_LUI, INSTRUCTION_TYPE_ORI, @@ -132,7 +132,7 @@ struct Cpu const uint32_t* getRegistersPtr() const; const std::vector& getInstructionsDump() const; - std::vector getPadProfiles(); + std::vector getPadProfiles() const; private: struct RegisterData diff --git a/pscx_emulator/pscx_disc.h b/pscx_emulator/pscx_disc.h index 222a307..fcf17ed 100644 --- a/pscx_emulator/pscx_disc.h +++ b/pscx_emulator/pscx_disc.h @@ -35,7 +35,7 @@ struct XaSector // Return payload data byte at "index". uint8_t getDataByte(uint16_t index) const; - enum XaSectorStatus + enum class XaSectorStatus { XA_SECTOR_STATUS_OK, XA_SECTOR_STATUS_INVALID_DATA, @@ -95,7 +95,7 @@ struct Disc { Disc(std::ifstream&& file, Region region); - enum DiscStatus + enum class DiscStatus { DISC_STATUS_OK, DISC_STATUS_INVALID_PATH, diff --git a/pscx_emulator/pscx_dma.cpp b/pscx_emulator/pscx_dma.cpp index fe4661c..62a1b11 100644 --- a/pscx_emulator/pscx_dma.cpp +++ b/pscx_emulator/pscx_dma.cpp @@ -80,15 +80,15 @@ uint32_t Channel::getDmaChannelControlRegister() const { uint32_t channelControlRegister = 0; - channelControlRegister |= m_direction; - channelControlRegister |= ((uint32_t)m_step) << 1; - channelControlRegister |= ((uint32_t)m_chop) << 8; - channelControlRegister |= ((uint32_t)m_sync) << 9; - channelControlRegister |= ((uint32_t)m_chopDmaWindowSize) << 16; - channelControlRegister |= ((uint32_t)m_chopCpuWindowSize) << 20; - channelControlRegister |= ((uint32_t)m_enable) << 24; - channelControlRegister |= ((uint32_t)m_trigger) << 28; - channelControlRegister |= ((uint32_t)m_dummy) << 29; + channelControlRegister |= static_cast(m_direction); + channelControlRegister |= static_cast(m_step) << 1; + channelControlRegister |= static_cast(m_chop) << 8; + channelControlRegister |= static_cast(m_sync) << 9; + channelControlRegister |= static_cast(m_chopDmaWindowSize) << 16; + channelControlRegister |= static_cast(m_chopCpuWindowSize) << 20; + channelControlRegister |= static_cast(m_enable) << 24; + channelControlRegister |= static_cast(m_trigger) << 28; + channelControlRegister |= static_cast(m_dummy) << 29; return channelControlRegister; } @@ -139,7 +139,7 @@ uint32_t Channel::getBlockControlRegister() const uint32_t blockSize = m_blockSize; uint32_t blockCount = m_blockCount; - return (blockSize << 16) | blockSize; + return (blockCount << 16) | blockSize; } void Channel::setBlockControlRegister(uint32_t value) diff --git a/pscx_emulator/pscx_gamepad.cpp b/pscx_emulator/pscx_gamepad.cpp index 51e25ec..340b428 100644 --- a/pscx_emulator/pscx_gamepad.cpp +++ b/pscx_emulator/pscx_gamepad.cpp @@ -1,7 +1,9 @@ #include "pscx_gamepad.h" +#include "pscx_common.h" // ********************** GamePad implementation ********************** GamePad::GamePad(Type padType) : + m_profile(nullptr), m_seq(0x0), m_active(true) { @@ -38,20 +40,22 @@ std::pair GamePad::sendCommand(uint8_t cmd) return command; } -Profile& GamePad::getProfile() +Profile* GamePad::getProfile() const { - return *m_profile; + return m_profile; } // ********************** DisconnectedProfile implementation ********************** std::pair DisconnectedProfile::handleCommand(uint8_t seq, uint8_t cmd) { - // The bus is open, no respomse + PCSX_UNUSED(seq, cmd); + // The bus is open, no response return std::make_pair(0xff, false); } void DisconnectedProfile::setButtonState(Button button, ButtonState state) { + PCSX_UNUSED(button, state); // Dummy function } diff --git a/pscx_emulator/pscx_gamepad.h b/pscx_emulator/pscx_gamepad.h index 48f6df5..ff83d73 100644 --- a/pscx_emulator/pscx_gamepad.h +++ b/pscx_emulator/pscx_gamepad.h @@ -3,7 +3,7 @@ #include // GamePad types supported by the emulator -enum Type +enum class Type { // No gamepad connected TYPE_DISCONNECTED, @@ -29,7 +29,7 @@ enum Button BUTTON_SQUARE = 15 }; -enum ButtonState +enum class ButtonState { BUTTON_STATE_PRESSED, BUTTON_STATE_RELEASED @@ -80,7 +80,7 @@ struct GamePad std::pair sendCommand(uint8_t cmd); // Return a mutable reference to the underlying gamepad Profile - Profile& getProfile(); + Profile* getProfile() const; private: // Gamepad profile diff --git a/pscx_emulator/pscx_gpu.cpp b/pscx_emulator/pscx_gpu.cpp index 5436666..9987df6 100644 --- a/pscx_emulator/pscx_gpu.cpp +++ b/pscx_emulator/pscx_gpu.cpp @@ -343,7 +343,7 @@ void Gpu::gp0(uint32_t value) void(Gpu::*gp0CommandMethod)(void); }; - CommandParameters commandParameters; + CommandParameters commandParameters{}; switch (opcode) { case 0x0: @@ -902,6 +902,7 @@ void Gpu::gp0ImageStore() uint32_t width = imageResolution & 0xffff; uint32_t height = imageResolution >> 16; + PCSX_UNUSED(width, height); LOG("Unhandled image store 0x" << width << " 0x" << height); } @@ -1104,7 +1105,7 @@ void Gpu::gp1DisplayMode(uint32_t value, TimeKeeper& timeKeeper, InterruptState& if (value & 0x80) { - LOG("Unsupported display mode 0x" << std::hex << val); + LOG("Unsupported display mode 0x" << std::hex << value); } sync(timeKeeper, irqState); diff --git a/pscx_emulator/pscx_gpu.h b/pscx_emulator/pscx_gpu.h index 3e46728..445dcb3 100644 --- a/pscx_emulator/pscx_gpu.h +++ b/pscx_emulator/pscx_gpu.h @@ -10,7 +10,7 @@ //const Cycles CLOCK_RATIO_FRAC = 0x10000; // Depth of the pixel values in a texture page -enum TextureDepth +enum class TextureDepth { // 4 bits per pixel TEXTURE_DEPTH_4_BIT, @@ -23,7 +23,7 @@ enum TextureDepth }; // Interlaced output splits each frame in two fields -enum Field +enum class Field { // Top Field ( odd lines ) FIELD_TOP = 1, @@ -97,7 +97,7 @@ struct HorizontalRes }; // Video output vertical resolution -enum VerticalRes +enum class VerticalRes { // 240 lines VERTICAL_RES_240_LINES, @@ -107,7 +107,7 @@ enum VerticalRes }; // Video modes -enum VMode +enum class VMode { // NTSC: 480i60Hz VMODE_NTSC, @@ -117,7 +117,7 @@ enum VMode }; // Display area color depth -enum DisplayDepth +enum class DisplayDepth { // 15 bits per pixel DISPLAY_DEPTH_15_BITS, @@ -127,7 +127,7 @@ enum DisplayDepth }; // Requested DMA direction -enum DmaDirection +enum class DmaDirection { DMA_DIRECTION_OFF, DMA_DIRECTION_FIFO, @@ -137,7 +137,7 @@ enum DmaDirection // There are a few hardware differences between PAL and NTSC consoles, // for instance runs slightly slower on PAL consoles. -enum HardwareType +enum class HardwareType { HARDWARE_TYPE_NTSC, HARDWARE_TYPE_PAL @@ -180,7 +180,7 @@ struct CommandBuffer }; // Possible states for the GP0 command register -enum Gp0Mode +enum class Gp0Mode { // Default mode: handling commands GP0_MODE_COMMAND, diff --git a/pscx_emulator/pscx_gte.cpp b/pscx_emulator/pscx_gte.cpp index 5f3f751..e01f895 100644 --- a/pscx_emulator/pscx_gte.cpp +++ b/pscx_emulator/pscx_gte.cpp @@ -6,7 +6,7 @@ Matrix fromMatrixCommand(uint32_t command) { - Matrix matrix; + Matrix matrix{ Matrix::MATRIX_ROTATION }; switch ((command >> 17) & 3) { case 0: @@ -27,7 +27,7 @@ Matrix fromMatrixCommand(uint32_t command) ControlVector fromControlVectorCommand(uint32_t command) { - ControlVector controlVector; + ControlVector controlVector{ ControlVector::CONTROL_VECTOR_TRANSLATION }; switch ((command >> 13) & 3) { case 0: diff --git a/pscx_emulator/pscx_instruction.h b/pscx_emulator/pscx_instruction.h index 22242f7..208f61e 100644 --- a/pscx_emulator/pscx_instruction.h +++ b/pscx_emulator/pscx_instruction.h @@ -7,7 +7,7 @@ using namespace pscx_memory; struct Instruction { - enum InstructionStatus + enum class InstructionStatus { INSTRUCTION_STATUS_LOADED_SUCCESSFULLY, INSTRUCTION_STATUS_NOT_IMPLEMENTED, @@ -16,8 +16,8 @@ struct Instruction INSTRUCTION_STATUS_COUNT }; - Instruction() : m_instruction(0x0), m_instructionStatus(INSTRUCTION_STATUS_LOADED_SUCCESSFULLY) {}; - Instruction(uint32_t opcode, InstructionStatus instructionStatus = INSTRUCTION_STATUS_LOADED_SUCCESSFULLY) : m_instruction(opcode), m_instructionStatus(instructionStatus) {} + Instruction() : m_instruction(0x0), m_instructionStatus(InstructionStatus::INSTRUCTION_STATUS_LOADED_SUCCESSFULLY) {}; + Instruction(uint32_t opcode, InstructionStatus instructionStatus = InstructionStatus::INSTRUCTION_STATUS_LOADED_SUCCESSFULLY) : m_instruction(opcode), m_instructionStatus(instructionStatus) {} // Return bits [31:26] of the instruction uint32_t getInstructionCode() const; diff --git a/pscx_emulator/pscx_interconnect.cpp b/pscx_emulator/pscx_interconnect.cpp index 12f11da..2cce189 100644 --- a/pscx_emulator/pscx_interconnect.cpp +++ b/pscx_emulator/pscx_interconnect.cpp @@ -3,7 +3,7 @@ #include "pscx_interconnect.h" -Interconnect::Interconnect(Bios bios, HardwareType hardwareType, const Disc* disc) : +Interconnect::Interconnect(const Bios& bios, HardwareType hardwareType, const Disc* disc) : m_irqState(new InterruptState), m_bios(new Bios(bios)), m_ram(new Ram), @@ -71,7 +71,7 @@ Instruction Interconnect::load(TimeKeeper& timeKeeper, uint32_t addr) if (EXPANSION_2.contains(targetPeripheralAddress, offset)) { - return Instruction(~0, Instruction::INSTRUCTION_STATUS_NOT_IMPLEMENTED); + return Instruction(~0, Instruction::InstructionStatus::INSTRUCTION_STATUS_NOT_IMPLEMENTED); } if (IRQ_CONTROL.contains(targetPeripheralAddress, offset)) @@ -81,7 +81,7 @@ Instruction Interconnect::load(TimeKeeper& timeKeeper, uint32_t addr) { irqControlValue = m_irqState->getInterruptStatus(); } - else if (offset = 0x4) + else if (offset == 0x4) { irqControlValue = m_irqState->getInterruptMask(); } @@ -119,7 +119,7 @@ Instruction Interconnect::load(TimeKeeper& timeKeeper, uint32_t addr) } LOG("Unhandled fetch32 at address 0x" << std::hex << addr); - return Instruction(~0, Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH); + return Instruction(~0, Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH); } template Instruction Interconnect::load(TimeKeeper&, uint32_t); @@ -552,7 +552,7 @@ Instruction Interconnect::loadInstruction(uint32_t pc) } LOG("Unhandled instruction load at address 0x" << std::hex << pc); - return Instruction(~0, Instruction::INSTRUCTION_STATUS_UNHANDLED_FETCH); + return Instruction(~0, Instruction::InstructionStatus::INSTRUCTION_STATUS_UNHANDLED_FETCH); } template Instruction Interconnect::loadInstruction(uint32_t); @@ -562,7 +562,7 @@ InterruptState Interconnect::getIrqState() const return *m_irqState; } -std::vector Interconnect::getPadProfiles() +std::vector Interconnect::getPadProfiles() const { return m_padMemCard->getPadProfiles(); } diff --git a/pscx_emulator/pscx_interconnect.h b/pscx_emulator/pscx_interconnect.h index 732713c..8e60080 100644 --- a/pscx_emulator/pscx_interconnect.h +++ b/pscx_emulator/pscx_interconnect.h @@ -23,7 +23,7 @@ using namespace pscx_memory; // Global interconnect struct Interconnect { - Interconnect(Bios bios, HardwareType hardwareType, const Disc* disc); + Interconnect(const Bios& bios, HardwareType hardwareType, const Disc* disc); template Instruction load(TimeKeeper& timeKeeper, uint32_t addr); @@ -50,7 +50,7 @@ struct Interconnect InterruptState getIrqState() const; - std::vector getPadProfiles(); + std::vector getPadProfiles() const; private: diff --git a/pscx_emulator/pscx_interrupts.h b/pscx_emulator/pscx_interrupts.h index a9471e2..1dcf05f 100644 --- a/pscx_emulator/pscx_interrupts.h +++ b/pscx_emulator/pscx_interrupts.h @@ -1,10 +1,14 @@ #pragma once #include +#include // The Playstation supports 10 interrupts enum Interrupt { + // Incorrect interuption, in case if something goes wrong + INTERRUPT_NONE = INT_MIN, + // Display the vertical blanking INTERRUPT_VBLANK = 0, @@ -24,7 +28,7 @@ enum Interrupt INTERRUPT_TIMER2 = 6, // Gamepad and Memory Card controller interrupt - INTERRUPT_PAD_MEMCARD = 7 + INTERRUPT_PAD_MEMCARD = 7, }; struct InterruptState diff --git a/pscx_emulator/pscx_main.cpp b/pscx_emulator/pscx_main.cpp index bb0147c..03de67a 100644 --- a/pscx_emulator/pscx_main.cpp +++ b/pscx_emulator/pscx_main.cpp @@ -126,7 +126,7 @@ static SDL_GameController* initializeSDL2Controllers() SDL_GameController* controller = SDL_GameControllerOpen(joystickId); if (controller) { - LOG("Successfully opened " << SDL_GameControllerName(joystick)); + LOG("Successfully opened " << SDL_GameControllerName(controller)); initializedController = controller; break; } @@ -191,7 +191,7 @@ static void handleKeyboard(Profile* pad, SDL_Keycode keyCode, ButtonState state) pad->setButtonState(button, state); } -static void handleController(Profile* pad, SDL_ControllerButtonEvent& buttonEvent, ButtonState state) +static void handleController(Profile* pad, const SDL_ControllerButtonEvent& buttonEvent, ButtonState state) { // Map the playstation controller on the xbox360 one Button button; @@ -265,7 +265,7 @@ static void updateControllerAxis(Profile* pad, SDL_JoyAxisEvent& joyAxisEvent) } // Handle SDL events -static Action handleEvents(SDL_Event& event, Cpu& cpu) +static Action handleEvents(SDL_Event& event, const Cpu& cpu) { while (SDL_PollEvent(&event)) { @@ -350,10 +350,10 @@ int main(int argc, char** argv) switch (state) { - case Bios::BIOS_STATE_INCORRECT_FILENAME: + case Bios::BiosState::BIOS_STATE_INCORRECT_FILENAME: std::cout << "Can't find location of the bios " << biosPath << std::endl; return EXIT_FAILURE; - case Bios::BIOS_STATE_INVALID_BIOS_SIZE: + case Bios::BiosState::BIOS_STATE_INVALID_BIOS_SIZE: std::cout << "Invalid BIOS size " << biosPath << std::endl; return EXIT_FAILURE; } diff --git a/pscx_emulator/pscx_padmemcard.cpp b/pscx_emulator/pscx_padmemcard.cpp index c3c62bd..d800300 100644 --- a/pscx_emulator/pscx_padmemcard.cpp +++ b/pscx_emulator/pscx_padmemcard.cpp @@ -183,9 +183,9 @@ void PadMemCard::sync(TimeKeeper& timeKeeper, InterruptState& irqState) } } -std::vector PadMemCard::getPadProfiles() +std::vector PadMemCard::getPadProfiles() const { - std::vector padProfiles{ &m_pad1.getProfile(), &m_pad2.getProfile() }; + std::vector padProfiles{ m_pad1.getProfile(), m_pad2.getProfile() }; return padProfiles; } diff --git a/pscx_emulator/pscx_padmemcard.h b/pscx_emulator/pscx_padmemcard.h index d3b4d5b..f126a7c 100644 --- a/pscx_emulator/pscx_padmemcard.h +++ b/pscx_emulator/pscx_padmemcard.h @@ -9,14 +9,14 @@ #include "pscx_interrupts.h" // Identifies the tagret of the serial communication, either the gamepad/memory card port 0 or 1. -enum Target +enum class Target { TARGET_PAD_MEMCARD1 = 0, TARGET_PAD_MEMCARD2 = 1 }; // Controller transaction state machine. -enum BusState +enum class BusState { // Bus is idle. BUS_STATE_IDLE, @@ -42,7 +42,7 @@ struct PadMemCard void sync(TimeKeeper& timeKeeper, InterruptState& irqState); // Return a mutable reference to the gamepad profiles being used. - std::vector getPadProfiles(); + std::vector getPadProfiles() const; void sendCommand(TimeKeeper& timeKeeper, uint8_t cmd); diff --git a/pscx_emulator/pscx_timekeeper.cpp b/pscx_emulator/pscx_timekeeper.cpp index b4c8863..62d9264 100644 --- a/pscx_emulator/pscx_timekeeper.cpp +++ b/pscx_emulator/pscx_timekeeper.cpp @@ -33,13 +33,13 @@ void TimeKeeper::tick(Cycles cycles) Cycles TimeKeeper::sync(Peripheral who) { - return m_timesheets[who].sync(m_now); + return m_timesheets[getPeripheralCode(who)].sync(m_now); } void TimeKeeper::setNextSyncDelta(Peripheral who, Cycles delta) { Cycles date = m_now + delta; - m_timesheets[who].setNextSync(date); + m_timesheets[getPeripheralCode(who)].setNextSync(date); if (date < m_nextSync) { @@ -50,9 +50,9 @@ void TimeKeeper::setNextSyncDelta(Peripheral who, Cycles delta) void TimeKeeper::setNextSyncDeltaIfCloser(Peripheral who, Cycles delta) { Cycles date = m_now + delta; - if (m_timesheets[who].getNextSync() > date) + if (m_timesheets[getPeripheralCode(who)].getNextSync() > date) { - m_timesheets[who].setNextSync(date); + m_timesheets[getPeripheralCode(who)].setNextSync(date); } } @@ -60,7 +60,7 @@ void TimeKeeper::noSyncNeeded(Peripheral who) { // Insted of sisabling the sync completely we can just use a distant date. // Peripheral's syncs should be idempotent. - m_timesheets[who].setNextSync(ULLONG_MAX); + m_timesheets[getPeripheralCode(who)].setNextSync(ULLONG_MAX); } bool TimeKeeper::syncPending() const @@ -70,7 +70,7 @@ bool TimeKeeper::syncPending() const bool TimeKeeper::needsSync(Peripheral who) const { - return m_timesheets[who].needsSync(m_now); + return m_timesheets[getPeripheralCode(who)].needsSync(m_now); } void TimeKeeper::updateSyncPending() diff --git a/pscx_emulator/pscx_timekeeper.h b/pscx_emulator/pscx_timekeeper.h index 1f47b72..13e8dec 100644 --- a/pscx_emulator/pscx_timekeeper.h +++ b/pscx_emulator/pscx_timekeeper.h @@ -2,12 +2,13 @@ #include #include +#include using Cycles = uint64_t; // List of all peripherals requiring a TimeSheet. The value of the // enum is used as the index in the table. -enum Peripheral +enum class Peripheral { // Graphics Processing Unit PERIPHERAL_GPU = 0, @@ -20,6 +21,11 @@ enum Peripheral PERIPHERAL_CDROM }; +inline uint64_t getPeripheralCode(Peripheral peripheral) +{ + return static_cast(peripheral); +} + // Struct used to keep track of individual peripherals struct TimeSheet { @@ -92,8 +98,8 @@ struct FracCycles static FracCycles fromF32(float value) { - float precision = (float)(1UL << FracCycles::fracBits()); - return (FracCycles)FracCycles(static_cast(value * precision)); + uint64_t precision = 1ULL << FracCycles::fracBits(); + return FracCycles(static_cast((double)value * precision)); } static FracCycles fromCycles(Cycles value) @@ -138,7 +144,7 @@ struct FracCycles Cycles ceil() const { Cycles shift = FracCycles::fracBits(); - Cycles align = (1 << shift) - 1; + Cycles align = (1ULL << shift) - 1; return (m_cycles + align) >> shift; } diff --git a/pscx_emulator/pscx_timers.cpp b/pscx_emulator/pscx_timers.cpp index 2fa9a8d..2de285e 100644 --- a/pscx_emulator/pscx_timers.cpp +++ b/pscx_emulator/pscx_timers.cpp @@ -33,7 +33,7 @@ Clock ClockSource::clock(Peripheral instance) const } }; - Clock clock; + Clock clock{}; switch (instance) { case Peripheral::PERIPHERAL_TIMER0: @@ -146,7 +146,7 @@ void Timer::sync(TimeKeeper& timeKeeper, InterruptState& irqState) m_counter = (uint16_t)count; if ((m_wrapIrq && overflow) || (m_targetIrq && targetPassed)) { - Interrupt interrupt; + Interrupt interrupt{ Interrupt::INTERRUPT_NONE }; switch (m_instance) { case Peripheral::PERIPHERAL_TIMER0: diff --git a/pscx_emulator/pscx_timers.h b/pscx_emulator/pscx_timers.h index 3c968c1..5262cde 100644 --- a/pscx_emulator/pscx_timers.h +++ b/pscx_emulator/pscx_timers.h @@ -10,7 +10,7 @@ struct Gpu; // Various synchronization modes when the timer is not in free-run -enum SyncTimer +enum class SyncTimer { // For timer 1/2: Pause during H/VBlank. For timer 3: Stop counter SYNC_TIMER_PAUSE = 0,