From 1000ee34951f58f64b41a11d4986d16d006f6aa7 Mon Sep 17 00:00:00 2001 From: Anton Kuzmin Date: Wed, 3 Apr 2024 00:55:00 +0200 Subject: [PATCH] Add support for GMM-7550 module (Cologne Chip GateMate FPGA) --- data/gmm7550.ccf | 65 +++++++++++++++++++++++++++++++++ servant.core | 17 +++++++++ servant/servant_gmm7550.v | 75 +++++++++++++++++++++++++++++++++++++++ servant/servant_ram.v | 2 ++ 4 files changed, 159 insertions(+) create mode 100644 data/gmm7550.ccf create mode 100644 servant/servant_gmm7550.v diff --git a/data/gmm7550.ccf b/data/gmm7550.ccf new file mode 100644 index 00000000..8dcdfa90 --- /dev/null +++ b/data/gmm7550.ccf @@ -0,0 +1,65 @@ +## GMM-7550 pins + +# This file is a part of the GMM-7550 VHDL Examples +# +# +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2023 Anton Kuzmin + +# Master clock input (100 MHz) +Pin_in "ser_clk" Loc = "SER_CLK"; + +### SPI + +Pin_inout "CFG_SPI_nCS" Loc = "IO_WA_A8"; +Pin_inout "CFG_SPI_CLK" Loc = "IO_WA_B8"; +Pin_inout "CFG_SPI_IO0" Loc = "IO_WA_B7"; # MOSI +Pin_inout "CFG_SPI_IO1" Loc = "IO_WA_A7"; # MISO +# Pin_inout "CFG_SPI_IO2" Loc = "IO_WA_B6"; # May be reused on the HAT for UART +# Pin_inout "CFG_SPI_IO3" Loc = "IO_WA_A6"; # May be reused on the HAT for UART +## HAT Adapter board + +# This file is a part of the GMM-7550 VHDL Examples +# +# +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2023 Anton Kuzmin + +# D4 CFG_FAILED (Red) +Pin_out "led_red_n" Loc = "IO_WA_A2"; + +# D2 CFG_DONE (Green) +Pin_out "led_green" Loc = "IO_WA_B2"; + +### UART + +Pin_out "uart_tx" Loc = "IO_WA_A6"; # SPI D3, GPIO pin 10 +Pin_in "uart_rx" Loc = "IO_WA_B6"; # SPI D2, GPIO pin 8 + +### Pmod J10 + +Pin_out "J10_EN" Loc = "IO_SA_A7"; + +Pin_inout "J10_IO[0]" Loc = "IO_SA_A0"; +Pin_inout "J10_IO[1]" Loc = "IO_SA_A1"; +Pin_inout "J10_IO[2]" Loc = "IO_SA_A2"; +Pin_inout "J10_IO[3]" Loc = "IO_SA_A3"; +Pin_inout "J10_IO[4]" Loc = "IO_SA_B0"; +Pin_inout "J10_IO[5]" Loc = "IO_SA_B1"; +Pin_inout "J10_IO[6]" Loc = "IO_SA_B2"; +Pin_inout "J10_IO[7]" Loc = "IO_SA_B3"; + +### Pmod J9 + +Pin_out "J9_EN" Loc = "IO_SB_B3"; + +Pin_inout "J9_IO[0]" Loc = "IO_SB_A6"; # CLK_2 +Pin_inout "J9_IO[1]" Loc = "IO_SB_A7"; # CLK_1 +Pin_inout "J9_IO[2]" Loc = "IO_SB_A8"; # CLK_0 +Pin_inout "J9_IO[3]" Loc = "IO_SB_A5"; # CLK_3 +Pin_inout "J9_IO[4]" Loc = "IO_SB_B6"; +Pin_inout "J9_IO[5]" Loc = "IO_SB_B7"; +Pin_inout "J9_IO[6]" Loc = "IO_SB_B8"; +Pin_inout "J9_IO[7]" Loc = "IO_SB_B5"; diff --git a/servant.core b/servant.core index a7f5efb5..9935cef7 100644 --- a/servant.core +++ b/servant.core @@ -135,6 +135,11 @@ filesets: icev_wireless : {files: [data/icev_wireless.pcf : {file_type : PCF}]} + gmm7550: + files: + - data/gmm7550.ccf : {file_type : CCF} + - servant/servant_gmm7550.v : {file_type : verilogSource} + lx9_microboard: files: - servant/servant_lx9_clock_gen.v : {file_type : verilogSource} @@ -383,6 +388,18 @@ targets: pnr: next toplevel : service + gmm7550: + default_tool: gatemate + description: CologneChip GateMate FPGA Module + filesets : [mem_files, soc, gmm7550] + parameters : [memfile=blinky.hex, memsize=8192] + toplevel : servant_gmm7550 + tools: + gatemate: + device : CCGM1A1 + yosys_synth_options : [ -nomx8 ] + p_r_options : [ +uCIO -cCP ] + lint: filesets : [soc] flow: lint diff --git a/servant/servant_gmm7550.v b/servant/servant_gmm7550.v new file mode 100644 index 00000000..b7a3f38e --- /dev/null +++ b/servant/servant_gmm7550.v @@ -0,0 +1,75 @@ +`timescale 1ns / 1ps + +module servant_gmm7550( + input wire ser_clk, + output wire led_green, + output wire led_red_n, + output wire uart_tx); + + // parameter memfile = "zephyr_hello.hex"; + parameter memfile = "blinky.hex"; + parameter memsize = 8192; + + wire clk270, clk180, clk90, clk0, usr_ref_out; + wire usr_pll_lock_stdy, usr_pll_lock; + + wire usr_rstn; + reg[4:0] rst; + + wire sys_clk; + wire sys_rst; + wire sys_rst_n; + wire q; + + assign led_red_n = 1'b1; + assign led_green = q; + assign uart_tx = q; + + CC_PLL #( + .REF_CLK("100.0"), // reference input in MHz + .OUT_CLK("32.0"), // pll output frequency in MHz + .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED + .LOCK_REQ(1), // Lock status required before PLL output enable + .LOW_JITTER(1), // 0: disable, 1: enable low jitter mode + .CI_FILTER_CONST(2), // optional CI filter constant + .CP_FILTER_CONST(4) // optional CP filter constant + ) pll_inst ( + .CLK_REF(ser_clk), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0), + .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(usr_pll_lock), + .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk0), .CLK_REF_OUT(usr_ref_out) + ); + + assign sys_clk = clk0; + + CC_USR_RSTN usr_rst_inst + (.USR_RSTN(usr_rstn)); + + always @(posedge sys_clk or negedge usr_rstn) + begin + if (!usr_rstn) begin + rst <= 5'b01111; + end else begin + if (usr_pll_lock) begin + if (!rst[4]) begin + rst <= rst - 1; + end else begin + rst <= rst; + end + end else begin + rst <= 5'b01111; + end + end + end + + assign sys_rst = !rst[4]; + assign sys_rst_n = rst[4]; + + servant + #(.memfile (memfile), + .memsize (memsize)) + servant + (.wb_clk (sys_clk), + .wb_rst (sys_rst), + .q (q)); + +endmodule diff --git a/servant/servant_ram.v b/servant/servant_ram.v index c3aca8f9..635e72df 100644 --- a/servant/servant_ram.v +++ b/servant/servant_ram.v @@ -38,7 +38,9 @@ module servant_ram initial if(|memfile) begin `ifndef ISE +`ifndef CCGM $display("Preloading %m from %s", memfile); +`endif `endif $readmemh(memfile, mem); end