diff --git a/doc/datasheet.rst b/doc/datasheet.rst
index a9e8d898..0c54ad48 100644
--- a/doc/datasheet.rst
+++ b/doc/datasheet.rst
@@ -2,4 +2,5 @@
 Datasheet
 *********
 
+.. include:: overview.rst
 .. include:: interface.rst
diff --git a/doc/overview.rst b/doc/overview.rst
new file mode 100644
index 00000000..33547d7c
--- /dev/null
+++ b/doc/overview.rst
@@ -0,0 +1,4 @@
+Interface
+=========
+
+The SERV RISC-V CPU is an award-winning and highly compact processor core based on the RISC-V instruction set architecture (ISA). It is designed to be the smallest possible RISC-V compliant CPU and is particularly well-suited for embedded systems and applications where silicon area is critical.