From 0f9e6c911d7f15305195d423d4f4a19686c14422 Mon Sep 17 00:00:00 2001 From: yetao01 Date: Tue, 24 Sep 2024 11:59:45 +0100 Subject: [PATCH 1/2] aarch64: fix jit_brgemm warnings Signed-off-by: yetao01 --- src/cpu/aarch64/brgemm/jit_brgemm_kernel.cpp | 8 ++++++-- .../aarch64/jit_brgemm_conv_comp_pad_kernel.hpp | 4 ++-- src/cpu/aarch64/jit_brgemm_post_ops.hpp | 15 +++++++++++---- 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/cpu/aarch64/brgemm/jit_brgemm_kernel.cpp b/src/cpu/aarch64/brgemm/jit_brgemm_kernel.cpp index 087fb52935a..8aa44c5a2da 100644 --- a/src/cpu/aarch64/brgemm/jit_brgemm_kernel.cpp +++ b/src/cpu/aarch64/brgemm/jit_brgemm_kernel.cpp @@ -1,6 +1,7 @@ /******************************************************************************* * Copyright 2021-2023 Intel Corporation * Copyright 2024 FUJITSU LIMITED +* Copyright 2024 Arm Ltd. and affiliates * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -1876,7 +1877,7 @@ void jit_brgemm_kernel_t::bdb_loop() { } void jit_brgemm_kernel_t::generate() { - size_t simd_w_; + size_t simd_w_ = 0; switch (brg.isa_impl) { case sve_512: simd_w_ = cpu_isa_traits::vlen / sizeof(float); @@ -1884,7 +1885,10 @@ void jit_brgemm_kernel_t::generate() { case sve_256: simd_w_ = cpu_isa_traits::vlen / sizeof(float); break; - default: assert(!"unsupported isa"); + default: { + assert(!"unsupported isa"); + return; + } } preamble(); if (simd_w_ != cpu_sveLen / sizeof(float)) { diff --git a/src/cpu/aarch64/jit_brgemm_conv_comp_pad_kernel.hpp b/src/cpu/aarch64/jit_brgemm_conv_comp_pad_kernel.hpp index 0472aafb91a..17b01080cc6 100644 --- a/src/cpu/aarch64/jit_brgemm_conv_comp_pad_kernel.hpp +++ b/src/cpu/aarch64/jit_brgemm_conv_comp_pad_kernel.hpp @@ -1,6 +1,7 @@ /******************************************************************************* * Copyright 2022-2023 Intel Corporation * Copyright 2024 FUJITSU LIMITED +* Copyright 2024 Arm Ltd. and affiliates * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -43,8 +44,7 @@ struct jit_uni_brgemm_conv_comp_pad_kernel_t : public jit_generator { using XReg = const Xbyak_aarch64::XReg; - jit_uni_brgemm_conv_comp_pad_kernel_t( - const jit_brgemm_conv_conf_t &ajcp); + jit_uni_brgemm_conv_comp_pad_kernel_t(const jit_brgemm_conv_conf_t &ajcp); ~jit_uni_brgemm_conv_comp_pad_kernel_t() = default; diff --git a/src/cpu/aarch64/jit_brgemm_post_ops.hpp b/src/cpu/aarch64/jit_brgemm_post_ops.hpp index 2809e1813b6..4257bfe31b8 100644 --- a/src/cpu/aarch64/jit_brgemm_post_ops.hpp +++ b/src/cpu/aarch64/jit_brgemm_post_ops.hpp @@ -1,6 +1,7 @@ /******************************************************************************* * Copyright 2020-2023 Intel Corporation * Copyright 2024 FUJITSU LIMITED +* Copyright 2024 Arm Ltd. and affiliates * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -196,7 +197,7 @@ struct jit_brgemm_kernel_diff_bias_t : public jit_generator { } void generate() override { - size_t simd_w_; + size_t simd_w_ = 0; switch (brg_.isa_impl) { case sve_512: simd_w_ = cpu_isa_traits::vlen / sizeof(float); @@ -204,7 +205,10 @@ struct jit_brgemm_kernel_diff_bias_t : public jit_generator { case sve_256: simd_w_ = cpu_isa_traits::vlen / sizeof(float); break; - default: assert(!"unsupported isa"); + default: { + assert(!"unsupported isa"); + return; + } } preamble(); if (simd_w_ != cpu_sveLen / sizeof(float)) { @@ -850,7 +854,7 @@ struct jit_brgemm_kernel_post_ops : public jit_generator { } void generate() override { - size_t simd_w_; + size_t simd_w_ = 0; switch (brg.isa_impl) { case sve_512: simd_w_ = cpu_isa_traits::vlen / sizeof(float); @@ -858,7 +862,10 @@ struct jit_brgemm_kernel_post_ops : public jit_generator { case sve_256: simd_w_ = cpu_isa_traits::vlen / sizeof(float); break; - default: assert(!"unsupported isa"); + default: { + assert(!"unsupported isa"); + return; + } } preamble(); if (simd_w_ != cpu_sveLen / sizeof(float)) { From 738c3c3d99b6206a9e0a0f55888eab8dbee87cee Mon Sep 17 00:00:00 2001 From: yetao01 Date: Wed, 25 Sep 2024 11:06:01 +0100 Subject: [PATCH 2/2] aarch64: fix out-of-bound warnings of deconvolution Signed-off-by: yetao01 --- src/cpu/cpu_deconvolution_list.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/cpu_deconvolution_list.cpp b/src/cpu/cpu_deconvolution_list.cpp index 468f4711452..cb2702f184e 100644 --- a/src/cpu/cpu_deconvolution_list.cpp +++ b/src/cpu/cpu_deconvolution_list.cpp @@ -1,7 +1,7 @@ /******************************************************************************* * Copyright 2019-2023 Intel Corporation * Copyright 2022 FUJITSU LIMITED -* Copyright 2022 Arm Ltd. and affiliates +* Copyright 2022, 2024 Arm Ltd. and affiliates * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -16,10 +16,9 @@ * limitations under the License. *******************************************************************************/ +#include "common/compiler_workarounds.hpp" #include "cpu/cpu_engine.hpp" - #include "cpu/ref_deconvolution.hpp" - #if DNNL_X64 #include "cpu/x64/jit_avx512_core_amx_deconvolution.hpp" #include "cpu/x64/jit_avx512_core_x8s8s32x_1x1_deconvolution.hpp"