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action_wrapper.vhd_source
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----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2016,2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE work.psl_accel_types.ALL;
USE work.action_types.ALL;
ENTITY action_wrapper IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
interrupt_src : OUT STD_LOGIC_VECTOR(INT_BITS-2 DOWNTO 0);
interrupt_ctx : OUT STD_LOGIC_VECTOR(CONTEXT_BITS-1 DOWNTO 0);
interrupt_ack : IN STD_LOGIC;
-- -- only for DDRI_USED=TRUE
-- AXI SDRAM Interface -- only for DDRI_USED=TRUE
m_axi_card_mem0_araddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arid : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arready : IN STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_arregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_aruser : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ARUSER_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_arvalid : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_awaddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awid : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awready : IN STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_awregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_AWUSER_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_awvalid : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_bid : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_bready : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_bresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_buser : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_BUSER_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_bvalid : IN STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_rdata : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_rid : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_rlast : IN STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_rready : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_rresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_ruser : IN STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_RUSER_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_rvalid : IN STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_wdata : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_wlast : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_wready : IN STD_LOGIC; -- only for DDRI_USED=TRUE
m_axi_card_mem0_wstrb : OUT STD_LOGIC_VECTOR ( (C_M_AXI_CARD_MEM0_DATA_WIDTH/8)-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_wuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_CARD_MEM0_WUSER_WIDTH-1 DOWNTO 0 ); -- only for DDRI_USED=TRUE
m_axi_card_mem0_wvalid : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
-- -- only for NVME_USED=TRUE
-- AXI NVME Interface -- only for NVME_USED=TRUE
m_axi_nvme_araddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ADDR_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arid : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arready : IN STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_arregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_aruser : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ARUSER_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_arvalid : OUT STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_awaddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ADDR_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awid : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awready : IN STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_awregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_NVME_AWUSER_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_awvalid : OUT STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_bid : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_bready : OUT STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_bresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_buser : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_BUSER_WIDTH -1 downto 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_bvalid : IN STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_rdata : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_DATA_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_rid : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_ID_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_rlast : IN STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_rready : OUT STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_rresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_ruser : IN STD_LOGIC_VECTOR ( C_M_AXI_NVME_RUSER_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_rvalid : IN STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_wdata : OUT STD_LOGIC_VECTOR (C_M_AXI_NVME_DATA_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_wlast : OUT STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_wready : IN STD_LOGIC; -- only for NVME_USED=TRUE
m_axi_nvme_wstrb : OUT STD_LOGIC_VECTOR ((C_M_AXI_NVME_DATA_WIDTH/8) -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_wuser : OUT STD_LOGIC_VECTOR (C_M_AXI_NVME_WUSER_WIDTH -1 DOWNTO 0 ); -- only for NVME_USED=TRUE
m_axi_nvme_wvalid : OUT STD_LOGIC; -- only for NVME_USED=TRUE
--
-- AXI Control Register Interface
s_axi_ctrl_reg_araddr : IN STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_arready : OUT STD_LOGIC;
s_axi_ctrl_reg_arvalid : IN STD_LOGIC;
s_axi_ctrl_reg_awaddr : IN STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_awready : OUT STD_LOGIC;
s_axi_ctrl_reg_awvalid : IN STD_LOGIC;
s_axi_ctrl_reg_bready : IN STD_LOGIC;
s_axi_ctrl_reg_bresp : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
s_axi_ctrl_reg_bvalid : OUT STD_LOGIC;
s_axi_ctrl_reg_rdata : OUT STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_rready : IN STD_LOGIC;
s_axi_ctrl_reg_rresp : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
s_axi_ctrl_reg_rvalid : OUT STD_LOGIC;
s_axi_ctrl_reg_wdata : IN STD_LOGIC_VECTOR ( C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0 );
s_axi_ctrl_reg_wready : OUT STD_LOGIC;
s_axi_ctrl_reg_wstrb : IN STD_LOGIC_VECTOR ( (C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 DOWNTO 0 );
s_axi_ctrl_reg_wvalid : IN STD_LOGIC;
--
-- AXI Host Memory Interface
m_axi_host_mem_araddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_arburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_arcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_arid : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_arlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_host_mem_arlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_arprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_arqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_arready : IN STD_LOGIC;
m_axi_host_mem_arregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_arsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_aruser : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_arvalid : OUT STD_LOGIC;
m_axi_host_mem_awaddr : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_awburst : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_awcache : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_awid : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_awlen : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
m_axi_host_mem_awlock : OUT STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_awprot : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_awqos : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_awready : IN STD_LOGIC;
m_axi_host_mem_awregion : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
m_axi_host_mem_awsize : OUT STD_LOGIC_VECTOR ( 2 DOWNTO 0 );
m_axi_host_mem_awuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_awvalid : OUT STD_LOGIC;
m_axi_host_mem_bid : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_bready : OUT STD_LOGIC;
m_axi_host_mem_bresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_buser : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_BUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_bvalid : IN STD_LOGIC;
m_axi_host_mem_rdata : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_rid : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_rlast : IN STD_LOGIC;
m_axi_host_mem_rready : OUT STD_LOGIC;
m_axi_host_mem_rresp : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
m_axi_host_mem_ruser : IN STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_RUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_rvalid : IN STD_LOGIC;
m_axi_host_mem_wdata : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_wlast : OUT STD_LOGIC;
m_axi_host_mem_wready : IN STD_LOGIC;
m_axi_host_mem_wstrb : OUT STD_LOGIC_VECTOR ( (C_M_AXI_HOST_MEM_DATA_WIDTH/8)-1 DOWNTO 0 );
m_axi_host_mem_wuser : OUT STD_LOGIC_VECTOR ( C_M_AXI_HOST_MEM_WUSER_WIDTH-1 DOWNTO 0 );
m_axi_host_mem_wvalid : OUT STD_LOGIC
);
END action_wrapper;
ARCHITECTURE STRUCTURE OF action_wrapper IS
COMPONENT action_example IS
GENERIC (
-- Parameters for Axi Master Bus Interface AXI_CARD_MEM0 : to on-card SDRAM
C_AXI_CARD_MEM0_ID_WIDTH : integer;
C_AXI_CARD_MEM0_ADDR_WIDTH : integer;
C_AXI_CARD_MEM0_DATA_WIDTH : integer;
C_AXI_CARD_MEM0_AWUSER_WIDTH : integer;
C_AXI_CARD_MEM0_ARUSER_WIDTH : integer;
C_AXI_CARD_MEM0_WUSER_WIDTH : integer;
C_AXI_CARD_MEM0_RUSER_WIDTH : integer;
C_AXI_CARD_MEM0_BUSER_WIDTH : integer;
-- Parameters for Axi Slave Bus Interface AXI_CTRL_REG
C_AXI_CTRL_REG_DATA_WIDTH : integer;
C_AXI_CTRL_REG_ADDR_WIDTH : integer;
-- Parameters for Axi Master Bus Interface AXI_HOST_MEM : to Host memory
C_AXI_HOST_MEM_ID_WIDTH : integer;
C_AXI_HOST_MEM_ADDR_WIDTH : integer;
C_AXI_HOST_MEM_DATA_WIDTH : integer;
C_AXI_HOST_MEM_AWUSER_WIDTH : integer;
C_AXI_HOST_MEM_ARUSER_WIDTH : integer;
C_AXI_HOST_MEM_WUSER_WIDTH : integer;
C_AXI_HOST_MEM_RUSER_WIDTH : integer;
C_AXI_HOST_MEM_BUSER_WIDTH : integer;
INT_BITS : integer;
CONTEXT_BITS : integer
);
PORT (
action_clk : IN STD_LOGIC;
action_rst_n : IN STD_LOGIC;
int_req : OUT STD_LOGIC;
int_src : OUT STD_LOGIC_VECTOR(INT_BITS-2 DOWNTO 0);
int_ctx : OUT STD_LOGIC_VECTOR(CONTEXT_BITS-1 DOWNTO 0);
int_req_ack : IN STD_LOGIC;
-- Ports of Axi Master Bus Interface AXI_CARD_MEM0 -- only for DDRI_USED=TRUE
-- to on-card SDRAM -- only for DDRI_USED=TRUE
axi_card_mem0_awaddr : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awvalid : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_awready : IN STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_wdata : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_wstrb : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_DATA_WIDTH/8-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_wlast : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_wvalid : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_wready : IN STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_bvalid : IN STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_bready : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_araddr : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_arvalid : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_arready : IN STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_rdata : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_DATA_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_rlast : IN STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_rvalid : IN STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_rready : OUT STD_LOGIC; -- only for DDRI_USED=TRUE
axi_card_mem0_arid : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_aruser : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ARUSER_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awid : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_awuser : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_AWUSER_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_bid : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_buser : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_BUSER_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_rid : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_ID_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_ruser : IN STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_RUSER_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
axi_card_mem0_wuser : OUT STD_LOGIC_VECTOR(C_M_AXI_CARD_MEM0_WUSER_WIDTH-1 DOWNTO 0); -- only for DDRI_USED=TRUE
-- -- only for NVME_USED=TRUE
-- Ports of Axi Master Bus Interface AXI_NVME -- only for NVME_USED=TRUE
-- to NVME -- only for NVME_USED=TRUE
axi_nvme_awaddr : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ADDR_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awvalid : OUT STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_awready : IN STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_wdata : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_DATA_WIDTH-1 downto 0); -- only for NVME_USED=TRUE
axi_nvme_wstrb : OUT STD_LOGIC_VECTOR((C_M_AXI_NVME_DATA_WIDTH/8)-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_wlast : OUT STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_wvalid : OUT STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_wready : IN STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_bvalid : IN STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_bready : OUT STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_araddr : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ADDR_WIDTH-1 downto 0); -- only for NVME_USED=TRUE
axi_nvme_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_arvalid : OUT STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_arready : IN STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_rdata : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_DATA_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_rlast : IN STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_rvalid : IN STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_rready : OUT STD_LOGIC; -- only for NVME_USED=TRUE
axi_nvme_arid : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_aruser : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ARUSER_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awid : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_awuser : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_AWUSER_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_bid : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_buser : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_BUSER_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_rid : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_ID_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_ruser : IN STD_LOGIC_VECTOR(C_M_AXI_NVME_RUSER_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
axi_nvme_wuser : OUT STD_LOGIC_VECTOR(C_M_AXI_NVME_WUSER_WIDTH-1 DOWNTO 0); -- only for NVME_USED=TRUE
--
-- Ports of Axi Slave Bus Interface AXI_CTRL_REG
axi_ctrl_reg_awaddr : IN STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_awvalid : IN STD_LOGIC;
axi_ctrl_reg_awready : OUT STD_LOGIC;
axi_ctrl_reg_wdata : IN STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_wstrb : IN STD_LOGIC_VECTOR((C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 DOWNTO 0);
axi_ctrl_reg_wvalid : IN STD_LOGIC;
axi_ctrl_reg_wready : OUT STD_LOGIC;
axi_ctrl_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_ctrl_reg_bvalid : OUT STD_LOGIC;
axi_ctrl_reg_bready : IN STD_LOGIC;
axi_ctrl_reg_araddr : IN STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_ADDR_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_arvalid : IN STD_LOGIC;
axi_ctrl_reg_arready : OUT STD_LOGIC;
axi_ctrl_reg_rdata : OUT STD_LOGIC_VECTOR(C_S_AXI_CTRL_REG_DATA_WIDTH-1 DOWNTO 0);
axi_ctrl_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_ctrl_reg_rvalid : OUT STD_LOGIC;
axi_ctrl_reg_rready : IN STD_LOGIC;
--
-- Ports of Axi Master Bus Interface AXI_HOST_MEM
-- to HOST memory
axi_host_mem_awaddr : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0);
axi_host_mem_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_host_mem_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_awlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_awvalid : OUT STD_LOGIC;
axi_host_mem_awready : IN STD_LOGIC;
axi_host_mem_wdata : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0);
axi_host_mem_wstrb : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_DATA_WIDTH/8-1 DOWNTO 0);
axi_host_mem_wlast : OUT STD_LOGIC;
axi_host_mem_wvalid : OUT STD_LOGIC;
axi_host_mem_wready : IN STD_LOGIC;
axi_host_mem_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_bvalid : IN STD_LOGIC;
axi_host_mem_bready : OUT STD_LOGIC;
axi_host_mem_araddr : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ADDR_WIDTH-1 DOWNTO 0);
axi_host_mem_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
axi_host_mem_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_arlock : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
axi_host_mem_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_host_mem_arvalid : OUT STD_LOGIC;
axi_host_mem_arready : IN STD_LOGIC;
axi_host_mem_rdata : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_DATA_WIDTH-1 DOWNTO 0);
axi_host_mem_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
axi_host_mem_rlast : IN STD_LOGIC;
axi_host_mem_rvalid : IN STD_LOGIC;
axi_host_mem_rready : OUT STD_LOGIC;
axi_host_mem_arid : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_aruser : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_awid : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_awuser : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_bid : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_buser : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_BUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_rid : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_ID_WIDTH-1 DOWNTO 0);
axi_host_mem_ruser : IN STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_RUSER_WIDTH-1 DOWNTO 0);
axi_host_mem_wuser : OUT STD_LOGIC_VECTOR(C_M_AXI_HOST_MEM_WUSER_WIDTH-1 DOWNTO 0)
);
END COMPONENT action_example;
BEGIN
action_0: COMPONENT action_example
GENERIC MAP (
-- Parameters for Axi Master Bus Interface AXI_CARD_MEM0 : to on-card SDRAM
C_AXI_CARD_MEM0_ID_WIDTH => C_M_AXI_CARD_MEM0_ID_WIDTH,
C_AXI_CARD_MEM0_ADDR_WIDTH => C_M_AXI_CARD_MEM0_ADDR_WIDTH,
C_AXI_CARD_MEM0_DATA_WIDTH => C_M_AXI_CARD_MEM0_DATA_WIDTH,
C_AXI_CARD_MEM0_AWUSER_WIDTH => C_M_AXI_CARD_MEM0_AWUSER_WIDTH,
C_AXI_CARD_MEM0_ARUSER_WIDTH => C_M_AXI_CARD_MEM0_ARUSER_WIDTH,
C_AXI_CARD_MEM0_WUSER_WIDTH => C_M_AXI_CARD_MEM0_WUSER_WIDTH,
C_AXI_CARD_MEM0_RUSER_WIDTH => C_M_AXI_CARD_MEM0_RUSER_WIDTH,
C_AXI_CARD_MEM0_BUSER_WIDTH => C_M_AXI_CARD_MEM0_BUSER_WIDTH,
-- Parameters for Axi Slave Bus Interface AXI_CTRL_REG
C_AXI_CTRL_REG_DATA_WIDTH => C_S_AXI_CTRL_REG_DATA_WIDTH,
C_AXI_CTRL_REG_ADDR_WIDTH => C_S_AXI_CTRL_REG_ADDR_WIDTH,
-- Parameters for Axi Master Bus Interface AXI_HOST_MEM : to Host memory
C_AXI_HOST_MEM_ID_WIDTH => C_M_AXI_HOST_MEM_ID_WIDTH,
C_AXI_HOST_MEM_ADDR_WIDTH => C_M_AXI_HOST_MEM_ADDR_WIDTH,
C_AXI_HOST_MEM_DATA_WIDTH => C_M_AXI_HOST_MEM_DATA_WIDTH,
C_AXI_HOST_MEM_AWUSER_WIDTH => C_M_AXI_HOST_MEM_AWUSER_WIDTH,
C_AXI_HOST_MEM_ARUSER_WIDTH => C_M_AXI_HOST_MEM_ARUSER_WIDTH,
C_AXI_HOST_MEM_WUSER_WIDTH => C_M_AXI_HOST_MEM_WUSER_WIDTH,
C_AXI_HOST_MEM_RUSER_WIDTH => C_M_AXI_HOST_MEM_RUSER_WIDTH,
C_AXI_HOST_MEM_BUSER_WIDTH => C_M_AXI_HOST_MEM_BUSER_WIDTH,
INT_BITS => INT_BITS,
CONTEXT_BITS => CONTEXT_BITS
)
PORT MAP (
action_clk => ap_clk,
action_rst_n => ap_rst_n,
int_req => interrupt,
int_src => interrupt_src,
int_ctx => interrupt_ctx,
int_req_ack => interrupt_ack,
axi_card_mem0_araddr => m_axi_card_mem0_araddr, -- only for DDRI_USED=TRUE
axi_card_mem0_arburst => m_axi_card_mem0_arburst, -- only for DDRI_USED=TRUE
axi_card_mem0_arcache => m_axi_card_mem0_arcache, -- only for DDRI_USED=TRUE
axi_card_mem0_arid => m_axi_card_mem0_arid, -- only for DDRI_USED=TRUE
axi_card_mem0_arlen => m_axi_card_mem0_arlen, -- only for DDRI_USED=TRUE
axi_card_mem0_arlock => m_axi_card_mem0_arlock, -- only for DDRI_USED=TRUE
axi_card_mem0_arprot => m_axi_card_mem0_arprot, -- only for DDRI_USED=TRUE
axi_card_mem0_arqos => m_axi_card_mem0_arqos, -- only for DDRI_USED=TRUE
axi_card_mem0_arready => m_axi_card_mem0_arready, -- only for DDRI_USED=TRUE
axi_card_mem0_arregion => m_axi_card_mem0_arregion, -- only for DDRI_USED=TRUE
axi_card_mem0_arsize => m_axi_card_mem0_arsize, -- only for DDRI_USED=TRUE
axi_card_mem0_aruser => m_axi_card_mem0_aruser, -- only for DDRI_USED=TRUE
axi_card_mem0_arvalid => m_axi_card_mem0_arvalid, -- only for DDRI_USED=TRUE
axi_card_mem0_awaddr => m_axi_card_mem0_awaddr, -- only for DDRI_USED=TRUE
axi_card_mem0_awburst => m_axi_card_mem0_awburst, -- only for DDRI_USED=TRUE
axi_card_mem0_awcache => m_axi_card_mem0_awcache, -- only for DDRI_USED=TRUE
axi_card_mem0_awid => m_axi_card_mem0_awid, -- only for DDRI_USED=TRUE
axi_card_mem0_awlen => m_axi_card_mem0_awlen, -- only for DDRI_USED=TRUE
axi_card_mem0_awlock => m_axi_card_mem0_awlock, -- only for DDRI_USED=TRUE
axi_card_mem0_awprot => m_axi_card_mem0_awprot, -- only for DDRI_USED=TRUE
axi_card_mem0_awqos => m_axi_card_mem0_awqos, -- only for DDRI_USED=TRUE
axi_card_mem0_awready => m_axi_card_mem0_awready, -- only for DDRI_USED=TRUE
axi_card_mem0_awregion => m_axi_card_mem0_awregion, -- only for DDRI_USED=TRUE
axi_card_mem0_awsize => m_axi_card_mem0_awsize, -- only for DDRI_USED=TRUE
axi_card_mem0_awuser => m_axi_card_mem0_awuser, -- only for DDRI_USED=TRUE
axi_card_mem0_awvalid => m_axi_card_mem0_awvalid, -- only for DDRI_USED=TRUE
axi_card_mem0_bid => m_axi_card_mem0_bid, -- only for DDRI_USED=TRUE
axi_card_mem0_bready => m_axi_card_mem0_bready, -- only for DDRI_USED=TRUE
axi_card_mem0_bresp => m_axi_card_mem0_bresp, -- only for DDRI_USED=TRUE
axi_card_mem0_buser => m_axi_card_mem0_buser, -- only for DDRI_USED=TRUE
axi_card_mem0_bvalid => m_axi_card_mem0_bvalid, -- only for DDRI_USED=TRUE
axi_card_mem0_rdata => m_axi_card_mem0_rdata, -- only for DDRI_USED=TRUE
axi_card_mem0_rid => m_axi_card_mem0_rid, -- only for DDRI_USED=TRUE
axi_card_mem0_rlast => m_axi_card_mem0_rlast, -- only for DDRI_USED=TRUE
axi_card_mem0_rready => m_axi_card_mem0_rready, -- only for DDRI_USED=TRUE
axi_card_mem0_rresp => m_axi_card_mem0_rresp, -- only for DDRI_USED=TRUE
axi_card_mem0_ruser => m_axi_card_mem0_ruser, -- only for DDRI_USED=TRUE
axi_card_mem0_rvalid => m_axi_card_mem0_rvalid, -- only for DDRI_USED=TRUE
axi_card_mem0_wdata => m_axi_card_mem0_wdata, -- only for DDRI_USED=TRUE
axi_card_mem0_wlast => m_axi_card_mem0_wlast, -- only for DDRI_USED=TRUE
axi_card_mem0_wready => m_axi_card_mem0_wready, -- only for DDRI_USED=TRUE
axi_card_mem0_wstrb => m_axi_card_mem0_wstrb, -- only for DDRI_USED=TRUE
axi_card_mem0_wuser => m_axi_card_mem0_wuser, -- only for DDRI_USED=TRUE
axi_card_mem0_wvalid => m_axi_card_mem0_wvalid, -- only for DDRI_USED=TRUE
axi_nvme_araddr => m_axi_nvme_araddr, -- only for NVME_USED=TRUE
axi_nvme_arburst => m_axi_nvme_arburst, -- only for NVME_USED=TRUE
axi_nvme_arcache => m_axi_nvme_arcache, -- only for NVME_USED=TRUE
axi_nvme_arid => m_axi_nvme_arid, -- only for NVME_USED=TRUE
axi_nvme_arlen => m_axi_nvme_arlen, -- only for NVME_USED=TRUE
axi_nvme_arlock => m_axi_nvme_arlock, -- only for NVME_USED=TRUE
axi_nvme_arprot => m_axi_nvme_arprot, -- only for NVME_USED=TRUE
axi_nvme_arqos => m_axi_nvme_arqos, -- only for NVME_USED=TRUE
axi_nvme_arready => m_axi_nvme_arready, -- only for NVME_USED=TRUE
axi_nvme_arregion => m_axi_nvme_arregion, -- only for NVME_USED=TRUE
axi_nvme_arsize => m_axi_nvme_arsize, -- only for NVME_USED=TRUE
axi_nvme_aruser => m_axi_nvme_aruser, -- only for NVME_USED=TRUE
axi_nvme_arvalid => m_axi_nvme_arvalid, -- only for NVME_USED=TRUE
axi_nvme_awaddr => m_axi_nvme_awaddr, -- only for NVME_USED=TRUE
axi_nvme_awburst => m_axi_nvme_awburst, -- only for NVME_USED=TRUE
axi_nvme_awcache => m_axi_nvme_awcache, -- only for NVME_USED=TRUE
axi_nvme_awid => m_axi_nvme_awid, -- only for NVME_USED=TRUE
axi_nvme_awlen => m_axi_nvme_awlen, -- only for NVME_USED=TRUE
axi_nvme_awlock => m_axi_nvme_awlock, -- only for NVME_USED=TRUE
axi_nvme_awprot => m_axi_nvme_awprot, -- only for NVME_USED=TRUE
axi_nvme_awqos => m_axi_nvme_awqos, -- only for NVME_USED=TRUE
axi_nvme_awready => m_axi_nvme_awready, -- only for NVME_USED=TRUE
axi_nvme_awregion => m_axi_nvme_awregion, -- only for NVME_USED=TRUE
axi_nvme_awsize => m_axi_nvme_awsize, -- only for NVME_USED=TRUE
axi_nvme_awuser => m_axi_nvme_awuser, -- only for NVME_USED=TRUE
axi_nvme_awvalid => m_axi_nvme_awvalid, -- only for NVME_USED=TRUE
axi_nvme_bid => m_axi_nvme_bid, -- only for NVME_USED=TRUE
axi_nvme_bready => m_axi_nvme_bready, -- only for NVME_USED=TRUE
axi_nvme_bresp => m_axi_nvme_bresp, -- only for NVME_USED=TRUE
axi_nvme_buser => m_axi_nvme_buser, -- only for NVME_USED=TRUE
axi_nvme_bvalid => m_axi_nvme_bvalid, -- only for NVME_USED=TRUE
axi_nvme_rdata => m_axi_nvme_rdata, -- only for NVME_USED=TRUE
axi_nvme_rid => m_axi_nvme_rid, -- only for NVME_USED=TRUE
axi_nvme_rlast => m_axi_nvme_rlast, -- only for NVME_USED=TRUE
axi_nvme_rready => m_axi_nvme_rready, -- only for NVME_USED=TRUE
axi_nvme_rresp => m_axi_nvme_rresp, -- only for NVME_USED=TRUE
axi_nvme_ruser => m_axi_nvme_ruser, -- only for NVME_USED=TRUE
axi_nvme_rvalid => m_axi_nvme_rvalid, -- only for NVME_USED=TRUE
axi_nvme_wdata => m_axi_nvme_wdata, -- only for NVME_USED=TRUE
axi_nvme_wlast => m_axi_nvme_wlast, -- only for NVME_USED=TRUE
axi_nvme_wready => m_axi_nvme_wready, -- only for NVME_USED=TRUE
axi_nvme_wstrb => m_axi_nvme_wstrb, -- only for NVME_USED=TRUE
axi_nvme_wuser => m_axi_nvme_wuser, -- only for NVME_USED=TRUE
axi_nvme_wvalid => m_axi_nvme_wvalid, -- only for NVME_USED=TRUE
axi_ctrl_reg_araddr => s_axi_ctrl_reg_araddr,
axi_ctrl_reg_arready => s_axi_ctrl_reg_arready,
axi_ctrl_reg_arvalid => s_axi_ctrl_reg_arvalid,
axi_ctrl_reg_awaddr => s_axi_ctrl_reg_awaddr,
axi_ctrl_reg_awready => s_axi_ctrl_reg_awready,
axi_ctrl_reg_awvalid => s_axi_ctrl_reg_awvalid,
axi_ctrl_reg_bready => s_axi_ctrl_reg_bready,
axi_ctrl_reg_bresp => s_axi_ctrl_reg_bresp,
axi_ctrl_reg_bvalid => s_axi_ctrl_reg_bvalid,
axi_ctrl_reg_rdata => s_axi_ctrl_reg_rdata,
axi_ctrl_reg_rready => s_axi_ctrl_reg_rready,
axi_ctrl_reg_rresp => s_axi_ctrl_reg_rresp,
axi_ctrl_reg_rvalid => s_axi_ctrl_reg_rvalid,
axi_ctrl_reg_wdata => s_axi_ctrl_reg_wdata,
axi_ctrl_reg_wready => s_axi_ctrl_reg_wready,
axi_ctrl_reg_wstrb => s_axi_ctrl_reg_wstrb,
axi_ctrl_reg_wvalid => s_axi_ctrl_reg_wvalid,
axi_host_mem_araddr => m_axi_host_mem_araddr,
axi_host_mem_arburst => m_axi_host_mem_arburst,
axi_host_mem_arcache => m_axi_host_mem_arcache,
axi_host_mem_arid => m_axi_host_mem_arid,
axi_host_mem_arlen => m_axi_host_mem_arlen,
axi_host_mem_arlock => m_axi_host_mem_arlock,
axi_host_mem_arprot => m_axi_host_mem_arprot,
axi_host_mem_arqos => m_axi_host_mem_arqos,
axi_host_mem_arready => m_axi_host_mem_arready,
axi_host_mem_arregion => m_axi_host_mem_arregion,
axi_host_mem_arsize => m_axi_host_mem_arsize,
axi_host_mem_aruser => m_axi_host_mem_aruser,
axi_host_mem_arvalid => m_axi_host_mem_arvalid,
axi_host_mem_awaddr => m_axi_host_mem_awaddr,
axi_host_mem_awburst => m_axi_host_mem_awburst,
axi_host_mem_awcache => m_axi_host_mem_awcache,
axi_host_mem_awid => m_axi_host_mem_awid,
axi_host_mem_awlen => m_axi_host_mem_awlen,
axi_host_mem_awlock => m_axi_host_mem_awlock,
axi_host_mem_awprot => m_axi_host_mem_awprot,
axi_host_mem_awqos => m_axi_host_mem_awqos,
axi_host_mem_awready => m_axi_host_mem_awready,
axi_host_mem_awregion => m_axi_host_mem_awregion,
axi_host_mem_awsize => m_axi_host_mem_awsize,
axi_host_mem_awuser => m_axi_host_mem_awuser,
axi_host_mem_awvalid => m_axi_host_mem_awvalid,
axi_host_mem_bid => m_axi_host_mem_bid,
axi_host_mem_bready => m_axi_host_mem_bready,
axi_host_mem_bresp => m_axi_host_mem_bresp,
axi_host_mem_buser => m_axi_host_mem_buser,
axi_host_mem_bvalid => m_axi_host_mem_bvalid,
axi_host_mem_rdata => m_axi_host_mem_rdata,
axi_host_mem_rid => m_axi_host_mem_rid,
axi_host_mem_rlast => m_axi_host_mem_rlast,
axi_host_mem_rready => m_axi_host_mem_rready,
axi_host_mem_rresp => m_axi_host_mem_rresp,
axi_host_mem_ruser => m_axi_host_mem_ruser,
axi_host_mem_rvalid => m_axi_host_mem_rvalid,
axi_host_mem_wdata => m_axi_host_mem_wdata,
axi_host_mem_wlast => m_axi_host_mem_wlast,
axi_host_mem_wready => m_axi_host_mem_wready,
axi_host_mem_wstrb => m_axi_host_mem_wstrb,
axi_host_mem_wuser => m_axi_host_mem_wuser,
axi_host_mem_wvalid => m_axi_host_mem_wvalid
);
END STRUCTURE;