From 502f201c748acd4b14a9b7fb80540fa177067c13 Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Mon, 29 Apr 2024 05:34:57 +0200 Subject: [PATCH 1/3] Update waiver line number changes on cv32e40p_decoder following RTL v1.8.0 Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 6 ++--- .../cv32e40pv2_code_fpu_cfg_waiver.do | 22 +++++++++++-------- .../cv32e40pv2_code_pulp_cfg_waiver.do | 2 +- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 3708b08bc1..021960d300 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -80,9 +80,9 @@ coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} -coverage exclude -line 2767 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} -coverage exclude -line 2765 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} -coverage exclude -line 2765 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2784 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2782 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2782 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} coverage exclude -line 419 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } coverage exclude -line 451 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -line 452 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index 3a989338f0..ed110a0758 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -1,12 +1,16 @@ -coverage exclude -line 1269 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1270 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1271 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1279 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1280 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1300 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1301 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1302 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1264 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1265 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1266 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1273 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1274 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1275 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1296 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1297 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1353 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} +coverage exclude -line 1362 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} +coverage exclude -line 1440 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} +coverage exclude -line 1483 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} coverage exclude -line 150 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 201 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do index 696a7ccec9..494debe1e6 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do @@ -55,7 +55,7 @@ coverage exclude -line 266 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 272 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 284 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} -coverage exclude -line 2983 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} +coverage exclude -line 3000 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} coverage exclude -line 1390 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} coverage exclude -line 89 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} From 5f1648a17183c0345787995d1e13d328264627ab Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Fri, 3 May 2024 04:51:12 +0200 Subject: [PATCH 2/3] Add code coverage waivers for CFG_P_F0 following review. Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 3 + .../cv32e40pv2_code_fpu_cfg_waiver.do | 122 ++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 021960d300..5ded79dc1b 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -177,5 +177,8 @@ coverage exclude -line 1131 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv coverage exclude -line 1230 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -line 1237 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -line 1237 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 399 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No interrupt during debug mode. To waive corner case to happen during FIRST_FETCH 1 clk cycle. } +coverage exclude -line 640 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {HWLoop1 cannot be nested in HWLoop0.} +coverage exclude -line 675 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No case when ID not ready for single stepped instruction. } coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/interrupt_assert_i -recursive -comment {this is TB module bind to RTL. No need code coverage.} coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/prefetch_controller_i/prefetch_controller_sva -recursive -comment {this is TB module bind to RTL. No need code coverage.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index ed110a0758..058ccb89e7 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -279,3 +279,125 @@ coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 242 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 243 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 125 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 125 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 126 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 127 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 129 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 130 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 131 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 139 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 140 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 141 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 220 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 220 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -feccondrow 872 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {one specific combination is unreachable. Proven with Formal. } +coverage exclude -line 181 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {we are in sigle master mode. The core wont push more instruction. } +coverage exclude -line 196 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 196 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 197 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 198 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 193 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/gen_parallel_slices[0]/active_format/i_fmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_noncomp} -comment {we never have is_boxed=0. TOP level parameter EnableNanBox is always 1. } +coverage exclude -line 193 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/gen_parallel_slices[0]/active_format/i_fmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_noncomp} -comment {we never have is_boxed=0. TOP level parameter EnableNanBox is always 1. } +coverage exclude -feccondrow 501 6 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {unreachable. Never fdsu_dn_stall during WB_IDLE state.} +coverage exclude -line 511 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 512 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 512 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 513 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 514 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 515 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 520 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_iter_start when in WB_CMPLT state.} +coverage exclude -line 520 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_iter_start when in WB_CMPLT state.} +coverage exclude -line 521 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_iter_start when in WB_CMPLT state.} +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 231 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb -comment {gnt_i can never be 0.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used. } +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used. } +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[3]/g_not_last_level/g_level[7]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[13]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[14]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[15]} -comment {this part of leading zero counter is not used.} From f6e264573bc18b845e5e66bef04b9cad961bb748 Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Fri, 3 May 2024 04:57:13 +0200 Subject: [PATCH 3/3] clean-up code coverage waivers on code type Expression. Not use. Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 18 -------------- .../cv32e40pv2_code_fpu_cfg_waiver.do | 24 ------------------- .../cv32e40pv2_code_pulp_cfg_waiver.do | 8 ------- 3 files changed, 50 deletions(-) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 5ded79dc1b..ebbbfbdea4 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -25,7 +25,6 @@ coverage exclude -line 140 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 142 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} coverage exclude -line 144 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} coverage exclude -line 1047 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.} -coverage exclude -line 1105 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i -comment {u_irq_enable_o never asserted. mstatus.uie never enabled.} coverage exclude -line 1047 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.} coverage exclude -line 1048 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Default of unique case not covered} coverage exclude -line 134 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} @@ -34,16 +33,7 @@ coverage exclude -line 165 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 134 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} coverage exclude -line 140 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} coverage exclude -line 165 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} -coverage exclude -line 113 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 125 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 141 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 201 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 212 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 163 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} -coverage exclude -line 174 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} -coverage exclude -line 185 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} coverage exclude -line 460 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.} -coverage exclude -line 459 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.} coverage exclude -line 549 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} coverage exclude -line 579 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} coverage exclude -line 608 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} @@ -65,18 +55,12 @@ coverage exclude -line 90 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_ coverage exclude -line 97 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {Fifo never empty when trying to push and pop at the same time.} coverage exclude -line 127 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 128 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} -coverage exclude -line 126 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 81 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never underflow the fifo.} coverage exclude -line 126 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 127 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 135 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} -coverage exclude -line 203 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.} -coverage exclude -line 204 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.} -coverage exclude -line 321 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.} -coverage exclude -line 322 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.} -coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {We are in PULP_OBI == 0 configuration. In this configuration, trans_valid is always asserted when used in this expression.} coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} @@ -138,8 +122,6 @@ coverage exclude -line 941 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 1051 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} coverage exclude -line 1062 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} coverage exclude -line 1072 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} -coverage exclude -line 299 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 844 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No PC = Hwloop1 end & Hwloop 1 counter = 0 in DECODE_HWLOOP FSM state.} coverage exclude -line 418 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } coverage exclude -line 421 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} coverage exclude -line 447 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index 058ccb89e7..276edb5b1b 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -11,8 +11,6 @@ coverage exclude -line 1353 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 1362 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} coverage exclude -line 1440 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} coverage exclude -line 1483 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} -coverage exclude -line 150 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} -coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 201 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 202 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 203 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} @@ -37,20 +35,13 @@ coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 416 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 424 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 425 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} -coverage exclude -line 458 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {flush_i set to 1'b0} coverage exclude -line 458 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {flush_i set to 1'b0} -coverage exclude -line 460 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {reg_ena_i is stuck to 0} -coverage exclude -line 464 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {Tag is stuck at 0} -coverage exclude -line 465 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {Mask is stuck at 0} coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} -coverage exclude -line 59 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} -coverage exclude -line 59 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 148 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.} coverage exclude -line 149 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.} -coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {idu_fpu_ex1_eu_sel is 0 or 4. idu_fpu_ex1_eu_sel[1] is always 0.} coverage exclude -line 155 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_src2_vld never asserted. This is expression 151.} coverage exclude -line 240 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0001. ex1_result_qnan_op0. This is always 0, comes from fdsu_special lines 282 and 294.} coverage exclude -line 240 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0001. ex1_result_qnan_op0. This is always 0, comes from fdsu_special lines 282 and 294.} @@ -87,21 +78,12 @@ coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 416 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} coverage exclude -line 417 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} coverage exclude -line 418 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} -coverage exclude -line 431 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} -coverage exclude -line 433 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} coverage exclude -line 443 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 444 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 464 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 465 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 483 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 484 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} -coverage exclude -line 540 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Both signal are acctually the same via external connection.} -coverage exclude -line 637 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {async_flush is stuck to 0. warm_up is stuck to 0. ex1_cancel is suck to 0. ex2_cancel is stuck to 0. We will never flush.} -coverage exclude -line 648 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {rtu_yy_xx_flush stuck to 0. fdsu_busy cannot be low if ctrl_sm_idle is low.} -coverage exclude -line 754 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} -coverage exclude -line 755 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} -coverage exclude -line 756 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} -coverage exclude -line 757 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} coverage exclude -line 280 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 280 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 282 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} @@ -121,11 +103,7 @@ coverage exclude -line 298 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 298 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 300 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 301 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 301 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 302 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 302 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 294 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 296 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 63 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} coverage exclude -line 63 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} coverage exclude -line 64 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} @@ -267,8 +245,6 @@ coverage exclude -line 208 -code b -allfalse -scope {/uvmt_cv32e40p_tb/dut_wrap/ coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} coverage exclude -line 209 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} coverage exclude -line 213 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {We never use cast and pack.} -coverage exclude -line 458 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/target_regs} -comment {No vector floating point operation.} -coverage exclude -line 476 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/target_regs} -comment {No vector floating point operation.} coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do index 494debe1e6..dd912631bf 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do @@ -12,10 +12,6 @@ coverage exclude -line 205 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 211 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 237 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 241 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 215 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 217 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 474 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 476 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 205 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 211 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 211 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} @@ -27,8 +23,6 @@ coverage exclude -line 1559 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 1560 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 1561 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 1562 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 920 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 1679 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 529 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 1557 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration. } coverage exclude -line 236 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} @@ -55,8 +49,6 @@ coverage exclude -line 266 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 272 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 284 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} -coverage exclude -line 3000 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} -coverage exclude -line 1390 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} coverage exclude -line 89 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 91 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.}