From 998eb342d8d5e510be5162ff067934d0bc3d81d1 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 2 May 2024 16:39:58 +0200 Subject: [PATCH] Added new test cases to improve RTL code coverage. Signed-off-by: Pascal Gouedo --- .../illegal_fp_instr_test.S | 17 ++++++++++++++++- .../zfinx_func_cov_improve_test.S | 12 +++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S b/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S index bbb238865a..50b7837ab9 100644 --- a/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S +++ b/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S @@ -11,7 +11,7 @@ #define TEST_FAIL 1 #define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 -#define EXPECTED_ILLEGAL_INSTRUCTIONS 31741 +#define EXPECTED_ILLEGAL_INSTRUCTIONS 31751 main: li t0, (0x1 << 3) @@ -31770,6 +31770,21 @@ main: .word(0x0151dfd3) .word(0xadf06543) .word(0xadf05543) + csrwi frm, 4 + .word(0xadf05543) + .word(0x0151dfd3) + csrwi frm, 3 + .word(0x0151dfd3) + .word(0xadf05543) + csrwi frm, 2 + .word(0x0151dfd3) + .word(0xadf05543) + csrwi frm, 1 + .word(0x0151dfd3) + .word(0xadf05543) + csrwi frm, 0 + .word(0x0151dfd3) + .word(0xadf05543) li x18, TEST_PASS li x16, EXPECTED_ILLEGAL_INSTRUCTIONS diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S index fb1df55b06..c6537d6e36 100644 --- a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S +++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S @@ -3695,9 +3695,19 @@ _fsgnjx_jr31: fsgnjx.s x31, x31, x31 # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end ######### FOR PULP_FPU CFG - END ######### - li x18, TEST_PASS + ######### Added for ex_stage hole coverage ######### + la x1, test_end + li x2, 1 + fcvt.s.w x2, x2 + + fdiv.s x3, x1, x2 + div x4, x5, x0 + jalr x0, x3, 0 + ######### End for ex_stage hole coverage ######### test_end: + li x18, TEST_PASS + li x17, VIRT_PERIPH_STATUS_FLAG_ADDR sw x18,0(x17) j _exit