From 098380dc69cc8f79dfb0043131eb44c6e1bbb879 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 25 Apr 2024 11:38:14 +0200 Subject: [PATCH 01/14] Added new testcase in pulp_hardware_loop test with ecall in a single HWloop 1 execution to improve RTL code coverage of line 630 of v1.7.0 cv32e40p_controller module. Signed-off-by: Pascal Gouedo --- .../pulp_hardware_loop/pulp_hardware_loop.S | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S b/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S index bd9512a1c5..ebc13066af 100644 --- a/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S +++ b/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S @@ -22,6 +22,8 @@ .globl _start .globl main .globl exit +.global endO_9 +.global startO_9 .section .text .global test_results test_results: @@ -424,6 +426,34 @@ endO_8: c.addi x15, 0x1 test8_1: + li x21, 20 + beq x21, x18, test9 + c.addi x15, 0x1 + +# test9 + +test9: + cv.counti 0, 0 + cv.counti 1, 0 + li x17, 0 + li x18, 0 + + .balign 4 + + cv.starti 1, startO_9 + cv.endi 1, endO_9 + cv.counti 1, 10 +startO_9: + + .option norvc + + addi x18, x18, 1 + ecall + addi x18, x18, 1 +endO_9: + + .option rvc + li x21, 20 beq x21, x18, exit_check c.addi x15, 0x1 From 676afd1b7745e395c7669bb64f0fa396a4b7e0fc Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 25 Apr 2024 12:57:23 +0200 Subject: [PATCH 02/14] Added new test with ebreak in a single HWloop 0 execution to improve RTL code coverage of lines 722, 771 and 773 of v1.7.0 cv32e40p_controller module. Made it auto-modifying to replace ebreak after one execution. Signed-off-by: Pascal Gouedo --- .../debug_hwloop_test/debug_hwloop_test.c | 238 ++++++++++++ .../custom/debug_hwloop_test/debugger.S | 268 ++++++++++++++ .../debug_hwloop_test/debugger_exception.S | 76 ++++ .../custom/debug_hwloop_test/handlers.S | 347 ++++++++++++++++++ .../custom/debug_hwloop_test/test.yaml | 9 + .../custom/debug_hwloop_test/trigger_code.S | 158 ++++++++ 6 files changed, 1096 insertions(+) create mode 100644 cv32e40p/tests/programs/custom/debug_hwloop_test/debug_hwloop_test.c create mode 100644 cv32e40p/tests/programs/custom/debug_hwloop_test/debugger.S create mode 100644 cv32e40p/tests/programs/custom/debug_hwloop_test/debugger_exception.S create mode 100644 cv32e40p/tests/programs/custom/debug_hwloop_test/handlers.S create mode 100644 cv32e40p/tests/programs/custom/debug_hwloop_test/test.yaml create mode 100644 cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/debug_hwloop_test.c b/cv32e40p/tests/programs/custom/debug_hwloop_test/debug_hwloop_test.c new file mode 100644 index 0000000000..56a853da4e --- /dev/null +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/debug_hwloop_test.c @@ -0,0 +1,238 @@ +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +******************************************************************************* +** Basic debugger test. Needs more work and bugs fixed +** It will launch a debug request and have debugger code execute (debugger.S) +******************************************************************************* +*/ + +#include +#include +#include + +volatile int glb_hart_status = 0; // Written by main code only, read by debug code +volatile int glb_debug_status = 0; // Written by debug code only, read by main code +volatile int glb_ebreak_status = 0; // Written by ebreak code only, read by main code +volatile int glb_illegal_insn_status = 0; // Written by illegal instruction code only, read by main code +volatile int glb_debug_exception_status = 0; // Written by debug code during exception only +volatile int glb_exception_ebreak_status = 0; // Written by main code, read by exception handler + +volatile int glb_previous_dpc = 0; // holds last dpc, used for checking correctness of stepping +volatile int glb_step_info = 0; // info to dbg code about actions to take on stepping +volatile int glb_step_count = 0; // Written by debug code for each time single step is entered +// Expectation flags. Raise an error if handler or routine is enterred when not expected, +volatile int glb_expect_illegal_insn = 0; +volatile int glb_expect_ebreak_handler = 0; +volatile int glb_expect_debug_entry = 0; +volatile int glb_expect_debug_exception = 0; +volatile int glb_expect_irq_entry = 0; +volatile int glb_irq_timeout = 0; +// Counter values +// Checked at start and end of debug code +// Only lower 32 bits checked, as simulation cannot overflow on 32 bits +volatile int glb_mcycle_start = 0; +volatile int glb_mcycle_end = 0; +volatile int glb_minstret_start = 0; +volatile int glb_minstret_end = 0; +#define TEST_FAILED *(volatile int *)0x20000000 = 1 +#define TEST_PASSED *(volatile int *)0x20000000 = 123456789 + +extern int __stack_start; +extern int __debugger_stack_start; +typedef union { + struct { + unsigned int start_delay : 15; // 14: 0 + unsigned int rand_start_delay : 1; // 15 + unsigned int pulse_width : 13; // 28:16 + unsigned int rand_pulse_width : 1; // 29 + unsigned int pulse_mode : 1; // 30 0 = level, 1 = pulse + unsigned int value : 1; // 31 + } fields; + unsigned int bits; +} debug_req_control_t; + +#define DEBUG_REQ_CONTROL_REG *(volatile int *)0x15000008 +#define TIMER_REG_ADDR ((volatile uint32_t *) 0x15000000) +#define TIMER_VAL_ADDR ((volatile uint32_t *) 0x15000004) + +typedef union { + struct { + unsigned int uie : 1; // 0 // Implemented if USER mode enabled + unsigned int sie : 1; // 1 + unsigned int wpri : 1; // 2 + unsigned int mie : 1; // 3 // Implemented + unsigned int upie : 1; // 4 // Implemented if USER mode enabled + unsigned int spie : 1; // 5 + unsigned int wpri0 : 1; // 6 + unsigned int mpie : 1; // 7 // Implemented + unsigned int spp : 1; // 8 + unsigned int wpri1 : 2; // 10: 9 + unsigned int mpp : 2; // 12:11 // Implemented + unsigned int fs : 2; // 14:13 + unsigned int xs : 2; // 16:15 + unsigned int mprv : 1; // 17 + unsigned int sum : 1; // 18 + unsigned int mxr : 1; // 19 + unsigned int tvm : 1; // 20 + unsigned int tw : 1; // 21 + unsigned int tsr : 1; // 22 + unsigned int wpri3 : 8; // 30:23 + unsigned int sd : 1; // 31 + } fields; + unsigned int bits; +} mstatus_t; + +extern void _single_step(int d); + +// Tag is simply to help debug and determine where the failure came from +void check_debug_status(int tag, int value) +{ + if(glb_debug_status != value){ + printf("ERROR: check_debug_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", + tag, value, tag, glb_debug_status, value); + TEST_FAILED; + } +} +void check_debug_exception_status(int tag, int value) +{ + if(glb_debug_exception_status != value){ + printf("ERROR: check_debug_exception_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", + tag, value, tag, glb_debug_exception_status, value); + TEST_FAILED; + } +} +void check_hart_status(int tag, int value) +{ + if(glb_hart_status != value){ + printf("ERROR: check_hart_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", + tag, value, tag, glb_hart_status, value); + TEST_FAILED; + } +} +void check_ebreak_status(int tag, int value) +{ + if(glb_ebreak_status != value){ + printf("ERROR: check_ebreak_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", + tag, value, tag, glb_ebreak_status, value); + TEST_FAILED; + } +} +void check_illegal_insn_status(int tag, int value) +{ + if(glb_illegal_insn_status != value){ + printf("ERROR: check_illegal_insn_status(%d, %d): Tag=%d status=%d, exp=%d \n\n", + tag, value, tag, glb_illegal_insn_status, value); + TEST_FAILED; + } +} +void delay(int count) { + for (volatile int d = 0; d < count; d++); +} + +void mstatus_mie_enable() { + int mie_bit = 0x1 << 3; + asm volatile("csrrs x0, mstatus, %0" : : "r" (mie_bit)); +} + +void mstatus_mie_disable() { + int mie_bit = 0x1 << 3; + asm volatile("csrrc x0, mstatus, %0" : : "r" (mie_bit)); +} + +void mie_enable_all() { + uint32_t mie_mask = (uint32_t) -1; + asm volatile("csrrs x0, mie, %0" : : "r" (mie_mask)); +} + +void mie_disable_all() { + uint32_t mie_mask = (uint32_t) -1; + asm volatile("csrrc x0, mie, %0" : : "r" (mie_mask)); +} + +void mie_enable(uint32_t irq) { + // Enable the interrupt irq in MIE + uint32_t mie_bit = 0x1 << irq; + asm volatile("csrrs x0, mie, %0" : : "r" (mie_bit)); +} + +void mie_disable(uint32_t irq) { + // Disable the interrupt irq in MIE + uint32_t mie_bit = 0x1 << irq; + asm volatile("csrrc x0, mie, %0" : : "r" (mie_bit)); +} + +void mm_ram_assert_irq(uint32_t mask, uint32_t cycle_delay) { + *TIMER_REG_ADDR = mask; + *TIMER_VAL_ADDR = 1 + cycle_delay; +} + +void counters_enable() { + // Enable counters mcycle (bit0) and minstret (bit2) + uint32_t mask = 1<<2 | 1<<0; + asm volatile("csrrc x0, 0x320, %0" : : "r" (mask)); +} +#define MACHINE 3 +int main(int argc, char *argv[]) +{ + unsigned int temp,temp1,temp2; + debug_req_control_t debug_req_control; + mstatus_t mstatus, mstatus_cmp; + counters_enable(); + + printf("------------------------\n"); + printf(" Test CSR access and default values in debug mode\n"); + debug_req_control = (debug_req_control_t) { + .fields.value = 1, + .fields.pulse_mode = 1, //PULSE Mode + .fields.rand_pulse_width = 0, + .fields.pulse_width = 5,// FIXME: BUG: one clock pulse cause core to lock up + .fields.rand_start_delay = 0, + .fields.start_delay = 200 + }; + glb_hart_status = 6; + glb_expect_debug_entry = 1; + DEBUG_REQ_CONTROL_REG = debug_req_control.bits; + while(glb_debug_status != glb_hart_status){ + printf("Wait for Debugger\n"); + } + check_debug_status(61,glb_hart_status); + + printf("------------------------\n"); + printf("Test : Execute HWloop in debug rom\n"); + glb_hart_status = 25; + glb_expect_debug_entry = 1; + // Does not expect irq to be taken while in debug mode + // but it will be taken when we exit from debug. + glb_expect_irq_entry = 1; + mstatus_mie_enable(); + mie_enable(30); + + *(int *)&__debugger_stack_start = 0x0; + + // Request debug + DEBUG_REQ_CONTROL_REG = debug_req_control.bits; + while(glb_debug_status != glb_hart_status){ + } + + check_debug_status(125, glb_hart_status); + + //-------------------------------- + //return EXIT_FAILURE; + printf("------------------------\n"); + printf("Finished \n"); + return EXIT_SUCCESS; +} diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/debugger.S b/cv32e40p/tests/programs/custom/debug_hwloop_test/debugger.S new file mode 100644 index 0000000000..4fe790e143 --- /dev/null +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/debugger.S @@ -0,0 +1,268 @@ + +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +******************************************************************************* +** Debugger code +******************************************************************************* +*/ + +.section .debugger, "ax" +.global _debugger_start +.global glb_debug_status +.global glb_hart_status +.global glb_expect_debug_entry +.global glb_step_info +.global glb_previous_dpc +.global glb_step_count +.global glb_irq_timeout +.global glb_mcycle_start +.global glb_mcycle_end +.global glb_minstret_start +.global glb_minstret_end +.global __debugger_stack_start +.global _debugger_fail +.global _debugger_end +.set test_ret_val, 0x20000000 +.set test_fail, 0x1 + +_debugger_start: + // Debugger Stack + csrw dscratch, a0 // dscratch0 + la a0, __debugger_stack_start + //sw t0, 0(a0) + csrw 0x7b3, t0 // dscratch1 + sw t1, 4(a0) + sw t2, 8(a0) + sw a1, 12(a0) + sw a2, 16(a0) + sw t3, 20(a0) + // Check if expecting debug entry + la a1, glb_expect_debug_entry + lw t1, 0(a1) + beq x0,t1,_debugger_fail + + // Read lower 32 bits of mcycle and minstret + // and store in globals for check at exit + csrr t1, mcycle + csrr t2, minstret + la a1, glb_mcycle_start + sw t1, 0(a1) + la a1, glb_minstret_start + sw t2, 0(a1) + + // Determine Test to execute in debugger code based on glb_hart_status + la a2, glb_hart_status + lw t2, 0(a2) + + // ebreak test will loop in debugger code over several iterations + // and will increment the global status each time + li t0,5 + beq t2,t0,_debugger_ebreak // Test 5 + + // For all other tests, + // Set debug status = hart status + la a1, glb_debug_status + sw t2, 0(a1) + + li t0,10 + beq t2,t0,_debugger_ebreak_entry // Test 10 + + li t0,12 + beq t2,t0,_debugger_ecall_exception // Test 12 + + li t0,14 + beq t2,t0, _debugger_ebreak_entry // Test 14 + + li t0, 19 + beq t2, t0, _debugger_irq + + li t0, 20 + beq t2, t0, _debugger_req_and_irq + + li t0, 25 + beq t2, t0, _debugger_hwloop + +_debugger_req_and_irq: + // Debug was requested at the same cycle as irq + // Check dpc to see that pc is not at irq handler + // IRQ used was 30, so addr would be 30*4=120, 0x78 + csrr t0, dpc + li t1, 0x78 + beq t0, t1, _debugger_fail + j _debugger_end + +_debugger_irq: + // Assert irq + li a1, 0x15000000 + li t0, 0x40000000 + sw t0, 0(a1) + li a1, 0x15000004 + li t0, 2 + sw t0, 0(a1) + + li t1, 1000 +// Wait for 1000 cycles, then timeout +_irq_wait_loop: + la a1, glb_expect_irq_entry + lw t0, 0(a1); + beq t1, x0, _irq_loop_end + addi t1, t1, -1 + bne t0, x0, _irq_wait_loop +_irq_loop_end: + la a1, glb_irq_timeout + sw t1, 0(a1) + j _debugger_end + +_debugger_ecall_exception: + ecall // exception + +_debugger_ebreak_entry: + la a1, glb_debug_status + li t1, 4<<28 | 1<<6 | 3<<0 | 1<<15 + csrr t2,dcsr + bne t1,t2,_debugger_fail + csrr a1,dpc + addi a1,a1,4 # uncompressed ebreak used to enter debug here + csrw dpc,a1 + //sw t1, 0(a1) + j _debugger_end + +_debugger_ebreak: + li t0, 4<<28 | 3<<6 | 3<<0 + csrr t1, dcsr + bne t0, t1, _debugger_fail + // Increment glb_debug_status + la a1, glb_debug_status + lw t1, 0(a1) + addi t1,t1,1 + sw t1, 0(a1) + // Repeat executing debug code until debug status = hart_status + 3 + addi t0, t2, 3 + beq t1, t0, _debugger_end + // Execute non-compressed ebreak for iteration 2 + addi t0, t2, 2 + beq t1, t0, _uncompressed_ebreak + // Debugger Un-Stack and call debugger code from start using ebreak + csrr t0, 0x7b3 + lw t1, 4(a0) + lw t2, 8(a0) + lw a1, 12(a0) + lw a2, 16(a0) + csrr a0, dscratch + ebreak +_uncompressed_ebreak: + // Debugger Un-Stack and call debugger code from start using ebreak + csrr t0, 0x7b3 + lw t1, 4(a0) + lw t2, 8(a0) + lw a1, 12(a0) + lw a2, 16(a0) + csrr a0, dscratch + .4byte 0x00100073 # ebreak + +_debugger_hwloop: + lw t3, 0(a0) + cv.bneimm t3, 0, replace_ebreak + li t3, 1 // To avoid to endlessly re-execute HWloop due to ebreak inside HWloop + sw t3, 0(a0) + + li a1, 0x15000000 + li t3, 0x40000000 + sw t3, 0(a1) + li a1, 0x15000004 + li t3, 3 + sw t3, 0(a1) + + li t1, 0 + + .balign 4 + + cv.starti 0, startZ_7_1 + cv.endi 0, endZ_7_1 + cv.counti 0, 10 + + .option norvc + +startZ_7_1: + addi t1, t1, 1 + addi t1, t1, 1 + addi t1, t1, 1 +to_replace: + ebreak + addi t1, t1, 1 +endZ_7_1: + + .option rvc + + li t2, 50 + bne t1, t2, _debugger_fail + j _debugger_end + +replace_ebreak: + li t2, 0x00130313 // put back addi t1, t1, 1 in place of ebreak + la a1, to_replace + sw t2, 0(a1) + + li t1, 3 + + j to_replace + +_debugger_end: + // Check counter values. They should have increased while in debug + // regardless of stopcount bit in csr + csrr t1, mcycle + la a1, glb_mcycle_start + lw t2, 0(a1) + sub t1, t1, t2 + beq t1, x0, _debugger_fail + + csrr t1, minstret + la a1, glb_minstret_start + lw t2, 0(a1) + sub t1, t1, t2 + beq t1, x0, _debugger_fail + + // If single stepping, do not clear + la a1, glb_hart_status + lw t0, 0(a1) + li t1, 18 + beq t0, t1, _debugger_end_continue + + // Clear debug entry expectation flag + la a1, glb_expect_debug_entry + sw x0, 0(a1) +_debugger_end_continue: + // Debugger Un-Stack + //lw t0, 0(a0) + la a0, __debugger_stack_start + csrr t0, 0x7b3 + lw t1, 4(a0) + lw t2, 8(a0) + lw a1, 12(a0) + lw a2, 16(a0) + lw t3, 20(a0) + csrr a0, dscratch + dret +_debugger_fail: //Test Failed + li a0, test_ret_val + li t0, test_fail + sw t0, 0(a0) + nop + nop + nop + nop + diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/debugger_exception.S b/cv32e40p/tests/programs/custom/debug_hwloop_test/debugger_exception.S new file mode 100644 index 0000000000..f5a67ca927 --- /dev/null +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/debugger_exception.S @@ -0,0 +1,76 @@ + +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +******************************************************************************* +** Debugger Exception code +******************************************************************************* +*/ + +.section .debugger_exception, "ax" +.global _debugger_exception_start +.global glb_debug_status +.global glb_hart_status +.global glb_debug_exception_status +.global glb_expect_debug_exception +//.global _debugger_fail +//.global _debugger_end + .set test_ret_val, 0x20000000 +.set test_fail, 0x1 + +_debugger_exception_start: + // First check to see if exception was expected + la a1, glb_expect_debug_exception + lw t1, 0(a1) + //beq x0,t1,_debugger_fail + beq x0,t1,_debugger_exception_fail + + // Set exception status to hart status + la a1, glb_hart_status + lw t1, 0(a1) + la a2, glb_debug_exception_status + sw t1, 0(a2) + + //j _debugger_end + j _debugger_exception_end + +// Should be exact same function as implmented in debugger.S + // I can't seem to point to that symble from this file +_debugger_exception_end: + // Clear debug entry expectation flag + la a1, glb_expect_debug_entry + sw x0, 0(a1) + la a1, glb_expect_debug_exception + sw x0, 0(a1) + // Debugger Un-Stack + //lw t0, 0(a0) + csrr t0, 0x7b3 + lw t1, 4(a0) + lw t2, 8(a0) + lw a1, 12(a0) + lw a2, 16(a0) + csrr a0, dscratch + dret +// Should be exact same function as implmented in debugger.S +_debugger_exception_fail: + li a0, test_ret_val + li t0, test_fail + sw t0, 0(a0) + nop + nop + nop + nop + diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/handlers.S b/cv32e40p/tests/programs/custom/debug_hwloop_test/handlers.S new file mode 100644 index 0000000000..c28bcade01 --- /dev/null +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/handlers.S @@ -0,0 +1,347 @@ +/* +* Copyright 2019 ETH Zürich and University of Bologna +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/* Exception codes */ +#define EXCEPTION_ILLEGAL_INSN 2 +#define EXCEPTION_BREAKPOINT 3 +#define EXCEPTION_ECALL_M 11 + +.section .text.handlers +.global __no_irq_handler +.global u_sw_irq_handler +.global m_software_irq_handler +.global m_timer_irq_handler +.global m_external_irq_handler +.global m_fast0_irq_handler +.global m_fast1_irq_handler +.global m_fast2_irq_handler +.global m_fast3_irq_handler +.global m_fast4_irq_handler +.global m_fast5_irq_handler +.global m_fast6_irq_handler +.global m_fast7_irq_handler +.global m_fast8_irq_handler +.global m_fast9_irq_handler +.global m_fast10_irq_handler +.global m_fast11_irq_handler +.global m_fast12_irq_handler +.global m_fast13_irq_handler +.global m_fast14_irq_handler +.global m_fast15_irq_handler + +.weak m_software_irq_handler +.weak m_timer_irq_handler +.weak m_external_irq_handler +.weak m_fast0_irq_handler +.weak m_fast1_irq_handler +.weak m_fast2_irq_handler +.weak m_fast3_irq_handler +.weak m_fast4_irq_handler +.weak m_fast5_irq_handler +.weak m_fast6_irq_handler +.weak m_fast7_irq_handler +.weak m_fast8_irq_handler +.weak m_fast9_irq_handler +.weak m_fast10_irq_handler +.weak m_fast11_irq_handler +.weak m_fast12_irq_handler +.weak m_fast13_irq_handler +.weak m_fast14_irq_handler +.weak m_fast15_irq_handler + +.global glb_illegal_insn_status +.global glb_ebreak_status +.global glb_expect_illegal_insn +.global glb_expect_ebreak_handler +.global glb_exception_ebreak_status +.global glb_expect_irq_entry +.set test_ret_val, 0x20000000 +.set test_fail, 0x1 + +/* exception handling */ +__no_irq_handler: + addi sp,sp,-64 + sw ra, 0(sp) + sw a0, 4(sp) + sw a1, 8(sp) + sw a2, 12(sp) + sw a3, 16(sp) + sw a4, 20(sp) + sw a5, 24(sp) + sw a6, 28(sp) + sw a7, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +# la a0, no_exception_handler_msg +# jal ra, puts + + // Check if we expected to enter irq + la a1, glb_expect_irq_entry + lw t0, 0(a1) + beq t0, x0, _irq_fail + + // Clear entry flag + li t0, 0 + sw t0, 0(a1) + //j __no_irq_handler + + // Return + lw ra, 0(sp) + lw a0, 4(sp) + lw a1, 8(sp) + lw a2, 12(sp) + lw a3, 16(sp) + lw a4, 20(sp) + lw a5, 24(sp) + lw a6, 28(sp) + lw a7, 32(sp) + lw t0, 36(sp) + lw t1, 40(sp) + lw t2, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + addi sp,sp,64 + mret + +_irq_fail: + li a0, test_ret_val + li t0, test_fail + sw t0, 0(a0) + ret + +u_sw_irq_handler: + /* While we are still using puts in handlers, save all caller saved + regs. Eventually, some of these saves could be deferred. */ + addi sp,sp,-64 + sw ra, 0(sp) + sw a0, 4(sp) + sw a1, 8(sp) + sw a2, 12(sp) + sw a3, 16(sp) + sw a4, 20(sp) + sw a5, 24(sp) + sw a6, 28(sp) + sw a7, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + csrr t0, mcause + li t1, EXCEPTION_ILLEGAL_INSN + beq t0, t1, handle_illegal_insn + li t1, EXCEPTION_ECALL_M + beq t0, t1, handle_ecall + li t1, EXCEPTION_BREAKPOINT + beq t0, t1, handle_ebreak + j handle_unknown + +handle_ecall: + la a0, ecall_msg + jal ra, handle_syscall + j end_handler_incr_mepc + +m_software_irq_handler: + j __no_irq_handler + +m_timer_irq_handler: + j __no_irq_handler + +m_external_irq_handler: + j __no_irq_handler + +m_fast0_irq_handler: + j __no_irq_handler + +m_fast1_irq_handler: + j __no_irq_handler + +m_fast2_irq_handler: + j __no_irq_handler + +m_fast3_irq_handler: + j __no_irq_handler + +m_fast4_irq_handler: + j __no_irq_handler + +m_fast5_irq_handler: + j __no_irq_handler + +m_fast6_irq_handler: + j __no_irq_handler + +m_fast7_irq_handler: + j __no_irq_handler + +m_fast8_irq_handler: + j __no_irq_handler + +m_fast9_irq_handler: + j __no_irq_handler + +m_fast10_irq_handler: + j __no_irq_handler + +m_fast11_irq_handler: + j __no_irq_handler + +m_fast12_irq_handler: + j __no_irq_handler + +m_fast13_irq_handler: + j __no_irq_handler + +m_fast14_irq_handler: + j __no_irq_handler + +m_fast15_irq_handler: + j __no_irq_handler + + +handle_ebreak: + /* TODO support debug handling requirements. */ + la a0, ebreak_msg + jal ra, puts + // Check if expecting ebreak handler + la a0, glb_expect_ebreak_handler + lw t0, 0(a0) + bne t0, x0, cont_handle_ebreak + // Not expecting ebreak, assert test failed + li a0, test_ret_val + li t0, 1 + sw t0, 0(a0) + j end_handler_incr_mepc +cont_handle_ebreak: + //increment hart status + sw x0, 0(a0) + la a0, glb_ebreak_status + lw t0, 0(a0) + addi t0,t0,1 + sw t0, 0(a0) + j end_handler_incr_mepc + + + +handle_illegal_insn: + la a0, illegal_insn_msg + jal ra, puts + // Check if expecting illegal instruction + la a0, glb_expect_illegal_insn + lw t0, 0(a0) + bne t0, x0, cont_illegal_insn + li a0, test_ret_val + li t0, 1 + sw t0, 0(a0) //Test Failed + j end_handler_incr_mepc +cont_illegal_insn: + //increment hart status + sw x0, 0(a0) + la a0, glb_illegal_insn_status + lw t0, 0(a0) + addi t0,t0,1 + sw t0, 0(a0) + + // Check if we are expected to execute ebreak + la a0, glb_exception_ebreak_status + lw t0, 0(a0) + // End handler if no ebreak is to be executed + beq t0, x0, end_handler_incr_mepc + + // Clear ebreak flag + sw x0, 0(a0) + // Execute ebreak + .4byte 0x00100073 + // Exit handler + j end_handler_incr_mepc + + j end_handler_incr_mepc + + + + + + + +handle_unknown: + la a0, unknown_msg + jal ra, puts + /* We don't know what interrupt/exception is being handled, so don't + increment mepc. */ + j end_handler_ret + + + + + + +end_handler_incr_mepc: + csrr t0, mepc + lb t1, 0(t0) + li a0, 0x3 + and t1, t1, a0 + /* Increment mepc by 2 or 4 depending on whether the instruction at mepc + is compressed or not. */ + bne t1, a0, end_handler_incr_mepc2 + addi t0, t0, 2 +end_handler_incr_mepc2: + addi t0, t0, 2 + csrw mepc, t0 +end_handler_ret: + lw ra, 0(sp) + lw a0, 4(sp) + lw a1, 8(sp) + lw a2, 12(sp) + lw a3, 16(sp) + lw a4, 20(sp) + lw a5, 24(sp) + lw a6, 28(sp) + lw a7, 32(sp) + lw t0, 36(sp) + lw t1, 40(sp) + lw t2, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + addi sp,sp,64 + mret +/* this interrupt can be generated for verification purposes, random or when the + PC is equal to a given value*/ +verification_irq_handler: + mret + +.section .rodata +illegal_insn_msg: + .string "illegal instruction exception handler entered\n" +ecall_msg: + .string "ecall exception handler entered\n" +ebreak_msg: + .string "ebreak exception handler entered\n" +unknown_msg: + .string "unknown exception handler entered\n" +no_exception_handler_msg: + .string "no exception handler installed\n" diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/test.yaml b/cv32e40p/tests/programs/custom/debug_hwloop_test/test.yaml new file mode 100644 index 0000000000..05b3907646 --- /dev/null +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/test.yaml @@ -0,0 +1,9 @@ +# Test definition YAML for test + +# Debug directed test +name: debug_hwloop_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +program: debug_hwloop_test +description: > + Debug directed test with HWloop execution + diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S b/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S new file mode 100644 index 0000000000..299aad770f --- /dev/null +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S @@ -0,0 +1,158 @@ +#Copyright 202[x] Silicon Labs, Inc. +# +#This file, and derivatives thereof are licensed under the +#Solderpad License, Version 2.0 (the "License"); +#Use of this file means you agree to the terms and conditions +#of the license and are in full compliance with the License. +#You may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.0/ +# +#Unless required by applicable law or agreed to in writing, software +#and hardware implementations thereof +#distributed under the License is distributed on an "AS IS" BASIS, +#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, EITHER EXPRESSED OR IMPLIED. +#See the License for the specific language governing permissions and +#limitations under the License. + +.section .trigger_code_sect, "ax" +.set test_ret_val, 0x20000000 +.set test_fail, 0x1 + +.global _trigger_exit +.global _trigger_test +.global _trigger_code +.global _trigger_test_ebreak +.global _trigger_code_ebreak +.global _trigger_code_illegal_insn +.global _trigger_code_branch_insn +.global _trigger_code_multicycle_insn +.global _trigger_code_cebreak +.type _trigger_code, @function +.type _trigger_code_ebreak, @function +.type _trigger_code_cebreak, @function +.type _trigger_code_illegal_insn, @function +.type _trigger_code_branch_insn, @function +.type _trigger_code_multicycle_insn, @function + + +_trigger_code_ebreak: + .4byte 0x00100073 + ret + +_trigger_code_cebreak: + c.ebreak + ret +_trigger_code_illegal_insn: + dret + ret +_trigger_code_branch_insn: + beq t0, t1, __trigger_fail + ret +_trigger_code_multicycle_insn: + mulhsu t0, t0, t1 + ret +_trigger_test_ebreak: + addi sp,sp,-30 + sw t0, 0(sp) + sw t1, 4(sp) + sw a0, 8(sp) + sw a1, 12(sp) + sw a2, 16(sp) + sw ra, 20(sp) + + # a0 holds argument + # 0 - ebreak + # 1 - c.c.ebreak + # 2 - illegal instruction + # 3 - branch instruction + # 4 - multicycle instruction (mulhsu) + + mv t1, a0 + li t0, 0 + beq t0, t1, _jmp_ebreak + + li t0, 1 + beq t0, t1, _jmp_cebreak + + li t0, 2 + beq t0, t1, _jmp_illegal_insn + + li t0, 3 + beq t0, t1, _jmp_branch_insn + + li t0, 4 + beq t0, t1, _jmp_multicycle_insn + +_jmp_ebreak: + jal ra, _trigger_code_ebreak + j __trigger_done +_jmp_cebreak: + jal ra, _trigger_code_cebreak + j __trigger_done +_jmp_illegal_insn: + jal ra, _trigger_code_illegal_insn + j __trigger_done +_jmp_branch_insn: + jal ra, _trigger_code_branch_insn + j __trigger_done +_jmp_multicycle_insn: + jal ra, _trigger_code_multicycle_insn + j __trigger_done + +# j __trigger_done + + + // We will trigger on the _trigger_code addess + // We should not expect the first instruction to execute + // The debugger code will move the PC to the trigger_exit_code + // Which essentially avoid executing all of the code in the trigger_code +_trigger_code: + add a2,a0,a1 + ret +_trigger_exit: + ret +_trigger_test: + addi sp,sp,-30 + sw t0, 0(sp) + sw t1, 4(sp) + sw a0, 8(sp) + sw a1, 12(sp) + sw a2, 16(sp) + sw ra, 20(sp) + + // a0 holds input to function (expect trigger) + mv t1, a0 + + // Load up some random data to add + li a0, 7893 + li a1, 1452 + li a2, 191 // a2 value will be overwrriten by _trigger_code + mv t2, a2 // keep a copy of the value to compare against + + // Call function that will have a trigger match + // If no trigger match, then a2=a0+a1 + // Else if trigger matched, then a2 is not modified + jal ra, _trigger_code + + // if (expect trigger) check against original value (in t2) + bne t1 ,x0, __trigger_check + // else + // trigger match not expected, function executes as normal + // set execpted value to t2 = a0 + a1 + add t2, a0, a1 +__trigger_check: + beq t2,a2,__trigger_done +__trigger_fail: + li a0, test_ret_val + li t0, 1 + sw t0, 0(a0) +__trigger_done: + lw t0, 0(sp) + lw t1, 4(sp) + lw a0, 8(sp) + lw a1, 12(sp) + lw a2, 16(sp) + lw ra, 20(sp) + addi sp,sp,30 + ret From 7bfd03060af3cbc508c6043834d0129375d0abd5 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 25 Apr 2024 12:58:26 +0200 Subject: [PATCH 03/14] Added debug_hwloop_test in cv32e40pv2_xpulp_instr.yaml for non-regression. Signed-off-by: Pascal Gouedo --- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index d17e4ceda3..e7b55d3899 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -152,6 +152,12 @@ tests: - default - no_pulp + debug_hwloop_test: + build: uvmt_cv32e40p + description: debug_hwloop_test directed test + dir: cv32e40p/sim/uvmt + cmd: make test COREV=YES TEST=debug_hwloop_test + num: 1 # ==================================================================================== # V1 legacy pulp tests From fa8bb2e5cfc0a7e0c01d9cf37a5bc51ea625ddb9 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Fri, 26 Apr 2024 12:44:33 +0200 Subject: [PATCH 04/14] Added few FPU illegal instruction cases. Signed-off-by: Pascal Gouedo --- .../custom/illegal_fp_instr_test/illegal_fp_instr_test.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S b/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S index d4f180246a..bbb238865a 100644 --- a/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S +++ b/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S @@ -11,7 +11,7 @@ #define TEST_FAIL 1 #define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 -#define EXPECTED_ILLEGAL_INSTRUCTIONS 31738 +#define EXPECTED_ILLEGAL_INSTRUCTIONS 31741 main: li t0, (0x1 << 3) @@ -31765,6 +31765,12 @@ main: ######### END OF GENERATED CODE ######### + ######### Manually added ######### + csrwi frm, 5 + .word(0x0151dfd3) + .word(0xadf06543) + .word(0xadf05543) + li x18, TEST_PASS li x16, EXPECTED_ILLEGAL_INSTRUCTIONS beq x31, x16, test_end From 88639fdd293d80400cbe9540ad64ac80acaa35f1 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Fri, 26 Apr 2024 12:57:23 +0200 Subject: [PATCH 05/14] Improved pulp_hardware_loop_debug_test to use it with any configuration. Signed-off-by: Pascal Gouedo --- cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml | 11 ----------- .../pulp_hardware_loop_debug_test/single_step.S | 2 ++ 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml index e7b55d3899..3ad5af78c4 100644 --- a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml @@ -140,17 +140,6 @@ tests: dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=pulp_hardware_loop_debug_test num: 1 - skip_sim: - - pulp - - pulp_fpu - - pulp_fpu_1cyclat - - pulp_fpu_2cyclat - - pulp_cluster - - pulp_cluster_fpu - - pulp_cluster_fpu_1cyclat - - pulp_cluster_fpu_2cyclat - - default - - no_pulp debug_hwloop_test: build: uvmt_cv32e40p diff --git a/cv32e40p/tests/programs/custom/pulp_hardware_loop_debug_test/single_step.S b/cv32e40p/tests/programs/custom/pulp_hardware_loop_debug_test/single_step.S index 3f6619c4fa..b5516b8f90 100644 --- a/cv32e40p/tests/programs/custom/pulp_hardware_loop_debug_test/single_step.S +++ b/cv32e40p/tests/programs/custom/pulp_hardware_loop_debug_test/single_step.S @@ -198,7 +198,9 @@ startO_3: startZ_3: addi x17, x17, 5 addi x18, x18, 6 +#ifdef ZFINX fdiv.s x19, x18, x17 +#endif endZ_3: addi x20, x20, 4 addi x20, x20, 4 From 502f201c748acd4b14a9b7fb80540fa177067c13 Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Mon, 29 Apr 2024 05:34:57 +0200 Subject: [PATCH 06/14] Update waiver line number changes on cv32e40p_decoder following RTL v1.8.0 Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 6 ++--- .../cv32e40pv2_code_fpu_cfg_waiver.do | 22 +++++++++++-------- .../cv32e40pv2_code_pulp_cfg_waiver.do | 2 +- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 3708b08bc1..021960d300 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -80,9 +80,9 @@ coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} -coverage exclude -line 2767 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} -coverage exclude -line 2765 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} -coverage exclude -line 2765 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2784 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2782 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} +coverage exclude -line 2782 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreacheable code as cur_priv_lvl_i is at maximum value.} coverage exclude -line 419 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } coverage exclude -line 451 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -line 452 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index 3a989338f0..ed110a0758 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -1,12 +1,16 @@ -coverage exclude -line 1269 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1270 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1271 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1279 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1280 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1300 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1301 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} -coverage exclude -line 1302 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1264 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1265 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1266 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1273 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1274 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1275 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1296 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1297 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Unreachable since C_XF16ALT is unsupported} +coverage exclude -line 1353 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} +coverage exclude -line 1362 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} +coverage exclude -line 1440 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} +coverage exclude -line 1483 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} coverage exclude -line 150 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 201 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do index 696a7ccec9..494debe1e6 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do @@ -55,7 +55,7 @@ coverage exclude -line 266 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 272 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 284 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} -coverage exclude -line 2983 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} +coverage exclude -line 3000 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} coverage exclude -line 1390 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} coverage exclude -line 89 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} From 013b3c0a25580ce042a46c0b5c0c20bf93307864 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 29 Apr 2024 16:34:01 +0200 Subject: [PATCH 07/14] Updated num_mhphcounter_29.yaml config file. Signed-off-by: Pascal Gouedo --- cv32e40p/tests/cfg/num_mhpmcounter_29.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml b/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml index fb1e4b053c..10e21c45f1 100644 --- a/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml +++ b/cv32e40p/tests/cfg/num_mhpmcounter_29.yaml @@ -1,12 +1,13 @@ name: num_mhpmcounters_29 description: Configuration for CV32E40P simulations with NUM_MHPMCOUNTER set to 29 compile_flags: - +define+NO_PULP+SET_NUM_MHPMCOUNTERS=29 + +define+NO_PULP +define+SET_NUM_MHPMCOUNTERS=29 ovpsim: > --override cpu/misa_Extensions=0x001104 --override cpu/compress_version=1.0.0-RC5.7 --override cpu/show_c_prefix=T - --override cpu/noinhibit_mask=0000000000 + --override cpu/noinhibit_mask=0x00000000 + --override cpu/extension_CVE4P/mcountinhibit_reset=0xfffffffd --override cpu/marchid=4 --override cpu/extension_CVE4P/CORE_VERSION=1 --override cpu/extension_CVE4P/COREV_PULP=F From 1fefb97931b033851c5afab40c538ae845e68e57 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 29 Apr 2024 16:34:52 +0200 Subject: [PATCH 08/14] Added ZFINX in generic_exception_test to check different number of errors. Signed-off-by: Pascal Gouedo --- .../generic_exception_test/generic_exception_test.S | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S b/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S index 99d601fe61..108a345d71 100644 --- a/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S +++ b/cv32e40p/tests/programs/custom/generic_exception_test/generic_exception_test.S @@ -42,16 +42,23 @@ # there are 2 env calls in the code # there are 5 breakpoints in the code # there are 129 unknown encodings (minus 2 because of 2 last instructions unused fields in fence), 2 unimp corresponding to .word 00000000, 1 (uret), 29 illegal CSR access = 9d -# For FPU-enabled configuration, letting mstatus_FS at default value lead to the same number of illegal instrucions +# For FPU-enabled configuration, letting mstatus_FS at default value lead to the same number of illegal instructions. +# Pascal Gouedo comment: Last sentence not true anymore as in Zfinx extension, mstatus_FS does not exist and FCSRs accesses don't lead to IIE. +# So removed 3 to illegal CSR access giving 9a for magic number in ZFINX configurations. + +#ifndef ZFINX #define MAGIC_NUMBER 0x259d +#else +#define MAGIC_NUMBER 0x259a +#endif test_results: .word 123456789 # main test main: li x15, 0x00001800 - csrrw x0, mstatus, x15 # redundant in cv32e40p: hardwired PoR value + csrrw x0, mstatus, x15 li x0, 0xf21ee7dc li x1, 0x80000000 li x3, 0xccda4374 From c4eb1f71167c0a927e213d44255f9e57a7062b88 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 30 Apr 2024 13:30:43 +0800 Subject: [PATCH 09/14] Fix restore context steps for csr mscratch Signed-off-by: dd-baoshan --- .../env/corev-dv/cv32e40p_instr_test_pkg.sv | 30 ++++++++++++------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv index 9ec248f1f4..8825925518 100644 --- a/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv +++ b/cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv @@ -118,19 +118,24 @@ package cv32e40p_instr_test_pkg; // Push general purpose register to the debugger stack function automatic void push_gpr_to_debugger_stack(cv32e40p_instr_gen_config cfg_corev, ref string instr[$]); - string store_instr = (XLEN == 32) ? "sw" : "sd"; + string store_instr = (XLEN == 32) ? "sw" : "sd"; + bit done_store_mscratch = 1'b0; + int unsigned total_gpr = 32; // Reserve space from debugger stack to save all 32 GPR except for x0 + MSCRATCH instr.push_back($sformatf("1: addi x%0d, x%0d, -%0d", cfg_corev.dp, cfg_corev.dp, 32 * (XLEN/8))); // Push all GPRs to debugger stack - for(int i = 1; i < 32; i++) begin + for(int i = 1; i < total_gpr; i++) begin if (i == cfg_corev.dp) continue; if (i == cfg_corev.sp) continue; if (i == cfg_corev.tp) continue; instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, i, (i-1) * (XLEN/8), cfg_corev.dp)); + if (!done_store_mscratch) begin + // Read and Push MSCRATCH to debugger stack + instr.push_back($sformatf("csrrw x%0d, 0x340, x%0d # MSCRATCH", i, i)); + instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, i, (total_gpr-1) * (XLEN/8), cfg_corev.dp)); + done_store_mscratch = 1; + end end - // Read and Push MSCRATCH to debugger stack - instr.push_back($sformatf("csrrw x5, 0x340, x5 # MSCRATCH")); - instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", store_instr, 5, 31 * (XLEN/8), cfg_corev.dp)); endfunction : push_gpr_to_debugger_stack // Push floating point registers to the debugger stack @@ -212,17 +217,22 @@ package cv32e40p_instr_test_pkg; // Pop general purpose register from debugger stack function automatic void pop_gpr_from_debugger_stack(cv32e40p_instr_gen_config cfg_corev, ref string instr[$]); - string load_instr = (XLEN == 32) ? "lw" : "ld"; + string load_instr = (XLEN == 32) ? "lw" : "ld"; + bit done_load_mscratch = 1'b0; + int unsigned total_gpr = 32; // Pop user mode GPRs from kernel stack - for(int i = 1; i < 32; i++) begin + for(int i = 1; i < total_gpr; i++) begin if (i == cfg_corev.dp) continue; if (i == cfg_corev.sp) continue; if (i == cfg_corev.tp) continue; + if (!done_load_mscratch) begin + // Pop and Write MSCRATCH from debugger stack + instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, i, (total_gpr-1) * (XLEN/8), cfg_corev.dp)); + instr.push_back($sformatf("csrrw x%0d, 0x340, x%0d # MSCRATCH", i, i)); + done_load_mscratch = 1; + end instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, i, (i-1) * (XLEN/8), cfg_corev.dp)); end - // Pop and Write MSCRATCH from debugger stack - instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, 5, 31 * (XLEN/8), cfg_corev.dp)); - instr.push_back($sformatf("csrrw x5, 0x340, x5 # MSCRATCH")); // Restore debugger stack pointer instr.push_back($sformatf("addi x%0d, x%0d, %0d", cfg_corev.dp, cfg_corev.dp, 31 * (XLEN/8))); endfunction : pop_gpr_from_debugger_stack From f8df5d580b044c30e84d70110568d2807a50b76e Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 30 Apr 2024 11:10:50 +0200 Subject: [PATCH 10/14] Updated configuration for both mhpmcounter29_csr_access_test tests. Signed-off-by: Pascal Gouedo --- cv32e40p/regress/cv32e40pv2_legacy_v1.yaml | 40 ++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml b/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml index 512c98ee33..c16d4d3e9c 100644 --- a/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml +++ b/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml @@ -157,17 +157,51 @@ tests: dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=matmul_32b_int CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + # Can only run with num_mhpmcounter_29 configuration mhpmcounter29_csr_access_test_1: - build: uvmt_cv32e40p + build: uvmt_cv32e40p_num_mhpmcounter_29 description: mhpmcounter29_csr_access_test_1 dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1 CFG_PLUSARGS="+UVM_TIMEOUT=30000000" - + skip_sim: default + no_pulp + pulp + pulp_fpu + pulp_fpu_1cyc_lat + pulp_fpu_2cyc_lat + pulp_fpu_zfinx + pulp_fpu_zfinx_1cyc_lat + pulp_fpu_zfinx_2cyc_lat + pulp_cluster + pulp_cluster_fpu + pulp_cluster_fpu_1cyc_lat + pulp_cluster_fpu_2cyc_lat + pulp_cluster_fpu_zfinx + pulp_cluster_fpu_zfinx_1cyc_lat + pulp_cluster_fpu_zfinx_2cyc_lat + + # Can only run with num_mhpmcounter_29 configuration mhpmcounter29_csr_access_test_2: - build: uvmt_cv32e40p + build: uvmt_cv32e40p_num_mhpmcounter_29 description: mhpmcounter29_csr_access_test_2 dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2 CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + skip_sim: default + no_pulp + pulp + pulp_fpu + pulp_fpu_1cyc_lat + pulp_fpu_2cyc_lat + pulp_fpu_zfinx + pulp_fpu_zfinx_1cyc_lat + pulp_fpu_zfinx_2cyc_lat + pulp_cluster + pulp_cluster_fpu + pulp_cluster_fpu_1cyc_lat + pulp_cluster_fpu_2cyc_lat + pulp_cluster_fpu_zfinx + pulp_cluster_fpu_zfinx_1cyc_lat + pulp_cluster_fpu_zfinx_2cyc_lat misalign: build: uvmt_cv32e40p From 2558ce73e3ccccc2b540b1958179abbe963a627b Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 2 May 2024 09:45:08 +0200 Subject: [PATCH 11/14] Corrected wrong configuration names. Signed-off-by: Pascal Gouedo --- cv32e40p/regress/cv32e40pv2_legacy_v1.yaml | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml b/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml index c16d4d3e9c..386eea2d96 100644 --- a/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml +++ b/cv32e40p/regress/cv32e40pv2_legacy_v1.yaml @@ -167,18 +167,18 @@ tests: no_pulp pulp pulp_fpu - pulp_fpu_1cyc_lat - pulp_fpu_2cyc_lat + pulp_fpu_1cyclat + pulp_fpu_2cyclat pulp_fpu_zfinx - pulp_fpu_zfinx_1cyc_lat - pulp_fpu_zfinx_2cyc_lat + pulp_fpu_zfinx_1cyclat + pulp_fpu_zfinx_2cyclat pulp_cluster pulp_cluster_fpu - pulp_cluster_fpu_1cyc_lat - pulp_cluster_fpu_2cyc_lat + pulp_cluster_fpu_1cyclat + pulp_cluster_fpu_2cyclat pulp_cluster_fpu_zfinx - pulp_cluster_fpu_zfinx_1cyc_lat - pulp_cluster_fpu_zfinx_2cyc_lat + pulp_cluster_fpu_zfinx_1cyclat + pulp_cluster_fpu_zfinx_2cyclat # Can only run with num_mhpmcounter_29 configuration mhpmcounter29_csr_access_test_2: @@ -190,18 +190,18 @@ tests: no_pulp pulp pulp_fpu - pulp_fpu_1cyc_lat - pulp_fpu_2cyc_lat + pulp_fpu_1cyclat + pulp_fpu_2cyclat pulp_fpu_zfinx - pulp_fpu_zfinx_1cyc_lat - pulp_fpu_zfinx_2cyc_lat + pulp_fpu_zfinx_1cyclat + pulp_fpu_zfinx_2cyclat pulp_cluster pulp_cluster_fpu - pulp_cluster_fpu_1cyc_lat - pulp_cluster_fpu_2cyc_lat + pulp_cluster_fpu_1cyclat + pulp_cluster_fpu_2cyclat pulp_cluster_fpu_zfinx - pulp_cluster_fpu_zfinx_1cyc_lat - pulp_cluster_fpu_zfinx_2cyc_lat + pulp_cluster_fpu_zfinx_1cyclat + pulp_cluster_fpu_zfinx_2cyclat misalign: build: uvmt_cv32e40p From 998eb342d8d5e510be5162ff067934d0bc3d81d1 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 2 May 2024 16:39:58 +0200 Subject: [PATCH 12/14] Added new test cases to improve RTL code coverage. Signed-off-by: Pascal Gouedo --- .../illegal_fp_instr_test.S | 17 ++++++++++++++++- .../zfinx_func_cov_improve_test.S | 12 +++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S b/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S index bbb238865a..50b7837ab9 100644 --- a/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S +++ b/cv32e40p/tests/programs/custom/illegal_fp_instr_test/illegal_fp_instr_test.S @@ -11,7 +11,7 @@ #define TEST_FAIL 1 #define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 -#define EXPECTED_ILLEGAL_INSTRUCTIONS 31741 +#define EXPECTED_ILLEGAL_INSTRUCTIONS 31751 main: li t0, (0x1 << 3) @@ -31770,6 +31770,21 @@ main: .word(0x0151dfd3) .word(0xadf06543) .word(0xadf05543) + csrwi frm, 4 + .word(0xadf05543) + .word(0x0151dfd3) + csrwi frm, 3 + .word(0x0151dfd3) + .word(0xadf05543) + csrwi frm, 2 + .word(0x0151dfd3) + .word(0xadf05543) + csrwi frm, 1 + .word(0x0151dfd3) + .word(0xadf05543) + csrwi frm, 0 + .word(0x0151dfd3) + .word(0xadf05543) li x18, TEST_PASS li x16, EXPECTED_ILLEGAL_INSTRUCTIONS diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S index fb1df55b06..c6537d6e36 100644 --- a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S +++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S @@ -3695,9 +3695,19 @@ _fsgnjx_jr31: fsgnjx.s x31, x31, x31 # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end ######### FOR PULP_FPU CFG - END ######### - li x18, TEST_PASS + ######### Added for ex_stage hole coverage ######### + la x1, test_end + li x2, 1 + fcvt.s.w x2, x2 + + fdiv.s x3, x1, x2 + div x4, x5, x0 + jalr x0, x3, 0 + ######### End for ex_stage hole coverage ######### test_end: + li x18, TEST_PASS + li x17, VIRT_PERIPH_STATUS_FLAG_ADDR sw x18,0(x17) j _exit From 5f1648a17183c0345787995d1e13d328264627ab Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Fri, 3 May 2024 04:51:12 +0200 Subject: [PATCH 13/14] Add code coverage waivers for CFG_P_F0 following review. Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 3 + .../cv32e40pv2_code_fpu_cfg_waiver.do | 122 ++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 021960d300..5ded79dc1b 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -177,5 +177,8 @@ coverage exclude -line 1131 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv coverage exclude -line 1230 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -line 1237 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -line 1237 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 399 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No interrupt during debug mode. To waive corner case to happen during FIRST_FETCH 1 clk cycle. } +coverage exclude -line 640 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {HWLoop1 cannot be nested in HWLoop0.} +coverage exclude -line 675 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No case when ID not ready for single stepped instruction. } coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/interrupt_assert_i -recursive -comment {this is TB module bind to RTL. No need code coverage.} coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/prefetch_controller_i/prefetch_controller_sva -recursive -comment {this is TB module bind to RTL. No need code coverage.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index ed110a0758..058ccb89e7 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -279,3 +279,125 @@ coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 242 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 243 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr -comment {We never flush. Flush is stuck to 0.} +coverage exclude -line 125 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 125 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 126 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 127 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we cannot have req_accepted in valid_inflight} +coverage exclude -line 129 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 130 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 131 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 139 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 140 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 141 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 220 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -line 220 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/gen_apu/apu_disp_i -comment {we never have returned_waiting} +coverage exclude -feccondrow 872 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {one specific combination is unreachable. Proven with Formal. } +coverage exclude -line 181 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {we are in sigle master mode. The core wont push more instruction. } +coverage exclude -line 196 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 196 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 197 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 198 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {No new work coming in while we are busy.} +coverage exclude -line 193 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/gen_parallel_slices[0]/active_format/i_fmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_noncomp} -comment {we never have is_boxed=0. TOP level parameter EnableNanBox is always 1. } +coverage exclude -line 193 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/gen_parallel_slices[0]/active_format/i_fmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_noncomp} -comment {we never have is_boxed=0. TOP level parameter EnableNanBox is always 1. } +coverage exclude -feccondrow 501 6 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {unreachable. Never fdsu_dn_stall during WB_IDLE state.} +coverage exclude -line 511 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 512 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 512 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 513 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 514 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 515 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_fdsu_wb_vld when in WB_EX2 state.} +coverage exclude -line 520 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_iter_start when in WB_CMPLT state.} +coverage exclude -line 520 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_iter_start when in WB_CMPLT state.} +coverage exclude -line 521 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {never ctrl_iter_start when in WB_CMPLT state.} +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[1]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[2]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[3]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[4]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 230 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 272 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[2]/gen_level[1]/gen_first_level/gen_reduce} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 299 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 301 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_levels[1]/gen_level[1]/gen_other_levels} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 209 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/gen_mask[0]} -comment {we only have 1 master generating 1 request per cycle, so do not use the round robin. The arbiter is only used for switching matrix. } +coverage exclude -line 231 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb -comment {gnt_i can never be 0.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used. } +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used. } +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_lower/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[2]/g_last_level/g_level[1]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[0]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[0]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_not_last_level/g_level[1]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 82 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/i_arbiter/gen_arbiter/gen_int_rr/gen_fair_arb/i_lzc_upper/gen_lzc/g_levels[1]/g_last_level/g_level[0]/g_reduce} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[3]/g_not_last_level/g_level[7]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[13]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[14]} -comment {this part of leading zero counter is not used.} +coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[15]} -comment {this part of leading zero counter is not used.} From f6e264573bc18b845e5e66bef04b9cad961bb748 Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Fri, 3 May 2024 04:57:13 +0200 Subject: [PATCH 14/14] clean-up code coverage waivers on code type Expression. Not use. Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 18 -------------- .../cv32e40pv2_code_fpu_cfg_waiver.do | 24 ------------------- .../cv32e40pv2_code_pulp_cfg_waiver.do | 8 ------- 3 files changed, 50 deletions(-) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 5ded79dc1b..ebbbfbdea4 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -25,7 +25,6 @@ coverage exclude -line 140 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 142 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} coverage exclude -line 144 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/int_controller_i -comment {All uncovered irq are unreachable. This is set by IRQ_MASK in cv32e40p_pkg.} coverage exclude -line 1047 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.} -coverage exclude -line 1105 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i -comment {u_irq_enable_o never asserted. mstatus.uie never enabled.} coverage exclude -line 1047 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Never save exception pc in ex because no data error from PMP.} coverage exclude -line 1048 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/cs_registers_i/gen_no_pulp_secure_write_logic -comment {Default of unique case not covered} coverage exclude -line 134 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} @@ -34,16 +33,7 @@ coverage exclude -line 165 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 134 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} coverage exclude -line 140 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} coverage exclude -line 165 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i -comment {We dont use USER mode.} -coverage exclude -line 113 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 125 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 141 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 201 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 212 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never fetch_valid == 0 when if_valid == 1. This case is impossible to reach since if_valid depends on fetch_valid to be asserted.} -coverage exclude -line 163 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} -coverage exclude -line 174 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} -coverage exclude -line 185 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/aligner_i -comment {Never aligner_ready when entering misaligned 16 state. Always fetch valid the cycle before.} coverage exclude -line 460 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.} -coverage exclude -line 459 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {We dont support OBI error.} coverage exclude -line 549 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} coverage exclude -line 579 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} coverage exclude -line 608 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i/alu_i -comment {Default part of uniqu_case for vector mode never reached.} @@ -65,18 +55,12 @@ coverage exclude -line 90 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_ coverage exclude -line 97 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {Fifo never empty when trying to push and pop at the same time.} coverage exclude -line 127 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 128 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} -coverage exclude -line 126 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 81 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never overflow the fifo.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {We never underflow the fifo.} coverage exclude -line 126 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 127 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/fifo_i -comment {flush_but_first is dependent on !fifo_empty so this is unreachable.} coverage exclude -line 135 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} -coverage exclude -line 203 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.} -coverage exclude -line 204 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No cv.elw in this configuration.} -coverage exclude -line 321 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.} -coverage exclude -line 322 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Data error not used.} -coverage exclude -line 397 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {We are in PULP_OBI == 0 configuration. In this configuration, trans_valid is always asserted when used in this expression.} coverage exclude -line 135 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {Case 2'b00 has been added for completion but is never used.} coverage exclude -line 155 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} coverage exclude -line 295 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {2'b11 choice that never exists in the decoder.} @@ -138,8 +122,6 @@ coverage exclude -line 941 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 1051 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} coverage exclude -line 1062 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} coverage exclude -line 1072 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} -coverage exclude -line 299 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 844 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No PC = Hwloop1 end & Hwloop 1 counter = 0 in DECODE_HWLOOP FSM state.} coverage exclude -line 418 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } coverage exclude -line 421 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} coverage exclude -line 447 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index 058ccb89e7..276edb5b1b 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -11,8 +11,6 @@ coverage exclude -line 1353 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 1362 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} coverage exclude -line 1440 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} coverage exclude -line 1483 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {Default cannot be reached.} -coverage exclude -line 150 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} -coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 201 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 202 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 203 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} @@ -37,20 +35,13 @@ coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 416 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 424 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 425 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} -coverage exclude -line 458 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {flush_i set to 1'b0} coverage exclude -line 458 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {flush_i set to 1'b0} -coverage exclude -line 460 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {reg_ena_i is stuck to 0} -coverage exclude -line 464 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {Tag is stuck at 0} -coverage exclude -line 465 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/gen_output_pipeline[0]} -comment {Mask is stuck at 0} coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} -coverage exclude -line 59 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 59 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} -coverage exclude -line 59 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 59 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_cast_multi/i_fpnew_rounding} -comment {Round towards odd does not exist in RISCV} coverage exclude -line 148 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.} coverage exclude -line 149 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_decode_rm is never 7. This correspond to DYN rounding mode.} -coverage exclude -line 151 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {idu_fpu_ex1_eu_sel is 0 or 4. idu_fpu_ex1_eu_sel[1] is always 0.} coverage exclude -line 155 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_src2_vld never asserted. This is expression 151.} coverage exclude -line 240 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0001. ex1_result_qnan_op0. This is always 0, comes from fdsu_special lines 282 and 294.} coverage exclude -line 240 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/x_pa_fpu_dp} -comment {ex1_special_sel[8:5] never 0001. ex1_result_qnan_op0. This is always 0, comes from fdsu_special lines 282 and 294.} @@ -87,21 +78,12 @@ coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 416 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} coverage exclude -line 417 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} coverage exclude -line 418 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} -coverage exclude -line 431 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} -coverage exclude -line 433 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {WFWB state never reached. Caused by fdsu_wb_grant always asserted during PACK state.} coverage exclude -line 443 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 444 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 464 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 465 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 483 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} coverage exclude -line 484 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Never flush. Related to expression line 637.} -coverage exclude -line 540 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {Both signal are acctually the same via external connection.} -coverage exclude -line 637 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {async_flush is stuck to 0. warm_up is stuck to 0. ex1_cancel is suck to 0. ex2_cancel is stuck to 0. We will never flush.} -coverage exclude -line 648 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {rtu_yy_xx_flush stuck to 0. fdsu_busy cannot be low if ctrl_sm_idle is low.} -coverage exclude -line 754 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} -coverage exclude -line 755 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} -coverage exclude -line 756 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} -coverage exclude -line 757 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_ctrl} -comment {ctrl_xx_ex1/2/3_warm_up stuck to 0.} coverage exclude -line 280 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 280 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 282 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} @@ -121,11 +103,7 @@ coverage exclude -line 298 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 298 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 300 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 301 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 301 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 302 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 302 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 294 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} -coverage exclude -line 296 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_special} -comment {cp0_fpu_xx_dqnan stuck to 0. Can never have the non masking condition.} coverage exclude -line 63 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} coverage exclude -line 63 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} coverage exclude -line 64 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th/i_divsqrt_thead/x_pa_fdsu_prepare/x_frac_expnt} -comment {This can only be reached when using double precision} @@ -267,8 +245,6 @@ coverage exclude -line 208 -code b -allfalse -scope {/uvmt_cv32e40p_tb/dut_wrap/ coverage exclude -line 208 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} coverage exclude -line 209 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {No float to float conversion. We are using only on format.} coverage exclude -line 213 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane} -comment {We never use cast and pack.} -coverage exclude -line 458 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/target_regs} -comment {No vector floating point operation.} -coverage exclude -line 476 -code e -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/target_regs} -comment {No vector floating point operation.} coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 243 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[3]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} coverage exclude -line 242 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[2]/i_opgroup_block/i_arbiter/gen_arbiter/gen_int_rr} -comment {We never flush. Flush is stuck to 0.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do index 494debe1e6..dd912631bf 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do @@ -12,10 +12,6 @@ coverage exclude -line 205 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 211 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 237 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 241 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 215 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 217 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 474 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 476 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 205 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 211 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} coverage exclude -line 211 -code b -allfalse -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {No FPU in this configuration.} @@ -27,8 +23,6 @@ coverage exclude -line 1559 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 1560 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 1561 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 1562 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 920 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} -coverage exclude -line 1679 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 529 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration.} coverage exclude -line 1557 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i -comment {No FPU in this configuration. } coverage exclude -line 236 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} @@ -55,8 +49,6 @@ coverage exclude -line 266 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 272 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 284 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} -coverage exclude -line 3000 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} -coverage exclude -line 1390 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} coverage exclude -line 89 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 91 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.}