From 4f571fa4aba644a1c7ab38f5b1cc39431d1c6ae2 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Mon, 8 Apr 2024 17:49:47 +0800 Subject: [PATCH 01/12] RVFI - Adding mhmpevents to imperas dv wrap --- .../tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv index ef7069366c..672d140fd1 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv @@ -325,6 +325,35 @@ module uvmt_cv32e40p_imperas_dv_wrap // `RVVI_SET_CSR( `CSR_MCYCLEH_ADDR, mcycleh ) `RVVI_SET_CSR( `CSR_MINSTRETH_ADDR, minstreth ) `RVVI_SET_CSR( `CSR_INSTRET_ADDR, instret ) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT3_ADDR, mhpmevent, 3) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT4_ADDR, mhpmevent, 4) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT5_ADDR, mhpmevent, 5) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT6_ADDR, mhpmevent, 6) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT7_ADDR, mhpmevent, 7) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT8_ADDR, mhpmevent, 8) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT9_ADDR, mhpmevent, 9) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT10_ADDR, mhpmevent, 10) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT11_ADDR, mhpmevent, 11) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT12_ADDR, mhpmevent, 12) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT13_ADDR, mhpmevent, 13) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT14_ADDR, mhpmevent, 14) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT15_ADDR, mhpmevent, 15) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT16_ADDR, mhpmevent, 16) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT17_ADDR, mhpmevent, 17) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT18_ADDR, mhpmevent, 18) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT19_ADDR, mhpmevent, 19) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT20_ADDR, mhpmevent, 20) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT21_ADDR, mhpmevent, 21) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT22_ADDR, mhpmevent, 22) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT23_ADDR, mhpmevent, 23) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT24_ADDR, mhpmevent, 24) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT25_ADDR, mhpmevent, 25) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT26_ADDR, mhpmevent, 26) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT27_ADDR, mhpmevent, 27) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT28_ADDR, mhpmevent, 28) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT29_ADDR, mhpmevent, 29) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT30_ADDR, mhpmevent, 30) + `RVVI_SET_CSR_VEC( `CSR_MHPMEVENT31_ADDR, mhpmevent, 31) `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER3_ADDR, mhpmcounter, 3) `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER3H_ADDR, mhpmcounterh, 3) `RVVI_SET_CSR_VEC( `CSR_MHPMCOUNTER4_ADDR, mhpmcounter, 4) From fd3a7ffe4a375a0622e1aa7255d6e3ea98429d48 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 9 Apr 2024 10:23:34 +0800 Subject: [PATCH 02/12] Add/Update tests to improve tb functional coverage holes (uvme_interrupt_covg_v2) Signed-off-by: dd-baoshan --- .../cv32e40p_instr_for_func_cvg_lib.sv | 9 ++-- .../cv32e40p_pulp_hwloop_instr_lib.sv | 45 ++++++++++++++++++- .../corev-dv.yaml | 2 +- .../corev-dv.yaml | 2 +- 4 files changed, 50 insertions(+), 8 deletions(-) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv index 9da800fe48..7880da732a 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_instr_for_func_cvg_lib.sv @@ -31,7 +31,6 @@ class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_i int unsigned loop_cnt = 0; int unsigned total_instr = 0; int unsigned loop_cnt_limit = 0; - int unsigned ignored_instr_cnt = 0; `uvm_object_utils(cv32e40p_cv_instrs_multi_loops_streams) `uvm_object_new @@ -47,14 +46,14 @@ class cv32e40p_cv_instrs_multi_loops_streams extends cv32e40p_float_zfinx_base_i include_group = new[1] ({RV32X}); exclude_instr = new[9] ({CV_START, CV_STARTI, CV_END, CV_ENDI, CV_COUNT, CV_COUNTI, CV_SETUP, CV_SETUPI, CV_ELW}); - // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to b ecovered) - ignored_instr_cnt = 4; - exclude_instr = new[exclude_instr.size()+ignored_instr_cnt] ({exclude_instr, CV_MAX, CV_ADDN, CV_AVG_SCI_H, CV_SHUFFLEI3_SCI_B}); + // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to be covered) + // example coding to reduce already covered instrs in previous accumulated coverage + // exclude_instr = new[exclude_instr.size()+4] ({exclude_instr, CV_MAX, CV_ADDN, CV_AVG_SCI_H, CV_SHUFFLEI3_SCI_B}); // these already covered in all cvg, can be ignored meantime - End if (include_load_store_base_sp) begin // cover c_[s|l]wsp insn only include_group = new[include_group.size()+1] ({include_group, RV32C}); - // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to b ecovered) + // these already covered in all cvg, can be ignored meantime - Start (note: users can modify this to focus on insn list to be covered) exclude_instr = new[exclude_instr.size()+25] ({exclude_instr, C_LW, C_SW, C_ADDI4SPN, C_ADDI, C_LI, C_ADDI16SP, C_LUI, C_SRLI, C_SRAI, C_ANDI, C_SUB, C_XOR, C_OR, C_AND, C_BEQZ, C_BNEZ, C_SLLI, C_MV, C_EBREAK, C_ADD, C_NOP, C_J, C_JAL, C_JR, C_JALR}); diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index cee892638b..bdaf1955ae 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -74,7 +74,7 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; localparam MAX_HWLOOP_INSTR_GEN = 4095; rand riscv_reg_t hwloop_avail_regs[]; - rand bit[1:0] num_loops_active; + rand int unsigned num_loops_active; rand bit gen_nested_loop; //nested or not-nested hwloop rand bit use_setup_inst[2]; rand bit use_loop_counti_inst[2]; @@ -1324,6 +1324,49 @@ class cv32e40p_xpulp_short_hwloop_stream_directed extends cv32e40p_xpulp_short_h endfunction : new endclass : cv32e40p_xpulp_short_hwloop_stream_directed +// directed test for more non-nested hwloop only with small loop count and lesser instrs +class cv32e40p_xpulp_short_single_hwloop_stream_directed extends cv32e40p_xpulp_short_hwloop_stream; + + `uvm_object_utils_begin(cv32e40p_xpulp_short_single_hwloop_stream_directed) + `uvm_field_int(num_loops_active, UVM_DEFAULT) + `uvm_field_int(gen_nested_loop, UVM_DEFAULT) + `uvm_field_sarray_int(use_setup_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_counti_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_starti_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_endi_inst, UVM_DEFAULT) + `uvm_field_sarray_int(use_loop_setupi_inst, UVM_DEFAULT) + `uvm_field_sarray_int(hwloop_count, UVM_DEFAULT) + `uvm_field_sarray_int(hwloop_counti, UVM_DEFAULT) + `uvm_field_sarray_int(num_hwloop_instr, UVM_DEFAULT) + `uvm_field_sarray_int(num_hwloop_ctrl_instr, UVM_DEFAULT) + `uvm_field_sarray_int(num_fill_instr_loop_ctrl_to_loop_start, UVM_DEFAULT) + `uvm_field_int(num_fill_instr_in_loop1_till_loop0_setup, UVM_DEFAULT) + `uvm_field_int(setup_l0_before_l1_start, UVM_DEFAULT) + `uvm_field_sarray_int(num_instr_cv_start_to_loop_start_label, UVM_DEFAULT) + `uvm_field_int(loop0_high_count, UVM_DEFAULT) + `uvm_object_utils_end + + constraint gen_hwloop_count_c { + + solve gen_nested_loop, loop0_high_count before hwloop_count, hwloop_counti; + solve gen_nested_loop before loop0_high_count; + + gen_nested_loop == 0; + num_loops_active inside {[800:1000]}; + + foreach(hwloop_counti[i]) { + hwloop_counti[i] inside {2,3}; + } + foreach(hwloop_count[i]) { + hwloop_count[i] inside {2,3}; + } + } + + function new(string name = "cv32e40p_xpulp_short_single_hwloop_stream_directed"); + super.new(name); + endfunction : new + +endclass : cv32e40p_xpulp_short_single_hwloop_stream_directed //Class: cv32e40p_xpulp_long_hwloop_stream diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml index 5aff998588..e575a168c0 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_debug/corev-dv.yaml @@ -13,7 +13,7 @@ plusargs: > +insert_rand_directed_instr_stream=1 +test_rand_directed_instr_stream_num=2 +rand_directed_instr_0=cv32e40p_xpulp_short_hwloop_stream_directed,1 - +rand_directed_instr_1=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_short_single_hwloop_stream_directed,1 +no_fence=1 +no_data_page=0 +randomize_csr=1 diff --git a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml index 9589b79c1b..3071fa434a 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_directed_pulp_hwloop_test/corev-dv.yaml @@ -13,7 +13,7 @@ plusargs: > +insert_rand_directed_instr_stream=1 +test_rand_directed_instr_stream_num=2 +rand_directed_instr_0=cv32e40p_xpulp_short_hwloop_stream_directed,1 - +rand_directed_instr_1=cv32e40p_xpulp_short_hwloop_stream_directed,1 + +rand_directed_instr_1=cv32e40p_xpulp_short_single_hwloop_stream_directed,1 +no_fence=0 +no_data_page=0 +randomize_csr=1 From 5b220828c92dddb34cd54e107736cb6d949bdbf8 Mon Sep 17 00:00:00 2001 From: Yoann Pruvost Date: Tue, 9 Apr 2024 12:08:02 +0800 Subject: [PATCH 03/12] Setting all mhpmevents csr as volatile in Imperas dv wrap --- .../tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv index 672d140fd1..a7492f796e 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_imperas_dv_wrap.sv @@ -582,6 +582,37 @@ module uvmt_cv32e40p_imperas_dv_wrap void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3_ADDR )); void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMCOUNTER3H_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT3_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT4_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT5_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT6_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT7_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT8_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT9_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT10_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT11_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT12_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT13_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT14_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT15_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT16_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT17_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT18_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT19_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT20_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT21_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT22_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT23_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT24_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT25_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT26_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT27_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT28_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT29_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT30_ADDR )); + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MHPMEVENT31_ADDR )); + + void'(rvviRefCsrSetVolatile(hart_id, `CSR_MCYCLE_ADDR )); void'(rvviRefCsrSetVolatile(hart_id, `CSR_MCYCLEH_ADDR )); From bf01f279a7b26e1198f3edc8fd47bff5347f17b5 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Wed, 10 Apr 2024 19:27:46 +0200 Subject: [PATCH 04/12] Added 2 tests with single loops for CSR access Signed-off-by: Pascal Gouedo --- .../pulp_hardware_loop/pulp_hardware_loop.S | 85 ++++++++++++++++--- 1 file changed, 74 insertions(+), 11 deletions(-) diff --git a/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S b/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S index c369ec2400..bd9512a1c5 100644 --- a/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S +++ b/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S @@ -315,9 +315,71 @@ test6_5: beq x20, x10, test7 c.addi x15, 0x1 -# test7 CSR read accesses during HWloop (same as test1 but with CSR reads to mstatus) +# test7 CSR read accesses during single HWloop (same as test1 but with CSR reads to mstatus) test7: + cv.counti 0, 0 + cv.counti 1, 0 + li x5, 0 + li x6, 0 + li x17, 0 + li x30, 0x80 + li x31, 0 + + .balign 4 + + cv.starti 0, startZ_7_1 + cv.endi 0, endZ_7_1 + cv.counti 0, 10 + + .option norvc + +startZ_7_1: + addi x17, x17, 1 + csrr x5, 0x300 # mstatus + addi x17, x17, 1 + lw x31, 0(x30) + csrr x6, 0x300 # mstatus +endZ_7_1: + + .option rvc + + li x20, 20 + beq x20, x17, test7_2 + c.addi x15, 0x1 + +test7_2: + li x5, 0 + li x6, 0 + li x17, 0 + li x30, 0x80 + li x31, 0 + + .balign 4 + + cv.starti 1, startZ_7_2 + cv.endi 1, endZ_7_2 + cv.counti 1, 10 + + .option norvc + +startZ_7_2: + addi x17, x17, 1 + csrr x5, 0x300 # mstatus + addi x17, x17, 1 + lw x31, 0(x30) + csrr x6, 0x300 # mstatus +endZ_7_2: + + .option rvc + + li x20, 20 + beq x20, x17, test8 + c.addi x15, 0x1 + +# test8 CSR read accesses during nested HWloop (same as test1 but with CSR reads to mstatus) + +test8: cv.counti 0, 0 cv.counti 1, 0 li x5, 0 @@ -331,36 +393,37 @@ test7: .balign 4 - cv.starti 1, startO_7 - cv.endi 1, endO_7 + cv.starti 1, startO_8 + cv.endi 1, endO_8 cv.counti 1, 10 - cv.starti 0, startZ_7 - cv.endi 0, endZ_7 -startO_7: + cv.starti 0, startZ_8 + cv.endi 0, endZ_8 +startO_8: cv.counti 0, 10 csrr x5, 0x300 # mstatus .option norvc -startZ_7: +startZ_8: addi x17, x17, 1 csrr x5, 0x300 # mstatus addi x17, x17, 1 lw x31, 0(x30) csrr x6, 0x300 # mstatus -endZ_7: +endZ_8: addi x18, x18, 1 csrr x7, 0x300 # mstatus addi x18, x18, 1 csrr x8, 0x300 # mstatus -endO_7: +endO_8: .option rvc li x20, 200 - beq x20, x17, test7_1 + beq x20, x17, test8_1 c.addi x15, 0x1 -test7_1: + +test8_1: li x21, 20 beq x21, x18, exit_check c.addi x15, 0x1 From f0f50ea57cc07ca14945cd66bd074829e0cda206 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Thu, 11 Apr 2024 17:05:00 +0800 Subject: [PATCH 05/12] Update test and add waiver to improve functional coverage holes (uvme_debug_covg) Signed-off-by: dd-baoshan --- .../vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do | 2 ++ .../tests/programs/custom/debug_test_trigger/debugger.S | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do index 14f406de24..da74b27e4a 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_debug_waiver.do @@ -4,3 +4,5 @@ coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpul coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_trigger_with_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_dbg_single_step_xpulp_instr/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} coverage exclude -cvgpath {/uvme_cv32e40p_pkg/uvme_debug_covg/cg_debug_with_xpulp_inst/\/uvme_cv32e40p_pkg::uvme_debug_covg::cg_debug_with_xpulp_inst /cr_xpulp_instructions_in_dbg_mode/} -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} + +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_debug_covg/cg_irq_dreq/irq_dreq_trig_branch -comment {not valid in v1.2 due to rtl behaviour change when PULP is enabled; decoding signal is low if debug trigger match during DECODE state; refer line 494 at cv32e40p_controller.sv;} diff --git a/cv32e40p/tests/programs/custom/debug_test_trigger/debugger.S b/cv32e40p/tests/programs/custom/debug_test_trigger/debugger.S index 64534e58ba..0c7c24d981 100644 --- a/cv32e40p/tests/programs/custom/debug_test_trigger/debugger.S +++ b/cv32e40p/tests/programs/custom/debug_test_trigger/debugger.S @@ -69,6 +69,13 @@ _debugger_start: la a2, glb_hart_status lw t2, 0(a2) + // extra codes in debug rom for coverage purpose +#if defined(PULP) + cv.bneimm x0, 0, b1_position +b1_position: + cv.beqimm x0, 0x01, b2_position +b2_position: +#endif // For all other tests, // Set debug status = hart status From 9f967984a1d13f22478000d11a1229c0e6dac889 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 15 Apr 2024 12:54:58 +0800 Subject: [PATCH 06/12] Add functional exclusion file - hwloop Signed-off-by: dd-baoshan --- .../cv32e40pv2_func_uvme_hwloop_waiver.do | 161 ++++++++++++++++++ .../tools/vsim/exclusion/pulp/exclusion.do | 3 + .../vsim/exclusion/pulp_fpu/exclusion.do | 3 + 3 files changed, 167 insertions(+) create mode 100644 cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_hwloop_waiver.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_hwloop_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_hwloop_waiver.do new file mode 100644 index 0000000000..a7a8a910d5 --- /dev/null +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_func_uvme_hwloop_waiver.do @@ -0,0 +1,161 @@ +# coverpoint - hwloop0 body does not allow hwloop configuration instructions for 0 and 1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_starti0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_start0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_endi0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_end0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_counti0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_count0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_setupi0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_setup0 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_starti1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_start1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_endi1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_end1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_counti1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_count1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_setupi1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_setup1 + +# coverpoint - hwloop1 body only allow hwloop configuration for 0 (nested loop) +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_starti1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_start1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_endi1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_end1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_counti1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_count1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_setupi1 +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_setup1 + +# coverpoint - cv.elw related +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_elw_pi_ri -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_elw_pi_ri -comment {fixme: this waiver is not applicable for pulp_cluster config. elw is currently not tested thoroughly in non-cluster config tb} + +# coverpoint - hwloop body does not allow branch insn +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_beqimm +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/cp_insn_list_in_hwloop/cv_bneimm +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_beqimm +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/cp_insn_list_in_hwloop/cv_bneimm + +# cross coverpoint - link to cg_features_of_hwloop_0/cp_insn_list_in_hwloop +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_0/ccp_hwloop_type_setup_insn_list/ + +# cross coverpoint - link to cg_features_of_hwloop_1/cp_insn_list_in_hwloop +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ +coverage exclude -cvgpath /uvme_cv32e40p_pkg/uvme_rv32x_hwloop_covg__1/cg_features_of_hwloop_1/ccp_hwloop_type_setup_insn_list/ diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do index ba5f1e50b7..fe305623f8 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp/exclusion.do @@ -7,6 +7,9 @@ do ../cv32e40pv2_func_uvme_interrupt_waiver.do # functional: uvme_debug_covg do ../cv32e40pv2_func_uvme_debug_waiver.do +# functional: uvme_rv32x_hwloop_covg +do ../cv32e40pv2_func_uvme_hwloop_waiver.do + # code coverage : common waiver do ../cv32e40pv2_code_all_cfg_waiver.do diff --git a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do index 5947356ce0..bfa1b0ca32 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do +++ b/cv32e40p/sim/tools/vsim/exclusion/pulp_fpu/exclusion.do @@ -7,6 +7,9 @@ do ../cv32e40pv2_func_uvme_interrupt_waiver.do # functional: uvme_debug_covg do ../cv32e40pv2_func_uvme_debug_waiver.do +# functional: uvme_rv32x_hwloop_covg +do ../cv32e40pv2_func_uvme_hwloop_waiver.do + # code coverage : common waiver do ../cv32e40pv2_code_all_cfg_waiver.do From 39d951de49fa5babb07e17c9aa291422bac8ee4c Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 15 Apr 2024 12:56:04 +0800 Subject: [PATCH 07/12] Allow mie[7] enablement for timer interrupt Signed-off-by: dd-baoshan --- cv32e40p/tests/test_cfg/gen_rand_int.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/cv32e40p/tests/test_cfg/gen_rand_int.yaml b/cv32e40p/tests/test_cfg/gen_rand_int.yaml index 54500496b5..2733609a63 100644 --- a/cv32e40p/tests/test_cfg/gen_rand_int.yaml +++ b/cv32e40p/tests/test_cfg/gen_rand_int.yaml @@ -3,5 +3,6 @@ description: > Enable and Trigger Interrupts plusargs: > +enable_interrupt=1 + +enable_timer_irq=1 +enable_fast_interrupt_handler=1 +gen_irq_noise From 25d0805745e75660c5625a072d63c4c42b400411 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 15 Apr 2024 11:36:04 +0200 Subject: [PATCH 08/12] As T-Head FDIV/FSQRT is longer that PULP one, added 2 cycles when waiting from WFI to sleep. Signed-off-by: Pascal Gouedo --- cv32e40p/tb/uvmt/uvmt_cv32e40p_interrupt_assert.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_interrupt_assert.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_interrupt_assert.sv index 325a3a0ec5..edf49bcd8b 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_interrupt_assert.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_interrupt_assert.sv @@ -343,13 +343,13 @@ module uvmt_cv32e40p_interrupt_assert // WFI assertion will assert core_sleep_o in 6 clocks property p_wfi_assert_core_sleep_o; !pending_enabled_irq_q ##0 !in_wfi ##1 !pending_enabled_irq_q ##0 - ((!pending_enabled_irq && !debug_mode_q && !debug_req_i) throughout in_wfi[*38]) + ((!pending_enabled_irq && !debug_mode_q && !debug_req_i) throughout in_wfi[*40]) |-> core_sleep_o; endproperty a_wfi_assert_core_sleep_o: assert property(p_wfi_assert_core_sleep_o) else `uvm_error(info_tag, - "Aassertion of core_sleep_o did not occur within 6 clocks") + "Assertion of core_sleep_o did not occur within 6 clocks") // core_sleep_o deassertion in wfi should be followed by WFI deassertion property p_core_sleep_deassert; From 3c714bb61c396cf05a231e5168175327f315b7d5 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 16 Apr 2024 16:51:26 +0800 Subject: [PATCH 09/12] Add custom test to improve functional coverage holes (uvme_cv32e40p_fp_instr_covg) Signed-off-by: dd-baoshan --- .../cv32e40pv2_for_func_cvg_improvement.yaml | 18 + cv32e40p/regress/cv32e40pv2_fpu_instr.yaml | 18 + .../fpu_func_cov_improve_test.S | 1524 +++++++++++++++++ .../fpu_func_cov_improve_test/test.yaml | 6 + 4 files changed, 1566 insertions(+) create mode 100644 cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S create mode 100644 cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml diff --git a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml index 7924e8d991..0dd639b2e5 100644 --- a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml +++ b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml @@ -62,3 +62,21 @@ tests: dir: cv32e40p/sim/uvmt cmd: make test COREV=YES TEST=debug_test_trigger num: 1 + + fpu_func_cov_improve_test: + build: uvmt_cv32e40p + description: directed custom test to improve missing coverage in cfg pulp_fpu + dir: cv32e40p/sim/uvmt + cmd: make test TEST=fpu_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000" + num: 1 + skip_sim: + - pulp + - pulp_zfinx + - pulp_zfinx_1cyclat + - pulp_zfinx_2cyclat + - pulp_cluster + - pulp_cluster_fpu + - pulp_cluster_fpu_1cyclat + - pulp_cluster_fpu_2cyclat + - default + - no_pulp diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml index ca5f00730b..ce570548f8 100644 --- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml @@ -63,3 +63,21 @@ tests: dir: cv32e40p/sim/uvmt cmd: make test TEST=illegal_fp_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000" num: 1 + + fpu_func_cov_improve_test: + build: uvmt_cv32e40p + description: directed custom test to improve missing coverage in cfg pulp_fpu + dir: cv32e40p/sim/uvmt + cmd: make test TEST=fpu_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000" + num: 1 + skip_sim: + - pulp + - pulp_zfinx + - pulp_zfinx_1cyclat + - pulp_zfinx_2cyclat + - pulp_cluster + - pulp_cluster_fpu + - pulp_cluster_fpu_1cyclat + - pulp_cluster_fpu_2cyclat + - default + - no_pulp diff --git a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S new file mode 100644 index 0000000000..3b4c4c0f47 --- /dev/null +++ b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S @@ -0,0 +1,1524 @@ + +.globl _start +.globl main +.globl exit +.section .text + +#define TEST_PASS 123456789 +#define TEST_FAIL 1 +#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 + +main: + li t0, (0x0 << 3) + csrs mstatus, t0 + li x31, 0x0 + +#if defined(FPU) + li x5, 0x00003800 + csrw 0x300, x5 # MSTATUS FPU enable +#endif + + ######### FOR PULP_FPU CFG - START ######### + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - start + .align 2 + + // 1 + jal x0, _j0 +_j0: fcvt.s.w f0, x0 + jal x1, _j1 +_j1: fcvt.s.w f1, x1 + jal x2, _j2 +_j2: fcvt.s.w f2, x2 + jal x3, _j3 +_j3: fcvt.s.w f3, x3 + jal x4, _j4 +_j4: fcvt.s.w f4, x4 + jal x5, _j5 +_j5: fcvt.s.w f5, x5 + jal x6, _j6 +_j6: fcvt.s.w f6, x6 + jal x7, _j7 +_j7: fcvt.s.w f7, x7 + jal x8, _j8 +_j8: fcvt.s.w f8, x8 + jal x9, _j9 +_j9: fcvt.s.w f9, x9 + jal x10, _j10 +_j10: fcvt.s.w f10, x10 + jal x11, _j11 +_j11: fcvt.s.w f11, x11 + jal x12, _j12 +_j12: fcvt.s.w f12, x12 + jal x13, _j13 +_j13: fcvt.s.w f13, x13 + jal x14, _j14 +_j14: fcvt.s.w f14, x14 + jal x15, _j15 +_j15: fcvt.s.w f15, x15 + jal x16, _j16 +_j16: fcvt.s.w f16, x16 + jal x17, _j17 +_j17: fcvt.s.w f17, x17 + jal x18, _j18 +_j18: fcvt.s.w f18, x18 + jal x19, _j19 +_j19: fcvt.s.w f19, x19 + jal x20, _j20 +_j20: fcvt.s.w f20, x20 + jal x21, _j21 +_j21: fcvt.s.w f21, x21 + jal x22, _j22 +_j22: fcvt.s.w f22, x22 + jal x23, _j23 +_j23: fcvt.s.w f23, x23 + jal x24, _j24 +_j24: fcvt.s.w f24, x24 + jal x25, _j25 +_j25: fcvt.s.w f25, x25 + jal x26, _j26 +_j26: fcvt.s.w f26, x26 + jal x27, _j27 +_j27: fcvt.s.w f27, x27 + jal x28, _j28 +_j28: fcvt.s.w f28, x28 + jal x29, _j29 +_j29: fcvt.s.w f29, x29 + jal x30, _j30 +_j30: fcvt.s.w f30, x30 + jal x31, _j31 +_j31: fcvt.s.w f31, x31 + + // 2 + jal x0, _jj0 +_jj0: fcvt.s.wu f0, x0 + jal x1, _jj1 +_jj1: fcvt.s.wu f1, x1 + jal x2, _jj2 +_jj2: fcvt.s.wu f2, x2 + jal x3, _jj3 +_jj3: fcvt.s.wu f3, x3 + jal x4, _jj4 +_jj4: fcvt.s.wu f4, x4 + jal x5, _jj5 +_jj5: fcvt.s.wu f5, x5 + jal x6, _jj6 +_jj6: fcvt.s.wu f6, x6 + jal x7, _jj7 +_jj7: fcvt.s.wu f7, x7 + jal x8, _jj8 +_jj8: fcvt.s.wu f8, x8 + jal x9, _jj9 +_jj9: fcvt.s.wu f9, x9 + jal x10, _jj10 +_jj10: fcvt.s.wu f10, x10 + jal x11, _jj11 +_jj11: fcvt.s.wu f11, x11 + jal x12, _jj12 +_jj12: fcvt.s.wu f12, x12 + jal x13, _jj13 +_jj13: fcvt.s.wu f13, x13 + jal x14, _jj14 +_jj14: fcvt.s.wu f14, x14 + jal x15, _jj15 +_jj15: fcvt.s.wu f15, x15 + jal x16, _jj16 +_jj16: fcvt.s.wu f16, x16 + jal x17, _jj17 +_jj17: fcvt.s.wu f17, x17 + jal x18, _jj18 +_jj18: fcvt.s.wu f18, x18 + jal x19, _jj19 +_jj19: fcvt.s.wu f19, x19 + jal x20, _jj20 +_jj20: fcvt.s.wu f20, x20 + jal x21, _jj21 +_jj21: fcvt.s.wu f21, x21 + jal x22, _jj22 +_jj22: fcvt.s.wu f22, x22 + jal x23, _jj23 +_jj23: fcvt.s.wu f23, x23 + jal x24, _jj24 +_jj24: fcvt.s.wu f24, x24 + jal x25, _jj25 +_jj25: fcvt.s.wu f25, x25 + jal x26, _jj26 +_jj26: fcvt.s.wu f26, x26 + jal x27, _jj27 +_jj27: fcvt.s.wu f27, x27 + jal x28, _jj28 +_jj28: fcvt.s.wu f28, x28 + jal x29, _jj29 +_jj29: fcvt.s.wu f29, x29 + jal x30, _jj30 +_jj30: fcvt.s.wu f30, x30 + jal x31, _jj31 +_jj31: fcvt.s.wu f31, x31 + + // 3 + la x1, _jr0 + jalr x0, x1, 0 +_jr0: fcvt.s.w f0, x0 + la x1, _jr1 + jalr x1, x1, 0 +_jr1: fcvt.s.w f1, x1 + la x1, _jr2 + jalr x2, x1, 0 +_jr2: fcvt.s.w f2, x2 + la x1, _jr3 + jalr x3, x1, 0 +_jr3: fcvt.s.w f3, x3 + la x1, _jr4 + jalr x4, x1, 0 +_jr4: fcvt.s.w f4, x4 + la x1, _jr5 + jalr x5, x1, 0 +_jr5: fcvt.s.w f5, x5 + la x1, _jr6 + jalr x6, x1, 0 +_jr6: fcvt.s.w f6, x6 + la x1, _jr7 + jalr x7, x1, 0 +_jr7: fcvt.s.w f7, x7 + la x1, _jr8 + jalr x8, x1, 0 +_jr8: fcvt.s.w f8, x8 + la x1, _jr9 + jalr x9, x1, 0 +_jr9: fcvt.s.w f9, x9 + la x1, _jr10 + jalr x10, x1, 0 +_jr10: fcvt.s.w f10, x10 + la x1, _jr11 + jalr x11, x1, 0 +_jr11: fcvt.s.w f11, x11 + la x1, _jr12 + jalr x12, x1, 0 +_jr12: fcvt.s.w f12, x12 + la x1, _jr13 + jalr x13, x1, 0 +_jr13: fcvt.s.w f13, x13 + la x1, _jr14 + jalr x14, x1, 0 +_jr14: fcvt.s.w f14, x14 + la x1, _jr15 + jalr x15, x1, 0 +_jr15: fcvt.s.w f15, x15 + la x1, _jr16 + jalr x16, x1, 0 +_jr16: fcvt.s.w f16, x16 + la x1, _jr17 + jalr x17, x1, 0 +_jr17: fcvt.s.w f17, x17 + la x1, _jr18 + jalr x18, x1, 0 +_jr18: fcvt.s.w f18, x18 + la x1, _jr19 + jalr x19, x1, 0 +_jr19: fcvt.s.w f19, x19 + la x1, _jr20 + jalr x20, x1, 0 +_jr20: fcvt.s.w f20, x20 + la x1, _jr21 + jalr x21, x1, 0 +_jr21: fcvt.s.w f21, x21 + la x1, _jr22 + jalr x22, x1, 0 +_jr22: fcvt.s.w f22, x22 + la x1, _jr23 + jalr x23, x1, 0 +_jr23: fcvt.s.w f23, x23 + la x1, _jr24 + jalr x24, x1, 0 +_jr24: fcvt.s.w f24, x24 + la x1, _jr25 + jalr x25, x1, 0 +_jr25: fcvt.s.w f25, x25 + la x1, _jr26 + jalr x26, x1, 0 +_jr26: fcvt.s.w f26, x26 + la x1, _jr27 + jalr x27, x1, 0 +_jr27: fcvt.s.w f27, x27 + la x1, _jr28 + jalr x28, x1, 0 +_jr28: fcvt.s.w f28, x28 + la x1, _jr29 + jalr x29, x1, 0 +_jr29: fcvt.s.w f29, x29 + la x1, _jr30 + jalr x30, x1, 0 +_jr30: fcvt.s.w f30, x30 + la x1, _jr31 + jalr x31, x1, 0 +_jr31: fcvt.s.w f31, x31 + la x1, _jr0 + + // 4 + la x1, _jjr0 + jalr x0, x1, 0 +_jjr0: fcvt.s.wu f0, x0 + la x1, _jjr1 + jalr x1, x1, 0 +_jjr1: fcvt.s.wu f1, x1 + la x1, _jjr2 + jalr x2, x1, 0 +_jjr2: fcvt.s.wu f2, x2 + la x1, _jjr3 + jalr x3, x1, 0 +_jjr3: fcvt.s.wu f3, x3 + la x1, _jjr4 + jalr x4, x1, 0 +_jjr4: fcvt.s.wu f4, x4 + la x1, _jjr5 + jalr x5, x1, 0 +_jjr5: fcvt.s.wu f5, x5 + la x1, _jjr6 + jalr x6, x1, 0 +_jjr6: fcvt.s.wu f6, x6 + la x1, _jjr7 + jalr x7, x1, 0 +_jjr7: fcvt.s.wu f7, x7 + la x1, _jjr8 + jalr x8, x1, 0 +_jjr8: fcvt.s.wu f8, x8 + la x1, _jjr9 + jalr x9, x1, 0 +_jjr9: fcvt.s.wu f9, x9 + la x1, _jjr10 + jalr x10, x1, 0 +_jjr10: fcvt.s.wu f10, x10 + la x1, _jjr11 + jalr x11, x1, 0 +_jjr11: fcvt.s.wu f11, x11 + la x1, _jjr12 + jalr x12, x1, 0 +_jjr12: fcvt.s.wu f12, x12 + la x1, _jjr13 + jalr x13, x1, 0 +_jjr13: fcvt.s.wu f13, x13 + la x1, _jjr14 + jalr x14, x1, 0 +_jjr14: fcvt.s.wu f14, x14 + la x1, _jjr15 + jalr x15, x1, 0 +_jjr15: fcvt.s.wu f15, x15 + la x1, _jjr16 + jalr x16, x1, 0 +_jjr16: fcvt.s.wu f16, x16 + la x1, _jjr17 + jalr x17, x1, 0 +_jjr17: fcvt.s.wu f17, x17 + la x1, _jjr18 + jalr x18, x1, 0 +_jjr18: fcvt.s.wu f18, x18 + la x1, _jjr19 + jalr x19, x1, 0 +_jjr19: fcvt.s.wu f19, x19 + la x1, _jjr20 + jalr x20, x1, 0 +_jjr20: fcvt.s.wu f20, x20 + la x1, _jjr21 + jalr x21, x1, 0 +_jjr21: fcvt.s.wu f21, x21 + la x1, _jjr22 + jalr x22, x1, 0 +_jjr22: fcvt.s.wu f22, x22 + la x1, _jjr23 + jalr x23, x1, 0 +_jjr23: fcvt.s.wu f23, x23 + la x1, _jjr24 + jalr x24, x1, 0 +_jjr24: fcvt.s.wu f24, x24 + la x1, _jjr25 + jalr x25, x1, 0 +_jjr25: fcvt.s.wu f25, x25 + la x1, _jjr26 + jalr x26, x1, 0 +_jjr26: fcvt.s.wu f26, x26 + la x1, _jjr27 + jalr x27, x1, 0 +_jjr27: fcvt.s.wu f27, x27 + la x1, _jjr28 + jalr x28, x1, 0 +_jjr28: fcvt.s.wu f28, x28 + la x1, _jjr29 + jalr x29, x1, 0 +_jjr29: fcvt.s.wu f29, x29 + la x1, _jjr30 + jalr x30, x1, 0 +_jjr30: fcvt.s.wu f30, x30 + la x1, _jjr31 + jalr x31, x1, 0 +_jjr31: fcvt.s.wu f31, x31 + la x1, _jjr0 + + // 5 + jal x0, _jf0 +_jf0: flw f0, 0(x0) + jal x1, _jf1 +_jf1: flw f0, 0(x1) + jal x2, _jf2 +_jf2: flw f0, 0(x2) + jal x3, _jf3 +_jf3: flw f0, 0(x3) + jal x4, _jf4 +_jf4: flw f0, 0(x4) + jal x5, _jf5 +_jf5: flw f0, 0(x5) + jal x6, _jf6 +_jf6: flw f0, 0(x6) + jal x7, _jf7 +_jf7: flw f0, 0(x7) + jal x8, _jf8 +_jf8: flw f0, 0(x8) + jal x9, _jf9 +_jf9: flw f0, 0(x9) + jal x10, _jf10 +_jf10: flw f0, 0(x10) + jal x11, _jf11 +_jf11: flw f0, 0(x11) + jal x12, _jf12 +_jf12: flw f0, 0(x12) + jal x13, _jf13 +_jf13: flw f0, 0(x13) + jal x14, _jf14 +_jf14: flw f0, 0(x14) + jal x15, _jf15 +_jf15: flw f0, 0(x15) + jal x16, _jf16 +_jf16: flw f0, 0(x16) + jal x17, _jf17 +_jf17: flw f0, 0(x17) + jal x18, _jf18 +_jf18: flw f0, 0(x18) + jal x19, _jf19 +_jf19: flw f0, 0(x19) + jal x20, _jf20 +_jf20: flw f0, 0(x20) + jal x21, _jf21 +_jf21: flw f0, 0(x21) + jal x22, _jf22 +_jf22: flw f0, 0(x22) + jal x23, _jf23 +_jf23: flw f0, 0(x23) + jal x24, _jf24 +_jf24: flw f0, 0(x24) + jal x25, _jf25 +_jf25: flw f0, 0(x25) + jal x26, _jf26 +_jf26: flw f0, 0(x26) + jal x27, _jf27 +_jf27: flw f0, 0(x27) + jal x28, _jf28 +_jf28: flw f0, 0(x28) + jal x29, _jf29 +_jf29: flw f0, 0(x29) + jal x30, _jf30 +_jf30: flw f0, 0(x30) + jal x31, _jf31 +_jf31: flw f0, 0(x31) + + // 6 + la x1, _jfr0 + jalr x0, x1, 0 +_jfr0: flw f0, 0(x0) + la x1, _jfr1 + jalr x1, x1, 0 +_jfr1: flw f0, 0(x1) + la x1, _jfr2 + jalr x2, x1, 0 +_jfr2: flw f0, 0(x2) + la x1, _jfr3 + jalr x3, x1, 0 +_jfr3: flw f0, 0(x3) + la x1, _jfr4 + jalr x4, x1, 0 +_jfr4: flw f0, 0(x4) + la x1, _jfr5 + jalr x5, x1, 0 +_jfr5: flw f0, 0(x5) + la x1, _jfr6 + jalr x6, x1, 0 +_jfr6: flw f0, 0(x6) + la x1, _jfr7 + jalr x7, x1, 0 +_jfr7: flw f0, 0(x7) + la x1, _jfr8 + jalr x8, x1, 0 +_jfr8: flw f0, 0(x8) + la x1, _jfr9 + jalr x9, x1, 0 +_jfr9: flw f0, 0(x9) + la x1, _jfr10 + jalr x10, x1, 0 +_jfr10: flw f0, 0(x10) + la x1, _jfr11 + jalr x11, x1, 0 +_jfr11: flw f0, 0(x11) + la x1, _jfr12 + jalr x12, x1, 0 +_jfr12: flw f0, 0(x12) + la x1, _jfr13 + jalr x13, x1, 0 +_jfr13: flw f0, 0(x13) + la x1, _jfr14 + jalr x14, x1, 0 +_jfr14: flw f0, 0(x14) + la x1, _jfr15 + jalr x15, x1, 0 +_jfr15: flw f0, 0(x15) + la x1, _jfr16 + jalr x16, x1, 0 +_jfr16: flw f0, 0(x16) + la x1, _jfr17 + jalr x17, x1, 0 +_jfr17: flw f0, 0(x17) + la x1, _jfr18 + jalr x18, x1, 0 +_jfr18: flw f0, 0(x18) + la x1, _jfr19 + jalr x19, x1, 0 +_jfr19: flw f0, 0(x19) + la x1, _jfr20 + jalr x20, x1, 0 +_jfr20: flw f0, 0(x20) + la x1, _jfr21 + jalr x21, x1, 0 +_jfr21: flw f0, 0(x21) + la x1, _jfr22 + jalr x22, x1, 0 +_jfr22: flw f0, 0(x22) + la x1, _jfr23 + jalr x23, x1, 0 +_jfr23: flw f0, 0(x23) + la x1, _jfr24 + jalr x24, x1, 0 +_jfr24: flw f0, 0(x24) + la x1, _jfr25 + jalr x25, x1, 0 +_jfr25: flw f0, 0(x25) + la x1, _jfr26 + jalr x26, x1, 0 +_jfr26: flw f0, 0(x26) + la x1, _jfr27 + jalr x27, x1, 0 +_jfr27: flw f0, 0(x27) + la x1, _jfr28 + jalr x28, x1, 0 +_jfr28: flw f0, 0(x28) + la x1, _jfr29 + jalr x29, x1, 0 +_jfr29: flw f0, 0(x29) + la x1, _jfr30 + jalr x30, x1, 0 +_jfr30: flw f0, 0(x30) + la x1, _jfr31 + jalr x31, x1, 0 +_jfr31: flw f0, 0(x31) + + # 7 + jal x0, _jm0 +_jm0: fmv.w.x f0, x0 + jal x1, _jm1 +_jm1: fmv.w.x f0, x1 + jal x2, _jm2 +_jm2: fmv.w.x f0, x2 + jal x3, _jm3 +_jm3: fmv.w.x f0, x3 + jal x4, _jm4 +_jm4: fmv.w.x f0, x4 + jal x5, _jm5 +_jm5: fmv.w.x f0, x5 + jal x6, _jm6 +_jm6: fmv.w.x f0, x6 + jal x7, _jm7 +_jm7: fmv.w.x f0, x7 + jal x8, _jm8 +_jm8: fmv.w.x f0, x8 + jal x9, _jm9 +_jm9: fmv.w.x f0, x9 + jal x10, _jm10 +_jm10: fmv.w.x f0, x10 + jal x11, _jm11 +_jm11: fmv.w.x f0, x11 + jal x12, _jm12 +_jm12: fmv.w.x f0, x12 + jal x13, _jm13 +_jm13: fmv.w.x f0, x13 + jal x14, _jm14 +_jm14: fmv.w.x f0, x14 + jal x15, _jm15 +_jm15: fmv.w.x f0, x15 + jal x16, _jm16 +_jm16: fmv.w.x f0, x16 + jal x17, _jm17 +_jm17: fmv.w.x f0, x17 + jal x18, _jm18 +_jm18: fmv.w.x f0, x18 + jal x19, _jm19 +_jm19: fmv.w.x f0, x19 + jal x20, _jm20 +_jm20: fmv.w.x f0, x20 + jal x21, _jm21 +_jm21: fmv.w.x f0, x21 + jal x22, _jm22 +_jm22: fmv.w.x f0, x22 + jal x23, _jm23 +_jm23: fmv.w.x f0, x23 + jal x24, _jm24 +_jm24: fmv.w.x f0, x24 + jal x25, _jm25 +_jm25: fmv.w.x f0, x25 + jal x26, _jm26 +_jm26: fmv.w.x f0, x26 + jal x27, _jm27 +_jm27: fmv.w.x f0, x27 + jal x28, _jm28 +_jm28: fmv.w.x f0, x28 + jal x29, _jm29 +_jm29: fmv.w.x f0, x29 + jal x30, _jm30 +_jm30: fmv.w.x f0, x30 + jal x31, _jm31 +_jm31: fmv.w.x f0, x31 + + # 8 + la x1, _jmr0 + jalr x0, x1, 0 +_jmr0: fmv.w.x f0, x0 + la x1, _jmr1 + jalr x1, x1, 0 +_jmr1: fmv.w.x f0, x1 + la x1, _jmr2 + jalr x2, x1, 0 +_jmr2: fmv.w.x f0, x2 + la x1, _jmr3 + jalr x3, x1, 0 +_jmr3: fmv.w.x f0, x3 + la x1, _jmr4 + jalr x4, x1, 0 +_jmr4: fmv.w.x f0, x4 + la x1, _jmr5 + jalr x5, x1, 0 +_jmr5: fmv.w.x f0, x5 + la x1, _jmr6 + jalr x6, x1, 0 +_jmr6: fmv.w.x f0, x6 + la x1, _jmr7 + jalr x7, x1, 0 +_jmr7: fmv.w.x f0, x7 + la x1, _jmr8 + jalr x8, x1, 0 +_jmr8: fmv.w.x f0, x8 + la x1, _jmr9 + jalr x9, x1, 0 +_jmr9: fmv.w.x f0, x9 + la x1, _jmr10 + jalr x10, x1, 0 +_jmr10: fmv.w.x f0, x10 + la x1, _jmr11 + jalr x11, x1, 0 +_jmr11: fmv.w.x f0, x11 + la x1, _jmr12 + jalr x12, x1, 0 +_jmr12: fmv.w.x f0, x12 + la x1, _jmr13 + jalr x13, x1, 0 +_jmr13: fmv.w.x f0, x13 + la x1, _jmr14 + jalr x14, x1, 0 +_jmr14: fmv.w.x f0, x14 + la x1, _jmr15 + jalr x15, x1, 0 +_jmr15: fmv.w.x f0, x15 + la x1, _jmr16 + jalr x16, x1, 0 +_jmr16: fmv.w.x f0, x16 + la x1, _jmr17 + jalr x17, x1, 0 +_jmr17: fmv.w.x f0, x17 + la x1, _jmr18 + jalr x18, x1, 0 +_jmr18: fmv.w.x f0, x18 + la x1, _jmr19 + jalr x19, x1, 0 +_jmr19: fmv.w.x f0, x19 + la x1, _jmr20 + jalr x20, x1, 0 +_jmr20: fmv.w.x f0, x20 + la x1, _jmr21 + jalr x21, x1, 0 +_jmr21: fmv.w.x f0, x21 + la x1, _jmr22 + jalr x22, x1, 0 +_jmr22: fmv.w.x f0, x22 + la x1, _jmr23 + jalr x23, x1, 0 +_jmr23: fmv.w.x f0, x23 + la x1, _jmr24 + jalr x24, x1, 0 +_jmr24: fmv.w.x f0, x24 + la x1, _jmr25 + jalr x25, x1, 0 +_jmr25: fmv.w.x f0, x25 + la x1, _jmr26 + jalr x26, x1, 0 +_jmr26: fmv.w.x f0, x26 + la x1, _jmr27 + jalr x27, x1, 0 +_jmr27: fmv.w.x f0, x27 + la x1, _jmr28 + jalr x28, x1, 0 +_jmr28: fmv.w.x f0, x28 + la x1, _jmr29 + jalr x29, x1, 0 +_jmr29: fmv.w.x f0, x29 + la x1, _jmr30 + jalr x30, x1, 0 +_jmr30: fmv.w.x f0, x30 + la x1, _jmr31 + jalr x31, x1, 0 +_jmr31: fmv.w.x f0, x31 + + + # 9 + auipc x0, 0x40000 + fsw f0, 0(x0) + auipc x1, 0x40000 + fsw f1, 0(x1) + auipc x2, 0x40000 + fsw f2, 0(x2) + auipc x3, 0x40000 + fsw f3, 0(x3) + auipc x4, 0x40000 + fsw f4, 0(x4) + auipc x5, 0x40000 + fsw f5, 0(x5) + auipc x6, 0x40000 + fsw f6, 0(x6) + auipc x7, 0x40000 + fsw f7, 0(x7) + auipc x8, 0x40000 + fsw f8, 0(x8) + auipc x9, 0x40000 + fsw f9, 0(x9) + auipc x10, 0x40000 + fsw f10, 0(x10) + auipc x11, 0x40000 + fsw f11, 0(x11) + auipc x12, 0x40000 + fsw f12, 0(x12) + auipc x13, 0x40000 + fsw f13, 0(x13) + auipc x14, 0x40000 + fsw f14, 0(x14) + auipc x15, 0x40000 + fsw f15, 0(x15) + auipc x16, 0x40000 + fsw f16, 0(x16) + auipc x17, 0x40000 + fsw f17, 0(x17) + auipc x18, 0x40000 + fsw f18, 0(x18) + auipc x19, 0x40000 + fsw f19, 0(x19) + auipc x20, 0x40000 + fsw f20, 0(x20) + auipc x21, 0x40000 + fsw f21, 0(x21) + auipc x22, 0x40000 + fsw f22, 0(x22) + auipc x23, 0x40000 + fsw f23, 0(x23) + auipc x24, 0x40000 + fsw f24, 0(x24) + auipc x25, 0x40000 + fsw f25, 0(x25) + auipc x26, 0x40000 + fsw f26, 0(x26) + auipc x27, 0x40000 + fsw f27, 0(x27) + auipc x28, 0x40000 + fsw f28, 0(x28) + auipc x29, 0x40000 + fsw f29, 0(x29) + auipc x30, 0x40000 + fsw f30, 0(x30) + auipc x31, 0x40000 + fsw f31, 0(x31) + + # 10 + jal x0, _jfs0 +_jfs0: fsw f0, 0(x0) + jal x1, _jfs1 +_jfs1: fsw f1, -8(x1) + jal x2, _jfs2 +_jfs2: fsw f2, -8(x2) + jal x3, _jfs3 +_jfs3: fsw f3, -8(x3) + jal x4, _jfs4 +_jfs4: fsw f4, -8(x4) + jal x5, _jfs5 +_jfs5: fsw f5, -8(x5) + jal x6, _jfs6 +_jfs6: fsw f6, -8(x6) + jal x7, _jfs7 +_jfs7: fsw f7, -8(x7) + jal x8, _jfs8 +_jfs8: fsw f8, -8(x8) + jal x9, _jfs9 +_jfs9: fsw f9, -8(x9) + jal x10, _jfs10 +_jfs10: fsw f10, -8(x10) + jal x11, _jfs11 +_jfs11: fsw f11, -8(x11) + jal x12, _jfs12 +_jfs12: fsw f12, -8(x12) + jal x13, _jfs13 +_jfs13: fsw f13, -8(x13) + jal x14, _jfs14 +_jfs14: fsw f14, -8(x14) + jal x15, _jfs15 +_jfs15: fsw f15, -8(x15) + jal x16, _jfs16 +_jfs16: fsw f16, -8(x16) + jal x17, _jfs17 +_jfs17: fsw f17, -8(x17) + jal x18, _jfs18 +_jfs18: fsw f18, -8(x18) + jal x19, _jfs19 +_jfs19: fsw f19, -8(x19) + jal x20, _jfs20 +_jfs20: fsw f20, -8(x20) + jal x21, _jfs21 +_jfs21: fsw f21, -8(x21) + jal x22, _jfs22 +_jfs22: fsw f22, -8(x22) + jal x23, _jfs23 +_jfs23: fsw f23, -8(x23) + jal x24, _jfs24 +_jfs24: fsw f24, -8(x24) + jal x25, _jfs25 +_jfs25: fsw f25, -8(x25) + jal x26, _jfs26 +_jfs26: fsw f26, -8(x26) + jal x27, _jfs27 +_jfs27: fsw f27, -8(x27) + jal x28, _jfs28 +_jfs28: fsw f28, -8(x28) + jal x29, _jfs29 +_jfs29: fsw f29, -8(x29) + jal x30, _jfs30 +_jfs30: fsw f30, -8(x30) + jal x31, _jfs31 +_jfs31: fsw f31, -8(x31) + + # 11 + la x1, _jrsw0 + jalr x0, x1, 0 +_jrsw0: fsw f0, 0(x0) + la x1, _jrsw1 + jalr x1, x1, 0 +_jrsw1: fsw f1, -8(x1) + la x1, _jrsw2 + jalr x2, x1, 0 +_jrsw2: fsw f2, -8(x2) + la x1, _jrsw3 + jalr x3, x1, 0 +_jrsw3: fsw f3, -8(x3) + la x1, _jrsw4 + jalr x4, x1, 0 +_jrsw4: fsw f4, -8(x4) + la x1, _jrsw5 + jalr x5, x1, 0 +_jrsw5: fsw f5, -8(x5) + la x1, _jrsw6 + jalr x6, x1, 0 +_jrsw6: fsw f6, -8(x6) + la x1, _jrsw7 + jalr x7, x1, 0 +_jrsw7: fsw f7, -8(x7) + la x1, _jrsw8 + jalr x8, x1, 0 +_jrsw8: fsw f8, -8(x8) + la x1, _jrsw9 + jalr x9, x1, 0 +_jrsw9: fsw f9, -8(x9) + la x1, _jrsw10 + jalr x10, x1, 0 +_jrsw10:fsw f10, -8(x10) + la x1, _jrsw11 + jalr x11, x1, 0 +_jrsw11:fsw f11, -8(x11) + la x1, _jrsw12 + jalr x12, x1, 0 +_jrsw12:fsw f12, -8(x12) + la x1, _jrsw13 + jalr x13, x1, 0 +_jrsw13:fsw f13, -8(x13) + la x1, _jrsw14 + jalr x14, x1, 0 +_jrsw14:fsw f14, -8(x14) + la x1, _jrsw15 + jalr x15, x1, 0 +_jrsw15:fsw f15, -8(x15) + la x1, _jrsw16 + jalr x16, x1, 0 +_jrsw16:fsw f16, -8(x16) + la x1, _jrsw17 + jalr x17, x1, 0 +_jrsw17:fsw f17, -8(x17) + la x1, _jrsw18 + jalr x18, x1, 0 +_jrsw18:fsw f18, -8(x18) + la x1, _jrsw19 + jalr x19, x1, 0 +_jrsw19:fsw f19, -8(x19) + la x1, _jrsw20 + jalr x20, x1, 0 +_jrsw20:fsw f20, -8(x20) + la x1, _jrsw21 + jalr x21, x1, 0 +_jrsw21:fsw f21, -8(x21) + la x1, _jrsw22 + jalr x22, x1, 0 +_jrsw22:fsw f22, -8(x22) + la x1, _jrsw23 + jalr x23, x1, 0 +_jrsw23:fsw f23, -8(x23) + la x1, _jrsw24 + jalr x24, x1, 0 +_jrsw24:fsw f24, -8(x24) + la x1, _jrsw25 + jalr x25, x1, 0 +_jrsw25:fsw f25, -8(x25) + la x1, _jrsw26 + jalr x26, x1, 0 +_jrsw26:fsw f26, -8(x26) + la x1, _jrsw27 + jalr x27, x1, 0 +_jrsw27:fsw f27, -8(x27) + la x1, _jrsw28 + jalr x28, x1, 0 +_jrsw28:fsw f28, -8(x28) + la x1, _jrsw29 + jalr x29, x1, 0 +_jrsw29:fsw f29, -8(x29) + la x1, _jrsw30 + jalr x30, x1, 0 +_jrsw30:fsw f30, -8(x30) + la x1, _jrsw31 + jalr x31, x1, 0 +_jrsw31:fsw f31, -8(x31) + + # 12 + sw x0, 0(x0) + lw x0, 0(x0) + fsw f0, 0(x0) + lw x1, 0(x0) + fsw f1, 0(x1) + lw x2, 0(x0) + fsw f2, 0(x2) + lw x3, 0(x0) + fsw f3, 0(x3) + lw x4, 0(x0) + fsw f4, 0(x4) + lw x5, 0(x0) + fsw f5, 0(x5) + lw x6, 0(x0) + fsw f6, 0(x6) + lw x7, 0(x0) + fsw f7, 0(x7) + lw x8, 0(x0) + fsw f8, 0(x8) + lw x9, 0(x0) + fsw f9, 0(x9) + lw x10, 0(x0) + fsw f10, 0(x10) + lw x11, 0(x0) + fsw f11, 0(x11) + lw x12, 0(x0) + fsw f12, 0(x12) + lw x13, 0(x0) + fsw f13, 0(x13) + lw x14, 0(x0) + fsw f14, 0(x14) + lw x15, 0(x0) + fsw f15, 0(x15) + lw x16, 0(x0) + fsw f16, 0(x16) + lw x17, 0(x0) + fsw f17, 0(x17) + lw x18, 0(x0) + fsw f18, 0(x18) + lw x19, 0(x0) + fsw f19, 0(x19) + lw x20, 0(x0) + fsw f20, 0(x20) + lw x21, 0(x0) + fsw f21, 0(x21) + lw x22, 0(x0) + fsw f22, 0(x22) + lw x23, 0(x0) + fsw f23, 0(x23) + lw x24, 0(x0) + fsw f24, 0(x24) + lw x25, 0(x0) + fsw f25, 0(x25) + lw x26, 0(x0) + fsw f26, 0(x26) + lw x27, 0(x0) + fsw f27, 0(x27) + lw x28, 0(x0) + fsw f28, 0(x28) + lw x29, 0(x0) + fsw f29, 0(x29) + lw x30, 0(x0) + fsw f30, 0(x30) + lw x31, 0(x0) + fsw f31, 0(x31) + + # 13 + lui x0, 0 + fsw f0, 0(x0) + lui x1, 0 + fsw f1, 0(x1) + lui x2, 0 + fsw f2, 0(x2) + lui x3, 0 + fsw f3, 0(x3) + lui x4, 0 + fsw f4, 0(x4) + lui x5, 0 + fsw f5, 0(x5) + lui x6, 0 + fsw f6, 0(x6) + lui x7, 0 + fsw f7, 0(x7) + lui x8, 0 + fsw f8, 0(x8) + lui x9, 0 + fsw f9, 0(x9) + lui x10, 0 + fsw f10, 0(x10) + lui x11, 0 + fsw f11, 0(x11) + lui x12, 0 + fsw f12, 0(x12) + lui x13, 0 + fsw f13, 0(x13) + lui x14, 0 + fsw f14, 0(x14) + lui x15, 0 + fsw f15, 0(x15) + lui x16, 0 + fsw f16, 0(x16) + lui x17, 0 + fsw f17, 0(x17) + lui x18, 0 + fsw f18, 0(x18) + lui x19, 0 + fsw f19, 0(x19) + lui x20, 0 + fsw f20, 0(x20) + lui x21, 0 + fsw f21, 0(x21) + lui x22, 0 + fsw f22, 0(x22) + lui x23, 0 + fsw f23, 0(x23) + lui x24, 0 + fsw f24, 0(x24) + lui x25, 0 + fsw f25, 0(x25) + lui x26, 0 + fsw f26, 0(x26) + lui x27, 0 + fsw f27, 0(x27) + lui x28, 0 + fsw f28, 0(x28) + lui x29, 0 + fsw f29, 0(x29) + lui x30, 0 + fsw f30, 0(x30) + lui x31, 0 + fsw f31, 0(x31) + + # 14 + mul x0, x0, x0 + fsw f0, 0(x0) + mul x1, x1, x0 + fsw f1, 0(x1) + mul x2, x2, x0 + fsw f2, 0(x2) + mul x3, x3, x0 + fsw f3, 0(x3) + mul x4, x4, x0 + fsw f4, 0(x4) + mul x5, x5, x0 + fsw f5, 0(x5) + mul x6, x6, x0 + fsw f6, 0(x6) + mul x7, x7, x0 + fsw f7, 0(x7) + mul x8, x8, x0 + fsw f8, 0(x8) + mul x9, x9, x0 + fsw f9, 0(x9) + mul x10, x10, x0 + fsw f10, 0(x10) + mul x11, x11, x0 + fsw f11, 0(x11) + mul x12, x12, x0 + fsw f12, 0(x12) + mul x13, x13, x0 + fsw f13, 0(x13) + mul x14, x14, x0 + fsw f14, 0(x14) + mul x15, x15, x0 + fsw f15, 0(x15) + mul x16, x16, x0 + fsw f16, 0(x16) + mul x17, x17, x0 + fsw f17, 0(x17) + mul x18, x18, x0 + fsw f18, 0(x18) + mul x19, x19, x0 + fsw f19, 0(x19) + mul x20, x20, x0 + fsw f20, 0(x20) + mul x21, x21, x0 + fsw f21, 0(x21) + mul x22, x22, x0 + fsw f22, 0(x22) + mul x23, x23, x0 + fsw f23, 0(x23) + mul x24, x24, x0 + fsw f24, 0(x24) + mul x25, x25, x0 + fsw f25, 0(x25) + mul x26, x26, x0 + fsw f26, 0(x26) + mul x27, x27, x0 + fsw f27, 0(x27) + mul x28, x28, x0 + fsw f28, 0(x28) + mul x29, x29, x0 + fsw f29, 0(x29) + mul x30, x30, x0 + fsw f30, 0(x30) + mul x31, x31, x0 + fsw f31, 0(x31) + + # 14 + addi x0, x0, 100 + fsw f0, 0(x0) + addi x1, x0, 100 + fsw f1, 0(x1) + addi x2, x0, 100 + fsw f2, 0(x2) + addi x3, x0, 100 + fsw f3, 0(x3) + addi x4, x0, 100 + fsw f4, 0(x4) + addi x5, x0, 100 + fsw f5, 0(x5) + addi x6, x0, 100 + fsw f6, 0(x6) + addi x7, x0, 100 + fsw f7, 0(x7) + addi x8, x0, 100 + fsw f8, 0(x8) + addi x9, x0, 100 + fsw f9, 0(x9) + addi x10, x0, 100 + fsw f10, 0(x10) + addi x11, x0, 100 + fsw f11, 0(x11) + addi x12, x0, 100 + fsw f12, 0(x12) + addi x13, x0, 100 + fsw f13, 0(x13) + addi x14, x0, 100 + fsw f14, 0(x14) + addi x15, x0, 100 + fsw f15, 0(x15) + addi x16, x0, 100 + fsw f16, 0(x16) + addi x17, x0, 100 + fsw f17, 0(x17) + addi x18, x0, 100 + fsw f18, 0(x18) + addi x19, x0, 100 + fsw f19, 0(x19) + addi x20, x0, 100 + fsw f20, 0(x20) + addi x21, x0, 100 + fsw f21, 0(x21) + addi x22, x0, 100 + fsw f22, 0(x22) + addi x23, x0, 100 + fsw f23, 0(x23) + addi x24, x0, 100 + fsw f24, 0(x24) + addi x25, x0, 100 + fsw f25, 0(x25) + addi x26, x0, 100 + fsw f26, 0(x26) + addi x27, x0, 100 + fsw f27, 0(x27) + addi x28, x0, 100 + fsw f28, 0(x28) + addi x29, x0, 100 + fsw f29, 0(x29) + addi x30, x0, 100 + fsw f30, 0(x30) + addi x31, x0, 100 + fsw f31, 0(x31) + + # 15 + sw x1, 0(x1) + cv.lbu x0, (x1), 4 + fsw f0, 0(x0) + cv.lbu x1, (x1), 4 + fsw f1, 0(x1) + cv.lbu x2, (x1), 4 + fsw f2, 0(x2) + cv.lbu x3, (x1), 4 + fsw f3, 0(x3) + cv.lbu x4, (x1), 4 + fsw f4, 0(x4) + cv.lbu x5, (x1), 4 + fsw f5, 0(x5) + cv.lbu x6, (x1), 4 + fsw f6, 0(x6) + cv.lbu x7, (x1), 4 + fsw f7, 0(x7) + cv.lbu x8, (x1), 4 + fsw f8, 0(x8) + cv.lbu x9, (x1), 4 + fsw f9, 0(x9) + cv.lbu x10, (x1), 4 + fsw f10, 0(x10) + cv.lbu x11, (x1), 4 + fsw f11, 0(x11) + cv.lbu x12, (x1), 4 + fsw f12, 0(x12) + cv.lbu x13, (x1), 4 + fsw f13, 0(x13) + cv.lbu x14, (x1), 4 + fsw f14, 0(x14) + cv.lbu x15, (x1), 4 + fsw f15, 0(x15) + cv.lbu x16, (x1), 4 + fsw f16, 0(x16) + cv.lbu x17, (x1), 4 + fsw f17, 0(x17) + cv.lbu x18, (x1), 4 + fsw f18, 0(x18) + cv.lbu x19, (x1), 4 + fsw f19, 0(x19) + cv.lbu x20, (x1), 4 + fsw f20, 0(x20) + cv.lbu x21, (x1), 4 + fsw f21, 0(x21) + cv.lbu x22, (x1), 4 + fsw f22, 0(x22) + cv.lbu x23, (x1), 4 + fsw f23, 0(x23) + cv.lbu x24, (x1), 4 + fsw f24, 0(x24) + cv.lbu x25, (x1), 4 + fsw f25, 0(x25) + cv.lbu x26, (x1), 4 + fsw f26, 0(x26) + cv.lbu x27, (x1), 4 + fsw f27, 0(x27) + cv.lbu x28, (x1), 4 + fsw f28, 0(x28) + cv.lbu x29, (x1), 4 + fsw f29, 0(x29) + cv.lbu x30, (x1), 4 + fsw f30, 0(x30) + cv.lbu x31, (x1), 4 + fsw f31, 0(x31) + + # 16 + sw x1, 0(x1) + cv.lbu x0, (x1), x0 + fsw f0, 0(x0) + cv.lbu x1, (x1), x0 + fsw f1, 0(x1) + cv.lbu x2, (x1), x0 + fsw f2, 0(x2) + cv.lbu x3, (x1), x0 + fsw f3, 0(x3) + cv.lbu x4, (x1), x0 + fsw f4, 0(x4) + cv.lbu x5, (x1), x0 + fsw f5, 0(x5) + cv.lbu x6, (x1), x0 + fsw f6, 0(x6) + cv.lbu x7, (x1), x0 + fsw f7, 0(x7) + cv.lbu x8, (x1), x0 + fsw f8, 0(x8) + cv.lbu x9, (x1), x0 + fsw f9, 0(x9) + cv.lbu x10, (x1), x0 + fsw f10, 0(x10) + cv.lbu x11, (x1), x0 + fsw f11, 0(x11) + cv.lbu x12, (x1), x0 + fsw f12, 0(x12) + cv.lbu x13, (x1), x0 + fsw f13, 0(x13) + cv.lbu x14, (x1), x0 + fsw f14, 0(x14) + cv.lbu x15, (x1), x0 + fsw f15, 0(x15) + cv.lbu x16, (x1), x0 + fsw f16, 0(x16) + cv.lbu x17, (x1), x0 + fsw f17, 0(x17) + cv.lbu x18, (x1), x0 + fsw f18, 0(x18) + cv.lbu x19, (x1), x0 + fsw f19, 0(x19) + cv.lbu x20, (x1), x0 + fsw f20, 0(x20) + cv.lbu x21, (x1), x0 + fsw f21, 0(x21) + cv.lbu x22, (x1), x0 + fsw f22, 0(x22) + cv.lbu x23, (x1), x0 + fsw f23, 0(x23) + cv.lbu x24, (x1), x0 + fsw f24, 0(x24) + cv.lbu x25, (x1), x0 + fsw f25, 0(x25) + cv.lbu x26, (x1), x0 + fsw f26, 0(x26) + cv.lbu x27, (x1), x0 + fsw f27, 0(x27) + cv.lbu x28, (x1), x0 + fsw f28, 0(x28) + cv.lbu x29, (x1), x0 + fsw f29, 0(x29) + cv.lbu x30, (x1), x0 + fsw f30, 0(x30) + cv.lbu x31, (x1), x0 + fsw f31, 0(x31) + + # 17 + cv.addun x0, x0, x0, 0 + fsw f0, 0(x0) + cv.addun x1, x1, x0, 0 + fsw f1, 0(x1) + cv.addun x2, x2, x0, 0 + fsw f2, 0(x2) + cv.addun x3, x3, x0, 0 + fsw f3, 0(x3) + cv.addun x4, x4, x0, 0 + fsw f4, 0(x4) + cv.addun x5, x5, x0, 0 + fsw f5, 0(x5) + cv.addun x6, x6, x0, 0 + fsw f6, 0(x6) + cv.addun x7, x7, x0, 0 + fsw f7, 0(x7) + cv.addun x8, x8, x0, 0 + fsw f8, 0(x8) + cv.addun x9, x9, x0, 0 + fsw f9, 0(x9) + cv.addun x10, x10, x0, 0 + fsw f10, 0(x10) + cv.addun x11, x11, x0, 0 + fsw f11, 0(x11) + cv.addun x12, x12, x0, 0 + fsw f12, 0(x12) + cv.addun x13, x13, x0, 0 + fsw f13, 0(x13) + cv.addun x14, x14, x0, 0 + fsw f14, 0(x14) + cv.addun x15, x15, x0, 0 + fsw f15, 0(x15) + cv.addun x16, x16, x0, 0 + fsw f16, 0(x16) + cv.addun x17, x17, x0, 0 + fsw f17, 0(x17) + cv.addun x18, x18, x0, 0 + fsw f18, 0(x18) + cv.addun x19, x19, x0, 0 + fsw f19, 0(x19) + cv.addun x20, x20, x0, 0 + fsw f20, 0(x20) + cv.addun x21, x21, x0, 0 + fsw f21, 0(x21) + cv.addun x22, x22, x0, 0 + fsw f22, 0(x22) + cv.addun x23, x23, x0, 0 + fsw f23, 0(x23) + cv.addun x24, x24, x0, 0 + fsw f24, 0(x24) + cv.addun x25, x25, x0, 0 + fsw f25, 0(x25) + cv.addun x26, x26, x0, 0 + fsw f26, 0(x26) + cv.addun x27, x27, x0, 0 + fsw f27, 0(x27) + cv.addun x28, x28, x0, 0 + fsw f28, 0(x28) + cv.addun x29, x29, x0, 0 + fsw f29, 0(x29) + cv.addun x30, x30, x0, 0 + fsw f30, 0(x30) + cv.addun x31, x31, x0, 0 + fsw f31, 0(x31) + + # 18 + cv.add.b x0, x0, x0 + fsw f0, 0(x0) + cv.add.b x1, x1, x0 + fsw f1, 0(x1) + cv.add.b x2, x2, x0 + fsw f2, 0(x2) + cv.add.b x3, x3, x0 + fsw f3, 0(x3) + cv.add.b x4, x4, x0 + fsw f4, 0(x4) + cv.add.b x5, x5, x0 + fsw f5, 0(x5) + cv.add.b x6, x6, x0 + fsw f6, 0(x6) + cv.add.b x7, x7, x0 + fsw f7, 0(x7) + cv.add.b x8, x8, x0 + fsw f8, 0(x8) + cv.add.b x9, x9, x0 + fsw f9, 0(x9) + cv.add.b x10, x10, x0 + fsw f10, 0(x10) + cv.add.b x11, x11, x0 + fsw f11, 0(x11) + cv.add.b x12, x12, x0 + fsw f12, 0(x12) + cv.add.b x13, x13, x0 + fsw f13, 0(x13) + cv.add.b x14, x14, x0 + fsw f14, 0(x14) + cv.add.b x15, x15, x0 + fsw f15, 0(x15) + cv.add.b x16, x16, x0 + fsw f16, 0(x16) + cv.add.b x17, x17, x0 + fsw f17, 0(x17) + cv.add.b x18, x18, x0 + fsw f18, 0(x18) + cv.add.b x19, x19, x0 + fsw f19, 0(x19) + cv.add.b x20, x20, x0 + fsw f20, 0(x20) + cv.add.b x21, x21, x0 + fsw f21, 0(x21) + cv.add.b x22, x22, x0 + fsw f22, 0(x22) + cv.add.b x23, x23, x0 + fsw f23, 0(x23) + cv.add.b x24, x24, x0 + fsw f24, 0(x24) + cv.add.b x25, x25, x0 + fsw f25, 0(x25) + cv.add.b x26, x26, x0 + fsw f26, 0(x26) + cv.add.b x27, x27, x0 + fsw f27, 0(x27) + cv.add.b x28, x28, x0 + fsw f28, 0(x28) + cv.add.b x29, x29, x0 + fsw f29, 0(x29) + cv.add.b x30, x30, x0 + fsw f30, 0(x30) + cv.add.b x31, x31, x0 + fsw f31, 0(x31) + + # 19 + sw x1, 0(x1) + cv.lbu x0, (x1), 4 + fcvt.s.wu f0, x0 + cv.lbu x1, (x1), 4 + fcvt.s.wu f1, x1 + cv.lbu x2, (x1), 4 + fcvt.s.wu f2, x2 + cv.lbu x3, (x1), 4 + fcvt.s.wu f3, x3 + cv.lbu x4, (x1), 4 + fcvt.s.wu f4, x4 + cv.lbu x5, (x1), 4 + fcvt.s.wu f5, x5 + cv.lbu x6, (x1), 4 + fcvt.s.wu f6, x6 + cv.lbu x7, (x1), 4 + fcvt.s.wu f7, x7 + cv.lbu x8, (x1), 4 + fcvt.s.wu f8, x8 + cv.lbu x9, (x1), 4 + fcvt.s.wu f9, x9 + cv.lbu x10, (x1), 4 + fcvt.s.wu f10, x10 + cv.lbu x11, (x1), 4 + fcvt.s.wu f11, x11 + cv.lbu x12, (x1), 4 + fcvt.s.wu f12, x12 + cv.lbu x13, (x1), 4 + fcvt.s.wu f13, x13 + cv.lbu x14, (x1), 4 + fcvt.s.wu f14, x14 + cv.lbu x15, (x1), 4 + fcvt.s.wu f15, x15 + cv.lbu x16, (x1), 4 + fcvt.s.wu f16, x16 + cv.lbu x17, (x1), 4 + fcvt.s.wu f17, x17 + cv.lbu x18, (x1), 4 + fcvt.s.wu f18, x18 + cv.lbu x19, (x1), 4 + fcvt.s.wu f19, x19 + cv.lbu x20, (x1), 4 + fcvt.s.wu f20, x20 + cv.lbu x21, (x1), 4 + fcvt.s.wu f21, x21 + cv.lbu x22, (x1), 4 + fcvt.s.wu f22, x22 + cv.lbu x23, (x1), 4 + fcvt.s.wu f23, x23 + cv.lbu x24, (x1), 4 + fcvt.s.wu f24, x24 + cv.lbu x25, (x1), 4 + fcvt.s.wu f25, x25 + cv.lbu x26, (x1), 4 + fcvt.s.wu f26, x26 + cv.lbu x27, (x1), 4 + fcvt.s.wu f27, x27 + cv.lbu x28, (x1), 4 + fcvt.s.wu f28, x28 + cv.lbu x29, (x1), 4 + fcvt.s.wu f29, x29 + cv.lbu x30, (x1), 4 + fcvt.s.wu f30, x30 + cv.lbu x31, (x1), 4 + fcvt.s.wu f31, x31 + + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end + ######### FOR PULP_FPU CFG - END ######### + + li x18, TEST_PASS + +test_end: + li x17, VIRT_PERIPH_STATUS_FLAG_ADDR + sw x18,0(x17) + j _exit + +_exit: + j _exit + diff --git a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml new file mode 100644 index 0000000000..ef5b8cece8 --- /dev/null +++ b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/test.yaml @@ -0,0 +1,6 @@ +# Test definition YAML for test + +name: fpu_func_cov_improve_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + This test is to close coverage holes for uvme_cv32e40p_fp_instr_covg. From bbb960d389a4759d1ec18c0199e34282fa51378b Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Wed, 17 Apr 2024 10:25:39 +0800 Subject: [PATCH 10/12] Fix to generate legal imm6 value for certain SIMD instructions Signed-off-by: dd-baoshan --- .../custom/isa/custom/riscv_custom_instr.sv | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv index 415b1cb1cb..46f95aa488 100644 --- a/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv +++ b/cv32e40p/env/corev-dv/custom/isa/custom/riscv_custom_instr.sv @@ -20,6 +20,7 @@ class cv32e40p_instr extends riscv_instr; // additionnal helper fields bit is_post_incr; bit is_r_format ; + bit is_simd_imm_legal = 1; bit hw_loop_label; @@ -676,7 +677,30 @@ class cv32e40p_instr extends riscv_instr; this.is_r_format = rhs_.is_r_format; endfunction : do_copy + virtual function void override_imm(); + if (category == SIMD) begin + if (is_simd_imm_legal) begin + case (instr_name) + CV_EXTRACT_H, CV_EXTRACTU_H, CV_INSERT_H : imm[5:1] = 5'd0; + CV_EXTRACT_B, CV_EXTRACTU_B, CV_INSERT_B, CV_SHUFFLE_SCI_H : imm[5:2] = 4'd0; + CV_SLL_SCI_B, CV_SRL_SCI_B, CV_SRA_SCI_B : imm[5:3] = 3'd0; + CV_SLL_SCI_H, CV_SRL_SCI_H, CV_SRA_SCI_H : imm[5:4] = 2'd0; + endcase + end + else begin + // below imms value lead to illegal exception + case (instr_name) + CV_EXTRACT_H, CV_EXTRACTU_H, CV_INSERT_H : imm[5:1] = $urandom_range(1, 31); + CV_EXTRACT_B, CV_EXTRACTU_B, CV_INSERT_B, CV_SHUFFLE_SCI_H : imm[5:2] = $urandom_range(1, 15); + CV_SLL_SCI_B, CV_SRL_SCI_B, CV_SRA_SCI_B : imm[5:3] = $urandom_range(1, 7); + CV_SLL_SCI_H, CV_SRL_SCI_H, CV_SRA_SCI_H : imm[5:4] = $urandom_range(1, 3); + endcase + end + end + endfunction : override_imm + virtual function void update_imm_str(); + override_imm(); if (category == BRANCH_IMM) begin // for branch imm, immediate is split in two parts imm_str = $sformatf("%0d, %0d", $signed(imm[16:12]), $signed(imm[11:0])); From 026ce2ad249d7c307fc431d963774b78a63e0601 Mon Sep 17 00:00:00 2001 From: Bee Nee Lim Date: Wed, 17 Apr 2024 04:36:11 +0200 Subject: [PATCH 11/12] Update code coverage waivers' line number following RTL v1.7.2 Signed-off-by: Bee Nee Lim --- .../cv32e40pv2_code_all_cfg_waiver.do | 132 +++++++++--------- .../cv32e40pv2_code_pulp_cfg_waiver.do | 2 +- 2 files changed, 67 insertions(+), 67 deletions(-) diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do index 27d299dc61..3708b08bc1 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_all_cfg_waiver.do @@ -100,46 +100,46 @@ coverage exclude -line 473 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 477 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} coverage exclude -line 478 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} coverage exclude -line 520 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } -coverage exclude -line 604 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw} -coverage exclude -line 605 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw} -coverage exclude -line 742 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0.} -coverage exclude -line 798 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 799 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 893 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 894 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 895 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 897 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 898 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 901 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 1006 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 1007 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 1008 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 1010 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 1011 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} -coverage exclude -line 1016 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1017 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1018 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1019 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1020 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} -coverage exclude -line 1061 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} -coverage exclude -line 1062 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} -coverage exclude -line 1117 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1118 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1119 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1219 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } -coverage exclude -line 1220 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } -coverage exclude -line 1221 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } -coverage exclude -line 1223 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } -coverage exclude -line 1224 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 614 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw} +coverage exclude -line 615 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw} +coverage exclude -line 752 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0.} +coverage exclude -line 818 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 819 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 913 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 914 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 915 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 917 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 918 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 921 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1026 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1027 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1028 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1030 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1031 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error.} +coverage exclude -line 1036 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1037 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1038 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1039 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1040 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0.} +coverage exclude -line 1081 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} +coverage exclude -line 1082 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} +coverage exclude -line 1131 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1132 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1133 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1233 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1234 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1235 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1237 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } +coverage exclude -line 1238 -code s -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI data error. data_err_i tied to 0. } coverage exclude -line 421 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} coverage exclude -line 522 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 744 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 921 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1031 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} -coverage exclude -line 1042 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} -coverage exclude -line 1052 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} +coverage exclude -line 754 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 941 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1051 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} +coverage exclude -line 1062 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} +coverage exclude -line 1072 -code c -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Single-step not possible during debug mode.} coverage exclude -line 299 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 824 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No PC = Hwloop1 end & Hwloop 1 counter = 0 in DECODE_HWLOOP FSM state.} +coverage exclude -line 844 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No PC = Hwloop1 end & Hwloop 1 counter = 0 in DECODE_HWLOOP FSM state.} coverage exclude -line 418 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } coverage exclude -line 421 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} coverage exclude -line 447 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } @@ -148,34 +148,34 @@ coverage exclude -line 459 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv3 coverage exclude -line 464 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } coverage exclude -line 519 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0. } coverage exclude -line 522 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 603 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 604 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 604 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 741 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0.} -coverage exclude -line 744 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 797 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 798 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 798 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 890 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 897 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 897 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 921 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 930 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 970 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} -coverage exclude -line 1004 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 1011 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 1011 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 1014 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1019 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1019 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } -coverage exclude -line 1060 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} -coverage exclude -line 1097 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Unreacheable default code.} -coverage exclude -line 1128 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Unreacheable default code.} -coverage exclude -line 1115 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1117 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1117 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} -coverage exclude -line 1216 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 1223 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } -coverage exclude -line 1223 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 613 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 614 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 614 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 751 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No Secure interrupt line. irq_sec_i tied to 0.} +coverage exclude -line 754 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 817 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 818 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 818 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 910 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 917 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 917 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 941 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 950 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 990 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No cv.elw.} +coverage exclude -line 1024 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1031 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1031 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1034 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1039 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1039 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Instr error. instr_err_i tied to 0. } +coverage exclude -line 1080 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Can't be reached as uret instruction is illegal instruction.} +coverage exclude -line 1111 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Unreacheable default code.} +coverage exclude -line 1142 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {Unreacheable default code.} +coverage exclude -line 1129 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1131 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1131 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No User Privilege Mode.} +coverage exclude -line 1230 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1237 -code b -item 1 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } +coverage exclude -line 1237 -code b -item 2 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No OBI Data error. data_err_i tied to 0. } coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/interrupt_assert_i -recursive -comment {this is TB module bind to RTL. No need code coverage.} coverage exclude -code bcefs -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/if_stage_i/prefetch_buffer_i/prefetch_controller_i/prefetch_controller_sva -recursive -comment {this is TB module bind to RTL. No need code coverage.} diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do index 7c69c5cdd4..696a7ccec9 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_pulp_cfg_waiver.do @@ -56,7 +56,7 @@ coverage exclude -line 272 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb coverage exclude -line 278 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 284 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/load_store_unit_i -comment {No FPU in this configuration.} coverage exclude -line 2983 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/decoder_i -comment {No FPU in this configuration.} -coverage exclude -line 1376 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} +coverage exclude -line 1390 -code e -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/controller_i -comment {No FPU in this configuration.} coverage exclude -line 89 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 90 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} coverage exclude -line 91 -code b -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/id_stage_i/register_file_i -comment {No FPU in this configuration.} From 95ad7c2ad8e27339dcd828d367bf6ee4bb0e361d Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Thu, 18 Apr 2024 13:06:08 +0800 Subject: [PATCH 12/12] Add custom test to improve functional coverage holes (uvme_cv32e40p_zfinx_instr_covg) Signed-off-by: dd-baoshan --- .../cv32e40pv2_for_func_cvg_improvement.yaml | 18 + cv32e40p/regress/cv32e40pv2_fpu_instr.yaml | 18 + .../zfinx_func_cov_improve_test/test.yaml | 6 + .../zfinx_func_cov_improve_test.S | 3705 +++++++++++++++++ 4 files changed, 3747 insertions(+) create mode 100644 cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml create mode 100644 cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S diff --git a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml index 0dd639b2e5..3400f236b5 100644 --- a/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml +++ b/cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml @@ -80,3 +80,21 @@ tests: - pulp_cluster_fpu_2cyclat - default - no_pulp + + zfinx_func_cov_improve_test: + build: uvmt_cv32e40p + description: directed custom test to improve missing coverage in cfg pulp_zfinx + dir: cv32e40p/sim/uvmt + cmd: make test TEST=zfinx_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000" + num: 1 + skip_sim: + - pulp + - pulp_fpu + - pulp_fpu_1cyclat + - pulp_fpu_2cyclat + - pulp_cluster + - pulp_cluster_fpu + - pulp_cluster_fpu_1cyclat + - pulp_cluster_fpu_2cyclat + - default + - no_pulp diff --git a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml index ce570548f8..9c8773ebd7 100644 --- a/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml +++ b/cv32e40p/regress/cv32e40pv2_fpu_instr.yaml @@ -81,3 +81,21 @@ tests: - pulp_cluster_fpu_2cyclat - default - no_pulp + + zfinx_func_cov_improve_test: + build: uvmt_cv32e40p + description: directed custom test to improve missing coverage in cfg pulp_zfinx + dir: cv32e40p/sim/uvmt + cmd: make test TEST=zfinx_func_cov_improve_test CFG_PLUSARGS="+UVM_TIMEOUT=100000000" + num: 1 + skip_sim: + - pulp + - pulp_fpu + - pulp_fpu_1cyclat + - pulp_fpu_2cyclat + - pulp_cluster + - pulp_cluster_fpu + - pulp_cluster_fpu_1cyclat + - pulp_cluster_fpu_2cyclat + - default + - no_pulp diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml new file mode 100644 index 0000000000..e41dff3377 --- /dev/null +++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/test.yaml @@ -0,0 +1,6 @@ +# Test definition YAML for test + +name: zfinx_func_cov_improve_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + This test is to close coverage holes for uvme_cv32e40p_zfinx_instr_covg. diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S new file mode 100644 index 0000000000..6ce5adab44 --- /dev/null +++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S @@ -0,0 +1,3705 @@ + +.globl _start +.globl main +.globl exit +.section .text + +#define TEST_PASS 123456789 +#define TEST_FAIL 1 +#define VIRT_PERIPH_STATUS_FLAG_ADDR 0x20000000 + +main: + li t0, (0x0 << 3) + csrs mstatus, t0 + li x31, 0x0 + +#if defined(FPU) + li x5, 0x00003800 + csrw 0x300, x5 # MSTATUS FPU enable +#endif + + ######### FOR PULP_FPU CFG - START ######### + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - start + .align 2 + + // 1 - jal -> fsub (rs1, rs2) + jal x0, _fsub_j0 +_fsub_j0: fsub.s x0, x0, x0 + jal x1, _fsub_j1 +_fsub_j1: fsub.s x1, x1, x1 + jal x2, _fsub_j2 +_fsub_j2: fsub.s x2, x2, x2 + jal x3, _fsub_j3 +_fsub_j3: fsub.s x3, x3, x3 + jal x4, _fsub_j4 +_fsub_j4: fsub.s x4, x4, x4 + jal x5, _fsub_j5 +_fsub_j5: fsub.s x5, x5, x5 + jal x6, _fsub_j6 +_fsub_j6: fsub.s x6, x6, x6 + jal x7, _fsub_j7 +_fsub_j7: fsub.s x7, x7, x7 + jal x8, _fsub_j8 +_fsub_j8: fsub.s x8, x8, x8 + jal x9, _fsub_j9 +_fsub_j9: fsub.s x9, x9, x9 + jal x10, _fsub_j10 +_fsub_j10: fsub.s x10, x10, x10 + jal x11, _fsub_j11 +_fsub_j11: fsub.s x11, x11, x11 + jal x12, _fsub_j12 +_fsub_j12: fsub.s x12, x12, x12 + jal x13, _fsub_j13 +_fsub_j13: fsub.s x13, x13, x13 + jal x14, _fsub_j14 +_fsub_j14: fsub.s x14, x14, x14 + jal x15, _fsub_j15 +_fsub_j15: fsub.s x15, x15, x15 + jal x16, _fsub_j16 +_fsub_j16: fsub.s x16, x16, x16 + jal x17, _fsub_j17 +_fsub_j17: fsub.s x17, x17, x17 + jal x18, _fsub_j18 +_fsub_j18: fsub.s x18, x18, x18 + jal x19, _fsub_j19 +_fsub_j19: fsub.s x19, x19, x19 + jal x20, _fsub_j20 +_fsub_j20: fsub.s x20, x20, x20 + jal x21, _fsub_j21 +_fsub_j21: fsub.s x21, x21, x21 + jal x22, _fsub_j22 +_fsub_j22: fsub.s x22, x22, x22 + jal x23, _fsub_j23 +_fsub_j23: fsub.s x23, x23, x23 + jal x24, _fsub_j24 +_fsub_j24: fsub.s x24, x24, x24 + jal x25, _fsub_j25 +_fsub_j25: fsub.s x25, x25, x25 + jal x26, _fsub_j26 +_fsub_j26: fsub.s x26, x26, x26 + jal x27, _fsub_j27 +_fsub_j27: fsub.s x27, x27, x27 + jal x28, _fsub_j28 +_fsub_j28: fsub.s x28, x28, x28 + jal x29, _fsub_j29 +_fsub_j29: fsub.s x29, x29, x29 + jal x30, _fsub_j30 +_fsub_j30: fsub.s x30, x30, x30 + jal x31, _fsub_j31 +_fsub_j31: fsub.s x31, x31, x31 + + // 2 - jalr -> fsub (rs1, rs2) + la x1, _fsub_jr0 + jalr x0, x1, 0 +_fsub_jr0: fsub.s x0, x0, x0 + la x1, _fsub_jr1 + jalr x1, x1, 0 +_fsub_jr1: fsub.s x1, x1, x1 + la x1, _fsub_jr2 + jalr x2, x1, 0 +_fsub_jr2: fsub.s x2, x2, x2 + la x1, _fsub_jr3 + jalr x3, x1, 0 +_fsub_jr3: fsub.s x3, x3, x3 + la x1, _fsub_jr4 + jalr x4, x1, 0 +_fsub_jr4: fsub.s x4, x4, x4 + la x1, _fsub_jr5 + jalr x5, x1, 0 +_fsub_jr5: fsub.s x5, x5, x5 + la x1, _fsub_jr6 + jalr x6, x1, 0 +_fsub_jr6: fsub.s x6, x6, x6 + la x1, _fsub_jr7 + jalr x7, x1, 0 +_fsub_jr7: fsub.s x7, x7, x7 + la x1, _fsub_jr8 + jalr x8, x1, 0 +_fsub_jr8: fsub.s x8, x8, x8 + la x1, _fsub_jr9 + jalr x9, x1, 0 +_fsub_jr9: fsub.s x9, x9, x9 + la x1, _fsub_jr10 + jalr x10, x1, 0 +_fsub_jr10: fsub.s x10, x10, x10 + la x1, _fsub_jr11 + jalr x11, x1, 0 +_fsub_jr11: fsub.s x11, x11, x11 + la x1, _fsub_jr12 + jalr x12, x1, 0 +_fsub_jr12: fsub.s x12, x12, x12 + la x1, _fsub_jr13 + jalr x13, x1, 0 +_fsub_jr13: fsub.s x13, x13, x13 + la x1, _fsub_jr14 + jalr x14, x1, 0 +_fsub_jr14: fsub.s x14, x14, x14 + la x1, _fsub_jr15 + jalr x15, x1, 0 +_fsub_jr15: fsub.s x15, x15, x15 + la x1, _fsub_jr16 + jalr x16, x1, 0 +_fsub_jr16: fsub.s x16, x16, x16 + la x1, _fsub_jr17 + jalr x17, x1, 0 +_fsub_jr17: fsub.s x17, x17, x17 + la x1, _fsub_jr18 + jalr x18, x1, 0 +_fsub_jr18: fsub.s x18, x18, x18 + la x1, _fsub_jr19 + jalr x19, x1, 0 +_fsub_jr19: fsub.s x19, x19, x19 + la x1, _fsub_jr20 + jalr x20, x1, 0 +_fsub_jr20: fsub.s x20, x20, x20 + la x1, _fsub_jr21 + jalr x21, x1, 0 +_fsub_jr21: fsub.s x21, x21, x21 + la x1, _fsub_jr22 + jalr x22, x1, 0 +_fsub_jr22: fsub.s x22, x22, x22 + la x1, _fsub_jr23 + jalr x23, x1, 0 +_fsub_jr23: fsub.s x23, x23, x23 + la x1, _fsub_jr24 + jalr x24, x1, 0 +_fsub_jr24: fsub.s x24, x24, x24 + la x1, _fsub_jr25 + jalr x25, x1, 0 +_fsub_jr25: fsub.s x25, x25, x25 + la x1, _fsub_jr26 + jalr x26, x1, 0 +_fsub_jr26: fsub.s x26, x26, x26 + la x1, _fsub_jr27 + jalr x27, x1, 0 +_fsub_jr27: fsub.s x27, x27, x27 + la x1, _fsub_jr28 + jalr x28, x1, 0 +_fsub_jr28: fsub.s x28, x28, x28 + la x1, _fsub_jr29 + jalr x29, x1, 0 +_fsub_jr29: fsub.s x29, x29, x29 + la x1, _fsub_jr30 + jalr x30, x1, 0 +_fsub_jr30: fsub.s x30, x30, x30 + la x1, _fsub_jr31 + jalr x31, x1, 0 +_fsub_jr31: fsub.s x31, x31, x31 + + // 3 - jal -> fsqrt (rs1) + jal x0, _fsqrt_j0 +_fsqrt_j0: fsqrt.s x0, x0 + jal x1, _fsqrt_j1 +_fsqrt_j1: fsqrt.s x1, x1 + jal x2, _fsqrt_j2 +_fsqrt_j2: fsqrt.s x2, x2 + jal x3, _fsqrt_j3 +_fsqrt_j3: fsqrt.s x3, x3 + jal x4, _fsqrt_j4 +_fsqrt_j4: fsqrt.s x4, x4 + jal x5, _fsqrt_j5 +_fsqrt_j5: fsqrt.s x5, x5 + jal x6, _fsqrt_j6 +_fsqrt_j6: fsqrt.s x6, x6 + jal x7, _fsqrt_j7 +_fsqrt_j7: fsqrt.s x7, x7 + jal x8, _fsqrt_j8 +_fsqrt_j8: fsqrt.s x8, x8 + jal x9, _fsqrt_j9 +_fsqrt_j9: fsqrt.s x9, x9 + jal x10, _fsqrt_j10 +_fsqrt_j10: fsqrt.s x10, x10 + jal x11, _fsqrt_j11 +_fsqrt_j11: fsqrt.s x11, x11 + jal x12, _fsqrt_j12 +_fsqrt_j12: fsqrt.s x12, x12 + jal x13, _fsqrt_j13 +_fsqrt_j13: fsqrt.s x13, x13 + jal x14, _fsqrt_j14 +_fsqrt_j14: fsqrt.s x14, x14 + jal x15, _fsqrt_j15 +_fsqrt_j15: fsqrt.s x15, x15 + jal x16, _fsqrt_j16 +_fsqrt_j16: fsqrt.s x16, x16 + jal x17, _fsqrt_j17 +_fsqrt_j17: fsqrt.s x17, x17 + jal x18, _fsqrt_j18 +_fsqrt_j18: fsqrt.s x18, x18 + jal x19, _fsqrt_j19 +_fsqrt_j19: fsqrt.s x19, x19 + jal x20, _fsqrt_j20 +_fsqrt_j20: fsqrt.s x20, x20 + jal x21, _fsqrt_j21 +_fsqrt_j21: fsqrt.s x21, x21 + jal x22, _fsqrt_j22 +_fsqrt_j22: fsqrt.s x22, x22 + jal x23, _fsqrt_j23 +_fsqrt_j23: fsqrt.s x23, x23 + jal x24, _fsqrt_j24 +_fsqrt_j24: fsqrt.s x24, x24 + jal x25, _fsqrt_j25 +_fsqrt_j25: fsqrt.s x25, x25 + jal x26, _fsqrt_j26 +_fsqrt_j26: fsqrt.s x26, x26 + jal x27, _fsqrt_j27 +_fsqrt_j27: fsqrt.s x27, x27 + jal x28, _fsqrt_j28 +_fsqrt_j28: fsqrt.s x28, x28 + jal x29, _fsqrt_j29 +_fsqrt_j29: fsqrt.s x29, x29 + jal x30, _fsqrt_j30 +_fsqrt_j30: fsqrt.s x30, x30 + jal x31, _fsqrt_j31 +_fsqrt_j31: fsqrt.s x31, x31 + + // 4 - jalr -> fsqrt (rs1, rs2) + la x1, _fsqrt_jr0 + jalr x0, x1, 0 +_fsqrt_jr0: fsqrt.s x0, x0 + la x1, _fsqrt_jr1 + jalr x1, x1, 0 +_fsqrt_jr1: fsqrt.s x1, x1 + la x1, _fsqrt_jr2 + jalr x2, x1, 0 +_fsqrt_jr2: fsqrt.s x2, x2 + la x1, _fsqrt_jr3 + jalr x3, x1, 0 +_fsqrt_jr3: fsqrt.s x3, x3 + la x1, _fsqrt_jr4 + jalr x4, x1, 0 +_fsqrt_jr4: fsqrt.s x4, x4 + la x1, _fsqrt_jr5 + jalr x5, x1, 0 +_fsqrt_jr5: fsqrt.s x5, x5 + la x1, _fsqrt_jr6 + jalr x6, x1, 0 +_fsqrt_jr6: fsqrt.s x6, x6 + la x1, _fsqrt_jr7 + jalr x7, x1, 0 +_fsqrt_jr7: fsqrt.s x7, x7 + la x1, _fsqrt_jr8 + jalr x8, x1, 0 +_fsqrt_jr8: fsqrt.s x8, x8 + la x1, _fsqrt_jr9 + jalr x9, x1, 0 +_fsqrt_jr9: fsqrt.s x9, x9 + la x1, _fsqrt_jr10 + jalr x10, x1, 0 +_fsqrt_jr10: fsqrt.s x10, x10 + la x1, _fsqrt_jr11 + jalr x11, x1, 0 +_fsqrt_jr11: fsqrt.s x11, x11 + la x1, _fsqrt_jr12 + jalr x12, x1, 0 +_fsqrt_jr12: fsqrt.s x12, x12 + la x1, _fsqrt_jr13 + jalr x13, x1, 0 +_fsqrt_jr13: fsqrt.s x13, x13 + la x1, _fsqrt_jr14 + jalr x14, x1, 0 +_fsqrt_jr14: fsqrt.s x14, x14 + la x1, _fsqrt_jr15 + jalr x15, x1, 0 +_fsqrt_jr15: fsqrt.s x15, x15 + la x1, _fsqrt_jr16 + jalr x16, x1, 0 +_fsqrt_jr16: fsqrt.s x16, x16 + la x1, _fsqrt_jr17 + jalr x17, x1, 0 +_fsqrt_jr17: fsqrt.s x17, x17 + la x1, _fsqrt_jr18 + jalr x18, x1, 0 +_fsqrt_jr18: fsqrt.s x18, x18 + la x1, _fsqrt_jr19 + jalr x19, x1, 0 +_fsqrt_jr19: fsqrt.s x19, x19 + la x1, _fsqrt_jr20 + jalr x20, x1, 0 +_fsqrt_jr20: fsqrt.s x20, x20 + la x1, _fsqrt_jr21 + jalr x21, x1, 0 +_fsqrt_jr21: fsqrt.s x21, x21 + la x1, _fsqrt_jr22 + jalr x22, x1, 0 +_fsqrt_jr22: fsqrt.s x22, x22 + la x1, _fsqrt_jr23 + jalr x23, x1, 0 +_fsqrt_jr23: fsqrt.s x23, x23 + la x1, _fsqrt_jr24 + jalr x24, x1, 0 +_fsqrt_jr24: fsqrt.s x24, x24 + la x1, _fsqrt_jr25 + jalr x25, x1, 0 +_fsqrt_jr25: fsqrt.s x25, x25 + la x1, _fsqrt_jr26 + jalr x26, x1, 0 +_fsqrt_jr26: fsqrt.s x26, x26 + la x1, _fsqrt_jr27 + jalr x27, x1, 0 +_fsqrt_jr27: fsqrt.s x27, x27 + la x1, _fsqrt_jr28 + jalr x28, x1, 0 +_fsqrt_jr28: fsqrt.s x28, x28 + la x1, _fsqrt_jr29 + jalr x29, x1, 0 +_fsqrt_jr29: fsqrt.s x29, x29 + la x1, _fsqrt_jr30 + jalr x30, x1, 0 +_fsqrt_jr30: fsqrt.s x30, x30 + la x1, _fsqrt_jr31 + jalr x31, x1, 0 +_fsqrt_jr31: fsqrt.s x31, x31 + + // 5 - jal -> fadd (rs1, rs2) + jal x0, _fadd_j0 +_fadd_j0: fadd.s x0, x0, x0 + jal x1, _fadd_j1 +_fadd_j1: fadd.s x1, x1, x1 + jal x2, _fadd_j2 +_fadd_j2: fadd.s x2, x2, x2 + jal x3, _fadd_j3 +_fadd_j3: fadd.s x3, x3, x3 + jal x4, _fadd_j4 +_fadd_j4: fadd.s x4, x4, x4 + jal x5, _fadd_j5 +_fadd_j5: fadd.s x5, x5, x5 + jal x6, _fadd_j6 +_fadd_j6: fadd.s x6, x6, x6 + jal x7, _fadd_j7 +_fadd_j7: fadd.s x7, x7, x7 + jal x8, _fadd_j8 +_fadd_j8: fadd.s x8, x8, x8 + jal x9, _fadd_j9 +_fadd_j9: fadd.s x9, x9, x9 + jal x10, _fadd_j10 +_fadd_j10: fadd.s x10, x10, x10 + jal x11, _fadd_j11 +_fadd_j11: fadd.s x11, x11, x11 + jal x12, _fadd_j12 +_fadd_j12: fadd.s x12, x12, x12 + jal x13, _fadd_j13 +_fadd_j13: fadd.s x13, x13, x13 + jal x14, _fadd_j14 +_fadd_j14: fadd.s x14, x14, x14 + jal x15, _fadd_j15 +_fadd_j15: fadd.s x15, x15, x15 + jal x16, _fadd_j16 +_fadd_j16: fadd.s x16, x16, x16 + jal x17, _fadd_j17 +_fadd_j17: fadd.s x17, x17, x17 + jal x18, _fadd_j18 +_fadd_j18: fadd.s x18, x18, x18 + jal x19, _fadd_j19 +_fadd_j19: fadd.s x19, x19, x19 + jal x20, _fadd_j20 +_fadd_j20: fadd.s x20, x20, x20 + jal x21, _fadd_j21 +_fadd_j21: fadd.s x21, x21, x21 + jal x22, _fadd_j22 +_fadd_j22: fadd.s x22, x22, x22 + jal x23, _fadd_j23 +_fadd_j23: fadd.s x23, x23, x23 + jal x24, _fadd_j24 +_fadd_j24: fadd.s x24, x24, x24 + jal x25, _fadd_j25 +_fadd_j25: fadd.s x25, x25, x25 + jal x26, _fadd_j26 +_fadd_j26: fadd.s x26, x26, x26 + jal x27, _fadd_j27 +_fadd_j27: fadd.s x27, x27, x27 + jal x28, _fadd_j28 +_fadd_j28: fadd.s x28, x28, x28 + jal x29, _fadd_j29 +_fadd_j29: fadd.s x29, x29, x29 + jal x30, _fadd_j30 +_fadd_j30: fadd.s x30, x30, x30 + jal x31, _fadd_j31 +_fadd_j31: fadd.s x31, x31, x31 + + // 6 - jalr -> fadd (rs1, rs2) + la x1, _fadd_jr0 + jalr x0, x1, 0 +_fadd_jr0: fadd.s x0, x0, x0 + la x1, _fadd_jr1 + jalr x1, x1, 0 +_fadd_jr1: fadd.s x1, x1, x1 + la x1, _fadd_jr2 + jalr x2, x1, 0 +_fadd_jr2: fadd.s x2, x2, x2 + la x1, _fadd_jr3 + jalr x3, x1, 0 +_fadd_jr3: fadd.s x3, x3, x3 + la x1, _fadd_jr4 + jalr x4, x1, 0 +_fadd_jr4: fadd.s x4, x4, x4 + la x1, _fadd_jr5 + jalr x5, x1, 0 +_fadd_jr5: fadd.s x5, x5, x5 + la x1, _fadd_jr6 + jalr x6, x1, 0 +_fadd_jr6: fadd.s x6, x6, x6 + la x1, _fadd_jr7 + jalr x7, x1, 0 +_fadd_jr7: fadd.s x7, x7, x7 + la x1, _fadd_jr8 + jalr x8, x1, 0 +_fadd_jr8: fadd.s x8, x8, x8 + la x1, _fadd_jr9 + jalr x9, x1, 0 +_fadd_jr9: fadd.s x9, x9, x9 + la x1, _fadd_jr10 + jalr x10, x1, 0 +_fadd_jr10: fadd.s x10, x10, x10 + la x1, _fadd_jr11 + jalr x11, x1, 0 +_fadd_jr11: fadd.s x11, x11, x11 + la x1, _fadd_jr12 + jalr x12, x1, 0 +_fadd_jr12: fadd.s x12, x12, x12 + la x1, _fadd_jr13 + jalr x13, x1, 0 +_fadd_jr13: fadd.s x13, x13, x13 + la x1, _fadd_jr14 + jalr x14, x1, 0 +_fadd_jr14: fadd.s x14, x14, x14 + la x1, _fadd_jr15 + jalr x15, x1, 0 +_fadd_jr15: fadd.s x15, x15, x15 + la x1, _fadd_jr16 + jalr x16, x1, 0 +_fadd_jr16: fadd.s x16, x16, x16 + la x1, _fadd_jr17 + jalr x17, x1, 0 +_fadd_jr17: fadd.s x17, x17, x17 + la x1, _fadd_jr18 + jalr x18, x1, 0 +_fadd_jr18: fadd.s x18, x18, x18 + la x1, _fadd_jr19 + jalr x19, x1, 0 +_fadd_jr19: fadd.s x19, x19, x19 + la x1, _fadd_jr20 + jalr x20, x1, 0 +_fadd_jr20: fadd.s x20, x20, x20 + la x1, _fadd_jr21 + jalr x21, x1, 0 +_fadd_jr21: fadd.s x21, x21, x21 + la x1, _fadd_jr22 + jalr x22, x1, 0 +_fadd_jr22: fadd.s x22, x22, x22 + la x1, _fadd_jr23 + jalr x23, x1, 0 +_fadd_jr23: fadd.s x23, x23, x23 + la x1, _fadd_jr24 + jalr x24, x1, 0 +_fadd_jr24: fadd.s x24, x24, x24 + la x1, _fadd_jr25 + jalr x25, x1, 0 +_fadd_jr25: fadd.s x25, x25, x25 + la x1, _fadd_jr26 + jalr x26, x1, 0 +_fadd_jr26: fadd.s x26, x26, x26 + la x1, _fadd_jr27 + jalr x27, x1, 0 +_fadd_jr27: fadd.s x27, x27, x27 + la x1, _fadd_jr28 + jalr x28, x1, 0 +_fadd_jr28: fadd.s x28, x28, x28 + la x1, _fadd_jr29 + jalr x29, x1, 0 +_fadd_jr29: fadd.s x29, x29, x29 + la x1, _fadd_jr30 + jalr x30, x1, 0 +_fadd_jr30: fadd.s x30, x30, x30 + la x1, _fadd_jr31 + jalr x31, x1, 0 +_fadd_jr31: fadd.s x31, x31, x31 + + // 7 - jal -> fclass (rs1) + jal x0, _fclass_j0 +_fclass_j0: fclass.s x0, x0 + jal x1, _fclass_j1 +_fclass_j1: fclass.s x1, x1 + jal x2, _fclass_j2 +_fclass_j2: fclass.s x2, x2 + jal x3, _fclass_j3 +_fclass_j3: fclass.s x3, x3 + jal x4, _fclass_j4 +_fclass_j4: fclass.s x4, x4 + jal x5, _fclass_j5 +_fclass_j5: fclass.s x5, x5 + jal x6, _fclass_j6 +_fclass_j6: fclass.s x6, x6 + jal x7, _fclass_j7 +_fclass_j7: fclass.s x7, x7 + jal x8, _fclass_j8 +_fclass_j8: fclass.s x8, x8 + jal x9, _fclass_j9 +_fclass_j9: fclass.s x9, x9 + jal x10, _fclass_j10 +_fclass_j10: fclass.s x10, x10 + jal x11, _fclass_j11 +_fclass_j11: fclass.s x11, x11 + jal x12, _fclass_j12 +_fclass_j12: fclass.s x12, x12 + jal x13, _fclass_j13 +_fclass_j13: fclass.s x13, x13 + jal x14, _fclass_j14 +_fclass_j14: fclass.s x14, x14 + jal x15, _fclass_j15 +_fclass_j15: fclass.s x15, x15 + jal x16, _fclass_j16 +_fclass_j16: fclass.s x16, x16 + jal x17, _fclass_j17 +_fclass_j17: fclass.s x17, x17 + jal x18, _fclass_j18 +_fclass_j18: fclass.s x18, x18 + jal x19, _fclass_j19 +_fclass_j19: fclass.s x19, x19 + jal x20, _fclass_j20 +_fclass_j20: fclass.s x20, x20 + jal x21, _fclass_j21 +_fclass_j21: fclass.s x21, x21 + jal x22, _fclass_j22 +_fclass_j22: fclass.s x22, x22 + jal x23, _fclass_j23 +_fclass_j23: fclass.s x23, x23 + jal x24, _fclass_j24 +_fclass_j24: fclass.s x24, x24 + jal x25, _fclass_j25 +_fclass_j25: fclass.s x25, x25 + jal x26, _fclass_j26 +_fclass_j26: fclass.s x26, x26 + jal x27, _fclass_j27 +_fclass_j27: fclass.s x27, x27 + jal x28, _fclass_j28 +_fclass_j28: fclass.s x28, x28 + jal x29, _fclass_j29 +_fclass_j29: fclass.s x29, x29 + jal x30, _fclass_j30 +_fclass_j30: fclass.s x30, x30 + jal x31, _fclass_j31 +_fclass_j31: fclass.s x31, x31 + + // 8 - jalr -> fclass (rs1) + la x1, _fclass_jr0 + jalr x0, x1, 0 +_fclass_jr0: fclass.s x0, x0 + la x1, _fclass_jr1 + jalr x1, x1, 0 +_fclass_jr1: fclass.s x1, x1 + la x1, _fclass_jr2 + jalr x2, x1, 0 +_fclass_jr2: fclass.s x2, x2 + la x1, _fclass_jr3 + jalr x3, x1, 0 +_fclass_jr3: fclass.s x3, x3 + la x1, _fclass_jr4 + jalr x4, x1, 0 +_fclass_jr4: fclass.s x4, x4 + la x1, _fclass_jr5 + jalr x5, x1, 0 +_fclass_jr5: fclass.s x5, x5 + la x1, _fclass_jr6 + jalr x6, x1, 0 +_fclass_jr6: fclass.s x6, x6 + la x1, _fclass_jr7 + jalr x7, x1, 0 +_fclass_jr7: fclass.s x7, x7 + la x1, _fclass_jr8 + jalr x8, x1, 0 +_fclass_jr8: fclass.s x8, x8 + la x1, _fclass_jr9 + jalr x9, x1, 0 +_fclass_jr9: fclass.s x9, x9 + la x1, _fclass_jr10 + jalr x10, x1, 0 +_fclass_jr10: fclass.s x10, x10 + la x1, _fclass_jr11 + jalr x11, x1, 0 +_fclass_jr11: fclass.s x11, x11 + la x1, _fclass_jr12 + jalr x12, x1, 0 +_fclass_jr12: fclass.s x12, x12 + la x1, _fclass_jr13 + jalr x13, x1, 0 +_fclass_jr13: fclass.s x13, x13 + la x1, _fclass_jr14 + jalr x14, x1, 0 +_fclass_jr14: fclass.s x14, x14 + la x1, _fclass_jr15 + jalr x15, x1, 0 +_fclass_jr15: fclass.s x15, x15 + la x1, _fclass_jr16 + jalr x16, x1, 0 +_fclass_jr16: fclass.s x16, x16 + la x1, _fclass_jr17 + jalr x17, x1, 0 +_fclass_jr17: fclass.s x17, x17 + la x1, _fclass_jr18 + jalr x18, x1, 0 +_fclass_jr18: fclass.s x18, x18 + la x1, _fclass_jr19 + jalr x19, x1, 0 +_fclass_jr19: fclass.s x19, x19 + la x1, _fclass_jr20 + jalr x20, x1, 0 +_fclass_jr20: fclass.s x20, x20 + la x1, _fclass_jr21 + jalr x21, x1, 0 +_fclass_jr21: fclass.s x21, x21 + la x1, _fclass_jr22 + jalr x22, x1, 0 +_fclass_jr22: fclass.s x22, x22 + la x1, _fclass_jr23 + jalr x23, x1, 0 +_fclass_jr23: fclass.s x23, x23 + la x1, _fclass_jr24 + jalr x24, x1, 0 +_fclass_jr24: fclass.s x24, x24 + la x1, _fclass_jr25 + jalr x25, x1, 0 +_fclass_jr25: fclass.s x25, x25 + la x1, _fclass_jr26 + jalr x26, x1, 0 +_fclass_jr26: fclass.s x26, x26 + la x1, _fclass_jr27 + jalr x27, x1, 0 +_fclass_jr27: fclass.s x27, x27 + la x1, _fclass_jr28 + jalr x28, x1, 0 +_fclass_jr28: fclass.s x28, x28 + la x1, _fclass_jr29 + jalr x29, x1, 0 +_fclass_jr29: fclass.s x29, x29 + la x1, _fclass_jr30 + jalr x30, x1, 0 +_fclass_jr30: fclass.s x30, x30 + la x1, _fclass_jr31 + jalr x31, x1, 0 +_fclass_jr31: fclass.s x31, x31 + + // 9 - jal -> fcvt.s.w (rs1) + jal x0, _fcvtsw_j0 +_fcvtsw_j0: fcvt.s.w x0, x0 + jal x1, _fcvtsw_j1 +_fcvtsw_j1: fcvt.s.w x1, x1 + jal x2, _fcvtsw_j2 +_fcvtsw_j2: fcvt.s.w x2, x2 + jal x3, _fcvtsw_j3 +_fcvtsw_j3: fcvt.s.w x3, x3 + jal x4, _fcvtsw_j4 +_fcvtsw_j4: fcvt.s.w x4, x4 + jal x5, _fcvtsw_j5 +_fcvtsw_j5: fcvt.s.w x5, x5 + jal x6, _fcvtsw_j6 +_fcvtsw_j6: fcvt.s.w x6, x6 + jal x7, _fcvtsw_j7 +_fcvtsw_j7: fcvt.s.w x7, x7 + jal x8, _fcvtsw_j8 +_fcvtsw_j8: fcvt.s.w x8, x8 + jal x9, _fcvtsw_j9 +_fcvtsw_j9: fcvt.s.w x9, x9 + jal x10, _fcvtsw_j10 +_fcvtsw_j10: fcvt.s.w x10, x10 + jal x11, _fcvtsw_j11 +_fcvtsw_j11: fcvt.s.w x11, x11 + jal x12, _fcvtsw_j12 +_fcvtsw_j12: fcvt.s.w x12, x12 + jal x13, _fcvtsw_j13 +_fcvtsw_j13: fcvt.s.w x13, x13 + jal x14, _fcvtsw_j14 +_fcvtsw_j14: fcvt.s.w x14, x14 + jal x15, _fcvtsw_j15 +_fcvtsw_j15: fcvt.s.w x15, x15 + jal x16, _fcvtsw_j16 +_fcvtsw_j16: fcvt.s.w x16, x16 + jal x17, _fcvtsw_j17 +_fcvtsw_j17: fcvt.s.w x17, x17 + jal x18, _fcvtsw_j18 +_fcvtsw_j18: fcvt.s.w x18, x18 + jal x19, _fcvtsw_j19 +_fcvtsw_j19: fcvt.s.w x19, x19 + jal x20, _fcvtsw_j20 +_fcvtsw_j20: fcvt.s.w x20, x20 + jal x21, _fcvtsw_j21 +_fcvtsw_j21: fcvt.s.w x21, x21 + jal x22, _fcvtsw_j22 +_fcvtsw_j22: fcvt.s.w x22, x22 + jal x23, _fcvtsw_j23 +_fcvtsw_j23: fcvt.s.w x23, x23 + jal x24, _fcvtsw_j24 +_fcvtsw_j24: fcvt.s.w x24, x24 + jal x25, _fcvtsw_j25 +_fcvtsw_j25: fcvt.s.w x25, x25 + jal x26, _fcvtsw_j26 +_fcvtsw_j26: fcvt.s.w x26, x26 + jal x27, _fcvtsw_j27 +_fcvtsw_j27: fcvt.s.w x27, x27 + jal x28, _fcvtsw_j28 +_fcvtsw_j28: fcvt.s.w x28, x28 + jal x29, _fcvtsw_j29 +_fcvtsw_j29: fcvt.s.w x29, x29 + jal x30, _fcvtsw_j30 +_fcvtsw_j30: fcvt.s.w x30, x30 + jal x31, _fcvtsw_j31 +_fcvtsw_j31: fcvt.s.w x31, x31 + + // 10 - jal -> fcvt.s.w (rs1) + la x1, _fcvtsw_jr0 + jalr x0, x1, 0 +_fcvtsw_jr0: fcvt.s.w x0, x0 + la x1, _fcvtsw_jr1 + jalr x1, x1, 0 +_fcvtsw_jr1: fcvt.s.w x1, x1 + la x1, _fcvtsw_jr2 + jalr x2, x1, 0 +_fcvtsw_jr2: fcvt.s.w x2, x2 + la x1, _fcvtsw_jr3 + jalr x3, x1, 0 +_fcvtsw_jr3: fcvt.s.w x3, x3 + la x1, _fcvtsw_jr4 + jalr x4, x1, 0 +_fcvtsw_jr4: fcvt.s.w x4, x4 + la x1, _fcvtsw_jr5 + jalr x5, x1, 0 +_fcvtsw_jr5: fcvt.s.w x5, x5 + la x1, _fcvtsw_jr6 + jalr x6, x1, 0 +_fcvtsw_jr6: fcvt.s.w x6, x6 + la x1, _fcvtsw_jr7 + jalr x7, x1, 0 +_fcvtsw_jr7: fcvt.s.w x7, x7 + la x1, _fcvtsw_jr8 + jalr x8, x1, 0 +_fcvtsw_jr8: fcvt.s.w x8, x8 + la x1, _fcvtsw_jr9 + jalr x9, x1, 0 +_fcvtsw_jr9: fcvt.s.w x9, x9 + la x1, _fcvtsw_jr10 + jalr x10, x1, 0 +_fcvtsw_jr10: fcvt.s.w x10, x10 + la x1, _fcvtsw_jr11 + jalr x11, x1, 0 +_fcvtsw_jr11: fcvt.s.w x11, x11 + la x1, _fcvtsw_jr12 + jalr x12, x1, 0 +_fcvtsw_jr12: fcvt.s.w x12, x12 + la x1, _fcvtsw_jr13 + jalr x13, x1, 0 +_fcvtsw_jr13: fcvt.s.w x13, x13 + la x1, _fcvtsw_jr14 + jalr x14, x1, 0 +_fcvtsw_jr14: fcvt.s.w x14, x14 + la x1, _fcvtsw_jr15 + jalr x15, x1, 0 +_fcvtsw_jr15: fcvt.s.w x15, x15 + la x1, _fcvtsw_jr16 + jalr x16, x1, 0 +_fcvtsw_jr16: fcvt.s.w x16, x16 + la x1, _fcvtsw_jr17 + jalr x17, x1, 0 +_fcvtsw_jr17: fcvt.s.w x17, x17 + la x1, _fcvtsw_jr18 + jalr x18, x1, 0 +_fcvtsw_jr18: fcvt.s.w x18, x18 + la x1, _fcvtsw_jr19 + jalr x19, x1, 0 +_fcvtsw_jr19: fcvt.s.w x19, x19 + la x1, _fcvtsw_jr20 + jalr x20, x1, 0 +_fcvtsw_jr20: fcvt.s.w x20, x20 + la x1, _fcvtsw_jr21 + jalr x21, x1, 0 +_fcvtsw_jr21: fcvt.s.w x21, x21 + la x1, _fcvtsw_jr22 + jalr x22, x1, 0 +_fcvtsw_jr22: fcvt.s.w x22, x22 + la x1, _fcvtsw_jr23 + jalr x23, x1, 0 +_fcvtsw_jr23: fcvt.s.w x23, x23 + la x1, _fcvtsw_jr24 + jalr x24, x1, 0 +_fcvtsw_jr24: fcvt.s.w x24, x24 + la x1, _fcvtsw_jr25 + jalr x25, x1, 0 +_fcvtsw_jr25: fcvt.s.w x25, x25 + la x1, _fcvtsw_jr26 + jalr x26, x1, 0 +_fcvtsw_jr26: fcvt.s.w x26, x26 + la x1, _fcvtsw_jr27 + jalr x27, x1, 0 +_fcvtsw_jr27: fcvt.s.w x27, x27 + la x1, _fcvtsw_jr28 + jalr x28, x1, 0 +_fcvtsw_jr28: fcvt.s.w x28, x28 + la x1, _fcvtsw_jr29 + jalr x29, x1, 0 +_fcvtsw_jr29: fcvt.s.w x29, x29 + la x1, _fcvtsw_jr30 + jalr x30, x1, 0 +_fcvtsw_jr30: fcvt.s.w x30, x30 + la x1, _fcvtsw_jr31 + jalr x31, x1, 0 +_fcvtsw_jr31: fcvt.s.w x31, x31 + + // 11 - jal -> fcvtswu (rs1) + jal x0, _fcvtswu_j0 +_fcvtswu_j0: fcvt.s.wu x0, x0 + jal x1, _fcvtswu_j1 +_fcvtswu_j1: fcvt.s.wu x1, x1 + jal x2, _fcvtswu_j2 +_fcvtswu_j2: fcvt.s.wu x2, x2 + jal x3, _fcvtswu_j3 +_fcvtswu_j3: fcvt.s.wu x3, x3 + jal x4, _fcvtswu_j4 +_fcvtswu_j4: fcvt.s.wu x4, x4 + jal x5, _fcvtswu_j5 +_fcvtswu_j5: fcvt.s.wu x5, x5 + jal x6, _fcvtswu_j6 +_fcvtswu_j6: fcvt.s.wu x6, x6 + jal x7, _fcvtswu_j7 +_fcvtswu_j7: fcvt.s.wu x7, x7 + jal x8, _fcvtswu_j8 +_fcvtswu_j8: fcvt.s.wu x8, x8 + jal x9, _fcvtswu_j9 +_fcvtswu_j9: fcvt.s.wu x9, x9 + jal x10, _fcvtswu_j10 +_fcvtswu_j10: fcvt.s.wu x10, x10 + jal x11, _fcvtswu_j11 +_fcvtswu_j11: fcvt.s.wu x11, x11 + jal x12, _fcvtswu_j12 +_fcvtswu_j12: fcvt.s.wu x12, x12 + jal x13, _fcvtswu_j13 +_fcvtswu_j13: fcvt.s.wu x13, x13 + jal x14, _fcvtswu_j14 +_fcvtswu_j14: fcvt.s.wu x14, x14 + jal x15, _fcvtswu_j15 +_fcvtswu_j15: fcvt.s.wu x15, x15 + jal x16, _fcvtswu_j16 +_fcvtswu_j16: fcvt.s.wu x16, x16 + jal x17, _fcvtswu_j17 +_fcvtswu_j17: fcvt.s.wu x17, x17 + jal x18, _fcvtswu_j18 +_fcvtswu_j18: fcvt.s.wu x18, x18 + jal x19, _fcvtswu_j19 +_fcvtswu_j19: fcvt.s.wu x19, x19 + jal x20, _fcvtswu_j20 +_fcvtswu_j20: fcvt.s.wu x20, x20 + jal x21, _fcvtswu_j21 +_fcvtswu_j21: fcvt.s.wu x21, x21 + jal x22, _fcvtswu_j22 +_fcvtswu_j22: fcvt.s.wu x22, x22 + jal x23, _fcvtswu_j23 +_fcvtswu_j23: fcvt.s.wu x23, x23 + jal x24, _fcvtswu_j24 +_fcvtswu_j24: fcvt.s.wu x24, x24 + jal x25, _fcvtswu_j25 +_fcvtswu_j25: fcvt.s.wu x25, x25 + jal x26, _fcvtswu_j26 +_fcvtswu_j26: fcvt.s.wu x26, x26 + jal x27, _fcvtswu_j27 +_fcvtswu_j27: fcvt.s.wu x27, x27 + jal x28, _fcvtswu_j28 +_fcvtswu_j28: fcvt.s.wu x28, x28 + jal x29, _fcvtswu_j29 +_fcvtswu_j29: fcvt.s.wu x29, x29 + jal x30, _fcvtswu_j30 +_fcvtswu_j30: fcvt.s.wu x30, x30 + jal x31, _fcvtswu_j31 +_fcvtswu_j31: fcvt.s.wu x31, x31 + + // 12 - jalr -> fcvtswu (rs1) + la x1, _fcvtswu_jr0 + jalr x0, x1, 0 +_fcvtswu_jr0: fcvt.s.wu x0, x0 + la x1, _fcvtswu_jr1 + jalr x1, x1, 0 +_fcvtswu_jr1: fcvt.s.wu x1, x1 + la x1, _fcvtswu_jr2 + jalr x2, x1, 0 +_fcvtswu_jr2: fcvt.s.wu x2, x2 + la x1, _fcvtswu_jr3 + jalr x3, x1, 0 +_fcvtswu_jr3: fcvt.s.wu x3, x3 + la x1, _fcvtswu_jr4 + jalr x4, x1, 0 +_fcvtswu_jr4: fcvt.s.wu x4, x4 + la x1, _fcvtswu_jr5 + jalr x5, x1, 0 +_fcvtswu_jr5: fcvt.s.wu x5, x5 + la x1, _fcvtswu_jr6 + jalr x6, x1, 0 +_fcvtswu_jr6: fcvt.s.wu x6, x6 + la x1, _fcvtswu_jr7 + jalr x7, x1, 0 +_fcvtswu_jr7: fcvt.s.wu x7, x7 + la x1, _fcvtswu_jr8 + jalr x8, x1, 0 +_fcvtswu_jr8: fcvt.s.wu x8, x8 + la x1, _fcvtswu_jr9 + jalr x9, x1, 0 +_fcvtswu_jr9: fcvt.s.wu x9, x9 + la x1, _fcvtswu_jr10 + jalr x10, x1, 0 +_fcvtswu_jr10: fcvt.s.wu x10, x10 + la x1, _fcvtswu_jr11 + jalr x11, x1, 0 +_fcvtswu_jr11: fcvt.s.wu x11, x11 + la x1, _fcvtswu_jr12 + jalr x12, x1, 0 +_fcvtswu_jr12: fcvt.s.wu x12, x12 + la x1, _fcvtswu_jr13 + jalr x13, x1, 0 +_fcvtswu_jr13: fcvt.s.wu x13, x13 + la x1, _fcvtswu_jr14 + jalr x14, x1, 0 +_fcvtswu_jr14: fcvt.s.wu x14, x14 + la x1, _fcvtswu_jr15 + jalr x15, x1, 0 +_fcvtswu_jr15: fcvt.s.wu x15, x15 + la x1, _fcvtswu_jr16 + jalr x16, x1, 0 +_fcvtswu_jr16: fcvt.s.wu x16, x16 + la x1, _fcvtswu_jr17 + jalr x17, x1, 0 +_fcvtswu_jr17: fcvt.s.wu x17, x17 + la x1, _fcvtswu_jr18 + jalr x18, x1, 0 +_fcvtswu_jr18: fcvt.s.wu x18, x18 + la x1, _fcvtswu_jr19 + jalr x19, x1, 0 +_fcvtswu_jr19: fcvt.s.wu x19, x19 + la x1, _fcvtswu_jr20 + jalr x20, x1, 0 +_fcvtswu_jr20: fcvt.s.wu x20, x20 + la x1, _fcvtswu_jr21 + jalr x21, x1, 0 +_fcvtswu_jr21: fcvt.s.wu x21, x21 + la x1, _fcvtswu_jr22 + jalr x22, x1, 0 +_fcvtswu_jr22: fcvt.s.wu x22, x22 + la x1, _fcvtswu_jr23 + jalr x23, x1, 0 +_fcvtswu_jr23: fcvt.s.wu x23, x23 + la x1, _fcvtswu_jr24 + jalr x24, x1, 0 +_fcvtswu_jr24: fcvt.s.wu x24, x24 + la x1, _fcvtswu_jr25 + jalr x25, x1, 0 +_fcvtswu_jr25: fcvt.s.wu x25, x25 + la x1, _fcvtswu_jr26 + jalr x26, x1, 0 +_fcvtswu_jr26: fcvt.s.wu x26, x26 + la x1, _fcvtswu_jr27 + jalr x27, x1, 0 +_fcvtswu_jr27: fcvt.s.wu x27, x27 + la x1, _fcvtswu_jr28 + jalr x28, x1, 0 +_fcvtswu_jr28: fcvt.s.wu x28, x28 + la x1, _fcvtswu_jr29 + jalr x29, x1, 0 +_fcvtswu_jr29: fcvt.s.wu x29, x29 + la x1, _fcvtswu_jr30 + jalr x30, x1, 0 +_fcvtswu_jr30: fcvt.s.wu x30, x30 + la x1, _fcvtswu_jr31 + jalr x31, x1, 0 +_fcvtswu_jr31: fcvt.s.wu x31, x31 + + // 13 - jal -> fcvtws (rs1) + jal x0, _fcvtws_j0 +_fcvtws_j0: fcvt.w.s x0, x0 + jal x1, _fcvtws_j1 +_fcvtws_j1: fcvt.w.s x1, x1 + jal x2, _fcvtws_j2 +_fcvtws_j2: fcvt.w.s x2, x2 + jal x3, _fcvtws_j3 +_fcvtws_j3: fcvt.w.s x3, x3 + jal x4, _fcvtws_j4 +_fcvtws_j4: fcvt.w.s x4, x4 + jal x5, _fcvtws_j5 +_fcvtws_j5: fcvt.w.s x5, x5 + jal x6, _fcvtws_j6 +_fcvtws_j6: fcvt.w.s x6, x6 + jal x7, _fcvtws_j7 +_fcvtws_j7: fcvt.w.s x7, x7 + jal x8, _fcvtws_j8 +_fcvtws_j8: fcvt.w.s x8, x8 + jal x9, _fcvtws_j9 +_fcvtws_j9: fcvt.w.s x9, x9 + jal x10, _fcvtws_j10 +_fcvtws_j10: fcvt.w.s x10, x10 + jal x11, _fcvtws_j11 +_fcvtws_j11: fcvt.w.s x11, x11 + jal x12, _fcvtws_j12 +_fcvtws_j12: fcvt.w.s x12, x12 + jal x13, _fcvtws_j13 +_fcvtws_j13: fcvt.w.s x13, x13 + jal x14, _fcvtws_j14 +_fcvtws_j14: fcvt.w.s x14, x14 + jal x15, _fcvtws_j15 +_fcvtws_j15: fcvt.w.s x15, x15 + jal x16, _fcvtws_j16 +_fcvtws_j16: fcvt.w.s x16, x16 + jal x17, _fcvtws_j17 +_fcvtws_j17: fcvt.w.s x17, x17 + jal x18, _fcvtws_j18 +_fcvtws_j18: fcvt.w.s x18, x18 + jal x19, _fcvtws_j19 +_fcvtws_j19: fcvt.w.s x19, x19 + jal x20, _fcvtws_j20 +_fcvtws_j20: fcvt.w.s x20, x20 + jal x21, _fcvtws_j21 +_fcvtws_j21: fcvt.w.s x21, x21 + jal x22, _fcvtws_j22 +_fcvtws_j22: fcvt.w.s x22, x22 + jal x23, _fcvtws_j23 +_fcvtws_j23: fcvt.w.s x23, x23 + jal x24, _fcvtws_j24 +_fcvtws_j24: fcvt.w.s x24, x24 + jal x25, _fcvtws_j25 +_fcvtws_j25: fcvt.w.s x25, x25 + jal x26, _fcvtws_j26 +_fcvtws_j26: fcvt.w.s x26, x26 + jal x27, _fcvtws_j27 +_fcvtws_j27: fcvt.w.s x27, x27 + jal x28, _fcvtws_j28 +_fcvtws_j28: fcvt.w.s x28, x28 + jal x29, _fcvtws_j29 +_fcvtws_j29: fcvt.w.s x29, x29 + jal x30, _fcvtws_j30 +_fcvtws_j30: fcvt.w.s x30, x30 + jal x31, _fcvtws_j31 +_fcvtws_j31: fcvt.w.s x31, x31 + + // 14 - jalr -> fcvtws (rs1) + la x1, _fcvtws_jr0 + jalr x0, x1, 0 +_fcvtws_jr0: fcvt.w.s x0, x0 + la x1, _fcvtws_jr1 + jalr x1, x1, 0 +_fcvtws_jr1: fcvt.w.s x1, x1 + la x1, _fcvtws_jr2 + jalr x2, x1, 0 +_fcvtws_jr2: fcvt.w.s x2, x2 + la x1, _fcvtws_jr3 + jalr x3, x1, 0 +_fcvtws_jr3: fcvt.w.s x3, x3 + la x1, _fcvtws_jr4 + jalr x4, x1, 0 +_fcvtws_jr4: fcvt.w.s x4, x4 + la x1, _fcvtws_jr5 + jalr x5, x1, 0 +_fcvtws_jr5: fcvt.w.s x5, x5 + la x1, _fcvtws_jr6 + jalr x6, x1, 0 +_fcvtws_jr6: fcvt.w.s x6, x6 + la x1, _fcvtws_jr7 + jalr x7, x1, 0 +_fcvtws_jr7: fcvt.w.s x7, x7 + la x1, _fcvtws_jr8 + jalr x8, x1, 0 +_fcvtws_jr8: fcvt.w.s x8, x8 + la x1, _fcvtws_jr9 + jalr x9, x1, 0 +_fcvtws_jr9: fcvt.w.s x9, x9 + la x1, _fcvtws_jr10 + jalr x10, x1, 0 +_fcvtws_jr10: fcvt.w.s x10, x10 + la x1, _fcvtws_jr11 + jalr x11, x1, 0 +_fcvtws_jr11: fcvt.w.s x11, x11 + la x1, _fcvtws_jr12 + jalr x12, x1, 0 +_fcvtws_jr12: fcvt.w.s x12, x12 + la x1, _fcvtws_jr13 + jalr x13, x1, 0 +_fcvtws_jr13: fcvt.w.s x13, x13 + la x1, _fcvtws_jr14 + jalr x14, x1, 0 +_fcvtws_jr14: fcvt.w.s x14, x14 + la x1, _fcvtws_jr15 + jalr x15, x1, 0 +_fcvtws_jr15: fcvt.w.s x15, x15 + la x1, _fcvtws_jr16 + jalr x16, x1, 0 +_fcvtws_jr16: fcvt.w.s x16, x16 + la x1, _fcvtws_jr17 + jalr x17, x1, 0 +_fcvtws_jr17: fcvt.w.s x17, x17 + la x1, _fcvtws_jr18 + jalr x18, x1, 0 +_fcvtws_jr18: fcvt.w.s x18, x18 + la x1, _fcvtws_jr19 + jalr x19, x1, 0 +_fcvtws_jr19: fcvt.w.s x19, x19 + la x1, _fcvtws_jr20 + jalr x20, x1, 0 +_fcvtws_jr20: fcvt.w.s x20, x20 + la x1, _fcvtws_jr21 + jalr x21, x1, 0 +_fcvtws_jr21: fcvt.w.s x21, x21 + la x1, _fcvtws_jr22 + jalr x22, x1, 0 +_fcvtws_jr22: fcvt.w.s x22, x22 + la x1, _fcvtws_jr23 + jalr x23, x1, 0 +_fcvtws_jr23: fcvt.w.s x23, x23 + la x1, _fcvtws_jr24 + jalr x24, x1, 0 +_fcvtws_jr24: fcvt.w.s x24, x24 + la x1, _fcvtws_jr25 + jalr x25, x1, 0 +_fcvtws_jr25: fcvt.w.s x25, x25 + la x1, _fcvtws_jr26 + jalr x26, x1, 0 +_fcvtws_jr26: fcvt.w.s x26, x26 + la x1, _fcvtws_jr27 + jalr x27, x1, 0 +_fcvtws_jr27: fcvt.w.s x27, x27 + la x1, _fcvtws_jr28 + jalr x28, x1, 0 +_fcvtws_jr28: fcvt.w.s x28, x28 + la x1, _fcvtws_jr29 + jalr x29, x1, 0 +_fcvtws_jr29: fcvt.w.s x29, x29 + la x1, _fcvtws_jr30 + jalr x30, x1, 0 +_fcvtws_jr30: fcvt.w.s x30, x30 + la x1, _fcvtws_jr31 + jalr x31, x1, 0 +_fcvtws_jr31: fcvt.w.s x31, x31 + + // 15 - jal -> fcvtwus (rs1) + jal x0, _fcvtwus_j0 +_fcvtwus_j0: fcvt.wu.s x0, x0 + jal x1, _fcvtwus_j1 +_fcvtwus_j1: fcvt.wu.s x1, x1 + jal x2, _fcvtwus_j2 +_fcvtwus_j2: fcvt.wu.s x2, x2 + jal x3, _fcvtwus_j3 +_fcvtwus_j3: fcvt.wu.s x3, x3 + jal x4, _fcvtwus_j4 +_fcvtwus_j4: fcvt.wu.s x4, x4 + jal x5, _fcvtwus_j5 +_fcvtwus_j5: fcvt.wu.s x5, x5 + jal x6, _fcvtwus_j6 +_fcvtwus_j6: fcvt.wu.s x6, x6 + jal x7, _fcvtwus_j7 +_fcvtwus_j7: fcvt.wu.s x7, x7 + jal x8, _fcvtwus_j8 +_fcvtwus_j8: fcvt.wu.s x8, x8 + jal x9, _fcvtwus_j9 +_fcvtwus_j9: fcvt.wu.s x9, x9 + jal x10, _fcvtwus_j10 +_fcvtwus_j10: fcvt.wu.s x10, x10 + jal x11, _fcvtwus_j11 +_fcvtwus_j11: fcvt.wu.s x11, x11 + jal x12, _fcvtwus_j12 +_fcvtwus_j12: fcvt.wu.s x12, x12 + jal x13, _fcvtwus_j13 +_fcvtwus_j13: fcvt.wu.s x13, x13 + jal x14, _fcvtwus_j14 +_fcvtwus_j14: fcvt.wu.s x14, x14 + jal x15, _fcvtwus_j15 +_fcvtwus_j15: fcvt.wu.s x15, x15 + jal x16, _fcvtwus_j16 +_fcvtwus_j16: fcvt.wu.s x16, x16 + jal x17, _fcvtwus_j17 +_fcvtwus_j17: fcvt.wu.s x17, x17 + jal x18, _fcvtwus_j18 +_fcvtwus_j18: fcvt.wu.s x18, x18 + jal x19, _fcvtwus_j19 +_fcvtwus_j19: fcvt.wu.s x19, x19 + jal x20, _fcvtwus_j20 +_fcvtwus_j20: fcvt.wu.s x20, x20 + jal x21, _fcvtwus_j21 +_fcvtwus_j21: fcvt.wu.s x21, x21 + jal x22, _fcvtwus_j22 +_fcvtwus_j22: fcvt.wu.s x22, x22 + jal x23, _fcvtwus_j23 +_fcvtwus_j23: fcvt.wu.s x23, x23 + jal x24, _fcvtwus_j24 +_fcvtwus_j24: fcvt.wu.s x24, x24 + jal x25, _fcvtwus_j25 +_fcvtwus_j25: fcvt.wu.s x25, x25 + jal x26, _fcvtwus_j26 +_fcvtwus_j26: fcvt.wu.s x26, x26 + jal x27, _fcvtwus_j27 +_fcvtwus_j27: fcvt.wu.s x27, x27 + jal x28, _fcvtwus_j28 +_fcvtwus_j28: fcvt.wu.s x28, x28 + jal x29, _fcvtwus_j29 +_fcvtwus_j29: fcvt.wu.s x29, x29 + jal x30, _fcvtwus_j30 +_fcvtwus_j30: fcvt.wu.s x30, x30 + jal x31, _fcvtwus_j31 +_fcvtwus_j31: fcvt.wu.s x31, x31 + + // 16 - jalr -> fcvtwus (rs1) + la x1, _fcvtwus_jr0 + jalr x0, x1, 0 +_fcvtwus_jr0: fcvt.wu.s x0, x0 + la x1, _fcvtwus_jr1 + jalr x1, x1, 0 +_fcvtwus_jr1: fcvt.wu.s x1, x1 + la x1, _fcvtwus_jr2 + jalr x2, x1, 0 +_fcvtwus_jr2: fcvt.wu.s x2, x2 + la x1, _fcvtwus_jr3 + jalr x3, x1, 0 +_fcvtwus_jr3: fcvt.wu.s x3, x3 + la x1, _fcvtwus_jr4 + jalr x4, x1, 0 +_fcvtwus_jr4: fcvt.wu.s x4, x4 + la x1, _fcvtwus_jr5 + jalr x5, x1, 0 +_fcvtwus_jr5: fcvt.wu.s x5, x5 + la x1, _fcvtwus_jr6 + jalr x6, x1, 0 +_fcvtwus_jr6: fcvt.wu.s x6, x6 + la x1, _fcvtwus_jr7 + jalr x7, x1, 0 +_fcvtwus_jr7: fcvt.wu.s x7, x7 + la x1, _fcvtwus_jr8 + jalr x8, x1, 0 +_fcvtwus_jr8: fcvt.wu.s x8, x8 + la x1, _fcvtwus_jr9 + jalr x9, x1, 0 +_fcvtwus_jr9: fcvt.wu.s x9, x9 + la x1, _fcvtwus_jr10 + jalr x10, x1, 0 +_fcvtwus_jr10: fcvt.wu.s x10, x10 + la x1, _fcvtwus_jr11 + jalr x11, x1, 0 +_fcvtwus_jr11: fcvt.wu.s x11, x11 + la x1, _fcvtwus_jr12 + jalr x12, x1, 0 +_fcvtwus_jr12: fcvt.wu.s x12, x12 + la x1, _fcvtwus_jr13 + jalr x13, x1, 0 +_fcvtwus_jr13: fcvt.wu.s x13, x13 + la x1, _fcvtwus_jr14 + jalr x14, x1, 0 +_fcvtwus_jr14: fcvt.wu.s x14, x14 + la x1, _fcvtwus_jr15 + jalr x15, x1, 0 +_fcvtwus_jr15: fcvt.wu.s x15, x15 + la x1, _fcvtwus_jr16 + jalr x16, x1, 0 +_fcvtwus_jr16: fcvt.wu.s x16, x16 + la x1, _fcvtwus_jr17 + jalr x17, x1, 0 +_fcvtwus_jr17: fcvt.wu.s x17, x17 + la x1, _fcvtwus_jr18 + jalr x18, x1, 0 +_fcvtwus_jr18: fcvt.wu.s x18, x18 + la x1, _fcvtwus_jr19 + jalr x19, x1, 0 +_fcvtwus_jr19: fcvt.wu.s x19, x19 + la x1, _fcvtwus_jr20 + jalr x20, x1, 0 +_fcvtwus_jr20: fcvt.wu.s x20, x20 + la x1, _fcvtwus_jr21 + jalr x21, x1, 0 +_fcvtwus_jr21: fcvt.wu.s x21, x21 + la x1, _fcvtwus_jr22 + jalr x22, x1, 0 +_fcvtwus_jr22: fcvt.wu.s x22, x22 + la x1, _fcvtwus_jr23 + jalr x23, x1, 0 +_fcvtwus_jr23: fcvt.wu.s x23, x23 + la x1, _fcvtwus_jr24 + jalr x24, x1, 0 +_fcvtwus_jr24: fcvt.wu.s x24, x24 + la x1, _fcvtwus_jr25 + jalr x25, x1, 0 +_fcvtwus_jr25: fcvt.wu.s x25, x25 + la x1, _fcvtwus_jr26 + jalr x26, x1, 0 +_fcvtwus_jr26: fcvt.wu.s x26, x26 + la x1, _fcvtwus_jr27 + jalr x27, x1, 0 +_fcvtwus_jr27: fcvt.wu.s x27, x27 + la x1, _fcvtwus_jr28 + jalr x28, x1, 0 +_fcvtwus_jr28: fcvt.wu.s x28, x28 + la x1, _fcvtwus_jr29 + jalr x29, x1, 0 +_fcvtwus_jr29: fcvt.wu.s x29, x29 + la x1, _fcvtwus_jr30 + jalr x30, x1, 0 +_fcvtwus_jr30: fcvt.wu.s x30, x30 + la x1, _fcvtwus_jr31 + jalr x31, x1, 0 +_fcvtwus_jr31: fcvt.wu.s x31, x31 + + // 17 - jal -> fdiv (rs1, rs2) + jal x0, _fdiv_j0 +_fdiv_j0: fdiv.s x0, x0, x0 + jal x1, _fdiv_j1 +_fdiv_j1: fdiv.s x1, x1, x1 + jal x2, _fdiv_j2 +_fdiv_j2: fdiv.s x2, x2, x2 + jal x3, _fdiv_j3 +_fdiv_j3: fdiv.s x3, x3, x3 + jal x4, _fdiv_j4 +_fdiv_j4: fdiv.s x4, x4, x4 + jal x5, _fdiv_j5 +_fdiv_j5: fdiv.s x5, x5, x5 + jal x6, _fdiv_j6 +_fdiv_j6: fdiv.s x6, x6, x6 + jal x7, _fdiv_j7 +_fdiv_j7: fdiv.s x7, x7, x7 + jal x8, _fdiv_j8 +_fdiv_j8: fdiv.s x8, x8, x8 + jal x9, _fdiv_j9 +_fdiv_j9: fdiv.s x9, x9, x9 + jal x10, _fdiv_j10 +_fdiv_j10: fdiv.s x10, x10, x10 + jal x11, _fdiv_j11 +_fdiv_j11: fdiv.s x11, x11, x11 + jal x12, _fdiv_j12 +_fdiv_j12: fdiv.s x12, x12, x12 + jal x13, _fdiv_j13 +_fdiv_j13: fdiv.s x13, x13, x13 + jal x14, _fdiv_j14 +_fdiv_j14: fdiv.s x14, x14, x14 + jal x15, _fdiv_j15 +_fdiv_j15: fdiv.s x15, x15, x15 + jal x16, _fdiv_j16 +_fdiv_j16: fdiv.s x16, x16, x16 + jal x17, _fdiv_j17 +_fdiv_j17: fdiv.s x17, x17, x17 + jal x18, _fdiv_j18 +_fdiv_j18: fdiv.s x18, x18, x18 + jal x19, _fdiv_j19 +_fdiv_j19: fdiv.s x19, x19, x19 + jal x20, _fdiv_j20 +_fdiv_j20: fdiv.s x20, x20, x20 + jal x21, _fdiv_j21 +_fdiv_j21: fdiv.s x21, x21, x21 + jal x22, _fdiv_j22 +_fdiv_j22: fdiv.s x22, x22, x22 + jal x23, _fdiv_j23 +_fdiv_j23: fdiv.s x23, x23, x23 + jal x24, _fdiv_j24 +_fdiv_j24: fdiv.s x24, x24, x24 + jal x25, _fdiv_j25 +_fdiv_j25: fdiv.s x25, x25, x25 + jal x26, _fdiv_j26 +_fdiv_j26: fdiv.s x26, x26, x26 + jal x27, _fdiv_j27 +_fdiv_j27: fdiv.s x27, x27, x27 + jal x28, _fdiv_j28 +_fdiv_j28: fdiv.s x28, x28, x28 + jal x29, _fdiv_j29 +_fdiv_j29: fdiv.s x29, x29, x29 + jal x30, _fdiv_j30 +_fdiv_j30: fdiv.s x30, x30, x30 + jal x31, _fdiv_j31 +_fdiv_j31: fdiv.s x31, x31, x31 + + // 18 - jalr -> fdiv (rs1, rs2) + la x1, _fdiv_jr0 + jalr x0, x1, 0 +_fdiv_jr0: fdiv.s x0, x0, x0 + la x1, _fdiv_jr1 + jalr x1, x1, 0 +_fdiv_jr1: fdiv.s x1, x1, x1 + la x1, _fdiv_jr2 + jalr x2, x1, 0 +_fdiv_jr2: fdiv.s x2, x2, x2 + la x1, _fdiv_jr3 + jalr x3, x1, 0 +_fdiv_jr3: fdiv.s x3, x3, x3 + la x1, _fdiv_jr4 + jalr x4, x1, 0 +_fdiv_jr4: fdiv.s x4, x4, x4 + la x1, _fdiv_jr5 + jalr x5, x1, 0 +_fdiv_jr5: fdiv.s x5, x5, x5 + la x1, _fdiv_jr6 + jalr x6, x1, 0 +_fdiv_jr6: fdiv.s x6, x6, x6 + la x1, _fdiv_jr7 + jalr x7, x1, 0 +_fdiv_jr7: fdiv.s x7, x7, x7 + la x1, _fdiv_jr8 + jalr x8, x1, 0 +_fdiv_jr8: fdiv.s x8, x8, x8 + la x1, _fdiv_jr9 + jalr x9, x1, 0 +_fdiv_jr9: fdiv.s x9, x9, x9 + la x1, _fdiv_jr10 + jalr x10, x1, 0 +_fdiv_jr10: fdiv.s x10, x10, x10 + la x1, _fdiv_jr11 + jalr x11, x1, 0 +_fdiv_jr11: fdiv.s x11, x11, x11 + la x1, _fdiv_jr12 + jalr x12, x1, 0 +_fdiv_jr12: fdiv.s x12, x12, x12 + la x1, _fdiv_jr13 + jalr x13, x1, 0 +_fdiv_jr13: fdiv.s x13, x13, x13 + la x1, _fdiv_jr14 + jalr x14, x1, 0 +_fdiv_jr14: fdiv.s x14, x14, x14 + la x1, _fdiv_jr15 + jalr x15, x1, 0 +_fdiv_jr15: fdiv.s x15, x15, x15 + la x1, _fdiv_jr16 + jalr x16, x1, 0 +_fdiv_jr16: fdiv.s x16, x16, x16 + la x1, _fdiv_jr17 + jalr x17, x1, 0 +_fdiv_jr17: fdiv.s x17, x17, x17 + la x1, _fdiv_jr18 + jalr x18, x1, 0 +_fdiv_jr18: fdiv.s x18, x18, x18 + la x1, _fdiv_jr19 + jalr x19, x1, 0 +_fdiv_jr19: fdiv.s x19, x19, x19 + la x1, _fdiv_jr20 + jalr x20, x1, 0 +_fdiv_jr20: fdiv.s x20, x20, x20 + la x1, _fdiv_jr21 + jalr x21, x1, 0 +_fdiv_jr21: fdiv.s x21, x21, x21 + la x1, _fdiv_jr22 + jalr x22, x1, 0 +_fdiv_jr22: fdiv.s x22, x22, x22 + la x1, _fdiv_jr23 + jalr x23, x1, 0 +_fdiv_jr23: fdiv.s x23, x23, x23 + la x1, _fdiv_jr24 + jalr x24, x1, 0 +_fdiv_jr24: fdiv.s x24, x24, x24 + la x1, _fdiv_jr25 + jalr x25, x1, 0 +_fdiv_jr25: fdiv.s x25, x25, x25 + la x1, _fdiv_jr26 + jalr x26, x1, 0 +_fdiv_jr26: fdiv.s x26, x26, x26 + la x1, _fdiv_jr27 + jalr x27, x1, 0 +_fdiv_jr27: fdiv.s x27, x27, x27 + la x1, _fdiv_jr28 + jalr x28, x1, 0 +_fdiv_jr28: fdiv.s x28, x28, x28 + la x1, _fdiv_jr29 + jalr x29, x1, 0 +_fdiv_jr29: fdiv.s x29, x29, x29 + la x1, _fdiv_jr30 + jalr x30, x1, 0 +_fdiv_jr30: fdiv.s x30, x30, x30 + la x1, _fdiv_jr31 + jalr x31, x1, 0 +_fdiv_jr31: fdiv.s x31, x31, x31 + + // 19 - jal -> feq (rs1, rs2) + jal x0, _feq_j0 +_feq_j0: feq.s x0, x0, x0 + jal x1, _feq_j1 +_feq_j1: feq.s x1, x1, x1 + jal x2, _feq_j2 +_feq_j2: feq.s x2, x2, x2 + jal x3, _feq_j3 +_feq_j3: feq.s x3, x3, x3 + jal x4, _feq_j4 +_feq_j4: feq.s x4, x4, x4 + jal x5, _feq_j5 +_feq_j5: feq.s x5, x5, x5 + jal x6, _feq_j6 +_feq_j6: feq.s x6, x6, x6 + jal x7, _feq_j7 +_feq_j7: feq.s x7, x7, x7 + jal x8, _feq_j8 +_feq_j8: feq.s x8, x8, x8 + jal x9, _feq_j9 +_feq_j9: feq.s x9, x9, x9 + jal x10, _feq_j10 +_feq_j10: feq.s x10, x10, x10 + jal x11, _feq_j11 +_feq_j11: feq.s x11, x11, x11 + jal x12, _feq_j12 +_feq_j12: feq.s x12, x12, x12 + jal x13, _feq_j13 +_feq_j13: feq.s x13, x13, x13 + jal x14, _feq_j14 +_feq_j14: feq.s x14, x14, x14 + jal x15, _feq_j15 +_feq_j15: feq.s x15, x15, x15 + jal x16, _feq_j16 +_feq_j16: feq.s x16, x16, x16 + jal x17, _feq_j17 +_feq_j17: feq.s x17, x17, x17 + jal x18, _feq_j18 +_feq_j18: feq.s x18, x18, x18 + jal x19, _feq_j19 +_feq_j19: feq.s x19, x19, x19 + jal x20, _feq_j20 +_feq_j20: feq.s x20, x20, x20 + jal x21, _feq_j21 +_feq_j21: feq.s x21, x21, x21 + jal x22, _feq_j22 +_feq_j22: feq.s x22, x22, x22 + jal x23, _feq_j23 +_feq_j23: feq.s x23, x23, x23 + jal x24, _feq_j24 +_feq_j24: feq.s x24, x24, x24 + jal x25, _feq_j25 +_feq_j25: feq.s x25, x25, x25 + jal x26, _feq_j26 +_feq_j26: feq.s x26, x26, x26 + jal x27, _feq_j27 +_feq_j27: feq.s x27, x27, x27 + jal x28, _feq_j28 +_feq_j28: feq.s x28, x28, x28 + jal x29, _feq_j29 +_feq_j29: feq.s x29, x29, x29 + jal x30, _feq_j30 +_feq_j30: feq.s x30, x30, x30 + jal x31, _feq_j31 +_feq_j31: feq.s x31, x31, x31 + + // 20 - jalr -> feq (rs1, rs2) + la x1, _feq_jr0 + jalr x0, x1, 0 +_feq_jr0: feq.s x0, x0, x0 + la x1, _feq_jr1 + jalr x1, x1, 0 +_feq_jr1: feq.s x1, x1, x1 + la x1, _feq_jr2 + jalr x2, x1, 0 +_feq_jr2: feq.s x2, x2, x2 + la x1, _feq_jr3 + jalr x3, x1, 0 +_feq_jr3: feq.s x3, x3, x3 + la x1, _feq_jr4 + jalr x4, x1, 0 +_feq_jr4: feq.s x4, x4, x4 + la x1, _feq_jr5 + jalr x5, x1, 0 +_feq_jr5: feq.s x5, x5, x5 + la x1, _feq_jr6 + jalr x6, x1, 0 +_feq_jr6: feq.s x6, x6, x6 + la x1, _feq_jr7 + jalr x7, x1, 0 +_feq_jr7: feq.s x7, x7, x7 + la x1, _feq_jr8 + jalr x8, x1, 0 +_feq_jr8: feq.s x8, x8, x8 + la x1, _feq_jr9 + jalr x9, x1, 0 +_feq_jr9: feq.s x9, x9, x9 + la x1, _feq_jr10 + jalr x10, x1, 0 +_feq_jr10: feq.s x10, x10, x10 + la x1, _feq_jr11 + jalr x11, x1, 0 +_feq_jr11: feq.s x11, x11, x11 + la x1, _feq_jr12 + jalr x12, x1, 0 +_feq_jr12: feq.s x12, x12, x12 + la x1, _feq_jr13 + jalr x13, x1, 0 +_feq_jr13: feq.s x13, x13, x13 + la x1, _feq_jr14 + jalr x14, x1, 0 +_feq_jr14: feq.s x14, x14, x14 + la x1, _feq_jr15 + jalr x15, x1, 0 +_feq_jr15: feq.s x15, x15, x15 + la x1, _feq_jr16 + jalr x16, x1, 0 +_feq_jr16: feq.s x16, x16, x16 + la x1, _feq_jr17 + jalr x17, x1, 0 +_feq_jr17: feq.s x17, x17, x17 + la x1, _feq_jr18 + jalr x18, x1, 0 +_feq_jr18: feq.s x18, x18, x18 + la x1, _feq_jr19 + jalr x19, x1, 0 +_feq_jr19: feq.s x19, x19, x19 + la x1, _feq_jr20 + jalr x20, x1, 0 +_feq_jr20: feq.s x20, x20, x20 + la x1, _feq_jr21 + jalr x21, x1, 0 +_feq_jr21: feq.s x21, x21, x21 + la x1, _feq_jr22 + jalr x22, x1, 0 +_feq_jr22: feq.s x22, x22, x22 + la x1, _feq_jr23 + jalr x23, x1, 0 +_feq_jr23: feq.s x23, x23, x23 + la x1, _feq_jr24 + jalr x24, x1, 0 +_feq_jr24: feq.s x24, x24, x24 + la x1, _feq_jr25 + jalr x25, x1, 0 +_feq_jr25: feq.s x25, x25, x25 + la x1, _feq_jr26 + jalr x26, x1, 0 +_feq_jr26: feq.s x26, x26, x26 + la x1, _feq_jr27 + jalr x27, x1, 0 +_feq_jr27: feq.s x27, x27, x27 + la x1, _feq_jr28 + jalr x28, x1, 0 +_feq_jr28: feq.s x28, x28, x28 + la x1, _feq_jr29 + jalr x29, x1, 0 +_feq_jr29: feq.s x29, x29, x29 + la x1, _feq_jr30 + jalr x30, x1, 0 +_feq_jr30: feq.s x30, x30, x30 + la x1, _feq_jr31 + jalr x31, x1, 0 +_feq_jr31: feq.s x31, x31, x31 + + // 21 - jal -> fle (rs1, rs2) + jal x0, _fle_j0 +_fle_j0: fle.s x0, x0, x0 + jal x1, _fle_j1 +_fle_j1: fle.s x1, x1, x1 + jal x2, _fle_j2 +_fle_j2: fle.s x2, x2, x2 + jal x3, _fle_j3 +_fle_j3: fle.s x3, x3, x3 + jal x4, _fle_j4 +_fle_j4: fle.s x4, x4, x4 + jal x5, _fle_j5 +_fle_j5: fle.s x5, x5, x5 + jal x6, _fle_j6 +_fle_j6: fle.s x6, x6, x6 + jal x7, _fle_j7 +_fle_j7: fle.s x7, x7, x7 + jal x8, _fle_j8 +_fle_j8: fle.s x8, x8, x8 + jal x9, _fle_j9 +_fle_j9: fle.s x9, x9, x9 + jal x10, _fle_j10 +_fle_j10: fle.s x10, x10, x10 + jal x11, _fle_j11 +_fle_j11: fle.s x11, x11, x11 + jal x12, _fle_j12 +_fle_j12: fle.s x12, x12, x12 + jal x13, _fle_j13 +_fle_j13: fle.s x13, x13, x13 + jal x14, _fle_j14 +_fle_j14: fle.s x14, x14, x14 + jal x15, _fle_j15 +_fle_j15: fle.s x15, x15, x15 + jal x16, _fle_j16 +_fle_j16: fle.s x16, x16, x16 + jal x17, _fle_j17 +_fle_j17: fle.s x17, x17, x17 + jal x18, _fle_j18 +_fle_j18: fle.s x18, x18, x18 + jal x19, _fle_j19 +_fle_j19: fle.s x19, x19, x19 + jal x20, _fle_j20 +_fle_j20: fle.s x20, x20, x20 + jal x21, _fle_j21 +_fle_j21: fle.s x21, x21, x21 + jal x22, _fle_j22 +_fle_j22: fle.s x22, x22, x22 + jal x23, _fle_j23 +_fle_j23: fle.s x23, x23, x23 + jal x24, _fle_j24 +_fle_j24: fle.s x24, x24, x24 + jal x25, _fle_j25 +_fle_j25: fle.s x25, x25, x25 + jal x26, _fle_j26 +_fle_j26: fle.s x26, x26, x26 + jal x27, _fle_j27 +_fle_j27: fle.s x27, x27, x27 + jal x28, _fle_j28 +_fle_j28: fle.s x28, x28, x28 + jal x29, _fle_j29 +_fle_j29: fle.s x29, x29, x29 + jal x30, _fle_j30 +_fle_j30: fle.s x30, x30, x30 + jal x31, _fle_j31 +_fle_j31: fle.s x31, x31, x31 + + // 22 - jal -> fle (rs1, rs2) + la x1, _fle_jr0 + jalr x0, x1, 0 +_fle_jr0: fle.s x0, x0, x0 + la x1, _fle_jr1 + jalr x1, x1, 0 +_fle_jr1: fle.s x1, x1, x1 + la x1, _fle_jr2 + jalr x2, x1, 0 +_fle_jr2: fle.s x2, x2, x2 + la x1, _fle_jr3 + jalr x3, x1, 0 +_fle_jr3: fle.s x3, x3, x3 + la x1, _fle_jr4 + jalr x4, x1, 0 +_fle_jr4: fle.s x4, x4, x4 + la x1, _fle_jr5 + jalr x5, x1, 0 +_fle_jr5: fle.s x5, x5, x5 + la x1, _fle_jr6 + jalr x6, x1, 0 +_fle_jr6: fle.s x6, x6, x6 + la x1, _fle_jr7 + jalr x7, x1, 0 +_fle_jr7: fle.s x7, x7, x7 + la x1, _fle_jr8 + jalr x8, x1, 0 +_fle_jr8: fle.s x8, x8, x8 + la x1, _fle_jr9 + jalr x9, x1, 0 +_fle_jr9: fle.s x9, x9, x9 + la x1, _fle_jr10 + jalr x10, x1, 0 +_fle_jr10: fle.s x10, x10, x10 + la x1, _fle_jr11 + jalr x11, x1, 0 +_fle_jr11: fle.s x11, x11, x11 + la x1, _fle_jr12 + jalr x12, x1, 0 +_fle_jr12: fle.s x12, x12, x12 + la x1, _fle_jr13 + jalr x13, x1, 0 +_fle_jr13: fle.s x13, x13, x13 + la x1, _fle_jr14 + jalr x14, x1, 0 +_fle_jr14: fle.s x14, x14, x14 + la x1, _fle_jr15 + jalr x15, x1, 0 +_fle_jr15: fle.s x15, x15, x15 + la x1, _fle_jr16 + jalr x16, x1, 0 +_fle_jr16: fle.s x16, x16, x16 + la x1, _fle_jr17 + jalr x17, x1, 0 +_fle_jr17: fle.s x17, x17, x17 + la x1, _fle_jr18 + jalr x18, x1, 0 +_fle_jr18: fle.s x18, x18, x18 + la x1, _fle_jr19 + jalr x19, x1, 0 +_fle_jr19: fle.s x19, x19, x19 + la x1, _fle_jr20 + jalr x20, x1, 0 +_fle_jr20: fle.s x20, x20, x20 + la x1, _fle_jr21 + jalr x21, x1, 0 +_fle_jr21: fle.s x21, x21, x21 + la x1, _fle_jr22 + jalr x22, x1, 0 +_fle_jr22: fle.s x22, x22, x22 + la x1, _fle_jr23 + jalr x23, x1, 0 +_fle_jr23: fle.s x23, x23, x23 + la x1, _fle_jr24 + jalr x24, x1, 0 +_fle_jr24: fle.s x24, x24, x24 + la x1, _fle_jr25 + jalr x25, x1, 0 +_fle_jr25: fle.s x25, x25, x25 + la x1, _fle_jr26 + jalr x26, x1, 0 +_fle_jr26: fle.s x26, x26, x26 + la x1, _fle_jr27 + jalr x27, x1, 0 +_fle_jr27: fle.s x27, x27, x27 + la x1, _fle_jr28 + jalr x28, x1, 0 +_fle_jr28: fle.s x28, x28, x28 + la x1, _fle_jr29 + jalr x29, x1, 0 +_fle_jr29: fle.s x29, x29, x29 + la x1, _fle_jr30 + jalr x30, x1, 0 +_fle_jr30: fle.s x30, x30, x30 + la x1, _fle_jr31 + jalr x31, x1, 0 +_fle_jr31: fle.s x31, x31, x31 + + // 23 - jal -> flt (rs1, rs2) + jal x0, _flt_j0 +_flt_j0: flt.s x0, x0, x0 + jal x1, _flt_j1 +_flt_j1: flt.s x1, x1, x1 + jal x2, _flt_j2 +_flt_j2: flt.s x2, x2, x2 + jal x3, _flt_j3 +_flt_j3: flt.s x3, x3, x3 + jal x4, _flt_j4 +_flt_j4: flt.s x4, x4, x4 + jal x5, _flt_j5 +_flt_j5: flt.s x5, x5, x5 + jal x6, _flt_j6 +_flt_j6: flt.s x6, x6, x6 + jal x7, _flt_j7 +_flt_j7: flt.s x7, x7, x7 + jal x8, _flt_j8 +_flt_j8: flt.s x8, x8, x8 + jal x9, _flt_j9 +_flt_j9: flt.s x9, x9, x9 + jal x10, _flt_j10 +_flt_j10: flt.s x10, x10, x10 + jal x11, _flt_j11 +_flt_j11: flt.s x11, x11, x11 + jal x12, _flt_j12 +_flt_j12: flt.s x12, x12, x12 + jal x13, _flt_j13 +_flt_j13: flt.s x13, x13, x13 + jal x14, _flt_j14 +_flt_j14: flt.s x14, x14, x14 + jal x15, _flt_j15 +_flt_j15: flt.s x15, x15, x15 + jal x16, _flt_j16 +_flt_j16: flt.s x16, x16, x16 + jal x17, _flt_j17 +_flt_j17: flt.s x17, x17, x17 + jal x18, _flt_j18 +_flt_j18: flt.s x18, x18, x18 + jal x19, _flt_j19 +_flt_j19: flt.s x19, x19, x19 + jal x20, _flt_j20 +_flt_j20: flt.s x20, x20, x20 + jal x21, _flt_j21 +_flt_j21: flt.s x21, x21, x21 + jal x22, _flt_j22 +_flt_j22: flt.s x22, x22, x22 + jal x23, _flt_j23 +_flt_j23: flt.s x23, x23, x23 + jal x24, _flt_j24 +_flt_j24: flt.s x24, x24, x24 + jal x25, _flt_j25 +_flt_j25: flt.s x25, x25, x25 + jal x26, _flt_j26 +_flt_j26: flt.s x26, x26, x26 + jal x27, _flt_j27 +_flt_j27: flt.s x27, x27, x27 + jal x28, _flt_j28 +_flt_j28: flt.s x28, x28, x28 + jal x29, _flt_j29 +_flt_j29: flt.s x29, x29, x29 + jal x30, _flt_j30 +_flt_j30: flt.s x30, x30, x30 + jal x31, _flt_j31 +_flt_j31: flt.s x31, x31, x31 + + // 24 - jalr -> flt (rs1, rs2) + la x1, _flt_jr0 + jalr x0, x1, 0 +_flt_jr0: flt.s x0, x0, x0 + la x1, _flt_jr1 + jalr x1, x1, 0 +_flt_jr1: flt.s x1, x1, x1 + la x1, _flt_jr2 + jalr x2, x1, 0 +_flt_jr2: flt.s x2, x2, x2 + la x1, _flt_jr3 + jalr x3, x1, 0 +_flt_jr3: flt.s x3, x3, x3 + la x1, _flt_jr4 + jalr x4, x1, 0 +_flt_jr4: flt.s x4, x4, x4 + la x1, _flt_jr5 + jalr x5, x1, 0 +_flt_jr5: flt.s x5, x5, x5 + la x1, _flt_jr6 + jalr x6, x1, 0 +_flt_jr6: flt.s x6, x6, x6 + la x1, _flt_jr7 + jalr x7, x1, 0 +_flt_jr7: flt.s x7, x7, x7 + la x1, _flt_jr8 + jalr x8, x1, 0 +_flt_jr8: flt.s x8, x8, x8 + la x1, _flt_jr9 + jalr x9, x1, 0 +_flt_jr9: flt.s x9, x9, x9 + la x1, _flt_jr10 + jalr x10, x1, 0 +_flt_jr10: flt.s x10, x10, x10 + la x1, _flt_jr11 + jalr x11, x1, 0 +_flt_jr11: flt.s x11, x11, x11 + la x1, _flt_jr12 + jalr x12, x1, 0 +_flt_jr12: flt.s x12, x12, x12 + la x1, _flt_jr13 + jalr x13, x1, 0 +_flt_jr13: flt.s x13, x13, x13 + la x1, _flt_jr14 + jalr x14, x1, 0 +_flt_jr14: flt.s x14, x14, x14 + la x1, _flt_jr15 + jalr x15, x1, 0 +_flt_jr15: flt.s x15, x15, x15 + la x1, _flt_jr16 + jalr x16, x1, 0 +_flt_jr16: flt.s x16, x16, x16 + la x1, _flt_jr17 + jalr x17, x1, 0 +_flt_jr17: flt.s x17, x17, x17 + la x1, _flt_jr18 + jalr x18, x1, 0 +_flt_jr18: flt.s x18, x18, x18 + la x1, _flt_jr19 + jalr x19, x1, 0 +_flt_jr19: flt.s x19, x19, x19 + la x1, _flt_jr20 + jalr x20, x1, 0 +_flt_jr20: flt.s x20, x20, x20 + la x1, _flt_jr21 + jalr x21, x1, 0 +_flt_jr21: flt.s x21, x21, x21 + la x1, _flt_jr22 + jalr x22, x1, 0 +_flt_jr22: flt.s x22, x22, x22 + la x1, _flt_jr23 + jalr x23, x1, 0 +_flt_jr23: flt.s x23, x23, x23 + la x1, _flt_jr24 + jalr x24, x1, 0 +_flt_jr24: flt.s x24, x24, x24 + la x1, _flt_jr25 + jalr x25, x1, 0 +_flt_jr25: flt.s x25, x25, x25 + la x1, _flt_jr26 + jalr x26, x1, 0 +_flt_jr26: flt.s x26, x26, x26 + la x1, _flt_jr27 + jalr x27, x1, 0 +_flt_jr27: flt.s x27, x27, x27 + la x1, _flt_jr28 + jalr x28, x1, 0 +_flt_jr28: flt.s x28, x28, x28 + la x1, _flt_jr29 + jalr x29, x1, 0 +_flt_jr29: flt.s x29, x29, x29 + la x1, _flt_jr30 + jalr x30, x1, 0 +_flt_jr30: flt.s x30, x30, x30 + la x1, _flt_jr31 + jalr x31, x1, 0 +_flt_jr31: flt.s x31, x31, x31 + + // 25 - jal -> fmadd (rs1, rs2, rs3) + jal x0, _fmadd_j0 +_fmadd_j0: fmadd.s x0, x0, x0, x0 + jal x1, _fmadd_j1 +_fmadd_j1: fmadd.s x1, x1, x1, x1 + jal x2, _fmadd_j2 +_fmadd_j2: fmadd.s x2, x2, x2, x2 + jal x3, _fmadd_j3 +_fmadd_j3: fmadd.s x3, x3, x3, x3 + jal x4, _fmadd_j4 +_fmadd_j4: fmadd.s x4, x4, x4, x4 + jal x5, _fmadd_j5 +_fmadd_j5: fmadd.s x5, x5, x5, x5 + jal x6, _fmadd_j6 +_fmadd_j6: fmadd.s x6, x6, x6, x6 + jal x7, _fmadd_j7 +_fmadd_j7: fmadd.s x7, x7, x7, x7 + jal x8, _fmadd_j8 +_fmadd_j8: fmadd.s x8, x8, x8, x8 + jal x9, _fmadd_j9 +_fmadd_j9: fmadd.s x9, x9, x9, x9 + jal x10, _fmadd_j10 +_fmadd_j10: fmadd.s x10, x10, x10, x10 + jal x11, _fmadd_j11 +_fmadd_j11: fmadd.s x11, x11, x11, x11 + jal x12, _fmadd_j12 +_fmadd_j12: fmadd.s x12, x12, x12, x12 + jal x13, _fmadd_j13 +_fmadd_j13: fmadd.s x13, x13, x13, x13 + jal x14, _fmadd_j14 +_fmadd_j14: fmadd.s x14, x14, x14, x14 + jal x15, _fmadd_j15 +_fmadd_j15: fmadd.s x15, x15, x15, x15 + jal x16, _fmadd_j16 +_fmadd_j16: fmadd.s x16, x16, x16, x16 + jal x17, _fmadd_j17 +_fmadd_j17: fmadd.s x17, x17, x17, x17 + jal x18, _fmadd_j18 +_fmadd_j18: fmadd.s x18, x18, x18, x18 + jal x19, _fmadd_j19 +_fmadd_j19: fmadd.s x19, x19, x19, x19 + jal x20, _fmadd_j20 +_fmadd_j20: fmadd.s x20, x20, x20, x20 + jal x21, _fmadd_j21 +_fmadd_j21: fmadd.s x21, x21, x21, x21 + jal x22, _fmadd_j22 +_fmadd_j22: fmadd.s x22, x22, x22, x22 + jal x23, _fmadd_j23 +_fmadd_j23: fmadd.s x23, x23, x23, x23 + jal x24, _fmadd_j24 +_fmadd_j24: fmadd.s x24, x24, x24, x24 + jal x25, _fmadd_j25 +_fmadd_j25: fmadd.s x25, x25, x25, x25 + jal x26, _fmadd_j26 +_fmadd_j26: fmadd.s x26, x26, x26, x26 + jal x27, _fmadd_j27 +_fmadd_j27: fmadd.s x27, x27, x27, x27 + jal x28, _fmadd_j28 +_fmadd_j28: fmadd.s x28, x28, x28, x28 + jal x29, _fmadd_j29 +_fmadd_j29: fmadd.s x29, x29, x29, x29 + jal x30, _fmadd_j30 +_fmadd_j30: fmadd.s x30, x30, x30, x30 + jal x31, _fmadd_j31 +_fmadd_j31: fmadd.s x31, x31, x31, x31 + + // 26 - jalr -> fmadd (rs1, rs2, rs3) + la x1, _fmadd_jr0 + jalr x0, x1, 0 +_fmadd_jr0: fmadd.s x0, x0, x0, x0 + la x1, _fmadd_jr1 + jalr x1, x1, 0 +_fmadd_jr1: fmadd.s x1, x1, x1, x1 + la x1, _fmadd_jr2 + jalr x2, x1, 0 +_fmadd_jr2: fmadd.s x2, x2, x2, x2 + la x1, _fmadd_jr3 + jalr x3, x1, 0 +_fmadd_jr3: fmadd.s x3, x3, x3, x3 + la x1, _fmadd_jr4 + jalr x4, x1, 0 +_fmadd_jr4: fmadd.s x4, x4, x4, x4 + la x1, _fmadd_jr5 + jalr x5, x1, 0 +_fmadd_jr5: fmadd.s x5, x5, x5, x5 + la x1, _fmadd_jr6 + jalr x6, x1, 0 +_fmadd_jr6: fmadd.s x6, x6, x6, x6 + la x1, _fmadd_jr7 + jalr x7, x1, 0 +_fmadd_jr7: fmadd.s x7, x7, x7, x7 + la x1, _fmadd_jr8 + jalr x8, x1, 0 +_fmadd_jr8: fmadd.s x8, x8, x8, x8 + la x1, _fmadd_jr9 + jalr x9, x1, 0 +_fmadd_jr9: fmadd.s x9, x9, x9, x9 + la x1, _fmadd_jr10 + jalr x10, x1, 0 +_fmadd_jr10: fmadd.s x10, x10, x10, x10 + la x1, _fmadd_jr11 + jalr x11, x1, 0 +_fmadd_jr11: fmadd.s x11, x11, x11, x11 + la x1, _fmadd_jr12 + jalr x12, x1, 0 +_fmadd_jr12: fmadd.s x12, x12, x12, x12 + la x1, _fmadd_jr13 + jalr x13, x1, 0 +_fmadd_jr13: fmadd.s x13, x13, x13, x13 + la x1, _fmadd_jr14 + jalr x14, x1, 0 +_fmadd_jr14: fmadd.s x14, x14, x14, x14 + la x1, _fmadd_jr15 + jalr x15, x1, 0 +_fmadd_jr15: fmadd.s x15, x15, x15, x15 + la x1, _fmadd_jr16 + jalr x16, x1, 0 +_fmadd_jr16: fmadd.s x16, x16, x16, x16 + la x1, _fmadd_jr17 + jalr x17, x1, 0 +_fmadd_jr17: fmadd.s x17, x17, x17, x17 + la x1, _fmadd_jr18 + jalr x18, x1, 0 +_fmadd_jr18: fmadd.s x18, x18, x18, x18 + la x1, _fmadd_jr19 + jalr x19, x1, 0 +_fmadd_jr19: fmadd.s x19, x19, x19, x19 + la x1, _fmadd_jr20 + jalr x20, x1, 0 +_fmadd_jr20: fmadd.s x20, x20, x20, x20 + la x1, _fmadd_jr21 + jalr x21, x1, 0 +_fmadd_jr21: fmadd.s x21, x21, x21, x21 + la x1, _fmadd_jr22 + jalr x22, x1, 0 +_fmadd_jr22: fmadd.s x22, x22, x22, x22 + la x1, _fmadd_jr23 + jalr x23, x1, 0 +_fmadd_jr23: fmadd.s x23, x23, x23, x23 + la x1, _fmadd_jr24 + jalr x24, x1, 0 +_fmadd_jr24: fmadd.s x24, x24, x24, x24 + la x1, _fmadd_jr25 + jalr x25, x1, 0 +_fmadd_jr25: fmadd.s x25, x25, x25, x25 + la x1, _fmadd_jr26 + jalr x26, x1, 0 +_fmadd_jr26: fmadd.s x26, x26, x26, x26 + la x1, _fmadd_jr27 + jalr x27, x1, 0 +_fmadd_jr27: fmadd.s x27, x27, x27, x27 + la x1, _fmadd_jr28 + jalr x28, x1, 0 +_fmadd_jr28: fmadd.s x28, x28, x28, x28 + la x1, _fmadd_jr29 + jalr x29, x1, 0 +_fmadd_jr29: fmadd.s x29, x29, x29, x29 + la x1, _fmadd_jr30 + jalr x30, x1, 0 +_fmadd_jr30: fmadd.s x30, x30, x30, x30 + la x1, _fmadd_jr31 + jalr x31, x1, 0 +_fmadd_jr31: fmadd.s x31, x31, x31, x31 + + // 27 - jal -> fmax (rs1, rs2) + jal x0, _fmax_j0 +_fmax_j0: fmax.s x0, x0, x0 + jal x1, _fmax_j1 +_fmax_j1: fmax.s x1, x1, x1 + jal x2, _fmax_j2 +_fmax_j2: fmax.s x2, x2, x2 + jal x3, _fmax_j3 +_fmax_j3: fmax.s x3, x3, x3 + jal x4, _fmax_j4 +_fmax_j4: fmax.s x4, x4, x4 + jal x5, _fmax_j5 +_fmax_j5: fmax.s x5, x5, x5 + jal x6, _fmax_j6 +_fmax_j6: fmax.s x6, x6, x6 + jal x7, _fmax_j7 +_fmax_j7: fmax.s x7, x7, x7 + jal x8, _fmax_j8 +_fmax_j8: fmax.s x8, x8, x8 + jal x9, _fmax_j9 +_fmax_j9: fmax.s x9, x9, x9 + jal x10, _fmax_j10 +_fmax_j10: fmax.s x10, x10, x10 + jal x11, _fmax_j11 +_fmax_j11: fmax.s x11, x11, x11 + jal x12, _fmax_j12 +_fmax_j12: fmax.s x12, x12, x12 + jal x13, _fmax_j13 +_fmax_j13: fmax.s x13, x13, x13 + jal x14, _fmax_j14 +_fmax_j14: fmax.s x14, x14, x14 + jal x15, _fmax_j15 +_fmax_j15: fmax.s x15, x15, x15 + jal x16, _fmax_j16 +_fmax_j16: fmax.s x16, x16, x16 + jal x17, _fmax_j17 +_fmax_j17: fmax.s x17, x17, x17 + jal x18, _fmax_j18 +_fmax_j18: fmax.s x18, x18, x18 + jal x19, _fmax_j19 +_fmax_j19: fmax.s x19, x19, x19 + jal x20, _fmax_j20 +_fmax_j20: fmax.s x20, x20, x20 + jal x21, _fmax_j21 +_fmax_j21: fmax.s x21, x21, x21 + jal x22, _fmax_j22 +_fmax_j22: fmax.s x22, x22, x22 + jal x23, _fmax_j23 +_fmax_j23: fmax.s x23, x23, x23 + jal x24, _fmax_j24 +_fmax_j24: fmax.s x24, x24, x24 + jal x25, _fmax_j25 +_fmax_j25: fmax.s x25, x25, x25 + jal x26, _fmax_j26 +_fmax_j26: fmax.s x26, x26, x26 + jal x27, _fmax_j27 +_fmax_j27: fmax.s x27, x27, x27 + jal x28, _fmax_j28 +_fmax_j28: fmax.s x28, x28, x28 + jal x29, _fmax_j29 +_fmax_j29: fmax.s x29, x29, x29 + jal x30, _fmax_j30 +_fmax_j30: fmax.s x30, x30, x30 + jal x31, _fmax_j31 +_fmax_j31: fmax.s x31, x31, x31 + + // 28 - jalr -> fmax (rs1, rs2) + la x1, _fmax_jr0 + jalr x0, x1, 0 +_fmax_jr0: fmax.s x0, x0, x0 + la x1, _fmax_jr1 + jalr x1, x1, 0 +_fmax_jr1: fmax.s x1, x1, x1 + la x1, _fmax_jr2 + jalr x2, x1, 0 +_fmax_jr2: fmax.s x2, x2, x2 + la x1, _fmax_jr3 + jalr x3, x1, 0 +_fmax_jr3: fmax.s x3, x3, x3 + la x1, _fmax_jr4 + jalr x4, x1, 0 +_fmax_jr4: fmax.s x4, x4, x4 + la x1, _fmax_jr5 + jalr x5, x1, 0 +_fmax_jr5: fmax.s x5, x5, x5 + la x1, _fmax_jr6 + jalr x6, x1, 0 +_fmax_jr6: fmax.s x6, x6, x6 + la x1, _fmax_jr7 + jalr x7, x1, 0 +_fmax_jr7: fmax.s x7, x7, x7 + la x1, _fmax_jr8 + jalr x8, x1, 0 +_fmax_jr8: fmax.s x8, x8, x8 + la x1, _fmax_jr9 + jalr x9, x1, 0 +_fmax_jr9: fmax.s x9, x9, x9 + la x1, _fmax_jr10 + jalr x10, x1, 0 +_fmax_jr10: fmax.s x10, x10, x10 + la x1, _fmax_jr11 + jalr x11, x1, 0 +_fmax_jr11: fmax.s x11, x11, x11 + la x1, _fmax_jr12 + jalr x12, x1, 0 +_fmax_jr12: fmax.s x12, x12, x12 + la x1, _fmax_jr13 + jalr x13, x1, 0 +_fmax_jr13: fmax.s x13, x13, x13 + la x1, _fmax_jr14 + jalr x14, x1, 0 +_fmax_jr14: fmax.s x14, x14, x14 + la x1, _fmax_jr15 + jalr x15, x1, 0 +_fmax_jr15: fmax.s x15, x15, x15 + la x1, _fmax_jr16 + jalr x16, x1, 0 +_fmax_jr16: fmax.s x16, x16, x16 + la x1, _fmax_jr17 + jalr x17, x1, 0 +_fmax_jr17: fmax.s x17, x17, x17 + la x1, _fmax_jr18 + jalr x18, x1, 0 +_fmax_jr18: fmax.s x18, x18, x18 + la x1, _fmax_jr19 + jalr x19, x1, 0 +_fmax_jr19: fmax.s x19, x19, x19 + la x1, _fmax_jr20 + jalr x20, x1, 0 +_fmax_jr20: fmax.s x20, x20, x20 + la x1, _fmax_jr21 + jalr x21, x1, 0 +_fmax_jr21: fmax.s x21, x21, x21 + la x1, _fmax_jr22 + jalr x22, x1, 0 +_fmax_jr22: fmax.s x22, x22, x22 + la x1, _fmax_jr23 + jalr x23, x1, 0 +_fmax_jr23: fmax.s x23, x23, x23 + la x1, _fmax_jr24 + jalr x24, x1, 0 +_fmax_jr24: fmax.s x24, x24, x24 + la x1, _fmax_jr25 + jalr x25, x1, 0 +_fmax_jr25: fmax.s x25, x25, x25 + la x1, _fmax_jr26 + jalr x26, x1, 0 +_fmax_jr26: fmax.s x26, x26, x26 + la x1, _fmax_jr27 + jalr x27, x1, 0 +_fmax_jr27: fmax.s x27, x27, x27 + la x1, _fmax_jr28 + jalr x28, x1, 0 +_fmax_jr28: fmax.s x28, x28, x28 + la x1, _fmax_jr29 + jalr x29, x1, 0 +_fmax_jr29: fmax.s x29, x29, x29 + la x1, _fmax_jr30 + jalr x30, x1, 0 +_fmax_jr30: fmax.s x30, x30, x30 + la x1, _fmax_jr31 + jalr x31, x1, 0 +_fmax_jr31: fmax.s x31, x31, x31 + + // 29 - jal -> fmin (rs1, rs2) + jal x0, _fmin_j0 +_fmin_j0: fmin.s x0, x0, x0 + jal x1, _fmin_j1 +_fmin_j1: fmin.s x1, x1, x1 + jal x2, _fmin_j2 +_fmin_j2: fmin.s x2, x2, x2 + jal x3, _fmin_j3 +_fmin_j3: fmin.s x3, x3, x3 + jal x4, _fmin_j4 +_fmin_j4: fmin.s x4, x4, x4 + jal x5, _fmin_j5 +_fmin_j5: fmin.s x5, x5, x5 + jal x6, _fmin_j6 +_fmin_j6: fmin.s x6, x6, x6 + jal x7, _fmin_j7 +_fmin_j7: fmin.s x7, x7, x7 + jal x8, _fmin_j8 +_fmin_j8: fmin.s x8, x8, x8 + jal x9, _fmin_j9 +_fmin_j9: fmin.s x9, x9, x9 + jal x10, _fmin_j10 +_fmin_j10: fmin.s x10, x10, x10 + jal x11, _fmin_j11 +_fmin_j11: fmin.s x11, x11, x11 + jal x12, _fmin_j12 +_fmin_j12: fmin.s x12, x12, x12 + jal x13, _fmin_j13 +_fmin_j13: fmin.s x13, x13, x13 + jal x14, _fmin_j14 +_fmin_j14: fmin.s x14, x14, x14 + jal x15, _fmin_j15 +_fmin_j15: fmin.s x15, x15, x15 + jal x16, _fmin_j16 +_fmin_j16: fmin.s x16, x16, x16 + jal x17, _fmin_j17 +_fmin_j17: fmin.s x17, x17, x17 + jal x18, _fmin_j18 +_fmin_j18: fmin.s x18, x18, x18 + jal x19, _fmin_j19 +_fmin_j19: fmin.s x19, x19, x19 + jal x20, _fmin_j20 +_fmin_j20: fmin.s x20, x20, x20 + jal x21, _fmin_j21 +_fmin_j21: fmin.s x21, x21, x21 + jal x22, _fmin_j22 +_fmin_j22: fmin.s x22, x22, x22 + jal x23, _fmin_j23 +_fmin_j23: fmin.s x23, x23, x23 + jal x24, _fmin_j24 +_fmin_j24: fmin.s x24, x24, x24 + jal x25, _fmin_j25 +_fmin_j25: fmin.s x25, x25, x25 + jal x26, _fmin_j26 +_fmin_j26: fmin.s x26, x26, x26 + jal x27, _fmin_j27 +_fmin_j27: fmin.s x27, x27, x27 + jal x28, _fmin_j28 +_fmin_j28: fmin.s x28, x28, x28 + jal x29, _fmin_j29 +_fmin_j29: fmin.s x29, x29, x29 + jal x30, _fmin_j30 +_fmin_j30: fmin.s x30, x30, x30 + jal x31, _fmin_j31 +_fmin_j31: fmin.s x31, x31, x31 + + // 30 - jalr -> fmin (rs1, rs2) + la x1, _fmin_jr0 + jalr x0, x1, 0 +_fmin_jr0: fmin.s x0, x0, x0 + la x1, _fmin_jr1 + jalr x1, x1, 0 +_fmin_jr1: fmin.s x1, x1, x1 + la x1, _fmin_jr2 + jalr x2, x1, 0 +_fmin_jr2: fmin.s x2, x2, x2 + la x1, _fmin_jr3 + jalr x3, x1, 0 +_fmin_jr3: fmin.s x3, x3, x3 + la x1, _fmin_jr4 + jalr x4, x1, 0 +_fmin_jr4: fmin.s x4, x4, x4 + la x1, _fmin_jr5 + jalr x5, x1, 0 +_fmin_jr5: fmin.s x5, x5, x5 + la x1, _fmin_jr6 + jalr x6, x1, 0 +_fmin_jr6: fmin.s x6, x6, x6 + la x1, _fmin_jr7 + jalr x7, x1, 0 +_fmin_jr7: fmin.s x7, x7, x7 + la x1, _fmin_jr8 + jalr x8, x1, 0 +_fmin_jr8: fmin.s x8, x8, x8 + la x1, _fmin_jr9 + jalr x9, x1, 0 +_fmin_jr9: fmin.s x9, x9, x9 + la x1, _fmin_jr10 + jalr x10, x1, 0 +_fmin_jr10: fmin.s x10, x10, x10 + la x1, _fmin_jr11 + jalr x11, x1, 0 +_fmin_jr11: fmin.s x11, x11, x11 + la x1, _fmin_jr12 + jalr x12, x1, 0 +_fmin_jr12: fmin.s x12, x12, x12 + la x1, _fmin_jr13 + jalr x13, x1, 0 +_fmin_jr13: fmin.s x13, x13, x13 + la x1, _fmin_jr14 + jalr x14, x1, 0 +_fmin_jr14: fmin.s x14, x14, x14 + la x1, _fmin_jr15 + jalr x15, x1, 0 +_fmin_jr15: fmin.s x15, x15, x15 + la x1, _fmin_jr16 + jalr x16, x1, 0 +_fmin_jr16: fmin.s x16, x16, x16 + la x1, _fmin_jr17 + jalr x17, x1, 0 +_fmin_jr17: fmin.s x17, x17, x17 + la x1, _fmin_jr18 + jalr x18, x1, 0 +_fmin_jr18: fmin.s x18, x18, x18 + la x1, _fmin_jr19 + jalr x19, x1, 0 +_fmin_jr19: fmin.s x19, x19, x19 + la x1, _fmin_jr20 + jalr x20, x1, 0 +_fmin_jr20: fmin.s x20, x20, x20 + la x1, _fmin_jr21 + jalr x21, x1, 0 +_fmin_jr21: fmin.s x21, x21, x21 + la x1, _fmin_jr22 + jalr x22, x1, 0 +_fmin_jr22: fmin.s x22, x22, x22 + la x1, _fmin_jr23 + jalr x23, x1, 0 +_fmin_jr23: fmin.s x23, x23, x23 + la x1, _fmin_jr24 + jalr x24, x1, 0 +_fmin_jr24: fmin.s x24, x24, x24 + la x1, _fmin_jr25 + jalr x25, x1, 0 +_fmin_jr25: fmin.s x25, x25, x25 + la x1, _fmin_jr26 + jalr x26, x1, 0 +_fmin_jr26: fmin.s x26, x26, x26 + la x1, _fmin_jr27 + jalr x27, x1, 0 +_fmin_jr27: fmin.s x27, x27, x27 + la x1, _fmin_jr28 + jalr x28, x1, 0 +_fmin_jr28: fmin.s x28, x28, x28 + la x1, _fmin_jr29 + jalr x29, x1, 0 +_fmin_jr29: fmin.s x29, x29, x29 + la x1, _fmin_jr30 + jalr x30, x1, 0 +_fmin_jr30: fmin.s x30, x30, x30 + la x1, _fmin_jr31 + jalr x31, x1, 0 +_fmin_jr31: fmin.s x31, x31, x31 + + // 31 - jal -> fmsub (rs1, rs2, rs3) + jal x0, _fmsub_j0 +_fmsub_j0: fmsub.s x0, x0, x0, x0 + jal x1, _fmsub_j1 +_fmsub_j1: fmsub.s x1, x1, x1, x1 + jal x2, _fmsub_j2 +_fmsub_j2: fmsub.s x2, x2, x2, x2 + jal x3, _fmsub_j3 +_fmsub_j3: fmsub.s x3, x3, x3, x3 + jal x4, _fmsub_j4 +_fmsub_j4: fmsub.s x4, x4, x4, x4 + jal x5, _fmsub_j5 +_fmsub_j5: fmsub.s x5, x5, x5, x5 + jal x6, _fmsub_j6 +_fmsub_j6: fmsub.s x6, x6, x6, x6 + jal x7, _fmsub_j7 +_fmsub_j7: fmsub.s x7, x7, x7, x7 + jal x8, _fmsub_j8 +_fmsub_j8: fmsub.s x8, x8, x8, x8 + jal x9, _fmsub_j9 +_fmsub_j9: fmsub.s x9, x9, x9, x9 + jal x10, _fmsub_j10 +_fmsub_j10: fmsub.s x10, x10, x10, x10 + jal x11, _fmsub_j11 +_fmsub_j11: fmsub.s x11, x11, x11, x11 + jal x12, _fmsub_j12 +_fmsub_j12: fmsub.s x12, x12, x12, x12 + jal x13, _fmsub_j13 +_fmsub_j13: fmsub.s x13, x13, x13, x13 + jal x14, _fmsub_j14 +_fmsub_j14: fmsub.s x14, x14, x14, x14 + jal x15, _fmsub_j15 +_fmsub_j15: fmsub.s x15, x15, x15, x15 + jal x16, _fmsub_j16 +_fmsub_j16: fmsub.s x16, x16, x16, x16 + jal x17, _fmsub_j17 +_fmsub_j17: fmsub.s x17, x17, x17, x17 + jal x18, _fmsub_j18 +_fmsub_j18: fmsub.s x18, x18, x18, x18 + jal x19, _fmsub_j19 +_fmsub_j19: fmsub.s x19, x19, x19, x19 + jal x20, _fmsub_j20 +_fmsub_j20: fmsub.s x20, x20, x20, x20 + jal x21, _fmsub_j21 +_fmsub_j21: fmsub.s x21, x21, x21, x21 + jal x22, _fmsub_j22 +_fmsub_j22: fmsub.s x22, x22, x22, x22 + jal x23, _fmsub_j23 +_fmsub_j23: fmsub.s x23, x23, x23, x23 + jal x24, _fmsub_j24 +_fmsub_j24: fmsub.s x24, x24, x24, x24 + jal x25, _fmsub_j25 +_fmsub_j25: fmsub.s x25, x25, x25, x25 + jal x26, _fmsub_j26 +_fmsub_j26: fmsub.s x26, x26, x26, x26 + jal x27, _fmsub_j27 +_fmsub_j27: fmsub.s x27, x27, x27, x27 + jal x28, _fmsub_j28 +_fmsub_j28: fmsub.s x28, x28, x28, x28 + jal x29, _fmsub_j29 +_fmsub_j29: fmsub.s x29, x29, x29, x29 + jal x30, _fmsub_j30 +_fmsub_j30: fmsub.s x30, x30, x30, x30 + jal x31, _fmsub_j31 +_fmsub_j31: fmsub.s x31, x31, x31, x31 + + // 32 - jalr -> fmsub (rs1, rs2, rs3) + la x1, _fmsub_jr0 + jalr x0, x1, 0 +_fmsub_jr0: fmsub.s x0, x0, x0, x0 + la x1, _fmsub_jr1 + jalr x1, x1, 0 +_fmsub_jr1: fmsub.s x1, x1, x1, x1 + la x1, _fmsub_jr2 + jalr x2, x1, 0 +_fmsub_jr2: fmsub.s x2, x2, x2, x2 + la x1, _fmsub_jr3 + jalr x3, x1, 0 +_fmsub_jr3: fmsub.s x3, x3, x3, x3 + la x1, _fmsub_jr4 + jalr x4, x1, 0 +_fmsub_jr4: fmsub.s x4, x4, x4, x4 + la x1, _fmsub_jr5 + jalr x5, x1, 0 +_fmsub_jr5: fmsub.s x5, x5, x5, x5 + la x1, _fmsub_jr6 + jalr x6, x1, 0 +_fmsub_jr6: fmsub.s x6, x6, x6, x6 + la x1, _fmsub_jr7 + jalr x7, x1, 0 +_fmsub_jr7: fmsub.s x7, x7, x7, x7 + la x1, _fmsub_jr8 + jalr x8, x1, 0 +_fmsub_jr8: fmsub.s x8, x8, x8, x8 + la x1, _fmsub_jr9 + jalr x9, x1, 0 +_fmsub_jr9: fmsub.s x9, x9, x9, x9 + la x1, _fmsub_jr10 + jalr x10, x1, 0 +_fmsub_jr10: fmsub.s x10, x10, x10, x10 + la x1, _fmsub_jr11 + jalr x11, x1, 0 +_fmsub_jr11: fmsub.s x11, x11, x11, x11 + la x1, _fmsub_jr12 + jalr x12, x1, 0 +_fmsub_jr12: fmsub.s x12, x12, x12, x12 + la x1, _fmsub_jr13 + jalr x13, x1, 0 +_fmsub_jr13: fmsub.s x13, x13, x13, x13 + la x1, _fmsub_jr14 + jalr x14, x1, 0 +_fmsub_jr14: fmsub.s x14, x14, x14, x14 + la x1, _fmsub_jr15 + jalr x15, x1, 0 +_fmsub_jr15: fmsub.s x15, x15, x15, x15 + la x1, _fmsub_jr16 + jalr x16, x1, 0 +_fmsub_jr16: fmsub.s x16, x16, x16, x16 + la x1, _fmsub_jr17 + jalr x17, x1, 0 +_fmsub_jr17: fmsub.s x17, x17, x17, x17 + la x1, _fmsub_jr18 + jalr x18, x1, 0 +_fmsub_jr18: fmsub.s x18, x18, x18, x18 + la x1, _fmsub_jr19 + jalr x19, x1, 0 +_fmsub_jr19: fmsub.s x19, x19, x19, x19 + la x1, _fmsub_jr20 + jalr x20, x1, 0 +_fmsub_jr20: fmsub.s x20, x20, x20, x20 + la x1, _fmsub_jr21 + jalr x21, x1, 0 +_fmsub_jr21: fmsub.s x21, x21, x21, x21 + la x1, _fmsub_jr22 + jalr x22, x1, 0 +_fmsub_jr22: fmsub.s x22, x22, x22, x22 + la x1, _fmsub_jr23 + jalr x23, x1, 0 +_fmsub_jr23: fmsub.s x23, x23, x23, x23 + la x1, _fmsub_jr24 + jalr x24, x1, 0 +_fmsub_jr24: fmsub.s x24, x24, x24, x24 + la x1, _fmsub_jr25 + jalr x25, x1, 0 +_fmsub_jr25: fmsub.s x25, x25, x25, x25 + la x1, _fmsub_jr26 + jalr x26, x1, 0 +_fmsub_jr26: fmsub.s x26, x26, x26, x26 + la x1, _fmsub_jr27 + jalr x27, x1, 0 +_fmsub_jr27: fmsub.s x27, x27, x27, x27 + la x1, _fmsub_jr28 + jalr x28, x1, 0 +_fmsub_jr28: fmsub.s x28, x28, x28, x28 + la x1, _fmsub_jr29 + jalr x29, x1, 0 +_fmsub_jr29: fmsub.s x29, x29, x29, x29 + la x1, _fmsub_jr30 + jalr x30, x1, 0 +_fmsub_jr30: fmsub.s x30, x30, x30, x30 + la x1, _fmsub_jr31 + jalr x31, x1, 0 +_fmsub_jr31: fmsub.s x31, x31, x31, x31 + + // 33 - jal -> fmul (rs1, rs2) + jal x0, _fmul_j0 +_fmul_j0: fmul.s x0, x0, x0 + jal x1, _fmul_j1 +_fmul_j1: fmul.s x1, x1, x1 + jal x2, _fmul_j2 +_fmul_j2: fmul.s x2, x2, x2 + jal x3, _fmul_j3 +_fmul_j3: fmul.s x3, x3, x3 + jal x4, _fmul_j4 +_fmul_j4: fmul.s x4, x4, x4 + jal x5, _fmul_j5 +_fmul_j5: fmul.s x5, x5, x5 + jal x6, _fmul_j6 +_fmul_j6: fmul.s x6, x6, x6 + jal x7, _fmul_j7 +_fmul_j7: fmul.s x7, x7, x7 + jal x8, _fmul_j8 +_fmul_j8: fmul.s x8, x8, x8 + jal x9, _fmul_j9 +_fmul_j9: fmul.s x9, x9, x9 + jal x10, _fmul_j10 +_fmul_j10: fmul.s x10, x10, x10 + jal x11, _fmul_j11 +_fmul_j11: fmul.s x11, x11, x11 + jal x12, _fmul_j12 +_fmul_j12: fmul.s x12, x12, x12 + jal x13, _fmul_j13 +_fmul_j13: fmul.s x13, x13, x13 + jal x14, _fmul_j14 +_fmul_j14: fmul.s x14, x14, x14 + jal x15, _fmul_j15 +_fmul_j15: fmul.s x15, x15, x15 + jal x16, _fmul_j16 +_fmul_j16: fmul.s x16, x16, x16 + jal x17, _fmul_j17 +_fmul_j17: fmul.s x17, x17, x17 + jal x18, _fmul_j18 +_fmul_j18: fmul.s x18, x18, x18 + jal x19, _fmul_j19 +_fmul_j19: fmul.s x19, x19, x19 + jal x20, _fmul_j20 +_fmul_j20: fmul.s x20, x20, x20 + jal x21, _fmul_j21 +_fmul_j21: fmul.s x21, x21, x21 + jal x22, _fmul_j22 +_fmul_j22: fmul.s x22, x22, x22 + jal x23, _fmul_j23 +_fmul_j23: fmul.s x23, x23, x23 + jal x24, _fmul_j24 +_fmul_j24: fmul.s x24, x24, x24 + jal x25, _fmul_j25 +_fmul_j25: fmul.s x25, x25, x25 + jal x26, _fmul_j26 +_fmul_j26: fmul.s x26, x26, x26 + jal x27, _fmul_j27 +_fmul_j27: fmul.s x27, x27, x27 + jal x28, _fmul_j28 +_fmul_j28: fmul.s x28, x28, x28 + jal x29, _fmul_j29 +_fmul_j29: fmul.s x29, x29, x29 + jal x30, _fmul_j30 +_fmul_j30: fmul.s x30, x30, x30 + jal x31, _fmul_j31 +_fmul_j31: fmul.s x31, x31, x31 + + // 34 - jalr -> fmul (rs1, rs2) + la x1, _fmul_jr0 + jalr x0, x1, 0 +_fmul_jr0: fmul.s x0, x0, x0 + la x1, _fmul_jr1 + jalr x1, x1, 0 +_fmul_jr1: fmul.s x1, x1, x1 + la x1, _fmul_jr2 + jalr x2, x1, 0 +_fmul_jr2: fmul.s x2, x2, x2 + la x1, _fmul_jr3 + jalr x3, x1, 0 +_fmul_jr3: fmul.s x3, x3, x3 + la x1, _fmul_jr4 + jalr x4, x1, 0 +_fmul_jr4: fmul.s x4, x4, x4 + la x1, _fmul_jr5 + jalr x5, x1, 0 +_fmul_jr5: fmul.s x5, x5, x5 + la x1, _fmul_jr6 + jalr x6, x1, 0 +_fmul_jr6: fmul.s x6, x6, x6 + la x1, _fmul_jr7 + jalr x7, x1, 0 +_fmul_jr7: fmul.s x7, x7, x7 + la x1, _fmul_jr8 + jalr x8, x1, 0 +_fmul_jr8: fmul.s x8, x8, x8 + la x1, _fmul_jr9 + jalr x9, x1, 0 +_fmul_jr9: fmul.s x9, x9, x9 + la x1, _fmul_jr10 + jalr x10, x1, 0 +_fmul_jr10: fmul.s x10, x10, x10 + la x1, _fmul_jr11 + jalr x11, x1, 0 +_fmul_jr11: fmul.s x11, x11, x11 + la x1, _fmul_jr12 + jalr x12, x1, 0 +_fmul_jr12: fmul.s x12, x12, x12 + la x1, _fmul_jr13 + jalr x13, x1, 0 +_fmul_jr13: fmul.s x13, x13, x13 + la x1, _fmul_jr14 + jalr x14, x1, 0 +_fmul_jr14: fmul.s x14, x14, x14 + la x1, _fmul_jr15 + jalr x15, x1, 0 +_fmul_jr15: fmul.s x15, x15, x15 + la x1, _fmul_jr16 + jalr x16, x1, 0 +_fmul_jr16: fmul.s x16, x16, x16 + la x1, _fmul_jr17 + jalr x17, x1, 0 +_fmul_jr17: fmul.s x17, x17, x17 + la x1, _fmul_jr18 + jalr x18, x1, 0 +_fmul_jr18: fmul.s x18, x18, x18 + la x1, _fmul_jr19 + jalr x19, x1, 0 +_fmul_jr19: fmul.s x19, x19, x19 + la x1, _fmul_jr20 + jalr x20, x1, 0 +_fmul_jr20: fmul.s x20, x20, x20 + la x1, _fmul_jr21 + jalr x21, x1, 0 +_fmul_jr21: fmul.s x21, x21, x21 + la x1, _fmul_jr22 + jalr x22, x1, 0 +_fmul_jr22: fmul.s x22, x22, x22 + la x1, _fmul_jr23 + jalr x23, x1, 0 +_fmul_jr23: fmul.s x23, x23, x23 + la x1, _fmul_jr24 + jalr x24, x1, 0 +_fmul_jr24: fmul.s x24, x24, x24 + la x1, _fmul_jr25 + jalr x25, x1, 0 +_fmul_jr25: fmul.s x25, x25, x25 + la x1, _fmul_jr26 + jalr x26, x1, 0 +_fmul_jr26: fmul.s x26, x26, x26 + la x1, _fmul_jr27 + jalr x27, x1, 0 +_fmul_jr27: fmul.s x27, x27, x27 + la x1, _fmul_jr28 + jalr x28, x1, 0 +_fmul_jr28: fmul.s x28, x28, x28 + la x1, _fmul_jr29 + jalr x29, x1, 0 +_fmul_jr29: fmul.s x29, x29, x29 + la x1, _fmul_jr30 + jalr x30, x1, 0 +_fmul_jr30: fmul.s x30, x30, x30 + la x1, _fmul_jr31 + jalr x31, x1, 0 +_fmul_jr31: fmul.s x31, x31, x31 + + // 35 - jal -> fnmadd (rs1, rs2, rs3) + jal x0, _fnmadd_j0 +_fnmadd_j0: fnmadd.s x0, x0, x0, x0 + jal x1, _fnmadd_j1 +_fnmadd_j1: fnmadd.s x1, x1, x1, x1 + jal x2, _fnmadd_j2 +_fnmadd_j2: fnmadd.s x2, x2, x2, x2 + jal x3, _fnmadd_j3 +_fnmadd_j3: fnmadd.s x3, x3, x3, x3 + jal x4, _fnmadd_j4 +_fnmadd_j4: fnmadd.s x4, x4, x4, x4 + jal x5, _fnmadd_j5 +_fnmadd_j5: fnmadd.s x5, x5, x5, x5 + jal x6, _fnmadd_j6 +_fnmadd_j6: fnmadd.s x6, x6, x6, x6 + jal x7, _fnmadd_j7 +_fnmadd_j7: fnmadd.s x7, x7, x7, x7 + jal x8, _fnmadd_j8 +_fnmadd_j8: fnmadd.s x8, x8, x8, x8 + jal x9, _fnmadd_j9 +_fnmadd_j9: fnmadd.s x9, x9, x9, x9 + jal x10, _fnmadd_j10 +_fnmadd_j10: fnmadd.s x10, x10, x10, x10 + jal x11, _fnmadd_j11 +_fnmadd_j11: fnmadd.s x11, x11, x11, x11 + jal x12, _fnmadd_j12 +_fnmadd_j12: fnmadd.s x12, x12, x12, x12 + jal x13, _fnmadd_j13 +_fnmadd_j13: fnmadd.s x13, x13, x13, x13 + jal x14, _fnmadd_j14 +_fnmadd_j14: fnmadd.s x14, x14, x14, x14 + jal x15, _fnmadd_j15 +_fnmadd_j15: fnmadd.s x15, x15, x15, x15 + jal x16, _fnmadd_j16 +_fnmadd_j16: fnmadd.s x16, x16, x16, x16 + jal x17, _fnmadd_j17 +_fnmadd_j17: fnmadd.s x17, x17, x17, x17 + jal x18, _fnmadd_j18 +_fnmadd_j18: fnmadd.s x18, x18, x18, x18 + jal x19, _fnmadd_j19 +_fnmadd_j19: fnmadd.s x19, x19, x19, x19 + jal x20, _fnmadd_j20 +_fnmadd_j20: fnmadd.s x20, x20, x20, x20 + jal x21, _fnmadd_j21 +_fnmadd_j21: fnmadd.s x21, x21, x21, x21 + jal x22, _fnmadd_j22 +_fnmadd_j22: fnmadd.s x22, x22, x22, x22 + jal x23, _fnmadd_j23 +_fnmadd_j23: fnmadd.s x23, x23, x23, x23 + jal x24, _fnmadd_j24 +_fnmadd_j24: fnmadd.s x24, x24, x24, x24 + jal x25, _fnmadd_j25 +_fnmadd_j25: fnmadd.s x25, x25, x25, x25 + jal x26, _fnmadd_j26 +_fnmadd_j26: fnmadd.s x26, x26, x26, x26 + jal x27, _fnmadd_j27 +_fnmadd_j27: fnmadd.s x27, x27, x27, x27 + jal x28, _fnmadd_j28 +_fnmadd_j28: fnmadd.s x28, x28, x28, x28 + jal x29, _fnmadd_j29 +_fnmadd_j29: fnmadd.s x29, x29, x29, x29 + jal x30, _fnmadd_j30 +_fnmadd_j30: fnmadd.s x30, x30, x30, x30 + jal x31, _fnmadd_j31 +_fnmadd_j31: fnmadd.s x31, x31, x31, x31 + + // 36 - jalr -> fnmadd (rs1, rs2, rs3) + la x1, _fnmadd_jr0 + jalr x0, x1, 0 +_fnmadd_jr0: fnmadd.s x0, x0, x0, x0 + la x1, _fnmadd_jr1 + jalr x1, x1, 0 +_fnmadd_jr1: fnmadd.s x1, x1, x1, x1 + la x1, _fnmadd_jr2 + jalr x2, x1, 0 +_fnmadd_jr2: fnmadd.s x2, x2, x2, x2 + la x1, _fnmadd_jr3 + jalr x3, x1, 0 +_fnmadd_jr3: fnmadd.s x3, x3, x3, x3 + la x1, _fnmadd_jr4 + jalr x4, x1, 0 +_fnmadd_jr4: fnmadd.s x4, x4, x4, x4 + la x1, _fnmadd_jr5 + jalr x5, x1, 0 +_fnmadd_jr5: fnmadd.s x5, x5, x5, x5 + la x1, _fnmadd_jr6 + jalr x6, x1, 0 +_fnmadd_jr6: fnmadd.s x6, x6, x6, x6 + la x1, _fnmadd_jr7 + jalr x7, x1, 0 +_fnmadd_jr7: fnmadd.s x7, x7, x7, x7 + la x1, _fnmadd_jr8 + jalr x8, x1, 0 +_fnmadd_jr8: fnmadd.s x8, x8, x8, x8 + la x1, _fnmadd_jr9 + jalr x9, x1, 0 +_fnmadd_jr9: fnmadd.s x9, x9, x9, x9 + la x1, _fnmadd_jr10 + jalr x10, x1, 0 +_fnmadd_jr10: fnmadd.s x10, x10, x10, x10 + la x1, _fnmadd_jr11 + jalr x11, x1, 0 +_fnmadd_jr11: fnmadd.s x11, x11, x11, x11 + la x1, _fnmadd_jr12 + jalr x12, x1, 0 +_fnmadd_jr12: fnmadd.s x12, x12, x12, x12 + la x1, _fnmadd_jr13 + jalr x13, x1, 0 +_fnmadd_jr13: fnmadd.s x13, x13, x13, x13 + la x1, _fnmadd_jr14 + jalr x14, x1, 0 +_fnmadd_jr14: fnmadd.s x14, x14, x14, x14 + la x1, _fnmadd_jr15 + jalr x15, x1, 0 +_fnmadd_jr15: fnmadd.s x15, x15, x15, x15 + la x1, _fnmadd_jr16 + jalr x16, x1, 0 +_fnmadd_jr16: fnmadd.s x16, x16, x16, x16 + la x1, _fnmadd_jr17 + jalr x17, x1, 0 +_fnmadd_jr17: fnmadd.s x17, x17, x17, x17 + la x1, _fnmadd_jr18 + jalr x18, x1, 0 +_fnmadd_jr18: fnmadd.s x18, x18, x18, x18 + la x1, _fnmadd_jr19 + jalr x19, x1, 0 +_fnmadd_jr19: fnmadd.s x19, x19, x19, x19 + la x1, _fnmadd_jr20 + jalr x20, x1, 0 +_fnmadd_jr20: fnmadd.s x20, x20, x20, x20 + la x1, _fnmadd_jr21 + jalr x21, x1, 0 +_fnmadd_jr21: fnmadd.s x21, x21, x21, x21 + la x1, _fnmadd_jr22 + jalr x22, x1, 0 +_fnmadd_jr22: fnmadd.s x22, x22, x22, x22 + la x1, _fnmadd_jr23 + jalr x23, x1, 0 +_fnmadd_jr23: fnmadd.s x23, x23, x23, x23 + la x1, _fnmadd_jr24 + jalr x24, x1, 0 +_fnmadd_jr24: fnmadd.s x24, x24, x24, x24 + la x1, _fnmadd_jr25 + jalr x25, x1, 0 +_fnmadd_jr25: fnmadd.s x25, x25, x25, x25 + la x1, _fnmadd_jr26 + jalr x26, x1, 0 +_fnmadd_jr26: fnmadd.s x26, x26, x26, x26 + la x1, _fnmadd_jr27 + jalr x27, x1, 0 +_fnmadd_jr27: fnmadd.s x27, x27, x27, x27 + la x1, _fnmadd_jr28 + jalr x28, x1, 0 +_fnmadd_jr28: fnmadd.s x28, x28, x28, x28 + la x1, _fnmadd_jr29 + jalr x29, x1, 0 +_fnmadd_jr29: fnmadd.s x29, x29, x29, x29 + la x1, _fnmadd_jr30 + jalr x30, x1, 0 +_fnmadd_jr30: fnmadd.s x30, x30, x30, x30 + la x1, _fnmadd_jr31 + jalr x31, x1, 0 +_fnmadd_jr31: fnmadd.s x31, x31, x31, x31 + + // 37 - jalr -> fnmsub (rs1, rs2, rs3) + jal x0, _fnmsub_j0 +_fnmsub_j0: fnmsub.s x0, x0, x0, x0 + jal x1, _fnmsub_j1 +_fnmsub_j1: fnmsub.s x1, x1, x1, x1 + jal x2, _fnmsub_j2 +_fnmsub_j2: fnmsub.s x2, x2, x2, x2 + jal x3, _fnmsub_j3 +_fnmsub_j3: fnmsub.s x3, x3, x3, x3 + jal x4, _fnmsub_j4 +_fnmsub_j4: fnmsub.s x4, x4, x4, x4 + jal x5, _fnmsub_j5 +_fnmsub_j5: fnmsub.s x5, x5, x5, x5 + jal x6, _fnmsub_j6 +_fnmsub_j6: fnmsub.s x6, x6, x6, x6 + jal x7, _fnmsub_j7 +_fnmsub_j7: fnmsub.s x7, x7, x7, x7 + jal x8, _fnmsub_j8 +_fnmsub_j8: fnmsub.s x8, x8, x8, x8 + jal x9, _fnmsub_j9 +_fnmsub_j9: fnmsub.s x9, x9, x9, x9 + jal x10, _fnmsub_j10 +_fnmsub_j10: fnmsub.s x10, x10, x10, x10 + jal x11, _fnmsub_j11 +_fnmsub_j11: fnmsub.s x11, x11, x11, x11 + jal x12, _fnmsub_j12 +_fnmsub_j12: fnmsub.s x12, x12, x12, x12 + jal x13, _fnmsub_j13 +_fnmsub_j13: fnmsub.s x13, x13, x13, x13 + jal x14, _fnmsub_j14 +_fnmsub_j14: fnmsub.s x14, x14, x14, x14 + jal x15, _fnmsub_j15 +_fnmsub_j15: fnmsub.s x15, x15, x15, x15 + jal x16, _fnmsub_j16 +_fnmsub_j16: fnmsub.s x16, x16, x16, x16 + jal x17, _fnmsub_j17 +_fnmsub_j17: fnmsub.s x17, x17, x17, x17 + jal x18, _fnmsub_j18 +_fnmsub_j18: fnmsub.s x18, x18, x18, x18 + jal x19, _fnmsub_j19 +_fnmsub_j19: fnmsub.s x19, x19, x19, x19 + jal x20, _fnmsub_j20 +_fnmsub_j20: fnmsub.s x20, x20, x20, x20 + jal x21, _fnmsub_j21 +_fnmsub_j21: fnmsub.s x21, x21, x21, x21 + jal x22, _fnmsub_j22 +_fnmsub_j22: fnmsub.s x22, x22, x22, x22 + jal x23, _fnmsub_j23 +_fnmsub_j23: fnmsub.s x23, x23, x23, x23 + jal x24, _fnmsub_j24 +_fnmsub_j24: fnmsub.s x24, x24, x24, x24 + jal x25, _fnmsub_j25 +_fnmsub_j25: fnmsub.s x25, x25, x25, x25 + jal x26, _fnmsub_j26 +_fnmsub_j26: fnmsub.s x26, x26, x26, x26 + jal x27, _fnmsub_j27 +_fnmsub_j27: fnmsub.s x27, x27, x27, x27 + jal x28, _fnmsub_j28 +_fnmsub_j28: fnmsub.s x28, x28, x28, x28 + jal x29, _fnmsub_j29 +_fnmsub_j29: fnmsub.s x29, x29, x29, x29 + jal x30, _fnmsub_j30 +_fnmsub_j30: fnmsub.s x30, x30, x30, x30 + jal x31, _fnmsub_j31 +_fnmsub_j31: fnmsub.s x31, x31, x31, x31 + + // 38 - jalr -> fnmsub (rs1, rs2, rs3) + la x1, _fnmsub_jr0 + jalr x0, x1, 0 +_fnmsub_jr0: fnmsub.s x0, x0, x0, x0 + la x1, _fnmsub_jr1 + jalr x1, x1, 0 +_fnmsub_jr1: fnmsub.s x1, x1, x1, x1 + la x1, _fnmsub_jr2 + jalr x2, x1, 0 +_fnmsub_jr2: fnmsub.s x2, x2, x2, x2 + la x1, _fnmsub_jr3 + jalr x3, x1, 0 +_fnmsub_jr3: fnmsub.s x3, x3, x3, x3 + la x1, _fnmsub_jr4 + jalr x4, x1, 0 +_fnmsub_jr4: fnmsub.s x4, x4, x4, x4 + la x1, _fnmsub_jr5 + jalr x5, x1, 0 +_fnmsub_jr5: fnmsub.s x5, x5, x5, x5 + la x1, _fnmsub_jr6 + jalr x6, x1, 0 +_fnmsub_jr6: fnmsub.s x6, x6, x6, x6 + la x1, _fnmsub_jr7 + jalr x7, x1, 0 +_fnmsub_jr7: fnmsub.s x7, x7, x7, x7 + la x1, _fnmsub_jr8 + jalr x8, x1, 0 +_fnmsub_jr8: fnmsub.s x8, x8, x8, x8 + la x1, _fnmsub_jr9 + jalr x9, x1, 0 +_fnmsub_jr9: fnmsub.s x9, x9, x9, x9 + la x1, _fnmsub_jr10 + jalr x10, x1, 0 +_fnmsub_jr10: fnmsub.s x10, x10, x10, x10 + la x1, _fnmsub_jr11 + jalr x11, x1, 0 +_fnmsub_jr11: fnmsub.s x11, x11, x11, x11 + la x1, _fnmsub_jr12 + jalr x12, x1, 0 +_fnmsub_jr12: fnmsub.s x12, x12, x12, x12 + la x1, _fnmsub_jr13 + jalr x13, x1, 0 +_fnmsub_jr13: fnmsub.s x13, x13, x13, x13 + la x1, _fnmsub_jr14 + jalr x14, x1, 0 +_fnmsub_jr14: fnmsub.s x14, x14, x14, x14 + la x1, _fnmsub_jr15 + jalr x15, x1, 0 +_fnmsub_jr15: fnmsub.s x15, x15, x15, x15 + la x1, _fnmsub_jr16 + jalr x16, x1, 0 +_fnmsub_jr16: fnmsub.s x16, x16, x16, x16 + la x1, _fnmsub_jr17 + jalr x17, x1, 0 +_fnmsub_jr17: fnmsub.s x17, x17, x17, x17 + la x1, _fnmsub_jr18 + jalr x18, x1, 0 +_fnmsub_jr18: fnmsub.s x18, x18, x18, x18 + la x1, _fnmsub_jr19 + jalr x19, x1, 0 +_fnmsub_jr19: fnmsub.s x19, x19, x19, x19 + la x1, _fnmsub_jr20 + jalr x20, x1, 0 +_fnmsub_jr20: fnmsub.s x20, x20, x20, x20 + la x1, _fnmsub_jr21 + jalr x21, x1, 0 +_fnmsub_jr21: fnmsub.s x21, x21, x21, x21 + la x1, _fnmsub_jr22 + jalr x22, x1, 0 +_fnmsub_jr22: fnmsub.s x22, x22, x22, x22 + la x1, _fnmsub_jr23 + jalr x23, x1, 0 +_fnmsub_jr23: fnmsub.s x23, x23, x23, x23 + la x1, _fnmsub_jr24 + jalr x24, x1, 0 +_fnmsub_jr24: fnmsub.s x24, x24, x24, x24 + la x1, _fnmsub_jr25 + jalr x25, x1, 0 +_fnmsub_jr25: fnmsub.s x25, x25, x25, x25 + la x1, _fnmsub_jr26 + jalr x26, x1, 0 +_fnmsub_jr26: fnmsub.s x26, x26, x26, x26 + la x1, _fnmsub_jr27 + jalr x27, x1, 0 +_fnmsub_jr27: fnmsub.s x27, x27, x27, x27 + la x1, _fnmsub_jr28 + jalr x28, x1, 0 +_fnmsub_jr28: fnmsub.s x28, x28, x28, x28 + la x1, _fnmsub_jr29 + jalr x29, x1, 0 +_fnmsub_jr29: fnmsub.s x29, x29, x29, x29 + la x1, _fnmsub_jr30 + jalr x30, x1, 0 +_fnmsub_jr30: fnmsub.s x30, x30, x30, x30 + la x1, _fnmsub_jr31 + jalr x31, x1, 0 +_fnmsub_jr31: fnmsub.s x31, x31, x31, x31 + + // 39 - jal -> fsgnjn (rs1, rs2) + jal x0, _fsgnjn_j0 +_fsgnjn_j0: fsgnjn.s x0, x0, x0 + jal x1, _fsgnjn_j1 +_fsgnjn_j1: fsgnjn.s x1, x1, x1 + jal x2, _fsgnjn_j2 +_fsgnjn_j2: fsgnjn.s x2, x2, x2 + jal x3, _fsgnjn_j3 +_fsgnjn_j3: fsgnjn.s x3, x3, x3 + jal x4, _fsgnjn_j4 +_fsgnjn_j4: fsgnjn.s x4, x4, x4 + jal x5, _fsgnjn_j5 +_fsgnjn_j5: fsgnjn.s x5, x5, x5 + jal x6, _fsgnjn_j6 +_fsgnjn_j6: fsgnjn.s x6, x6, x6 + jal x7, _fsgnjn_j7 +_fsgnjn_j7: fsgnjn.s x7, x7, x7 + jal x8, _fsgnjn_j8 +_fsgnjn_j8: fsgnjn.s x8, x8, x8 + jal x9, _fsgnjn_j9 +_fsgnjn_j9: fsgnjn.s x9, x9, x9 + jal x10, _fsgnjn_j10 +_fsgnjn_j10: fsgnjn.s x10, x10, x10 + jal x11, _fsgnjn_j11 +_fsgnjn_j11: fsgnjn.s x11, x11, x11 + jal x12, _fsgnjn_j12 +_fsgnjn_j12: fsgnjn.s x12, x12, x12 + jal x13, _fsgnjn_j13 +_fsgnjn_j13: fsgnjn.s x13, x13, x13 + jal x14, _fsgnjn_j14 +_fsgnjn_j14: fsgnjn.s x14, x14, x14 + jal x15, _fsgnjn_j15 +_fsgnjn_j15: fsgnjn.s x15, x15, x15 + jal x16, _fsgnjn_j16 +_fsgnjn_j16: fsgnjn.s x16, x16, x16 + jal x17, _fsgnjn_j17 +_fsgnjn_j17: fsgnjn.s x17, x17, x17 + jal x18, _fsgnjn_j18 +_fsgnjn_j18: fsgnjn.s x18, x18, x18 + jal x19, _fsgnjn_j19 +_fsgnjn_j19: fsgnjn.s x19, x19, x19 + jal x20, _fsgnjn_j20 +_fsgnjn_j20: fsgnjn.s x20, x20, x20 + jal x21, _fsgnjn_j21 +_fsgnjn_j21: fsgnjn.s x21, x21, x21 + jal x22, _fsgnjn_j22 +_fsgnjn_j22: fsgnjn.s x22, x22, x22 + jal x23, _fsgnjn_j23 +_fsgnjn_j23: fsgnjn.s x23, x23, x23 + jal x24, _fsgnjn_j24 +_fsgnjn_j24: fsgnjn.s x24, x24, x24 + jal x25, _fsgnjn_j25 +_fsgnjn_j25: fsgnjn.s x25, x25, x25 + jal x26, _fsgnjn_j26 +_fsgnjn_j26: fsgnjn.s x26, x26, x26 + jal x27, _fsgnjn_j27 +_fsgnjn_j27: fsgnjn.s x27, x27, x27 + jal x28, _fsgnjn_j28 +_fsgnjn_j28: fsgnjn.s x28, x28, x28 + jal x29, _fsgnjn_j29 +_fsgnjn_j29: fsgnjn.s x29, x29, x29 + jal x30, _fsgnjn_j30 +_fsgnjn_j30: fsgnjn.s x30, x30, x30 + jal x31, _fsgnjn_j31 +_fsgnjn_j31: fsgnjn.s x31, x31, x31 + + // 40 - jalr -> fsgnjn (rs1, rs2) + la x1, _fsgnjn_jr0 + jalr x0, x1, 0 +_fsgnjn_jr0: fsgnjn.s x0, x0, x0 + la x1, _fsgnjn_jr1 + jalr x1, x1, 0 +_fsgnjn_jr1: fsgnjn.s x1, x1, x1 + la x1, _fsgnjn_jr2 + jalr x2, x1, 0 +_fsgnjn_jr2: fsgnjn.s x2, x2, x2 + la x1, _fsgnjn_jr3 + jalr x3, x1, 0 +_fsgnjn_jr3: fsgnjn.s x3, x3, x3 + la x1, _fsgnjn_jr4 + jalr x4, x1, 0 +_fsgnjn_jr4: fsgnjn.s x4, x4, x4 + la x1, _fsgnjn_jr5 + jalr x5, x1, 0 +_fsgnjn_jr5: fsgnjn.s x5, x5, x5 + la x1, _fsgnjn_jr6 + jalr x6, x1, 0 +_fsgnjn_jr6: fsgnjn.s x6, x6, x6 + la x1, _fsgnjn_jr7 + jalr x7, x1, 0 +_fsgnjn_jr7: fsgnjn.s x7, x7, x7 + la x1, _fsgnjn_jr8 + jalr x8, x1, 0 +_fsgnjn_jr8: fsgnjn.s x8, x8, x8 + la x1, _fsgnjn_jr9 + jalr x9, x1, 0 +_fsgnjn_jr9: fsgnjn.s x9, x9, x9 + la x1, _fsgnjn_jr10 + jalr x10, x1, 0 +_fsgnjn_jr10: fsgnjn.s x10, x10, x10 + la x1, _fsgnjn_jr11 + jalr x11, x1, 0 +_fsgnjn_jr11: fsgnjn.s x11, x11, x11 + la x1, _fsgnjn_jr12 + jalr x12, x1, 0 +_fsgnjn_jr12: fsgnjn.s x12, x12, x12 + la x1, _fsgnjn_jr13 + jalr x13, x1, 0 +_fsgnjn_jr13: fsgnjn.s x13, x13, x13 + la x1, _fsgnjn_jr14 + jalr x14, x1, 0 +_fsgnjn_jr14: fsgnjn.s x14, x14, x14 + la x1, _fsgnjn_jr15 + jalr x15, x1, 0 +_fsgnjn_jr15: fsgnjn.s x15, x15, x15 + la x1, _fsgnjn_jr16 + jalr x16, x1, 0 +_fsgnjn_jr16: fsgnjn.s x16, x16, x16 + la x1, _fsgnjn_jr17 + jalr x17, x1, 0 +_fsgnjn_jr17: fsgnjn.s x17, x17, x17 + la x1, _fsgnjn_jr18 + jalr x18, x1, 0 +_fsgnjn_jr18: fsgnjn.s x18, x18, x18 + la x1, _fsgnjn_jr19 + jalr x19, x1, 0 +_fsgnjn_jr19: fsgnjn.s x19, x19, x19 + la x1, _fsgnjn_jr20 + jalr x20, x1, 0 +_fsgnjn_jr20: fsgnjn.s x20, x20, x20 + la x1, _fsgnjn_jr21 + jalr x21, x1, 0 +_fsgnjn_jr21: fsgnjn.s x21, x21, x21 + la x1, _fsgnjn_jr22 + jalr x22, x1, 0 +_fsgnjn_jr22: fsgnjn.s x22, x22, x22 + la x1, _fsgnjn_jr23 + jalr x23, x1, 0 +_fsgnjn_jr23: fsgnjn.s x23, x23, x23 + la x1, _fsgnjn_jr24 + jalr x24, x1, 0 +_fsgnjn_jr24: fsgnjn.s x24, x24, x24 + la x1, _fsgnjn_jr25 + jalr x25, x1, 0 +_fsgnjn_jr25: fsgnjn.s x25, x25, x25 + la x1, _fsgnjn_jr26 + jalr x26, x1, 0 +_fsgnjn_jr26: fsgnjn.s x26, x26, x26 + la x1, _fsgnjn_jr27 + jalr x27, x1, 0 +_fsgnjn_jr27: fsgnjn.s x27, x27, x27 + la x1, _fsgnjn_jr28 + jalr x28, x1, 0 +_fsgnjn_jr28: fsgnjn.s x28, x28, x28 + la x1, _fsgnjn_jr29 + jalr x29, x1, 0 +_fsgnjn_jr29: fsgnjn.s x29, x29, x29 + la x1, _fsgnjn_jr30 + jalr x30, x1, 0 +_fsgnjn_jr30: fsgnjn.s x30, x30, x30 + la x1, _fsgnjn_jr31 + jalr x31, x1, 0 +_fsgnjn_jr31: fsgnjn.s x31, x31, x31 + + // 41 - jal -> fsgnj (rs1, rs2) + jal x0, _fsgnj_j0 +_fsgnj_j0: fsgnj.s x0, x0, x0 + jal x1, _fsgnj_j1 +_fsgnj_j1: fsgnj.s x1, x1, x1 + jal x2, _fsgnj_j2 +_fsgnj_j2: fsgnj.s x2, x2, x2 + jal x3, _fsgnj_j3 +_fsgnj_j3: fsgnj.s x3, x3, x3 + jal x4, _fsgnj_j4 +_fsgnj_j4: fsgnj.s x4, x4, x4 + jal x5, _fsgnj_j5 +_fsgnj_j5: fsgnj.s x5, x5, x5 + jal x6, _fsgnj_j6 +_fsgnj_j6: fsgnj.s x6, x6, x6 + jal x7, _fsgnj_j7 +_fsgnj_j7: fsgnj.s x7, x7, x7 + jal x8, _fsgnj_j8 +_fsgnj_j8: fsgnj.s x8, x8, x8 + jal x9, _fsgnj_j9 +_fsgnj_j9: fsgnj.s x9, x9, x9 + jal x10, _fsgnj_j10 +_fsgnj_j10: fsgnj.s x10, x10, x10 + jal x11, _fsgnj_j11 +_fsgnj_j11: fsgnj.s x11, x11, x11 + jal x12, _fsgnj_j12 +_fsgnj_j12: fsgnj.s x12, x12, x12 + jal x13, _fsgnj_j13 +_fsgnj_j13: fsgnj.s x13, x13, x13 + jal x14, _fsgnj_j14 +_fsgnj_j14: fsgnj.s x14, x14, x14 + jal x15, _fsgnj_j15 +_fsgnj_j15: fsgnj.s x15, x15, x15 + jal x16, _fsgnj_j16 +_fsgnj_j16: fsgnj.s x16, x16, x16 + jal x17, _fsgnj_j17 +_fsgnj_j17: fsgnj.s x17, x17, x17 + jal x18, _fsgnj_j18 +_fsgnj_j18: fsgnj.s x18, x18, x18 + jal x19, _fsgnj_j19 +_fsgnj_j19: fsgnj.s x19, x19, x19 + jal x20, _fsgnj_j20 +_fsgnj_j20: fsgnj.s x20, x20, x20 + jal x21, _fsgnj_j21 +_fsgnj_j21: fsgnj.s x21, x21, x21 + jal x22, _fsgnj_j22 +_fsgnj_j22: fsgnj.s x22, x22, x22 + jal x23, _fsgnj_j23 +_fsgnj_j23: fsgnj.s x23, x23, x23 + jal x24, _fsgnj_j24 +_fsgnj_j24: fsgnj.s x24, x24, x24 + jal x25, _fsgnj_j25 +_fsgnj_j25: fsgnj.s x25, x25, x25 + jal x26, _fsgnj_j26 +_fsgnj_j26: fsgnj.s x26, x26, x26 + jal x27, _fsgnj_j27 +_fsgnj_j27: fsgnj.s x27, x27, x27 + jal x28, _fsgnj_j28 +_fsgnj_j28: fsgnj.s x28, x28, x28 + jal x29, _fsgnj_j29 +_fsgnj_j29: fsgnj.s x29, x29, x29 + jal x30, _fsgnj_j30 +_fsgnj_j30: fsgnj.s x30, x30, x30 + jal x31, _fsgnj_j31 +_fsgnj_j31: fsgnj.s x31, x31, x31 + + // 42 - jalr -> fsgnj (rs1, rs2) + la x1, _fsgnj_jr0 + jalr x0, x1, 0 +_fsgnj_jr0: fsgnj.s x0, x0, x0 + la x1, _fsgnj_jr1 + jalr x1, x1, 0 +_fsgnj_jr1: fsgnj.s x1, x1, x1 + la x1, _fsgnj_jr2 + jalr x2, x1, 0 +_fsgnj_jr2: fsgnj.s x2, x2, x2 + la x1, _fsgnj_jr3 + jalr x3, x1, 0 +_fsgnj_jr3: fsgnj.s x3, x3, x3 + la x1, _fsgnj_jr4 + jalr x4, x1, 0 +_fsgnj_jr4: fsgnj.s x4, x4, x4 + la x1, _fsgnj_jr5 + jalr x5, x1, 0 +_fsgnj_jr5: fsgnj.s x5, x5, x5 + la x1, _fsgnj_jr6 + jalr x6, x1, 0 +_fsgnj_jr6: fsgnj.s x6, x6, x6 + la x1, _fsgnj_jr7 + jalr x7, x1, 0 +_fsgnj_jr7: fsgnj.s x7, x7, x7 + la x1, _fsgnj_jr8 + jalr x8, x1, 0 +_fsgnj_jr8: fsgnj.s x8, x8, x8 + la x1, _fsgnj_jr9 + jalr x9, x1, 0 +_fsgnj_jr9: fsgnj.s x9, x9, x9 + la x1, _fsgnj_jr10 + jalr x10, x1, 0 +_fsgnj_jr10: fsgnj.s x10, x10, x10 + la x1, _fsgnj_jr11 + jalr x11, x1, 0 +_fsgnj_jr11: fsgnj.s x11, x11, x11 + la x1, _fsgnj_jr12 + jalr x12, x1, 0 +_fsgnj_jr12: fsgnj.s x12, x12, x12 + la x1, _fsgnj_jr13 + jalr x13, x1, 0 +_fsgnj_jr13: fsgnj.s x13, x13, x13 + la x1, _fsgnj_jr14 + jalr x14, x1, 0 +_fsgnj_jr14: fsgnj.s x14, x14, x14 + la x1, _fsgnj_jr15 + jalr x15, x1, 0 +_fsgnj_jr15: fsgnj.s x15, x15, x15 + la x1, _fsgnj_jr16 + jalr x16, x1, 0 +_fsgnj_jr16: fsgnj.s x16, x16, x16 + la x1, _fsgnj_jr17 + jalr x17, x1, 0 +_fsgnj_jr17: fsgnj.s x17, x17, x17 + la x1, _fsgnj_jr18 + jalr x18, x1, 0 +_fsgnj_jr18: fsgnj.s x18, x18, x18 + la x1, _fsgnj_jr19 + jalr x19, x1, 0 +_fsgnj_jr19: fsgnj.s x19, x19, x19 + la x1, _fsgnj_jr20 + jalr x20, x1, 0 +_fsgnj_jr20: fsgnj.s x20, x20, x20 + la x1, _fsgnj_jr21 + jalr x21, x1, 0 +_fsgnj_jr21: fsgnj.s x21, x21, x21 + la x1, _fsgnj_jr22 + jalr x22, x1, 0 +_fsgnj_jr22: fsgnj.s x22, x22, x22 + la x1, _fsgnj_jr23 + jalr x23, x1, 0 +_fsgnj_jr23: fsgnj.s x23, x23, x23 + la x1, _fsgnj_jr24 + jalr x24, x1, 0 +_fsgnj_jr24: fsgnj.s x24, x24, x24 + la x1, _fsgnj_jr25 + jalr x25, x1, 0 +_fsgnj_jr25: fsgnj.s x25, x25, x25 + la x1, _fsgnj_jr26 + jalr x26, x1, 0 +_fsgnj_jr26: fsgnj.s x26, x26, x26 + la x1, _fsgnj_jr27 + jalr x27, x1, 0 +_fsgnj_jr27: fsgnj.s x27, x27, x27 + la x1, _fsgnj_jr28 + jalr x28, x1, 0 +_fsgnj_jr28: fsgnj.s x28, x28, x28 + la x1, _fsgnj_jr29 + jalr x29, x1, 0 +_fsgnj_jr29: fsgnj.s x29, x29, x29 + la x1, _fsgnj_jr30 + jalr x30, x1, 0 +_fsgnj_jr30: fsgnj.s x30, x30, x30 + la x1, _fsgnj_jr31 + jalr x31, x1, 0 +_fsgnj_jr31: fsgnj.s x31, x31, x31 + + // 43 - jal -> fsgnjx (rs1, rs2) + jal x0, _fsgnjx_j0 +_fsgnjx_j0: fsgnjx.s x0, x0, x0 + jal x1, _fsgnjx_j1 +_fsgnjx_j1: fsgnjx.s x1, x1, x1 + jal x2, _fsgnjx_j2 +_fsgnjx_j2: fsgnjx.s x2, x2, x2 + jal x3, _fsgnjx_j3 +_fsgnjx_j3: fsgnjx.s x3, x3, x3 + jal x4, _fsgnjx_j4 +_fsgnjx_j4: fsgnjx.s x4, x4, x4 + jal x5, _fsgnjx_j5 +_fsgnjx_j5: fsgnjx.s x5, x5, x5 + jal x6, _fsgnjx_j6 +_fsgnjx_j6: fsgnjx.s x6, x6, x6 + jal x7, _fsgnjx_j7 +_fsgnjx_j7: fsgnjx.s x7, x7, x7 + jal x8, _fsgnjx_j8 +_fsgnjx_j8: fsgnjx.s x8, x8, x8 + jal x9, _fsgnjx_j9 +_fsgnjx_j9: fsgnjx.s x9, x9, x9 + jal x10, _fsgnjx_j10 +_fsgnjx_j10: fsgnjx.s x10, x10, x10 + jal x11, _fsgnjx_j11 +_fsgnjx_j11: fsgnjx.s x11, x11, x11 + jal x12, _fsgnjx_j12 +_fsgnjx_j12: fsgnjx.s x12, x12, x12 + jal x13, _fsgnjx_j13 +_fsgnjx_j13: fsgnjx.s x13, x13, x13 + jal x14, _fsgnjx_j14 +_fsgnjx_j14: fsgnjx.s x14, x14, x14 + jal x15, _fsgnjx_j15 +_fsgnjx_j15: fsgnjx.s x15, x15, x15 + jal x16, _fsgnjx_j16 +_fsgnjx_j16: fsgnjx.s x16, x16, x16 + jal x17, _fsgnjx_j17 +_fsgnjx_j17: fsgnjx.s x17, x17, x17 + jal x18, _fsgnjx_j18 +_fsgnjx_j18: fsgnjx.s x18, x18, x18 + jal x19, _fsgnjx_j19 +_fsgnjx_j19: fsgnjx.s x19, x19, x19 + jal x20, _fsgnjx_j20 +_fsgnjx_j20: fsgnjx.s x20, x20, x20 + jal x21, _fsgnjx_j21 +_fsgnjx_j21: fsgnjx.s x21, x21, x21 + jal x22, _fsgnjx_j22 +_fsgnjx_j22: fsgnjx.s x22, x22, x22 + jal x23, _fsgnjx_j23 +_fsgnjx_j23: fsgnjx.s x23, x23, x23 + jal x24, _fsgnjx_j24 +_fsgnjx_j24: fsgnjx.s x24, x24, x24 + jal x25, _fsgnjx_j25 +_fsgnjx_j25: fsgnjx.s x25, x25, x25 + jal x26, _fsgnjx_j26 +_fsgnjx_j26: fsgnjx.s x26, x26, x26 + jal x27, _fsgnjx_j27 +_fsgnjx_j27: fsgnjx.s x27, x27, x27 + jal x28, _fsgnjx_j28 +_fsgnjx_j28: fsgnjx.s x28, x28, x28 + jal x29, _fsgnjx_j29 +_fsgnjx_j29: fsgnjx.s x29, x29, x29 + jal x30, _fsgnjx_j30 +_fsgnjx_j30: fsgnjx.s x30, x30, x30 + jal x31, _fsgnjx_j31 +_fsgnjx_j31: fsgnjx.s x31, x31, x31 + + // 44 - jalr -> fsgnjx (rs1, rs2) + la x1, _fsgnjx_jr0 + jalr x0, x1, 0 +_fsgnjx_jr0: fsgnjx.s x0, x0, x0 + la x1, _fsgnjx_jr1 + jalr x1, x1, 0 +_fsgnjx_jr1: fsgnjx.s x1, x1, x1 + la x1, _fsgnjx_jr2 + jalr x2, x1, 0 +_fsgnjx_jr2: fsgnjx.s x2, x2, x2 + la x1, _fsgnjx_jr3 + jalr x3, x1, 0 +_fsgnjx_jr3: fsgnjx.s x3, x3, x3 + la x1, _fsgnjx_jr4 + jalr x4, x1, 0 +_fsgnjx_jr4: fsgnjx.s x4, x4, x4 + la x1, _fsgnjx_jr5 + jalr x5, x1, 0 +_fsgnjx_jr5: fsgnjx.s x5, x5, x5 + la x1, _fsgnjx_jr6 + jalr x6, x1, 0 +_fsgnjx_jr6: fsgnjx.s x6, x6, x6 + la x1, _fsgnjx_jr7 + jalr x7, x1, 0 +_fsgnjx_jr7: fsgnjx.s x7, x7, x7 + la x1, _fsgnjx_jr8 + jalr x8, x1, 0 +_fsgnjx_jr8: fsgnjx.s x8, x8, x8 + la x1, _fsgnjx_jr9 + jalr x9, x1, 0 +_fsgnjx_jr9: fsgnjx.s x9, x9, x9 + la x1, _fsgnjx_jr10 + jalr x10, x1, 0 +_fsgnjx_jr10: fsgnjx.s x10, x10, x10 + la x1, _fsgnjx_jr11 + jalr x11, x1, 0 +_fsgnjx_jr11: fsgnjx.s x11, x11, x11 + la x1, _fsgnjx_jr12 + jalr x12, x1, 0 +_fsgnjx_jr12: fsgnjx.s x12, x12, x12 + la x1, _fsgnjx_jr13 + jalr x13, x1, 0 +_fsgnjx_jr13: fsgnjx.s x13, x13, x13 + la x1, _fsgnjx_jr14 + jalr x14, x1, 0 +_fsgnjx_jr14: fsgnjx.s x14, x14, x14 + la x1, _fsgnjx_jr15 + jalr x15, x1, 0 +_fsgnjx_jr15: fsgnjx.s x15, x15, x15 + la x1, _fsgnjx_jr16 + jalr x16, x1, 0 +_fsgnjx_jr16: fsgnjx.s x16, x16, x16 + la x1, _fsgnjx_jr17 + jalr x17, x1, 0 +_fsgnjx_jr17: fsgnjx.s x17, x17, x17 + la x1, _fsgnjx_jr18 + jalr x18, x1, 0 +_fsgnjx_jr18: fsgnjx.s x18, x18, x18 + la x1, _fsgnjx_jr19 + jalr x19, x1, 0 +_fsgnjx_jr19: fsgnjx.s x19, x19, x19 + la x1, _fsgnjx_jr20 + jalr x20, x1, 0 +_fsgnjx_jr20: fsgnjx.s x20, x20, x20 + la x1, _fsgnjx_jr21 + jalr x21, x1, 0 +_fsgnjx_jr21: fsgnjx.s x21, x21, x21 + la x1, _fsgnjx_jr22 + jalr x22, x1, 0 +_fsgnjx_jr22: fsgnjx.s x22, x22, x22 + la x1, _fsgnjx_jr23 + jalr x23, x1, 0 +_fsgnjx_jr23: fsgnjx.s x23, x23, x23 + la x1, _fsgnjx_jr24 + jalr x24, x1, 0 +_fsgnjx_jr24: fsgnjx.s x24, x24, x24 + la x1, _fsgnjx_jr25 + jalr x25, x1, 0 +_fsgnjx_jr25: fsgnjx.s x25, x25, x25 + la x1, _fsgnjx_jr26 + jalr x26, x1, 0 +_fsgnjx_jr26: fsgnjx.s x26, x26, x26 + la x1, _fsgnjx_jr27 + jalr x27, x1, 0 +_fsgnjx_jr27: fsgnjx.s x27, x27, x27 + la x1, _fsgnjx_jr28 + jalr x28, x1, 0 +_fsgnjx_jr28: fsgnjx.s x28, x28, x28 + la x1, _fsgnjx_jr29 + jalr x29, x1, 0 +_fsgnjx_jr29: fsgnjx.s x29, x29, x29 + la x1, _fsgnjx_jr30 + jalr x30, x1, 0 +_fsgnjx_jr30: fsgnjx.s x30, x30, x30 + la x1, _fsgnjx_jr31 + jalr x31, x1, 0 +_fsgnjx_jr31: fsgnjx.s x31, x31, x31 + + // 45 - custom_0 - rd0 + sw x1, 0(x1) + cv.lbu x0, (x1), 4 + fadd.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fdiv.s x1, x0, x0 + cv.lbu x0, (x1), 4 + feq.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fle.s x1, x0, x0 + cv.lbu x0, (x1), 4 + flt.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fmax.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fmin.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fmul.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fsgnjn.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fsgnj.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fsgnjx.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fsub.s x1, x0, x0 + cv.lbu x0, (x1), 4 + fmadd.s x1, x0, x0, x0 + cv.lbu x0, (x1), 4 + fmsub.s x1, x0, x0, x0 + cv.lbu x0, (x1), 4 + fnmadd.s x1, x0, x0, x0 + cv.lbu x0, (x1), 4 + fnmadd.s x1, x0, x0, x0 + cv.lbu x0, (x1), 4 + fnmsub.s x1, x0, x0, x0 + cv.lbu x0, (x1), 4 + fsqrt.s x1, x0 + cv.lbu x0, (x1), 4 + fcvt.s.w x1, x0 + cv.lbu x0, (x1), 4 + fcvt.wu.s x1, x0 + + // 46 - custom_1 - rd0 + cv.lbu x0, (x1), x0 + fnmsub.s x1, x0, x0, x0 + cv.lbu x0, (x1), x0 + fnmadd.s x1, x0, x0, x0 + + // 47 - + // 48 - + // 49 - + // 50 - + // (rs1, rs2, rs3) refer lines 1994-2057 + // (rs1, rs2, rs3) refer lines 2060-2155 + // (rs1, rs2) refer lines 26-89 + // (rs1, rs2) refer lines 92-187 + // (rs1) refer lines 190-253 + // (rs1) refer lines 256-351 + + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end + ######### FOR PULP_FPU CFG - END ######### + + li x18, TEST_PASS + +test_end: + li x17, VIRT_PERIPH_STATUS_FLAG_ADDR + sw x18,0(x17) + j _exit + +_exit: + j _exit +