From ae287d980558864868520f13442d9fc290dded33 Mon Sep 17 00:00:00 2001 From: adeel10x Date: Wed, 17 Jan 2024 19:15:35 +0500 Subject: [PATCH 1/2] This patch replaces __builtin_riscv_cv_bitmanip_ror with target independent __builtin_rotateright32. Consequently, the definitions of __builtin_riscv_cv_bitmanip_ror and the intrinsic int_riscv_cv_bitmanip_ror were removed, and relevant tests in clang and llvm were updated. --- clang/include/clang/Basic/BuiltinsRISCVCOREV.def | 1 - clang/lib/Headers/riscv_corev_bitmanip.h | 2 +- .../RISCV/corev-intrinsics/bitmanip-c-api.c | 2 +- .../CodeGen/RISCV/corev-intrinsics/bitmanip.c | 15 --------------- llvm/include/llvm/IR/IntrinsicsRISCV.td | 2 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 ++++++++------ llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td | 6 ++++-- llvm/test/CodeGen/RISCV/corev/bitmanip.ll | 4 ++-- 8 files changed, 16 insertions(+), 30 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def index 21f8ee9e0f16..720da442be3f 100644 --- a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def +++ b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def @@ -174,7 +174,6 @@ TARGET_BUILTIN(bitmanip_ff1, "UZcUZi", "nc", "xcvbitmanip") TARGET_BUILTIN(bitmanip_fl1, "UZcUZi", "nc", "xcvbitmanip") TARGET_BUILTIN(bitmanip_clb, "UZcUZi", "nc", "xcvbitmanip") TARGET_BUILTIN(bitmanip_cnt, "UZcUZi", "nc", "xcvbitmanip") -TARGET_BUILTIN(bitmanip_ror, "UZiUZiUZi", "nc", "xcvbitmanip") TARGET_BUILTIN(bitmanip_bitrev, "UZiUZiIUcIUc", "nc", "xcvbitmanip") TARGET_BUILTIN(mac_mac, "UZiUZiUZiUZi", "nc", "xcvmac") diff --git a/clang/lib/Headers/riscv_corev_bitmanip.h b/clang/lib/Headers/riscv_corev_bitmanip.h index b14c460fadf9..8bcdcd8bdde6 100644 --- a/clang/lib/Headers/riscv_corev_bitmanip.h +++ b/clang/lib/Headers/riscv_corev_bitmanip.h @@ -58,7 +58,7 @@ static __inline__ uint8_t __DEFAULT_FN_ATTRS __riscv_cv_bitmanip_cnt(unsigned lo } static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_bitmanip_ror(unsigned long a, unsigned long b) { - return __builtin_riscv_cv_bitmanip_ror(a, b); + return __builtin_rotateright32(a, b); } #define __riscv_cv_bitmanip_bitrev(rs1, PTS, RADIX) \ diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip-c-api.c b/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip-c-api.c index 96b1c335ef0f..435f4f92cbae 100644 --- a/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip-c-api.c +++ b/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip-c-api.c @@ -90,7 +90,7 @@ uint32_t test_cnt(uint32_t a) { } // CHECK-LABEL: @test_ror -// CHECK: @llvm.riscv.cv.bitmanip.ror +// CHECK: @llvm.fshr.i32 uint32_t test_ror(uint32_t a, uint32_t b) { return __riscv_cv_bitmanip_ror(a, b); } diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip.c b/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip.c index f6370b6dc29a..7278762694dd 100644 --- a/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip.c +++ b/clang/test/CodeGen/RISCV/corev-intrinsics/bitmanip.c @@ -199,21 +199,6 @@ uint32_t test_cnt(uint32_t a) { return __builtin_riscv_cv_bitmanip_cnt(a); } -// CHECK-LABEL: @test_ror( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.bitmanip.ror(i32 [[TMP0]], i32 [[TMP1]]) -// CHECK-NEXT: ret i32 [[TMP2]] -// -uint32_t test_ror(uint32_t a, uint32_t b) { - return __builtin_riscv_cv_bitmanip_ror(a, b); -} - // CHECK-LABEL: @test_bitrev( // CHECK-NEXT: entry: // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 10b5177df01c..2f45d27ddc74 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1730,8 +1730,6 @@ def int_riscv_cv_bitmanip_fl1 : ScalarCoreVBitManipGprIntrinsic; def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic; def int_riscv_cv_bitmanip_cnt : ScalarCoreVBitManipGprIntrinsic; -def int_riscv_cv_bitmanip_ror : ScalarCoreVBitManipGprGprIntrinsic; - def int_riscv_cv_bitmanip_bitrev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg>, ImmArg>]>; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index e67dd773210c..a40eea7aee56 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -272,13 +272,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, XLenVT, Custom); - if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) { - if (Subtarget.is64Bit()) - setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom); - } else { - setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand); + + if (!Subtarget.hasExtXcvbitmanip()) { + if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) { + if (Subtarget.is64Bit()) + setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom); + } else { + setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand); + } } - // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll // pattern match it directly in isel. setOperationAction(ISD::BSWAP, XLenVT, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td index a6d33e1079d4..c4ec99f39325 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td @@ -1222,8 +1222,10 @@ let Predicates = [HasExtXcvbitmanip, IsRV32] in { def : PatGpr; def : PatGpr; - def : PatGprGpr; - + //def : PatGprGpr; + def : Pat<(rotr i32:$rs1, i32:$rs2), + (CV_ROR GPR:$rs1, GPR:$rs2)>; + def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts, cv_tuimm2:$radix), (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>; } diff --git a/llvm/test/CodeGen/RISCV/corev/bitmanip.ll b/llvm/test/CodeGen/RISCV/corev/bitmanip.ll index 430a283dbb16..ee28e26dad0f 100644 --- a/llvm/test/CodeGen/RISCV/corev/bitmanip.ll +++ b/llvm/test/CodeGen/RISCV/corev/bitmanip.ll @@ -155,14 +155,14 @@ define i32 @test.cv.cnt(i32 %a) { ret i32 %1 } -declare i32 @llvm.riscv.cv.bitmanip.ror(i32, i32) +declare i32 @llvm.fshr.i32(i32, i32, i32) define i32 @test.cv.ror(i32 %a, i32 %b) { ; CHECK-LABEL: test.cv.ror: ; CHECK: # %bb.0: ; CHECK-NEXT: cv.ror a0, a0, a1 ; CHECK-NEXT: ret - %1 = call i32 @llvm.riscv.cv.bitmanip.ror(i32 %a, i32 %b) + %1 = call i32 @llvm.fshr.i32(i32 %a, i32 %a , i32 %b) ret i32 %1 } From 9024d063279370bf467b41b20cec70905a9f8692 Mon Sep 17 00:00:00 2001 From: adeel10x Date: Wed, 17 Jan 2024 20:13:11 +0500 Subject: [PATCH 2/2] Used PatGprGpr class to define instruction selection pattern for cv.ror. In previous patch, Pat class was used directly --- llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td index c4ec99f39325..7ba6294de016 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td @@ -1222,9 +1222,7 @@ let Predicates = [HasExtXcvbitmanip, IsRV32] in { def : PatGpr; def : PatGpr; - //def : PatGprGpr; - def : Pat<(rotr i32:$rs1, i32:$rs2), - (CV_ROR GPR:$rs1, GPR:$rs2)>; + def : PatGprGpr; def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts, cv_tuimm2:$radix), (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;