From c80a912cfad9f407e95a107aa1a9740a339ddddd Mon Sep 17 00:00:00 2001 From: Paolo Savini Date: Thu, 14 Dec 2023 17:49:04 +0000 Subject: [PATCH 1/2] [RISCV][Clang] Fix types of CORE-V simd Clang builtins. This patch fixes the types of simd CORE-V Clang builtins as per spec. The patch also adds the `I` qualifier to the immediate argument of extract[u]_[h,b] intrinsics so that clang errors when a variable is passed instead of letting the compiler crash later. The patch also updates the clang CoreGen test accordingly. --- .../clang/Basic/BuiltinsRISCVCOREV.def | 68 +++++++++---------- .../CodeGen/RISCV/corev-intrinsics/simd.c | 44 ++++++------ 2 files changed, 56 insertions(+), 56 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def index cefdb48110d6..21f8ee9e0f16 100644 --- a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def +++ b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def @@ -34,36 +34,36 @@ TARGET_BUILTIN(simd_avg_sc_h, "UZiUZiSs", "nc", "xcvsimd") TARGET_BUILTIN(simd_avg_sc_b, "UZiUZiSc", "nc", "xcvsimd") TARGET_BUILTIN(simd_avgu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_avgu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_avgu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_avgu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_avgu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_avgu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_min_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_min_b, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_min_sc_h, "UZiUZiSs", "nc", "xcvsimd") TARGET_BUILTIN(simd_min_sc_b, "UZiUZiSc", "nc", "xcvsimd") TARGET_BUILTIN(simd_minu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_minu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_minu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_minu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_minu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_minu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_max_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_max_b, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_max_sc_h, "UZiUZiSs", "nc", "xcvsimd") TARGET_BUILTIN(simd_max_sc_b, "UZiUZiSc", "nc", "xcvsimd") TARGET_BUILTIN(simd_maxu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_maxu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_maxu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_maxu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_maxu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_maxu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_srl_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_srl_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_srl_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_srl_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_srl_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_srl_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_sra_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sra_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sra_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sra_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sra_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sra_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_sll_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sll_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sll_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sll_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sll_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sll_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_or_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_or_b, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_or_sc_h, "UZiUZiSs", "nc", "xcvsimd") @@ -88,26 +88,26 @@ TARGET_BUILTIN(simd_dotusp_h, "ZiUZiSZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_dotusp_b, "ZiUZiSZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_dotusp_sc_h, "ZiUZiSs", "nc", "xcvsimd") TARGET_BUILTIN(simd_dotusp_sc_b, "ZiUZiSc", "nc", "xcvsimd") -TARGET_BUILTIN(simd_dotsp_h, "ZiSZiSZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_dotsp_b, "ZiSZiSZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_dotsp_sc_h, "ZiSZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_dotsp_sc_b, "ZiSZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_dotsp_h, "ZiUZiUZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_dotsp_b, "ZiUZiUZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_dotsp_sc_h, "ZiUZiSs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_dotsp_sc_b, "ZiUZiSc", "nc", "xcvsimd") TARGET_BUILTIN(simd_sdotup_h, "UZiUZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sdotup_b, "UZiUZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sdotup_sc_h, "UZiUZiUsUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sdotup_sc_b, "UZiUZiUcUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sdotusp_h, "ZiUZiSZiZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sdotusp_b, "ZiUZiSZiZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sdotusp_h, "ZiUZiUZiZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sdotusp_b, "ZiUZiUZiZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sdotusp_sc_h, "ZiUZiSsZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_sdotusp_sc_b, "ZiUZiScZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sdotsp_h, "ZiSZiSZiZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sdotsp_b, "ZiSZiSZiZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sdotsp_sc_h, "ZiSZiSsZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_sdotsp_sc_b, "ZiSZiScZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_extract_h, "ZiUZiUc", "nc", "xcvsimd") -TARGET_BUILTIN(simd_extract_b, "ZiUZiUc", "nc", "xcvsimd") -TARGET_BUILTIN(simd_extractu_h, "UZiUZiUc", "nc", "xcvsimd") -TARGET_BUILTIN(simd_extractu_b, "UZiUZiUc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sdotsp_h, "ZiUZiUZiZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sdotsp_b, "ZiUZiUZiZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sdotsp_sc_h, "ZiUZiSsZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_sdotsp_sc_b, "ZiUZiScZi", "nc", "xcvsimd") +TARGET_BUILTIN(simd_extract_h, "ZiUZiIUc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_extract_b, "ZiUZiIUc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_extractu_h, "UZiUZiIUc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_extractu_b, "UZiUZiIUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_insert_h, "UZiUZiUZiIUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_insert_b, "UZiUZiUZiIUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_shuffle_h, "UZiUZiUZi", "nc", "xcvsimd") @@ -146,20 +146,20 @@ TARGET_BUILTIN(simd_cmple_sc_h, "UZiUZiSs", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmple_sc_b, "UZiUZiSc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpgtu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpgtu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpgtu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpgtu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpgtu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpgtu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpgeu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpgeu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpgeu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpgeu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpgeu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpgeu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpltu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpltu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpltu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpltu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpltu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpltu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpleu_h, "UZiUZiUZi", "nc", "xcvsimd") TARGET_BUILTIN(simd_cmpleu_b, "UZiUZiUZi", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpleu_sc_h, "UZiUZiSs", "nc", "xcvsimd") -TARGET_BUILTIN(simd_cmpleu_sc_b, "UZiUZiSc", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpleu_sc_h, "UZiUZiUs", "nc", "xcvsimd") +TARGET_BUILTIN(simd_cmpleu_sc_b, "UZiUZiUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cplxmul_r, "UZiUZiUZiUZiIUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cplxmul_i, "UZiUZiUZiUZiIUc", "nc", "xcvsimd") TARGET_BUILTIN(simd_cplxconj, "UZiUZi", "nc", "xcvsimd") diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/simd.c b/clang/test/CodeGen/RISCV/corev-intrinsics/simd.c index c8ab9176a81a..638265f3ae60 100644 --- a/clang/test/CodeGen/RISCV/corev-intrinsics/simd.c +++ b/clang/test/CodeGen/RISCV/corev-intrinsics/simd.c @@ -462,7 +462,7 @@ uint32_t test_avgu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.avgu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -487,7 +487,7 @@ uint32_t test_avgu_sci_h(uint32_t a) { // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.avgu.sc.h(i32 [[TMP0]], i32 -32) +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.avgu.sc.h(i32 [[TMP0]], i32 65504) // CHECK-NEXT: ret i32 [[TMP1]] // uint32_t test_avgu_sci_h_negative(uint32_t a) { @@ -502,7 +502,7 @@ uint32_t test_avgu_sci_h_negative(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.avgu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -527,7 +527,7 @@ uint32_t test_avgu_sci_b(uint32_t a) { // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.avgu.sc.b(i32 [[TMP0]], i32 -32) +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.avgu.sc.b(i32 [[TMP0]], i32 224) // CHECK-NEXT: ret i32 [[TMP1]] // uint32_t test_avgu_sci_b_negative(uint32_t a) { @@ -682,7 +682,7 @@ uint32_t test_minu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.minu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -710,7 +710,7 @@ uint32_t test_minu_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.minu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -878,7 +878,7 @@ uint32_t test_maxu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.maxu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -906,7 +906,7 @@ uint32_t test_maxu_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.maxu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -964,7 +964,7 @@ uint32_t test_srl_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.srl.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -992,7 +992,7 @@ uint32_t test_srl_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.srl.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -1050,7 +1050,7 @@ uint32_t test_sra_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.sra.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -1078,7 +1078,7 @@ uint32_t test_sra_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.sra.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -1136,7 +1136,7 @@ uint32_t test_sll_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.sll.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -1164,7 +1164,7 @@ uint32_t test_sll_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.sll.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3306,7 +3306,7 @@ uint32_t test_cmpgtu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpgtu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3334,7 +3334,7 @@ uint32_t test_cmpgtu_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpgtu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3392,7 +3392,7 @@ uint32_t test_cmpgeu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpgeu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3420,7 +3420,7 @@ uint32_t test_cmpgeu_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpgeu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3478,7 +3478,7 @@ uint32_t test_cmpltu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpltu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3506,7 +3506,7 @@ uint32_t test_cmpltu_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpltu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3564,7 +3564,7 @@ uint32_t test_cmpleu_b(uint32_t a, uint32_t b) { // CHECK-NEXT: store i16 [[B:%.*]], ptr [[B_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2 -// CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpleu.sc.h(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // @@ -3592,7 +3592,7 @@ uint32_t test_cmpleu_sci_h(uint32_t a) { // CHECK-NEXT: store i8 [[B:%.*]], ptr [[B_ADDR]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[B_ADDR]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32 // CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.simd.cmpleu.sc.b(i32 [[TMP0]], i32 [[TMP2]]) // CHECK-NEXT: ret i32 [[TMP3]] // From 45dce63c329ef371a14d6ab4ed3b45ae9a53e17b Mon Sep 17 00:00:00 2001 From: Paolo Savini Date: Thu, 14 Dec 2023 18:20:14 +0000 Subject: [PATCH 2/2] [RISCV][Clang] Add C API header for simd CORE-V intrinsics. This commit adds the C API header to serve as an interface for the intrinsic functions provided with the CORE-V xcvsimd extension. The commit includes the addition of the header itself and a clang CodeGen test that checks the integrity of the call to the wrapper functions designed in the C API CORE-V simd header. --- clang/lib/Headers/CMakeLists.txt | 1 + clang/lib/Headers/riscv_corev_simd.h | 615 +++++++++ .../RISCV/corev-intrinsics/simd-c-api.c | 1206 +++++++++++++++++ 3 files changed, 1822 insertions(+) create mode 100644 clang/lib/Headers/riscv_corev_simd.h create mode 100644 clang/test/CodeGen/RISCV/corev-intrinsics/simd-c-api.c diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index 0fcd3cd8e4f2..494c3b707496 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -97,6 +97,7 @@ set(riscv_files riscv_corev_bitmanip.h riscv_corev_elw.h riscv_corev_mac.h + riscv_corev_simd.h ) set(systemz_files diff --git a/clang/lib/Headers/riscv_corev_simd.h b/clang/lib/Headers/riscv_corev_simd.h new file mode 100644 index 000000000000..7612203087bd --- /dev/null +++ b/clang/lib/Headers/riscv_corev_simd.h @@ -0,0 +1,615 @@ +/*===---- riscv_corev_simd.h - CORE-V SIMD intrinsics ----------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __RISCV_COREV_SIMD_H +#define __RISCV_COREV_SIMD_H + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(__riscv_xcvsimd) + +#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__)) + +#define __riscv_cv_simd_add_h(rs1, rs2, DIV) \ + (unsigned long) __builtin_riscv_cv_simd_add_h((unsigned long) (rs1), \ + (unsigned long) (rs2), (const uint8_t) (DIV)) + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_add_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_add_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_add_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_add_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_add_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_add_sc_b(a, b); +} + +#define __riscv_cv_simd_sub_h(rs1, rs2, DIV) \ + (unsigned long) __builtin_riscv_cv_simd_sub_h((unsigned long) (rs1), \ + (unsigned long) (rs2), (const uint8_t) (DIV)) + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sub_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_sub_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sub_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_sub_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sub_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_sub_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avg_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_avg_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avg_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_avg_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avg_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_avg_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avg_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_avg_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avgu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_avgu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avgu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_avgu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avgu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_avgu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_avgu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_avgu_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_min_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_min_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_min_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_min_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_min_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_min_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_min_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_min_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_minu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_minu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_minu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_minu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_minu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_minu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_minu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_minu_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_max_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_max_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_max_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_max_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_max_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_max_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_max_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_max_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_maxu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_maxu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_maxu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_maxu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_maxu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_maxu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_maxu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_maxu_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_srl_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_srl_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_srl_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_srl_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_srl_sc_h(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_srl_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_srl_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_srl_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sra_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_sra_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sra_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_sra_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sra_sc_h(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_sra_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sra_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_sra_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sll_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_sll_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sll_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_sll_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sll_sc_h(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_sll_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sll_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_sll_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_or_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_or_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_or_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_or_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_or_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_or_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_or_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_or_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_xor_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_xor_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_xor_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_xor_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_xor_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_xor_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_xor_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_xor_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_and_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_and_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_and_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_and_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_and_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_and_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_and_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_and_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_abs_h(unsigned long a) { + return __builtin_riscv_cv_simd_abs_h(a); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_abs_b(unsigned long a) { + return __builtin_riscv_cv_simd_abs_b(a); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_neg_h(unsigned long a) { + return __builtin_riscv_cv_simd_neg_h(a); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_neg_b(unsigned long a) { + return __builtin_riscv_cv_simd_neg_b(a); +} + +#define __riscv_cv_simd_extract_h(rs1, SEL) \ + (unsigned long) __builtin_riscv_cv_simd_extract_h((unsigned long) (rs1), \ + (const uint8_t) (SEL)) + +#define __riscv_cv_simd_extract_b(rs1, SEL) \ + (unsigned long) __builtin_riscv_cv_simd_extract_b((unsigned long) (rs1), \ + (const uint8_t) (SEL)) + +#define __riscv_cv_simd_extractu_h(rs1, SEL) \ + (unsigned long) __builtin_riscv_cv_simd_extractu_h((unsigned long) (rs1), \ + (const uint8_t) (SEL)) + +#define __riscv_cv_simd_extractu_b(rs1, SEL) \ + (unsigned long) __builtin_riscv_cv_simd_extractu_b((unsigned long) (rs1), \ + (const uint8_t) (SEL)) + +#define __riscv_cv_simd_insert_h(rs1, rs2, SEL) \ + (unsigned long) __builtin_riscv_cv_simd_insert_h((unsigned long) (rs1), \ + (unsigned long) (rs2), (const uint8_t) (SEL)) + +#define __riscv_cv_simd_insert_b(rs1, rs2, SEL) \ + (unsigned long) __builtin_riscv_cv_simd_insert_b((unsigned long) (rs1), \ + (unsigned long) (rs2), (const uint8_t) (SEL)) + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotup_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_dotup_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotup_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_dotup_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotup_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_dotup_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotup_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_dotup_sc_b(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotusp_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_dotusp_h(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotusp_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_dotusp_b(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotusp_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_dotusp_sc_h(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotusp_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_dotusp_sc_b(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotsp_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_dotsp_h(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotsp_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_dotsp_b(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotsp_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_dotsp_sc_h(a, b); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_dotsp_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_dotsp_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotup_h(unsigned long a, unsigned long b, + unsigned long c) { + return __builtin_riscv_cv_simd_sdotup_h(a, b, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotup_b(unsigned long a, unsigned long b, + unsigned long c) { + return __builtin_riscv_cv_simd_sdotup_b(a, b, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotup_sc_h(unsigned long a, uint16_t b, + unsigned long c) { + return __builtin_riscv_cv_simd_sdotup_sc_h(a, b, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotup_sc_b(unsigned long a, uint8_t b, + unsigned long c) { + return __builtin_riscv_cv_simd_sdotup_sc_b(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotusp_h(unsigned long a, unsigned long b, long c) { + return __builtin_riscv_cv_simd_sdotusp_h(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotusp_b(unsigned long a, unsigned long b, long c) { + return __builtin_riscv_cv_simd_sdotusp_b(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotusp_sc_h(unsigned long a, int16_t b, long c) { + return __builtin_riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotusp_sc_b(unsigned long a, int8_t b, long c) { + return __builtin_riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotsp_h(unsigned long a, unsigned long b, long c) { + return __builtin_riscv_cv_simd_sdotsp_h(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotsp_b(unsigned long a, unsigned long b, long c) { + return __builtin_riscv_cv_simd_sdotsp_b(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotsp_sc_h(unsigned long a, int16_t b, long c) { + return __builtin_riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + +static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_simd_sdotsp_sc_b(unsigned long a, int8_t b, long c) { + return __builtin_riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_shuffle_h(unsigned long a, unsigned long flgs) { + return __builtin_riscv_cv_simd_shuffle_h(a, flgs); +} + +#define __riscv_cv_simd_shuffle_sci_h(rs1, FLGS) \ + (unsigned long) __builtin_riscv_cv_simd_shuffle_sci_h((unsigned long) (rs1), \ + (const uint8_t) (FLGS)) + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_shuffle_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_shuffle_b(a, b); +} + +#define __riscv_cv_simd_shuffle_sci_b(rs1, FLGS) \ + (unsigned long) __builtin_riscv_cv_simd_shuffle_sci_b((unsigned long) (rs1), \ + (const uint8_t) (FLGS)) + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_shuffle2_h(unsigned long a, unsigned long flgs, + unsigned long c) { + return __builtin_riscv_cv_simd_shuffle2_h(a, flgs, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_shuffle2_b(unsigned long a, unsigned long flgs, + unsigned long c) { + return __builtin_riscv_cv_simd_shuffle2_b(a, flgs, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_packhi_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_packhi_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_packlo_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_packlo_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_packhi_b(unsigned long a, unsigned long b, + unsigned long c) { + return __builtin_riscv_cv_simd_packhi_b(a, b, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_packlo_b(unsigned long a, unsigned long b, + unsigned long c) { + return __builtin_riscv_cv_simd_packlo_b(a, b, c); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpeq_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpeq_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpeq_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpeq_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpeq_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_cmpeq_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpeq_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_cmpeq_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpne_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpne_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpne_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpne_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpne_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_cmpne_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpne_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_cmpne_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgt_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpgt_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgt_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpgt_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgt_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_cmpgt_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgt_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_cmpgt_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpge_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpge_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpge_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpge_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpge_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_cmpge_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpge_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_cmpge_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmplt_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmplt_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmplt_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmplt_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmplt_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_cmplt_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmplt_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_cmplt_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmple_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmple_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmple_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmple_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmple_sc_h(unsigned long a, int16_t b) { + return __builtin_riscv_cv_simd_cmple_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmple_sc_b(unsigned long a, int8_t b) { + return __builtin_riscv_cv_simd_cmple_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgtu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpgtu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgtu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpgtu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgtu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_cmpgtu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgtu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_cmpgtu_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgeu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpgeu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgeu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpgeu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgeu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_cmpgeu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpgeu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_cmpgeu_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpltu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpltu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpltu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpltu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpltu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_cmpltu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpltu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_cmpltu_sc_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpleu_h(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpleu_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpleu_b(unsigned long a, unsigned long b) { + return __builtin_riscv_cv_simd_cmpleu_b(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpleu_sc_h(unsigned long a, uint16_t b) { + return __builtin_riscv_cv_simd_cmpleu_sc_h(a, b); +} + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cmpleu_sc_b(unsigned long a, uint8_t b) { + return __builtin_riscv_cv_simd_cmpleu_sc_b(a, b); +} + +#define __riscv_cv_simd_cplxmul_r(rs1, rs2, rD, DIV) \ + (unsigned long) __builtin_riscv_cv_simd_cplxmul_r((unsigned long) (rs1), \ + (unsigned long) (rs2), (unsigned long) (rD), \ + (const uint8_t) (DIV)) + +#define __riscv_cv_simd_cplxmul_i(rs1, rs2, rD, DIV) \ + (unsigned long) __builtin_riscv_cv_simd_cplxmul_i((unsigned long) (rs1), \ + (unsigned long) (rs2), (unsigned long) (rD), \ + (const uint8_t) (DIV)) + +static __inline__ unsigned long __DEFAULT_FN_ATTRS __riscv_cv_simd_cplxconj(unsigned long a) { + return __builtin_riscv_cv_simd_cplxconj(a); +} + +#define __riscv_cv_simd_subrotmj(rs1, rs2, DIV) \ + (unsigned long) __builtin_riscv_cv_simd_subrotmj((unsigned long) (rs1), \ + (unsigned long) (rs2), (const uint8_t) (DIV)) + +#endif // defined(__riscv_xcvsimd) + +#if defined(__cplusplus) +} +#endif + +#endif // define __RISCV_COREV_SIMD_H diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/simd-c-api.c b/clang/test/CodeGen/RISCV/corev-intrinsics/simd-c-api.c new file mode 100644 index 000000000000..f80adf812684 --- /dev/null +++ b/clang/test/CodeGen/RISCV/corev-intrinsics/simd-c-api.c @@ -0,0 +1,1206 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvsimd -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include +#include + +// CHECK-LABEL: @test_add_h +// CHECK: @llvm.riscv.cv.simd.add.h +uint32_t test_add_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_add_h(a, b, 0); +} + +// CHECK-LABEL: @test_add_b +// CHECK: @llvm.riscv.cv.simd.add.b +uint32_t test_add_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_add_b(a, b); +} + +// CHECK-LABEL: @test_add_sc_h +// CHECK: @llvm.riscv.cv.simd.add.sc.h +uint32_t test_add_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_add_sc_h(a, b); +} + +// CHECK-LABEL: @test_add_sci_h +// CHECK: @llvm.riscv.cv.simd.add.sc.h +uint32_t test_add_sci_h(uint32_t a) { + return __riscv_cv_simd_add_sc_h(a, 0); +} + +// CHECK-LABEL: @test_add_sc_b +// CHECK: @llvm.riscv.cv.simd.add.sc.b +uint32_t test_add_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_add_sc_b(a, b); +} + +// CHECK-LABEL: @test_add_sci_b +// CHECK: @llvm.riscv.cv.simd.add.sc.b +uint32_t test_add_sci_b(uint32_t a) { + return __riscv_cv_simd_add_sc_b(a, 0); +} + +// CHECK-LABEL: @test_sub_h +// CHECK: @llvm.riscv.cv.simd.sub.h +uint32_t test_sub_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_sub_h(a, b, 0); +} + +// CHECK-LABEL: @test_sub_b +// CHECK: @llvm.riscv.cv.simd.sub.b +uint32_t test_sub_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_sub_b(a, b); +} + +// CHECK-LABEL: @test_sub_sc_h +// CHECK: @llvm.riscv.cv.simd.sub.sc.h +uint32_t test_sub_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_sub_sc_h(a, b); +} + +// CHECK-LABEL: @test_sub_sci_h +// CHECK: @llvm.riscv.cv.simd.sub.sc.h +uint32_t test_sub_sci_h(uint32_t a) { + return __riscv_cv_simd_sub_sc_h(a, 0); +} + +// CHECK-LABEL: @test_sub_sc_b +// CHECK: @llvm.riscv.cv.simd.sub.sc.b +uint32_t test_sub_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_sub_sc_b(a, b); +} + +// CHECK-LABEL: @test_sub_sci_b +// CHECK: @llvm.riscv.cv.simd.sub.sc.b +uint32_t test_sub_sci_b(uint32_t a) { + return __riscv_cv_simd_sub_sc_b(a, 0); +} + +// CHECK-LABEL: @test_avg_h +// CHECK: @llvm.riscv.cv.simd.avg.h +uint32_t test_avg_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_avg_h(a, b); +} + +// CHECK-LABEL: @test_avg_b +// CHECK: @llvm.riscv.cv.simd.avg.b +uint32_t test_avg_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_avg_b(a, b); +} + +// CHECK-LABEL: @test_avg_sc_h +// CHECK: @llvm.riscv.cv.simd.avg.sc.h +uint32_t test_avg_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_avg_sc_h(a, b); +} + +// CHECK-LABEL: @test_avg_sci_h +// CHECK: @llvm.riscv.cv.simd.avg.sc.h +uint32_t test_avg_sci_h(uint32_t a) { + return __riscv_cv_simd_avg_sc_h(a, 0); +} + +// CHECK-LABEL: @test_avg_sc_b +// CHECK: @llvm.riscv.cv.simd.avg.sc.b +uint32_t test_avg_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_avg_sc_b(a, b); +} + +// CHECK-LABEL: @test_avg_sci_b +// CHECK: @llvm.riscv.cv.simd.avg.sc.b +uint32_t test_avg_sci_b(uint32_t a) { + return __riscv_cv_simd_avg_sc_b(a, 0); +} + +// CHECK-LABEL: @test_avgu_h +// CHECK: @llvm.riscv.cv.simd.avgu.h +uint32_t test_avgu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_avgu_h(a, b); +} + +// CHECK-LABEL: @test_avgu_b +// CHECK: @llvm.riscv.cv.simd.avgu.b +uint32_t test_avgu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_avgu_b(a, b); +} + +// CHECK-LABEL: @test_avgu_sc_h +// CHECK: @llvm.riscv.cv.simd.avgu.sc.h +uint32_t test_avgu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_avgu_sc_h(a, b); +} + +// CHECK-LABEL: @test_avgu_sci_h +// CHECK: @llvm.riscv.cv.simd.avgu.sc.h +uint32_t test_avgu_sci_h(uint32_t a) { + return __riscv_cv_simd_avgu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_avgu_sc_b +// CHECK: @llvm.riscv.cv.simd.avgu.sc.b +uint32_t test_avgu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_avgu_sc_b(a, b); +} + +// CHECK-LABEL: @test_avgu_sci_b +// CHECK: @llvm.riscv.cv.simd.avgu.sc.b +uint32_t test_avgu_sci_b(uint32_t a) { + return __riscv_cv_simd_avgu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_min_h +// CHECK: @llvm.riscv.cv.simd.min.h +uint32_t test_min_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_min_h(a, b); +} + +// CHECK-LABEL: @test_min_b +// CHECK: @llvm.riscv.cv.simd.min.b +uint32_t test_min_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_min_b(a, b); +} + +// CHECK-LABEL: @test_min_sc_h +// CHECK: @llvm.riscv.cv.simd.min.sc.h +uint32_t test_min_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_min_sc_h(a, b); +} + +// CHECK-LABEL: @test_min_sci_h +// CHECK: @llvm.riscv.cv.simd.min.sc.h +uint32_t test_min_sci_h(uint32_t a) { + return __riscv_cv_simd_min_sc_h(a, 0); +} + +// CHECK-LABEL: @test_min_sc_b +// CHECK: @llvm.riscv.cv.simd.min.sc.b +uint32_t test_min_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_min_sc_b(a, b); +} + +// CHECK-LABEL: @test_min_sci_b +// CHECK: @llvm.riscv.cv.simd.min.sc.b +uint32_t test_min_sci_b(uint32_t a) { + return __riscv_cv_simd_min_sc_b(a, 0); +} + +// CHECK-LABEL: @test_minu_h +// CHECK: @llvm.riscv.cv.simd.minu.h +uint32_t test_minu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_minu_h(a, b); +} + +// CHECK-LABEL: @test_minu_b +// CHECK: @llvm.riscv.cv.simd.minu.b +uint32_t test_minu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_minu_b(a, b); +} + +// CHECK-LABEL: @test_minu_sc_h +// CHECK: @llvm.riscv.cv.simd.minu.sc.h +uint32_t test_minu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_minu_sc_h(a, b); +} + +// CHECK-LABEL: @test_minu_sci_h +// CHECK: @llvm.riscv.cv.simd.minu.sc.h +uint32_t test_minu_sci_h(uint32_t a) { + return __riscv_cv_simd_minu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_minu_sc_b +// CHECK: @llvm.riscv.cv.simd.minu.sc.b +uint32_t test_minu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_minu_sc_b(a, b); +} + +// CHECK-LABEL: @test_minu_sci_b +// CHECK: @llvm.riscv.cv.simd.minu.sc.b +uint32_t test_minu_sci_b(uint32_t a) { + return __riscv_cv_simd_minu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_max_h +// CHECK: @llvm.riscv.cv.simd.max.h +uint32_t test_max_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_max_h(a, b); +} + +// CHECK-LABEL: @test_max_b +// CHECK: @llvm.riscv.cv.simd.max.b +uint32_t test_max_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_max_b(a, b); +} + +// CHECK-LABEL: @test_max_sc_h +// CHECK: @llvm.riscv.cv.simd.max.sc.h +uint32_t test_max_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_max_sc_h(a, b); +} + +// CHECK-LABEL: @test_max_sci_h +// CHECK: @llvm.riscv.cv.simd.max.sc.h +uint32_t test_max_sci_h(uint32_t a) { + return __riscv_cv_simd_max_sc_h(a, 0); +} + +// CHECK-LABEL: @test_max_sc_b +// CHECK: @llvm.riscv.cv.simd.max.sc.b +uint32_t test_max_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_max_sc_b(a, b); +} + +// CHECK-LABEL: @test_max_sci_b +// CHECK: @llvm.riscv.cv.simd.max.sc.b +uint32_t test_max_sci_b(uint32_t a) { + return __riscv_cv_simd_max_sc_b(a, 0); +} + +// CHECK-LABEL: @test_maxu_h +// CHECK: @llvm.riscv.cv.simd.maxu.h +uint32_t test_maxu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_maxu_h(a, b); +} + +// CHECK-LABEL: @test_maxu_b +// CHECK: @llvm.riscv.cv.simd.maxu.b +uint32_t test_maxu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_maxu_b(a, b); +} + +// CHECK-LABEL: @test_maxu_sc_h +// CHECK: @llvm.riscv.cv.simd.maxu.sc.h +uint32_t test_maxu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_maxu_sc_h(a, b); +} + +// CHECK-LABEL: @test_maxu_sci_h +// CHECK: @llvm.riscv.cv.simd.maxu.sc.h +uint32_t test_maxu_sci_h(uint32_t a) { + return __riscv_cv_simd_maxu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_maxu_sc_b +// CHECK: @llvm.riscv.cv.simd.maxu.sc.b +uint32_t test_maxu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_maxu_sc_b(a, b); +} + +// CHECK-LABEL: @test_maxu_sci_b +// CHECK: @llvm.riscv.cv.simd.maxu.sc.b +uint32_t test_maxu_sci_b(uint32_t a) { + return __riscv_cv_simd_maxu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_srl_h +// CHECK: @llvm.riscv.cv.simd.srl.h +uint32_t test_srl_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_srl_h(a, b); +} + +// CHECK-LABEL: @test_srl_b +// CHECK: @llvm.riscv.cv.simd.srl.b +uint32_t test_srl_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_srl_b(a, b); +} + +// CHECK-LABEL: @test_srl_sc_h +// CHECK: @llvm.riscv.cv.simd.srl.sc.h +uint32_t test_srl_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_srl_sc_h(a, b); +} + +// CHECK-LABEL: @test_srl_sci_h +// CHECK: @llvm.riscv.cv.simd.srl.sc.h +uint32_t test_srl_sci_h(uint32_t a) { + return __riscv_cv_simd_srl_sc_h(a, 0); +} + +// CHECK-LABEL: @test_srl_sc_b +// CHECK: @llvm.riscv.cv.simd.srl.sc.b +uint32_t test_srl_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_srl_sc_b(a, b); +} + +// CHECK-LABEL: @test_srl_sci_b +// CHECK: @llvm.riscv.cv.simd.srl.sc.b +uint32_t test_srl_sci_b(uint32_t a) { + return __riscv_cv_simd_srl_sc_b(a, 0); +} + +// CHECK-LABEL: @test_sra_h +// CHECK: @llvm.riscv.cv.simd.sra.h +uint32_t test_sra_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_sra_h(a, b); +} + +// CHECK-LABEL: @test_sra_b +// CHECK: @llvm.riscv.cv.simd.sra.b +uint32_t test_sra_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_sra_b(a, b); +} + +// CHECK-LABEL: @test_sra_sc_h +// CHECK: @llvm.riscv.cv.simd.sra.sc.h +uint32_t test_sra_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_sra_sc_h(a, b); +} + +// CHECK-LABEL: @test_sra_sci_h +// CHECK: @llvm.riscv.cv.simd.sra.sc.h +uint32_t test_sra_sci_h(uint32_t a) { + return __riscv_cv_simd_sra_sc_h(a, 0); +} + +// CHECK-LABEL: @test_sra_sc_b +// CHECK: @llvm.riscv.cv.simd.sra.sc.b +uint32_t test_sra_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_sra_sc_b(a, b); +} + +// CHECK-LABEL: @test_sra_sci_b +// CHECK: @llvm.riscv.cv.simd.sra.sc.b +uint32_t test_sra_sci_b(uint32_t a) { + return __riscv_cv_simd_sra_sc_b(a, 0); +} + +// CHECK-LABEL: @test_sll_h +// CHECK: @llvm.riscv.cv.simd.sll.h +uint32_t test_sll_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_sll_h(a, b); +} + +// CHECK-LABEL: @test_sll_b +// CHECK: @llvm.riscv.cv.simd.sll.b +uint32_t test_sll_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_sll_b(a, b); +} + +// CHECK-LABEL: @test_sll_sc_h +// CHECK: @llvm.riscv.cv.simd.sll.sc.h +uint32_t test_sll_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_sll_sc_h(a, b); +} + +// CHECK-LABEL: @test_sll_sci_h +// CHECK: @llvm.riscv.cv.simd.sll.sc.h +uint32_t test_sll_sci_h(uint32_t a) { + return __riscv_cv_simd_sll_sc_h(a, 0); +} + +// CHECK-LABEL: @test_sll_sc_b +// CHECK: @llvm.riscv.cv.simd.sll.sc.b +uint32_t test_sll_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_sll_sc_b(a, b); +} + +// CHECK-LABEL: @test_sll_sci_b +// CHECK: @llvm.riscv.cv.simd.sll.sc.b +uint32_t test_sll_sci_b(uint32_t a) { + return __riscv_cv_simd_sll_sc_b(a, 0); +} + +// CHECK-LABEL: @test_or_h +// CHECK: @llvm.riscv.cv.simd.or.h +uint32_t test_or_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_or_h(a, b); +} + +// CHECK-LABEL: @test_or_b +// CHECK: @llvm.riscv.cv.simd.or.b +uint32_t test_or_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_or_b(a, b); +} + +// CHECK-LABEL: @test_or_sc_h +// CHECK: @llvm.riscv.cv.simd.or.sc.h +uint32_t test_or_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_or_sc_h(a, b); +} + +// CHECK-LABEL: @test_or_sci_h +// CHECK: @llvm.riscv.cv.simd.or.sc.h +uint32_t test_or_sci_h(uint32_t a) { + return __riscv_cv_simd_or_sc_h(a, 0); +} + +// CHECK-LABEL: @test_or_sc_b +// CHECK: @llvm.riscv.cv.simd.or.sc.b +uint32_t test_or_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_or_sc_b(a, b); +} + +// CHECK-LABEL: @test_or_sci_b +// CHECK: @llvm.riscv.cv.simd.or.sc.b +uint32_t test_or_sci_b(uint32_t a) { + return __riscv_cv_simd_or_sc_b(a, 0); +} + +// CHECK-LABEL: @test_xor_h +// CHECK: @llvm.riscv.cv.simd.xor.h +uint32_t test_xor_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_xor_h(a, b); +} + +// CHECK-LABEL: @test_xor_b +// CHECK: @llvm.riscv.cv.simd.xor.b +uint32_t test_xor_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_xor_b(a, b); +} + +// CHECK-LABEL: @test_xor_sc_h +// CHECK: @llvm.riscv.cv.simd.xor.sc.h +uint32_t test_xor_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_xor_sc_h(a, b); +} + +// CHECK-LABEL: @test_xor_sci_h +// CHECK: @llvm.riscv.cv.simd.xor.sc.h +uint32_t test_xor_sci_h(uint32_t a) { + return __riscv_cv_simd_xor_sc_h(a, 0); +} + +// CHECK-LABEL: @test_xor_sc_b +// CHECK: @llvm.riscv.cv.simd.xor.sc.b +uint32_t test_xor_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_xor_sc_b(a, b); +} + +// CHECK-LABEL: @test_xor_sci_b +// CHECK: @llvm.riscv.cv.simd.xor.sc.b +uint32_t test_xor_sci_b(uint32_t a) { + return __riscv_cv_simd_xor_sc_b(a, 0); +} + +// CHECK-LABEL: @test_and_h +// CHECK: @llvm.riscv.cv.simd.and.h +uint32_t test_and_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_and_h(a, b); +} + +// CHECK-LABEL: @test_and_b +// CHECK: @llvm.riscv.cv.simd.and.b +uint32_t test_and_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_and_b(a, b); +} + +// CHECK-LABEL: @test_and_sc_h +// CHECK: @llvm.riscv.cv.simd.and.sc.h +uint32_t test_and_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_and_sc_h(a, b); +} + +// CHECK-LABEL: @test_and_sci_h +// CHECK: @llvm.riscv.cv.simd.and.sc.h +uint32_t test_and_sci_h(uint32_t a) { + return __riscv_cv_simd_and_sc_h(a, 0); +} + +// CHECK-LABEL: @test_and_sc_b +// CHECK: @llvm.riscv.cv.simd.and.sc.b +uint32_t test_and_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_and_sc_b(a, b); +} + +// CHECK-LABEL: @test_and_sci_b +// CHECK: @llvm.riscv.cv.simd.and.sc.b +uint32_t test_and_sci_b(uint32_t a) { + return __riscv_cv_simd_and_sc_b(a, 0); +} + +// CHECK-LABEL: @test_abs_h +// CHECK: @llvm.riscv.cv.simd.abs.h +uint32_t test_abs_h(uint32_t a) { + return __riscv_cv_simd_abs_h(a); +} + +// CHECK-LABEL: @test_abs_b +// CHECK: @llvm.riscv.cv.simd.abs.b +uint32_t test_abs_b(uint32_t a) { + return __riscv_cv_simd_abs_b(a); +} + +// CHECK-LABEL: @test_neg_h +// CHECK: @llvm.riscv.cv.simd.sub.h +uint32_t test_neg_h(uint32_t a) { + return __riscv_cv_simd_neg_h(a); +} + +// CHECK-LABEL: @test_neg_b +// CHECK: @llvm.riscv.cv.simd.sub.b +uint32_t test_neg_b(uint32_t a) { + return __riscv_cv_simd_neg_b(a); +} + +// CHECK-LABEL: @test_dotup_h +// CHECK: @llvm.riscv.cv.simd.dotup.h +uint32_t test_dotup_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_dotup_h(a, b); +} + +// CHECK-LABEL: @test_dotup_b +// CHECK: @llvm.riscv.cv.simd.dotup.b +uint32_t test_dotup_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_dotup_b(a, b); +} + +// CHECK-LABEL: @test_dotup_sc_h +// CHECK: @llvm.riscv.cv.simd.dotup.sc.h +uint32_t test_dotup_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_dotup_sc_h(a, b); +} + +// CHECK-LABEL: @test_dotup_sci_h +// CHECK: @llvm.riscv.cv.simd.dotup.sc.h +uint32_t test_dotup_sci_h(uint32_t a) { + return __riscv_cv_simd_dotup_sc_h(a, 0); +} + +// CHECK-LABEL: @test_dotup_sc_b +// CHECK: @llvm.riscv.cv.simd.dotup.sc.b +uint32_t test_dotup_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_dotup_sc_b(a, b); +} + +// CHECK-LABEL: @test_dotup_sci_b +// CHECK: @llvm.riscv.cv.simd.dotup.sc.b +uint32_t test_dotup_sci_b(uint32_t a) { + return __riscv_cv_simd_dotup_sc_b(a, 0); +} + +// CHECK-LABEL: @test_dotusp_h +// CHECK: @llvm.riscv.cv.simd.dotusp.h +uint32_t test_dotusp_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_dotusp_h(a, b); +} + +// CHECK-LABEL: @test_dotusp_b +// CHECK: @llvm.riscv.cv.simd.dotusp.b +uint32_t test_dotusp_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_dotusp_b(a, b); +} + +// CHECK-LABEL: @test_dotusp_sc_h +// CHECK: @llvm.riscv.cv.simd.dotusp.sc.h +uint32_t test_dotusp_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_dotusp_sc_h(a, b); +} + +// CHECK-LABEL: @test_dotusp_sci_h +// CHECK: @llvm.riscv.cv.simd.dotusp.sc.h +uint32_t test_dotusp_sci_h(uint32_t a) { + return __riscv_cv_simd_dotusp_sc_h(a, 0); +} + +// CHECK-LABEL: @test_dotusp_sc_b +// CHECK: @llvm.riscv.cv.simd.dotusp.sc.b +uint32_t test_dotusp_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_dotusp_sc_b(a, b); +} + +// CHECK-LABEL: @test_dotusp_sci_b +// CHECK: @llvm.riscv.cv.simd.dotusp.sc.b +uint32_t test_dotusp_sci_b(uint32_t a) { + return __riscv_cv_simd_dotusp_sc_b(a, 0); +} + +// CHECK-LABEL: @test_dotsp_h +// CHECK: @llvm.riscv.cv.simd.dotsp.h +uint32_t test_dotsp_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_dotsp_h(a, b); +} + +// CHECK-LABEL: @test_dotsp_b +// CHECK: @llvm.riscv.cv.simd.dotsp.b +uint32_t test_dotsp_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_dotsp_b(a, b); +} + +// CHECK-LABEL: @test_dotsp_sc_h +// CHECK: @llvm.riscv.cv.simd.dotsp.sc.h +uint32_t test_dotsp_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_dotsp_sc_h(a, b); +} + +// CHECK-LABEL: @test_dotsp_sci_h +// CHECK: @llvm.riscv.cv.simd.dotsp.sc.h +uint32_t test_dotsp_sci_h(uint32_t a) { + return __riscv_cv_simd_dotsp_sc_h(a, 0); +} + +// CHECK-LABEL: @test_dotsp_sc_b +// CHECK: @llvm.riscv.cv.simd.dotsp.sc.b +uint32_t test_dotsp_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_dotsp_sc_b(a, b); +} + +// CHECK-LABEL: @test_dotsp_sci_b +// CHECK: @llvm.riscv.cv.simd.dotsp.sc.b +uint32_t test_dotsp_sci_b(uint32_t a) { + return __riscv_cv_simd_dotsp_sc_b(a, 0); +} + +// CHECK-LABEL: @test_sdotup_h +// CHECK: @llvm.riscv.cv.simd.sdotup.h +uint32_t test_sdotup_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotup_h(a, b, c); +} + +// CHECK-LABEL: @test_sdotup_b +// CHECK: @llvm.riscv.cv.simd.sdotup.b +uint32_t test_sdotup_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotup_b(a, b, c); +} + +// CHECK-LABEL: @test_sdotup_sc_h +// CHECK: @llvm.riscv.cv.simd.sdotup.sc.h +uint32_t test_sdotup_sc_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotup_sc_h(a, b, c); +} + +// CHECK-LABEL: @test_sdotup_sci_h +// CHECK: @llvm.riscv.cv.simd.sdotup.sc.h +uint32_t test_sdotup_sci_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_sdotup_sc_h(a, 0, b); +} + +// CHECK-LABEL: @test_sdotup_sc_b +// CHECK: @llvm.riscv.cv.simd.sdotup.sc.b +uint32_t test_sdotup_sc_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotup_sc_b(a, b, c); +} + +// CHECK-LABEL: @test_sdotup_sci_b +// CHECK: @llvm.riscv.cv.simd.sdotup.sc.b +uint32_t test_sdotup_sci_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_sdotup_sc_b(a, 0, b); +} + +// CHECK-LABEL: @test_sdotusp_h +// CHECK: @llvm.riscv.cv.simd.sdotusp.h +uint32_t test_sdotusp_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotusp_h(a, b, c); +} + +// CHECK-LABEL: @test_sdotusp_b +// CHECK: @llvm.riscv.cv.simd.sdotusp.b +uint32_t test_sdotusp_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotusp_b(a, b, c); +} + +// CHECK-LABEL: @test_sdotusp_sc_h +// CHECK: @llvm.riscv.cv.simd.sdotusp.sc.h +uint32_t test_sdotusp_sc_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotusp_sc_h(a, b, c); +} + +// CHECK-LABEL: @test_sdotusp_sci_h +// CHECK: @llvm.riscv.cv.simd.sdotusp.sc.h +uint32_t test_sdotusp_sci_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_sdotusp_sc_h(a, 0, b); +} + +// CHECK-LABEL: @test_sdotusp_sc_b +// CHECK: @llvm.riscv.cv.simd.sdotusp.sc.b +uint32_t test_sdotusp_sc_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotusp_sc_b(a, b, c); +} + +// CHECK-LABEL: @test_sdotusp_sci_b +// CHECK: @llvm.riscv.cv.simd.sdotusp.sc.b +uint32_t test_sdotusp_sci_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_sdotusp_sc_b(a, 0, b); +} + +// CHECK-LABEL: @test_sdotsp_h +// CHECK: @llvm.riscv.cv.simd.sdotsp.h +uint32_t test_sdotsp_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotsp_h(a, b, c); +} + +// CHECK-LABEL: @test_sdotsp_b +// CHECK: @llvm.riscv.cv.simd.sdotsp.b +uint32_t test_sdotsp_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotsp_b(a, b, c); +} + +// CHECK-LABEL: @test_sdotsp_sc_h +// CHECK: @llvm.riscv.cv.simd.sdotsp.sc.h +uint32_t test_sdotsp_sc_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotsp_sc_h(a, b, c); +} + +// CHECK-LABEL: @test_sdotsp_sci_h +// CHECK: @llvm.riscv.cv.simd.sdotsp.sc.h +uint32_t test_sdotsp_sci_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_sdotsp_sc_h(a, 0, b); +} + +// CHECK-LABEL: @test_sdotsp_sc_b +// CHECK: @llvm.riscv.cv.simd.sdotsp.sc.b +uint32_t test_sdotsp_sc_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_sdotsp_sc_b(a, b, c); +} + +// CHECK-LABEL: @test_sdotsp_sci_b +// CHECK: @llvm.riscv.cv.simd.sdotsp.sc.b +uint32_t test_sdotsp_sci_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_sdotsp_sc_b(a, 0, b); +} + +// CHECK-LABEL: @test_extract_h +// CHECK: @llvm.riscv.cv.simd.extract.h +uint32_t test_extract_h(uint32_t a) { + return __riscv_cv_simd_extract_h(a, 0); +} + +// CHECK-LABEL: @test_extract_b +// CHECK: @llvm.riscv.cv.simd.extract.b +uint32_t test_extract_b(uint32_t a) { + return __riscv_cv_simd_extract_b(a, 0); +} + +// CHECK-LABEL: @test_extractu_h +// CHECK: @llvm.riscv.cv.simd.extractu.h +uint32_t test_extractu_h(uint32_t a) { + return __riscv_cv_simd_extractu_h(a, 0); +} + +// CHECK-LABEL: @test_extractu_b +// CHECK: @llvm.riscv.cv.simd.extractu.b +uint32_t test_extractu_b(uint32_t a) { + return __riscv_cv_simd_extractu_b(a, 0); +} + +// CHECK-LABEL: @test_shuffle_h +// CHECK: @llvm.riscv.cv.simd.shuffle.h +uint32_t test_shuffle_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_shuffle_h(a, b); +} + +// CHECK-LABEL: @test_shuffle_b +// CHECK: @llvm.riscv.cv.simd.shuffle.b +uint32_t test_shuffle_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_shuffle_b(a, b); +} + +// CHECK-LABEL: @test_shuffle_sci_h +// CHECK: @llvm.riscv.cv.simd.shuffle.sci.h +uint32_t test_shuffle_sci_h(uint32_t a) { + return __riscv_cv_simd_shuffle_sci_h(a, 0); +} + +// CHECK-LABEL: @test_shuffleI0_sci_b +// CHECK: @llvm.riscv.cv.simd.shuffle.sci.b +uint32_t test_shuffleI0_sci_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_shuffle_sci_b(a, 0); +} + +// CHECK-LABEL: @test_shuffle2_h +// CHECK: @llvm.riscv.cv.simd.shuffle2.h +uint32_t test_shuffle2_h(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_shuffle2_h(a, b, c); +} + +// CHECK-LABEL: @test_shuffle2_b +// CHECK: @llvm.riscv.cv.simd.shuffle2.b +uint32_t test_shuffle2_b(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_shuffle2_b(a, b, c); +} + +// CHECK-LABEL: @test_packhi_h +// CHECK: @llvm.riscv.cv.simd.packhi.h +uint32_t test_packhi_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_packhi_h(a, b); +} + +// CHECK-LABEL: @test_packlo_h +// CHECK: @llvm.riscv.cv.simd.packlo.h +uint32_t test_packlo_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_packlo_h(a, b); +} + +// CHECK-LABEL: @test_cmpeq_h +// CHECK: @llvm.riscv.cv.simd.cmpeq.h +uint32_t test_cmpeq_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpeq_h(a, b); +} + +// CHECK-LABEL: @test_cmpeq_b +// CHECK: @llvm.riscv.cv.simd.cmpeq.b +uint32_t test_cmpeq_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpeq_b(a, b); +} + +// CHECK-LABEL: @test_cmpeq_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpeq.sc.h +uint32_t test_cmpeq_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpeq_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpeq_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpeq.sc.h +uint32_t test_cmpeq_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpeq_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpeq_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpeq.sc.b +uint32_t test_cmpeq_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpeq_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpeq_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpeq.sc.b +uint32_t test_cmpeq_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpeq_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpne_h +// CHECK: @llvm.riscv.cv.simd.cmpne.h +uint32_t test_cmpne_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpne_h(a, b); +} + +// CHECK-LABEL: @test_cmpne_b +// CHECK: @llvm.riscv.cv.simd.cmpne.b +uint32_t test_cmpne_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpne_b(a, b); +} + +// CHECK-LABEL: @test_cmpne_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpne.sc.h +uint32_t test_cmpne_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpne_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpne_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpne.sc.h +uint32_t test_cmpne_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpne_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpne_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpne.sc.b +uint32_t test_cmpne_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpne_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpne_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpne.sc.b +uint32_t test_cmpne_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpne_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpgt_h +// CHECK: @llvm.riscv.cv.simd.cmpgt.h +uint32_t test_cmpgt_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpgt_h(a, b); +} + +// CHECK-LABEL: @test_cmpgt_b +// CHECK: @llvm.riscv.cv.simd.cmpgt.b +uint32_t test_cmpgt_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpgt_b(a, b); +} + +// CHECK-LABEL: @test_cmpgt_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpgt.sc.h +uint32_t test_cmpgt_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpgt_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpgt_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpgt.sc.h +uint32_t test_cmpgt_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpgt_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpgt_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpgt.sc.b +uint32_t test_cmpgt_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpgt_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpgt_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpgt.sc.b +uint32_t test_cmpgt_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpgt_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpge_h +// CHECK: @llvm.riscv.cv.simd.cmpge.h +uint32_t test_cmpge_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpge_h(a, b); +} + +// CHECK-LABEL: @test_cmpge_b +// CHECK: @llvm.riscv.cv.simd.cmpge.b +uint32_t test_cmpge_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpge_b(a, b); +} + +// CHECK-LABEL: @test_cmpge_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpge.sc.h +uint32_t test_cmpge_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpge_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpge_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpge.sc.h +uint32_t test_cmpge_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpge_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpge_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpge.sc.b +uint32_t test_cmpge_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpge_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpge_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpge.sc.b +uint32_t test_cmpge_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpge_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmplt_h +// CHECK: @llvm.riscv.cv.simd.cmplt.h +uint32_t test_cmplt_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmplt_h(a, b); +} + +// CHECK-LABEL: @test_cmplt_b +// CHECK: @llvm.riscv.cv.simd.cmplt.b +uint32_t test_cmplt_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmplt_b(a, b); +} + +// CHECK-LABEL: @test_cmplt_sc_h +// CHECK: @llvm.riscv.cv.simd.cmplt.sc.h +uint32_t test_cmplt_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmplt_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmplt_sci_h +// CHECK: @llvm.riscv.cv.simd.cmplt.sc.h +uint32_t test_cmplt_sci_h(uint32_t a) { + return __riscv_cv_simd_cmplt_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmplt_sc_b +// CHECK: @llvm.riscv.cv.simd.cmplt.sc.b +uint32_t test_cmplt_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmplt_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmplt_sci_b +// CHECK: @llvm.riscv.cv.simd.cmplt.sc.b +uint32_t test_cmplt_sci_b(uint32_t a) { + return __riscv_cv_simd_cmplt_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmple_h +// CHECK: @llvm.riscv.cv.simd.cmple.h +uint32_t test_cmple_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmple_h(a, b); +} + +// CHECK-LABEL: @test_cmple_b +// CHECK: @llvm.riscv.cv.simd.cmple.b +uint32_t test_cmple_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmple_b(a, b); +} + +// CHECK-LABEL: @test_cmple_sc_h +// CHECK: @llvm.riscv.cv.simd.cmple.sc.h +uint32_t test_cmple_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmple_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmple_sci_h +// CHECK: @llvm.riscv.cv.simd.cmple.sc.h +uint32_t test_cmple_sci_h(uint32_t a) { + return __riscv_cv_simd_cmple_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmple_sc_b +// CHECK: @llvm.riscv.cv.simd.cmple.sc.b +uint32_t test_cmple_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmple_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmple_sci_b +// CHECK: @llvm.riscv.cv.simd.cmple.sc.b +uint32_t test_cmple_sci_b(uint32_t a) { + return __riscv_cv_simd_cmple_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpgtu_h +// CHECK: @llvm.riscv.cv.simd.cmpgtu.h +uint32_t test_cmpgtu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpgtu_h(a, b); +} + +// CHECK-LABEL: @test_cmpgtu_b +// CHECK: @llvm.riscv.cv.simd.cmpgtu.b +uint32_t test_cmpgtu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpgtu_b(a, b); +} + +// CHECK-LABEL: @test_cmpgtu_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpgtu.sc.h +uint32_t test_cmpgtu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpgtu_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpgtu_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpgtu.sc.h +uint32_t test_cmpgtu_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpgtu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpgtu_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpgtu.sc.b +uint32_t test_cmpgtu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpgtu_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpgtu_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpgtu.sc.b +uint32_t test_cmpgtu_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpgtu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpgeu_h +// CHECK: @llvm.riscv.cv.simd.cmpgeu.h +uint32_t test_cmpgeu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpgeu_h(a, b); +} + +// CHECK-LABEL: @test_cmpgeu_b +// CHECK: @llvm.riscv.cv.simd.cmpgeu.b +uint32_t test_cmpgeu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpgeu_b(a, b); +} + +// CHECK-LABEL: @test_cmpgeu_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpgeu.sc.h +uint32_t test_cmpgeu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpgeu_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpgeu_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpgeu.sc.h +uint32_t test_cmpgeu_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpgeu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpgeu_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpgeu.sc.b +uint32_t test_cmpgeu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpgeu_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpgeu_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpgeu.sc.b +uint32_t test_cmpgeu_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpgeu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpltu_h +// CHECK: @llvm.riscv.cv.simd.cmpltu.h +uint32_t test_cmpltu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpltu_h(a, b); +} + +// CHECK-LABEL: @test_cmpltu_b +// CHECK: @llvm.riscv.cv.simd.cmpltu.b +uint32_t test_cmpltu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpltu_b(a, b); +} + +// CHECK-LABEL: @test_cmpltu_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpltu.sc.h +uint32_t test_cmpltu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpltu_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpltu_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpltu.sc.h +uint32_t test_cmpltu_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpltu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpltu_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpltu.sc.b +uint32_t test_cmpltu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpltu_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpltu_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpltu.sc.b +uint32_t test_cmpltu_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpltu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cmpleu_h +// CHECK: @llvm.riscv.cv.simd.cmpleu.h +uint32_t test_cmpleu_h(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpleu_h(a, b); +} + +// CHECK-LABEL: @test_cmpleu_b +// CHECK: @llvm.riscv.cv.simd.cmpleu.b +uint32_t test_cmpleu_b(uint32_t a, uint32_t b) { + return __riscv_cv_simd_cmpleu_b(a, b); +} + +// CHECK-LABEL: @test_cmpleu_sc_h +// CHECK: @llvm.riscv.cv.simd.cmpleu.sc.h +uint32_t test_cmpleu_sc_h(uint32_t a, uint16_t b) { + return __riscv_cv_simd_cmpleu_sc_h(a, b); +} + +// CHECK-LABEL: @test_cmpleu_sci_h +// CHECK: @llvm.riscv.cv.simd.cmpleu.sc.h +uint32_t test_cmpleu_sci_h(uint32_t a) { + return __riscv_cv_simd_cmpleu_sc_h(a, 0); +} + +// CHECK-LABEL: @test_cmpleu_sc_b +// CHECK: @llvm.riscv.cv.simd.cmpleu.sc.b +uint32_t test_cmpleu_sc_b(uint32_t a, uint8_t b) { + return __riscv_cv_simd_cmpleu_sc_b(a, b); +} + +// CHECK-LABEL: @test_cmpleu_sci_b +// CHECK: @llvm.riscv.cv.simd.cmpleu.sc.b +uint32_t test_cmpleu_sci_b(uint32_t a) { + return __riscv_cv_simd_cmpleu_sc_b(a, 0); +} + +// CHECK-LABEL: @test_cplxmul_r +// CHECK: @llvm.riscv.cv.simd.cplxmul.r +uint32_t test_cplxmul_r(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_cplxmul_r(a, b, c, 0); +} + +// CHECK-LABEL: @test_cplxmul_i +// CHECK: @llvm.riscv.cv.simd.cplxmul.i +uint32_t test_cplxmul_i(uint32_t a, uint32_t b, uint32_t c) { + return __riscv_cv_simd_cplxmul_i(a, b, c, 0); +} + +// CHECK-LABEL: @test_cplxconj +// CHECK: @llvm.riscv.cv.simd.cplxconj +uint32_t test_cplxconj(uint32_t a) { + return __riscv_cv_simd_cplxconj(a); +} + +// CHECK-LABEL: @test_subrotmj +// CHECK: @llvm.riscv.cv.simd.subrotmj +uint32_t test_subrotmj(uint32_t a, uint32_t b) { + return __riscv_cv_simd_subrotmj(a, b, 0); +}