From 34977aa07e41d22098a33f32a38cefc084e2b39b Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 19 Oct 2023 11:18:43 +0200 Subject: [PATCH 1/3] Added a note about MSTATUS.FS update. Signed-off-by: Pascal Gouedo --- docs/source/control_status_registers.rst | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/docs/source/control_status_registers.rst b/docs/source/control_status_registers.rst index 9ccfc070b..be4ae1652 100644 --- a/docs/source/control_status_registers.rst +++ b/docs/source/control_status_registers.rst @@ -445,7 +445,7 @@ Detailed: +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ | 30:15 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 14:13 | RW | **FS:** Floating point State | + | 14:13 | RW | **FS:** Floating point State (See note below) | | | | | | | | 00 = Off | | | | | @@ -478,6 +478,10 @@ Detailed: | 2:0 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ +.. note:: + + As allowed by RISC-V ISA and to simplify MSTATUS.FS update in the design, the state is updated to Dirty when executing any F instructions except for all FSW ones. + .. only:: USER User Status (``ustatus``) @@ -652,8 +656,10 @@ Detailed: | 4:0 | RW | **Exception Code** (See note below) | +-------------+-----------+----------------------------------------------------------------------------------+ -**NOTE**: software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example, -when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior. +.. note:: + + Software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example, + when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior. Machine Trap Value (``mtval``) @@ -1603,8 +1609,10 @@ Detailed: | 4:0 | RW | **Exception Code** (See note below) | +-------------+-----------+------------------------------------------------------------------------------------+ - **NOTE**: software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example, - when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior. + .. note:: + + Software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example, + when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior. .. only:: PMP From 7c2bb288d79d7b61e27a73fb99984ef50d2da1de Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 24 Oct 2023 17:32:55 +0200 Subject: [PATCH 2/3] Corrected MPIE/MPP mode. Signed-off-by: Pascal Gouedo --- docs/source/control_status_registers.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/source/control_status_registers.rst b/docs/source/control_status_registers.rst index be4ae1652..28f3d2fe6 100644 --- a/docs/source/control_status_registers.rst +++ b/docs/source/control_status_registers.rst @@ -457,13 +457,13 @@ Detailed: | | | | | | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 12:11 | RO | **MPP:** Machine Previous Priviledge mode | + | 12:11 | RW | **MPP:** Machine Previous Priviledge mode | | | | | - | | | 11 when the user mode is not enabled. | + | | | Hardwired to 11 when the User mode is not enabled. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ | 10:8 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 7 | RO | **MPIE:** Machine Previous Interrupt Enable | + | 7 | RW | **MPIE:** Machine Previous Interrupt Enable | | | | | | | | When an exception is encountered, MPIE will be set to MIE. | | | | When the mret instruction is executed, the value of MPIE will be stored to MIE. | From b13c97efd75a4dd8487252b20fd498279f6c8778 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Fri, 27 Oct 2023 15:45:44 +0200 Subject: [PATCH 3/3] Updated CVFPU release version Signed-off-by: Pascal Gouedo --- docs/source/fpu.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/fpu.rst b/docs/source/fpu.rst index 9dc85aa2e..019630a35 100644 --- a/docs/source/fpu.rst +++ b/docs/source/fpu.rst @@ -25,7 +25,7 @@ precision can be enabled by setting the parameter **FPU** of the ``cv32e40p_top` to 1. This will extend the CV32E40P decoder accordingly and will instantiate the FPU. The FPU repository used by the CV32E40P is available at `https://github.com/openhwgroup/cvfpu `_ and its documentation can be found `here `_. -CVFPU v1.0.0 release has been copied in CV32E40P repository inside rtl/vendor (used for verification and implementation) so all core and FPU RTL files should be taken from CV32E40P repository. +CVFPU v0.8.1 release has been copied in CV32E40P repository inside rtl/vendor (used for verification and implementation) so all core and FPU RTL files should be taken from CV32E40P repository. cv32e40p_fpu_manifest file is listing all necessary files for both the Core and CVFPU.