diff --git a/docs/requirements.txt b/docs/requirements.txt index ed9ee59ef..4753c4386 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,5 +1,5 @@ sphinx -sphinx-rtd-theme +sphinx_rtd_theme recommonmark sphinxcontrib-svg2pdfconverter sphinx_github_changelog diff --git a/docs/source/conf.py b/docs/source/conf.py index 9ebeb077c..0bc083e57 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -38,7 +38,7 @@ # -- Project information ----------------------------------------------------- project = u'CORE-V CV32E40P User Manual' -copyright = u'2020, OpenHW Group' +copyright = u'2022, OpenHW Group' author = u'PULP Platform and OpenHW Group' # The short X.Y version @@ -59,6 +59,7 @@ extensions = [ 'sphinx.ext.autodoc', 'sphinx.ext.todo', + 'sphinx.ext.imgconverter', 'recommonmark', 'sphinxcontrib.inkscapeconverter', 'sphinx_github_changelog', @@ -118,7 +119,7 @@ # so a file named "default.css" will overwrite the builtin "default.css". #html_static_path = ['ystatic'] # Set html_static_path to null on the advice of RTDs: -html_static_path = [] +html_static_path = ['_static'] # Custom sidebar templates, must be a dictionary that maps document names # to template names. @@ -130,6 +131,9 @@ # # html_sidebars = {} +html_css_files = [ + 'css/custom.css', +] # -- Options for HTMLHelp output --------------------------------------------- @@ -161,8 +165,8 @@ # (source start file, target name, title, # author, documentclass [howto, manual, or own class]). latex_documents = [ - (master_doc, 'CV32E40P_User_Manual.tex', u'CORE-V-Docs Documentation', - u'Davide Schiavone', 'manual'), + (master_doc, 'CV32E40P_User_Manual.tex', u'CV32E40P User Manual', + u'OpenHW Group', 'manual'), ] diff --git a/docs/source/index.rst b/docs/source/index.rst index 50ec8b80d..357b813d9 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -17,8 +17,6 @@ OpenHW Group CV32E40P User Manual ================================= -Editor: **Davide Schiavone** -`davide@openhwgroup.org `__ .. toctree:: :maxdepth: 3 diff --git a/docs/source/intro.rst b/docs/source/intro.rst index dd210d522..7006b1327 100644 --- a/docs/source/intro.rst +++ b/docs/source/intro.rst @@ -239,7 +239,7 @@ A classification of the issues themselves: +==============================+=======+========================================================================================+ | RTL Functional | 40 | A bug! | +------------------------------+-------+----------------------------------------------------------------------------------------+ - | RTL coding style | 4 | Linter issues, removing TODOs, removing `ifdefs, etc. | + | RTL coding style | 4 | Linter issues, removing TODOs, removing \`ifdefs, etc. | +------------------------------+-------+----------------------------------------------------------------------------------------+ | Non-RTL functional | 1 | Issue related to behavioral tracer (not part of the core) | +------------------------------+-------+----------------------------------------------------------------------------------------+ @@ -273,7 +273,7 @@ Contents History ------- -CV32E40P started its life as a fork of the OR10N CPU core based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform team until February 2020, when it has been contributed to OpenHW Group https://www.openhwgroup.org>. +CV32E40P started its life as a fork of the OR10N CPU core based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform team until February 2020, when it has been contributed to OpenHW Group https://www.openhwgroup.org. As RI5CY has been used in several projects, a list of all the changes made by OpenHW Group since February 2020 follows: @@ -332,18 +332,14 @@ References Contributors ------------ -| Andreas Traber - (`*atraber@iis.ee.ethz.ch* `__) +| Andreas Traber (`*atraber@iis.ee.ethz.ch* `__) +| Michael Gautschi (`*gautschi@iis.ee.ethz.ch* `__) +| Pasquale Davide Schiavone (`*pschiavo@iis.ee.ethz.ch* `__) -Michael Gautschi -(`*gautschi@iis.ee.ethz.ch* `__) +| Arjan Bink (`*arjan.bink@silabs.com* `__) +| Paul Zavalney (`*paul.zavalney@silabs.com* `__) -Pasquale Davide Schiavone -(`*pschiavo@iis.ee.ethz.ch* `__) - -Arjan Bink (`*arjan.bink@silabs.com* `__) - -Paul Zavalney (`*paul.zavalney@silabs.com* `__) +| Pascal Gouédo (`*pascal.gouedo@dolphin.fr* `__) | Micrel Lab and Multitherman Lab | University of Bologna, Italy diff --git a/docs/source/pipeline.rst b/docs/source/pipeline.rst index 4109ce88d..c0c9d623e 100644 --- a/docs/source/pipeline.rst +++ b/docs/source/pipeline.rst @@ -17,15 +17,15 @@ .. _pipeline-details: +Pipeline Details +================ + .. figure:: ../images/CV32E40P_Pipeline.png :name: cv32e40p-pipeline :align: center CV32E40P Pipeline -Pipeline Details -================ - CV32E40P has a 4-stage in-order completion pipeline, the 4 stages are: Instruction Fetch (IF) diff --git a/docs/source/preface.rst b/docs/source/preface.rst index bb891478b..f6b516214 100644 --- a/docs/source/preface.rst +++ b/docs/source/preface.rst @@ -2,5 +2,6 @@ Changelog ========= .. changelog:: + :changelog-url: https://cv32e40p-user-manual.readthedocs.io/en/stable/#changelog :github: https://github.com/openhwgroup/cv32e40p/releases/