RTL Code Coverage Hole in cv32e40p_controller module line 640

[pascalgouedo]

Component

Component:RTL

Issue description

There is 1 condition not covered on line 640 of cv32e40p_controller during all the simulation non-regressions:
No return from interrupt, ecall, ebreak or exceptions on HWLoop 1 last instruction with HWLoop 1 counter <= 1 while it happened on HWLoop 0 (line 630).

Added a scenario in pulp_hardware_loop test with an ecall just before the last instruction of the body in a single HWloop 1 execution (test9).
Showed that this uncovered condition can not happen because when (hwlp_end1_eq_pc = 1 && hwlp_counter1_gt_1 = 0), is_hwloop_body = 0 on line 620 preventing to evaluate this condition. It happened on HWLoop 0 when it is nested in HWloop 1 because is_hwloop_body is still 1 when (hwlp_end0_eq_pc = 1 && hwlp_counter0_gt_1 = 0) is evaluated (and then covered).
But as HWloop 1 can not be nested in HWloop 0 this condition hole will never be covered for HWloop 1.

So it has been waived in v2.
It could maybe be proven using SLEC app of Cadence JasperGold tool?