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RTL Code Coverage Hole in cv32e40p_EX_stage module line 211 for FPU configuration #1016

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YoannPruvost opened this issue Jul 2, 2024 · 0 comments
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) WAIVED:CV32E40P Issue does not impact a major release of CV32E40P and is waived

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@YoannPruvost
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Component:RTL

Issue Description

One of the possible combination in the if statement line 211 of cv32e40p_EX_stage was not covered during all the simulation non-regressions.

After analysis we suspected that this scenario was in fact unreachable.
Siemens Questa Static formal tool was used to prove that this scenario was unreachable. For this scenario a dedicated assertion was written, named assert_unreachable_ex_211.

All information necessary to reproduce and analyze our work with formal can be found in the ReadMe in the cv32e40p/scripts/formal folder

As it was too late to implement a fix in the RTL due to long RISC-V ISA Formal Verification runs and requiring to update all waivers files as well, it has been decided to waive this scenario hole in v2.

211-1
211-2

@YoannPruvost YoannPruvost added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) WAIVED:CV32E40P Issue does not impact a major release of CV32E40P and is waived labels Jul 2, 2024
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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) WAIVED:CV32E40P Issue does not impact a major release of CV32E40P and is waived
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