From 40ac9cf0389de87908fd8c96639b4cba875e7e67 Mon Sep 17 00:00:00 2001 From: Oystein Knauserud Date: Mon, 9 Jan 2023 12:34:59 +0100 Subject: [PATCH] Updated documentation of JVT CSR alignment from 1024 Bytes to 64 Bytes. Signed-off-by: Oystein Knauserud --- docs/user_manual/source/control_status_registers.rst | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst index be083fc0..0a924542 100644 --- a/docs/user_manual/source/control_status_registers.rst +++ b/docs/user_manual/source/control_status_registers.rst @@ -412,9 +412,7 @@ Detailed: +----------+------------+-----------------------------------------------------------------------------------------------+ | Bit # | R/W | Description | +==========+============+===============================================================================================+ - | 31:10 | WARL | **BASE[31:10]**: Table Jump Base Address, 1024 byte aligned. | - +----------+------------+-----------------------------------------------------------------------------------------------+ - | 9:6 | WARL (0x0) | **BASE[9:6]**: Table Jump Base Address, 1024 byte aligned. ``jvt[9:6]`` is hardwired to 0x0. | + | 31:6 | WARL | **BASE[31:6]**: Table Jump Base Address, 64 byte aligned. | +----------+------------+-----------------------------------------------------------------------------------------------+ | 5:0 | WARL (0x0) | **MODE**: Jump table mode | +----------+------------+-----------------------------------------------------------------------------------------------+