From 174dcfa36dea78f602de909609a0613566f859ea Mon Sep 17 00:00:00 2001 From: Arjan Bink Date: Mon, 28 Mar 2022 15:12:05 +0200 Subject: [PATCH] Updated WARL behavior of pmpxcfg Signed-off-by: Arjan Bink --- .../source/control_status_registers.rst | 50 +++++++++---------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst index 248769d4..533fcfec 100644 --- a/docs/user_manual/source/control_status_registers.rst +++ b/docs/user_manual/source/control_status_registers.rst @@ -1719,13 +1719,13 @@ Detailed: +-------+-----------------+---------------------------------------------------------------------------------------------------------------+ | Bit# | R/W | Definition | +=======+=================+===============================================================================================================+ - | 31:24 | RW / WARL (0x0) | PMP3CFG | + | 31:24 | RW | PMP3CFG | +-------+-----------------+---------------------------------------------------------------------------------------------------------------+ - | 23:16 | RW / WARL (0x0) | PMP2CFG | + | 23:16 | RW | PMP2CFG | +-------+-----------------+---------------------------------------------------------------------------------------------------------------+ - | 15:8 | RW / WARL (0x0) | PMP1CFG | + | 15:8 | RW | PMP1CFG | +-------+-----------------+---------------------------------------------------------------------------------------------------------------+ - | 7:0 | RW / WARL (0x0) | PMP0CFG | + | 7:0 | RW | PMP0CFG | +-------+-----------------+---------------------------------------------------------------------------------------------------------------+ Detailed ``pmpcfg1``: @@ -1733,13 +1733,13 @@ Detailed: +-------+------------------+---------------------------------------------------------------------------------------------------------------+ | Bit# | R/W | Definition | +=======+==================+===============================================================================================================+ - | 31:24 | RW / WARL (0x0) | PMP7CFG | + | 31:24 | RW | PMP7CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - | 23:16 | RW / WARL (0x0) | PMP6CFG | + | 23:16 | RW | PMP6CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - | 15:8 | RW / WARL (0x0) | PMP5CFG | + | 15:8 | RW | PMP5CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - | 7:0 | RW / WARL (0x0) | PMP4CFG | + | 7:0 | RW | PMP4CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ ... @@ -1749,43 +1749,41 @@ Detailed: +-------+------------------+---------------------------------------------------------------------------------------------------------------+ | Bit# | R/W | Definition | +=======+==================+===============================================================================================================+ - | 31:24 | RW / WARL (0x0) | PMP63CFG | + | 31:24 | RW | PMP63CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - | 23:16 | RW / WARL (0x0) | PMP62CFG | + | 23:16 | RW | PMP62CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - | 15:8 | RW / WARL (0x0) | PMP61CFG | + | 15:8 | RW | PMP61CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - | 7:0 | RW / WARL (0x0) | PMP60CFG | + | 7:0 | RW | PMP60CFG | +-------+------------------+---------------------------------------------------------------------------------------------------------------+ - The configuration fields for each pmpxcfg are as follows: + The configuration fields for each ``pmpxcfg`` are as follows: +-------+------------------+---------------------------+ | Bit# | R/W | Definition | +=======+==================+===========================+ | 8 | WARL (0x0) | Reserved | +-------+------------------+---------------------------+ - | 7 | RW / WARL (0x0) | **L**. Lock | + | 7 | RW | **L**. Lock | +-------+------------------+---------------------------+ | 6:5 | WARL (0x0) | Reserved | +-------+------------------+---------------------------+ - | 4:3 | RW / WARL (0x0) | **A**. Mode | + | 4:3 | RW | **A**. Mode | +-------+------------------+---------------------------+ - | 2 | RW / WARL (0x0) | **X**. Execute permission | + | 2 | RW / | **X**. Execute permission | + +-------+ WARL (0x0, 0x1, +---------------------------+ + | 1 | 0x3, 0x4, | **W**. Write permission | + +-------+ 0x5, 0x7) +---------------------------+ + | 0 | | **R**. Read permission | +-------+------------------+---------------------------+ - | 1 | RW / WARL (0x0) | **W**. Write permission | - +-------+------------------+---------------------------+ - | 0 | RW / WARL (0x0) | **R**. Read permission | - +-------+------------------+---------------------------+ - - pmpxcfg is RW if x < ``PMP_NUM_REGIONS`` and WARL (0x0) otherwise. - .. note:: + pmpxcfg is WARL (0x0) if x >= ``PMP_NUM_REGIONS``. - The **R**, **W** and **X** together form a WARL field for which the combinations with **R** = 0 and **W** = 1 are reserved for future use - if **mseccfg.MML** = 0. - In |corev| the **W** bit will be forced to 0 when attempting to write **R** = 0 and **W** = 1 while **mseccfg.MML** = 0. + .. note:: + The **R**, **W** and **X** together form a collective WARL field for which the combinations with **R** = 0 and **W** = 1 are reserved for future use + if **mseccfg.MML** = 0. The value of the collective **R**, **W**, **X** bitfield will remain unchanged when attempting to write **R** = 0 and **W** = 1 while **mseccfg.MML** = 0. PMP Address (``pmpaddr0`` - ``pmpaddr63``) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~