diff --git a/core/cva6.sv b/core/cva6.sv
index c7062b217e..0609c461a1 100644
--- a/core/cva6.sv
+++ b/core/cva6.sv
@@ -1297,6 +1297,7 @@ module cva6
   // Cache port 0 is being ultilized in implicit read access in ZCMT extension.
   if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin
     assign dcache_req_ports_cache_id = dcache_req_from_cache[0];
+    assign dcache_req_ports_cache_ex[0] = '0;
   end else begin
     assign dcache_req_ports_cache_ex[0] = dcache_req_from_cache[0];
   end