From 67c8aac4634547ace93a605a53cf840a3db76b25 Mon Sep 17 00:00:00 2001
From: dassheladiya <150680188+dassheladiya@users.noreply.github.com>
Date: Wed, 13 Nov 2024 15:06:05 +0100
Subject: [PATCH] Update core/cva6_tip.sv

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
---
 core/cva6_tip.sv | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/core/cva6_tip.sv b/core/cva6_tip.sv
index 973aef4046d..d69ac1257b1 100644
--- a/core/cva6_tip.sv
+++ b/core/cva6_tip.sv
@@ -57,12 +57,14 @@ endgenerate
 
 
 
-//TIP signals
-always_comb begin
-      for (int i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
-        logic exception, mem_exception;
-        exception = commit_instr_i[i].valid && ex_commit_i.valid;
-        mem_exception = exception &&
+
+
+  //TIP signals
+  always_comb begin
+    for (int i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
+      logic exception, mem_exception;
+      exception = commit_instr_i[i].valid && ex_commit_i.valid;
+      mem_exception = exception &&
           (ex_commit_i.cause == riscv::INSTR_ADDR_MISALIGNED ||
            ex_commit_i.cause == riscv::INSTR_ACCESS_FAULT ||
            ex_commit_i.cause == riscv::ILLEGAL_INSTR ||