From 88ed8a765d486003a6a4d4c65633984019493700 Mon Sep 17 00:00:00 2001 From: Gianmarco Ottavi Date: Mon, 20 Jan 2025 13:16:02 +0100 Subject: [PATCH] bp: add BHT with private history Co-authored-by: Riccardo Tedeschi --- Bender.yml | 1 + Flist.ariane | 1 + core/Flist.cva6 | 1 + core/frontend/bht2lvl.sv | 135 ++++++++++++++++++ core/frontend/frontend.sv | 16 ++- core/include/build_config_pkg.sv | 2 + core/include/config_pkg.sv | 12 ++ core/include/cv32a60x_config_pkg.sv | 2 + core/include/cv32a65x_config_pkg.sv | 2 + .../cv32a6_embedded_config_pkg_deprecated.sv | 4 + .../cv32a6_ima_sv32_fpga_config_pkg.sv | 4 + core/include/cv32a6_imac_sv0_config_pkg.sv | 4 + core/include/cv32a6_imac_sv32_config_pkg.sv | 4 + core/include/cv32a6_imafc_sv32_config_pkg.sv | 4 + core/include/cv64a60ax_config_pkg.sv | 2 + .../cv64a6_imadfcv_sv39_polara_config_pkg.sv | 4 + core/include/cv64a6_imafdc_sv39_config_pkg.sv | 4 + .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 4 + ...64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv | 4 + ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 4 + .../cv64a6_imafdc_sv39_wb_config_pkg.sv | 4 + .../include/cv64a6_imafdch_sv39_config_pkg.sv | 4 + .../cv64a6_imafdch_sv39_wb_config_pkg.sv | 4 + .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 6 +- core/include/cv64a6_mmu_config_pkg.sv | 2 + docs/scripts/spec_builder.py | 1 + src_files.yml | 1 + 27 files changed, 234 insertions(+), 2 deletions(-) create mode 100644 core/frontend/bht2lvl.sv diff --git a/Bender.yml b/Bender.yml index 292149edeb..2178c96f71 100644 --- a/Bender.yml +++ b/Bender.yml @@ -122,6 +122,7 @@ sources: # Frontend (i.e., fetch, decode, dispatch) - core/frontend/btb.sv - core/frontend/bht.sv + - core/frontend/bht2lvl.sv - core/frontend/ras.sv - core/frontend/instr_scan.sv - core/frontend/instr_queue.sv diff --git a/Flist.ariane b/Flist.ariane index 0edfa8e4f5..592125b7f5 100644 --- a/Flist.ariane +++ b/Flist.ariane @@ -72,6 +72,7 @@ core/decoder.sv core/ex_stage.sv core/frontend/btb.sv core/frontend/bht.sv +core/frontend/bht2lvl.sv core/frontend/ras.sv core/frontend/instr_scan.sv core/frontend/instr_queue.sv diff --git a/core/Flist.cva6 b/core/Flist.cva6 index e82365d12b..17cb6ae98a 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -144,6 +144,7 @@ ${CVA6_REPO_DIR}/core/cva6_fifo_v3.sv // What is "frontend"? ${CVA6_REPO_DIR}/core/frontend/btb.sv ${CVA6_REPO_DIR}/core/frontend/bht.sv +${CVA6_REPO_DIR}/core/frontend/bht2lvl.sv ${CVA6_REPO_DIR}/core/frontend/ras.sv ${CVA6_REPO_DIR}/core/frontend/instr_scan.sv ${CVA6_REPO_DIR}/core/frontend/instr_queue.sv diff --git a/core/frontend/bht2lvl.sv b/core/frontend/bht2lvl.sv new file mode 100644 index 0000000000..011442b7c7 --- /dev/null +++ b/core/frontend/bht2lvl.sv @@ -0,0 +1,135 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Original author: Gianmarco Ottavi, University of Bologna +// Description: Private history BHT + +module bht2lvl #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned NR_ENTRIES = 256, + parameter int unsigned HISTORY_LENGTH = 3, + parameter type bht_update_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic [ CVA6Cfg.VLEN-1:0] vpc_i, + input bht_update_t bht_update_i, + // we potentially need INSTR_PER_FETCH predictions/cycle + output ariane_pkg::bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction_o +); + + // the last bit is always zero, we don't need it for indexing + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; + // re-shape the branch history table + localparam NR_ROWS = NR_ENTRIES / CVA6Cfg.INSTR_PER_FETCH; + // number of bits needed to index the row + localparam ROW_ADDR_BITS = $clog2(CVA6Cfg.INSTR_PER_FETCH); + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1; + // number of bits we should use for prediction + localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; + + struct packed { + logic valid; + logic [HISTORY_LENGTH-1:0] hist; + logic [2**HISTORY_LENGTH-1:0][1:0] saturation_counter; + } + bht_d[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0], + bht_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0]; + + + logic [$clog2(NR_ROWS)-1:0] index, update_pc; + logic [HISTORY_LENGTH-1:0] update_hist; + logic [ROW_INDEX_BITS-1:0] update_row_index; + + assign index = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_pc = bht_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_hist = bht_q[update_pc][update_row_index].hist; + + if (CVA6Cfg.RVC) begin : gen_update_row_index + assign update_row_index = bht_update_i.pc[ROW_ADDR_BITS+OFFSET-1:OFFSET]; + end else begin + assign update_row_index = '0; + end + + + logic [1:0] saturation_counter; + + // Get the current history of the entry + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][HISTORY_LENGTH-1:0] read_history; + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + assign read_history[i] = bht_q[index][i].hist; + end + + // prediction assignment + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_output + assign bht_prediction_o[i].valid = bht_q[index][i].valid; + assign bht_prediction_o[i].taken = bht_q[index][i].saturation_counter[read_history[i]][1] == 1'b1; + end + + always_comb begin : update_bht + bht_d = bht_q; + saturation_counter = bht_q[update_pc][update_row_index].saturation_counter[update_hist]; + + if (bht_update_i.valid) begin + bht_d[update_pc][update_row_index].valid = 1'b1; + + if (saturation_counter == 2'b11) begin + // we can safely decrease it + if (!bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1; + // then check if it saturated in the negative regime e.g.: branch not taken + end else if (saturation_counter == 2'b00) begin + // we can safely increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1; + end else begin // otherwise we are not in any boundaries and can decrease or increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1; + else + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1; + end + + bht_d[update_pc][update_row_index].hist = { + update_hist[HISTORY_LENGTH-2:0], bht_update_i.taken + }; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + for (int unsigned i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + bht_q[i][j] <= '0; + for (int k = 0; k < 2 ** HISTORY_LENGTH; k++) begin + bht_q[i][j].saturation_counter[k] <= 2'b10; + end + end + end + end else begin + // evict all entries + if (flush_i) begin + for (int i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + bht_q[i][j].valid <= 1'b0; + bht_q[i][j].hist <= '0; + for (int k = 0; k < 2 ** HISTORY_LENGTH; k++) begin + bht_q[i][j].saturation_counter[k] <= 2'b10; + end + end + end + end else begin + bht_q <= bht_d; + end + end + end + + +endmodule diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 1505140e8c..caab48c819 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -510,7 +510,7 @@ module frontend if (CVA6Cfg.BHTEntries == 0) begin assign bht_prediction = '0; - end else begin : bht_gen + end else if (CVA6Cfg.BPType == config_pkg::BHT) begin : bht_gen bht #( .CVA6Cfg (CVA6Cfg), .bht_update_t(bht_update_t), @@ -524,6 +524,20 @@ module frontend .bht_update_i (bht_update), .bht_prediction_o(bht_prediction) ); + end else if (CVA6Cfg.BPType == config_pkg::PH_BHT) begin : bht2lvl_gen + bht2lvl #( + .CVA6Cfg (CVA6Cfg), + .NR_ENTRIES (CVA6Cfg.BHTEntries), + .HISTORY_LENGTH(CVA6Cfg.BHTHist), + .bht_update_t (bht_update_t) + ) i_bht ( + .clk_i, + .rst_ni, + .flush_i (flush_bp_i), + .vpc_i (icache_vaddr_q), + .bht_update_i (bht_update), + .bht_prediction_o(bht_prediction) + ); end // we need to inspect up to CVA6Cfg.INSTR_PER_FETCH instructions for branches diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 8dcad2937e..e40ad5c987 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -103,7 +103,9 @@ package build_config_pkg; cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress; cfg.RASDepth = CVA6Cfg.RASDepth; cfg.BTBEntries = CVA6Cfg.BTBEntries; + cfg.BPType = CVA6Cfg.BPType; cfg.BHTEntries = CVA6Cfg.BHTEntries; + cfg.BHTHist = CVA6Cfg.BHTHist; cfg.DmBaseAddress = CVA6Cfg.DmBaseAddress; cfg.TvalEn = CVA6Cfg.TvalEn; cfg.DirectVecOnly = CVA6Cfg.DirectVecOnly; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 681ee4e1b1..c6a5f2308a 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -35,6 +35,12 @@ package config_pkg; HPDCACHE_WT_WB = 4 } cache_type_t; + /// Branch predictor parameter + typedef enum logic { + BHT = 0, // Bimodal predictor + PH_BHT = 1 // Private History Bimodal predictor + } bp_type_t; + /// Data and Address length typedef enum logic [3:0] { ModeOff = 0, @@ -214,8 +220,12 @@ package config_pkg; int unsigned RASDepth; // Branch target buffer entries int unsigned BTBEntries; + // Branch predictor type + bp_type_t BPType; // Branch history entries int unsigned BHTEntries; + // Branch history bits + int unsigned BHTHist; // MMU instruction TLB entries int unsigned InstrTlbEntries; // MMU data TLB entries @@ -299,7 +309,9 @@ package config_pkg; logic [63:0] ExceptionAddress; int unsigned RASDepth; int unsigned BTBEntries; + bp_type_t BPType; int unsigned BHTEntries; + int unsigned BHTHist; int unsigned InstrTlbEntries; int unsigned DataTlbEntries; bit unsigned UseSharedTlb; diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index 147cce228d..711ddab261 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -62,7 +62,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(2), BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index c3d7dd32c1..d3c530a6ca 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -62,7 +62,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(2), BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index b649a284f2..20333f1fc7 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -62,6 +62,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 0; localparam CVA6ConfigBHTEntries = 32; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 0; @@ -117,7 +119,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 77434c9c84..cce9ae9580 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -58,6 +58,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -115,7 +117,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: unsigned'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 9765d5de44..cb48b0313d 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -58,6 +58,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -115,7 +117,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: unsigned'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 549eac2314..45b3c88668 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -57,6 +57,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -114,7 +116,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 4fd3bbec63..4eaf94a41f 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -58,6 +58,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -115,7 +117,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a60ax_config_pkg.sv b/core/include/cv64a60ax_config_pkg.sv index 3631ef39ee..474ff03c81 100644 --- a/core/include/cv64a60ax_config_pkg.sv +++ b/core/include/cv64a60ax_config_pkg.sv @@ -69,7 +69,9 @@ localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ ExceptionAddress: 64'h808, RASDepth: unsigned'(4), BTBEntries: unsigned'(16), + BPType: config_pkg::BHT, BHTEntries: unsigned'(64), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(1), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index c2497b4118..0d33cc66a1 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -61,6 +61,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -118,7 +120,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 42d1e9bdf2..c0050dd0ee 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -61,6 +61,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -118,7 +120,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 1fdbe45fad..7f803b45cc 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -68,6 +68,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -125,7 +127,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv index 8b077d36c0..3863941dab 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @@ -68,6 +68,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -125,7 +127,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index f18fa72c22..be84b040af 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -61,6 +61,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -118,7 +120,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 9742be6d63..4dca437cd2 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -61,6 +61,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -118,7 +120,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index dc85d86d75..d77023d85a 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -61,6 +61,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -118,7 +120,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 3195111477..2ca78359ce 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -61,6 +61,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -118,7 +120,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 42c1a76da3..643f09b522 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -35,7 +35,7 @@ package cva6_config_pkg; localparam CVA6ConfigAxiAddrWidth = 64; localparam CVA6ConfigAxiDataWidth = 64; localparam CVA6ConfigFetchUserEn = 0; - localparam CVA6ConfigFetchUserWidth = 1; // Just not to raise warnings + localparam CVA6ConfigFetchUserWidth = 1; // Just not to raise warnings localparam CVA6ConfigDataUserEn = 0; localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; @@ -63,6 +63,8 @@ package cva6_config_pkg; localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 32; localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigBHTHist = 3; + localparam config_pkg::bp_type_t CVA6ConfigBPType = config_pkg::BHT; localparam CVA6ConfigTvalEn = 1; @@ -120,7 +122,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: CVA6ConfigBPType, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(CVA6ConfigBHTHist), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index be6ce8eaca..c52f8f8292 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -69,7 +69,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(2), BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), diff --git a/docs/scripts/spec_builder.py b/docs/scripts/spec_builder.py index 31c47ea86c..a9407228a5 100755 --- a/docs/scripts/spec_builder.py +++ b/docs/scripts/spec_builder.py @@ -181,6 +181,7 @@ def main(): file.append("../core/cva6.sv") file.append("../core/frontend/frontend.sv") file.append("../core/frontend/bht.sv") + file.append("../core/frontend/bht2lvl.sv") file.append("../core/frontend/btb.sv") file.append("../core/frontend/ras.sv") file.append("../core/frontend/instr_queue.sv") diff --git a/src_files.yml b/src_files.yml index b71b628b6e..33c8bf6c05 100644 --- a/src_files.yml +++ b/src_files.yml @@ -22,6 +22,7 @@ ariane: src/ex_stage.sv, src/frontend/btb.sv, src/frontend/bht.sv, + src/frontend/bht2lvl.sv, src/frontend/ras.sv, src/frontend/instr_scan.sv, src/frontend/frontend.sv,