From ab89beaebbcb5ade0a9f3dd51f0f79ffadad5bbd Mon Sep 17 00:00:00 2001 From: khandelwaltanuj <158037163+khandelwaltanuj@users.noreply.github.com> Date: Fri, 28 Feb 2025 07:55:13 +0100 Subject: [PATCH] Adding a new configuration file for cv64a60ax and dv target RV64IMAFDC (#2761) A new configuration file and core v target is added to start working on a 64 bit CVA6 core. --------- Co-authored-by: JeanRochCoulon --- .../cv64a60ax/spec/custom_spec.yaml | 55 + .../cv64a60ax/spec/debug_spec.yaml | 168 ++ .../riscv-config/cv64a60ax/spec/isa_spec.yaml | 1863 +++++++++++++++++ .../cv64a60ax/spec/platform_spec.yaml | 53 + core/include/cv64a60ax_config_pkg.sv | 116 + .../target/rv64imafdc/riscv_core_setting.sv | 188 ++ 6 files changed, 2443 insertions(+) create mode 100644 config/riscv-config/cv64a60ax/spec/custom_spec.yaml create mode 100644 config/riscv-config/cv64a60ax/spec/debug_spec.yaml create mode 100644 config/riscv-config/cv64a60ax/spec/isa_spec.yaml create mode 100644 config/riscv-config/cv64a60ax/spec/platform_spec.yaml create mode 100644 core/include/cv64a60ax_config_pkg.sv create mode 100644 verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv diff --git a/config/riscv-config/cv64a60ax/spec/custom_spec.yaml b/config/riscv-config/cv64a60ax/spec/custom_spec.yaml new file mode 100644 index 0000000000..ec2c1f8449 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/custom_spec.yaml @@ -0,0 +1,55 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Zbigniew CHAMSKI - Thales + +hart_ids: [0] +hart0: + icache: + reset-val: 0x1 + rv32: + accessible: false + rv64: + accessible: true + icache: + implemented: true + type: + rw: true + description: bit for cache-enable of instruction cache + msb: 0 + lsb: 0 + shadow: + shadow_type: + description: the register controls the operation of the i-cache unit. + address: 0x7c0 + priv_mode: M + dcache: + reset-val: 0x1 + rv32: + accessible: false + rv64: + accessible: true + dcache: + implemented: true + type: + rw: true + description: bit for cache-enable of data cache + shadow: + shadow_type: + msb: 0 + lsb: 0 + description: the register controls the operation of the d-cache unit. + address: 0x7c1 + priv_mode: M + diff --git a/config/riscv-config/cv64a60ax/spec/debug_spec.yaml b/config/riscv-config/cv64a60ax/spec/debug_spec.yaml new file mode 100644 index 0000000000..7c1f981a68 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/debug_spec.yaml @@ -0,0 +1,168 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Zbigniew CHAMSKI - Thales +# Updated from CV66 64 CEA - Tanuj Khandelwal - Thales + +hart_ids: [0] +hart0: &hart0 + Debug_Spec_Version: '1.0.0' + supported_xlen: [64] + debug_mode: true + parking_loop: 0x800 + dcsr: + reset-val: 0x40000413 + rv64: + accessible: true + debugver: + implemented: true + type: + ro_constant: 0x4 + ebreakvs: + implemented: false + ebreakvu: + implemented: false + ebreakm: + implemented: true + ebreaks: + implemented: true + ebreaku: + implemented: true + stepie: + implemented: true + stopcount: + implemented: true + stoptime: + implemented: true + cause: + implemented: true + type: + ro_variable: true + v: + implemented: true + mprven: + implemented: true + nmip: + implemented: true + type: + ro_variable: true + step: + implemented: true + prv: + implemented: true + rv32: + accessible: false + dpc: + rv64: + accessible: true + rv32: + accessible: false + tselect: + rv32: + accessible: False + rv64: + accessible: True + type: + warl: + dependency_fields: [] + legal: + - tselect[63:0] in [0x00000000:0x3] + wr_illegal: + - unchanged + tinfo: #FIXME + rv32: + accessible: False + rv64: + accessible: True + index_select_reg: tselect + index_list: + - reset-val: 0x78 + index_val: 0 + shadow: + shadow_type: + type: + ro_constant: 0x78 + - reset-val: 0x8 + index_val: 1 + shadow: + shadow_type: + type: + ro_constant: 0x8 + - reset-val: 0x10 + index_val: 2 + shadow: + shadow_type: + type: + ro_constant: 0x10 + tdata1: + rv32: + accessible: False + rv64: + accessible: True + index_select_reg: tselect + index_list: + - reset-val: 0xdeadbeef + index_val: 0 + shadow: + shadow_type: + type: + ro_constant: 0xdeadbeef + - reset-val: 0 + index_val: 1 + shadow: + shadow_type: + type: &mywarl + warl: + dependency_fields: [] + legal: + - writeval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + - reset-val: 0 + index_val: 2 + shadow: + shadow_type: + type: + warl: + dependency_fields: [] + legal: + - writeval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + + #FIXME NTO SUPPORTED BY RISCV CNFIG + # tdata2: + # rv64: + # accessible: true + # type: + # ro_variable: true + # rv32: + # accessible: false + # tdata3: + # rv64: + # accessible: true + # type: + # ro_variable: true + # rv32: + # accessible: false + dscratch0: + rv64: + accessible: true + rv32: + accessible: false + dscratch1: + rv64: + accessible: true + rv32: + accessible: false diff --git a/config/riscv-config/cv64a60ax/spec/isa_spec.yaml b/config/riscv-config/cv64a60ax/spec/isa_spec.yaml new file mode 100644 index 0000000000..3ae10eed68 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/isa_spec.yaml @@ -0,0 +1,1863 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Zbigniew CHAMSKI - Thales +# Updated from CV6A60AX 64 CEA - Tanuj Khandelwal - Thales + +hart_ids: [0] +hart0: &hart0 + ISA: RV64IMAFDCNSUZicsr_Zicbom_Zicbop_Zicboz_Zifencei_Zcb_Zba_Zbb_Zbc_Zbs + User_Spec_Version: '2.3' + supported_xlen: [64] + physical_addr_sz: 39 + pmp_granularity: 10 # FIXME: To verify + misa: + # reset-val: 0xC00000000214312F # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25 + rv64: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x2] + wr_illegal: + - unchanged + extensions: + implemented: true + type: + # ro_constant: 0x214312F + mvendorid: + reset-val: 0x00000602 + rv64: + accessible: true + type: + ro_constant: 0x00000602 + rv32: + accessible: false + fcsr: + rv32: + accessible: false + rv64: + accessible: true + fflags: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - fflags[4:0] in [0x00:0x1F] + wr_illegal: + - Unchanged + mtvec: + reset-val: 0x80010000 + rv64: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # The 62 bits of 'base' are suffixed with 2'b00 + # ==> all values are legal, alignment 4 bytes is implied + - base[61:0] in [0x00000000:0x3FFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # Only Direct mode. + - mode[1:0] in [0x0] + wr_illegal: + - Unchanged + vsstatus: + reset-val: 0x0 + rv64: + accessible: false + rv32: + accessible: false + mstatus: # FIXME verify details + reset-val: 0xA00001800 # .mpp = 0x3 + rv64: + accessible: true + uie: + implemented: true + sie: + implemented: true + mie: + implemented: true + upie: + implemented: true + spie: + implemented: true + sxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - sxl[1:0] in [0x2] + wr_illegal: + - unchanged + uxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - uxl[1:0] in [0x2] + wr_illegal: + - unchanged + mpie: + implemented: true + mpp: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mpp[1:0] in [0x3] + wr_illegal: + - Unchanged + fs: + implemented: true + xs: + implemented: true + mprv: + implemented: false + sum: + implemented: true + mxr: + implemented: true + tvm: + implemented: false + tw: + implemented: false + tsr: + implemented: false + rv32: + accessible: false + mip: # Check if readonly or not + reset-val: 0 + rv64: + accessible: true + usip: + implemented: true + ssip: + implemented: true + msip: + implemented: true + utip: + implemented: true + stip: + implemented: true + mtip: + implemented: true + type: + ro_variable: true + ueip: + implemented: true + seip: + implemented: true + meip: + implemented: true + type: + ro_variable: true + rv32: + accessible: false + hip: + reset-val: 0 + rv64: + accessible: false + vssip: + implemented: false + vstip: + implemented: false + vseip: + implemented: false + sgeip: + implemented: false + rv32: + accessible: false + mie: + reset-val: 0 + rv64: + accessible: true + usie: + implemented: true + ssie: + implemented: true + msie: + implemented: true + utie: + implemented: true + stie: + implemented: true + mtie: + implemented: true + ueie: + implemented: true + seie: + implemented: true + meie: + implemented: true + rv32: + accessible: false + hie: + reset-val: 0 + rv64: + accessible: false + vssie: + implemented: false + vstie: + implemented: false + vseie: + implemented: false + sgeie: + implemented: false + rv32: + accessible: false + mepc: + reset-val: 0x0 + rv64: + accessible: true + rv32: + accessible: false + mtval: + reset-val: 0x0 + rv64: + accessible: true + rv32: + accessible: false + mcause: + reset-val: 0 + rv64: + accessible: true + interrupt: + implemented: true + exception_code: + implemented: true + rv32: + accessible: false + medeleg: + reset-val: 0 + rv64: + accessible: true + rv32: + accessible: false + mideleg: + reset-val: 0 + rv64: + accessible: true + rv32: + accessible: false + menvcfg: #FIXME: not convinced if it is needed + reset-val: 0 + rv64: + accessible: true + rv32: + accessible: false + marchid: + rv64: + accessible: true + type: + ro_constant: 0x00000003 + rv32: + accessible: false + reset-val: 0x00000003 + # FIXME not supported yet + # mconfigptr: + # rv64: + # accessible: true + # type: + # ro_constant: 0x0 + # rv32: + # accessible: false + # reset-val: 0x0 + mhartid: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x00 + mhpmcounter3: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter4: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter5: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter6: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter7: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter8: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter9: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter10: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter11: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter12: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter13: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter14: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter15: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter16: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter17: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter18: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter19: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter20: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter21: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter22: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter23: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter24: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter25: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter26: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter27: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter28: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter29: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter30: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter31: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + # FIXME NOT SUPPORTED + # instret: + # rv64: + # accessible: true + # type: + # warl: + # dependency_fields: [] + # legal: + # - instret[31:0] in [0x00000000:0xFFFFFFFF] + # wr_illegal: + # - unchanged + # rv32: + # accessible: false + # reset-val: 0 + mcountinhibit: #FIXME Details + rv64: + accessible: true + rv32: + accessible: false + reset-val: 0x0 + mhpmevent3: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent4: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent5: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent6: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent7: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent8: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent9: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent10: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent11: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent12: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent13: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent14: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent15: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent16: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent17: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent18: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent19: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent20: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent21: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent22: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent23: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent24: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent25: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent26: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent27: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent28: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent29: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent30: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent31: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mimpid: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + mcounteren: #FIXME Check details + rv64: + accessible: true + rv32: + accessible: false + reset-val: 0 + pmpcfg0: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp0cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp0cfg] + legal: + - "pmp0cfg[7] in [0] -> pmp0cfg[7] in [0x0:0x1] pmp0cfg[6:5] in [0] pmp0cfg[4:3] not in [2] pmp0cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp1cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp1cfg] + legal: + - "pmp1cfg[7] in [0] -> pmp1cfg[7] in [0x0,0x1] pmp1cfg[6:5] in [0] pmp1cfg[4:3] not in [2] pmp1cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp2cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp2cfg] + legal: + - "pmp2cfg[7] in [0] -> pmp2cfg[7] in [0x0,0x1] pmp2cfg[6:5] in [0] pmp2cfg[4:3] not in [2] pmp2cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp3cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp3cfg] + legal: + - "pmp3cfg[7] in [0] -> pmp3cfg[7] in [0x0,0x1] pmp3cfg[6:5] in [0] pmp3cfg[4:3] not in [2] pmp3cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp4cfg: + implemented: true + type: + ro_constant: 0 + pmp5cfg: + implemented: true + type: + ro_constant: 0 + pmp6cfg: + implemented: true + type: + ro_constant: 0 + pmp7cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg2: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp8cfg: + implemented: true + type: + ro_constant: 0 + pmp9cfg: + implemented: true + type: + ro_constant: 0 + pmp10cfg: + implemented: true + type: + ro_constant: 0 + pmp11cfg: + implemented: true + type: + ro_constant: 0 + pmp12cfg: + implemented: true + type: + ro_constant: 0 + pmp13cfg: + implemented: true + type: + ro_constant: 0 + pmp14cfg: + implemented: true + type: + ro_constant: 0 + pmp15cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg4: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp16cfg: + implemented: true + type: + ro_constant: 0 + pmp17cfg: + implemented: true + type: + ro_constant: 0 + pmp18cfg: + implemented: true + type: + ro_constant: 0 + pmp19cfg: + implemented: true + type: + ro_constant: 0 + pmp20cfg: + implemented: true + type: + ro_constant: 0 + pmp21cfg: + implemented: true + type: + ro_constant: 0 + pmp22cfg: + implemented: true + type: + ro_constant: 0 + pmp23cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg6: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp24cfg: + implemented: true + type: + ro_constant: 0 + pmp25cfg: + implemented: true + type: + ro_constant: 0 + pmp26cfg: + implemented: true + type: + ro_constant: 0 + pmp27cfg: + implemented: true + type: + ro_constant: 0 + pmp28cfg: + implemented: true + type: + ro_constant: 0 + pmp29cfg: + implemented: true + type: + ro_constant: 0 + pmp30cfg: + implemented: true + type: + ro_constant: 0 + pmp31cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg8: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp32cfg: + implemented: true + type: + ro_constant: 0 + pmp33cfg: + implemented: true + type: + ro_constant: 0 + pmp34cfg: + implemented: true + type: + ro_constant: 0 + pmp35cfg: + implemented: true + type: + ro_constant: 0 + pmp36cfg: + implemented: true + type: + ro_constant: 0 + pmp37cfg: + implemented: true + type: + ro_constant: 0 + pmp38cfg: + implemented: true + type: + ro_constant: 0 + pmp39cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg10: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp40cfg: + implemented: true + type: + ro_constant: 0 + pmp41cfg: + implemented: true + type: + ro_constant: 0 + pmp42cfg: + implemented: true + type: + ro_constant: 0 + pmp43cfg: + implemented: true + type: + ro_constant: 0 + pmp44cfg: + implemented: true + type: + ro_constant: 0 + pmp45cfg: + implemented: true + type: + ro_constant: 0 + pmp46cfg: + implemented: true + type: + ro_constant: 0 + pmp47cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg12: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp48cfg: + implemented: true + type: + ro_constant: 0 + pmp49cfg: + implemented: true + type: + ro_constant: 0 + pmp50cfg: + implemented: true + type: + ro_constant: 0 + pmp51cfg: + implemented: true + type: + ro_constant: 0 + pmp52cfg: + implemented: true + type: + ro_constant: 0 + pmp53cfg: + implemented: true + type: + ro_constant: 0 + pmp54cfg: + implemented: true + type: + ro_constant: 0 + pmp55cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg14: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp56cfg: + implemented: true + type: + ro_constant: 0 + pmp57cfg: + implemented: true + type: + ro_constant: 0 + pmp58cfg: + implemented: true + type: + ro_constant: 0 + pmp59cfg: + implemented: true + type: + ro_constant: 0 + pmp60cfg: + implemented: true + type: + ro_constant: 0 + pmp61cfg: + implemented: true + type: + ro_constant: 0 + pmp62cfg: + implemented: true + type: + ro_constant: 0 + pmp63cfg: + implemented: true + type: + ro_constant: 0 + mcycle: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycle[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + minstret: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstret[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr0: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr0[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr1: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr1[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr2: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr2[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr3: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr3[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr4: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr4[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr5: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr5[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr6: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr6[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr7: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr7[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr8: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr9: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr10: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr11: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr12: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr13: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr14: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr15: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr16: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr17: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr18: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr19: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr20: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr21: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr22: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr23: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr24: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr25: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr26: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr27: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr28: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr29: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr30: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr31: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr32: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr33: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr34: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr35: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr36: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr37: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr38: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr39: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr40: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr41: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr42: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr43: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr44: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr45: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr46: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr47: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr48: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr49: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr50: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr51: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr52: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr53: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr54: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr55: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr56: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr57: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr58: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr59: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr60: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr61: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr62: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr63: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + satp: + rv32: + accessible: false + rv64: + accessible: true + ppn: + type: + warl: + dependency_fields: [] + legal: + - "ppn[43:0] in [0x00000000000:0xFFFFFFFFFFF]" + wr_illegal: + - Unchanged + asid: + type: + warl: + dependency_fields: [] + legal: + - "asid[15:0] in [0x0000:0x00FF]" + wr_illegal: + - Unchanged + mode: + type: + warl: + dependency_fields: [] + legal: + - "mode[3:0] in [0,8]" + wr_illegal: + - Unchanged + reset-val: 0x0000000000000000 + scause: + rv32: + accessible: false + rv64: + accessible: true + exception_code: + implemented: True + interrupt: + implemented: True + reset-val: 0 + senvcfg: + rv32: + accessible: false + rv64: + accessible: true + reset-val: 0 + sepc: + rv32: + accessible: false + rv64: + accessible: true + reset-val: 0 + sie: #FIXME Check if readonly or not + reset-val: 0 + rv64: + accessible: true + ssie: + implemented: true + stie: + implemented: true + seie: + implemented: true + rv32: + accessible: false + sip: #FIXME Check if readonly or not + reset-val: 0 + rv64: + accessible: true + ssip: + implemented: true + stip: + implemented: true + seip: + implemented: true + rv32: + accessible: false + sscratch: + rv64: + accessible: true + rv32: + accessible: false + sstatus: + reset-val: 0x0 + rv64: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + # FIXME not supported yet + #uxl: + # implemented: true + # type: + # warl: + # dependency_fields: [] + # legal: + # - uxl[1:0] in [0x2] + # wr_illegal: + # - unchanged + sd: + implemented: true + rv32: + accessible: false + stval: + rv32: + accessible: false + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - stval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + reset-val: 0 + stvec: + reset-val: 0x80010000 + rv64: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # The 62 bits of 'base' are suffixed with 2'b00 + # ==> all values are legal, alignment 4 bytes is implied + - base[61:0] in [0x00000000:0x3FFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # Only Direct mode. + - mode[1:0] in [0x0] + wr_illegal: + - Unchanged + time: + rv64: + accessible: true + type: + ro_variable: true + rv32: + accessible: false + reset-val: 0 diff --git a/config/riscv-config/cv64a60ax/spec/platform_spec.yaml b/config/riscv-config/cv64a60ax/spec/platform_spec.yaml new file mode 100644 index 0000000000..23d847bf39 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/platform_spec.yaml @@ -0,0 +1,53 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Tanuj Khandelwal CEA (copied from riscv-config examples) + +nmi: + label: nmi_vector + # address: 12288 +reset: + label: reset_vector + # address: 16384 +mtime: + implemented: false +mtimecmp: + implemented: false + #mcause_non_standard: + # implemented: true +mtval_condition_writes: + implemented: false +scause_non_standard: + implemented: false +stval_condition_writes: + implemented: false +zicbo_cache_block_sz : + implemented: true + zicbom_sz: 64 + zicboz_sz: 64 + +#memory_map: +# - memory_region: +# name: bootrom +# base_addr: 0x10000 +# size: 0x10000 +# description: System boot ROM +# attributes: +# read_only: true +# cached: false +# - memory_region: +# name: dram +# base_addr: 0x80000000 +# size: 0x40000000 +# description: System (D)RAM diff --git a/core/include/cv64a60ax_config_pkg.sv b/core/include/cv64a60ax_config_pkg.sv new file mode 100644 index 0000000000..3631ef39ee --- /dev/null +++ b/core/include/cv64a60ax_config_pkg.sv @@ -0,0 +1,116 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales +// +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Author: Tanuj Khandelwal - CEA +// Date: Janvary, 2025 +// Description: CVA6 configuration package using the HPDcache as cache subsystem + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + localparam CVA6ConfigRvfiTrace = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigDataUserWidth = 32; + + +localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(64), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) + TechnoCut: bit'(0), + SuperscalarEn: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), + NrLoadBufEntries: unsigned'(8), + RVF: bit'(1), + RVD: bit'(1), + XF16: bit'(0), + XF16ALT: bit'(0), + XF8: bit'(0), + RVA: bit'(1), + RVB: bit'(1), + ZKN: bit'(1), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCMT: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(0), + XFVec: bit'(0), + CvxifEn: bit'(1), + RVZiCond: bit'(1), + RVZicntr: bit'(1), + RVZihpm: bit'(1), + NrScoreboardEntries: unsigned'(8), + PerfCounterEn: bit'(1), + MmuPresent: bit'(1), + RVS: bit'(1), + RVU: bit'(1), + SoftwareInterruptEn: bit'(0), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(4), + BTBEntries: unsigned'(16), + BHTEntries: unsigned'(64), + DmBaseAddress: 64'h0, + TvalEn: bit'(1), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(32768), + IcacheSetAssoc: unsigned'(8), + IcacheLineWidth: unsigned'(512), + DCacheType: config_pkg::HPDCACHE_WT, + DcacheByteSize: unsigned'(32768), + DcacheSetAssoc: unsigned'(8), + DcacheLineWidth: unsigned'(512), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), + DataUserEn: unsigned'(0), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(32), + FetchUserEn: unsigned'(0), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(0), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(3) +}; + +endpackage diff --git a/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv b/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv new file mode 100644 index 0000000000..6ab432b43d --- /dev/null +++ b/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv @@ -0,0 +1,188 @@ +/* + * Copyright 2019 Google LLC + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------- +// Processor feature configuration +//----------------------------------------------------------------------------- +// XLEN +parameter int XLEN = 64; + +// Parameter for SATP mode, set to BARE if address translation is not supported +parameter satp_mode_t SATP_MODE = SV39; + +// Supported Privileged mode +privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE}; + +// Unsupported instructions +riscv_instr_name_t unsupported_instr[]; + +// ISA supported by the processor +riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C, RV32A, RV64A, + RV32F, RV64F, RV32D, RV64D}; +// Interrupt mode support +mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +int max_interrupt_vector_num = 16; + +// Physical memory protection support +bit support_pmp = 0; + +// Enhanced physical memory protection support +bit support_epmp = 0; + +// Debug mode support +bit support_debug_mode = 0; + +// Support delegate trap to user mode +bit support_umode_trap = 0; + +// Support sfence.vma instruction +bit support_sfence = 1; + +// Support unaligned load/store +bit support_unaligned_load_store = 1'b1; + +// GPR setting +parameter int NUM_FLOAT_GPR = 32; +parameter int NUM_GPR = 32; +parameter int NUM_VEC_GPR = 32; + +// ---------------------------------------------------------------------------- +// Vector extension configuration +// ---------------------------------------------------------------------------- + +// Parameter for vector extension +parameter int VECTOR_EXTENSION_ENABLE = 0; + +parameter int VLEN = 512; + +// Maximum size of a single vector element +parameter int ELEN = 32; + +// Minimum size of a sub-element, which must be at most 8-bits. +parameter int SELEN = 8; + +// Maximum size of a single vector element (encoded in vsew format) +parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3; + +// Maxium LMUL supported by the core +parameter int MAX_LMUL = 8; + +// ---------------------------------------------------------------------------- +// Multi-harts configuration +// ---------------------------------------------------------------------------- + +// Number of harts +parameter int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Previleged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented previlieged CSR list +`ifdef DSIM +privileged_reg_t implemented_csr[] = { +`else +const privileged_reg_t implemented_csr[] = { +`endif + // User mode CSR + USTATUS, // User status + UIE, // User interrupt-enable register + UTVEC, // User trap-handler base address + USCRATCH, // Scratch register for user trap handlers + UEPC, // User exception program counter + UCAUSE, // User trap cause + UTVAL, // User bad address or instruction + UIP, // User interrupt pending + // Supervisor mode CSR + SSTATUS, // Supervisor status + SEDELEG, // Supervisor exception delegation register + SIDELEG, // Supervisor interrupt delegation register + SIE, // Supervisor interrupt-enable register + STVEC, // Supervisor trap-handler base address + SCOUNTEREN, // Supervisor counter enable + SSCRATCH, // Scratch register for supervisor trap handlers + SEPC, // Supervisor exception program counter + SCAUSE, // Supervisor trap cause + STVAL, // Supervisor bad address or instruction + SIP, // Supervisor interrupt pending + SATP, // Supervisor address translation and protection + // Machine mode mode CSR + MVENDORID, // Vendor ID + MARCHID, // Architecture ID + MIMPID, // Implementation ID + MHARTID, // Hardware thread ID + MSTATUS, // Machine status + MISA, // ISA and extensions + MEDELEG, // Machine exception delegation register + MIDELEG, // Machine interrupt delegation register + MIE, // Machine interrupt-enable register + MTVEC, // Machine trap-handler base address + MCOUNTEREN, // Machine counter enable + MSCRATCH, // Scratch register for machine trap handlers + MEPC, // Machine exception program counter + MCAUSE, // Machine trap cause + MTVAL, // Machine bad address or instruction + MIP, // Machine interrupt pending + // Floating point CSR + FCSR // Floating point control and status +}; + +// Implementation-specific custom CSRs +bit [11:0] custom_csr[] = { +}; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +`ifdef DSIM +interrupt_cause_t implemented_interrupt[] = { +`else +const interrupt_cause_t implemented_interrupt[] = { +`endif + U_SOFTWARE_INTR, + S_SOFTWARE_INTR, + M_SOFTWARE_INTR, + U_TIMER_INTR, + S_TIMER_INTR, + M_TIMER_INTR, + U_EXTERNAL_INTR, + S_EXTERNAL_INTR, + M_EXTERNAL_INTR +}; + +`ifdef DSIM +exception_cause_t implemented_exception[] = { +`else +const exception_cause_t implemented_exception[] = { +`endif + INSTRUCTION_ACCESS_FAULT, + ILLEGAL_INSTRUCTION, + BREAKPOINT, + LOAD_ADDRESS_MISALIGNED, + LOAD_ACCESS_FAULT, + STORE_AMO_ADDRESS_MISALIGNED, + STORE_AMO_ACCESS_FAULT, + ECALL_UMODE, + ECALL_SMODE, + ECALL_MMODE, + INSTRUCTION_PAGE_FAULT, + LOAD_PAGE_FAULT, + STORE_AMO_PAGE_FAULT +};