From d253686ad1f26f517fb62572b6964ebfff2b899d Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Fri, 28 Feb 2025 17:16:59 +1100 Subject: [PATCH] mmu: Use latched value to determine if misaligned exception occurred Adds to #2798. Sorry for noticing this only now. Signed-off-by: Nils Wistoff --- core/cva6_mmu/cva6_mmu.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 9b6f5ca568..eebb9b6e46 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -515,6 +515,9 @@ module cva6_mmu lsu_valid_o = lsu_req_q; lsu_exception_o = misaligned_ex_q; + // mute misaligned exceptions if there is no request otherwise they will throw accidental exceptions + misaligned_ex_n.valid = misaligned_ex_i.valid & lsu_req_i; + // we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal to bit [CVA6Cfg.SV] canonical_addr_check = (lsu_req_i && en_ld_st_translation_i && !((&lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)); @@ -538,7 +541,7 @@ module cva6_mmu lsu_dtlb_ppn_o = (CVA6Cfg.PPNW)'(lsu_vaddr_n[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):12]); // translation is enabled and no misaligned exception occurred - if ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !misaligned_ex_i.valid) begin + if ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !misaligned_ex_q.valid) begin lsu_valid_o = 1'b0; lsu_dtlb_ppn_o = (en_ld_st_g_translation_i && CVA6Cfg.RVH)? dtlb_g_content.ppn :dtlb_content.ppn;