From 7d922af35a52b42c5650c2bfd109f2c73b4cfe09 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Fri, 8 Nov 2024 17:52:12 +0100 Subject: [PATCH 01/13] add CVA6ConfigFpgaAltera parameter --- core/include/build_config_pkg.sv | 7 +- core/include/config_pkg.sv | 11 +- .../include/cv32a60x_config_pkg_deprecated.sv | 2 + core/include/cv32a65x_config_pkg.sv | 1 + .../cv32a6_embedded_config_pkg_deprecated.sv | 2 + .../cv32a6_ima_sv32_fpga_config_pkg.sv | 2 + core/include/cv32a6_imac_sv0_config_pkg.sv | 2 + core/include/cv32a6_imac_sv32_config_pkg.sv | 2 + core/include/cv32a6_imafc_sv32_config_pkg.sv | 2 + core/include/cv32a6_thales_avs_config_pkg.sv | 161 ++++++++++++++++++ .../cv64a6_imadfcv_sv39_polara_config_pkg.sv | 2 + core/include/cv64a6_imafdc_sv39_config_pkg.sv | 2 + .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 2 + ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 2 + .../cv64a6_imafdc_sv39_wb_config_pkg.sv | 2 + .../include/cv64a6_imafdch_sv39_config_pkg.sv | 2 + .../cv64a6_imafdch_sv39_wb_config_pkg.sv | 2 + .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 2 + core/include/cv64a6_mmu_config_pkg.sv | 1 + 19 files changed, 204 insertions(+), 5 deletions(-) create mode 100644 core/include/cv32a6_thales_avs_config_pkg.sv diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 629c96dc93..c40cbf383f 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -42,6 +42,7 @@ package build_config_pkg; cfg.VMID_WIDTH = (CVA6Cfg.XLEN == 64) ? 14 : 1; cfg.FpgaEn = CVA6Cfg.FpgaEn; + cfg.FpgaAltera = CVA6Cfg.FpgaAltera; cfg.TechnoCut = CVA6Cfg.TechnoCut; cfg.SuperscalarEn = CVA6Cfg.SuperscalarEn; @@ -75,7 +76,7 @@ package build_config_pkg; cfg.RVZicntr = CVA6Cfg.RVZicntr; cfg.RVZihpm = CVA6Cfg.RVZihpm; cfg.NR_SB_ENTRIES = CVA6Cfg.NrScoreboardEntries; - cfg.TRANS_ID_BITS = $clog2(CVA6Cfg.NrScoreboardEntries); + cfg.TRANS_ID_BITS = CVA6Cfg.NrScoreboardEntries > 1 ? $clog2(CVA6Cfg.NrScoreboardEntries) : CVA6Cfg.NrScoreboardEntries; cfg.FpPresent = bit'(FpPresent); cfg.NSX = bit'(NSX); @@ -122,7 +123,7 @@ package build_config_pkg; cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc; - cfg.ICACHE_SET_ASSOC_WIDTH = $clog2(CVA6Cfg.IcacheSetAssoc); + cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc; cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH; cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH; cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth; @@ -130,7 +131,7 @@ package build_config_pkg; cfg.DCacheType = CVA6Cfg.DCacheType; cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth; cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc; - cfg.DCACHE_SET_ASSOC_WIDTH = $clog2(CVA6Cfg.DcacheSetAssoc); + cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc; cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH; cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH; cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index f464f69542..dfa637f31f 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -170,6 +170,8 @@ package config_pkg; int unsigned FetchUserWidth; // Is FPGA optimization of CV32A6 bit FpgaEn; + // Is FPGA optimization for Altera FPGA + bit FpgaAltera; // Is Techno Cut instanciated bit TechnoCut; // Enable superscalar* with 2 issue ports and 2 commit ports. @@ -213,8 +215,13 @@ package config_pkg; int unsigned ASID_WIDTH; int unsigned VMID_WIDTH; - bit FpgaEn; - bit TechnoCut; + bit FpgaEn; + bit FpgaAltera; + bit TechnoCut; + /// Number of commit ports, i.e., maximum number of instructions that the + /// core can retire per cycle. It can be beneficial to have more commit + /// ports than issue ports, for the scoreboard to empty out in case one + /// instruction stalls a little longer. bit SuperscalarEn; int unsigned NrCommitPorts; diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv index c2637baf1e..de9dffcb39 100644 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ b/core/include/cv32a60x_config_pkg_deprecated.sv @@ -53,6 +53,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 4; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,6 +78,7 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index c886cfbf4c..eacc84a384 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -22,6 +22,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(0), + FpgaAltera: bit'(0), TechnoCut: bit'(1), SuperscalarEn: bit'(1), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index b8990ae566..93d8de533c 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -52,6 +52,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 4; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 0; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 25bf0290df..daa173cf00 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 4; localparam CVA6ConfigFpgaEn = 1; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index eb91ac01e2..165b1d1117 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -52,6 +52,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrLoadBufEntries = 2; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 0068eb1b55..0c3890e328 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 11eb14e9e4..987b487ef7 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_thales_avs_config_pkg.sv b/core/include/cv32a6_thales_avs_config_pkg.sv new file mode 100644 index 0000000000..ff0c2a12ee --- /dev/null +++ b/core/include/cv32a6_thales_avs_config_pkg.sv @@ -0,0 +1,161 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 32; + + localparam CVA6ConfigRVF = 0; + localparam CVA6ConfigF16En = 0; + localparam CVA6ConfigF16AltEn = 0; + localparam CVA6ConfigF8En = 0; + localparam CVA6ConfigFVecEn = 0; + + localparam CVA6ConfigCvxifEn = 0; + localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigZcbExtEn = 0; + localparam CVA6ConfigZcmpExtEn = 0; + localparam CVA6ConfigAExtEn = 1; + localparam CVA6ConfigHExtEn = 0; // always disabled + localparam CVA6ConfigBExtEn = 0; + localparam CVA6ConfigVExtEn = 0; + localparam CVA6ConfigRVZiCond = 0; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + + localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheSetAssoc = 4; + localparam CVA6ConfigIcacheLineWidth = 128; + localparam CVA6ConfigDcacheByteSize = 16384; + localparam CVA6ConfigDcacheSetAssoc = 4; + localparam CVA6ConfigDcacheLineWidth = 128; + + localparam CVA6ConfigDcacheIdWidth = 1; + localparam CVA6ConfigMemTidWidth = CVA6ConfigAxiIdWidth; + + localparam CVA6ConfigWtDcacheWbufDepth = 4; + + localparam CVA6ConfigSuperscalarEn = 0; + localparam CVA6ConfigNrCommitPorts = 1; + localparam CVA6ConfigNrScoreboardEntries = 4; + + localparam CVA6ConfigFpgaEn = 1; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + + localparam CVA6ConfigNrLoadPipeRegs = 1; + localparam CVA6ConfigNrStorePipeRegs = 0; + localparam CVA6ConfigNrLoadBufEntries = 2; + + localparam CVA6ConfigRASDepth = 2; + localparam CVA6ConfigBTBEntries = 32; + localparam CVA6ConfigBHTEntries = 128; + + localparam CVA6ConfigTvalEn = 1; + + localparam CVA6ConfigNrPMPEntries = 0; + + localparam CVA6ConfigPerfCounterEn = 1; + + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT; +// localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; + + localparam CVA6ConfigMmuPresent = 0; + + localparam CVA6ConfigRvfiTrace = 1; + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), + TechnoCut: bit'(0), + NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), + NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), + RVF: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVF), + XF16: bit'(CVA6ConfigF16En), + XF16ALT: bit'(CVA6ConfigF16AltEn), + XF8: bit'(CVA6ConfigF8En), + RVA: bit'(CVA6ConfigAExtEn), + RVB: bit'(CVA6ConfigBExtEn), + RVV: bit'(CVA6ConfigVExtEn), + RVC: bit'(CVA6ConfigCExtEn), + RVH: bit'(CVA6ConfigHExtEn), + RVZCB: bit'(CVA6ConfigZcbExtEn), + RVZCMP: bit'(CVA6ConfigZcmpExtEn), + XFVec: bit'(CVA6ConfigFVecEn), + CvxifEn: bit'(CVA6ConfigCvxifEn), + RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZicntr: bit'(0), + RVZihpm: bit'(0), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), + MmuPresent: bit'(CVA6ConfigMmuPresent), + RVS: bit'(1), + RVU: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(CVA6ConfigRASDepth), + BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BHTEntries: unsigned'(CVA6ConfigBHTEntries), + DmBaseAddress: 64'h0, + TvalEn: unsigned'(CVA6ConfigTvalEn), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + // idempotent region + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(3), + // DRAM, Boot ROM, Debug Module + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + // cached region + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), + IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), + IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, + DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), + DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), + DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DataUserEn: unsigned'(CVA6ConfigDataUserEn), + WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), + FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), + FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), + InstrTlbEntries: int'(2), + DataTlbEntries: int'(2), + UseSharedTlb: bit'(1), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), + NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), + DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) + }; + +endpackage diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 740fe251ea..3ca75c31de 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 40feaac7a5..e16af1d674 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index d71531f498..39b88a9597 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -58,6 +58,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -83,6 +84,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 6785fefd20..4250ce2897 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 99a886d9db..8a6baf0278 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index efb9636bb1..976df44c53 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 4156235a0b..30da14a0c9 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(0), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 5792767869..7ca227d6da 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -51,6 +51,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigFpgaEn = 0; + localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), + FpgaAltera: bit'(CVA6ConfigFpgaAltera), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index 3310f558c3..6a83697e83 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -29,6 +29,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), + FpgaAltera: bit'(0), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), From e706dad02d8efa86f4697658d5f5cfad5f0c1306 Mon Sep 17 00:00:00 2001 From: AngelaGonzalezMarino <135128652+AngelaGonzalezMarino@users.noreply.github.com> Date: Fri, 8 Nov 2024 17:54:22 +0100 Subject: [PATCH 02/13] Update core/include/config_pkg.sv Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --- core/include/config_pkg.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index dfa637f31f..0dadaec4cc 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -215,9 +215,9 @@ package config_pkg; int unsigned ASID_WIDTH; int unsigned VMID_WIDTH; - bit FpgaEn; - bit FpgaAltera; - bit TechnoCut; + bit FpgaEn; + bit FpgaAltera; + bit TechnoCut; /// Number of commit ports, i.e., maximum number of instructions that the /// core can retire per cycle. It can be beneficial to have more commit /// ports than issue ports, for the scoreboard to empty out in case one From 14e6f08a651924b17d65821602ea7d5e0876eb65 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Fri, 8 Nov 2024 18:31:45 +0100 Subject: [PATCH 03/13] use synchronous ram for altera fpga in instruction queue and axi adapter fifos --- core/cache_subsystem/wt_axi_adapter.sv | 10 +-- core/cva6_fifo_v3.sv | 71 ++++++++++++++----- core/frontend/instr_queue.sv | 12 ++-- core/include/build_config_pkg.sv | 9 ++- core/include/cv32a6_thales_avs_config_pkg.sv | 17 +++-- .../fpga-support/rtl/SyncDpRam_ind_r_w.sv | 59 +++++++++++++++ 6 files changed, 146 insertions(+), 32 deletions(-) create mode 100644 vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 14dade2b58..30fc2f7c35 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -311,8 +311,9 @@ module wt_axi_adapter end cva6_fifo_v3 #( - .dtype (icache_req_t), - .DEPTH (ReqFifoDepth), + .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .dtype(icache_req_t), + .DEPTH(ReqFifoDepth), .FPGA_EN(CVA6Cfg.FpgaEn) ) i_icache_data_fifo ( .clk_i (clk_i), @@ -329,8 +330,9 @@ module wt_axi_adapter ); cva6_fifo_v3 #( - .dtype (dcache_req_t), - .DEPTH (ReqFifoDepth), + .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .dtype(dcache_req_t), + .DEPTH(ReqFifoDepth), .FPGA_EN(CVA6Cfg.FpgaEn) ) i_dcache_data_fifo ( .clk_i (clk_i), diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index 25bb881e53..3e6c792eee 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -1,4 +1,5 @@ // Copyright 2018 ETH Zurich and University of Bologna. +// Copyright 2024 - PlanV Technologies for additionnal contribution. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -9,9 +10,12 @@ // specific language governing permissions and limitations under the License. // Author: Florian Zaruba +// Additional contributions by: +// Angela Gonzalez - PlanV Technologies module cva6_fifo_v3 #( parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter bit FPGA_ALTERA = 1'b0, // fifo is in fall-through mode parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 parameter type dtype = logic [DATA_WIDTH-1:0], @@ -46,6 +50,8 @@ module cva6_fifo_v3 #( logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q; // actual memory dtype [FifoDepth - 1:0] mem_n, mem_q; + dtype data_ft_n, data_ft_q; + logic first_word_n, first_word_q; // fifo ram signals for fpga target logic fifo_ram_we; @@ -71,12 +77,13 @@ module cva6_fifo_v3 #( read_pointer_n = read_pointer_q; write_pointer_n = write_pointer_q; status_cnt_n = status_cnt_q; + data_ft_n = data_ft_q; + first_word_n = first_word_q; if (FPGA_EN) begin fifo_ram_we = '0; - fifo_ram_read_address = read_pointer_q; fifo_ram_write_address = '0; fifo_ram_wdata = '0; - data_o = (DEPTH == 0) ? data_i : fifo_ram_rdata; + data_o = (DEPTH == 0) ? data_i : (first_word_q ? data_ft_q : fifo_ram_rdata); end else begin data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; mem_n = mem_q; @@ -89,6 +96,7 @@ module cva6_fifo_v3 #( fifo_ram_we = 1'b1; fifo_ram_write_address = write_pointer_q; fifo_ram_wdata = data_i; + first_word_n = FPGA_ALTERA && first_word_q && pop_i; end else begin // push the data onto the queue mem_n[write_pointer_q] = data_i; @@ -104,6 +112,8 @@ module cva6_fifo_v3 #( end if (pop_i && ~empty_o) begin + data_ft_n = data_i; + first_word_n = FPGA_EN && FPGA_ALTERA && first_word_q && push_i; // read from the queue is a default assignment // but increment the read pointer... if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0; @@ -116,14 +126,22 @@ module cva6_fifo_v3 #( if (push_i && pop_i && ~full_o && ~empty_o) status_cnt_n = status_cnt_q; // FIFO is in pass through mode -> do not change the pointers - if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin - data_o = data_i; + if ((FALL_THROUGH || (FPGA_EN && FPGA_ALTERA)) && (status_cnt_q == 0) && push_i) begin + if (FALL_THROUGH) data_o = data_i; + if (FPGA_EN && FPGA_ALTERA) begin + data_ft_n = data_i; + first_word_n = '1; + end if (pop_i) begin + first_word_n = '0; status_cnt_n = status_cnt_q; read_pointer_n = read_pointer_q; write_pointer_n = write_pointer_q; end end + + if (FPGA_EN) fifo_ram_read_address = (FPGA_ALTERA == 1) ? read_pointer_n : read_pointer_q; + end // sequential process @@ -132,32 +150,53 @@ module cva6_fifo_v3 #( read_pointer_q <= '0; write_pointer_q <= '0; status_cnt_q <= '0; + first_word_q <= '0; + data_ft_q <= '0; end else begin if (flush_i) begin read_pointer_q <= '0; write_pointer_q <= '0; status_cnt_q <= '0; + first_word_q <= '0; + data_ft_q <= '0; end else begin read_pointer_q <= read_pointer_n; write_pointer_q <= write_pointer_n; status_cnt_q <= status_cnt_n; + data_ft_q <= data_ft_n; + first_word_q <=first_word_n; end end end if (FPGA_EN) begin : gen_fpga_queue - AsyncDpRam #( - .ADDR_WIDTH(ADDR_DEPTH), - .DATA_DEPTH(DEPTH), - .DATA_WIDTH($bits(dtype)) - ) fifo_ram ( - .Clk_CI (clk_i), - .WrEn_SI (fifo_ram_we), - .RdAddr_DI(fifo_ram_read_address), - .WrAddr_DI(fifo_ram_write_address), - .WrData_DI(fifo_ram_wdata), - .RdData_DO(fifo_ram_rdata) - ); + if (FPGA_ALTERA) begin + SyncDpRam_ind_r_w #( + .ADDR_WIDTH(ADDR_DEPTH), + .DATA_DEPTH(DEPTH), + .DATA_WIDTH($bits(dtype)) + ) fifo_ram ( + .Clk_CI (clk_i), + .WrEn_SI (fifo_ram_we), + .RdAddr_DI(fifo_ram_read_address), + .WrAddr_DI(fifo_ram_write_address), + .WrData_DI(fifo_ram_wdata), + .RdData_DO(fifo_ram_rdata) + ); + end else begin + AsyncDpRam #( + .ADDR_WIDTH(ADDR_DEPTH), + .DATA_DEPTH(DEPTH), + .DATA_WIDTH($bits(dtype)) + ) fifo_ram ( + .Clk_CI (clk_i), + .WrEn_SI (fifo_ram_we), + .RdAddr_DI(fifo_ram_read_address), + .WrAddr_DI(fifo_ram_write_address), + .WrData_DI(fifo_ram_wdata), + .RdData_DO(fifo_ram_rdata) + ); + end end else begin : gen_asic_queue always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index 938473e264..1aaa918240 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -461,8 +461,9 @@ module instr_queue // Make sure we don't save any instructions if we couldn't save the address assign push_instr_fifo[i] = push_instr[i] & ~address_overflow; cva6_fifo_v3 #( - .DEPTH (ariane_pkg::FETCH_FIFO_DEPTH), - .dtype (instr_data_t), + .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .DEPTH(ariane_pkg::FETCH_FIFO_DEPTH), + .dtype(instr_data_t), .FPGA_EN(CVA6Cfg.FpgaEn) ) i_fifo_instr_data ( .clk_i (clk_i), @@ -489,9 +490,10 @@ module instr_queue end cva6_fifo_v3 #( - .DEPTH (ariane_pkg::FETCH_ADDR_FIFO_DEPTH), - .DATA_WIDTH(CVA6Cfg.VLEN), - .FPGA_EN (CVA6Cfg.FpgaEn) + .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .DEPTH (ariane_pkg::FETCH_ADDR_FIFO_DEPTH), + .DATA_WIDTH (CVA6Cfg.VLEN), + .FPGA_EN (CVA6Cfg.FpgaEn) ) i_fifo_address ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index c40cbf383f..f86baedb56 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -76,7 +76,8 @@ package build_config_pkg; cfg.RVZicntr = CVA6Cfg.RVZicntr; cfg.RVZihpm = CVA6Cfg.RVZihpm; cfg.NR_SB_ENTRIES = CVA6Cfg.NrScoreboardEntries; - cfg.TRANS_ID_BITS = CVA6Cfg.NrScoreboardEntries > 1 ? $clog2(CVA6Cfg.NrScoreboardEntries) : CVA6Cfg.NrScoreboardEntries; + cfg.TRANS_ID_BITS = CVA6Cfg.NrScoreboardEntries > 1 ? $clog2(CVA6Cfg.NrScoreboardEntries) : + CVA6Cfg.NrScoreboardEntries; cfg.FpPresent = bit'(FpPresent); cfg.NSX = bit'(NSX); @@ -123,7 +124,8 @@ package build_config_pkg; cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc; - cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc; + cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : + CVA6Cfg.IcacheSetAssoc; cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH; cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH; cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth; @@ -131,7 +133,8 @@ package build_config_pkg; cfg.DCacheType = CVA6Cfg.DCacheType; cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth; cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc; - cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc; + cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : + CVA6Cfg.DcacheSetAssoc; cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH; cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH; cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth; diff --git a/core/include/cv32a6_thales_avs_config_pkg.sv b/core/include/cv32a6_thales_avs_config_pkg.sv index ff0c2a12ee..38bcf482a1 100644 --- a/core/include/cv32a6_thales_avs_config_pkg.sv +++ b/core/include/cv32a6_thales_avs_config_pkg.sv @@ -70,7 +70,7 @@ package cva6_config_pkg; localparam CVA6ConfigPerfCounterEn = 1; localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT; -// localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; + // localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; localparam CVA6ConfigMmuPresent = 0; @@ -124,15 +124,24 @@ package cva6_config_pkg; PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region - NrNonIdempotentRules: unsigned'(2), + NrNonIdempotentRules: + unsigned'( + 2 + ), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), NonIdempotentLength: 1024'({64'b0, 64'b0}), NrExecuteRegionRules: unsigned'(3), // DRAM, Boot ROM, Debug Module - ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionAddrBase: + 1024'( + {64'h8000_0000, 64'h1_0000, 64'h0} + ), ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), // cached region - NrCachedRegionRules: unsigned'(1), + NrCachedRegionRules: + unsigned'( + 1 + ), CachedRegionAddrBase: 1024'({64'h8000_0000}), CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), diff --git a/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv b/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv new file mode 100644 index 0000000000..afddbcc7e4 --- /dev/null +++ b/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv @@ -0,0 +1,59 @@ +// Copyright 2024 PlanV Technologies +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses +// +// Inferable, Synchronous Dual-Port RAM, there are a write port and a read port fully independent +// +// +// This module is designed to work with both Xilinx, Microchip and Altera FPGA tools by following the respective +// guidelines: +// - Xilinx UG901 Vivado Design Suite User Guide: Synthesis +// - Inferring Microchip PolarFire RAM Blocks +// - Altera Quartus II Handbook Volume 1: Design and Synthesis (p. 768) +// +// Current Maintainers:: Angela Gonzalez - PlanV Technologies + +module SyncDpRam_ind_r_w +#( + parameter ADDR_WIDTH = 10, + parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower + parameter DATA_WIDTH = 32 +)( + input logic Clk_CI, + + // Write port + input logic WrEn_SI, + input logic [ADDR_WIDTH-1:0] WrAddr_DI, + input logic [DATA_WIDTH-1:0] WrData_DI, + + // Read port + input logic [ADDR_WIDTH-1:0] RdAddr_DI, + output logic [DATA_WIDTH-1:0] RdData_DO +); + +// logic [DATA_WIDTH-1:0] mem [DATA_DEPTH-1:0]= '{default:0}; +(* ramstyle = "mlab" *) logic [DATA_WIDTH-1:0] mem [DATA_DEPTH-1:0]= '{default:0}; + + // WRITE + always_ff @(posedge Clk_CI) + begin + if (WrEn_SI) begin + mem[WrAddr_DI] <= WrData_DI; + end + RdData_DO = mem[RdAddr_DI]; + end + + //////////////////////////// + // assertions + //////////////////////////// + + // pragma translate_off + assert property + (@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH))) + else $error("depth out of bounds"); + // pragma translate_on + +endmodule \ No newline at end of file From 04dce533a3efbfdd0bc247a9ac332ab0b7544bf1 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Tue, 12 Nov 2024 16:07:06 +0100 Subject: [PATCH 04/13] remove unnecessary files --- core/include/cv32a6_thales_avs_config_pkg.sv | 161 ------------------- 1 file changed, 161 deletions(-) delete mode 100644 core/include/cv32a6_thales_avs_config_pkg.sv diff --git a/core/include/cv32a6_thales_avs_config_pkg.sv b/core/include/cv32a6_thales_avs_config_pkg.sv deleted file mode 100644 index ff0c2a12ee..0000000000 --- a/core/include/cv32a6_thales_avs_config_pkg.sv +++ /dev/null @@ -1,161 +0,0 @@ -// Copyright 2021 Thales DIS design services SAS -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// You may obtain a copy of the License at https://solderpad.org/licenses/ -// -// Original Author: Jean-Roch COULON - Thales - - -package cva6_config_pkg; - - localparam CVA6ConfigXlen = 32; - - localparam CVA6ConfigRVF = 0; - localparam CVA6ConfigF16En = 0; - localparam CVA6ConfigF16AltEn = 0; - localparam CVA6ConfigF8En = 0; - localparam CVA6ConfigFVecEn = 0; - - localparam CVA6ConfigCvxifEn = 0; - localparam CVA6ConfigCExtEn = 1; - localparam CVA6ConfigZcbExtEn = 0; - localparam CVA6ConfigZcmpExtEn = 0; - localparam CVA6ConfigAExtEn = 1; - localparam CVA6ConfigHExtEn = 0; // always disabled - localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigVExtEn = 0; - localparam CVA6ConfigRVZiCond = 0; - - localparam CVA6ConfigAxiIdWidth = 4; - localparam CVA6ConfigAxiAddrWidth = 64; - localparam CVA6ConfigAxiDataWidth = 64; - localparam CVA6ConfigFetchUserEn = 0; - localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; - localparam CVA6ConfigDataUserEn = 0; - localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; - - localparam CVA6ConfigIcacheByteSize = 16384; - localparam CVA6ConfigIcacheSetAssoc = 4; - localparam CVA6ConfigIcacheLineWidth = 128; - localparam CVA6ConfigDcacheByteSize = 16384; - localparam CVA6ConfigDcacheSetAssoc = 4; - localparam CVA6ConfigDcacheLineWidth = 128; - - localparam CVA6ConfigDcacheIdWidth = 1; - localparam CVA6ConfigMemTidWidth = CVA6ConfigAxiIdWidth; - - localparam CVA6ConfigWtDcacheWbufDepth = 4; - - localparam CVA6ConfigSuperscalarEn = 0; - localparam CVA6ConfigNrCommitPorts = 1; - localparam CVA6ConfigNrScoreboardEntries = 4; - - localparam CVA6ConfigFpgaEn = 1; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective - - localparam CVA6ConfigNrLoadPipeRegs = 1; - localparam CVA6ConfigNrStorePipeRegs = 0; - localparam CVA6ConfigNrLoadBufEntries = 2; - - localparam CVA6ConfigRASDepth = 2; - localparam CVA6ConfigBTBEntries = 32; - localparam CVA6ConfigBHTEntries = 128; - - localparam CVA6ConfigTvalEn = 1; - - localparam CVA6ConfigNrPMPEntries = 0; - - localparam CVA6ConfigPerfCounterEn = 1; - - localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT; -// localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE; - - localparam CVA6ConfigMmuPresent = 0; - - localparam CVA6ConfigRvfiTrace = 1; - - localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ - XLEN: unsigned'(CVA6ConfigXlen), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), - TechnoCut: bit'(0), - NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), - AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), - AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), - AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), - AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), - MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), - NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), - RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), - XF16: bit'(CVA6ConfigF16En), - XF16ALT: bit'(CVA6ConfigF16AltEn), - XF8: bit'(CVA6ConfigF8En), - RVA: bit'(CVA6ConfigAExtEn), - RVB: bit'(CVA6ConfigBExtEn), - RVV: bit'(CVA6ConfigVExtEn), - RVC: bit'(CVA6ConfigCExtEn), - RVH: bit'(CVA6ConfigHExtEn), - RVZCB: bit'(CVA6ConfigZcbExtEn), - RVZCMP: bit'(CVA6ConfigZcmpExtEn), - XFVec: bit'(CVA6ConfigFVecEn), - CvxifEn: bit'(CVA6ConfigCvxifEn), - RVZiCond: bit'(CVA6ConfigRVZiCond), - RVZicntr: bit'(0), - RVZihpm: bit'(0), - NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), - PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), - MmuPresent: bit'(CVA6ConfigMmuPresent), - RVS: bit'(1), - RVU: bit'(1), - HaltAddress: 64'h800, - ExceptionAddress: 64'h808, - RASDepth: unsigned'(CVA6ConfigRASDepth), - BTBEntries: unsigned'(CVA6ConfigBTBEntries), - BHTEntries: unsigned'(CVA6ConfigBHTEntries), - DmBaseAddress: 64'h0, - TvalEn: unsigned'(CVA6ConfigTvalEn), - DirectVecOnly: bit'(0), - NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {16{64'h0}}, - PMPAddrRstVal: {16{64'h0}}, - PMPEntryReadOnly: 16'd0, - NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, - // idempotent region - NrNonIdempotentRules: unsigned'(2), - NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), - NonIdempotentLength: 1024'({64'b0, 64'b0}), - NrExecuteRegionRules: unsigned'(3), - // DRAM, Boot ROM, Debug Module - ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), - ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), - // cached region - NrCachedRegionRules: unsigned'(1), - CachedRegionAddrBase: 1024'({64'h8000_0000}), - CachedRegionLength: 1024'({64'h40000000}), - MaxOutstandingStores: unsigned'(7), - DebugEn: bit'(1), - AxiBurstWriteEn: bit'(0), - IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), - IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), - IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), - DCacheType: CVA6ConfigDcacheType, - DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), - DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), - DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), - DataUserEn: unsigned'(CVA6ConfigDataUserEn), - WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), - FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), - FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), - InstrTlbEntries: int'(2), - DataTlbEntries: int'(2), - UseSharedTlb: bit'(1), - SharedTlbDepth: int'(64), - NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), - NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), - DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) - }; - -endpackage From fc65f0b5dd8ecabd269e858061f022345bd83822 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Tue, 12 Nov 2024 16:09:28 +0100 Subject: [PATCH 05/13] remove old comment --- core/include/config_pkg.sv | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 0dadaec4cc..f6e31db34b 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -218,11 +218,7 @@ package config_pkg; bit FpgaEn; bit FpgaAltera; bit TechnoCut; - /// Number of commit ports, i.e., maximum number of instructions that the - /// core can retire per cycle. It can be beneficial to have more commit - /// ports than issue ports, for the scoreboard to empty out in case one - /// instruction stalls a little longer. - + bit SuperscalarEn; int unsigned NrCommitPorts; int unsigned NrIssuePorts; From 3682f6193b88c050bdfaca34ff04939ecaf4f3a0 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Tue, 12 Nov 2024 16:24:57 +0100 Subject: [PATCH 06/13] Change FpgaAltera parameter to FpgaAlteraEn --- core/include/build_config_pkg.sv | 4 ++-- core/include/config_pkg.sv | 4 ++-- core/include/cv32a60x_config_pkg_deprecated.sv | 6 +++--- core/include/cv32a65x_config_pkg.sv | 2 +- core/include/cv32a6_embedded_config_pkg_deprecated.sv | 6 +++--- core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 6 +++--- core/include/cv32a6_imac_sv0_config_pkg.sv | 6 +++--- core/include/cv32a6_imac_sv32_config_pkg.sv | 6 +++--- core/include/cv32a6_imafc_sv32_config_pkg.sv | 6 +++--- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdc_sv39_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdch_sv39_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv | 6 +++--- core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 6 +++--- core/include/cv64a6_mmu_config_pkg.sv | 2 +- 18 files changed, 48 insertions(+), 48 deletions(-) diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index c40cbf383f..5d4808bb1c 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -42,7 +42,7 @@ package build_config_pkg; cfg.VMID_WIDTH = (CVA6Cfg.XLEN == 64) ? 14 : 1; cfg.FpgaEn = CVA6Cfg.FpgaEn; - cfg.FpgaAltera = CVA6Cfg.FpgaAltera; + cfg.FpgaAlteraEn = CVA6Cfg.FpgaAlteraEn; cfg.TechnoCut = CVA6Cfg.TechnoCut; cfg.SuperscalarEn = CVA6Cfg.SuperscalarEn; @@ -76,7 +76,7 @@ package build_config_pkg; cfg.RVZicntr = CVA6Cfg.RVZicntr; cfg.RVZihpm = CVA6Cfg.RVZihpm; cfg.NR_SB_ENTRIES = CVA6Cfg.NrScoreboardEntries; - cfg.TRANS_ID_BITS = CVA6Cfg.NrScoreboardEntries > 1 ? $clog2(CVA6Cfg.NrScoreboardEntries) : CVA6Cfg.NrScoreboardEntries; + cfg.TRANS_ID_BITS = $clog2(CVA6Cfg.NrScoreboardEntries); cfg.FpPresent = bit'(FpPresent); cfg.NSX = bit'(NSX); diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index f6e31db34b..224447546c 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -171,7 +171,7 @@ package config_pkg; // Is FPGA optimization of CV32A6 bit FpgaEn; // Is FPGA optimization for Altera FPGA - bit FpgaAltera; + bit FpgaAlteraEn; // Is Techno Cut instanciated bit TechnoCut; // Enable superscalar* with 2 issue ports and 2 commit ports. @@ -218,7 +218,7 @@ package config_pkg; bit FpgaEn; bit FpgaAltera; bit TechnoCut; - + bit SuperscalarEn; int unsigned NrCommitPorts; int unsigned NrIssuePorts; diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv index de9dffcb39..d4773c3ec5 100644 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ b/core/include/cv32a60x_config_pkg_deprecated.sv @@ -52,8 +52,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrCommitPorts = 1; localparam CVA6ConfigNrScoreboardEntries = 4; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -78,7 +78,7 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index eacc84a384..d9d028fa16 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -22,7 +22,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(0), - FpgaAltera: bit'(0), + FpgaAlteraEn: bit'(0), TechnoCut: bit'(1), SuperscalarEn: bit'(1), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index 93d8de533c..50c938bd0c 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -51,8 +51,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrCommitPorts = 1; localparam CVA6ConfigNrScoreboardEntries = 4; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 0; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index daa173cf00..0b66b20569 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 4; - localparam CVA6ConfigFpgaEn = 1; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 165b1d1117..27cb05ce6f 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -51,8 +51,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigNrLoadBufEntries = 2; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 0c3890e328..ddb1778ff1 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 987b487ef7..5497f3f8b2 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 3ca75c31de..aea391290a 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index e16af1d674..a11d7ea990 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 39b88a9597..1e9cb027e2 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -57,8 +57,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -84,7 +84,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 4250ce2897..9990751ca8 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 8a6baf0278..43ff7614c5 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index 976df44c53..b1ac37be24 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 30da14a0c9..d2075ff2aa 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(0), + FpgaAlteraEn: bit'(0), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 7ca227d6da..4312669b1d 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -50,8 +50,8 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 0; - localparam CVA6ConfigFpgaAltera = 0; //usually disabled, default is xilinx. Needs FpgaEn =1 to be effective + localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera + localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -77,7 +77,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAltera: bit'(CVA6ConfigFpgaAltera), + FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index 6a83697e83..8e0b686386 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -29,7 +29,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), - FpgaAltera: bit'(0), + FpgaAlteraEn: bit'(0), TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), From df8c95ec47adffa1bd2c1ef74a1c7915fb7ee961 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Tue, 12 Nov 2024 16:44:29 +0100 Subject: [PATCH 07/13] remove localparams for FpgaEn and FpgaAlteraEn parameters --- core/include/config_pkg.sv | 2 +- core/include/cv32a60x_config_pkg_deprecated.sv | 7 ++----- core/include/cv32a6_embedded_config_pkg_deprecated.sv | 7 ++----- core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 7 ++----- core/include/cv32a6_imac_sv0_config_pkg.sv | 7 ++----- core/include/cv32a6_imac_sv32_config_pkg.sv | 7 ++----- core/include/cv32a6_imafc_sv32_config_pkg.sv | 7 ++----- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdc_sv39_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdch_sv39_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv | 7 ++----- core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 7 ++----- 15 files changed, 29 insertions(+), 71 deletions(-) diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 224447546c..f75ab01149 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -216,7 +216,7 @@ package config_pkg; int unsigned VMID_WIDTH; bit FpgaEn; - bit FpgaAltera; + bit FpgaAlteraEn; bit TechnoCut; bit SuperscalarEn; diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv index d4773c3ec5..066869bf60 100644 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ b/core/include/cv32a60x_config_pkg_deprecated.sv @@ -52,9 +52,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrCommitPorts = 1; localparam CVA6ConfigNrScoreboardEntries = 4; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -77,8 +74,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index 50c938bd0c..4f248af75e 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -51,9 +51,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrCommitPorts = 1; localparam CVA6ConfigNrScoreboardEntries = 4; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 0; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 1; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 0b66b20569..b00eef97e6 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 4; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(1), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 27cb05ce6f..47b973e2bf 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -51,9 +51,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; localparam CVA6ConfigNrLoadBufEntries = 2; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index ddb1778ff1..bf68deeac3 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 5497f3f8b2..ac61e10816 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index aea391290a..3883688866 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index a11d7ea990..3c0e080027 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 1e9cb027e2..20ab297940 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -57,9 +57,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 8; @@ -83,8 +80,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 9990751ca8..554a21075e 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 43ff7614c5..e0f829aa0c 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index b1ac37be24..da9ca93a3c 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index d2075ff2aa..a9de5f8ffd 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(0), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 4312669b1d..e9f8db17cb 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -50,9 +50,6 @@ package cva6_config_pkg; localparam CVA6ConfigNrScoreboardEntries = 8; - localparam CVA6ConfigFpgaEn = 1; // for Xilinx and Altera - localparam CVA6ConfigFpgaAlteraEn = 1; // for Altera (only) - localparam CVA6ConfigNrLoadPipeRegs = 1; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; @@ -76,8 +73,8 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), - FpgaEn: bit'(CVA6ConfigFpgaEn), - FpgaAlteraEn: bit'(CVA6ConfigFpgaAlteraEn), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), From 85f682d8ba3d2b3061b574c7ed812248ad201724 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Tue, 12 Nov 2024 16:48:18 +0100 Subject: [PATCH 08/13] verible --- core/include/cv32a60x_config_pkg_deprecated.sv | 2 +- core/include/cv32a6_embedded_config_pkg_deprecated.sv | 2 +- core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 2 +- core/include/cv32a6_imac_sv0_config_pkg.sv | 2 +- core/include/cv32a6_imac_sv32_config_pkg.sv | 2 +- core/include/cv32a6_imafc_sv32_config_pkg.sv | 2 +- core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 2 +- core/include/cv64a6_imafdc_sv39_config_pkg.sv | 2 +- core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 2 +- core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 2 +- core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv | 2 +- core/include/cv64a6_imafdch_sv39_config_pkg.sv | 2 +- core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv | 2 +- core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv index 066869bf60..660e8c9f34 100644 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ b/core/include/cv32a60x_config_pkg_deprecated.sv @@ -75,7 +75,7 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index 4f248af75e..ff6a1fcd41 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index b00eef97e6..be7ff3ee14 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(1), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 47b973e2bf..2687370b26 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index bf68deeac3..9c2e622947 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index ac61e10816..6ad09136e4 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(32), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 3883688866..0422eef3bf 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 3c0e080027..8050e88f27 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 20ab297940..36c4397ade 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -81,7 +81,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 554a21075e..16f329c456 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index e0f829aa0c..b785da8296 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index da9ca93a3c..6e4d755ea1 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index a9de5f8ffd..49bc7693b2 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(2), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index e9f8db17cb..2c642f5345 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -74,7 +74,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), VLEN: unsigned'(64), FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) + FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(1), From 258d43c81ba13bd383cb5c254cb6c4e6dfa76386 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Tue, 12 Nov 2024 17:39:36 +0100 Subject: [PATCH 09/13] use FpgaAlteraEn parameter instead of FpgaAltera --- core/cache_subsystem/wt_axi_adapter.sv | 4 ++-- core/frontend/instr_queue.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 30fc2f7c35..6c5fe585f8 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -311,7 +311,7 @@ module wt_axi_adapter end cva6_fifo_v3 #( - .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), .dtype(icache_req_t), .DEPTH(ReqFifoDepth), .FPGA_EN(CVA6Cfg.FpgaEn) @@ -330,7 +330,7 @@ module wt_axi_adapter ); cva6_fifo_v3 #( - .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), .dtype(dcache_req_t), .DEPTH(ReqFifoDepth), .FPGA_EN(CVA6Cfg.FpgaEn) diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index 1aaa918240..ceac06bbe2 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -461,7 +461,7 @@ module instr_queue // Make sure we don't save any instructions if we couldn't save the address assign push_instr_fifo[i] = push_instr[i] & ~address_overflow; cva6_fifo_v3 #( - .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), .DEPTH(ariane_pkg::FETCH_FIFO_DEPTH), .dtype(instr_data_t), .FPGA_EN(CVA6Cfg.FpgaEn) @@ -490,7 +490,7 @@ module instr_queue end cva6_fifo_v3 #( - .FPGA_ALTERA(CVA6Cfg.FpgaAltera), + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), .DEPTH (ariane_pkg::FETCH_ADDR_FIFO_DEPTH), .DATA_WIDTH (CVA6Cfg.VLEN), .FPGA_EN (CVA6Cfg.FpgaEn) From 967a9acafaeab350b80f0e1d3da37017b1bfc14c Mon Sep 17 00:00:00 2001 From: AngelaGonzalezMarino <135128652+AngelaGonzalezMarino@users.noreply.github.com> Date: Tue, 12 Nov 2024 18:00:15 +0100 Subject: [PATCH 10/13] Update core/include/config_pkg.sv Co-authored-by: JeanRochCoulon --- core/include/config_pkg.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index f75ab01149..d711d5f262 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -168,7 +168,7 @@ package config_pkg; int unsigned FetchUserEn; // Width of fetch user field int unsigned FetchUserWidth; - // Is FPGA optimization of CV32A6 + // Is FPGA optimization of CV32A6 for Xilinx and Altera bit FpgaEn; // Is FPGA optimization for Altera FPGA bit FpgaAlteraEn; From 8278aaa4c532d24797a6ab120cecc4f2e746db7f Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Thu, 14 Nov 2024 12:46:14 +0100 Subject: [PATCH 11/13] update fpga_altera parameter comment --- core/cva6_fifo_v3.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index 3e6c792eee..8da99c72d0 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -15,7 +15,7 @@ module cva6_fifo_v3 #( parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode - parameter bit FPGA_ALTERA = 1'b0, // fifo is in fall-through mode + parameter bit FPGA_ALTERA = 1'b0, // FPGA Altera optimizations enabled parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 parameter type dtype = logic [DATA_WIDTH-1:0], From b664dfed6b14c55731fe5fd2769ee17894e034f6 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Thu, 14 Nov 2024 17:47:14 +0100 Subject: [PATCH 12/13] remove registers when fpga_altera not used --- core/cva6_fifo_v3.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index 8da99c72d0..81bfd20243 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -157,14 +157,14 @@ module cva6_fifo_v3 #( read_pointer_q <= '0; write_pointer_q <= '0; status_cnt_q <= '0; - first_word_q <= '0; - data_ft_q <= '0; + if (FPGA_ALTERA) first_word_q <= '0; + if (FPGA_ALTERA) data_ft_q <= '0; end else begin read_pointer_q <= read_pointer_n; write_pointer_q <= write_pointer_n; status_cnt_q <= status_cnt_n; - data_ft_q <= data_ft_n; - first_word_q <=first_word_n; + if (FPGA_ALTERA) data_ft_q <= data_ft_n; + if (FPGA_ALTERA) first_word_q <= first_word_n; end end end From cef743aaf724ce26ea53af4d0e24db2dce5eb6c3 Mon Sep 17 00:00:00 2001 From: AngelaGonzalezMarino <135128652+AngelaGonzalezMarino@users.noreply.github.com> Date: Thu, 14 Nov 2024 19:04:03 +0100 Subject: [PATCH 13/13] Update core/cva6_fifo_v3.sv Co-authored-by: JeanRochCoulon --- core/cva6_fifo_v3.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index 81bfd20243..4a9a560864 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -141,6 +141,7 @@ module cva6_fifo_v3 #( end if (FPGA_EN) fifo_ram_read_address = (FPGA_ALTERA == 1) ? read_pointer_n : read_pointer_q; + else fifo_ram_read_address = '0; end