FDIV FSQRT Rounding Mode Calculation Mismatches

[M31581]

FDIV and FSQRT rounding mode calculation mismatches found when comparing the results from FPnew to a RocketChip RISCV IMAF processor.

I have attached a few examples of calculation mismatches found:
FDIV FSQRT Rounding Mode Calculation Mismatches .xlsx

Note: I have added the solution from issue #47 since it fixed rounding mode issues found when testing against the RISCV Compliance tests, and I have found there are less rounding mode issues detected with it included.

Can you comment on my findings?

[MikeOpenHWGroup]

Thanks for reporting this @M31581, it is very much appreciated. As you may know cvfpu is under-going verification as part of the CV32E40Pv2 project. At this time cvfpu is not fully verified and it is not surprising that there are bugs. In particular, the SQRT function is known to have many issues.

We are working on it!