We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Hi there!
I've detected a bug in CVFPU.
A conversion from double to unsigned int fcvt.wu.d provides wrong results in some cases. I discovered the bug through cva6.
fcvt.wu.d
Here is an example RISC-V (rv64imfd) snippet:
.section ".text.init","ax",@progbits .globl _start .align 2 _start: # Enable the FPU li t0, 0x2000 csrs mstatus, t0 csrw fcsr,x0 la t0, .fdata0 fld ft0, (t0) fcvt.wu.d a0, ft0, rup li t0, 0x10 sd a0, (t0) sw x0, 0(x0) infinite_loop: j infinite_loop .section ".fdata0","ax",@progbits .8byte 0x41dfffffffc00001 # 2.14748e+09
We expect a0=0xffffffff80000000. I verified this with Spike. However, CVA6 gives a0=0x80000000.
a0=0xffffffff80000000
a0=0x80000000
.section ".text.init","ax",@progbits .globl _start .align 2 _start: # Enable the FPU li t0, 0x2000 csrs mstatus, t0 csrw fcsr,x0 la t0, .fdata0 fld ft0, (t0) fcvt.wu.d a0, ft0, rmm li t0, 0x10 sd a0, (t0) sw x0, 0(x0) infinite_loop: j infinite_loop .section ".fdata0","ax",@progbits .8byte 0x41efffffffffffff # 4.29497e+09
We expect a0=0xffffffffffffffff. I verified this with Spike. However, CVA6 gives a0=0.
a0=0xffffffffffffffff
a0=0
Thanks! Flavien
The text was updated successfully, but these errors were encountered:
No branches or pull requests
Hi there!
I've detected a bug in CVFPU.
Brief bug description
A conversion from double to unsigned int
fcvt.wu.d
provides wrong results in some cases.I discovered the bug through cva6.
Example instance 1
Here is an example RISC-V (rv64imfd) snippet:
Expected and actual results
We expect
a0=0xffffffff80000000
. I verified this with Spike.However, CVA6 gives
a0=0x80000000
.Example instance 2
Here is an example RISC-V (rv64imfd) snippet:
Expected and actual results
We expect
a0=0xffffffffffffffff
. I verified this with Spike.However, CVA6 gives
a0=0
.Thanks!
Flavien
The text was updated successfully, but these errors were encountered: