readme.md

FPGA flow

Installation and Overview of SandPiper

• SandPiper is a code generator that generates readable, well-structured, Verilog or SystemVerilog\ code from the given TL-Verilog code.
• SandPiper SaaS Edition runs as a microservice in the cloud to support easy open-source development. Install Sanpiper SaaS Edition for this project.
• To run locally, SandPiper Education Edition can be requested from RedwoodEDA

Steps to run FPGA setup

1. git clone https://github.com/BalaDhinesh/Virtual-FPGA-Lab.git

2. From your working directory run the shell script /<complete_path>/run.sh.

3. Three inputs will be asked by shell script

   a. Input file name of TL-Verilog file

   

   b. Board name (if board is not from given options then provide part number of board)

   If board is from given options:

   

   If board is not from given options:

   

   c. (Optional) If board is not from given options then constraints file should be present in your working directory as <filename_partno>.xdc.

   For example: From above iamge it should be design_xc7a100tcsg324-1.xdc

   d. Clock period (in ns)