diff --git a/CMakeLists.txt b/CMakeLists.txt
index 53fa5d109..b8a716ee9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -17,7 +17,7 @@ set(VERSION_MINOR 0)
 
 
 
-set(VERSION_PATCH 379)
+set(VERSION_PATCH 380)
 
 
 
diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc
index 0a8d1fd7f..d0cc5b223 100644
--- a/design_edit/src/rs_design_edit.cc
+++ b/design_edit/src/rs_design_edit.cc
@@ -1566,6 +1566,8 @@ struct DesignEditRapidSilicon : public ScriptPass {
           for (auto conn : cell->connections()) {
             IdString portName = conn.first;
             RTLIL::SigSpec actual = conn.second;
+            bool unset_port = true;
+            RTLIL::SigSpec sigspec;
             if (actual.is_chunk()) {
               RTLIL::Wire *wire = actual.as_chunk().wire;
               if (wire != NULL) {
@@ -1585,19 +1587,6 @@ struct DesignEditRapidSilicon : public ScriptPass {
                     }
                   }
                 }
-              } else {
-                RTLIL::SigSpec const_sig = actual;
-                if (GetSize(const_sig) != 0)
-                {
-                  RTLIL::SigSig new_conn;
-                  RTLIL::Wire *new_wire = original_mod->addWire(NEW_ID, GetSize(const_sig));
-                  cell->unsetPort(portName);
-                  cell->setPort(portName, new_wire);
-                  new_conn.first = new_wire;
-                  new_conn.second = const_sig;
-                  original_mod->connect(new_conn);
-                  process_wire(cell, portName, new_wire);
-                }
               }
             } else {
               for (auto it = actual.chunks().rbegin();
@@ -1623,6 +1612,32 @@ struct DesignEditRapidSilicon : public ScriptPass {
                 }
               }
             }
+            for (SigBit bit : conn.second)
+            {
+              // Route constant bits through fabric
+              if (bit.wire == nullptr)
+              {
+                if (unset_port)
+                {
+                  cell->unsetPort(portName);
+                  unset_port = false;
+                }
+                RTLIL::SigSig new_conn;
+                RTLIL::Wire *new_wire = original_mod->addWire(NEW_ID, 1);
+                new_conn.first = new_wire;
+                new_conn.second = bit;
+                original_mod->connect(new_conn);
+                new_outs.insert(new_wire->name.str());
+                sigspec.append(new_wire);
+              } else {
+                sigspec.append(bit);
+              }
+            }
+
+            if (!unset_port)
+            {
+              cell->setPort(portName, sigspec);
+            }
           }
         } else {
           for (auto conn : cell->connections()) {