From fc117f38bce4dc88f84857790a2049b6cd67e617 Mon Sep 17 00:00:00 2001 From: behzadmehmood <behzadmehmood82@gmail.com> Date: Thu, 28 Nov 2024 17:00:50 +0500 Subject: [PATCH] Correcting typo --- design_edit/src/rs_design_edit.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/design_edit/src/rs_design_edit.cc b/design_edit/src/rs_design_edit.cc index b6a4c9a8e..6f3ef7611 100644 --- a/design_edit/src/rs_design_edit.cc +++ b/design_edit/src/rs_design_edit.cc @@ -815,7 +815,7 @@ struct DesignEditRapidSilicon : public ScriptPass { string module_name = remove_backslashes(cell->type.str()); if (std::find(primitives.begin(), primitives.end(), module_name) != primitives.end()) { - //EDA-3010: output primitives cal also have danlging output wire + //EDA-3010: output primitives can also have danlging output wire //bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false; //if (is_out_prim) continue; // Upgrading dangling outs of input primtives to output ports