diff --git a/CMakeLists.txt b/CMakeLists.txt
index 910f13754..0eac3f8e0 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -16,7 +16,7 @@ set(VERSION_MAJOR 0)
 set(VERSION_MINOR 0)
 
 
-set(VERSION_PATCH 267)
+set(VERSION_PATCH 268)
 
 
 project(yosys_verific_rs)
diff --git a/RTL_Benchmark b/RTL_Benchmark
index 0980aef53..1b9edd8b5 160000
--- a/RTL_Benchmark
+++ b/RTL_Benchmark
@@ -1 +1 @@
-Subproject commit 0980aef536a02e1bfa1a156162e3e9cd6b625323
+Subproject commit 1b9edd8b5a4fdee2dded95aad87b1b9456098845
diff --git a/suites/yosys_validation/bram_valid.json b/suites/yosys_validation/bram_valid.json
index 29b3b06e3..ba86dc6c1 100644
--- a/suites/yosys_validation/bram_valid.json
+++ b/suites/yosys_validation/bram_valid.json
@@ -7,6 +7,12 @@
     "num_process": 4,
     "timeout": 1800,
     "benchmarks": {
+        "EDA-2292": {
+            "compile_status" : "active",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-2292/",
+            "top_module": "ram_simple_dp_dc_with_re_512x32"
+        },
         "EDA-1776": {
             "compile_status" : "active",
             "sim_status": "active",
@@ -182,7 +188,7 @@
             "top_module": "rams_sp_reg_addr_readmem_1024x1"
         },
         "EDA-1091": {
-            "compile_status" : "active",
+            "compile_status" : "inactive",
             "sim_status": "inactive",
             "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1091/",
             "top_module": "aes_256_sr_top"
@@ -318,6 +324,18 @@
             "sim_status": "inactive",
             "test_path": "RTL_Benchmark/Verilog/yosys_validation/EDA-1436",
             "top_module": "rams_sp_rf_rst_async_512x16_block"
+        },
+        "read_first_tdp_512x16": {
+            "compile_status" : "inactive",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/read_first_tdp_512x16/",
+            "top_module": "ram_true_dp_rf_512x16"
+        },
+        "read_first_tdp_if_if_512x16": {
+            "compile_status" : "inactive",
+            "sim_status": "active",
+            "test_path": "RTL_Benchmark/Verilog/yosys_validation/read_first_tdp_if_if_512x16/",
+            "top_module": "read_first_tdp_if_if_512x16"
         }
     }
 }
diff --git a/yosys b/yosys
index 65c41d693..a6793a5a5 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit 65c41d6936f3e1781f3b2dd9105f083f5ce200bf
+Subproject commit a6793a5a57a627face8ef5626d84475f5aafae22
diff --git a/yosys-rs-plugin b/yosys-rs-plugin
index 0a0868971..590b0290c 160000
--- a/yosys-rs-plugin
+++ b/yosys-rs-plugin
@@ -1 +1 @@
-Subproject commit 0a086897130972e1bf7f25c3ca1e49469fd91cf1
+Subproject commit 590b0290cd08075f0e7f9494aec4a593ba08b498