Gate clock low while RESET_N makes high transition (out of reset)

[aolofsson]

The reset issue is still visible in the E16 chips (rare but visible) and unfortunately it looks like we have the same problem in the E64. We need to implement a gating circuit in the FPGA to solve this problem cleanly. 100ns before and after the rising edge should be more than enough.

[Fred3]

The latest projects (to be pushed to github shortly) implement clock gating on reset in all configurations E16/E64 HDMI/headless 7020/7010. Initial results are positive.