diff --git a/docs/source/control_status_registers.rst b/docs/source/control_status_registers.rst index c8565e3fc..9ccfc070b 100644 --- a/docs/source/control_status_registers.rst +++ b/docs/source/control_status_registers.rst @@ -375,7 +375,7 @@ Detailed: +=============+===========+===========================================+ | 31:2 | URO | Start Address of the HWLoop 0/1. | +-------------+-----------+-------------------------------------------+ - | 1:0 | URO | Hardwired to 0. | + | 1:0 | URO | 0 | +-------------+-----------+-------------------------------------------+ HWLoop End Address 0/1 (``lpend0/1``) @@ -396,7 +396,7 @@ Detailed: +=============+===========+===========================================+ | 31:2 | URO | End Address of the HWLoop 0/1. | +-------------+-----------+-------------------------------------------+ - | 1:0 | URO | Hardwired to 0. | + | 1:0 | URO | 0 | +-------------+-----------+-------------------------------------------+ HWLoop Count Address 0/1 (``lpcount0/1``) @@ -441,9 +441,9 @@ Detailed: | | | | | | | SD set to 1 if **FS** = 11 meaning Floating point State is dirty so save/restore is needed in case of context switch. | | | | | - | | | Hardwired to 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). | + | | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 30:15 | RO | Unimplemented, hardwired to 0. | + | 30:15 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ | 14:13 | RW | **FS:** Floating point State | | | | | @@ -455,27 +455,27 @@ Detailed: | | | | | | | 11 = Dirty | | | | | - | | | Hardwired to 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). | + | | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ | 12:11 | RO | **MPP:** Machine Previous Priviledge mode | | | | | - | | | Hardwired to 11 when the user mode is not enabled. | + | | | 11 when the user mode is not enabled. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 10:8 | RO | Unimplemented, hardwired to 0. | + | 10:8 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ | 7 | RO | **MPIE:** Machine Previous Interrupt Enable | | | | | | | | When an exception is encountered, MPIE will be set to MIE. | | | | When the mret instruction is executed, the value of MPIE will be stored to MIE. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 6:4 | RO | Unimplemented, hardwired to 0. | + | 6:4 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ | 3 | RW | **MIE:** Machine Interrupt Enable | | | | | | | | If you want to enable interrupt handling in your exception handler, | | | | set the Interrupt Enable MIE to 1 inside your handler code. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ - | 2:0 | RO | Unimplemented, hardwired to 0. | + | 2:0 | RO | 0, Unimplemented. | +-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+ .. only:: USER @@ -519,25 +519,25 @@ Detailed: | | | | | | | Set bit x to enable interrupt irq_i[x] (x between 16 and 31). | +-------------+-----------+------------------------------------------------------------------------------------------+ - | 15:12 | RO | Hardwired to 0. | + | 15:12 | RO | 0 | +-------------+-----------+------------------------------------------------------------------------------------------+ | 11 | RW | **MEIE:** Machine External Interrupt Enable | | | | | | | | If set, irq_i[11] is enabled. | +-------------+-----------+------------------------------------------------------------------------------------------+ - | 10:8 | RO | Hardwired to 0. | + | 10:8 | RO | 0 | +-------------+-----------+------------------------------------------------------------------------------------------+ | 7 | RW | **MTIE:** Machine Timer Interrupt Enable | | | | | | | | If set, irq_i[7] is enabled. | +-------------+-----------+------------------------------------------------------------------------------------------+ - | 6:4 | RO | Hardwired to 0. | + | 6:4 | RO | 0 | +-------------+-----------+------------------------------------------------------------------------------------------+ | 3 | RW | **MSIE:** Machine Software Interrupt Enable | | | | | | | | If set, irq_i[3] is enabled. | +-------------+-----------+------------------------------------------------------------------------------------------+ - | 2:0 | RO | Hardwired to 0. | + | 2:0 | RO | 0 | +-------------+-----------+------------------------------------------------------------------------------------------+ .. _csr-mtvec: @@ -695,25 +695,25 @@ Detailed: | | | | | | | If bit x is set, interrupt irq_i[x] is pending (x between 16 and 31). | +-------------+-----------+---------------------------------------------------------------------------------------------------+ - | 15:12 | RO | Hardwired to 0. | + | 15:12 | RO | 0 | +-------------+-----------+---------------------------------------------------------------------------------------------------+ | 11 | RO | **MEIP:** Machine External Interrupt Pending | | | | | | | | If set, irq_i[11] is pending. | +-------------+-----------+---------------------------------------------------------------------------------------------------+ - | 10:8 | RO | Hardwired to 0. | + | 10:8 | RO | 0 | +-------------+-----------+---------------------------------------------------------------------------------------------------+ | 7 | RO | **MTIP:** Machine Timer Interrupt Pending | | | | | | | | If set, irq_i[7] is pending. | +-------------+-----------+---------------------------------------------------------------------------------------------------+ - | 6:4 | RO | Hardwired to 0. | + | 6:4 | RO | 0 | +-------------+-----------+---------------------------------------------------------------------------------------------------+ | 3 | RO | **MSIP:** Machine Software Interrupt Pending | | | | | | | | If set, irq_i[3] is pending. | +-------------+-----------+---------------------------------------------------------------------------------------------------+ - | 2:0 | RO | Hardwired to 0. | + | 2:0 | RO | 0 | +-------------+-----------+---------------------------------------------------------------------------------------------------+ Trigger CSRs @@ -1504,7 +1504,7 @@ Machine Implementation ID (``mimpid``) CSR Address: 0xF13 -Reset Value: 0x0000_0000 +Reset Value: Defined Detailed: @@ -1512,11 +1512,13 @@ Detailed: :widths: 15 15 70 :class: no-scrollbar-table - +-------------+-----------+------------------------------------------------------------------------+ - | **Bit #** | **Mode** | **Description** | - +=============+===========+========================================================================+ - | 31:0 | RO | 0 | - +-------------+-----------+------------------------------------------------------------------------+ + +-------------+-----------+-------------------------------------------------------------------------+ + | **Bit #** | **Mode** | **Description** | + +=============+===========+=========================================================================+ + | 31 : 1 | RO | 0 | + +-------------+-----------+-------------------------------------------------------------------------+ + | 0 | RO | 1 if ``FPU`` = 1 or ``COREV_PULP`` = 1 or ``COREV_CLUSTER`` = 1 else 0. | + +-------------+-----------+-------------------------------------------------------------------------+ .. _csr-mhartid: @@ -1714,10 +1716,10 @@ Reset Value: Defined :widths: 15 15 70 :class: no-scrollbar-table - +-------------+-----------+----------------------------------------------------------------+ - | **Bit #** | **Mode** | **Description** | - +=============+===========+================================================================+ - | 31:1 | RO | Hardwired to 0. | - +-------------+-----------+----------------------------------------------------------------+ - | 0 | RO | 1 if ``FPU`` = 1 and ``ZFINX`` = 1 else 0. | - +-------------+-----------+----------------------------------------------------------------+ + +-------------+-----------+---------------------------------------------------+ + | **Bit #** | **Mode** | **Description** | + +=============+===========+===================================================+ + | 31:1 | RO | 0 | + +-------------+-----------+---------------------------------------------------+ + | 0 | RO | 1 if ``FPU`` = 1 and ``ZFINX`` = 1 else 0. | + +-------------+-----------+---------------------------------------------------+ diff --git a/docs/source/core_versions.rst b/docs/source/core_versions.rst index 9af9a71dd..c23169985 100644 --- a/docs/source/core_versions.rst +++ b/docs/source/core_versions.rst @@ -129,8 +129,8 @@ It refers to the CV32E40P core verified with the following parameters: +---------------------------+-------+ | ``PULP_CLUSTER`` | 0 | +---------------------------+-------+ -| ``NUM_MHPMCOUNTERS`` | 1 | -+---------------------------+-------+ + +Verification of cv32e40p_v1.0.0 has been done with only following value for ``NUM_MHPMCOUNTERS`` parameter: ``NUM_MHPMCOUNTERS`` == 1. The list of open (waived) issues at the time of applying the cv32e40p_v1.0.0 tag can be found at: @@ -165,16 +165,13 @@ When parameters are set with the exact same values than for cv32e40p_v1.0.0 rele +---------------------------+-------+ | ``COREV_CLUSTER`` | 0 | +---------------------------+-------+ -| ``NUM_MHPMCOUNTERS`` | 1 | -+---------------------------+-------+ mimpid = 1 ~~~~~~~~~~ When one parameter is set with a different value than for cv32e40p_v1.0.0 release then ``mimpid`` value is equal to ``1``. -This means either ``FPU``, ``ZFINX``, ``COREV_PULP`` or ``COREV_CLUSTER`` is set to 1. -Or ``NUM_MHPMCOUNTERS`` is set to a value greater than 1. +This means either ``FPU``, ``COREV_PULP`` or ``COREV_CLUSTER`` is set to 1. .. The list of open (waived) issues at the time of applying the cv32e40p_v1.0.0 tag can be found at: diff --git a/docs/source/instruction_set_extensions.rst b/docs/source/instruction_set_extensions.rst index d43ac1080..351720f22 100644 --- a/docs/source/instruction_set_extensions.rst +++ b/docs/source/instruction_set_extensions.rst @@ -76,7 +76,7 @@ Load operations .. note:: - When same register is used as address and destination (rD == rs1) for post-incremented loads (rs1!), + When same register is used as address and destination (rD == rs1) for post-incremented loads, loaded data has highest priority over incremented address when writing to this same register. .. table:: Load operations @@ -89,45 +89,45 @@ Load operations +====================================================+===============================+ | **Register-Immediate Loads with Post-Increment** | +----------------------------------------------------+-------------------------------+ - | **cv.lb rD, Imm(rs1!)** | rD = Sext(Mem8(rs1)) | + | **cv.lb rD, (rs1), Imm** | rD = Sext(Mem8(rs1)) | | | | | | rs1 += Sext(Imm[11:0]) | +----------------------------------------------------+-------------------------------+ - | **cv.lbu rD, Imm(rs1!)** | rD = Zext(Mem8(rs1)) | + | **cv.lbu rD, (rs1), Imm** | rD = Zext(Mem8(rs1)) | | | | | | rs1 += Sext(Imm[11:0]) | +----------------------------------------------------+-------------------------------+ - | **cv.lh rD, Imm(rs1!)** | rD = Sext(Mem16(rs1)) | + | **cv.lh rD, (rs1), Imm** | rD = Sext(Mem16(rs1)) | | | | | | rs1 += Sext(Imm[11:0]) | +----------------------------------------------------+-------------------------------+ - | **cv.lhu rD, Imm(rs1!)** | rD = Zext(Mem16(rs1)) | + | **cv.lhu rD, (rs1), Imm** | rD = Zext(Mem16(rs1)) | | | | | | rs1 += Sext(Imm[11:0]) | +----------------------------------------------------+-------------------------------+ - | **cv.lw rD, Imm(rs1!)** | rD = Mem32(rs1) | + | **cv.lw rD, (rs1), Imm** | rD = Mem32(rs1) | | | | | | rs1 += Sext(Imm[11:0]) | +----------------------------------------------------+-------------------------------+ | **Register-Register Loads with Post-Increment** | +----------------------------------------------------+-------------------------------+ - | **cv.lb rD, rs2(rs1!)** | rD = Sext(Mem8(rs1)) | + | **cv.lb rD, (rs1), rs2** | rD = Sext(Mem8(rs1)) | | | | | | rs1 += rs2 | +----------------------------------------------------+-------------------------------+ - | **cv.lbu rD, rs2(rs1!)** | rD = Zext(Mem8(rs1)) | + | **cv.lbu rD, (rs1), rs2** | rD = Zext(Mem8(rs1)) | | | | | | rs1 += rs2 | +----------------------------------------------------+-------------------------------+ - | **cv.lh rD, rs2(rs1!)** | rD = Sext(Mem16(rs1)) | + | **cv.lh rD, (rs1), rs2** | rD = Sext(Mem16(rs1)) | | | | | | rs1 += rs2 | +----------------------------------------------------+-------------------------------+ - | **cv.lhu rD, rs2(rs1!)** | rD = Zext(Mem16(rs1)) | + | **cv.lhu rD, (rs1), rs2** | rD = Zext(Mem16(rs1)) | | | | | | rs1 += rs2 | +----------------------------------------------------+-------------------------------+ - | **cv.lw rD, rs2(rs1!)** | rD = Mem32(rs1) | + | **cv.lw rD, (rs1), rs2** | rD = Mem32(rs1) | | | | | | rs1 += rs2 | +----------------------------------------------------+-------------------------------+ @@ -157,29 +157,29 @@ Store operations +=====================================================+==========================+ | **Register-Immediate Stores with Post-Increment** | +-----------------------------------------------------+--------------------------+ - | **cv.sb rs2, Imm(rs1!)** | Mem8(rs1) = rs2 | + | **cv.sb rs2, (rs1), Imm** | Mem8(rs1) = rs2 | | | | | | rs1 += Sext(Imm[11:0]) | +-----------------------------------------------------+--------------------------+ - | **cv.sh rs2, Imm(rs1!)** | Mem16(rs1) = rs2 | + | **cv.sh rs2, (rs1), Imm** | Mem16(rs1) = rs2 | | | | | | rs1 += Sext(Imm[11:0]) | +-----------------------------------------------------+--------------------------+ - | **cv.sw rs2, Imm(rs1!)** | Mem32(rs1) = rs2 | + | **cv.sw rs2, (rs1), Imm** | Mem32(rs1) = rs2 | | | | | | rs1 += Sext(Imm[11:0]) | +-----------------------------------------------------+--------------------------+ | **Register-Register Stores with Post-Increment** | +-----------------------------------------------------+--------------------------+ - | **cv.sb rs2, rs3(rs1!)** | Mem8(rs1) = rs2 | + | **cv.sb rs2, (rs1), rs3** | Mem8(rs1) = rs2 | | | | | | rs1 += rs3 | +-----------------------------------------------------+--------------------------+ - | **cv.sh rs2, rs3(rs1!)** | Mem16(rs1) = rs2 | + | **cv.sh rs2, (rs1), rs3** | Mem16(rs1) = rs2 | | | | | | rs1 += rs3 | +-----------------------------------------------------+--------------------------+ - | **cv.sw rs2, rs3(rs1!)** | Mem32(rs1) = rs2 | + | **cv.sw rs2, (rs1), rs3** | Mem32(rs1) = rs2 | | | | | | rs1 += rs3 | +-----------------------------------------------------+--------------------------+ @@ -205,15 +205,15 @@ Encoding +---------------+---------+------------+--------+------------+---------------------------+ | **imm[11:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** | +===============+=========+============+========+============+===========================+ - | offset | base | 000 | dest | 000 1011 | **cv.lb rD, Imm(rs1!)** | + | offset | base | 000 | dest | 000 1011 | **cv.lb rD, (rs1), Imm** | +---------------+---------+------------+--------+------------+---------------------------+ - | offset | base | 100 | dest | 000 1011 | **cv.lbu rD, Imm(rs1!)** | + | offset | base | 100 | dest | 000 1011 | **cv.lbu rD, (rs1), Imm** | +---------------+---------+------------+--------+------------+---------------------------+ - | offset | base | 001 | dest | 000 1011 | **cv.lh rD, Imm(rs1!)** | + | offset | base | 001 | dest | 000 1011 | **cv.lh rD, (rs1), Imm** | +---------------+---------+------------+--------+------------+---------------------------+ - | offset | base | 101 | dest | 000 1011 | **cv.lhu rD, Imm(rs1!)** | + | offset | base | 101 | dest | 000 1011 | **cv.lhu rD, (rs1), Imm** | +---------------+---------+------------+--------+------------+---------------------------+ - | offset | base | 010 | dest | 000 1011 | **cv.lw rD, Imm(rs1!)** | + | offset | base | 010 | dest | 000 1011 | **cv.lw rD, (rs1), Imm** | +---------------+---------+------------+--------+------------+---------------------------+ .. table:: Post-Increment Register-Register Load operations encoding @@ -226,15 +226,15 @@ Encoding +------------+----------+---------+------------+--------+------------+---------------------------+ | **funct7** | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** | +============+==========+=========+============+========+============+===========================+ - | 000 0000 | offset | base | 011 | dest | 010 1011 | **cv.lb rD, rs2(rs1!)** | + | 000 0000 | offset | base | 011 | dest | 010 1011 | **cv.lb rD, (rs1), rs2** | +------------+----------+---------+------------+--------+------------+---------------------------+ - | 000 1000 | offset | base | 011 | dest | 010 1011 | **cv.lbu rD, rs2(rs1!)** | + | 000 1000 | offset | base | 011 | dest | 010 1011 | **cv.lbu rD, (rs1), rs2** | +------------+----------+---------+------------+--------+------------+---------------------------+ - | 000 0001 | offset | base | 011 | dest | 010 1011 | **cv.lh rD, rs2(rs1!)** | + | 000 0001 | offset | base | 011 | dest | 010 1011 | **cv.lh rD, (rs1), rs2** | +------------+----------+---------+------------+--------+------------+---------------------------+ - | 000 1001 | offset | base | 011 | dest | 010 1011 | **cv.lhu rD, rs2(rs1!)** | + | 000 1001 | offset | base | 011 | dest | 010 1011 | **cv.lhu rD, (rs1), rs2** | +------------+----------+---------+------------+--------+------------+---------------------------+ - | 000 0010 | offset | base | 011 | dest | 010 1011 | **cv.lw rD, rs2(rs1!)** | + | 000 0010 | offset | base | 011 | dest | 010 1011 | **cv.lw rD, (rs1), rs2** | +------------+----------+---------+------------+--------+------------+---------------------------+ .. table:: Register-Register Load operations encoding @@ -268,11 +268,11 @@ Encoding +----------------+---------+---------+------------+---------------+------------+---------------------------+ | **imm[11:5]** | **rs2** | **rs1** | **funct3** | **imm[4:0]** | **opcode** | **Mnemonic** | +================+=========+=========+============+===============+============+===========================+ - | offset[11:5] | src | base | 000 | offset[4:0] | 010 1011 | **cv.sb rs2, Imm(rs1!)** | + | offset[11:5] | src | base | 000 | offset[4:0] | 010 1011 | **cv.sb rs2, (rs1), Imm** | +----------------+---------+---------+------------+---------------+------------+---------------------------+ - | offset[11:5] | src | base | 001 | offset[4:0] | 010 1011 | **cv.sh rs2, Imm(rs1!)** | + | offset[11:5] | src | base | 001 | offset[4:0] | 010 1011 | **cv.sh rs2, (rs1), Imm** | +----------------+---------+---------+------------+---------------+------------+---------------------------+ - | offset[11:5] | src | base | 010 | offset[4:0] | 010 1011 | **cv.sw rs2, Imm(rs1!)** | + | offset[11:5] | src | base | 010 | offset[4:0] | 010 1011 | **cv.sw rs2, (rs1), Imm** | +----------------+---------+---------+------------+---------------+------------+---------------------------+ .. table:: Post-Increment Register-Register Store operations encoding @@ -285,11 +285,11 @@ Encoding +------------+----------+---------+------------+---------+------------+---------------------------+ | **funct7** | **rs2** | **rs1** | **funct3** | **rs3** | **opcode** | **Mnemonic** | +============+==========+=========+============+=========+============+===========================+ - | 001 0000 | src | base | 011 | offset | 010 1011 | **cv.sb rs2, rs3(rs1!)** | + | 001 0000 | src | base | 011 | offset | 010 1011 | **cv.sb rs2, (rs1), rs3** | +------------+----------+---------+------------+---------+------------+---------------------------+ - | 001 0001 | src | base | 011 | offset | 010 1011 | **cv.sh rs2, rs3(rs1!)** | + | 001 0001 | src | base | 011 | offset | 010 1011 | **cv.sh rs2, (rs1), rs3** | +------------+----------+---------+------------+---------+------------+---------------------------+ - | 001 0010 | src | base | 011 | offse t | 010 1011 | **cv.sw rs2, rs3(rs1!)** | + | 001 0010 | src | base | 011 | offse t | 010 1011 | **cv.sw rs2, (rs1), rs3** | +------------+----------+---------+------------+---------+------------+---------------------------+ .. table:: Register-Register Store operations encoding @@ -733,11 +733,11 @@ General ALU operations +===========================================+========================================================================+ | **cv.abs rD, rs1** | rD = rs1 < 0 ? -rs1 : rs1 | +-------------------------------------------+------------------------------------------------------------------------+ - | **cv.slet rD, rs1, rs2** | rD = rs1 <= rs2 ? 1 : 0 | + | **cv.sle rD, rs1, rs2** | rD = rs1 <= rs2 ? 1 : 0 | | | | | | Note: Comparison is signed. | +-------------------------------------------+------------------------------------------------------------------------+ - | **cv.sletu rD, rs1, rs2** | rD = rs1 <= rs2 ? 1 : 0 | + | **cv.sleu rD, rs1, rs2** | rD = rs1 <= rs2 ? 1 : 0 | | | | | | Note: Comparison is unsigned. | +-------------------------------------------+------------------------------------------------------------------------+ @@ -895,9 +895,9 @@ General ALU Encoding +============+=========+=========+============+========+============+===========================+ | 010 1000 | 00000 | src1 | 011 | dest | 010 1011 | **cv.abs rD, rs1** | +------------+---------+---------+------------+--------+------------+---------------------------+ - | 010 1001 | src2 | src1 | 011 | dest | 010 1011 | **cv.slet rD, rs1, rs2** | + | 010 1001 | src2 | src1 | 011 | dest | 010 1011 | **cv.sle rD, rs1, rs2** | +------------+---------+---------+------------+--------+------------+---------------------------+ - | 010 1010 | src2 | src1 | 011 | dest | 010 1011 | **cv.sletu rD, rs1, rs2** | + | 010 1010 | src2 | src1 | 011 | dest | 010 1011 | **cv.sleu rD, rs1, rs2** | +------------+---------+---------+------------+--------+------------+---------------------------+ | 010 1011 | src2 | src1 | 011 | dest | 010 1011 | **cv.min rD, rs1, rs2** | +------------+---------+---------+------------+--------+------------+---------------------------+ diff --git a/docs/source/integration.rst b/docs/source/integration.rst index 27b0238c9..d2fa3eac8 100644 --- a/docs/source/integration.rst +++ b/docs/source/integration.rst @@ -225,3 +225,55 @@ The ``cv32e40p_sim_clock_gate.sv`` file is not intended for synthesis. For ASIC should be adapted to use a customer specific file that implements the ``cv32e40p_clock_gate`` module using design primitives that are appropriate for the intended synthesis target technology. +.. _synthesis_guidelines: + +Synthesis guidelines +-------------------- + +The CV32E40P core is fully synthesizable. +It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well. + +The top level module is called cv32e40p_top and includes both the core and the FPU. +All the core files are in ``rtl`` and ``rtl/include`` folders (all synthesizable) +while all the FPU files are in ``rtl/vendor/pulp_platform_common_cells``, ``rtl/vendor/pulp_platform_fpnew`` and ``rtl/vendor/pulp_platform_fpu_div_sqrt``. +.. while all the FPU files are in ``rtl/vendor/pulp_platform_common_cells``, ``rtl/vendor/pulp_platform_fpnew`` and ``rtl/vendor/opene906``. +cv32e40p_fpu_manifest.flist is listing all the required files. + +The user must provide a clock-gating module that instantiates the functionally equivalent clock-gating cell of the target technology. +This file must have the same interface and module name as the one provided for simulation-only purposes at ``bhv/cv32e40p_sim_clock_gate.sv`` (see :ref:`clock-gating-cell`). + +The ``constraints/cv32e40p_core.sdc`` file provides an example of synthesis constraints. + + +ASIC Synthesis +^^^^^^^^^^^^^^ + +ASIC synthesis is supported for CV32E40P. The whole design is completely +synchronous and uses positive-edge triggered flip-flops. The +core occupies an area of about XX kGE. +With the FPU, the area increases to about XX kGE (XX kGE +FPU, XX kGE additional register file). A technology specific implementation +of a clock gating cell as described in :ref:`clock-gating-cell` needs to +be provided. + +FPGA Synthesis +^^^^^^^^^^^^^^^ + +FPGA synthesis is only supported for CV32E40P. +The user needs to provide a technology specific implementation of a clock gating cell as described +in :ref:`clock-gating-cell`. + +.. _synthesis_with_fpu: + +Synthesizing with the FPU +^^^^^^^^^^^^^^^^^^^^^^^^^ + +By default the pipeline of the FPU is purely combinatorial (FPU_*_LAT = 0). In this case FPU instructions latency is the same than simple ALU operations (except FP multicycle DIV/SQRT ones). +But as FPU operations are much more complex than ALU ones, maximum achievable frequency is much lower than ALU one when FPU is enabled. +If this can be fine for low frequency systems, it is possible to indicate how many pipeline registers are instantiated in the FPU to reach higher target frequency. +This is done with FPU_*_LAT CV32E40P parameters setting to perfectly fit target frequency. +It should be noted that any additional pipeline register is impacting FPU instructions latency and could cause performances degradation depending of applications using Floating-Point operations. +Those pipeline registers are all added at the end of the FPU pipeline with all operators before them. Optimal frequency is only achievable using automatic retiming commands in implementation tools. +This can be achieved with the following command for Synopsys Design Compiler: +“set_optimize_registers true -designs [get_object_name [get_designs "\*cv32e40p_fp_wrapper\*"]]”. + diff --git a/docs/source/intro.rst b/docs/source/intro.rst index 059fd43fb..853ef357c 100644 --- a/docs/source/intro.rst +++ b/docs/source/intro.rst @@ -137,76 +137,22 @@ CV32E40P currently supports the following features according to the RISC-V Privi * Hardware Performance Counters as described in :ref:`performance-counters` controlled by the ``NUM_MHPMCOUNTERS`` parameter * Trap handling supporting direct mode or vectored mode as described at :ref:`exceptions-interrupts` - -.. _synthesis_guidelines: - -Synthesis guidelines --------------------- - -The CV32E40P core is fully synthesizable. -It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well. - -The top level module is called cv32e40p_top and includes both the core and the FPU. -All the core files are in ``rtl`` and ``rtl/include`` folders (all synthesizable) -while all the FPU files are in ``rtl/vendor/pulp_platform_common_cells``, ``rtl/vendor/pulp_platform_fpnew`` and ``rtl/vendor/pulp_platform_fpu_div_sqrt``. -.. while all the FPU files are in ``rtl/vendor/pulp_platform_common_cells``, ``rtl/vendor/pulp_platform_fpnew`` and ``rtl/vendor/opene906``. -cv32e40p_fpu_manifest.flist is listing all the required files. - -The user must provide a clock-gating module that instantiates the functionally equivalent clock-gating cell of the target technology. -This file must have the same interface and module name as the one provided for simulation-only purposes at ``bhv/cv32e40p_sim_clock_gate.sv`` (see :ref:`clock-gating-cell`). - -The ``constraints/cv32e40p_core.sdc`` file provides an example of synthesis constraints. - - -ASIC Synthesis -^^^^^^^^^^^^^^ - -ASIC synthesis is supported for CV32E40P. The whole design is completely -synchronous and uses positive-edge triggered flip-flops. The -core occupies an area of about XX kGE. -With the FPU, the area increases to about XX kGE (XX kGE -FPU, XX kGE additional register file). A technology specific implementation -of a clock gating cell as described in :ref:`clock-gating-cell` needs to -be provided. - -FPGA Synthesis -^^^^^^^^^^^^^^^ - -FPGA synthesis is only supported for CV32E40P. -The user needs to provide a technology specific implementation of a clock gating cell as described -in :ref:`clock-gating-cell`. - -.. _synthesis_with_fpu: - -Synthesizing with the FPU -^^^^^^^^^^^^^^^^^^^^^^^^^ - -By default the pipeline of the FPU is purely combinatorial (FPU_*_LAT = 0). In this case FPU instructions latency is the same than simple ALU operations (except FP multicycle DIV/SQRT ones). -But as FPU operations are much more complex than ALU ones, maximum achievable frequency is much lower than ALU one when FPU is enabled. -If this can be fine for low frequency systems, it is possible to indicate how many pipeline registers are instantiated in the FPU to reach higher target frequency. -This is done with FPU_*_LAT CV32E40P parameters setting to perfectly fit target frequency. -It should be noted that any additional pipeline register is impacting FPU instructions latency and could cause performances degradation depending of applications using Floating-Point operations. -Those pipeline registers are all added at the end of the FPU pipeline with all operators before them. Optimal frequency is only achievable using automatic retiming commands in implementation tools. -This can be achieved with the following command for Synopsys Design Compiler: -“set_optimize_registers true -designs [get_object_name [get_designs "\*cv32e40p_fp_wrapper\*"]]”. - Contents -------- - * :ref:`getting-started` discusses the requirements and initial steps to start using CV32E40P. - * :ref:`core-integration` provides the instantiation template and gives descriptions of the design parameters as well as the input and output ports. - * :ref:`verification` gives a brief overview of the verification methodology. - * :ref:`pipeline-details` described the overal pipeline structure. - * The instruction and data interfaces of CV32E40P are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`, respectively. - * The two register-file flavors are described in :ref:`register-file`. + * :ref:`core-integration` provides the instantiation template and gives descriptions of the design parameters as well as the input and output ports. It gives synthesis guidelines as well, especially with respect to the Floating-Point Unit. * :ref:`fpu` describes the Floating Point Unit (FPU). - * :ref:`sleep_unit` describes the Sleep unit including the PULP Cluster extension. + * :ref:`verification` gives a brief overview of the verification methodology. * :ref:`hwloop-specs` describes the PULP Hardware Loop extension. - * The control and status registers are explained in :ref:`cs-registers`. + * :ref:`custom-isa-extensions` describes the custom instruction set extensions. * :ref:`performance-counters` gives an overview of the performance monitors and event counters available in CV32E40P. + * The control and status registers are explained in :ref:`cs-registers`. * :ref:`exceptions-interrupts` deals with the infrastructure for handling exceptions and interrupts. * :ref:`debug-support` gives a brief overview on the debug infrastructure. - * :ref:`custom-isa-extensions` describes the custom instruction set extensions. + * :ref:`pipeline-details` described the overal pipeline structure. + * The instruction and data interfaces of CV32E40P are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`, respectively. + * The register-file is described in :ref:`register-file`. + * :ref:`sleep_unit` describes the Sleep unit including the PULP Cluster extension. * :ref:`core_versions` describes the core versioning. * :ref:`glossary` provides definitions of used terminology. @@ -253,8 +199,7 @@ PULP HWLoop Spec ^^^^^^^^^^^^^^^^ RI5CY supported two nested HWLoops. Every loop had a minimum of two instructions. The start and end of the loop addresses -could be misaligned, and the instructions in the loop body could be of any kind. CV32E40P has a more restricted spec for the -HWLoop (see :ref:`hwloop-specs`). +could be misaligned, and the instructions in the loop body could be of any kind. CV32E40P has a more restricted constraints for the HWLoop (see :ref:`hwloop-specs`). Compliancy, bug fixing, code clean-up, and documentation ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^