From 788caae7d5e4d5fc07f68dc7f34f6307ca17f5d4 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 25 Jul 2023 14:17:29 +0200 Subject: [PATCH 1/5] Issue #838 correction Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_controller.sv | 53 ++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/rtl/cv32e40p_controller.sv b/rtl/cv32e40p_controller.sv index 56cce6281..7cd3d41d7 100644 --- a/rtl/cv32e40p_controller.sv +++ b/rtl/cv32e40p_controller.sv @@ -223,6 +223,8 @@ module cv32e40p_controller import cv32e40p_pkg::*; logic hwlp_end1_eq_pc; logic hwlp_counter0_gt_1; logic hwlp_counter1_gt_1; + logic hwlp_counter0_eq_1; + logic hwlp_counter1_eq_1; logic hwlp_end0_eq_pc_plus4; logic hwlp_end1_eq_pc_plus4; logic hwlp_start0_leq_pc; @@ -617,26 +619,34 @@ module cv32e40p_controller import cv32e40p_pkg::*; // we can be at the end of HWloop due to a return from interrupt or ecall or ebreak or exceptions if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin - pc_mux_o = PC_HWLOOP; - if (~jump_done_q) begin - pc_set_o = 1'b1; - // Keep the instruction and the related address in the Aligner if - // ID is stalled during a jump - jump_done = 1'b1; - hwlp_dec_cnt_o[0] = 1'b1; - end - end - if(hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin - pc_mux_o = PC_HWLOOP; - if (~jump_done_q) begin - pc_set_o = 1'b1; - // Keep the instruction and the related address in the Aligner if - // ID is stalled during a jump - jump_done = 1'b1; - hwlp_dec_cnt_o[1] = 1'b1; - end - end + pc_mux_o = PC_HWLOOP; + if (~jump_done_q) begin + pc_set_o = 1'b1; + // Keep the instruction and the related address in the Aligner if + // ID is stalled during a jump + jump_done = 1'b1; + hwlp_dec_cnt_o[0] = 1'b1; + end end + if (hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin + pc_mux_o = PC_HWLOOP; + if (~jump_done_q) begin + pc_set_o = 1'b1; + // Keep the instruction and the related address in the Aligner if + // ID is stalled during a jump + jump_done = 1'b1; + hwlp_dec_cnt_o[1] = 1'b1; + end + end + end + + if (hwlp_end0_eq_pc && hwlp_counter0_eq_1) begin + hwlp_dec_cnt_o[0] = 1'b1; + end + if (hwlp_end1_eq_pc && hwlp_counter1_eq_1) begin + hwlp_dec_cnt_o[1] = 1'b1; + end + end endcase // unique case (1'b1) @@ -1269,6 +1279,8 @@ generate assign hwlp_end1_eq_pc = hwlp_end_addr_i[1] == pc_id_i + 4; // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i assign hwlp_counter0_gt_1 = hwlp_counter_i[0] > 1; assign hwlp_counter1_gt_1 = hwlp_counter_i[1] > 1; + assign hwlp_counter0_eq_1 = hwlp_counter_i[0] == 1; + assign hwlp_counter1_eq_1 = hwlp_counter_i[1] == 1; assign hwlp_end0_eq_pc_plus4 = hwlp_end_addr_i[0] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[0] - 4 == pc_id_i + 4 assign hwlp_end1_eq_pc_plus4 = hwlp_end_addr_i[1] == pc_id_i + 8; // Equivalent to hwlp_end_addr_i[1] - 4 == pc_id_i + 4 assign hwlp_start0_leq_pc = hwlp_start_addr_i[0] <= pc_id_i; @@ -1285,6 +1297,8 @@ generate assign hwlp_end1_eq_pc = 1'b0; assign hwlp_counter0_gt_1 = 1'b0; assign hwlp_counter1_gt_1 = 1'b0; + assign hwlp_counter0_eq_1 = 1'b0; + assign hwlp_counter1_eq_1 = 1'b0; assign hwlp_end0_eq_pc_plus4 = 1'b0; assign hwlp_end1_eq_pc_plus4 = 1'b0; assign hwlp_start0_leq_pc = 1'b0; @@ -1555,6 +1569,7 @@ endgenerate (hwlp_start_addr_i == 'b0) && (hwlp_end_addr_i == 'b0) && (hwlp_counter_i[1] == 32'b0) && (hwlp_counter_i[0] == 32'b0) && (hwlp_dec_cnt_o == 2'b0) && (hwlp_jump_o == 1'b0) && (hwlp_targ_addr_o == 32'b0) && (hwlp_end0_eq_pc == 1'b0) && (hwlp_end1_eq_pc == 1'b0) && (hwlp_counter0_gt_1 == 1'b0) && (hwlp_counter1_gt_1 == 1'b0) && + (hwlp_counter0_eq_1 == 1'b0) && (hwlp_counter1_eq_1 == 1'b0) && (hwlp_end0_eq_pc_plus4 == 1'b0) && (hwlp_end1_eq_pc_plus4 == 1'b0) && (hwlp_start0_leq_pc == 0) && (hwlp_start1_leq_pc == 0) && (hwlp_end0_geq_pc == 1'b0) && (hwlp_end1_geq_pc == 1'b0) && (hwlp_end_4_id_d == 1'b0) && (hwlp_end_4_id_q == 1'b0)); endproperty From 6cfb7438ba62fb433823c85d04e2e001d56e5b81 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Tue, 25 Jul 2023 14:23:36 +0200 Subject: [PATCH 2/5] Issue #730 correction Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_id_stage.sv | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/rtl/cv32e40p_id_stage.sv b/rtl/cv32e40p_id_stage.sv index 0f54e31eb..80b5b645e 100644 --- a/rtl/cv32e40p_id_stage.sv +++ b/rtl/cv32e40p_id_stage.sv @@ -808,7 +808,7 @@ module cv32e40p_id_stage apu_read_regs[0] = regfile_addr_ra_id; apu_read_regs_valid[0] = 1'b1; end // OP_A_REGA_OR_FWD: - OP_A_REGB_OR_FWD: begin + OP_A_REGB_OR_FWD, OP_A_REGC_OR_FWD: begin apu_read_regs[0] = regfile_addr_rb_id; apu_read_regs_valid[0] = 1'b1; end @@ -847,8 +847,13 @@ module cv32e40p_id_stage apu_read_regs_valid[2] = 1'b1; end OP_C_REGC_OR_FWD: begin - apu_read_regs[2] = regfile_addr_rc_id; - apu_read_regs_valid[2] = 1'b1; + if (alu_op_a_mux_sel != OP_A_REGC_OR_FWD) begin + apu_read_regs[2] = regfile_addr_rc_id; + apu_read_regs_valid[2] = 1'b1; + end else begin + apu_read_regs[2] = regfile_addr_rc_id; + apu_read_regs_valid[2] = 1'b0; + end end default: begin apu_read_regs[2] = regfile_addr_rc_id; From 6beb8220671166d18b331ac1d2e1bb7907c0798f Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 31 Jul 2023 15:01:56 +0200 Subject: [PATCH 3/5] Issue #840 correction Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_cs_registers.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/rtl/cv32e40p_cs_registers.sv b/rtl/cv32e40p_cs_registers.sv index 23ede7970..ebcaa43b7 100644 --- a/rtl/cv32e40p_cs_registers.sv +++ b/rtl/cv32e40p_cs_registers.sv @@ -505,8 +505,11 @@ module cv32e40p_cs_registers // marchid: Machine Architecture ID CSR_MARCHID: csr_rdata_int = MARCHID; + // mimpid, Machine Implementation ID + CSR_MIMPID: csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER || (NUM_MHPMCOUNTERS > 1)) ? 32'h1 : 'b0; + // unimplemented, read 0 CSRs - CSR_MIMPID, CSR_MTVAL: csr_rdata_int = 'b0; + CSR_MTVAL: csr_rdata_int = 'b0; CSR_TSELECT, CSR_TDATA3, CSR_MCONTEXT, CSR_SCONTEXT: csr_rdata_int = 'b0; // Always read 0 CSR_TDATA1: csr_rdata_int = tmatch_control_rdata; From 260feb45e5f5cb0b5c501c3228d49af9672d8266 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Mon, 31 Jul 2023 15:12:30 +0200 Subject: [PATCH 4/5] Verible ! Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_cs_registers.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/rtl/cv32e40p_cs_registers.sv b/rtl/cv32e40p_cs_registers.sv index ebcaa43b7..5782b2957 100644 --- a/rtl/cv32e40p_cs_registers.sv +++ b/rtl/cv32e40p_cs_registers.sv @@ -506,7 +506,9 @@ module cv32e40p_cs_registers CSR_MARCHID: csr_rdata_int = MARCHID; // mimpid, Machine Implementation ID - CSR_MIMPID: csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER || (NUM_MHPMCOUNTERS > 1)) ? 32'h1 : 'b0; + CSR_MIMPID: begin + csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER || (NUM_MHPMCOUNTERS > 1)) ? 32'h1 : 'b0; + end // unimplemented, read 0 CSRs CSR_MTVAL: csr_rdata_int = 'b0; From 0491837ebe928770ef46d57efecb73f43839c9b8 Mon Sep 17 00:00:00 2001 From: Pascal Gouedo Date: Thu, 3 Aug 2023 15:21:29 +0200 Subject: [PATCH 5/5] Removed NUM_MHPMCOUNTERS from mimpid computation. Signed-off-by: Pascal Gouedo --- rtl/cv32e40p_cs_registers.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/cv32e40p_cs_registers.sv b/rtl/cv32e40p_cs_registers.sv index 5782b2957..455e3cfcb 100644 --- a/rtl/cv32e40p_cs_registers.sv +++ b/rtl/cv32e40p_cs_registers.sv @@ -507,7 +507,7 @@ module cv32e40p_cs_registers // mimpid, Machine Implementation ID CSR_MIMPID: begin - csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER || (NUM_MHPMCOUNTERS > 1)) ? 32'h1 : 'b0; + csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0; end // unimplemented, read 0 CSRs