From 47d3d83db5f101a3fd4128f1d40577001d38e0c1 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Thu, 3 Oct 2024 17:49:10 +0200 Subject: [PATCH 01/18] updated field names and added pass trough components --- mips-lib/examples/mips_pipe_example_1.rs | 71 ++++++++++++++++++------ 1 file changed, 55 insertions(+), 16 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index 441249b..c93fd57 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -26,21 +26,25 @@ fn main() { store: vec![ Rc::new(PhysicalMem::new("phys_mem", (0.0, 0.0))), // register that holds instr addr - Register::rc_new("pc", (170.0, 410.0), Input::new("mux_jump_merge", "out")), + Register::rc_new( + "pc", + (170.0, 410.0), + Input::new("mux_jump_merge", MUX_OUT_ID), + ), // step addr from reg by 4 Constant::rc_new("+4", (170.0, 380.0), 4), Add::rc_new( "pc+4", (220.0, 380.0), - Input::new("pc", "out"), - Input::new("+4", "out"), + Input::new("pc", REGISTER_OUT_ID), + Input::new("+4", CONSTANT_OUT_ID), ), // // Rc::new(InstrMem::new( "instr_mem".into(), (280.0, 600.0), - Input::new("pc", "out"), + Input::new("pc", REGISTER_OUT_ID), "phys_mem".into(), "reg_file".into(), )), @@ -69,6 +73,11 @@ fn main() { // // Register::rc_new("pc+4_reg", (2300.0, 5000.0), Input::new("pc+4", ADD_OUT_ID)), + PassThrough::rc_new( + "pc+4_pass", + (2350.0, 5000.0), + Input::new("pc+4_reg", REGISTER_OUT_ID), + ), // Register::rc_new( "InMem_reg", @@ -88,6 +97,11 @@ fn main() { (280.0, 140.0), Input::new("InMem_reg", REGISTER_OUT_ID), ), + PassThrough::rc_new( + "InMem_pass", + (280.0, 140.0), + Input::new("InMem_reg", REGISTER_OUT_ID), + ), // // First CU, handles, select for sign/zero_extend and mux_write_addr ControlUnit::rc_new( @@ -216,7 +230,12 @@ fn main() { //TODO: make 2 more control units "control_EX_reg", (3450.0, 1400.0), - Input::new("InMem_reg", REGISTER_OUT_ID), + Input::new("InMem_pass", PASS_THROUGH_OUT_ID), + ), + PassThrough::rc_new( + "control_EX_pass", + (3480.0, 1400.0), + Input::new("control_EX_reg", REGISTER_OUT_ID), ), // Register::rc_new( @@ -229,20 +248,25 @@ fn main() { //TODO: fix after adding 4 muxes "operand_a_reg", (3450.0, 1800.0), - Input::new("equals_operand_A_2", MUX_OUT_ID), + Input::new("equals_operand_A_2", EQUAL_OUT_ID), ), // Register::rc_new( //TODO: fix after muxes "operand_b_reg", (3450.0, 2200.0), - Input::new("equals_operand_B_2", MERGE_OUT_ID), + Input::new("equals_operand_B_2", EQUAL_OUT_ID), + ), + PassThrough::rc_new( + "operand_b_pass", + (4200.0, 2500.0), + Input::new("operand_b_reg", REGISTER_OUT_ID), ), // Register::rc_new( "mux_b2_reg", (3450.0, 5000.0), - Input::new("pc+4_reg", REGISTER_OUT_ID), + Input::new("pc+4_pass", PASS_THROUGH_OUT_ID), ), Register::rc_new( "mux_b3_reg", @@ -255,6 +279,11 @@ fn main() { (3450.0, 5500.0), Input::new("mux_write_addr", MUX_OUT_ID), ), + PassThrough::rc_new( + "reg_addr_EX_pass", + (3450.0, 5500.0), + Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), + ), // // ZeroExtend::rc_new( @@ -270,9 +299,9 @@ fn main() { (650.0, 220.0), Input::new("control_unit_2", cntr_field::ALU_SRC_A_OUT), vec![ - Input::new("zero_extend_for_shamt", SIGNZEROEXTEND_OUT_ID), + Input::new("zero_extend_for_shamt", ZEROEXTEND_OUT_ID), Input::new("operand_a_reg", REGISTER_OUT_ID), - Input::new("0_a_inp", "out"), + Input::new("0_a_inp", CONSTANT_OUT_ID), ], ), // @@ -315,7 +344,12 @@ fn main() { Register::rc_new( "control_MEM_reg", (4200.0, 1400.0), - Input::new("control_EX_reg", REGISTER_OUT_ID), + Input::new("control_EX_pass", PASS_THROUGH_OUT_ID), + ), + PassThrough::rc_new( + "control_MEM_pass", + (4200.0, 1400.0), + Input::new("control_MEM_reg", REGISTER_OUT_ID), ), // Register::rc_new( @@ -327,13 +361,18 @@ fn main() { Register::rc_new( "data_MEM_reg", (4200.0, 2500.0), - Input::new("operand_b_reg", REGISTER_OUT_ID), + Input::new("operand_b_pass", PASS_THROUGH_OUT_ID), ), // Register::rc_new( "reg_addr_MEM_reg", (4200.0, 5500.0), - Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), + Input::new("reg_addr_EX_pass", PASS_THROUGH_OUT_ID), + ), + PassThrough::rc_new( + "reg_addr_MEM_pass", + (4250.0, 5500.0), + Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), ), // // @@ -351,7 +390,7 @@ fn main() { Register::rc_new( "control_WB_reg", (4400.0, 1400.0), - Input::new("control_MEM_reg", REGISTER_OUT_ID), + Input::new("control_MEM_pass", PASS_THROUGH_OUT_ID), ), // Register::rc_new( @@ -363,7 +402,7 @@ fn main() { Register::rc_new( "reg_addr_reg", (4400.0, 5500.0), - Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), + Input::new("reg_addr_MEM_pass", PASS_THROUGH_OUT_ID), ), // // @@ -391,7 +430,7 @@ fn main() { vec![ Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RD_ID), - Input::new("0x_1F", "out"), + Input::new("0x_1F", CONSTANT_OUT_ID), ], ), rc_reg_file, From a26f92c54aef1b9e06871170f99d389f8e79ad5c Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Mon, 7 Oct 2024 11:30:28 +0200 Subject: [PATCH 02/18] worked on mips pipe --- mips-lib/mips_pipe.json | 2873 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 2873 insertions(+) create mode 100644 mips-lib/mips_pipe.json diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json new file mode 100644 index 0000000..4ed6790 --- /dev/null +++ b/mips-lib/mips_pipe.json @@ -0,0 +1,2873 @@ +{ + "store": [ + { + "type": "Register", + "id": "operand_a_reg", + "pos": [ + 1093.1989, + 216.00018 + ], + "r_in": { + "id": "operand_A_mux_2", + "field": "mux_out" + } + }, + { + "type": "Register", + "id": "mux_b2_reg", + "pos": [ + 1091.6001, + 547.2002 + ], + "r_in": { + "id": "pc+4_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "InMem_reg", + "pos": [ + 208.7998, + 474.4015 + ], + "r_in": { + "id": "instr_mem", + "field": "instruction" + } + }, + { + "type": "Register", + "id": "zero_extend_reg", + "pos": [ + 1098.0002, + 107.20001 + ], + "r_in": { + "id": "instruction_split", + "field": "shamt_out" + } + }, + { + "type": "Register", + "id": "alu_reg", + "pos": [ + 1470.4004, + 252.79993 + ], + "r_in": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Register", + "id": "merge_reg", + "pos": [ + 216.00024, + 582.40155 + ], + "r_in": { + "id": "jump_merge", + "field": "merge_out" + } + }, + { + "type": "Register", + "id": "reg_addr_EX_reg", + "pos": [ + 1123.5989, + 794.3998 + ], + "r_in": { + "id": "mux_write_addr", + "field": "mux_out" + } + }, + { + "type": "Register", + "id": "control_WB_reg", + "pos": [ + 1918.4001, + -73.60004 + ], + "r_in": { + "id": "control_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "mux_b3_reg", + "pos": [ + 1101.1995, + 624.7999 + ], + "r_in": { + "id": "signzero_extend", + "field": "sz_out" + } + }, + { + "type": "Register", + "id": "operand_b_reg", + "pos": [ + 1101.1985, + 324.80035 + ], + "r_in": { + "id": "operand_B_mux_2", + "field": "mux_out" + } + }, + { + "type": "Register", + "id": "pc+4_reg", + "pos": [ + 201.59985, + 371.20197 + ], + "r_in": { + "id": "pc+4", + "field": "add_out" + } + }, + { + "type": "Register", + "id": "pc", + "pos": [ + 79.60004, + 415.60004 + ], + "r_in": { + "id": "mux_jump_merge", + "field": "mux_out" + } + }, + { + "type": "Register", + "id": "control_MEM_reg", + "pos": [ + 1473.6001, + -80.00018 + ], + "r_in": { + "id": "control_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "control_EX_reg", + "pos": [ + 918.7965, + -38.400085 + ], + "r_in": { + "id": "InMem_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "data_MEM_reg", + "pos": [ + 1477.6, + 566.4001 + ], + "r_in": { + "id": "operand_b_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "result_reg_EX", + "pos": [ + 1918.3983, + 268.79993 + ], + "r_in": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Register", + "id": "reg_addr_reg", + "pos": [ + 1947.2009, + 799.2012 + ], + "r_in": { + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "reg_addr_MEM_reg", + "pos": [ + 1480.0015, + 802.40173 + ], + "r_in": { + "id": "reg_addr_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "ZeroExtend", + "id": "zero_extend_for_shamt", + "pos": [ + 1166.7983, + 107.600006 + ], + "signal_in": { + "id": "zero_extend_reg", + "field": "register_out" + } + }, + { + "type": "Constant", + "id": "+4", + "pos": [ + 78.80005, + 382.39996 + ], + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } + } + }, + { + "type": "ControlUnit", + "id": "control_unit_4", + "pos": [ + 2216.0002, + 23.200073 + ], + "a_in": { + "id": "control_WB_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "reg_addr_EX_pass", + "pos": [ + 1153.9998, + 794.401 + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "InMem_pass", + "pos": [ + 232.40002, + 474.8 + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "ControlUnit", + "id": "control_unit_1", + "pos": [ + 263.2, + 2.4000092 + ], + "a_in": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "operand_b_pass", + "pos": [ + 1160.8, + 360.00006 + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "pc+4_pass", + "pos": [ + 235.60022, + 371.99823 + ], + "input": { + "id": "pc+4_reg", + "field": "register_out" + } + }, + { + "type": "Add", + "id": "pc+4", + "pos": [ + 130.40002, + 380.8 + ], + "a_in": { + "id": "pc", + "field": "register_out" + }, + "b_in": { + "id": "+4", + "field": "constant_out" + }, + "scale": 1.0 + }, + { + "type": "InstrMem", + "id": "instr_mem", + "pos": [ + 98.400024, + 585.6 + ], + "pc": { + "id": "pc", + "field": "register_out" + }, + "phys_mem_id": "phys_mem", + "regfile_id": "reg_file", + "mem_view": { + "visible": true, + "title": "instruction memory view", + "id": "instr_mem", + "row_offset": 0, + "max_rows": 1024, + "big_endian": true, + "format": "HexAndMips", + "show_settings": { + "symbols": true, + "sections": false, + "program_counter": false, + "registers": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + true + ] + }, + "register_values": [ + 0, + 0, + 4020265517, + 0, + 4512, + 4175, + 0, + 0, + 1478048723, + 3184185328, + 56462194, + 274701634, + 4176, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147481728, + 2147481744, + 152 + ], + "dynamic_symbols": { + "PC_IM": [ + 276, + true + ] + }, + "break_points": [ + 224 + ] + } + }, + { + "type": "JumpMerge", + "id": "jump_merge", + "pos": [ + -62.200012, + 492.80005 + ], + "instr_addr_in": { + "id": "pc", + "field": "register_out" + }, + "jump_addr_in": { + "id": "instr_mem", + "field": "instruction" + } + }, + { + "type": "InstrSplit", + "id": "instruction_split", + "pos": [ + 271.19995, + 154.79999 + ], + "instruction_in": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Equal", + "id": "equals_operand_A_2", + "pos": [ + 969.59796, + 167.20001 + ], + "a_in": { + "id": "reg_addr_EX_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "SignZeroExtend", + "id": "signzero_extend", + "pos": [ + 310.0, + 410.0 + ], + "signzero_signal_in": { + "id": "instruction_split", + "field": "immediate_out" + }, + "signzero_ctrl_in": { + "id": "control_unit_1", + "field": "extend_select" + } + }, + { + "type": "ShiftConst", + "id": "branch_shift", + "pos": [ + 380.0, + 460.0 + ], + "signal_in": { + "id": "signzero_extend", + "field": "sz_out" + }, + "shift_by": 2 + }, + { + "type": "Add", + "id": "pc_add_branch", + "pos": [ + 420.0, + 440.0 + ], + "a_in": { + "id": "pc+4_reg", + "field": "register_out" + }, + "b_in": { + "id": "branch_shift", + "field": "shift_left_const_out" + }, + "scale": 1.0 + }, + { + "type": "ControlUnit", + "id": "control_unit_3", + "pos": [ + 1667.2002, + 27.199997 + ], + "a_in": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "DataMem", + "id": "data_mem", + "pos": [ + 1665.5996, + 560.8 + ], + "address_input": { + "id": "alu_reg", + "field": "register_out" + }, + "data_input": { + "id": "data_MEM_reg", + "field": "register_out" + }, + "op_input": { + "id": "control_unit_3", + "field": "mem_mode" + }, + "write_enable_input": { + "id": "control_unit_3", + "field": "mem_write_enable" + }, + "phys_mem_id": "phys_mem", + "regfile_id": "reg_file", + "mem_view": { + "visible": true, + "title": "Data memory view", + "id": "data_mem", + "row_offset": 512, + "max_rows": 1024, + "big_endian": true, + "format": "ByteAndUtf8", + "show_settings": { + "symbols": true, + "sections": false, + "program_counter": false, + "registers": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false + ] + }, + "register_values": [ + 0, + 0, + 4020265517, + 0, + 4512, + 4175, + 0, + 0, + 1478048723, + 3184185328, + 56462194, + 274701634, + 4176, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147481728, + 2147481744, + 152 + ], + "dynamic_symbols": { + "DM_ADRS": [ + 4175, + false + ] + }, + "break_points": [ + 4172 + ] + } + }, + { + "type": "PassThrough", + "id": "control_EX_pass", + "pos": [ + 944.7983, + -39.19998 + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "RegFile", + "id": "reg_file", + "pos": [ + 434.4, + 177.20001 + ], + "rs_address_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "rt_address_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "write_address_in": { + "id": "reg_addr_reg", + "field": "register_out" + }, + "write_data_in": { + "id": "result_reg_EX", + "field": "register_out" + }, + "write_enable_in": { + "id": "control_unit_4", + "field": "reg_write_enable" + } + }, + { + "type": "ControlUnit", + "id": "control_unit_2", + "pos": [ + 1207.2001, + 27.199997 + ], + "a_in": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "Mux", + "id": "mux_source_b", + "pos": [ + 1254.8002, + 325.60004 + ], + "select": { + "id": "control_unit_2", + "field": "alu_src_b" + }, + "m_in": [ + { + "id": "operand_b_reg", + "field": "register_out" + }, + { + "id": "mux_b2_reg", + "field": "register_out" + }, + { + "id": "mux_b3_reg", + "field": "register_out" + } + ], + "scale": 1.0 + }, + { + "type": "Constant", + "id": "0x_1F", + "pos": [ + 500.0, + 510.0 + ], + "value": { + "data": { + "Data": 31 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } + } + }, + { + "type": "Mux", + "id": "mux_write_addr", + "pos": [ + 560.0, + 500.0 + ], + "select": { + "id": "control_unit_1", + "field": "reg_dest" + }, + "m_in": [ + { + "id": "instruction_split", + "field": "rt_out" + }, + { + "id": "instruction_split", + "field": "rd_out" + }, + { + "id": "0x_1F", + "field": "constant_out" + } + ], + "scale": 1.0 + }, + { + "type": "Mux", + "id": "write_back_mux", + "pos": [ + 1681.5999, + 270.00012 + ], + "select": { + "id": "control_unit_3", + "field": "reg_write_src" + }, + "m_in": [ + { + "id": "alu_reg", + "field": "register_out" + }, + { + "id": "data_mem", + "field": "data_out" + } + ], + "scale": 1.0 + }, + { + "type": "Equal", + "id": "equals_operand_B", + "pos": [ + 811.9999, + 426.39972 + ], + "a_in": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Mux", + "id": "operand_B_mux_1", + "pos": [ + 812.79956, + 323.99988 + ], + "select": { + "id": "equals_operand_B", + "field": "equals_out" + }, + "m_in": [ + { + "id": "reg_file", + "field": "rt_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, + { + "type": "Equal", + "id": "equals_operand_A", + "pos": [ + 803.1997, + 163.99988 + ], + "a_in": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Mux", + "id": "operand_A_mux_1", + "pos": [ + 809.6, + 225.60065 + ], + "select": { + "id": "equals_operand_A", + "field": "equals_out" + }, + "m_in": [ + { + "id": "reg_file", + "field": "rs_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, + { + "type": "Equal", + "id": "equals_operand_B_2", + "pos": [ + 974.3968, + 426.40027 + ], + "a_in": { + "id": "reg_addr_EX_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "PassThrough", + "id": "reg_addr_MEM_pass", + "pos": [ + 1523.5994, + 802.3993 + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "control_MEM_pass", + "pos": [ + 1498.3997, + -80.0 + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Constant", + "id": "0_a_inp", + "pos": [ + 596.00006, + 48.40001 + ], + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } + } + }, + { + "type": "Mux", + "id": "mux_source_a", + "pos": [ + 1252.4003, + 207.99994 + ], + "select": { + "id": "control_unit_2", + "field": "alu_src_a" + }, + "m_in": [ + { + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" + }, + { + "id": "operand_a_reg", + "field": "register_out" + }, + { + "id": "0_a_inp", + "field": "constant_out" + } + ], + "scale": 1.0 + }, + { + "type": "ALU", + "id": "alu", + "pos": [ + 1395.9999, + 214.40002 + ], + "a_in": { + "id": "mux_source_a", + "field": "mux_out" + }, + "b_in": { + "id": "mux_source_b", + "field": "mux_out" + }, + "op_in": { + "id": "control_unit_2", + "field": "alu_op" + } + }, + { + "type": "Mux", + "id": "operand_A_mux_2", + "pos": [ + 965.6015, + 227.99994 + ], + "select": { + "id": "equals_operand_A_2", + "field": "equals_out" + }, + "m_in": [ + { + "id": "operand_A_mux_1", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" + } + ], + "scale": 1.0 + }, + { + "type": "Mux", + "id": "operand_B_mux_2", + "pos": [ + 966.4005, + 325.60052 + ], + "select": { + "id": "equals_operand_B_2", + "field": "equals_out" + }, + "m_in": [ + { + "id": "operand_B_mux_1", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" + } + ], + "scale": 1.0 + }, + { + "type": "BranchLogic", + "id": "branch", + "pos": [ + 1037.0, + 274.40002 + ], + "op_in": { + "id": "instruction_split", + "field": "op_out" + }, + "rt_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "funct_in": { + "id": "instruction_split", + "field": "funct_out" + }, + "rs_value": { + "id": "operand_A_mux_2", + "field": "mux_out" + }, + "rt_value": { + "id": "operand_B_mux_2", + "field": "mux_out" + } + }, + { + "type": "Mux", + "id": "mux_jump_merge", + "pos": [ + -54.399963, + 380.40002 + ], + "select": { + "id": "branch", + "field": "branch_out" + }, + "m_in": [ + { + "id": "pc_add_branch", + "field": "add_out" + }, + { + "id": "reg_file", + "field": "rs_value_out" + }, + { + "id": "merge_reg", + "field": "register_out" + }, + { + "id": "pc+4", + "field": "add_out" + } + ], + "scale": 1.0 + }, + { + "type": "PhysicalMem", + "id": "phys_mem", + "pos": [ + 0.0, + 0.0 + ] + }, + { + "type": "Wire", + "id": "from operand_A_mux_2:mux_out to operand_a_reg:r_in", + "pos": [ + [ + 975.6015, + 227.99994 + ], + [ + 1083.1989, + 216.00018 + ] + ], + "input": { + "id": "operand_A_mux_2", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", + "pos": [ + [ + 235.60022, + 371.99823 + ], + [ + 1081.6001, + 547.2002 + ] + ], + "input": { + "id": "pc+4_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from instr_mem:instruction to InMem_reg:r_in", + "pos": [ + [ + 138.40002, + 552.1 + ], + [ + 198.7998, + 474.4015 + ] + ], + "input": { + "id": "instr_mem", + "field": "instruction" + } + }, + { + "type": "Wire", + "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", + "pos": [ + [ + 302.19995, + 77.02221 + ], + [ + 1088.0002, + 107.20001 + ] + ], + "input": { + "id": "instruction_split", + "field": "shamt_out" + } + }, + { + "type": "Wire", + "id": "from alu:alu_out to alu_reg:r_in", + "pos": [ + [ + 1415.9999, + 214.40002 + ], + [ + 1460.4004, + 252.79993 + ] + ], + "input": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Wire", + "id": "from jump_merge:merge_out to merge_reg:r_in", + "pos": [ + [ + -62.200012, + 492.80005 + ], + [ + 206.00024, + 582.40155 + ] + ], + "input": { + "id": "jump_merge", + "field": "merge_out" + } + }, + { + "type": "Wire", + "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", + "pos": [ + [ + 570.0, + 500.0 + ], + [ + 1113.5989, + 794.3998 + ] + ], + "input": { + "id": "mux_write_addr", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", + "pos": [ + [ + 1498.3997, + -80.0 + ], + [ + 1908.4001, + -73.60004 + ] + ], + "input": { + "id": "control_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", + "pos": [ + [ + 368.5, + 410.0 + ], + [ + 1091.1995, + 624.7999 + ] + ], + "input": { + "id": "signzero_extend", + "field": "sz_out" + } + }, + { + "type": "Wire", + "id": "from operand_B_mux_2:mux_out to operand_b_reg:r_in", + "pos": [ + [ + 976.4005, + 325.60052 + ], + [ + 1091.1985, + 324.80035 + ] + ], + "input": { + "id": "operand_B_mux_2", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from pc+4:add_out to pc+4_reg:r_in", + "pos": [ + [ + 150.40002, + 380.8 + ], + [ + 191.59985, + 371.20197 + ] + ], + "input": { + "id": "pc+4", + "field": "add_out" + } + }, + { + "type": "Wire", + "id": "from mux_jump_merge:mux_out to pc:r_in", + "pos": [ + [ + -44.399963, + 380.40002 + ], + [ + 69.60004, + 415.60004 + ] + ], + "input": { + "id": "mux_jump_merge", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", + "pos": [ + [ + 944.7983, + -39.19998 + ], + [ + 1463.6001, + -80.00018 + ] + ], + "input": { + "id": "control_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", + "pos": [ + [ + 232.40002, + 474.8 + ], + [ + 908.7965, + -38.400085 + ] + ], + "input": { + "id": "InMem_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", + "pos": [ + [ + 1160.8, + 360.00006 + ], + [ + 1467.6, + 566.4001 + ] + ], + "input": { + "id": "operand_b_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from write_back_mux:mux_out to result_reg_EX:r_in", + "pos": [ + [ + 1691.5999, + 270.00012 + ], + [ + 1908.3983, + 268.79993 + ] + ], + "input": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", + "pos": [ + [ + 1523.5994, + 802.3993 + ], + [ + 1937.2009, + 799.2012 + ] + ], + "input": { + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", + "pos": [ + [ + 1153.9998, + 794.401 + ], + [ + 1470.0015, + 802.40173 + ] + ], + "input": { + "id": "reg_addr_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", + "pos": [ + [ + 1108.0002, + 107.20001 + ], + [ + 1125.7983, + 107.600006 + ] + ], + "input": { + "id": "zero_extend_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", + "pos": [ + [ + 1928.4001, + -73.60004 + ], + [ + 2010.0002, + 23.200073 + ] + ], + "input": { + "id": "control_WB_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", + "pos": [ + [ + 1133.5989, + 794.3998 + ], + [ + 1153.9998, + 794.401 + ] + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", + "pos": [ + [ + 218.7998, + 474.4015 + ], + [ + 232.40002, + 474.8 + ] + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", + "pos": [ + [ + 218.7998, + 474.4015 + ], + [ + 57.200012, + 2.4000092 + ] + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", + "pos": [ + [ + 1111.1985, + 324.80035 + ], + [ + 1160.8, + 360.00006 + ] + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", + "pos": [ + [ + 211.59985, + 371.20197 + ], + [ + 235.60022, + 371.99823 + ] + ], + "input": { + "id": "pc+4_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from pc:register_out to pc+4:a_in", + "pos": [ + [ + 89.60004, + 415.60004 + ], + [ + 110.400024, + 360.8 + ] + ], + "input": { + "id": "pc", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from +4:constant_out to pc+4:b_in", + "pos": [ + [ + 78.80005, + 382.39996 + ], + [ + 110.400024, + 400.8 + ] + ], + "input": { + "id": "+4", + "field": "constant_out" + } + }, + { + "type": "Wire", + "id": "from pc:register_out to instr_mem:pc", + "pos": [ + [ + 89.60004, + 415.60004 + ], + [ + 58.400024, + 552.1 + ] + ], + "input": { + "id": "pc", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from pc:register_out to jump_merge:merge_instr_addr_in", + "pos": [ + [ + 89.60004, + 415.60004 + ], + [ + -62.200012, + 492.80005 + ] + ], + "input": { + "id": "pc", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", + "pos": [ + [ + 138.40002, + 552.1 + ], + [ + -62.200012, + 492.80005 + ] + ], + "input": { + "id": "instr_mem", + "field": "instruction" + } + }, + { + "type": "Wire", + "id": "from InMem_reg:register_out to instruction_split:instruction_in", + "pos": [ + [ + 218.7998, + 474.4015 + ], + [ + 240.19995, + 154.79999 + ] + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to equals_operand_A_2:a_in", + "pos": [ + [ + 1133.5989, + 794.3998 + ], + [ + 952.59796, + 157.20001 + ] + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rs_out to equals_operand_A_2:b_in", + "pos": [ + [ + 302.19995, + 143.68887 + ], + [ + 952.59796, + 177.20001 + ] + ], + "input": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", + "pos": [ + [ + 302.19995, + 188.13332 + ], + [ + 251.5, + 410.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "immediate_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", + "pos": [ + [ + 96.53334, + 15.900009 + ], + [ + 310.0, + 389.0 + ] + ], + "input": { + "id": "control_unit_1", + "field": "extend_select" + } + }, + { + "type": "Wire", + "id": "from signzero_extend:sz_out to branch_shift:shift_in", + "pos": [ + [ + 368.5, + 410.0 + ], + [ + 346.5, + 460.0 + ] + ], + "input": { + "id": "signzero_extend", + "field": "sz_out" + } + }, + { + "type": "Wire", + "id": "from pc+4_reg:register_out to pc_add_branch:a_in", + "pos": [ + [ + 211.59985, + 371.20197 + ], + [ + 400.0, + 420.0 + ] + ], + "input": { + "id": "pc+4_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", + "pos": [ + [ + 413.5, + 460.0 + ], + [ + 400.0, + 460.0 + ] + ], + "input": { + "id": "branch_shift", + "field": "shift_left_const_out" + } + }, + { + "type": "Wire", + "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", + "pos": [ + [ + 1483.6001, + -80.00018 + ], + [ + 1461.2002, + 27.199997 + ] + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from alu_reg:register_out to data_mem:data_mem_address_in", + "pos": [ + [ + 1480.4004, + 252.79993 + ], + [ + 1635.5996, + 527.3 + ] + ], + "input": { + "id": "alu_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", + "pos": [ + [ + 1700.5336, + 40.699997 + ], + [ + 1695.5996, + 527.3 + ] + ], + "input": { + "id": "control_unit_3", + "field": "mem_mode" + } + }, + { + "type": "Wire", + "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", + "pos": [ + [ + 1487.6, + 566.4001 + ], + [ + 1599.5996, + 560.8 + ] + ], + "input": { + "id": "data_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", + "pos": [ + [ + 1667.2002, + 40.699997 + ], + [ + 1665.5996, + 527.3 + ] + ], + "input": { + "id": "control_unit_3", + "field": "mem_write_enable" + } + }, + { + "type": "Wire", + "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", + "pos": [ + [ + 928.7965, + -38.400085 + ], + [ + 944.7983, + -39.19998 + ] + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rs_out to reg_file:rs_address_in", + "pos": [ + [ + 302.19995, + 143.68887 + ], + [ + 434.4, + 46.200012 + ] + ], + "input": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to reg_file:rt_address_in", + "pos": [ + [ + 302.19995, + 165.9111 + ], + [ + 434.4, + 308.2 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_reg:register_out to reg_file:write_address_in", + "pos": [ + [ + 1957.2009, + 799.2012 + ], + [ + 368.4, + 267.2 + ] + ], + "input": { + "id": "reg_addr_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from result_reg_EX:register_out to reg_file:write_data_in", + "pos": [ + [ + 1928.3983, + 268.79993 + ], + [ + 368.4, + 287.2 + ] + ], + "input": { + "id": "result_reg_EX", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", + "pos": [ + [ + 2382.667, + 36.700073 + ], + [ + 368.4, + 247.20001 + ] + ], + "input": { + "id": "control_unit_4", + "field": "reg_write_enable" + } + }, + { + "type": "Wire", + "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", + "pos": [ + [ + 928.7965, + -38.400085 + ], + [ + 1001.2001, + 27.199997 + ] + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:alu_src_b to mux_source_b:select", + "pos": [ + [ + 1173.8667, + 40.699997 + ], + [ + 1244.8002, + 285.60004 + ] + ], + "input": { + "id": "control_unit_2", + "field": "alu_src_b" + } + }, + { + "type": "Wire", + "id": "from operand_b_reg:register_out to mux_source_b:in0", + "pos": [ + [ + 1111.1985, + 324.80035 + ], + [ + 1234.8002, + 305.60004 + ] + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from mux_b2_reg:register_out to mux_source_b:in1", + "pos": [ + [ + 1101.6001, + 547.2002 + ], + [ + 1234.8002, + 325.60004 + ] + ], + "input": { + "id": "mux_b2_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from mux_b3_reg:register_out to mux_source_b:in2", + "pos": [ + [ + 1111.1995, + 624.7999 + ], + [ + 1234.8002, + 345.60004 + ] + ], + "input": { + "id": "mux_b3_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_1:reg_dest to mux_write_addr:select", + "pos": [ + [ + 163.20001, + 15.900009 + ], + [ + 550.0, + 460.0 + ] + ], + "input": { + "id": "control_unit_1", + "field": "reg_dest" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to mux_write_addr:in0", + "pos": [ + [ + 302.19995, + 165.9111 + ], + [ + 540.0, + 480.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rd_out to mux_write_addr:in1", + "pos": [ + [ + 302.19995, + 210.35555 + ], + [ + 540.0, + 500.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rd_out" + } + }, + { + "type": "Wire", + "id": "from 0x_1F:constant_out to mux_write_addr:in2", + "pos": [ + [ + 500.0, + 510.0 + ], + [ + 540.0, + 520.0 + ] + ], + "input": { + "id": "0x_1F", + "field": "constant_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:reg_write_src to write_back_mux:select", + "pos": [ + [ + 1800.5336, + 40.699997 + ], + [ + 1671.5999, + 240.00012 + ] + ], + "input": { + "id": "control_unit_3", + "field": "reg_write_src" + } + }, + { + "type": "Wire", + "id": "from alu_reg:register_out to write_back_mux:in0", + "pos": [ + [ + 1480.4004, + 252.79993 + ], + [ + 1661.5999, + 260.00012 + ] + ], + "input": { + "id": "alu_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from data_mem:data_out to write_back_mux:in1", + "pos": [ + [ + 1731.5996, + 560.8 + ], + [ + 1661.5999, + 280.00012 + ] + ], + "input": { + "id": "data_mem", + "field": "data_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to equals_operand_B:a_in", + "pos": [ + [ + 1490.0015, + 802.40173 + ], + [ + 794.9999, + 416.39972 + ] + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to equals_operand_B:b_in", + "pos": [ + [ + 302.19995, + 165.9111 + ], + [ + 794.9999, + 436.39972 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from equals_operand_B:equals_out to operand_B_mux_1:select", + "pos": [ + [ + 828.9999, + 426.39972 + ], + [ + 802.79956, + 293.99988 + ] + ], + "input": { + "id": "equals_operand_B", + "field": "equals_out" + } + }, + { + "type": "Wire", + "id": "from reg_file:rt_value_out to operand_B_mux_1:in0", + "pos": [ + [ + 500.4, + 137.20001 + ], + [ + 792.79956, + 313.99988 + ] + ], + "input": { + "id": "reg_file", + "field": "rt_value_out" + } + }, + { + "type": "Wire", + "id": "from write_back_mux:mux_out to operand_B_mux_1:in1", + "pos": [ + [ + 1691.5999, + 270.00012 + ], + [ + 792.79956, + 333.99988 + ] + ], + "input": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to equals_operand_A:a_in", + "pos": [ + [ + 1490.0015, + 802.40173 + ], + [ + 786.1997, + 153.99988 + ] + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rs_out to equals_operand_A:b_in", + "pos": [ + [ + 302.19995, + 143.68887 + ], + [ + 786.1997, + 173.99988 + ] + ], + "input": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Wire", + "id": "from equals_operand_A:equals_out to operand_A_mux_1:select", + "pos": [ + [ + 820.1997, + 163.99988 + ], + [ + 799.6, + 195.60065 + ] + ], + "input": { + "id": "equals_operand_A", + "field": "equals_out" + } + }, + { + "type": "Wire", + "id": "from reg_file:rs_value_out to operand_A_mux_1:in0", + "pos": [ + [ + 500.4, + 217.20001 + ], + [ + 789.6, + 215.60065 + ] + ], + "input": { + "id": "reg_file", + "field": "rs_value_out" + } + }, + { + "type": "Wire", + "id": "from write_back_mux:mux_out to operand_A_mux_1:in1", + "pos": [ + [ + 1691.5999, + 270.00012 + ], + [ + 789.6, + 235.60065 + ] + ], + "input": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to equals_operand_B_2:a_in", + "pos": [ + [ + 1133.5989, + 794.3998 + ], + [ + 957.3968, + 416.40027 + ] + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to equals_operand_B_2:b_in", + "pos": [ + [ + 302.19995, + 165.9111 + ], + [ + 957.3968, + 436.40027 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", + "pos": [ + [ + 1490.0015, + 802.40173 + ], + [ + 1523.5994, + 802.3993 + ] + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", + "pos": [ + [ + 1483.6001, + -80.00018 + ], + [ + 1498.3997, + -80.0 + ] + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:alu_src_a to mux_source_a:select", + "pos": [ + [ + 1140.5334, + 40.699997 + ], + [ + 1242.4003, + 167.99994 + ] + ], + "input": { + "id": "control_unit_2", + "field": "alu_src_a" + } + }, + { + "type": "Wire", + "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", + "pos": [ + [ + 1207.7983, + 107.600006 + ], + [ + 1232.4003, + 187.99994 + ] + ], + "input": { + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" + } + }, + { + "type": "Wire", + "id": "from operand_a_reg:register_out to mux_source_a:in1", + "pos": [ + [ + 1103.1989, + 216.00018 + ], + [ + 1232.4003, + 207.99994 + ] + ], + "input": { + "id": "operand_a_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from 0_a_inp:constant_out to mux_source_a:in2", + "pos": [ + [ + 596.00006, + 48.40001 + ], + [ + 1232.4003, + 227.99994 + ] + ], + "input": { + "id": "0_a_inp", + "field": "constant_out" + } + }, + { + "type": "Wire", + "id": "from mux_source_a:mux_out to alu:full_add_a_in", + "pos": [ + [ + 1262.4003, + 207.99994 + ], + [ + 1375.9999, + 184.40002 + ] + ], + "input": { + "id": "mux_source_a", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from mux_source_b:mux_out to alu:full_add_b_in", + "pos": [ + [ + 1264.8002, + 325.60004 + ], + [ + 1375.9999, + 244.40002 + ] + ], + "input": { + "id": "mux_source_b", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:alu_op to alu:full_add_op_in", + "pos": [ + [ + 1307.2001, + 40.699997 + ], + [ + 1385.9999, + 174.40002 + ] + ], + "input": { + "id": "control_unit_2", + "field": "alu_op" + } + }, + { + "type": "Wire", + "id": "from equals_operand_A_2:equals_out to operand_A_mux_2:select", + "pos": [ + [ + 986.59796, + 167.20001 + ], + [ + 955.6015, + 197.99994 + ] + ], + "input": { + "id": "equals_operand_A_2", + "field": "equals_out" + } + }, + { + "type": "Wire", + "id": "from operand_A_mux_1:mux_out to operand_A_mux_2:in0", + "pos": [ + [ + 819.6, + 225.60065 + ], + [ + 945.6015, + 217.99994 + ] + ], + "input": { + "id": "operand_A_mux_1", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu:alu_out to operand_A_mux_2:in1", + "pos": [ + [ + 1415.9999, + 214.40002 + ], + [ + 945.6015, + 237.99994 + ] + ], + "input": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Wire", + "id": "from equals_operand_B_2:equals_out to operand_B_mux_2:select", + "pos": [ + [ + 991.3968, + 426.40027 + ], + [ + 956.4005, + 295.60052 + ] + ], + "input": { + "id": "equals_operand_B_2", + "field": "equals_out" + } + }, + { + "type": "Wire", + "id": "from operand_B_mux_1:mux_out to operand_B_mux_2:in0", + "pos": [ + [ + 822.79956, + 323.99988 + ], + [ + 946.4005, + 315.60052 + ] + ], + "input": { + "id": "operand_B_mux_1", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu:alu_out to operand_B_mux_2:in1", + "pos": [ + [ + 1415.9999, + 214.40002 + ], + [ + 946.4005, + 335.60052 + ] + ], + "input": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:op_out to branch:branch_op_in", + "pos": [ + [ + 302.19995, + 99.24443 + ], + [ + 1037.0, + 274.40002 + ] + ], + "input": { + "id": "instruction_split", + "field": "op_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to branch:branch_rt_in", + "pos": [ + [ + 302.19995, + 165.9111 + ], + [ + 1037.0, + 274.40002 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:funct_out to branch:branch_funct_in", + "pos": [ + [ + 302.19995, + 121.46665 + ], + [ + 1037.0, + 274.40002 + ] + ], + "input": { + "id": "instruction_split", + "field": "funct_out" + } + }, + { + "type": "Wire", + "id": "from operand_A_mux_2:mux_out to branch:branch_rs_value_id", + "pos": [ + [ + 975.6015, + 227.99994 + ], + [ + 1037.0, + 274.40002 + ] + ], + "input": { + "id": "operand_A_mux_2", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from operand_B_mux_2:mux_out to branch:branch_rt_value_id", + "pos": [ + [ + 976.4005, + 325.60052 + ], + [ + 1037.0, + 274.40002 + ] + ], + "input": { + "id": "operand_B_mux_2", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from branch:branch_out to mux_jump_merge:select", + "pos": [ + [ + 1037.0, + 274.40002 + ], + [ + -64.39996, + 330.40002 + ] + ], + "input": { + "id": "branch", + "field": "branch_out" + } + }, + { + "type": "Wire", + "id": "from pc_add_branch:add_out to mux_jump_merge:in0", + "pos": [ + [ + 440.0, + 440.0 + ], + [ + -74.39996, + 350.40002 + ] + ], + "input": { + "id": "pc_add_branch", + "field": "add_out" + } + }, + { + "type": "Wire", + "id": "from reg_file:rs_value_out to mux_jump_merge:in1", + "pos": [ + [ + 500.4, + 217.20001 + ], + [ + -74.39996, + 370.40002 + ] + ], + "input": { + "id": "reg_file", + "field": "rs_value_out" + } + }, + { + "type": "Wire", + "id": "from merge_reg:register_out to mux_jump_merge:in2", + "pos": [ + [ + 226.00024, + 582.40155 + ], + [ + -74.39996, + 390.40002 + ] + ], + "input": { + "id": "merge_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from pc+4:add_out to mux_jump_merge:in3", + "pos": [ + [ + 150.40002, + 380.8 + ], + [ + -74.39996, + 410.40002 + ] + ], + "input": { + "id": "pc+4", + "field": "add_out" + } + } + ] +} \ No newline at end of file From 9bfbb9a7c040eccee7f09dbbc84aa43ffbb39528 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Mon, 7 Oct 2024 15:21:03 +0200 Subject: [PATCH 03/18] updated example to match json --- mips-lib/examples/mips_pipe_example_1.rs | 6 +++--- mips-lib/mips_pipe.json | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index c93fd57..b04b63e 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -221,8 +221,8 @@ fn main() { Input::new("instruction_split", INSTRUCTION_SPLITTER_OP_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_FUNCT_ID), - Input::new("reg_file", reg_file_fields::RS_VALUE_OUT_ID), - Input::new("reg_file", reg_file_fields::RT_VALUE_OUT_ID), + Input::new("operand_A_mux_2", MUX_OUT_ID), + Input::new("operand_B_mux_2", MUX_OUT_ID), ), // // @@ -381,7 +381,7 @@ fn main() { (800.0, 270.0), Input::new("control_unit_3", cntr_field::REG_WRITE_SRC_OUT), vec![ - Input::new("alu", FULL_ADD_OUT_ID), + Input::new("alu_reg", REGISTER_OUT_ID), Input::new("data_mem", DATA_MEM_READ_DATA_OUT_ID), ], ), diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index 4ed6790..a9be933 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -2870,4 +2870,4 @@ } } ] -} \ No newline at end of file +} From 18e6e42c34552d5e0d1812096bdeecf5c1822981 Mon Sep 17 00:00:00 2001 From: malco <56635871+salon64@users.noreply.github.com> Date: Mon, 7 Oct 2024 14:23:10 +0200 Subject: [PATCH 04/18] added special case equals component, wip gui --- .../src/components/mips_equals_forward.rs | 100 ++++++++++++ mips-lib/src/components/mips_equals_load.rs | 145 ++++++++++++++++++ mips-lib/src/components/mod.rs | 4 + .../components/mips_equals_forward.rs | 91 +++++++++++ .../gui_egui/components/mips_equals_load.rs | 0 mips-lib/src/gui_egui/components/mod.rs | 2 + 6 files changed, 342 insertions(+) create mode 100644 mips-lib/src/components/mips_equals_forward.rs create mode 100644 mips-lib/src/components/mips_equals_load.rs create mode 100644 mips-lib/src/gui_egui/components/mips_equals_forward.rs create mode 100644 mips-lib/src/gui_egui/components/mips_equals_load.rs diff --git a/mips-lib/src/components/mips_equals_forward.rs b/mips-lib/src/components/mips_equals_forward.rs new file mode 100644 index 0000000..0c460e1 --- /dev/null +++ b/mips-lib/src/components/mips_equals_forward.rs @@ -0,0 +1,100 @@ +//TODO: add so it can take undefined number of inputs +use log::*; +use serde::{Deserialize, Serialize}; +use std::any::Any; +use std::rc::Rc; +use syncrim::common::{ + Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator, +}; +pub const EQUAL_A_IN_ID: &str = "a_in"; +pub const EQUAL_B_IN_ID: &str = "b_in"; +pub const EQUAL_WE_IN_ID: &str = "we_in"; + +pub const EQUAL_OUT_ID: &str = "equals_forward_out"; + +#[derive(Serialize, Deserialize, Clone)] +pub struct Equal { + pub(crate) id: Id, + pub(crate) pos: (f32, f32), + pub(crate) a_in: Input, + pub(crate) b_in: Input, + pub(crate) we_in: Input, +} + +#[typetag::serde] +impl Component for Equal { + fn to_(&self) { + trace!("Equal_Forward"); + } + + fn get_id_ports(&self) -> (Id, Ports) { + ( + self.id.clone(), + Ports::new( + vec![ + &InputPort { + port_id: EQUAL_A_IN_ID.to_string(), + input: self.a_in.clone(), + }, + &InputPort { + port_id: EQUAL_B_IN_ID.to_string(), + input: self.b_in.clone(), + }, + &InputPort { + port_id: EQUAL_WE_IN_ID.to_string(), + input: self.we_in.clone(), + }, + ], + OutputType::Combinatorial, + vec![EQUAL_OUT_ID], + ), + ) + } + + // propagate addition to output + fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> { + // get input values + let a_in: u32 = simulator.get_input_value(&self.a_in).try_into().unwrap(); + let b_in: u32 = simulator.get_input_value(&self.b_in).try_into().unwrap(); + let we_in: u32 = simulator.get_input_value(&self.we_in).try_into().unwrap(); + + let equal: u32 = (a_in == b_in) as u32; + let result: u32; + if we_in == 1 { + result = equal; + } else { + result = 0; + } + + simulator.set_out_value(&self.id, EQUAL_OUT_ID, SignalValue::Data(result)); + Ok(()) + } + + fn set_id_port(&mut self, target_port_id: Id, new_input: Input) { + match target_port_id.as_str() { + EQUAL_A_IN_ID => self.a_in = new_input, + EQUAL_B_IN_ID => self.b_in = new_input, + _ => (), + } + } + + fn as_any(&self) -> &dyn Any { + self + } +} + +impl Equal { + pub fn new(id: &str, pos: (f32, f32), a_in: Input, b_in: Input, we_in: Input) -> Self { + Equal { + id: id.to_string(), + pos, + a_in, + b_in, + we_in, + } + } + + pub fn rc_new(id: &str, pos: (f32, f32), a_in: Input, b_in: Input, we_in: Input) -> Rc { + Rc::new(Equal::new(id, pos, a_in, b_in, we_in)) + } +} diff --git a/mips-lib/src/components/mips_equals_load.rs b/mips-lib/src/components/mips_equals_load.rs new file mode 100644 index 0000000..42f8a0e --- /dev/null +++ b/mips-lib/src/components/mips_equals_load.rs @@ -0,0 +1,145 @@ +use data_op::{LOAD_BYTE, LOAD_BYTE_U, LOAD_HALF, LOAD_HALF_U, LOAD_WORD}; +//TODO: add so it can take undefined number of inputs +use log::*; +use serde::{Deserialize, Serialize}; +use std::any::Any; +use std::rc::Rc; +use syncrim::common::{ + Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator, +}; + +pub const EQUAL_A_IN_ID: &str = "a_in"; +pub const EQUAL_B_IN_ID: &str = "b_in"; +pub const EQUAL_WE_IN_ID: &str = "we_in"; +pub const EQUAL_LOAD_IN_ID: &str = "load_in"; + +pub const EQUAL_OUT_ID: &str = "equals_forward_out"; + +#[derive(Serialize, Deserialize, Clone)] +pub struct Equal { + pub(crate) id: Id, + pub(crate) pos: (f32, f32), + pub(crate) a_in: Input, + pub(crate) b_in: Input, + pub(crate) we_in: Input, + pub(crate) load_in: Input, +} + +pub mod data_op { + pub const NO_OP: u32 = 0; + + pub const LOAD_BYTE: u32 = 1; + pub const LOAD_BYTE_U: u32 = 2; + pub const LOAD_HALF: u32 = 3; + pub const LOAD_HALF_U: u32 = 4; + pub const LOAD_WORD: u32 = 5; + + pub const STORE_BYTE: u32 = 6; + pub const STORE_HALF: u32 = 7; + pub const STORE_WORD: u32 = 8; +} + +#[typetag::serde] +impl Component for Equal { + fn to_(&self) { + trace!("Equal_Load"); + } + + fn get_id_ports(&self) -> (Id, Ports) { + ( + self.id.clone(), + Ports::new( + vec![ + &InputPort { + port_id: EQUAL_A_IN_ID.to_string(), + input: self.a_in.clone(), + }, + &InputPort { + port_id: EQUAL_B_IN_ID.to_string(), + input: self.b_in.clone(), + }, + &InputPort { + port_id: EQUAL_WE_IN_ID.to_string(), + input: self.we_in.clone(), + }, + &InputPort { + port_id: EQUAL_LOAD_IN_ID.to_string(), + input: self.load_in.clone(), + }, + ], + OutputType::Combinatorial, + vec![EQUAL_OUT_ID], + ), + ) + } + + // propagate addition to output + fn clock(&self, simulator: &mut Simulator) -> Result<(), Condition> { + // get input values + let a_in: u32 = simulator.get_input_value(&self.a_in).try_into().unwrap(); + let b_in: u32 = simulator.get_input_value(&self.b_in).try_into().unwrap(); + let we_in: u32 = simulator.get_input_value(&self.we_in).try_into().unwrap(); + let load_in: u32 = simulator.get_input_value(&self.load_in).try_into().unwrap(); + + let equal: u32 = (a_in == b_in) as u32; + let result: u32; + + if we_in == 1 + && (load_in == LOAD_BYTE + || load_in == LOAD_BYTE_U + || load_in == LOAD_HALF + || load_in == LOAD_HALF_U + || load_in == LOAD_WORD) + { + result = equal; + } else { + result = 0; + } + + simulator.set_out_value(&self.id, EQUAL_OUT_ID, SignalValue::Data(result)); + Ok(()) + } + + fn set_id_port(&mut self, target_port_id: Id, new_input: Input) { + match target_port_id.as_str() { + EQUAL_A_IN_ID => self.a_in = new_input, + EQUAL_B_IN_ID => self.b_in = new_input, + _ => (), + } + } + + fn as_any(&self) -> &dyn Any { + self + } +} + +impl Equal { + pub fn new( + id: &str, + pos: (f32, f32), + a_in: Input, + b_in: Input, + we_in: Input, + load_in: Input, + ) -> Self { + Equal { + id: id.to_string(), + pos, + a_in, + b_in, + we_in, + load_in, + } + } + + pub fn rc_new( + id: &str, + pos: (f32, f32), + a_in: Input, + b_in: Input, + we_in: Input, + load_in: Input, + ) -> Rc { + Rc::new(Equal::new(id, pos, a_in, b_in, we_in, load_in)) + } +} diff --git a/mips-lib/src/components/mod.rs b/mips-lib/src/components/mod.rs index 95d9675..b496130 100644 --- a/mips-lib/src/components/mod.rs +++ b/mips-lib/src/components/mod.rs @@ -2,6 +2,8 @@ mod mips_alu; mod mips_branch_logic; mod mips_control_unit; mod mips_dm; +mod mips_equals_forward; +mod mips_equals_load; mod mips_im; mod mips_instruction_splitter; mod mips_jump_merge; @@ -13,6 +15,8 @@ pub use mips_alu::*; pub use mips_branch_logic::*; pub use mips_control_unit::*; pub use mips_dm::*; +pub use mips_equals_forward::*; +pub use mips_equals_load::*; pub use mips_im::*; pub use mips_instruction_splitter::*; pub use mips_jump_merge::*; diff --git a/mips-lib/src/gui_egui/components/mips_equals_forward.rs b/mips-lib/src/gui_egui/components/mips_equals_forward.rs new file mode 100644 index 0000000..3515eb7 --- /dev/null +++ b/mips-lib/src/gui_egui/components/mips_equals_forward.rs @@ -0,0 +1,91 @@ +use crate::common::{EguiComponent, Id, Input, Ports, Simulator}; +use crate::components::{Equal, EQUAL_A_IN_ID, EQUAL_B_IN_ID, EQUAL_OUT_ID}; +use crate::gui_egui::editor::{EditorMode, EditorRenderReturn, GridOptions}; +use crate::gui_egui::gui::EguiExtra; +use crate::gui_egui::helper::basic_component_gui; +use egui::{pos2, Rect, Response, Ui, Vec2}; + +#[typetag::serde] +impl EguiComponent for Equal { + fn render( + &self, + ui: &mut Ui, + _context: &mut EguiExtra, + simulator: Option<&mut Simulator>, + offset: Vec2, + scale: f32, + clip_rect: Rect, + _editor_mode: EditorMode, + ) -> Option> { + basic_component_gui(self, &simulator, ui.ctx(), offset, scale, clip_rect, |ui| { + ui.label("Equal_Load"); + }) + } + + fn render_editor( + &mut self, + ui: &mut egui::Ui, + context: &mut EguiExtra, + simulator: Option<&mut Simulator>, + offset: egui::Vec2, + scale: f32, + clip_rect: egui::Rect, + _id_ports: &[(Id, Ports)], + _grid: &GridOptions, + editor_mode: EditorMode, + ) -> EditorRenderReturn { + self.render( + ui, + context, + simulator, + offset, + scale, + clip_rect, + editor_mode, + ); + EditorRenderReturn { + delete: false, + resp: None, + } + } + + fn set_pos(&mut self, pos: (f32, f32)) { + self.pos = pos; + } + + fn get_pos(&self) -> (f32, f32) { + self.pos + } + + fn top_padding(&self) -> f32 { + 20f32 + } + + fn get_input_location(&self, id: Input) -> Option<(f32, f32)> { + let loc = self + .ports_location() + .iter() + .map(|(_, loc)| <(f32, f32)>::from(loc)) + .collect::>(); + if id == self.a_in { + Some(loc[0]) + } else if id == self.b_in { + Some(loc[1]) + } else if id == Input::new(&self.id, EQUAL_OUT_ID) { + Some(loc[2]) + } else { + None + } + } + + fn ports_location(&self) -> Vec<(Id, egui::Pos2)> { + //size 22-14 + let m = 6f32; // margin + let pos: Vec2 = self.pos.into(); + vec![ + (EQUAL_A_IN_ID.to_string(), pos2(-11.0 - m, -10.0) + pos), + (EQUAL_B_IN_ID.to_string(), pos2(-11.0 - m, 10.0) + pos), + (EQUAL_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), + ] + } +} diff --git a/mips-lib/src/gui_egui/components/mips_equals_load.rs b/mips-lib/src/gui_egui/components/mips_equals_load.rs new file mode 100644 index 0000000..e69de29 diff --git a/mips-lib/src/gui_egui/components/mod.rs b/mips-lib/src/gui_egui/components/mod.rs index b28720e..d20118e 100644 --- a/mips-lib/src/gui_egui/components/mod.rs +++ b/mips-lib/src/gui_egui/components/mod.rs @@ -2,6 +2,8 @@ mod full_adder; mod mips_branch_logic; mod mips_control_unit; mod mips_dm; +mod mips_equals_forward; +mod mips_equals_load; mod mips_im; mod mips_instruction_splitter; mod mips_jump_merge; From 9e7c9607a2669644e9245e17e57c2f3f15142f82 Mon Sep 17 00:00:00 2001 From: malco <56635871+salon64@users.noreply.github.com> Date: Mon, 7 Oct 2024 15:16:38 +0200 Subject: [PATCH 05/18] gui added --- .../src/components/mips_equals_forward.rs | 34 +++--- mips-lib/src/components/mips_equals_load.rs | 56 ++++------ .../components/mips_equals_forward.rs | 35 ++++-- .../gui_egui/components/mips_equals_load.rs | 103 ++++++++++++++++++ 4 files changed, 166 insertions(+), 62 deletions(-) diff --git a/mips-lib/src/components/mips_equals_forward.rs b/mips-lib/src/components/mips_equals_forward.rs index 0c460e1..b55f2e7 100644 --- a/mips-lib/src/components/mips_equals_forward.rs +++ b/mips-lib/src/components/mips_equals_forward.rs @@ -6,14 +6,14 @@ use std::rc::Rc; use syncrim::common::{ Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator, }; -pub const EQUAL_A_IN_ID: &str = "a_in"; -pub const EQUAL_B_IN_ID: &str = "b_in"; -pub const EQUAL_WE_IN_ID: &str = "we_in"; +pub const EQUAL_FORWARD_A_IN_ID: &str = "a_in"; +pub const EQUAL_FORWARD_B_IN_ID: &str = "b_in"; +pub const EQUAL_FORWARD_WE_IN_ID: &str = "we_in"; -pub const EQUAL_OUT_ID: &str = "equals_forward_out"; +pub const EQUAL_FORWARD_OUT_ID: &str = "equals_forward_out"; #[derive(Serialize, Deserialize, Clone)] -pub struct Equal { +pub struct EqualForward { pub(crate) id: Id, pub(crate) pos: (f32, f32), pub(crate) a_in: Input, @@ -22,9 +22,9 @@ pub struct Equal { } #[typetag::serde] -impl Component for Equal { +impl Component for EqualForward { fn to_(&self) { - trace!("Equal_Forward"); + trace!("EqualForward"); } fn get_id_ports(&self) -> (Id, Ports) { @@ -33,20 +33,20 @@ impl Component for Equal { Ports::new( vec![ &InputPort { - port_id: EQUAL_A_IN_ID.to_string(), + port_id: EQUAL_FORWARD_A_IN_ID.to_string(), input: self.a_in.clone(), }, &InputPort { - port_id: EQUAL_B_IN_ID.to_string(), + port_id: EQUAL_FORWARD_B_IN_ID.to_string(), input: self.b_in.clone(), }, &InputPort { - port_id: EQUAL_WE_IN_ID.to_string(), + port_id: EQUAL_FORWARD_WE_IN_ID.to_string(), input: self.we_in.clone(), }, ], OutputType::Combinatorial, - vec![EQUAL_OUT_ID], + vec![EQUAL_FORWARD_OUT_ID], ), ) } @@ -66,14 +66,14 @@ impl Component for Equal { result = 0; } - simulator.set_out_value(&self.id, EQUAL_OUT_ID, SignalValue::Data(result)); + simulator.set_out_value(&self.id, EQUAL_FORWARD_OUT_ID, SignalValue::Data(result)); Ok(()) } fn set_id_port(&mut self, target_port_id: Id, new_input: Input) { match target_port_id.as_str() { - EQUAL_A_IN_ID => self.a_in = new_input, - EQUAL_B_IN_ID => self.b_in = new_input, + EQUAL_FORWARD_A_IN_ID => self.a_in = new_input, + EQUAL_FORWARD_B_IN_ID => self.b_in = new_input, _ => (), } } @@ -83,9 +83,9 @@ impl Component for Equal { } } -impl Equal { +impl EqualForward { pub fn new(id: &str, pos: (f32, f32), a_in: Input, b_in: Input, we_in: Input) -> Self { - Equal { + EqualForward { id: id.to_string(), pos, a_in, @@ -95,6 +95,6 @@ impl Equal { } pub fn rc_new(id: &str, pos: (f32, f32), a_in: Input, b_in: Input, we_in: Input) -> Rc { - Rc::new(Equal::new(id, pos, a_in, b_in, we_in)) + Rc::new(EqualForward::new(id, pos, a_in, b_in, we_in)) } } diff --git a/mips-lib/src/components/mips_equals_load.rs b/mips-lib/src/components/mips_equals_load.rs index 42f8a0e..4352875 100644 --- a/mips-lib/src/components/mips_equals_load.rs +++ b/mips-lib/src/components/mips_equals_load.rs @@ -1,5 +1,3 @@ -use data_op::{LOAD_BYTE, LOAD_BYTE_U, LOAD_HALF, LOAD_HALF_U, LOAD_WORD}; -//TODO: add so it can take undefined number of inputs use log::*; use serde::{Deserialize, Serialize}; use std::any::Any; @@ -8,15 +6,17 @@ use syncrim::common::{ Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator, }; -pub const EQUAL_A_IN_ID: &str = "a_in"; -pub const EQUAL_B_IN_ID: &str = "b_in"; -pub const EQUAL_WE_IN_ID: &str = "we_in"; -pub const EQUAL_LOAD_IN_ID: &str = "load_in"; +use super::data_op::{LOAD_BYTE, LOAD_BYTE_U, LOAD_HALF, LOAD_HALF_U, LOAD_WORD}; -pub const EQUAL_OUT_ID: &str = "equals_forward_out"; +pub const EQUAL_LOAD_A_IN_ID: &str = "a_in"; +pub const EQUAL_LOAD_B_IN_ID: &str = "b_in"; +pub const EQUAL_LOAD_WE_IN_ID: &str = "we_in"; +pub const EQUAL_LOAD_LOAD_IN_ID: &str = "load_in"; + +pub const EQUAL_LOAD_OUT_ID: &str = "equals_forward_out"; #[derive(Serialize, Deserialize, Clone)] -pub struct Equal { +pub struct EqualLoad { pub(crate) id: Id, pub(crate) pos: (f32, f32), pub(crate) a_in: Input, @@ -25,24 +25,10 @@ pub struct Equal { pub(crate) load_in: Input, } -pub mod data_op { - pub const NO_OP: u32 = 0; - - pub const LOAD_BYTE: u32 = 1; - pub const LOAD_BYTE_U: u32 = 2; - pub const LOAD_HALF: u32 = 3; - pub const LOAD_HALF_U: u32 = 4; - pub const LOAD_WORD: u32 = 5; - - pub const STORE_BYTE: u32 = 6; - pub const STORE_HALF: u32 = 7; - pub const STORE_WORD: u32 = 8; -} - #[typetag::serde] -impl Component for Equal { +impl Component for EqualLoad { fn to_(&self) { - trace!("Equal_Load"); + trace!("EqualLoad"); } fn get_id_ports(&self) -> (Id, Ports) { @@ -51,24 +37,24 @@ impl Component for Equal { Ports::new( vec![ &InputPort { - port_id: EQUAL_A_IN_ID.to_string(), + port_id: EQUAL_LOAD_A_IN_ID.to_string(), input: self.a_in.clone(), }, &InputPort { - port_id: EQUAL_B_IN_ID.to_string(), + port_id: EQUAL_LOAD_B_IN_ID.to_string(), input: self.b_in.clone(), }, &InputPort { - port_id: EQUAL_WE_IN_ID.to_string(), + port_id: EQUAL_LOAD_WE_IN_ID.to_string(), input: self.we_in.clone(), }, &InputPort { - port_id: EQUAL_LOAD_IN_ID.to_string(), + port_id: EQUAL_LOAD_LOAD_IN_ID.to_string(), input: self.load_in.clone(), }, ], OutputType::Combinatorial, - vec![EQUAL_OUT_ID], + vec![EQUAL_LOAD_OUT_ID], ), ) } @@ -96,14 +82,14 @@ impl Component for Equal { result = 0; } - simulator.set_out_value(&self.id, EQUAL_OUT_ID, SignalValue::Data(result)); + simulator.set_out_value(&self.id, EQUAL_LOAD_OUT_ID, SignalValue::Data(result)); Ok(()) } fn set_id_port(&mut self, target_port_id: Id, new_input: Input) { match target_port_id.as_str() { - EQUAL_A_IN_ID => self.a_in = new_input, - EQUAL_B_IN_ID => self.b_in = new_input, + EQUAL_LOAD_A_IN_ID => self.a_in = new_input, + EQUAL_LOAD_B_IN_ID => self.b_in = new_input, _ => (), } } @@ -113,7 +99,7 @@ impl Component for Equal { } } -impl Equal { +impl EqualLoad { pub fn new( id: &str, pos: (f32, f32), @@ -122,7 +108,7 @@ impl Equal { we_in: Input, load_in: Input, ) -> Self { - Equal { + EqualLoad { id: id.to_string(), pos, a_in, @@ -140,6 +126,6 @@ impl Equal { we_in: Input, load_in: Input, ) -> Rc { - Rc::new(Equal::new(id, pos, a_in, b_in, we_in, load_in)) + Rc::new(EqualLoad::new(id, pos, a_in, b_in, we_in, load_in)) } } diff --git a/mips-lib/src/gui_egui/components/mips_equals_forward.rs b/mips-lib/src/gui_egui/components/mips_equals_forward.rs index 3515eb7..1225a0f 100644 --- a/mips-lib/src/gui_egui/components/mips_equals_forward.rs +++ b/mips-lib/src/gui_egui/components/mips_equals_forward.rs @@ -1,12 +1,15 @@ -use crate::common::{EguiComponent, Id, Input, Ports, Simulator}; -use crate::components::{Equal, EQUAL_A_IN_ID, EQUAL_B_IN_ID, EQUAL_OUT_ID}; -use crate::gui_egui::editor::{EditorMode, EditorRenderReturn, GridOptions}; -use crate::gui_egui::gui::EguiExtra; -use crate::gui_egui::helper::basic_component_gui; +use crate::components::{ + EqualForward, EQUAL_FORWARD_A_IN_ID, EQUAL_FORWARD_B_IN_ID, EQUAL_FORWARD_OUT_ID, + EQUAL_FORWARD_WE_IN_ID, +}; use egui::{pos2, Rect, Response, Ui, Vec2}; +use syncrim::common::{EguiComponent, Id, Input, Ports, Simulator}; +use syncrim::gui_egui::editor::{EditorMode, EditorRenderReturn, GridOptions}; +use syncrim::gui_egui::gui::EguiExtra; +use syncrim::gui_egui::helper::basic_component_gui; #[typetag::serde] -impl EguiComponent for Equal { +impl EguiComponent for EqualForward { fn render( &self, ui: &mut Ui, @@ -71,8 +74,10 @@ impl EguiComponent for Equal { Some(loc[0]) } else if id == self.b_in { Some(loc[1]) - } else if id == Input::new(&self.id, EQUAL_OUT_ID) { + } else if id == self.we_in { Some(loc[2]) + } else if id == Input::new(&self.id, EQUAL_FORWARD_OUT_ID) { + Some(loc[3]) } else { None } @@ -83,9 +88,19 @@ impl EguiComponent for Equal { let m = 6f32; // margin let pos: Vec2 = self.pos.into(); vec![ - (EQUAL_A_IN_ID.to_string(), pos2(-11.0 - m, -10.0) + pos), - (EQUAL_B_IN_ID.to_string(), pos2(-11.0 - m, 10.0) + pos), - (EQUAL_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), + ( + EQUAL_FORWARD_A_IN_ID.to_string(), + pos2(-11.0 - m, -10.0) + pos, + ), + ( + EQUAL_FORWARD_B_IN_ID.to_string(), + pos2(-11.0 - m, 10.0) + pos, + ), + ( + EQUAL_FORWARD_WE_IN_ID.to_string(), + pos2(-11.0 - m, 0.0) + pos, + ), + (EQUAL_FORWARD_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), ] } } diff --git a/mips-lib/src/gui_egui/components/mips_equals_load.rs b/mips-lib/src/gui_egui/components/mips_equals_load.rs index e69de29..b309244 100644 --- a/mips-lib/src/gui_egui/components/mips_equals_load.rs +++ b/mips-lib/src/gui_egui/components/mips_equals_load.rs @@ -0,0 +1,103 @@ +use crate::components::{ + EqualLoad, EQUAL_LOAD_A_IN_ID, EQUAL_LOAD_B_IN_ID, EQUAL_LOAD_LOAD_IN_ID, EQUAL_LOAD_OUT_ID, + EQUAL_LOAD_WE_IN_ID, +}; +use egui::{pos2, Rect, Response, Ui, Vec2}; +use syncrim::common::{EguiComponent, Id, Input, Ports, Simulator}; +use syncrim::gui_egui::editor::{EditorMode, EditorRenderReturn, GridOptions}; +use syncrim::gui_egui::gui::EguiExtra; +use syncrim::gui_egui::helper::basic_component_gui; + +#[typetag::serde] +impl EguiComponent for EqualLoad { + fn render( + &self, + ui: &mut Ui, + _context: &mut EguiExtra, + simulator: Option<&mut Simulator>, + offset: Vec2, + scale: f32, + clip_rect: Rect, + _editor_mode: EditorMode, + ) -> Option> { + basic_component_gui(self, &simulator, ui.ctx(), offset, scale, clip_rect, |ui| { + ui.label("Equal_Load"); + }) + } + + fn render_editor( + &mut self, + ui: &mut egui::Ui, + context: &mut EguiExtra, + simulator: Option<&mut Simulator>, + offset: egui::Vec2, + scale: f32, + clip_rect: egui::Rect, + _id_ports: &[(Id, Ports)], + _grid: &GridOptions, + editor_mode: EditorMode, + ) -> EditorRenderReturn { + self.render( + ui, + context, + simulator, + offset, + scale, + clip_rect, + editor_mode, + ); + EditorRenderReturn { + delete: false, + resp: None, + } + } + + fn set_pos(&mut self, pos: (f32, f32)) { + self.pos = pos; + } + + fn get_pos(&self) -> (f32, f32) { + self.pos + } + + fn top_padding(&self) -> f32 { + 20f32 + } + + fn get_input_location(&self, id: Input) -> Option<(f32, f32)> { + let loc = self + .ports_location() + .iter() + .map(|(_, loc)| <(f32, f32)>::from(loc)) + .collect::>(); + if id == self.a_in { + Some(loc[0]) + } else if id == self.b_in { + Some(loc[1]) + } else if id == self.we_in { + Some(loc[2]) + } else if id == self.load_in { + Some(loc[3]) + } else if id == Input::new(&self.id, EQUAL_LOAD_OUT_ID) { + Some(loc[4]) + } else { + None + } + } + + fn ports_location(&self) -> Vec<(Id, egui::Pos2)> { + //size 22-14 + let m = 6f32; // margin + let pos: Vec2 = self.pos.into(); + vec![ + (EQUAL_LOAD_A_IN_ID.to_string(), pos2(-11.0 - m, -10.0) + pos), + (EQUAL_LOAD_B_IN_ID.to_string(), pos2(-11.0 - m, 10.0) + pos), + (EQUAL_LOAD_WE_IN_ID.to_string(), pos2(-11.0 - m, 2.5) + pos), + ( + EQUAL_LOAD_LOAD_IN_ID.to_string(), + pos2(-11.0 - m, 7.5) + pos, + ), + (EQUAL_LOAD_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), + ] + } +} From 6da7be643aa1b0f21d26f6a350a673bd86ce6deb Mon Sep 17 00:00:00 2001 From: malco <56635871+salon64@users.noreply.github.com> Date: Mon, 7 Oct 2024 15:51:39 +0200 Subject: [PATCH 06/18] this does not work --- mips-lib/examples/mips_pipe_example_1.rs | 50 +++++++++++++++++++----- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index b04b63e..9755da5 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -143,17 +143,24 @@ fn main() { // // // - Equal::rc_new( + // Equal::rc_new( + // "equals_operand_A", + // (3200.0, 1700.0), + // Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), + // Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), + // ), + EqualForward::rc_new( "equals_operand_A", (3200.0, 1700.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), + Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), ), // Mux::rc_new( "operand_A_mux_1", (3200.0, 1800.0), - Input::new("equals_operand_A", EQUAL_OUT_ID), + Input::new("equals_operand_A", EQUAL_FORWARD_OUT_ID), vec![ Input::new("reg_file", reg_file_fields::RS_VALUE_OUT_ID), Input::new("write_back_mux", MUX_OUT_ID), @@ -161,17 +168,24 @@ fn main() { ), // // - Equal::rc_new( + // Equal::rc_new( + // "equals_operand_B", + // (3200.0, 2300.0), + // Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), + // Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), + // ), + EqualForward::rc_new( "equals_operand_B", (3200.0, 2300.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), + Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), ), // Mux::rc_new( "operand_B_mux_1", (3200.0, 2200.0), - Input::new("equals_operand_B", EQUAL_OUT_ID), + Input::new("equals_operand_B", EQUAL_FORWARD_OUT_ID), vec![ Input::new("reg_file", reg_file_fields::RT_VALUE_OUT_ID), Input::new("write_back_mux", MUX_OUT_ID), @@ -179,17 +193,25 @@ fn main() { ), // // - Equal::rc_new( + // Equal::rc_new( + // "equals_operand_A_2", + // (3300.0, 1700.0), + // Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), + // Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), + // ), + EqualLoad::rc_new( "equals_operand_A_2", (3300.0, 1700.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), + Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), + Input::new("control_unit_2", cntr_field::MEM_MODE_OUT), ), // Mux::rc_new( "operand_A_mux_2", (3300.0, 1800.0), - Input::new("equals_operand_A_2", EQUAL_OUT_ID), + Input::new("equals_operand_A_2", EQUAL_LOAD_OUT_ID), vec![ Input::new("operand_A_mux_1", MUX_OUT_ID), Input::new("alu", FULL_ADD_OUT_ID), @@ -197,17 +219,25 @@ fn main() { ), // // - Equal::rc_new( + // Equal::rc_new( + // "equals_operand_B_2", + // (3300.0, 2300.0), + // Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), + // Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), + // ), + EqualLoad::rc_new( "equals_operand_B_2", (3300.0, 2300.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), + Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), + Input::new("control_unit_2", cntr_field::MEM_MODE_OUT), ), // Mux::rc_new( "operand_B_mux_2", (3300.0, 2200.0), - Input::new("equals_operand_B_2", EQUAL_OUT_ID), + Input::new("equals_operand_B_2", EQUAL_LOAD_OUT_ID), vec![ Input::new("operand_B_mux_1", MUX_OUT_ID), Input::new("alu", FULL_ADD_OUT_ID), @@ -248,14 +278,14 @@ fn main() { //TODO: fix after adding 4 muxes "operand_a_reg", (3450.0, 1800.0), - Input::new("equals_operand_A_2", EQUAL_OUT_ID), + Input::new("operand_A_mux_2", MUX_OUT_ID), ), // Register::rc_new( //TODO: fix after muxes "operand_b_reg", (3450.0, 2200.0), - Input::new("equals_operand_B_2", EQUAL_OUT_ID), + Input::new("operand_B_mux_2", MUX_OUT_ID), ), PassThrough::rc_new( "operand_b_pass", From c860dd5e5b0b213510a7aa99326f176e9b66cc05 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Mon, 7 Oct 2024 21:40:05 +0200 Subject: [PATCH 07/18] updated mips pipe example positions --- mips-lib/examples/mips_pipe_example_1.rs | 112 +++++++++++------------ 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index 9755da5..5e5a985 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -14,7 +14,7 @@ fn main() { let rc_reg_file = RegFile::rc_new( "reg_file", - (360.0, 170.0), + (435.0, 180.0), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("reg_addr_reg", REGISTER_OUT_ID), //write address @@ -32,10 +32,10 @@ fn main() { Input::new("mux_jump_merge", MUX_OUT_ID), ), // step addr from reg by 4 - Constant::rc_new("+4", (170.0, 380.0), 4), + Constant::rc_new("+4", (80.0, 380.0), 4), Add::rc_new( "pc+4", - (220.0, 380.0), + (130.0, 380.0), Input::new("pc", REGISTER_OUT_ID), Input::new("+4", CONSTANT_OUT_ID), ), @@ -43,7 +43,7 @@ fn main() { // Rc::new(InstrMem::new( "instr_mem".into(), - (280.0, 600.0), + (100.0, 585.0), Input::new("pc", REGISTER_OUT_ID), "phys_mem".into(), "reg_file".into(), @@ -53,7 +53,7 @@ fn main() { // MUX to choose what instruction addr to choose from, branch jump, reg, pc+4 Mux::rc_new( "mux_jump_merge", - (140.0, 390.0), + (-54.0, 390.0), Input::new("branch", BRANCH_OUT_ID), vec![ Input::new("pc_add_branch", ADD_OUT_ID), // describe origin @@ -66,68 +66,68 @@ fn main() { // merges to find out jump location JumpMerge::rc_new( "jump_merge", - (125.0, 500.0), + (-62.0, 500.0), Input::new("pc", REGISTER_OUT_ID), //input from reg before pc+4 Input::new("instr_mem", INSTR_MEM_INSTRUCTION_ID), //input from instruction mem ), // // - Register::rc_new("pc+4_reg", (2300.0, 5000.0), Input::new("pc+4", ADD_OUT_ID)), + Register::rc_new("pc+4_reg", (200.0, 370.0), Input::new("pc+4", ADD_OUT_ID)), PassThrough::rc_new( "pc+4_pass", - (2350.0, 5000.0), + (240.0, 370.0), Input::new("pc+4_reg", REGISTER_OUT_ID), ), // Register::rc_new( "InMem_reg", - (2300.0, 5200.0), + (210.0, 475.0), Input::new("instr_mem", INSTR_MEM_INSTRUCTION_ID), ), + PassThrough::rc_new( + "InMem_pass", + (250.0, 475.0), + Input::new("InMem_reg", REGISTER_OUT_ID), + ), // Register::rc_new( "merge_reg", - (2300.0, 5300.0), + (215.0, 580.0), Input::new("jump_merge", MERGE_OUT_ID), ), // // splits instructions from ir to fields InstrSplit::rc_new( "instruction_split", - (280.0, 140.0), - Input::new("InMem_reg", REGISTER_OUT_ID), - ), - PassThrough::rc_new( - "InMem_pass", - (280.0, 140.0), + (270.0, 150.0), Input::new("InMem_reg", REGISTER_OUT_ID), ), // // First CU, handles, select for sign/zero_extend and mux_write_addr ControlUnit::rc_new( "control_unit_1", - (280.0, 100.0), + (260.0, 0.0), Input::new("InMem_reg", REGISTER_OUT_ID), ), // // Second CU, handles, mux_source_a, mux_source_b and the alu ControlUnit::rc_new( "control_unit_2", - (380.0, 100.0), + (1200.0, 0.0), Input::new("control_EX_reg", REGISTER_OUT_ID), ), // // Third CU, handles, write_back_mux, and DMs mem-read and mem-write ControlUnit::rc_new( "control_unit_3", - (480.0, 100.0), + (1670.0, 0.0), Input::new("control_MEM_reg", REGISTER_OUT_ID), ), // // Fourth CU, handles, WE for reg_file in the WB stage ControlUnit::rc_new( "control_unit_4", - (580.0, 100.0), + (2216.0, 0.0), Input::new("control_WB_reg", REGISTER_OUT_ID), ), // @@ -151,7 +151,7 @@ fn main() { // ), EqualForward::rc_new( "equals_operand_A", - (3200.0, 1700.0), + (800.0, 160.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), @@ -159,7 +159,7 @@ fn main() { // Mux::rc_new( "operand_A_mux_1", - (3200.0, 1800.0), + (800.0, 225.0), Input::new("equals_operand_A", EQUAL_FORWARD_OUT_ID), vec![ Input::new("reg_file", reg_file_fields::RS_VALUE_OUT_ID), @@ -176,7 +176,7 @@ fn main() { // ), EqualForward::rc_new( "equals_operand_B", - (3200.0, 2300.0), + (800.0, 425.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), @@ -184,7 +184,7 @@ fn main() { // Mux::rc_new( "operand_B_mux_1", - (3200.0, 2200.0), + (800.0, 325.0), Input::new("equals_operand_B", EQUAL_FORWARD_OUT_ID), vec![ Input::new("reg_file", reg_file_fields::RT_VALUE_OUT_ID), @@ -201,7 +201,7 @@ fn main() { // ), EqualLoad::rc_new( "equals_operand_A_2", - (3300.0, 1700.0), + (970.0, 160.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), @@ -210,7 +210,7 @@ fn main() { // Mux::rc_new( "operand_A_mux_2", - (3300.0, 1800.0), + (970.0, 225.0), Input::new("equals_operand_A_2", EQUAL_LOAD_OUT_ID), vec![ Input::new("operand_A_mux_1", MUX_OUT_ID), @@ -227,7 +227,7 @@ fn main() { // ), EqualLoad::rc_new( "equals_operand_B_2", - (3300.0, 2300.0), + (970.0, 425.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), @@ -236,7 +236,7 @@ fn main() { // Mux::rc_new( "operand_B_mux_2", - (3300.0, 2200.0), + (970.0, 325.0), Input::new("equals_operand_B_2", EQUAL_LOAD_OUT_ID), vec![ Input::new("operand_B_mux_1", MUX_OUT_ID), @@ -247,7 +247,7 @@ fn main() { // BranchLogic::rc_new( "branch", - (525.0, 300.0), + (1040.0, 275.0), Input::new("instruction_split", INSTRUCTION_SPLITTER_OP_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_FUNCT_ID), @@ -259,74 +259,74 @@ fn main() { Register::rc_new( //TODO: make 2 more control units "control_EX_reg", - (3450.0, 1400.0), + (920.0, -40.0), Input::new("InMem_pass", PASS_THROUGH_OUT_ID), ), PassThrough::rc_new( "control_EX_pass", - (3480.0, 1400.0), + (960.0, -40.0), Input::new("control_EX_reg", REGISTER_OUT_ID), ), // Register::rc_new( "zero_extend_reg", - (3450.0, 1600.0), + (1100.0, 110.0), Input::new("instruction_split", INSTRUCTION_SPLITTER_SHAMT_ID), ), // Register::rc_new( //TODO: fix after adding 4 muxes "operand_a_reg", - (3450.0, 1800.0), + (1100.0, 215.0), Input::new("operand_A_mux_2", MUX_OUT_ID), ), // Register::rc_new( //TODO: fix after muxes "operand_b_reg", - (3450.0, 2200.0), + (1100.0, 325.0), Input::new("operand_B_mux_2", MUX_OUT_ID), ), PassThrough::rc_new( "operand_b_pass", - (4200.0, 2500.0), + (1140.0, 325.0), Input::new("operand_b_reg", REGISTER_OUT_ID), ), // Register::rc_new( "mux_b2_reg", - (3450.0, 5000.0), + (1100.0, 550.0), Input::new("pc+4_pass", PASS_THROUGH_OUT_ID), ), Register::rc_new( "mux_b3_reg", - (3450.0, 5100.0), + (1100.0, 625.0), Input::new("signzero_extend", SIGNZEROEXTEND_OUT_ID), ), // Register::rc_new( "reg_addr_EX_reg", - (3450.0, 5500.0), + (1125.0, 800.0), Input::new("mux_write_addr", MUX_OUT_ID), ), PassThrough::rc_new( "reg_addr_EX_pass", - (3450.0, 5500.0), + (1165.0, 800.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), ), // // ZeroExtend::rc_new( "zero_extend_for_shamt", - (550.0, 170.0), + (1165.0, 110.0), Input::new("zero_extend_reg", REGISTER_OUT_ID), ), // // - Constant::rc_new("0_a_inp", (600.0, 230.0), 0), + Constant::rc_new("0_a_inp", (600.0, 50.0), 4), Mux::rc_new( "mux_source_a", - (650.0, 220.0), + (1250.0, 210.0), Input::new("control_unit_2", cntr_field::ALU_SRC_A_OUT), vec![ Input::new("zero_extend_for_shamt", ZEROEXTEND_OUT_ID), @@ -338,7 +338,7 @@ fn main() { // Mux::rc_new( "mux_source_b", - (650.0, 300.0), + (1250.0, 325.0), Input::new("control_unit_2", cntr_field::ALU_SRC_B_OUT), vec![ Input::new("operand_b_reg", REGISTER_OUT_ID), @@ -352,7 +352,7 @@ fn main() { // ALU::rc_new( "alu", - (720.0, 220.0), + (1400.0, 220.0), Input::new("mux_source_a", MUX_OUT_ID), Input::new("mux_source_b", MUX_OUT_ID), Input::new("control_unit_2", cntr_field::ALU_OP_OUT), @@ -361,7 +361,7 @@ fn main() { // Rc::new(DataMem::new( "data_mem".into(), - (600.0, 580.0), + (1660.0, 560.0), Input::new("alu_reg", REGISTER_OUT_ID), // calculated from rs and imm Input::new("data_MEM_reg", REGISTER_OUT_ID), Input::new("control_unit_3", cntr_field::MEM_MODE_OUT), @@ -373,42 +373,42 @@ fn main() { // Register::rc_new( "control_MEM_reg", - (4200.0, 1400.0), + (1470.0, -40.0), Input::new("control_EX_pass", PASS_THROUGH_OUT_ID), ), PassThrough::rc_new( "control_MEM_pass", - (4200.0, 1400.0), + (1510.0, -40.0), Input::new("control_MEM_reg", REGISTER_OUT_ID), ), // Register::rc_new( "alu_reg", - (4200.0, 2000.0), + (1470.0, 250.0), Input::new("alu", FULL_ADD_OUT_ID), ), // Register::rc_new( "data_MEM_reg", - (4200.0, 2500.0), + (1470.0, 565.0), Input::new("operand_b_pass", PASS_THROUGH_OUT_ID), ), // Register::rc_new( "reg_addr_MEM_reg", - (4200.0, 5500.0), + (1480.0, 800.0), Input::new("reg_addr_EX_pass", PASS_THROUGH_OUT_ID), ), PassThrough::rc_new( "reg_addr_MEM_pass", - (4250.0, 5500.0), + (1520.0, 800.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), ), // // Mux::rc_new( "write_back_mux", - (800.0, 270.0), + (1680.0, 270.0), Input::new("control_unit_3", cntr_field::REG_WRITE_SRC_OUT), vec![ Input::new("alu_reg", REGISTER_OUT_ID), @@ -419,19 +419,19 @@ fn main() { // Register::rc_new( "control_WB_reg", - (4400.0, 1400.0), + (1920.0, -40.0), Input::new("control_MEM_pass", PASS_THROUGH_OUT_ID), ), // Register::rc_new( "result_reg_EX", - (4400.0, 2200.0), + (1920.0, 270.0), Input::new("write_back_mux", MUX_OUT_ID), ), // Register::rc_new( "reg_addr_reg", - (4400.0, 5500.0), + (1920.0, 800.0), Input::new("reg_addr_MEM_pass", PASS_THROUGH_OUT_ID), ), // @@ -447,7 +447,7 @@ fn main() { Add::rc_new( "pc_add_branch", (420.0, 440.0), - Input::new("pc+4", ADD_OUT_ID), + Input::new("pc+4_reg", REGISTER_OUT_ID), Input::new("branch_shift", SHIFT_OUT_ID), ), // From 2345157197d7d9953a3eb6d5bfe703eee1f31ddb Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Tue, 8 Oct 2024 14:51:18 +0200 Subject: [PATCH 08/18] Made mips pipe almost work by fixing equal_load, and changed equal froward to use cu3 --- mips-lib/examples/mips_pipe_example_1.rs | 4 ++-- mips-lib/src/components/mips_equals_load.rs | 12 ++++-------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index 5e5a985..fcf7c4f 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -154,7 +154,7 @@ fn main() { (800.0, 160.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), - Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), + Input::new("control_unit_3", cntr_field::REG_WRITE_ENABLE_OUT), ), // Mux::rc_new( @@ -179,7 +179,7 @@ fn main() { (800.0, 425.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), - Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), + Input::new("control_unit_3", cntr_field::REG_WRITE_ENABLE_OUT), ), // Mux::rc_new( diff --git a/mips-lib/src/components/mips_equals_load.rs b/mips-lib/src/components/mips_equals_load.rs index 4352875..9aba547 100644 --- a/mips-lib/src/components/mips_equals_load.rs +++ b/mips-lib/src/components/mips_equals_load.rs @@ -6,7 +6,7 @@ use syncrim::common::{ Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator, }; -use super::data_op::{LOAD_BYTE, LOAD_BYTE_U, LOAD_HALF, LOAD_HALF_U, LOAD_WORD}; +use super::data_op::NO_OP; pub const EQUAL_LOAD_A_IN_ID: &str = "a_in"; pub const EQUAL_LOAD_B_IN_ID: &str = "b_in"; @@ -70,13 +70,9 @@ impl Component for EqualLoad { let equal: u32 = (a_in == b_in) as u32; let result: u32; - if we_in == 1 - && (load_in == LOAD_BYTE - || load_in == LOAD_BYTE_U - || load_in == LOAD_HALF - || load_in == LOAD_HALF_U - || load_in == LOAD_WORD) - { + // if the instruction is write forward + // dont forward if its some from adrs calc for lw or sw + if we_in == 1 && load_in == NO_OP { result = equal; } else { result = 0; From 9d2afc7114700566cf52faed749a68edd198fc61 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Wed, 9 Oct 2024 13:03:13 +0200 Subject: [PATCH 09/18] fix mips cu zero extending addiu --- mips-lib/src/components/mips_control_unit.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/mips-lib/src/components/mips_control_unit.rs b/mips-lib/src/components/mips_control_unit.rs index 19de48a..427bf7e 100644 --- a/mips-lib/src/components/mips_control_unit.rs +++ b/mips-lib/src/components/mips_control_unit.rs @@ -554,6 +554,10 @@ impl Component for ControlUnit { } OP_ADDIU => { set_i_instr!(); + set!( + cntr_field::EXTEND_SELECT_OUT, + cntr_unit_signals::EXTEND_SIGNED + ); set!(cntr_field::ALU_OP_OUT, alu_op::ADDU); Ok(()) } From 95cc3ecc1047273b8c409dc8f52a7f6b0b7a80a6 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Wed, 9 Oct 2024 13:03:51 +0200 Subject: [PATCH 10/18] fixed wrong connections in mips pipe --- mips-lib/examples/mips_pipe_example_1.rs | 6 +- mips-lib/mips_pipe.json | 2570 ++++------------------ 2 files changed, 406 insertions(+), 2170 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index fcf7c4f..b64cd1e 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -56,9 +56,9 @@ fn main() { (-54.0, 390.0), Input::new("branch", BRANCH_OUT_ID), vec![ - Input::new("pc_add_branch", ADD_OUT_ID), // describe origin - Input::new("reg_file", reg_file_fields::RS_VALUE_OUT_ID), // goes to addr, RD2 - Input::new("merge_reg", REGISTER_OUT_ID), // + Input::new("pc_add_branch", ADD_OUT_ID), // describe origin + Input::new("operand_A_mux_2", MUX_OUT_ID), // goes to addr, RD2 + Input::new("merge_reg", REGISTER_OUT_ID), // Input::new("pc+4", ADD_OUT_ID), ], ), diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index a9be933..810c85f 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -1,17 +1,5 @@ { "store": [ - { - "type": "Register", - "id": "operand_a_reg", - "pos": [ - 1093.1989, - 216.00018 - ], - "r_in": { - "id": "operand_A_mux_2", - "field": "mux_out" - } - }, { "type": "Register", "id": "mux_b2_reg", @@ -26,98 +14,98 @@ }, { "type": "Register", - "id": "InMem_reg", + "id": "mux_b3_reg", "pos": [ - 208.7998, - 474.4015 + 1101.1995, + 624.7999 ], "r_in": { - "id": "instr_mem", - "field": "instruction" + "id": "signzero_extend", + "field": "sz_out" } }, { "type": "Register", - "id": "zero_extend_reg", + "id": "reg_addr_EX_reg", "pos": [ - 1098.0002, - 107.20001 + 1123.5989, + 794.3998 ], "r_in": { - "id": "instruction_split", - "field": "shamt_out" + "id": "mux_write_addr", + "field": "mux_out" } }, { "type": "Register", - "id": "alu_reg", + "id": "control_WB_reg", "pos": [ - 1470.4004, - 252.79993 + 1918.4001, + -73.60004 ], "r_in": { - "id": "alu", - "field": "alu_out" + "id": "control_MEM_pass", + "field": "pass_through_out" } }, { "type": "Register", - "id": "merge_reg", + "id": "reg_addr_reg", "pos": [ - 216.00024, - 582.40155 + 1947.2009, + 799.2012 ], "r_in": { - "id": "jump_merge", - "field": "merge_out" + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" } }, { "type": "Register", - "id": "reg_addr_EX_reg", + "id": "control_MEM_reg", "pos": [ - 1123.5989, - 794.3998 + 1473.6001, + -80.00018 ], "r_in": { - "id": "mux_write_addr", - "field": "mux_out" + "id": "control_EX_pass", + "field": "pass_through_out" } }, { "type": "Register", - "id": "control_WB_reg", + "id": "reg_addr_MEM_reg", "pos": [ - 1918.4001, - -73.60004 + 1480.0015, + 802.40173 ], "r_in": { - "id": "control_MEM_pass", + "id": "reg_addr_EX_pass", "field": "pass_through_out" } }, { "type": "Register", - "id": "mux_b3_reg", + "id": "alu_reg", "pos": [ - 1101.1995, - 624.7999 + 1470.4004, + 252.79993 ], "r_in": { - "id": "signzero_extend", - "field": "sz_out" + "id": "alu", + "field": "alu_out" } }, { "type": "Register", - "id": "operand_b_reg", + "id": "zero_extend_reg", "pos": [ - 1101.1985, - 324.80035 + 1098.0002, + 107.20001 ], "r_in": { - "id": "operand_B_mux_2", - "field": "mux_out" + "id": "instruction_split", + "field": "shamt_out" } }, { @@ -134,38 +122,38 @@ }, { "type": "Register", - "id": "pc", + "id": "InMem_reg", "pos": [ - 79.60004, - 415.60004 + 208.7998, + 474.4015 ], "r_in": { - "id": "mux_jump_merge", - "field": "mux_out" + "id": "instr_mem", + "field": "instruction" } }, { "type": "Register", - "id": "control_MEM_reg", + "id": "operand_b_reg", "pos": [ - 1473.6001, - -80.00018 + 1101.1985, + 324.80035 ], "r_in": { - "id": "control_EX_pass", - "field": "pass_through_out" + "id": "operand_B_mux_2", + "field": "mux_out" } }, { "type": "Register", - "id": "control_EX_reg", + "id": "result_reg_EX", "pos": [ - 918.7965, - -38.400085 + 1918.3983, + 268.79993 ], "r_in": { - "id": "InMem_pass", - "field": "pass_through_out" + "id": "write_back_mux", + "field": "mux_out" } }, { @@ -182,58 +170,90 @@ }, { "type": "Register", - "id": "result_reg_EX", + "id": "pc", "pos": [ - 1918.3983, - 268.79993 + 79.60004, + 415.60004 ], "r_in": { - "id": "write_back_mux", + "id": "mux_jump_merge", "field": "mux_out" } }, { "type": "Register", - "id": "reg_addr_reg", + "id": "merge_reg", "pos": [ - 1947.2009, - 799.2012 + 216.00024, + 582.40155 ], "r_in": { - "id": "reg_addr_MEM_pass", - "field": "pass_through_out" + "id": "jump_merge", + "field": "merge_out" } }, { "type": "Register", - "id": "reg_addr_MEM_reg", + "id": "control_EX_reg", "pos": [ - 1480.0015, - 802.40173 + 918.7965, + -38.400085 ], "r_in": { - "id": "reg_addr_EX_pass", + "id": "InMem_pass", "field": "pass_through_out" } }, { - "type": "ZeroExtend", - "id": "zero_extend_for_shamt", + "type": "Register", + "id": "operand_a_reg", "pos": [ - 1166.7983, - 107.600006 + 1093.1989, + 216.00018 ], - "signal_in": { - "id": "zero_extend_reg", + "r_in": { + "id": "operand_A_mux_2", + "field": "mux_out" + } + }, + { + "type": "ControlUnit", + "id": "control_unit_3", + "pos": [ + 1667.2002, + 27.199997 + ], + "a_in": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "reg_addr_MEM_pass", + "pos": [ + 1523.5994, + 802.3993 + ], + "input": { + "id": "reg_addr_MEM_reg", "field": "register_out" } }, + { + "type": "PhysicalMem", + "id": "phys_mem", + "pos": [ + 0.0, + 0.0 + ] + }, { "type": "Constant", - "id": "+4", + "id": "0_a_inp", "pos": [ - 78.80005, - 382.39996 + 596.00006, + 48.40001 ], "value": { "data": { @@ -261,78 +281,187 @@ }, { "type": "PassThrough", - "id": "reg_addr_EX_pass", + "id": "pc+4_pass", "pos": [ - 1153.9998, - 794.401 + 235.60022, + 371.99823 ], "input": { - "id": "reg_addr_EX_reg", + "id": "pc+4_reg", "field": "register_out" } }, { - "type": "PassThrough", - "id": "InMem_pass", + "type": "InstrSplit", + "id": "instruction_split", "pos": [ - 232.40002, - 474.8 + 271.19995, + 154.79999 ], - "input": { + "instruction_in": { "id": "InMem_reg", "field": "register_out" } }, { - "type": "ControlUnit", - "id": "control_unit_1", + "type": "Equal", + "id": "equals_operand_B", "pos": [ - 263.2, - 2.4000092 + 811.9999, + 426.39972 ], "a_in": { - "id": "InMem_reg", + "id": "reg_addr_MEM_reg", "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" } }, { - "type": "PassThrough", - "id": "operand_b_pass", + "type": "Equal", + "id": "equals_operand_B_2", "pos": [ - 1160.8, - 360.00006 + 974.3968, + 426.40027 ], - "input": { - "id": "operand_b_reg", + "a_in": { + "id": "reg_addr_EX_reg", "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" } }, { - "type": "PassThrough", - "id": "pc+4_pass", + "type": "Equal", + "id": "equals_operand_A_2", "pos": [ - 235.60022, - 371.99823 + 969.59796, + 167.20001 ], - "input": { - "id": "pc+4_reg", + "a_in": { + "id": "reg_addr_EX_reg", "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "PassThrough", + "id": "operand_b_pass", + "pos": [ + 1160.8, + 360.00006 + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" + } + }, + { + "type": "Equal", + "id": "equals_operand_A", + "pos": [ + 803.1997, + 163.99988 + ], + "a_in": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "RegFile", + "id": "reg_file", + "pos": [ + 434.4, + 177.20001 + ], + "rs_address_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "rt_address_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "write_address_in": { + "id": "reg_addr_reg", + "field": "register_out" + }, + "write_data_in": { + "id": "result_reg_EX", + "field": "register_out" + }, + "write_enable_in": { + "id": "control_unit_4", + "field": "reg_write_enable" + } + }, + { + "type": "ControlUnit", + "id": "control_unit_1", + "pos": [ + 263.2, + 2.4000092 + ], + "a_in": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "SignZeroExtend", + "id": "signzero_extend", + "pos": [ + 310.0, + 410.0 + ], + "signzero_signal_in": { + "id": "instruction_split", + "field": "immediate_out" + }, + "signzero_ctrl_in": { + "id": "control_unit_1", + "field": "extend_select" } }, + { + "type": "ShiftConst", + "id": "branch_shift", + "pos": [ + 380.0, + 460.0 + ], + "signal_in": { + "id": "signzero_extend", + "field": "sz_out" + }, + "shift_by": 2 + }, { "type": "Add", - "id": "pc+4", + "id": "pc_add_branch", "pos": [ - 130.40002, - 380.8 + 420.0, + 440.0 ], "a_in": { - "id": "pc", + "id": "pc+4_reg", "field": "register_out" }, "b_in": { - "id": "+4", - "field": "constant_out" + "id": "branch_shift", + "field": "shift_left_const_out" }, "scale": 1.0 }, @@ -350,7 +479,7 @@ "phys_mem_id": "phys_mem", "regfile_id": "reg_file", "mem_view": { - "visible": true, + "visible": false, "title": "instruction memory view", "id": "instr_mem", "row_offset": 0, @@ -399,17 +528,9 @@ "register_values": [ 0, 0, - 4020265517, 0, - 4512, - 4175, 0, 0, - 1478048723, - 3184185328, - 56462194, - 274701634, - 4176, 0, 0, 0, @@ -426,13 +547,21 @@ 0, 0, 0, - 2147481728, - 2147481744, - 152 + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 ], "dynamic_symbols": { "PC_IM": [ - 276, + 0, true ] }, @@ -458,89 +587,34 @@ } }, { - "type": "InstrSplit", - "id": "instruction_split", + "type": "PassThrough", + "id": "InMem_pass", "pos": [ - 271.19995, - 154.79999 + 232.40002, + 474.8 ], - "instruction_in": { + "input": { "id": "InMem_reg", "field": "register_out" } }, { - "type": "Equal", - "id": "equals_operand_A_2", - "pos": [ - 969.59796, - 167.20001 - ], - "a_in": { - "id": "reg_addr_EX_reg", - "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "SignZeroExtend", - "id": "signzero_extend", - "pos": [ - 310.0, - 410.0 - ], - "signzero_signal_in": { - "id": "instruction_split", - "field": "immediate_out" - }, - "signzero_ctrl_in": { - "id": "control_unit_1", - "field": "extend_select" - } - }, - { - "type": "ShiftConst", - "id": "branch_shift", - "pos": [ - 380.0, - 460.0 - ], - "signal_in": { - "id": "signzero_extend", - "field": "sz_out" - }, - "shift_by": 2 - }, - { - "type": "Add", - "id": "pc_add_branch", - "pos": [ - 420.0, - 440.0 - ], - "a_in": { - "id": "pc+4_reg", - "field": "register_out" - }, - "b_in": { - "id": "branch_shift", - "field": "shift_left_const_out" - }, - "scale": 1.0 - }, - { - "type": "ControlUnit", - "id": "control_unit_3", + "type": "Constant", + "id": "+4", "pos": [ - 1667.2002, - 27.199997 + 78.80005, + 382.39996 ], - "a_in": { - "id": "control_MEM_reg", - "field": "register_out" + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { @@ -569,7 +643,7 @@ "phys_mem_id": "phys_mem", "regfile_id": "reg_file", "mem_view": { - "visible": true, + "visible": false, "title": "Data memory view", "id": "data_mem", "row_offset": 512, @@ -618,17 +692,9 @@ "register_values": [ 0, 0, - 4020265517, 0, - 4512, - 4175, 0, 0, - 1478048723, - 3184185328, - 56462194, - 274701634, - 4176, 0, 0, 0, @@ -645,13 +711,21 @@ 0, 0, 0, - 2147481728, - 2147481744, - 152 + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 ], "dynamic_symbols": { "DM_ADRS": [ - 4175, + 0, false ] }, @@ -661,44 +735,67 @@ } }, { - "type": "PassThrough", - "id": "control_EX_pass", + "type": "Mux", + "id": "write_back_mux", "pos": [ - 944.7983, - -39.19998 + 1681.5999, + 270.00012 ], - "input": { - "id": "control_EX_reg", - "field": "register_out" - } + "select": { + "id": "control_unit_3", + "field": "reg_write_src" + }, + "m_in": [ + { + "id": "alu_reg", + "field": "register_out" + }, + { + "id": "data_mem", + "field": "data_out" + } + ], + "scale": 1.0 }, { - "type": "RegFile", - "id": "reg_file", + "type": "Mux", + "id": "operand_A_mux_1", "pos": [ - 434.4, - 177.20001 + 809.6, + 225.60065 ], - "rs_address_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "rt_address_in": { - "id": "instruction_split", - "field": "rt_out" + "select": { + "id": "equals_operand_A", + "field": "equals_out" }, - "write_address_in": { - "id": "reg_addr_reg", + "m_in": [ + { + "id": "reg_file", + "field": "rs_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, + { + "type": "Add", + "id": "pc+4", + "pos": [ + 130.40002, + 380.8 + ], + "a_in": { + "id": "pc", "field": "register_out" }, - "write_data_in": { - "id": "result_reg_EX", - "field": "register_out" + "b_in": { + "id": "+4", + "field": "constant_out" }, - "write_enable_in": { - "id": "control_unit_4", - "field": "reg_write_enable" - } + "scale": 1.0 }, { "type": "ControlUnit", @@ -739,6 +836,41 @@ ], "scale": 1.0 }, + { + "type": "Mux", + "id": "operand_B_mux_1", + "pos": [ + 812.79956, + 323.99988 + ], + "select": { + "id": "equals_operand_B", + "field": "equals_out" + }, + "m_in": [ + { + "id": "reg_file", + "field": "rt_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, + { + "type": "PassThrough", + "id": "control_MEM_pass", + "pos": [ + 1498.3997, + -80.0 + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, { "type": "Constant", "id": "0x_1F", @@ -786,165 +918,17 @@ "scale": 1.0 }, { - "type": "Mux", - "id": "write_back_mux", - "pos": [ - 1681.5999, - 270.00012 - ], - "select": { - "id": "control_unit_3", - "field": "reg_write_src" - }, - "m_in": [ - { - "id": "alu_reg", - "field": "register_out" - }, - { - "id": "data_mem", - "field": "data_out" - } - ], - "scale": 1.0 - }, - { - "type": "Equal", - "id": "equals_operand_B", - "pos": [ - 811.9999, - 426.39972 - ], - "a_in": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Mux", - "id": "operand_B_mux_1", - "pos": [ - 812.79956, - 323.99988 - ], - "select": { - "id": "equals_operand_B", - "field": "equals_out" - }, - "m_in": [ - { - "id": "reg_file", - "field": "rt_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } - ], - "scale": 1.0 - }, - { - "type": "Equal", - "id": "equals_operand_A", - "pos": [ - 803.1997, - 163.99988 - ], - "a_in": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "Mux", - "id": "operand_A_mux_1", - "pos": [ - 809.6, - 225.60065 - ], - "select": { - "id": "equals_operand_A", - "field": "equals_out" - }, - "m_in": [ - { - "id": "reg_file", - "field": "rs_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } - ], - "scale": 1.0 - }, - { - "type": "Equal", - "id": "equals_operand_B_2", - "pos": [ - 974.3968, - 426.40027 - ], - "a_in": { - "id": "reg_addr_EX_reg", - "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "PassThrough", - "id": "reg_addr_MEM_pass", - "pos": [ - 1523.5994, - 802.3993 - ], - "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - } - }, - { - "type": "PassThrough", - "id": "control_MEM_pass", + "type": "ZeroExtend", + "id": "zero_extend_for_shamt", "pos": [ - 1498.3997, - -80.0 + 1166.7983, + 107.600006 ], - "input": { - "id": "control_MEM_reg", + "signal_in": { + "id": "zero_extend_reg", "field": "register_out" } }, - { - "type": "Constant", - "id": "0_a_inp", - "pos": [ - 596.00006, - 48.40001 - ], - "value": { - "data": { - "Data": 4 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } - } - }, { "type": "Mux", "id": "mux_source_a", @@ -1015,6 +999,18 @@ ], "scale": 1.0 }, + { + "type": "PassThrough", + "id": "control_EX_pass", + "pos": [ + 944.7983, + -39.19998 + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, { "type": "Mux", "id": "operand_B_mux_2", @@ -1098,1776 +1094,16 @@ "scale": 1.0 }, { - "type": "PhysicalMem", - "id": "phys_mem", - "pos": [ - 0.0, - 0.0 - ] - }, - { - "type": "Wire", - "id": "from operand_A_mux_2:mux_out to operand_a_reg:r_in", - "pos": [ - [ - 975.6015, - 227.99994 - ], - [ - 1083.1989, - 216.00018 - ] - ], - "input": { - "id": "operand_A_mux_2", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", - "pos": [ - [ - 235.60022, - 371.99823 - ], - [ - 1081.6001, - 547.2002 - ] - ], - "input": { - "id": "pc+4_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from instr_mem:instruction to InMem_reg:r_in", - "pos": [ - [ - 138.40002, - 552.1 - ], - [ - 198.7998, - 474.4015 - ] - ], - "input": { - "id": "instr_mem", - "field": "instruction" - } - }, - { - "type": "Wire", - "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", - "pos": [ - [ - 302.19995, - 77.02221 - ], - [ - 1088.0002, - 107.20001 - ] - ], - "input": { - "id": "instruction_split", - "field": "shamt_out" - } - }, - { - "type": "Wire", - "id": "from alu:alu_out to alu_reg:r_in", - "pos": [ - [ - 1415.9999, - 214.40002 - ], - [ - 1460.4004, - 252.79993 - ] - ], - "input": { - "id": "alu", - "field": "alu_out" - } - }, - { - "type": "Wire", - "id": "from jump_merge:merge_out to merge_reg:r_in", - "pos": [ - [ - -62.200012, - 492.80005 - ], - [ - 206.00024, - 582.40155 - ] - ], - "input": { - "id": "jump_merge", - "field": "merge_out" - } - }, - { - "type": "Wire", - "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", - "pos": [ - [ - 570.0, - 500.0 - ], - [ - 1113.5989, - 794.3998 - ] - ], - "input": { - "id": "mux_write_addr", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", - "pos": [ - [ - 1498.3997, - -80.0 - ], - [ - 1908.4001, - -73.60004 - ] - ], - "input": { - "id": "control_MEM_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", - "pos": [ - [ - 368.5, - 410.0 - ], - [ - 1091.1995, - 624.7999 - ] - ], - "input": { - "id": "signzero_extend", - "field": "sz_out" - } - }, - { - "type": "Wire", - "id": "from operand_B_mux_2:mux_out to operand_b_reg:r_in", - "pos": [ - [ - 976.4005, - 325.60052 - ], - [ - 1091.1985, - 324.80035 - ] - ], - "input": { - "id": "operand_B_mux_2", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from pc+4:add_out to pc+4_reg:r_in", - "pos": [ - [ - 150.40002, - 380.8 - ], - [ - 191.59985, - 371.20197 - ] - ], - "input": { - "id": "pc+4", - "field": "add_out" - } - }, - { - "type": "Wire", - "id": "from mux_jump_merge:mux_out to pc:r_in", - "pos": [ - [ - -44.399963, - 380.40002 - ], - [ - 69.60004, - 415.60004 - ] - ], - "input": { - "id": "mux_jump_merge", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", - "pos": [ - [ - 944.7983, - -39.19998 - ], - [ - 1463.6001, - -80.00018 - ] - ], - "input": { - "id": "control_EX_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", - "pos": [ - [ - 232.40002, - 474.8 - ], - [ - 908.7965, - -38.400085 - ] - ], - "input": { - "id": "InMem_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", - "pos": [ - [ - 1160.8, - 360.00006 - ], - [ - 1467.6, - 566.4001 - ] - ], - "input": { - "id": "operand_b_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from write_back_mux:mux_out to result_reg_EX:r_in", - "pos": [ - [ - 1691.5999, - 270.00012 - ], - [ - 1908.3983, - 268.79993 - ] - ], - "input": { - "id": "write_back_mux", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", - "pos": [ - [ - 1523.5994, - 802.3993 - ], - [ - 1937.2009, - 799.2012 - ] - ], - "input": { - "id": "reg_addr_MEM_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", - "pos": [ - [ - 1153.9998, - 794.401 - ], - [ - 1470.0015, - 802.40173 - ] - ], - "input": { - "id": "reg_addr_EX_pass", - "field": "pass_through_out" - } - }, - { - "type": "Wire", - "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", - "pos": [ - [ - 1108.0002, - 107.20001 - ], - [ - 1125.7983, - 107.600006 - ] - ], - "input": { - "id": "zero_extend_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", - "pos": [ - [ - 1928.4001, - -73.60004 - ], - [ - 2010.0002, - 23.200073 - ] - ], - "input": { - "id": "control_WB_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", - "pos": [ - [ - 1133.5989, - 794.3998 - ], - [ - 1153.9998, - 794.401 - ] - ], - "input": { - "id": "reg_addr_EX_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", - "pos": [ - [ - 218.7998, - 474.4015 - ], - [ - 232.40002, - 474.8 - ] - ], - "input": { - "id": "InMem_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", - "pos": [ - [ - 218.7998, - 474.4015 - ], - [ - 57.200012, - 2.4000092 - ] - ], - "input": { - "id": "InMem_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", - "pos": [ - [ - 1111.1985, - 324.80035 - ], - [ - 1160.8, - 360.00006 - ] - ], - "input": { - "id": "operand_b_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", - "pos": [ - [ - 211.59985, - 371.20197 - ], - [ - 235.60022, - 371.99823 - ] - ], - "input": { - "id": "pc+4_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from pc:register_out to pc+4:a_in", - "pos": [ - [ - 89.60004, - 415.60004 - ], - [ - 110.400024, - 360.8 - ] - ], - "input": { - "id": "pc", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from +4:constant_out to pc+4:b_in", - "pos": [ - [ - 78.80005, - 382.39996 - ], - [ - 110.400024, - 400.8 - ] - ], - "input": { - "id": "+4", - "field": "constant_out" - } - }, - { - "type": "Wire", - "id": "from pc:register_out to instr_mem:pc", - "pos": [ - [ - 89.60004, - 415.60004 - ], - [ - 58.400024, - 552.1 - ] - ], - "input": { - "id": "pc", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from pc:register_out to jump_merge:merge_instr_addr_in", - "pos": [ - [ - 89.60004, - 415.60004 - ], - [ - -62.200012, - 492.80005 - ] - ], - "input": { - "id": "pc", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", - "pos": [ - [ - 138.40002, - 552.1 - ], - [ - -62.200012, - 492.80005 - ] - ], - "input": { - "id": "instr_mem", - "field": "instruction" - } - }, - { - "type": "Wire", - "id": "from InMem_reg:register_out to instruction_split:instruction_in", - "pos": [ - [ - 218.7998, - 474.4015 - ], - [ - 240.19995, - 154.79999 - ] - ], - "input": { - "id": "InMem_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to equals_operand_A_2:a_in", - "pos": [ - [ - 1133.5989, - 794.3998 - ], - [ - 952.59796, - 157.20001 - ] - ], - "input": { - "id": "reg_addr_EX_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rs_out to equals_operand_A_2:b_in", - "pos": [ - [ - 302.19995, - 143.68887 - ], - [ - 952.59796, - 177.20001 - ] - ], - "input": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", - "pos": [ - [ - 302.19995, - 188.13332 - ], - [ - 251.5, - 410.0 - ] - ], - "input": { - "id": "instruction_split", - "field": "immediate_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", - "pos": [ - [ - 96.53334, - 15.900009 - ], - [ - 310.0, - 389.0 - ] - ], - "input": { - "id": "control_unit_1", - "field": "extend_select" - } - }, - { - "type": "Wire", - "id": "from signzero_extend:sz_out to branch_shift:shift_in", - "pos": [ - [ - 368.5, - 410.0 - ], - [ - 346.5, - 460.0 - ] - ], - "input": { - "id": "signzero_extend", - "field": "sz_out" - } - }, - { - "type": "Wire", - "id": "from pc+4_reg:register_out to pc_add_branch:a_in", - "pos": [ - [ - 211.59985, - 371.20197 - ], - [ - 400.0, - 420.0 - ] - ], - "input": { - "id": "pc+4_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", - "pos": [ - [ - 413.5, - 460.0 - ], - [ - 400.0, - 460.0 - ] - ], - "input": { - "id": "branch_shift", - "field": "shift_left_const_out" - } - }, - { - "type": "Wire", - "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", - "pos": [ - [ - 1483.6001, - -80.00018 - ], - [ - 1461.2002, - 27.199997 - ] - ], - "input": { - "id": "control_MEM_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from alu_reg:register_out to data_mem:data_mem_address_in", - "pos": [ - [ - 1480.4004, - 252.79993 - ], - [ - 1635.5996, - 527.3 - ] - ], - "input": { - "id": "alu_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", - "pos": [ - [ - 1700.5336, - 40.699997 - ], - [ - 1695.5996, - 527.3 - ] - ], - "input": { - "id": "control_unit_3", - "field": "mem_mode" - } - }, - { - "type": "Wire", - "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", - "pos": [ - [ - 1487.6, - 566.4001 - ], - [ - 1599.5996, - 560.8 - ] - ], - "input": { - "id": "data_MEM_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", - "pos": [ - [ - 1667.2002, - 40.699997 - ], - [ - 1665.5996, - 527.3 - ] - ], - "input": { - "id": "control_unit_3", - "field": "mem_write_enable" - } - }, - { - "type": "Wire", - "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", - "pos": [ - [ - 928.7965, - -38.400085 - ], - [ - 944.7983, - -39.19998 - ] - ], - "input": { - "id": "control_EX_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rs_out to reg_file:rs_address_in", - "pos": [ - [ - 302.19995, - 143.68887 - ], - [ - 434.4, - 46.200012 - ] - ], - "input": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rt_out to reg_file:rt_address_in", - "pos": [ - [ - 302.19995, - 165.9111 - ], - [ - 434.4, - 308.2 - ] - ], - "input": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_reg:register_out to reg_file:write_address_in", - "pos": [ - [ - 1957.2009, - 799.2012 - ], - [ - 368.4, - 267.2 - ] - ], - "input": { - "id": "reg_addr_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from result_reg_EX:register_out to reg_file:write_data_in", - "pos": [ - [ - 1928.3983, - 268.79993 - ], - [ - 368.4, - 287.2 - ] - ], - "input": { - "id": "result_reg_EX", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", - "pos": [ - [ - 2382.667, - 36.700073 - ], - [ - 368.4, - 247.20001 - ] - ], - "input": { - "id": "control_unit_4", - "field": "reg_write_enable" - } - }, - { - "type": "Wire", - "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", - "pos": [ - [ - 928.7965, - -38.400085 - ], - [ - 1001.2001, - 27.199997 - ] - ], - "input": { - "id": "control_EX_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_2:alu_src_b to mux_source_b:select", - "pos": [ - [ - 1173.8667, - 40.699997 - ], - [ - 1244.8002, - 285.60004 - ] - ], - "input": { - "id": "control_unit_2", - "field": "alu_src_b" - } - }, - { - "type": "Wire", - "id": "from operand_b_reg:register_out to mux_source_b:in0", - "pos": [ - [ - 1111.1985, - 324.80035 - ], - [ - 1234.8002, - 305.60004 - ] - ], - "input": { - "id": "operand_b_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from mux_b2_reg:register_out to mux_source_b:in1", - "pos": [ - [ - 1101.6001, - 547.2002 - ], - [ - 1234.8002, - 325.60004 - ] - ], - "input": { - "id": "mux_b2_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from mux_b3_reg:register_out to mux_source_b:in2", - "pos": [ - [ - 1111.1995, - 624.7999 - ], - [ - 1234.8002, - 345.60004 - ] - ], - "input": { - "id": "mux_b3_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_1:reg_dest to mux_write_addr:select", - "pos": [ - [ - 163.20001, - 15.900009 - ], - [ - 550.0, - 460.0 - ] - ], - "input": { - "id": "control_unit_1", - "field": "reg_dest" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rt_out to mux_write_addr:in0", - "pos": [ - [ - 302.19995, - 165.9111 - ], - [ - 540.0, - 480.0 - ] - ], - "input": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rd_out to mux_write_addr:in1", - "pos": [ - [ - 302.19995, - 210.35555 - ], - [ - 540.0, - 500.0 - ] - ], - "input": { - "id": "instruction_split", - "field": "rd_out" - } - }, - { - "type": "Wire", - "id": "from 0x_1F:constant_out to mux_write_addr:in2", - "pos": [ - [ - 500.0, - 510.0 - ], - [ - 540.0, - 520.0 - ] - ], - "input": { - "id": "0x_1F", - "field": "constant_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_3:reg_write_src to write_back_mux:select", - "pos": [ - [ - 1800.5336, - 40.699997 - ], - [ - 1671.5999, - 240.00012 - ] - ], - "input": { - "id": "control_unit_3", - "field": "reg_write_src" - } - }, - { - "type": "Wire", - "id": "from alu_reg:register_out to write_back_mux:in0", - "pos": [ - [ - 1480.4004, - 252.79993 - ], - [ - 1661.5999, - 260.00012 - ] - ], - "input": { - "id": "alu_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from data_mem:data_out to write_back_mux:in1", - "pos": [ - [ - 1731.5996, - 560.8 - ], - [ - 1661.5999, - 280.00012 - ] - ], - "input": { - "id": "data_mem", - "field": "data_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to equals_operand_B:a_in", - "pos": [ - [ - 1490.0015, - 802.40173 - ], - [ - 794.9999, - 416.39972 - ] - ], - "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rt_out to equals_operand_B:b_in", - "pos": [ - [ - 302.19995, - 165.9111 - ], - [ - 794.9999, - 436.39972 - ] - ], - "input": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Wire", - "id": "from equals_operand_B:equals_out to operand_B_mux_1:select", - "pos": [ - [ - 828.9999, - 426.39972 - ], - [ - 802.79956, - 293.99988 - ] - ], - "input": { - "id": "equals_operand_B", - "field": "equals_out" - } - }, - { - "type": "Wire", - "id": "from reg_file:rt_value_out to operand_B_mux_1:in0", - "pos": [ - [ - 500.4, - 137.20001 - ], - [ - 792.79956, - 313.99988 - ] - ], - "input": { - "id": "reg_file", - "field": "rt_value_out" - } - }, - { - "type": "Wire", - "id": "from write_back_mux:mux_out to operand_B_mux_1:in1", - "pos": [ - [ - 1691.5999, - 270.00012 - ], - [ - 792.79956, - 333.99988 - ] - ], - "input": { - "id": "write_back_mux", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to equals_operand_A:a_in", - "pos": [ - [ - 1490.0015, - 802.40173 - ], - [ - 786.1997, - 153.99988 - ] - ], - "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rs_out to equals_operand_A:b_in", - "pos": [ - [ - 302.19995, - 143.68887 - ], - [ - 786.1997, - 173.99988 - ] - ], - "input": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "Wire", - "id": "from equals_operand_A:equals_out to operand_A_mux_1:select", - "pos": [ - [ - 820.1997, - 163.99988 - ], - [ - 799.6, - 195.60065 - ] - ], - "input": { - "id": "equals_operand_A", - "field": "equals_out" - } - }, - { - "type": "Wire", - "id": "from reg_file:rs_value_out to operand_A_mux_1:in0", - "pos": [ - [ - 500.4, - 217.20001 - ], - [ - 789.6, - 215.60065 - ] - ], - "input": { - "id": "reg_file", - "field": "rs_value_out" - } - }, - { - "type": "Wire", - "id": "from write_back_mux:mux_out to operand_A_mux_1:in1", - "pos": [ - [ - 1691.5999, - 270.00012 - ], - [ - 789.6, - 235.60065 - ] - ], - "input": { - "id": "write_back_mux", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to equals_operand_B_2:a_in", + "type": "PassThrough", + "id": "reg_addr_EX_pass", "pos": [ - [ - 1133.5989, - 794.3998 - ], - [ - 957.3968, - 416.40027 - ] + 1153.9998, + 794.401 ], "input": { "id": "reg_addr_EX_reg", "field": "register_out" } - }, - { - "type": "Wire", - "id": "from instruction_split:rt_out to equals_operand_B_2:b_in", - "pos": [ - [ - 302.19995, - 165.9111 - ], - [ - 957.3968, - 436.40027 - ] - ], - "input": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", - "pos": [ - [ - 1490.0015, - 802.40173 - ], - [ - 1523.5994, - 802.3993 - ] - ], - "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", - "pos": [ - [ - 1483.6001, - -80.00018 - ], - [ - 1498.3997, - -80.0 - ] - ], - "input": { - "id": "control_MEM_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_2:alu_src_a to mux_source_a:select", - "pos": [ - [ - 1140.5334, - 40.699997 - ], - [ - 1242.4003, - 167.99994 - ] - ], - "input": { - "id": "control_unit_2", - "field": "alu_src_a" - } - }, - { - "type": "Wire", - "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", - "pos": [ - [ - 1207.7983, - 107.600006 - ], - [ - 1232.4003, - 187.99994 - ] - ], - "input": { - "id": "zero_extend_for_shamt", - "field": "zero_extend_out" - } - }, - { - "type": "Wire", - "id": "from operand_a_reg:register_out to mux_source_a:in1", - "pos": [ - [ - 1103.1989, - 216.00018 - ], - [ - 1232.4003, - 207.99994 - ] - ], - "input": { - "id": "operand_a_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from 0_a_inp:constant_out to mux_source_a:in2", - "pos": [ - [ - 596.00006, - 48.40001 - ], - [ - 1232.4003, - 227.99994 - ] - ], - "input": { - "id": "0_a_inp", - "field": "constant_out" - } - }, - { - "type": "Wire", - "id": "from mux_source_a:mux_out to alu:full_add_a_in", - "pos": [ - [ - 1262.4003, - 207.99994 - ], - [ - 1375.9999, - 184.40002 - ] - ], - "input": { - "id": "mux_source_a", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from mux_source_b:mux_out to alu:full_add_b_in", - "pos": [ - [ - 1264.8002, - 325.60004 - ], - [ - 1375.9999, - 244.40002 - ] - ], - "input": { - "id": "mux_source_b", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_2:alu_op to alu:full_add_op_in", - "pos": [ - [ - 1307.2001, - 40.699997 - ], - [ - 1385.9999, - 174.40002 - ] - ], - "input": { - "id": "control_unit_2", - "field": "alu_op" - } - }, - { - "type": "Wire", - "id": "from equals_operand_A_2:equals_out to operand_A_mux_2:select", - "pos": [ - [ - 986.59796, - 167.20001 - ], - [ - 955.6015, - 197.99994 - ] - ], - "input": { - "id": "equals_operand_A_2", - "field": "equals_out" - } - }, - { - "type": "Wire", - "id": "from operand_A_mux_1:mux_out to operand_A_mux_2:in0", - "pos": [ - [ - 819.6, - 225.60065 - ], - [ - 945.6015, - 217.99994 - ] - ], - "input": { - "id": "operand_A_mux_1", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from alu:alu_out to operand_A_mux_2:in1", - "pos": [ - [ - 1415.9999, - 214.40002 - ], - [ - 945.6015, - 237.99994 - ] - ], - "input": { - "id": "alu", - "field": "alu_out" - } - }, - { - "type": "Wire", - "id": "from equals_operand_B_2:equals_out to operand_B_mux_2:select", - "pos": [ - [ - 991.3968, - 426.40027 - ], - [ - 956.4005, - 295.60052 - ] - ], - "input": { - "id": "equals_operand_B_2", - "field": "equals_out" - } - }, - { - "type": "Wire", - "id": "from operand_B_mux_1:mux_out to operand_B_mux_2:in0", - "pos": [ - [ - 822.79956, - 323.99988 - ], - [ - 946.4005, - 315.60052 - ] - ], - "input": { - "id": "operand_B_mux_1", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from alu:alu_out to operand_B_mux_2:in1", - "pos": [ - [ - 1415.9999, - 214.40002 - ], - [ - 946.4005, - 335.60052 - ] - ], - "input": { - "id": "alu", - "field": "alu_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:op_out to branch:branch_op_in", - "pos": [ - [ - 302.19995, - 99.24443 - ], - [ - 1037.0, - 274.40002 - ] - ], - "input": { - "id": "instruction_split", - "field": "op_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rt_out to branch:branch_rt_in", - "pos": [ - [ - 302.19995, - 165.9111 - ], - [ - 1037.0, - 274.40002 - ] - ], - "input": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:funct_out to branch:branch_funct_in", - "pos": [ - [ - 302.19995, - 121.46665 - ], - [ - 1037.0, - 274.40002 - ] - ], - "input": { - "id": "instruction_split", - "field": "funct_out" - } - }, - { - "type": "Wire", - "id": "from operand_A_mux_2:mux_out to branch:branch_rs_value_id", - "pos": [ - [ - 975.6015, - 227.99994 - ], - [ - 1037.0, - 274.40002 - ] - ], - "input": { - "id": "operand_A_mux_2", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from operand_B_mux_2:mux_out to branch:branch_rt_value_id", - "pos": [ - [ - 976.4005, - 325.60052 - ], - [ - 1037.0, - 274.40002 - ] - ], - "input": { - "id": "operand_B_mux_2", - "field": "mux_out" - } - }, - { - "type": "Wire", - "id": "from branch:branch_out to mux_jump_merge:select", - "pos": [ - [ - 1037.0, - 274.40002 - ], - [ - -64.39996, - 330.40002 - ] - ], - "input": { - "id": "branch", - "field": "branch_out" - } - }, - { - "type": "Wire", - "id": "from pc_add_branch:add_out to mux_jump_merge:in0", - "pos": [ - [ - 440.0, - 440.0 - ], - [ - -74.39996, - 350.40002 - ] - ], - "input": { - "id": "pc_add_branch", - "field": "add_out" - } - }, - { - "type": "Wire", - "id": "from reg_file:rs_value_out to mux_jump_merge:in1", - "pos": [ - [ - 500.4, - 217.20001 - ], - [ - -74.39996, - 370.40002 - ] - ], - "input": { - "id": "reg_file", - "field": "rs_value_out" - } - }, - { - "type": "Wire", - "id": "from merge_reg:register_out to mux_jump_merge:in2", - "pos": [ - [ - 226.00024, - 582.40155 - ], - [ - -74.39996, - 390.40002 - ] - ], - "input": { - "id": "merge_reg", - "field": "register_out" - } - }, - { - "type": "Wire", - "id": "from pc+4:add_out to mux_jump_merge:in3", - "pos": [ - [ - 150.40002, - 380.8 - ], - [ - -74.39996, - 410.40002 - ] - ], - "input": { - "id": "pc+4", - "field": "add_out" - } } ] -} +} \ No newline at end of file From 98921311c347a859cd0e259a526ae1fd0c279cda Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Thu, 10 Oct 2024 10:23:45 +0200 Subject: [PATCH 11/18] Refactored some components names and id to be more precise --- mips-lib/examples/mips_pipe_example_1.rs | 54 +- mips-lib/mips_pipe.json | 3159 +++++++++++++---- ...ips_equals_load.rs => mips_alu_forward.rs} | 38 +- ...equals_forward.rs => mips_data_forward.rs} | 34 +- mips-lib/src/components/mod.rs | 8 +- ...ips_equals_load.rs => mips_alu_forward.rs} | 23 +- ...equals_forward.rs => mips_data_forward.rs} | 18 +- mips-lib/src/gui_egui/components/mod.rs | 4 +- 8 files changed, 2581 insertions(+), 757 deletions(-) rename mips-lib/src/components/{mips_equals_load.rs => mips_alu_forward.rs} (73%) rename mips-lib/src/components/{mips_equals_forward.rs => mips_data_forward.rs} (71%) rename mips-lib/src/gui_egui/components/{mips_equals_load.rs => mips_alu_forward.rs} (78%) rename mips-lib/src/gui_egui/components/{mips_equals_forward.rs => mips_data_forward.rs} (83%) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index b64cd1e..6464719 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -56,9 +56,9 @@ fn main() { (-54.0, 390.0), Input::new("branch", BRANCH_OUT_ID), vec![ - Input::new("pc_add_branch", ADD_OUT_ID), // describe origin - Input::new("operand_A_mux_2", MUX_OUT_ID), // goes to addr, RD2 - Input::new("merge_reg", REGISTER_OUT_ID), // + Input::new("pc_add_branch", ADD_OUT_ID), // describe origin + Input::new("alu_forward_A_mux", MUX_OUT_ID), // goes to addr, RD2 + Input::new("merge_reg", REGISTER_OUT_ID), // Input::new("pc+4", ADD_OUT_ID), ], ), @@ -144,13 +144,13 @@ fn main() { // // // Equal::rc_new( - // "equals_operand_A", + // "data_forward_A", // (3200.0, 1700.0), // Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), // Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), // ), - EqualForward::rc_new( - "equals_operand_A", + DataForward::rc_new( + "data_forward_A", (800.0, 160.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), @@ -158,9 +158,9 @@ fn main() { ), // Mux::rc_new( - "operand_A_mux_1", + "data_forward_A_mux", (800.0, 225.0), - Input::new("equals_operand_A", EQUAL_FORWARD_OUT_ID), + Input::new("data_forward_A", DATA_FORWARD_OUT_ID), vec![ Input::new("reg_file", reg_file_fields::RS_VALUE_OUT_ID), Input::new("write_back_mux", MUX_OUT_ID), @@ -169,13 +169,13 @@ fn main() { // // // Equal::rc_new( - // "equals_operand_B", + // "data_forward_B", // (3200.0, 2300.0), // Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), // Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), // ), - EqualForward::rc_new( - "equals_operand_B", + DataForward::rc_new( + "data_forward_B", (800.0, 425.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), @@ -183,9 +183,9 @@ fn main() { ), // Mux::rc_new( - "operand_B_mux_1", + "data_forward_B_mux", (800.0, 325.0), - Input::new("equals_operand_B", EQUAL_FORWARD_OUT_ID), + Input::new("data_forward_B", DATA_FORWARD_OUT_ID), vec![ Input::new("reg_file", reg_file_fields::RT_VALUE_OUT_ID), Input::new("write_back_mux", MUX_OUT_ID), @@ -194,13 +194,13 @@ fn main() { // // // Equal::rc_new( - // "equals_operand_A_2", + // "alu_forward_A", // (3300.0, 1700.0), // Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), // Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), // ), - EqualLoad::rc_new( - "equals_operand_A_2", + AluForward::rc_new( + "alu_forward_A", (970.0, 160.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), @@ -209,11 +209,11 @@ fn main() { ), // Mux::rc_new( - "operand_A_mux_2", + "alu_forward_A_mux", (970.0, 225.0), - Input::new("equals_operand_A_2", EQUAL_LOAD_OUT_ID), + Input::new("alu_forward_A", ALU_FORWARD_OUT_ID), vec![ - Input::new("operand_A_mux_1", MUX_OUT_ID), + Input::new("data_forward_A_mux", MUX_OUT_ID), Input::new("alu", FULL_ADD_OUT_ID), ], ), @@ -225,7 +225,7 @@ fn main() { // Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), // Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), // ), - EqualLoad::rc_new( + AluForward::rc_new( "equals_operand_B_2", (970.0, 425.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), @@ -235,11 +235,11 @@ fn main() { ), // Mux::rc_new( - "operand_B_mux_2", + "alu_forward_B_mux", (970.0, 325.0), - Input::new("equals_operand_B_2", EQUAL_LOAD_OUT_ID), + Input::new("equals_operand_B_2", ALU_FORWARD_OUT_ID), vec![ - Input::new("operand_B_mux_1", MUX_OUT_ID), + Input::new("data_forward_B_mux", MUX_OUT_ID), Input::new("alu", FULL_ADD_OUT_ID), ], ), @@ -251,8 +251,8 @@ fn main() { Input::new("instruction_split", INSTRUCTION_SPLITTER_OP_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_FUNCT_ID), - Input::new("operand_A_mux_2", MUX_OUT_ID), - Input::new("operand_B_mux_2", MUX_OUT_ID), + Input::new("alu_forward_A_mux", MUX_OUT_ID), + Input::new("alu_forward_B_mux", MUX_OUT_ID), ), // // @@ -278,14 +278,14 @@ fn main() { //TODO: fix after adding 4 muxes "operand_a_reg", (1100.0, 215.0), - Input::new("operand_A_mux_2", MUX_OUT_ID), + Input::new("alu_forward_A_mux", MUX_OUT_ID), ), // Register::rc_new( //TODO: fix after muxes "operand_b_reg", (1100.0, 325.0), - Input::new("operand_B_mux_2", MUX_OUT_ID), + Input::new("alu_forward_B_mux", MUX_OUT_ID), ), PassThrough::rc_new( "operand_b_pass", diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index 810c85f..dce6a04 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -1,119 +1,184 @@ { "store": [ { - "type": "Register", - "id": "mux_b2_reg", - "pos": [ - 1091.6001, - 547.2002 - ], - "r_in": { - "id": "pc+4_pass", - "field": "pass_through_out" - } - }, - { - "type": "Register", - "id": "mux_b3_reg", + "type": "PhysicalMem", + "id": "phys_mem", "pos": [ - 1101.1995, - 624.7999 - ], - "r_in": { - "id": "signzero_extend", - "field": "sz_out" - } + 0.0, + 0.0 + ] }, { "type": "Register", - "id": "reg_addr_EX_reg", + "id": "pc", "pos": [ - 1123.5989, - 794.3998 + 170.0, + 410.0 ], "r_in": { - "id": "mux_write_addr", + "id": "mux_jump_merge", "field": "mux_out" } }, { - "type": "Register", - "id": "control_WB_reg", + "type": "Constant", + "id": "+4", "pos": [ - 1918.4001, - -73.60004 + 80.0, + 380.0 ], - "r_in": { - "id": "control_MEM_pass", - "field": "pass_through_out" + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { - "type": "Register", - "id": "reg_addr_reg", + "type": "Add", + "id": "pc+4", "pos": [ - 1947.2009, - 799.2012 + 130.0, + 380.0 ], - "r_in": { - "id": "reg_addr_MEM_pass", - "field": "pass_through_out" - } + "a_in": { + "id": "pc", + "field": "register_out" + }, + "b_in": { + "id": "+4", + "field": "constant_out" + }, + "scale": 1.0 }, { - "type": "Register", - "id": "control_MEM_reg", + "type": "InstrMem", + "id": "instr_mem", "pos": [ - 1473.6001, - -80.00018 + 100.0, + 585.0 ], - "r_in": { - "id": "control_EX_pass", - "field": "pass_through_out" + "pc": { + "id": "pc", + "field": "register_out" + }, + "phys_mem_id": "phys_mem", + "regfile_id": "reg_file", + "mem_view": { + "visible": false, + "title": "instruction memory view", + "id": "instr_mem", + "row_offset": 0, + "max_rows": 1024, + "big_endian": true, + "format": "HexAndMips", + "show_settings": { + "symbols": true, + "sections": false, + "program_counter": false, + "registers": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + true + ] + }, + "register_values": null, + "dynamic_symbols": { + "PC_IM": [ + 0, + true + ] + }, + "break_points": [] } }, { - "type": "Register", - "id": "reg_addr_MEM_reg", + "type": "Mux", + "id": "mux_jump_merge", "pos": [ - 1480.0015, - 802.40173 + -54.0, + 390.0 ], - "r_in": { - "id": "reg_addr_EX_pass", - "field": "pass_through_out" - } - }, - { - "type": "Register", - "id": "alu_reg", - "pos": [ - 1470.4004, - 252.79993 + "select": { + "id": "branch", + "field": "branch_out" + }, + "m_in": [ + { + "id": "pc_add_branch", + "field": "add_out" + }, + { + "id": "alu_forward_A_mux", + "field": "mux_out" + }, + { + "id": "merge_reg", + "field": "register_out" + }, + { + "id": "pc+4", + "field": "add_out" + } ], - "r_in": { - "id": "alu", - "field": "alu_out" - } + "scale": 1.0 }, { - "type": "Register", - "id": "zero_extend_reg", + "type": "JumpMerge", + "id": "jump_merge", "pos": [ - 1098.0002, - 107.20001 + -62.0, + 500.0 ], - "r_in": { - "id": "instruction_split", - "field": "shamt_out" + "instr_addr_in": { + "id": "pc", + "field": "register_out" + }, + "jump_addr_in": { + "id": "instr_mem", + "field": "instruction" } }, { "type": "Register", "id": "pc+4_reg", "pos": [ - 201.59985, - 371.20197 + 200.0, + 370.0 ], "r_in": { "id": "pc+4", @@ -121,107 +186,95 @@ } }, { - "type": "Register", - "id": "InMem_reg", - "pos": [ - 208.7998, - 474.4015 - ], - "r_in": { - "id": "instr_mem", - "field": "instruction" - } - }, - { - "type": "Register", - "id": "operand_b_reg", + "type": "PassThrough", + "id": "pc+4_pass", "pos": [ - 1101.1985, - 324.80035 + 240.0, + 370.0 ], - "r_in": { - "id": "operand_B_mux_2", - "field": "mux_out" + "input": { + "id": "pc+4_reg", + "field": "register_out" } }, { "type": "Register", - "id": "result_reg_EX", + "id": "InMem_reg", "pos": [ - 1918.3983, - 268.79993 + 210.0, + 475.0 ], "r_in": { - "id": "write_back_mux", - "field": "mux_out" + "id": "instr_mem", + "field": "instruction" } }, { - "type": "Register", - "id": "data_MEM_reg", + "type": "PassThrough", + "id": "InMem_pass", "pos": [ - 1477.6, - 566.4001 + 250.0, + 475.0 ], - "r_in": { - "id": "operand_b_pass", - "field": "pass_through_out" + "input": { + "id": "InMem_reg", + "field": "register_out" } }, { "type": "Register", - "id": "pc", + "id": "merge_reg", "pos": [ - 79.60004, - 415.60004 + 215.0, + 580.0 ], "r_in": { - "id": "mux_jump_merge", - "field": "mux_out" + "id": "jump_merge", + "field": "merge_out" } }, { - "type": "Register", - "id": "merge_reg", + "type": "InstrSplit", + "id": "instruction_split", "pos": [ - 216.00024, - 582.40155 + 270.0, + 150.0 ], - "r_in": { - "id": "jump_merge", - "field": "merge_out" + "instruction_in": { + "id": "InMem_reg", + "field": "register_out" } }, { - "type": "Register", - "id": "control_EX_reg", + "type": "ControlUnit", + "id": "control_unit_1", "pos": [ - 918.7965, - -38.400085 + 260.0, + 0.0 ], - "r_in": { - "id": "InMem_pass", - "field": "pass_through_out" + "a_in": { + "id": "InMem_reg", + "field": "register_out" } }, { - "type": "Register", - "id": "operand_a_reg", + "type": "ControlUnit", + "id": "control_unit_2", "pos": [ - 1093.1989, - 216.00018 + 1200.0, + 0.0 ], - "r_in": { - "id": "operand_A_mux_2", - "field": "mux_out" + "a_in": { + "id": "control_EX_reg", + "field": "register_out" } }, { "type": "ControlUnit", "id": "control_unit_3", "pos": [ - 1667.2002, - 27.199997 + 1670.0, + 0.0 ], "a_in": { "id": "control_MEM_reg", @@ -229,86 +282,82 @@ } }, { - "type": "PassThrough", - "id": "reg_addr_MEM_pass", - "pos": [ - 1523.5994, - 802.3993 + "type": "ControlUnit", + "id": "control_unit_4", + "pos": [ + 2216.0, + 0.0 ], - "input": { - "id": "reg_addr_MEM_reg", + "a_in": { + "id": "control_WB_reg", "field": "register_out" } }, { - "type": "PhysicalMem", - "id": "phys_mem", - "pos": [ - 0.0, - 0.0 - ] - }, - { - "type": "Constant", - "id": "0_a_inp", + "type": "SignZeroExtend", + "id": "signzero_extend", "pos": [ - 596.00006, - 48.40001 + 310.0, + 410.0 ], - "value": { - "data": { - "Data": 4 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } + "signzero_signal_in": { + "id": "instruction_split", + "field": "immediate_out" + }, + "signzero_ctrl_in": { + "id": "control_unit_1", + "field": "extend_select" } }, { - "type": "ControlUnit", - "id": "control_unit_4", + "type": "DataForward", + "id": "data_forward_A", "pos": [ - 2216.0002, - 23.200073 + 800.0, + 160.0 ], "a_in": { - "id": "control_WB_reg", + "id": "reg_addr_MEM_reg", "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "we_in": { + "id": "control_unit_3", + "field": "reg_write_enable" } }, { - "type": "PassThrough", - "id": "pc+4_pass", + "type": "Mux", + "id": "data_forward_A_mux", "pos": [ - 235.60022, - 371.99823 + 800.0, + 225.0 ], - "input": { - "id": "pc+4_reg", - "field": "register_out" - } - }, - { - "type": "InstrSplit", - "id": "instruction_split", - "pos": [ - 271.19995, - 154.79999 + "select": { + "id": "data_forward_A", + "field": "data_forward_out" + }, + "m_in": [ + { + "id": "reg_file", + "field": "rs_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } ], - "instruction_in": { - "id": "InMem_reg", - "field": "register_out" - } + "scale": 1.0 }, { - "type": "Equal", - "id": "equals_operand_B", + "type": "DataForward", + "id": "data_forward_B", "pos": [ - 811.9999, - 426.39972 + 800.0, + 425.0 ], "a_in": { "id": "reg_addr_MEM_reg", @@ -317,30 +366,41 @@ "b_in": { "id": "instruction_split", "field": "rt_out" + }, + "we_in": { + "id": "control_unit_3", + "field": "reg_write_enable" } }, { - "type": "Equal", - "id": "equals_operand_B_2", + "type": "Mux", + "id": "data_forward_B_mux", "pos": [ - 974.3968, - 426.40027 + 800.0, + 325.0 ], - "a_in": { - "id": "reg_addr_EX_reg", - "field": "register_out" + "select": { + "id": "data_forward_B", + "field": "data_forward_out" }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - } + "m_in": [ + { + "id": "reg_file", + "field": "rt_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 }, { - "type": "Equal", - "id": "equals_operand_A_2", + "type": "AluForward", + "id": "alu_forward_A", "pos": [ - 969.59796, - 167.20001 + 970.0, + 160.0 ], "a_in": { "id": "reg_addr_EX_reg", @@ -349,261 +409,252 @@ "b_in": { "id": "instruction_split", "field": "rs_out" + }, + "we_in": { + "id": "control_unit_2", + "field": "reg_write_enable" + }, + "load_in": { + "id": "control_unit_2", + "field": "mem_mode" } }, { - "type": "PassThrough", - "id": "operand_b_pass", + "type": "Mux", + "id": "alu_forward_A_mux", "pos": [ - 1160.8, - 360.00006 + 970.0, + 225.0 ], - "input": { - "id": "operand_b_reg", - "field": "register_out" - } + "select": { + "id": "alu_forward_A", + "field": "equals_forward_out" + }, + "m_in": [ + { + "id": "data_forward_A_mux", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" + } + ], + "scale": 1.0 }, { - "type": "Equal", - "id": "equals_operand_A", + "type": "AluForward", + "id": "equals_operand_B_2", "pos": [ - 803.1997, - 163.99988 + 970.0, + 425.0 ], "a_in": { - "id": "reg_addr_MEM_reg", + "id": "reg_addr_EX_reg", "field": "register_out" }, "b_in": { "id": "instruction_split", - "field": "rs_out" + "field": "rt_out" + }, + "we_in": { + "id": "control_unit_2", + "field": "reg_write_enable" + }, + "load_in": { + "id": "control_unit_2", + "field": "mem_mode" } }, { - "type": "RegFile", - "id": "reg_file", + "type": "Mux", + "id": "alu_forward_B_mux", "pos": [ - 434.4, - 177.20001 + 970.0, + 325.0 ], - "rs_address_in": { + "select": { + "id": "equals_operand_B_2", + "field": "equals_forward_out" + }, + "m_in": [ + { + "id": "data_forward_B_mux", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" + } + ], + "scale": 1.0 + }, + { + "type": "BranchLogic", + "id": "branch", + "pos": [ + 1040.0, + 275.0 + ], + "op_in": { "id": "instruction_split", - "field": "rs_out" + "field": "op_out" }, - "rt_address_in": { + "rt_in": { "id": "instruction_split", "field": "rt_out" }, - "write_address_in": { - "id": "reg_addr_reg", - "field": "register_out" + "funct_in": { + "id": "instruction_split", + "field": "funct_out" }, - "write_data_in": { - "id": "result_reg_EX", - "field": "register_out" + "rs_value": { + "id": "alu_forward_A_mux", + "field": "mux_out" }, - "write_enable_in": { - "id": "control_unit_4", - "field": "reg_write_enable" + "rt_value": { + "id": "alu_forward_B_mux", + "field": "mux_out" } }, { - "type": "ControlUnit", - "id": "control_unit_1", + "type": "Register", + "id": "control_EX_reg", "pos": [ - 263.2, - 2.4000092 + 920.0, + -40.0 ], - "a_in": { - "id": "InMem_reg", + "r_in": { + "id": "InMem_pass", + "field": "pass_through_out" + } + }, + { + "type": "PassThrough", + "id": "control_EX_pass", + "pos": [ + 960.0, + -40.0 + ], + "input": { + "id": "control_EX_reg", "field": "register_out" } }, { - "type": "SignZeroExtend", - "id": "signzero_extend", + "type": "Register", + "id": "zero_extend_reg", "pos": [ - 310.0, - 410.0 + 1100.0, + 110.0 ], - "signzero_signal_in": { + "r_in": { "id": "instruction_split", - "field": "immediate_out" - }, - "signzero_ctrl_in": { - "id": "control_unit_1", - "field": "extend_select" + "field": "shamt_out" } }, { - "type": "ShiftConst", - "id": "branch_shift", + "type": "Register", + "id": "operand_a_reg", "pos": [ - 380.0, - 460.0 + 1100.0, + 215.0 ], - "signal_in": { - "id": "signzero_extend", - "field": "sz_out" - }, - "shift_by": 2 + "r_in": { + "id": "alu_forward_A_mux", + "field": "mux_out" + } }, { - "type": "Add", - "id": "pc_add_branch", + "type": "Register", + "id": "operand_b_reg", "pos": [ - 420.0, - 440.0 + 1100.0, + 325.0 ], - "a_in": { - "id": "pc+4_reg", - "field": "register_out" - }, - "b_in": { - "id": "branch_shift", - "field": "shift_left_const_out" - }, - "scale": 1.0 + "r_in": { + "id": "alu_forward_B_mux", + "field": "mux_out" + } }, { - "type": "InstrMem", - "id": "instr_mem", + "type": "PassThrough", + "id": "operand_b_pass", "pos": [ - 98.400024, - 585.6 + 1140.0, + 325.0 ], - "pc": { - "id": "pc", + "input": { + "id": "operand_b_reg", "field": "register_out" - }, - "phys_mem_id": "phys_mem", - "regfile_id": "reg_file", - "mem_view": { - "visible": false, - "title": "instruction memory view", - "id": "instr_mem", - "row_offset": 0, - "max_rows": 1024, - "big_endian": true, - "format": "HexAndMips", - "show_settings": { - "symbols": true, - "sections": false, - "program_counter": false, - "registers": [ - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - true - ] - }, - "register_values": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 2147483648, - 0, - 0 - ], - "dynamic_symbols": { - "PC_IM": [ - 0, - true - ] - }, - "break_points": [ - 224 - ] } }, { - "type": "JumpMerge", - "id": "jump_merge", + "type": "Register", + "id": "mux_b2_reg", "pos": [ - -62.200012, - 492.80005 + 1100.0, + 550.0 ], - "instr_addr_in": { - "id": "pc", - "field": "register_out" - }, - "jump_addr_in": { - "id": "instr_mem", - "field": "instruction" + "r_in": { + "id": "pc+4_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "mux_b3_reg", + "pos": [ + 1100.0, + 625.0 + ], + "r_in": { + "id": "signzero_extend", + "field": "sz_out" + } + }, + { + "type": "Register", + "id": "reg_addr_EX_reg", + "pos": [ + 1125.0, + 800.0 + ], + "r_in": { + "id": "mux_write_addr", + "field": "mux_out" } }, { "type": "PassThrough", - "id": "InMem_pass", + "id": "reg_addr_EX_pass", "pos": [ - 232.40002, - 474.8 + 1165.0, + 800.0 ], "input": { - "id": "InMem_reg", + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "ZeroExtend", + "id": "zero_extend_for_shamt", + "pos": [ + 1165.0, + 110.0 + ], + "signal_in": { + "id": "zero_extend_reg", "field": "register_out" } }, { "type": "Constant", - "id": "+4", + "id": "0_a_inp", "pos": [ - 78.80005, - 382.39996 + 600.0, + 50.0 ], "value": { "data": { @@ -617,12 +668,86 @@ } } }, + { + "type": "Mux", + "id": "mux_source_a", + "pos": [ + 1250.0, + 210.0 + ], + "select": { + "id": "control_unit_2", + "field": "alu_src_a" + }, + "m_in": [ + { + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" + }, + { + "id": "operand_a_reg", + "field": "register_out" + }, + { + "id": "0_a_inp", + "field": "constant_out" + } + ], + "scale": 1.0 + }, + { + "type": "Mux", + "id": "mux_source_b", + "pos": [ + 1250.0, + 325.0 + ], + "select": { + "id": "control_unit_2", + "field": "alu_src_b" + }, + "m_in": [ + { + "id": "operand_b_reg", + "field": "register_out" + }, + { + "id": "mux_b2_reg", + "field": "register_out" + }, + { + "id": "mux_b3_reg", + "field": "register_out" + } + ], + "scale": 1.0 + }, + { + "type": "ALU", + "id": "alu", + "pos": [ + 1400.0, + 220.0 + ], + "a_in": { + "id": "mux_source_a", + "field": "mux_out" + }, + "b_in": { + "id": "mux_source_b", + "field": "mux_out" + }, + "op_in": { + "id": "control_unit_2", + "field": "alu_op" + } + }, { "type": "DataMem", "id": "data_mem", "pos": [ - 1665.5996, - 560.8 + 1660.0, + 560.0 ], "address_input": { "id": "alu_reg", @@ -646,7 +771,7 @@ "visible": false, "title": "Data memory view", "id": "data_mem", - "row_offset": 512, + "row_offset": 0, "max_rows": 1024, "big_endian": true, "format": "ByteAndUtf8", @@ -689,57 +814,89 @@ false ] }, - "register_values": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 2147483648, - 0, - 0 - ], - "dynamic_symbols": { - "DM_ADRS": [ - 0, - false - ] - }, - "break_points": [ - 4172 - ] + "register_values": null, + "dynamic_symbols": {}, + "break_points": [] + } + }, + { + "type": "Register", + "id": "control_MEM_reg", + "pos": [ + 1470.0, + -40.0 + ], + "r_in": { + "id": "control_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "PassThrough", + "id": "control_MEM_pass", + "pos": [ + 1510.0, + -40.0 + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Register", + "id": "alu_reg", + "pos": [ + 1470.0, + 250.0 + ], + "r_in": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Register", + "id": "data_MEM_reg", + "pos": [ + 1470.0, + 565.0 + ], + "r_in": { + "id": "operand_b_pass", + "field": "pass_through_out" + } + }, + { + "type": "Register", + "id": "reg_addr_MEM_reg", + "pos": [ + 1480.0, + 800.0 + ], + "r_in": { + "id": "reg_addr_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "PassThrough", + "id": "reg_addr_MEM_pass", + "pos": [ + 1520.0, + 800.0 + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" } }, { "type": "Mux", "id": "write_back_mux", "pos": [ - 1681.5999, - 270.00012 + 1680.0, + 270.0 ], "select": { "id": "control_unit_3", @@ -758,119 +915,71 @@ "scale": 1.0 }, { - "type": "Mux", - "id": "operand_A_mux_1", + "type": "Register", + "id": "control_WB_reg", "pos": [ - 809.6, - 225.60065 + 1920.0, + -40.0 ], - "select": { - "id": "equals_operand_A", - "field": "equals_out" - }, - "m_in": [ - { - "id": "reg_file", - "field": "rs_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } - ], - "scale": 1.0 + "r_in": { + "id": "control_MEM_pass", + "field": "pass_through_out" + } }, { - "type": "Add", - "id": "pc+4", + "type": "Register", + "id": "result_reg_EX", "pos": [ - 130.40002, - 380.8 + 1920.0, + 270.0 ], - "a_in": { - "id": "pc", - "field": "register_out" - }, - "b_in": { - "id": "+4", - "field": "constant_out" - }, - "scale": 1.0 + "r_in": { + "id": "write_back_mux", + "field": "mux_out" + } }, { - "type": "ControlUnit", - "id": "control_unit_2", + "type": "Register", + "id": "reg_addr_reg", "pos": [ - 1207.2001, - 27.199997 + 1920.0, + 800.0 ], - "a_in": { - "id": "control_EX_reg", - "field": "register_out" + "r_in": { + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" } }, { - "type": "Mux", - "id": "mux_source_b", + "type": "ShiftConst", + "id": "branch_shift", "pos": [ - 1254.8002, - 325.60004 + 380.0, + 460.0 ], - "select": { - "id": "control_unit_2", - "field": "alu_src_b" + "signal_in": { + "id": "signzero_extend", + "field": "sz_out" }, - "m_in": [ - { - "id": "operand_b_reg", - "field": "register_out" - }, - { - "id": "mux_b2_reg", - "field": "register_out" - }, - { - "id": "mux_b3_reg", - "field": "register_out" - } - ], - "scale": 1.0 + "shift_by": 2 }, { - "type": "Mux", - "id": "operand_B_mux_1", + "type": "Add", + "id": "pc_add_branch", "pos": [ - 812.79956, - 323.99988 + 420.0, + 440.0 ], - "select": { - "id": "equals_operand_B", - "field": "equals_out" + "a_in": { + "id": "pc+4_reg", + "field": "register_out" + }, + "b_in": { + "id": "branch_shift", + "field": "shift_left_const_out" }, - "m_in": [ - { - "id": "reg_file", - "field": "rt_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } - ], "scale": 1.0 }, - { - "type": "PassThrough", - "id": "control_MEM_pass", - "pos": [ - 1498.3997, - -80.0 - ], - "input": { - "id": "control_MEM_reg", - "field": "register_out" - } - }, { "type": "Constant", "id": "0x_1F", @@ -918,192 +1027,1904 @@ "scale": 1.0 }, { - "type": "ZeroExtend", - "id": "zero_extend_for_shamt", + "type": "RegFile", + "id": "reg_file", "pos": [ - 1166.7983, - 107.600006 + 435.0, + 180.0 ], - "signal_in": { - "id": "zero_extend_reg", + "rs_address_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "rt_address_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "write_address_in": { + "id": "reg_addr_reg", + "field": "register_out" + }, + "write_data_in": { + "id": "result_reg_EX", "field": "register_out" + }, + "write_enable_in": { + "id": "control_unit_4", + "field": "reg_write_enable" } }, { - "type": "Mux", - "id": "mux_source_a", + "type": "Wire", + "id": "from mux_jump_merge:mux_out to pc:r_in", "pos": [ - 1252.4003, - 207.99994 - ], - "select": { - "id": "control_unit_2", - "field": "alu_src_a" - }, - "m_in": [ - { - "id": "zero_extend_for_shamt", - "field": "zero_extend_out" - }, - { - "id": "operand_a_reg", - "field": "register_out" - }, - { - "id": "0_a_inp", - "field": "constant_out" - } + [ + -44.0, + 390.0 + ], + [ + 160.0, + 410.0 + ] ], - "scale": 1.0 + "input": { + "id": "mux_jump_merge", + "field": "mux_out" + } }, { - "type": "ALU", - "id": "alu", + "type": "Wire", + "id": "from pc:register_out to pc+4:a_in", "pos": [ - 1395.9999, - 214.40002 + [ + 180.0, + 410.0 + ], + [ + 110.0, + 360.0 + ] ], - "a_in": { - "id": "mux_source_a", - "field": "mux_out" - }, - "b_in": { - "id": "mux_source_b", - "field": "mux_out" - }, - "op_in": { - "id": "control_unit_2", - "field": "alu_op" + "input": { + "id": "pc", + "field": "register_out" } }, { - "type": "Mux", - "id": "operand_A_mux_2", + "type": "Wire", + "id": "from +4:constant_out to pc+4:b_in", "pos": [ - 965.6015, - 227.99994 - ], - "select": { - "id": "equals_operand_A_2", - "field": "equals_out" - }, - "m_in": [ - { - "id": "operand_A_mux_1", - "field": "mux_out" - }, - { - "id": "alu", - "field": "alu_out" - } + [ + 80.0, + 380.0 + ], + [ + 110.0, + 400.0 + ] ], - "scale": 1.0 + "input": { + "id": "+4", + "field": "constant_out" + } }, { - "type": "PassThrough", - "id": "control_EX_pass", + "type": "Wire", + "id": "from pc:register_out to instr_mem:pc", "pos": [ - 944.7983, - -39.19998 + [ + 180.0, + 410.0 + ], + [ + 60.0, + 551.5 + ] ], "input": { - "id": "control_EX_reg", + "id": "pc", "field": "register_out" } }, { - "type": "Mux", - "id": "operand_B_mux_2", + "type": "Wire", + "id": "from branch:branch_out to mux_jump_merge:select", "pos": [ - 966.4005, - 325.60052 + [ + 1040.0, + 275.0 + ], + [ + -64.0, + 340.0 + ] ], - "select": { - "id": "equals_operand_B_2", - "field": "equals_out" - }, - "m_in": [ - { - "id": "operand_B_mux_1", - "field": "mux_out" - }, - { - "id": "alu", - "field": "alu_out" - } + "input": { + "id": "branch", + "field": "branch_out" + } + }, + { + "type": "Wire", + "id": "from pc_add_branch:add_out to mux_jump_merge:in0", + "pos": [ + [ + 440.0, + 440.0 + ], + [ + -74.0, + 360.0 + ] ], - "scale": 1.0 + "input": { + "id": "pc_add_branch", + "field": "add_out" + } }, { - "type": "BranchLogic", - "id": "branch", + "type": "Wire", + "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", "pos": [ - 1037.0, - 274.40002 + [ + 980.0, + 225.0 + ], + [ + -74.0, + 380.0 + ] ], - "op_in": { - "id": "instruction_split", - "field": "op_out" - }, - "rt_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "funct_in": { - "id": "instruction_split", - "field": "funct_out" - }, - "rs_value": { - "id": "operand_A_mux_2", - "field": "mux_out" - }, - "rt_value": { - "id": "operand_B_mux_2", + "input": { + "id": "alu_forward_A_mux", "field": "mux_out" } }, { - "type": "Mux", - "id": "mux_jump_merge", + "type": "Wire", + "id": "from merge_reg:register_out to mux_jump_merge:in2", "pos": [ - -54.399963, - 380.40002 + [ + 225.0, + 580.0 + ], + [ + -74.0, + 400.0 + ] ], - "select": { - "id": "branch", - "field": "branch_out" - }, - "m_in": [ - { - "id": "pc_add_branch", - "field": "add_out" - }, - { - "id": "reg_file", - "field": "rs_value_out" - }, - { - "id": "merge_reg", - "field": "register_out" - }, - { - "id": "pc+4", - "field": "add_out" - } + "input": { + "id": "merge_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from pc+4:add_out to mux_jump_merge:in3", + "pos": [ + [ + 150.0, + 380.0 + ], + [ + -74.0, + 420.0 + ] + ], + "input": { + "id": "pc+4", + "field": "add_out" + } + }, + { + "type": "Wire", + "id": "from pc:register_out to jump_merge:merge_instr_addr_in", + "pos": [ + [ + 180.0, + 410.0 + ], + [ + -62.0, + 500.0 + ] + ], + "input": { + "id": "pc", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", + "pos": [ + [ + 140.0, + 551.5 + ], + [ + -62.0, + 500.0 + ] + ], + "input": { + "id": "instr_mem", + "field": "instruction" + } + }, + { + "type": "Wire", + "id": "from pc+4:add_out to pc+4_reg:r_in", + "pos": [ + [ + 150.0, + 380.0 + ], + [ + 190.0, + 370.0 + ] + ], + "input": { + "id": "pc+4", + "field": "add_out" + } + }, + { + "type": "Wire", + "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", + "pos": [ + [ + 210.0, + 370.0 + ], + [ + 240.0, + 370.0 + ] + ], + "input": { + "id": "pc+4_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instr_mem:instruction to InMem_reg:r_in", + "pos": [ + [ + 140.0, + 551.5 + ], + [ + 200.0, + 475.0 + ] + ], + "input": { + "id": "instr_mem", + "field": "instruction" + } + }, + { + "type": "Wire", + "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", + "pos": [ + [ + 220.0, + 475.0 + ], + [ + 250.0, + 475.0 + ] + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from jump_merge:merge_out to merge_reg:r_in", + "pos": [ + [ + -62.0, + 500.0 + ], + [ + 205.0, + 580.0 + ] + ], + "input": { + "id": "jump_merge", + "field": "merge_out" + } + }, + { + "type": "Wire", + "id": "from InMem_reg:register_out to instruction_split:instruction_in", + "pos": [ + [ + 220.0, + 475.0 + ], + [ + 239.0, + 150.0 + ] + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", + "pos": [ + [ + 220.0, + 475.0 + ], + [ + 54.0, + 0.0 + ] + ], + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", + "pos": [ + [ + 930.0, + -40.0 + ], + [ + 994.0, + 0.0 + ] + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", + "pos": [ + [ + 1480.0, + -40.0 + ], + [ + 1464.0, + 0.0 + ] + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", + "pos": [ + [ + 1930.0, + -40.0 + ], + [ + 2010.0, + 0.0 + ] + ], + "input": { + "id": "control_WB_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", + "pos": [ + [ + 301.0, + 183.33333 + ], + [ + 251.5, + 410.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "immediate_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", + "pos": [ + [ + 93.33333, + 13.5 + ], + [ + 310.0, + 389.0 + ] + ], + "input": { + "id": "control_unit_1", + "field": "extend_select" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", + "pos": [ + [ + 1490.0, + 800.0 + ], + [ + 783.0, + 150.0 + ] + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rs_out to data_forward_A:b_in", + "pos": [ + [ + 301.0, + 138.88889 + ], + [ + 783.0, + 170.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", + "pos": [ + [ + 1836.6666, + 13.5 + ], + [ + 783.0, + 160.0 + ] + ], + "input": { + "id": "control_unit_3", + "field": "reg_write_enable" + } + }, + { + "type": "Wire", + "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", + "pos": [ + [ + 817.0, + 160.0 + ], + [ + 790.0, + 195.0 + ] + ], + "input": { + "id": "data_forward_A", + "field": "data_forward_out" + } + }, + { + "type": "Wire", + "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", + "pos": [ + [ + 501.0, + 220.0 + ], + [ + 780.0, + 215.0 + ] + ], + "input": { + "id": "reg_file", + "field": "rs_value_out" + } + }, + { + "type": "Wire", + "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", + "pos": [ + [ + 1690.0, + 270.0 + ], + [ + 780.0, + 235.0 + ] + ], + "input": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", + "pos": [ + [ + 1490.0, + 800.0 + ], + [ + 783.0, + 415.0 + ] + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to data_forward_B:b_in", + "pos": [ + [ + 301.0, + 161.11111 + ], + [ + 783.0, + 435.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", + "pos": [ + [ + 1836.6666, + 13.5 + ], + [ + 783.0, + 425.0 + ] + ], + "input": { + "id": "control_unit_3", + "field": "reg_write_enable" + } + }, + { + "type": "Wire", + "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", + "pos": [ + [ + 817.0, + 425.0 + ], + [ + 790.0, + 295.0 + ] + ], + "input": { + "id": "data_forward_B", + "field": "data_forward_out" + } + }, + { + "type": "Wire", + "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", + "pos": [ + [ + 501.0, + 140.0 + ], + [ + 780.0, + 315.0 + ] + ], + "input": { + "id": "reg_file", + "field": "rt_value_out" + } + }, + { + "type": "Wire", + "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", + "pos": [ + [ + 1690.0, + 270.0 + ], + [ + 780.0, + 335.0 + ] + ], + "input": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", + "pos": [ + [ + 1135.0, + 800.0 + ], + [ + 953.0, + 150.0 + ] + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rs_out to alu_forward_A:b_in", + "pos": [ + [ + 301.0, + 138.88889 + ], + [ + 953.0, + 170.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", + "pos": [ + [ + 1366.6666, + 13.5 + ], + [ + 953.0, + 162.5 + ] + ], + "input": { + "id": "control_unit_2", + "field": "reg_write_enable" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", + "pos": [ + [ + 1233.3334, + 13.5 + ], + [ + 953.0, + 167.5 + ] + ], + "input": { + "id": "control_unit_2", + "field": "mem_mode" + } + }, + { + "type": "Wire", + "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", + "pos": [ + [ + 987.0, + 160.0 + ], + [ + 960.0, + 195.0 + ] + ], + "input": { + "id": "alu_forward_A", + "field": "equals_forward_out" + } + }, + { + "type": "Wire", + "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", + "pos": [ + [ + 810.0, + 225.0 + ], + [ + 950.0, + 215.0 + ] + ], + "input": { + "id": "data_forward_A_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu:alu_out to alu_forward_A_mux:in1", + "pos": [ + [ + 1420.0, + 220.0 + ], + [ + 950.0, + 235.0 + ] + ], + "input": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to equals_operand_B_2:a_in", + "pos": [ + [ + 1135.0, + 800.0 + ], + [ + 953.0, + 415.0 + ] + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to equals_operand_B_2:b_in", + "pos": [ + [ + 301.0, + 161.11111 + ], + [ + 953.0, + 435.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:reg_write_enable to equals_operand_B_2:we_in", + "pos": [ + [ + 1366.6666, + 13.5 + ], + [ + 953.0, + 427.5 + ] + ], + "input": { + "id": "control_unit_2", + "field": "reg_write_enable" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:mem_mode to equals_operand_B_2:load_in", + "pos": [ + [ + 1233.3334, + 13.5 + ], + [ + 953.0, + 432.5 + ] + ], + "input": { + "id": "control_unit_2", + "field": "mem_mode" + } + }, + { + "type": "Wire", + "id": "from equals_operand_B_2:equals_forward_out to alu_forward_B_mux:select", + "pos": [ + [ + 987.0, + 425.0 + ], + [ + 960.0, + 295.0 + ] + ], + "input": { + "id": "equals_operand_B_2", + "field": "equals_forward_out" + } + }, + { + "type": "Wire", + "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", + "pos": [ + [ + 810.0, + 325.0 + ], + [ + 950.0, + 315.0 + ] + ], + "input": { + "id": "data_forward_B_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu:alu_out to alu_forward_B_mux:in1", + "pos": [ + [ + 1420.0, + 220.0 + ], + [ + 950.0, + 335.0 + ] + ], + "input": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:op_out to branch:branch_op_in", + "pos": [ + [ + 301.0, + 94.44444 + ], + [ + 1040.0, + 275.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "op_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to branch:branch_rt_in", + "pos": [ + [ + 301.0, + 161.11111 + ], + [ + 1040.0, + 275.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:funct_out to branch:branch_funct_in", + "pos": [ + [ + 301.0, + 116.666664 + ], + [ + 1040.0, + 275.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "funct_out" + } + }, + { + "type": "Wire", + "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", + "pos": [ + [ + 980.0, + 225.0 + ], + [ + 1040.0, + 275.0 + ] + ], + "input": { + "id": "alu_forward_A_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", + "pos": [ + [ + 980.0, + 325.0 + ], + [ + 1040.0, + 275.0 + ] + ], + "input": { + "id": "alu_forward_B_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", + "pos": [ + [ + 250.0, + 475.0 + ], + [ + 910.0, + -40.0 + ] + ], + "input": { + "id": "InMem_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", + "pos": [ + [ + 930.0, + -40.0 + ], + [ + 960.0, + -40.0 + ] + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", + "pos": [ + [ + 301.0, + 72.22222 + ], + [ + 1090.0, + 110.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "shamt_out" + } + }, + { + "type": "Wire", + "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", + "pos": [ + [ + 980.0, + 225.0 + ], + [ + 1090.0, + 215.0 + ] + ], + "input": { + "id": "alu_forward_A_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", + "pos": [ + [ + 980.0, + 325.0 + ], + [ + 1090.0, + 325.0 + ] + ], + "input": { + "id": "alu_forward_B_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", + "pos": [ + [ + 1110.0, + 325.0 + ], + [ + 1140.0, + 325.0 + ] + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", + "pos": [ + [ + 240.0, + 370.0 + ], + [ + 1090.0, + 550.0 + ] + ], + "input": { + "id": "pc+4_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", + "pos": [ + [ + 368.5, + 410.0 + ], + [ + 1090.0, + 625.0 + ] + ], + "input": { + "id": "signzero_extend", + "field": "sz_out" + } + }, + { + "type": "Wire", + "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", + "pos": [ + [ + 570.0, + 500.0 + ], + [ + 1115.0, + 800.0 + ] + ], + "input": { + "id": "mux_write_addr", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", + "pos": [ + [ + 1135.0, + 800.0 + ], + [ + 1165.0, + 800.0 + ] + ], + "input": { + "id": "reg_addr_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", + "pos": [ + [ + 1110.0, + 110.0 + ], + [ + 1124.0, + 110.0 + ] + ], + "input": { + "id": "zero_extend_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:alu_src_a to mux_source_a:select", + "pos": [ + [ + 1133.3334, + 13.5 + ], + [ + 1240.0, + 170.0 + ] + ], + "input": { + "id": "control_unit_2", + "field": "alu_src_a" + } + }, + { + "type": "Wire", + "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", + "pos": [ + [ + 1206.0, + 110.0 + ], + [ + 1230.0, + 190.0 + ] + ], + "input": { + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" + } + }, + { + "type": "Wire", + "id": "from operand_a_reg:register_out to mux_source_a:in1", + "pos": [ + [ + 1110.0, + 215.0 + ], + [ + 1230.0, + 210.0 + ] + ], + "input": { + "id": "operand_a_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from 0_a_inp:constant_out to mux_source_a:in2", + "pos": [ + [ + 600.0, + 50.0 + ], + [ + 1230.0, + 230.0 + ] + ], + "input": { + "id": "0_a_inp", + "field": "constant_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:alu_src_b to mux_source_b:select", + "pos": [ + [ + 1166.6666, + 13.5 + ], + [ + 1240.0, + 285.0 + ] + ], + "input": { + "id": "control_unit_2", + "field": "alu_src_b" + } + }, + { + "type": "Wire", + "id": "from operand_b_reg:register_out to mux_source_b:in0", + "pos": [ + [ + 1110.0, + 325.0 + ], + [ + 1230.0, + 305.0 + ] + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from mux_b2_reg:register_out to mux_source_b:in1", + "pos": [ + [ + 1110.0, + 550.0 + ], + [ + 1230.0, + 325.0 + ] + ], + "input": { + "id": "mux_b2_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from mux_b3_reg:register_out to mux_source_b:in2", + "pos": [ + [ + 1110.0, + 625.0 + ], + [ + 1230.0, + 345.0 + ] + ], + "input": { + "id": "mux_b3_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from mux_source_a:mux_out to alu:full_add_a_in", + "pos": [ + [ + 1260.0, + 210.0 + ], + [ + 1380.0, + 190.0 + ] + ], + "input": { + "id": "mux_source_a", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from mux_source_b:mux_out to alu:full_add_b_in", + "pos": [ + [ + 1260.0, + 325.0 + ], + [ + 1380.0, + 250.0 + ] + ], + "input": { + "id": "mux_source_b", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_2:alu_op to alu:full_add_op_in", + "pos": [ + [ + 1300.0, + 13.5 + ], + [ + 1390.0, + 180.0 + ] + ], + "input": { + "id": "control_unit_2", + "field": "alu_op" + } + }, + { + "type": "Wire", + "id": "from alu_reg:register_out to data_mem:data_mem_address_in", + "pos": [ + [ + 1480.0, + 250.0 + ], + [ + 1630.0, + 526.5 + ] + ], + "input": { + "id": "alu_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", + "pos": [ + [ + 1703.3334, + 13.5 + ], + [ + 1690.0, + 526.5 + ] + ], + "input": { + "id": "control_unit_3", + "field": "mem_mode" + } + }, + { + "type": "Wire", + "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", + "pos": [ + [ + 1480.0, + 565.0 + ], + [ + 1594.0, + 560.0 + ] ], - "scale": 1.0 + "input": { + "id": "data_MEM_reg", + "field": "register_out" + } }, { - "type": "PassThrough", - "id": "reg_addr_EX_pass", + "type": "Wire", + "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", + "pos": [ + [ + 1670.0, + 13.5 + ], + [ + 1660.0, + 526.5 + ] + ], + "input": { + "id": "control_unit_3", + "field": "mem_write_enable" + } + }, + { + "type": "Wire", + "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", "pos": [ - 1153.9998, - 794.401 + [ + 960.0, + -40.0 + ], + [ + 1460.0, + -40.0 + ] ], "input": { - "id": "reg_addr_EX_reg", + "id": "control_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", + "pos": [ + [ + 1480.0, + -40.0 + ], + [ + 1510.0, + -40.0 + ] + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from alu:alu_out to alu_reg:r_in", + "pos": [ + [ + 1420.0, + 220.0 + ], + [ + 1460.0, + 250.0 + ] + ], + "input": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Wire", + "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", + "pos": [ + [ + 1140.0, + 325.0 + ], + [ + 1460.0, + 565.0 + ] + ], + "input": { + "id": "operand_b_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", + "pos": [ + [ + 1165.0, + 800.0 + ], + [ + 1470.0, + 800.0 + ] + ], + "input": { + "id": "reg_addr_EX_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", + "pos": [ + [ + 1490.0, + 800.0 + ], + [ + 1520.0, + 800.0 + ] + ], + "input": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_3:reg_write_src to write_back_mux:select", + "pos": [ + [ + 1803.3334, + 13.5 + ], + [ + 1670.0, + 240.0 + ] + ], + "input": { + "id": "control_unit_3", + "field": "reg_write_src" + } + }, + { + "type": "Wire", + "id": "from alu_reg:register_out to write_back_mux:in0", + "pos": [ + [ + 1480.0, + 250.0 + ], + [ + 1660.0, + 260.0 + ] + ], + "input": { + "id": "alu_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from data_mem:data_out to write_back_mux:in1", + "pos": [ + [ + 1726.0, + 560.0 + ], + [ + 1660.0, + 280.0 + ] + ], + "input": { + "id": "data_mem", + "field": "data_out" + } + }, + { + "type": "Wire", + "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", + "pos": [ + [ + 1510.0, + -40.0 + ], + [ + 1910.0, + -40.0 + ] + ], + "input": { + "id": "control_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from write_back_mux:mux_out to result_reg_EX:r_in", + "pos": [ + [ + 1690.0, + 270.0 + ], + [ + 1910.0, + 270.0 + ] + ], + "input": { + "id": "write_back_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", + "pos": [ + [ + 1520.0, + 800.0 + ], + [ + 1910.0, + 800.0 + ] + ], + "input": { + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Wire", + "id": "from signzero_extend:sz_out to branch_shift:shift_in", + "pos": [ + [ + 368.5, + 410.0 + ], + [ + 346.5, + 460.0 + ] + ], + "input": { + "id": "signzero_extend", + "field": "sz_out" + } + }, + { + "type": "Wire", + "id": "from pc+4_reg:register_out to pc_add_branch:a_in", + "pos": [ + [ + 210.0, + 370.0 + ], + [ + 400.0, + 420.0 + ] + ], + "input": { + "id": "pc+4_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", + "pos": [ + [ + 413.5, + 460.0 + ], + [ + 400.0, + 460.0 + ] + ], + "input": { + "id": "branch_shift", + "field": "shift_left_const_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_1:reg_dest to mux_write_addr:select", + "pos": [ + [ + 160.0, + 13.5 + ], + [ + 550.0, + 460.0 + ] + ], + "input": { + "id": "control_unit_1", + "field": "reg_dest" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to mux_write_addr:in0", + "pos": [ + [ + 301.0, + 161.11111 + ], + [ + 540.0, + 480.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rd_out to mux_write_addr:in1", + "pos": [ + [ + 301.0, + 205.55556 + ], + [ + 540.0, + 500.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rd_out" + } + }, + { + "type": "Wire", + "id": "from 0x_1F:constant_out to mux_write_addr:in2", + "pos": [ + [ + 500.0, + 510.0 + ], + [ + 540.0, + 520.0 + ] + ], + "input": { + "id": "0x_1F", + "field": "constant_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rs_out to reg_file:rs_address_in", + "pos": [ + [ + 301.0, + 138.88889 + ], + [ + 435.0, + 49.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rs_out" + } + }, + { + "type": "Wire", + "id": "from instruction_split:rt_out to reg_file:rt_address_in", + "pos": [ + [ + 301.0, + 161.11111 + ], + [ + 435.0, + 311.0 + ] + ], + "input": { + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "Wire", + "id": "from reg_addr_reg:register_out to reg_file:write_address_in", + "pos": [ + [ + 1930.0, + 800.0 + ], + [ + 369.0, + 270.0 + ] + ], + "input": { + "id": "reg_addr_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from result_reg_EX:register_out to reg_file:write_data_in", + "pos": [ + [ + 1930.0, + 270.0 + ], + [ + 369.0, + 290.0 + ] + ], + "input": { + "id": "result_reg_EX", "field": "register_out" } + }, + { + "type": "Wire", + "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", + "pos": [ + [ + 2382.6667, + 13.5 + ], + [ + 369.0, + 250.0 + ] + ], + "input": { + "id": "control_unit_4", + "field": "reg_write_enable" + } } ] -} \ No newline at end of file +} diff --git a/mips-lib/src/components/mips_equals_load.rs b/mips-lib/src/components/mips_alu_forward.rs similarity index 73% rename from mips-lib/src/components/mips_equals_load.rs rename to mips-lib/src/components/mips_alu_forward.rs index 9aba547..2c2a354 100644 --- a/mips-lib/src/components/mips_equals_load.rs +++ b/mips-lib/src/components/mips_alu_forward.rs @@ -8,15 +8,15 @@ use syncrim::common::{ use super::data_op::NO_OP; -pub const EQUAL_LOAD_A_IN_ID: &str = "a_in"; -pub const EQUAL_LOAD_B_IN_ID: &str = "b_in"; -pub const EQUAL_LOAD_WE_IN_ID: &str = "we_in"; -pub const EQUAL_LOAD_LOAD_IN_ID: &str = "load_in"; +pub const ALU_FORWARD_A_IN_ID: &str = "a_in"; +pub const ALU_FORWARD_B_IN_ID: &str = "b_in"; +pub const ALU_FORWARD_WE_IN_ID: &str = "we_in"; +pub const ALU_FORWARD_LOAD_IN_ID: &str = "load_in"; -pub const EQUAL_LOAD_OUT_ID: &str = "equals_forward_out"; +pub const ALU_FORWARD_OUT_ID: &str = "equals_forward_out"; #[derive(Serialize, Deserialize, Clone)] -pub struct EqualLoad { +pub struct AluForward { pub(crate) id: Id, pub(crate) pos: (f32, f32), pub(crate) a_in: Input, @@ -26,9 +26,9 @@ pub struct EqualLoad { } #[typetag::serde] -impl Component for EqualLoad { +impl Component for AluForward { fn to_(&self) { - trace!("EqualLoad"); + trace!("AluForward"); } fn get_id_ports(&self) -> (Id, Ports) { @@ -37,24 +37,24 @@ impl Component for EqualLoad { Ports::new( vec![ &InputPort { - port_id: EQUAL_LOAD_A_IN_ID.to_string(), + port_id: ALU_FORWARD_A_IN_ID.to_string(), input: self.a_in.clone(), }, &InputPort { - port_id: EQUAL_LOAD_B_IN_ID.to_string(), + port_id: ALU_FORWARD_B_IN_ID.to_string(), input: self.b_in.clone(), }, &InputPort { - port_id: EQUAL_LOAD_WE_IN_ID.to_string(), + port_id: ALU_FORWARD_WE_IN_ID.to_string(), input: self.we_in.clone(), }, &InputPort { - port_id: EQUAL_LOAD_LOAD_IN_ID.to_string(), + port_id: ALU_FORWARD_LOAD_IN_ID.to_string(), input: self.load_in.clone(), }, ], OutputType::Combinatorial, - vec![EQUAL_LOAD_OUT_ID], + vec![ALU_FORWARD_OUT_ID], ), ) } @@ -78,14 +78,14 @@ impl Component for EqualLoad { result = 0; } - simulator.set_out_value(&self.id, EQUAL_LOAD_OUT_ID, SignalValue::Data(result)); + simulator.set_out_value(&self.id, ALU_FORWARD_OUT_ID, SignalValue::Data(result)); Ok(()) } fn set_id_port(&mut self, target_port_id: Id, new_input: Input) { match target_port_id.as_str() { - EQUAL_LOAD_A_IN_ID => self.a_in = new_input, - EQUAL_LOAD_B_IN_ID => self.b_in = new_input, + ALU_FORWARD_A_IN_ID => self.a_in = new_input, + ALU_FORWARD_B_IN_ID => self.b_in = new_input, _ => (), } } @@ -95,7 +95,7 @@ impl Component for EqualLoad { } } -impl EqualLoad { +impl AluForward { pub fn new( id: &str, pos: (f32, f32), @@ -104,7 +104,7 @@ impl EqualLoad { we_in: Input, load_in: Input, ) -> Self { - EqualLoad { + AluForward { id: id.to_string(), pos, a_in, @@ -122,6 +122,6 @@ impl EqualLoad { we_in: Input, load_in: Input, ) -> Rc { - Rc::new(EqualLoad::new(id, pos, a_in, b_in, we_in, load_in)) + Rc::new(AluForward::new(id, pos, a_in, b_in, we_in, load_in)) } } diff --git a/mips-lib/src/components/mips_equals_forward.rs b/mips-lib/src/components/mips_data_forward.rs similarity index 71% rename from mips-lib/src/components/mips_equals_forward.rs rename to mips-lib/src/components/mips_data_forward.rs index b55f2e7..eb02061 100644 --- a/mips-lib/src/components/mips_equals_forward.rs +++ b/mips-lib/src/components/mips_data_forward.rs @@ -6,14 +6,14 @@ use std::rc::Rc; use syncrim::common::{ Component, Condition, Id, Input, InputPort, OutputType, Ports, SignalValue, Simulator, }; -pub const EQUAL_FORWARD_A_IN_ID: &str = "a_in"; -pub const EQUAL_FORWARD_B_IN_ID: &str = "b_in"; -pub const EQUAL_FORWARD_WE_IN_ID: &str = "we_in"; +pub const DATA_FORWARD_A_IN_ID: &str = "a_in"; +pub const DATA_FORWARD_B_IN_ID: &str = "b_in"; +pub const DATA_FORWARD_WE_IN_ID: &str = "we_in"; -pub const EQUAL_FORWARD_OUT_ID: &str = "equals_forward_out"; +pub const DATA_FORWARD_OUT_ID: &str = "data_forward_out"; #[derive(Serialize, Deserialize, Clone)] -pub struct EqualForward { +pub struct DataForward { pub(crate) id: Id, pub(crate) pos: (f32, f32), pub(crate) a_in: Input, @@ -22,9 +22,9 @@ pub struct EqualForward { } #[typetag::serde] -impl Component for EqualForward { +impl Component for DataForward { fn to_(&self) { - trace!("EqualForward"); + trace!("AluFroward"); } fn get_id_ports(&self) -> (Id, Ports) { @@ -33,20 +33,20 @@ impl Component for EqualForward { Ports::new( vec![ &InputPort { - port_id: EQUAL_FORWARD_A_IN_ID.to_string(), + port_id: DATA_FORWARD_A_IN_ID.to_string(), input: self.a_in.clone(), }, &InputPort { - port_id: EQUAL_FORWARD_B_IN_ID.to_string(), + port_id: DATA_FORWARD_B_IN_ID.to_string(), input: self.b_in.clone(), }, &InputPort { - port_id: EQUAL_FORWARD_WE_IN_ID.to_string(), + port_id: DATA_FORWARD_WE_IN_ID.to_string(), input: self.we_in.clone(), }, ], OutputType::Combinatorial, - vec![EQUAL_FORWARD_OUT_ID], + vec![DATA_FORWARD_OUT_ID], ), ) } @@ -66,14 +66,14 @@ impl Component for EqualForward { result = 0; } - simulator.set_out_value(&self.id, EQUAL_FORWARD_OUT_ID, SignalValue::Data(result)); + simulator.set_out_value(&self.id, DATA_FORWARD_OUT_ID, SignalValue::Data(result)); Ok(()) } fn set_id_port(&mut self, target_port_id: Id, new_input: Input) { match target_port_id.as_str() { - EQUAL_FORWARD_A_IN_ID => self.a_in = new_input, - EQUAL_FORWARD_B_IN_ID => self.b_in = new_input, + DATA_FORWARD_A_IN_ID => self.a_in = new_input, + DATA_FORWARD_B_IN_ID => self.b_in = new_input, _ => (), } } @@ -83,9 +83,9 @@ impl Component for EqualForward { } } -impl EqualForward { +impl DataForward { pub fn new(id: &str, pos: (f32, f32), a_in: Input, b_in: Input, we_in: Input) -> Self { - EqualForward { + DataForward { id: id.to_string(), pos, a_in, @@ -95,6 +95,6 @@ impl EqualForward { } pub fn rc_new(id: &str, pos: (f32, f32), a_in: Input, b_in: Input, we_in: Input) -> Rc { - Rc::new(EqualForward::new(id, pos, a_in, b_in, we_in)) + Rc::new(DataForward::new(id, pos, a_in, b_in, we_in)) } } diff --git a/mips-lib/src/components/mod.rs b/mips-lib/src/components/mod.rs index b496130..b30e7b9 100644 --- a/mips-lib/src/components/mod.rs +++ b/mips-lib/src/components/mod.rs @@ -1,9 +1,9 @@ mod mips_alu; +mod mips_alu_forward; mod mips_branch_logic; mod mips_control_unit; +mod mips_data_forward; mod mips_dm; -mod mips_equals_forward; -mod mips_equals_load; mod mips_im; mod mips_instruction_splitter; mod mips_jump_merge; @@ -12,11 +12,11 @@ mod physical_mem; mod sz_extend; pub use mips_alu::*; +pub use mips_alu_forward::*; pub use mips_branch_logic::*; pub use mips_control_unit::*; +pub use mips_data_forward::*; pub use mips_dm::*; -pub use mips_equals_forward::*; -pub use mips_equals_load::*; pub use mips_im::*; pub use mips_instruction_splitter::*; pub use mips_jump_merge::*; diff --git a/mips-lib/src/gui_egui/components/mips_equals_load.rs b/mips-lib/src/gui_egui/components/mips_alu_forward.rs similarity index 78% rename from mips-lib/src/gui_egui/components/mips_equals_load.rs rename to mips-lib/src/gui_egui/components/mips_alu_forward.rs index b309244..c127318 100644 --- a/mips-lib/src/gui_egui/components/mips_equals_load.rs +++ b/mips-lib/src/gui_egui/components/mips_alu_forward.rs @@ -1,6 +1,6 @@ use crate::components::{ - EqualLoad, EQUAL_LOAD_A_IN_ID, EQUAL_LOAD_B_IN_ID, EQUAL_LOAD_LOAD_IN_ID, EQUAL_LOAD_OUT_ID, - EQUAL_LOAD_WE_IN_ID, + AluForward, ALU_FORWARD_A_IN_ID, ALU_FORWARD_B_IN_ID, ALU_FORWARD_LOAD_IN_ID, + ALU_FORWARD_OUT_ID, ALU_FORWARD_WE_IN_ID, }; use egui::{pos2, Rect, Response, Ui, Vec2}; use syncrim::common::{EguiComponent, Id, Input, Ports, Simulator}; @@ -9,7 +9,7 @@ use syncrim::gui_egui::gui::EguiExtra; use syncrim::gui_egui::helper::basic_component_gui; #[typetag::serde] -impl EguiComponent for EqualLoad { +impl EguiComponent for AluForward { fn render( &self, ui: &mut Ui, @@ -21,7 +21,7 @@ impl EguiComponent for EqualLoad { _editor_mode: EditorMode, ) -> Option> { basic_component_gui(self, &simulator, ui.ctx(), offset, scale, clip_rect, |ui| { - ui.label("Equal_Load"); + ui.label("="); }) } @@ -78,7 +78,7 @@ impl EguiComponent for EqualLoad { Some(loc[2]) } else if id == self.load_in { Some(loc[3]) - } else if id == Input::new(&self.id, EQUAL_LOAD_OUT_ID) { + } else if id == Input::new(&self.id, ALU_FORWARD_OUT_ID) { Some(loc[4]) } else { None @@ -90,14 +90,17 @@ impl EguiComponent for EqualLoad { let m = 6f32; // margin let pos: Vec2 = self.pos.into(); vec![ - (EQUAL_LOAD_A_IN_ID.to_string(), pos2(-11.0 - m, -10.0) + pos), - (EQUAL_LOAD_B_IN_ID.to_string(), pos2(-11.0 - m, 10.0) + pos), - (EQUAL_LOAD_WE_IN_ID.to_string(), pos2(-11.0 - m, 2.5) + pos), ( - EQUAL_LOAD_LOAD_IN_ID.to_string(), + ALU_FORWARD_A_IN_ID.to_string(), + pos2(-11.0 - m, -10.0) + pos, + ), + (ALU_FORWARD_B_IN_ID.to_string(), pos2(-11.0 - m, 10.0) + pos), + (ALU_FORWARD_WE_IN_ID.to_string(), pos2(-11.0 - m, 2.5) + pos), + ( + ALU_FORWARD_LOAD_IN_ID.to_string(), pos2(-11.0 - m, 7.5) + pos, ), - (EQUAL_LOAD_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), + (ALU_FORWARD_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), ] } } diff --git a/mips-lib/src/gui_egui/components/mips_equals_forward.rs b/mips-lib/src/gui_egui/components/mips_data_forward.rs similarity index 83% rename from mips-lib/src/gui_egui/components/mips_equals_forward.rs rename to mips-lib/src/gui_egui/components/mips_data_forward.rs index 1225a0f..a2b6c95 100644 --- a/mips-lib/src/gui_egui/components/mips_equals_forward.rs +++ b/mips-lib/src/gui_egui/components/mips_data_forward.rs @@ -1,6 +1,6 @@ use crate::components::{ - EqualForward, EQUAL_FORWARD_A_IN_ID, EQUAL_FORWARD_B_IN_ID, EQUAL_FORWARD_OUT_ID, - EQUAL_FORWARD_WE_IN_ID, + DataForward, DATA_FORWARD_A_IN_ID, DATA_FORWARD_B_IN_ID, DATA_FORWARD_OUT_ID, + DATA_FORWARD_WE_IN_ID, }; use egui::{pos2, Rect, Response, Ui, Vec2}; use syncrim::common::{EguiComponent, Id, Input, Ports, Simulator}; @@ -9,7 +9,7 @@ use syncrim::gui_egui::gui::EguiExtra; use syncrim::gui_egui::helper::basic_component_gui; #[typetag::serde] -impl EguiComponent for EqualForward { +impl EguiComponent for DataForward { fn render( &self, ui: &mut Ui, @@ -21,7 +21,7 @@ impl EguiComponent for EqualForward { _editor_mode: EditorMode, ) -> Option> { basic_component_gui(self, &simulator, ui.ctx(), offset, scale, clip_rect, |ui| { - ui.label("Equal_Load"); + ui.label("="); }) } @@ -76,7 +76,7 @@ impl EguiComponent for EqualForward { Some(loc[1]) } else if id == self.we_in { Some(loc[2]) - } else if id == Input::new(&self.id, EQUAL_FORWARD_OUT_ID) { + } else if id == Input::new(&self.id, DATA_FORWARD_OUT_ID) { Some(loc[3]) } else { None @@ -89,18 +89,18 @@ impl EguiComponent for EqualForward { let pos: Vec2 = self.pos.into(); vec![ ( - EQUAL_FORWARD_A_IN_ID.to_string(), + DATA_FORWARD_A_IN_ID.to_string(), pos2(-11.0 - m, -10.0) + pos, ), ( - EQUAL_FORWARD_B_IN_ID.to_string(), + DATA_FORWARD_B_IN_ID.to_string(), pos2(-11.0 - m, 10.0) + pos, ), ( - EQUAL_FORWARD_WE_IN_ID.to_string(), + DATA_FORWARD_WE_IN_ID.to_string(), pos2(-11.0 - m, 0.0) + pos, ), - (EQUAL_FORWARD_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), + (DATA_FORWARD_OUT_ID.to_string(), pos2(11.0 + m, 0.0) + pos), ] } } diff --git a/mips-lib/src/gui_egui/components/mod.rs b/mips-lib/src/gui_egui/components/mod.rs index d20118e..5ea95d9 100644 --- a/mips-lib/src/gui_egui/components/mod.rs +++ b/mips-lib/src/gui_egui/components/mod.rs @@ -1,9 +1,9 @@ mod full_adder; +mod mips_alu_forward; mod mips_branch_logic; mod mips_control_unit; +mod mips_data_forward; mod mips_dm; -mod mips_equals_forward; -mod mips_equals_load; mod mips_im; mod mips_instruction_splitter; mod mips_jump_merge; From 2a5946a035bcb708d3ab522c4bb677b2a1a991e6 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Fri, 11 Oct 2024 14:37:41 +0200 Subject: [PATCH 12/18] work on stylizing wires --- mips-lib/examples/mips_pipe_example_1.rs | 84 +- mips-lib/mips_pipe.json | 3599 ++++++++++++---------- 2 files changed, 1987 insertions(+), 1696 deletions(-) diff --git a/mips-lib/examples/mips_pipe_example_1.rs b/mips-lib/examples/mips_pipe_example_1.rs index 6464719..40d0eb2 100644 --- a/mips-lib/examples/mips_pipe_example_1.rs +++ b/mips-lib/examples/mips_pipe_example_1.rs @@ -14,7 +14,7 @@ fn main() { let rc_reg_file = RegFile::rc_new( "reg_file", - (435.0, 180.0), + (585.0, 275.0), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("reg_addr_reg", REGISTER_OUT_ID), //write address @@ -24,15 +24,11 @@ fn main() { let cs = ComponentStore { store: vec![ - Rc::new(PhysicalMem::new("phys_mem", (0.0, 0.0))), + Rc::new(PhysicalMem::new("phys_mem", (800.0, 600.0))), // register that holds instr addr - Register::rc_new( - "pc", - (170.0, 410.0), - Input::new("mux_jump_merge", MUX_OUT_ID), - ), + Register::rc_new("pc", (0.0, 390.0), Input::new("mux_jump_merge", MUX_OUT_ID)), // step addr from reg by 4 - Constant::rc_new("+4", (80.0, 380.0), 4), + Constant::rc_new("+4", (80.0, 400.0), 4), Add::rc_new( "pc+4", (130.0, 380.0), @@ -43,7 +39,7 @@ fn main() { // Rc::new(InstrMem::new( "instr_mem".into(), - (100.0, 585.0), + (45.0, 585.0), Input::new("pc", REGISTER_OUT_ID), "phys_mem".into(), "reg_file".into(), @@ -66,22 +62,22 @@ fn main() { // merges to find out jump location JumpMerge::rc_new( "jump_merge", - (-62.0, 500.0), + (180.0, 530.0), Input::new("pc", REGISTER_OUT_ID), //input from reg before pc+4 Input::new("instr_mem", INSTR_MEM_INSTRUCTION_ID), //input from instruction mem ), // // - Register::rc_new("pc+4_reg", (200.0, 370.0), Input::new("pc+4", ADD_OUT_ID)), + Register::rc_new("pc+4_reg", (240.0, 370.0), Input::new("pc+4", ADD_OUT_ID)), PassThrough::rc_new( "pc+4_pass", - (240.0, 370.0), + (260.0, 370.0), Input::new("pc+4_reg", REGISTER_OUT_ID), ), // Register::rc_new( "InMem_reg", - (210.0, 475.0), + (240.0, 475.0), Input::new("instr_mem", INSTR_MEM_INSTRUCTION_ID), ), PassThrough::rc_new( @@ -92,42 +88,42 @@ fn main() { // Register::rc_new( "merge_reg", - (215.0, 580.0), + (240.0, 580.0), Input::new("jump_merge", MERGE_OUT_ID), ), // // splits instructions from ir to fields InstrSplit::rc_new( "instruction_split", - (270.0, 150.0), + (400.0, 275.0), Input::new("InMem_reg", REGISTER_OUT_ID), ), // // First CU, handles, select for sign/zero_extend and mux_write_addr ControlUnit::rc_new( "control_unit_1", - (260.0, 0.0), + (670.0, 0.0), Input::new("InMem_reg", REGISTER_OUT_ID), ), // // Second CU, handles, mux_source_a, mux_source_b and the alu ControlUnit::rc_new( "control_unit_2", - (1200.0, 0.0), + (1285.0, 0.0), Input::new("control_EX_reg", REGISTER_OUT_ID), ), // // Third CU, handles, write_back_mux, and DMs mem-read and mem-write ControlUnit::rc_new( "control_unit_3", - (1670.0, 0.0), + (1695.0, 0.0), Input::new("control_MEM_reg", REGISTER_OUT_ID), ), // // Fourth CU, handles, WE for reg_file in the WB stage ControlUnit::rc_new( "control_unit_4", - (2216.0, 0.0), + (2220.0, 0.0), Input::new("control_WB_reg", REGISTER_OUT_ID), ), // @@ -135,7 +131,7 @@ fn main() { // extends immediate field SignZeroExtend::rc_new( "signzero_extend", - (310.0, 410.0), + (400.0, 475.0), Input::new("instruction_split", INSTRUCTION_SPLITTER_IMMEDIATE_ID), Input::new("control_unit_1", cntr_field::EXTEND_SELECT_OUT), // cu tells it to either sing- or zero- extend ), @@ -151,7 +147,7 @@ fn main() { // ), DataForward::rc_new( "data_forward_A", - (800.0, 160.0), + (800.0, 155.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), Input::new("control_unit_3", cntr_field::REG_WRITE_ENABLE_OUT), @@ -176,7 +172,7 @@ fn main() { // ), DataForward::rc_new( "data_forward_B", - (800.0, 425.0), + (800.0, 395.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("control_unit_3", cntr_field::REG_WRITE_ENABLE_OUT), @@ -201,7 +197,7 @@ fn main() { // ), AluForward::rc_new( "alu_forward_A", - (970.0, 160.0), + (970.0, 155.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RS_ID), Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), @@ -220,14 +216,14 @@ fn main() { // // // Equal::rc_new( - // "equals_operand_B_2", + // "alu_forward_B", // (3300.0, 2300.0), // Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), // Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), // ), AluForward::rc_new( - "equals_operand_B_2", - (970.0, 425.0), + "alu_forward_B", + (970.0, 395.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), Input::new("control_unit_2", cntr_field::REG_WRITE_ENABLE_OUT), @@ -237,7 +233,7 @@ fn main() { Mux::rc_new( "alu_forward_B_mux", (970.0, 325.0), - Input::new("equals_operand_B_2", ALU_FORWARD_OUT_ID), + Input::new("alu_forward_B", ALU_FORWARD_OUT_ID), vec![ Input::new("data_forward_B_mux", MUX_OUT_ID), Input::new("alu", FULL_ADD_OUT_ID), @@ -259,12 +255,12 @@ fn main() { Register::rc_new( //TODO: make 2 more control units "control_EX_reg", - (920.0, -40.0), + (1100.0, -40.0), Input::new("InMem_pass", PASS_THROUGH_OUT_ID), ), PassThrough::rc_new( "control_EX_pass", - (960.0, -40.0), + (1140.0, -40.0), Input::new("control_EX_reg", REGISTER_OUT_ID), ), // @@ -295,23 +291,23 @@ fn main() { // Register::rc_new( "mux_b2_reg", - (1100.0, 550.0), + (1100.0, 420.0), Input::new("pc+4_pass", PASS_THROUGH_OUT_ID), ), Register::rc_new( "mux_b3_reg", - (1100.0, 625.0), + (1100.0, 465.0), Input::new("signzero_extend", SIGNZEROEXTEND_OUT_ID), ), // Register::rc_new( "reg_addr_EX_reg", - (1125.0, 800.0), + (1100.0, 520.0), Input::new("mux_write_addr", MUX_OUT_ID), ), PassThrough::rc_new( "reg_addr_EX_pass", - (1165.0, 800.0), + (1165.0, 520.0), Input::new("reg_addr_EX_reg", REGISTER_OUT_ID), ), // @@ -323,7 +319,7 @@ fn main() { ), // // - Constant::rc_new("0_a_inp", (600.0, 50.0), 4), + Constant::rc_new("0_a_inp", (1190.0, 210.0), 4), Mux::rc_new( "mux_source_a", (1250.0, 210.0), @@ -352,7 +348,7 @@ fn main() { // ALU::rc_new( "alu", - (1400.0, 220.0), + (1400.0, 250.0), Input::new("mux_source_a", MUX_OUT_ID), Input::new("mux_source_b", MUX_OUT_ID), Input::new("control_unit_2", cntr_field::ALU_OP_OUT), @@ -361,7 +357,7 @@ fn main() { // Rc::new(DataMem::new( "data_mem".into(), - (1660.0, 560.0), + (1660.0, 585.0), Input::new("alu_reg", REGISTER_OUT_ID), // calculated from rs and imm Input::new("data_MEM_reg", REGISTER_OUT_ID), Input::new("control_unit_3", cntr_field::MEM_MODE_OUT), @@ -390,25 +386,25 @@ fn main() { // Register::rc_new( "data_MEM_reg", - (1470.0, 565.0), + (1470.0, 585.0), Input::new("operand_b_pass", PASS_THROUGH_OUT_ID), ), // Register::rc_new( "reg_addr_MEM_reg", - (1480.0, 800.0), + (1470.0, 520.0), Input::new("reg_addr_EX_pass", PASS_THROUGH_OUT_ID), ), PassThrough::rc_new( "reg_addr_MEM_pass", - (1520.0, 800.0), + (1520.0, 520.0), Input::new("reg_addr_MEM_reg", REGISTER_OUT_ID), ), // // Mux::rc_new( "write_back_mux", - (1680.0, 270.0), + (1800.0, 270.0), Input::new("control_unit_3", cntr_field::REG_WRITE_SRC_OUT), vec![ Input::new("alu_reg", REGISTER_OUT_ID), @@ -431,14 +427,14 @@ fn main() { // Register::rc_new( "reg_addr_reg", - (1920.0, 800.0), + (1920.0, 520.0), Input::new("reg_addr_MEM_pass", PASS_THROUGH_OUT_ID), ), // // ShiftConst::rc_new( "branch_shift", - (380.0, 460.0), + (400.0, 585.0), Input::new("signzero_extend", SIGNZEROEXTEND_OUT_ID), 2, ), @@ -446,7 +442,7 @@ fn main() { // Add::rc_new( "pc_add_branch", - (420.0, 440.0), + (585.0, 565.0), Input::new("pc+4_reg", REGISTER_OUT_ID), Input::new("branch_shift", SHIFT_OUT_ID), ), @@ -455,7 +451,7 @@ fn main() { Constant::rc_new("0x_1F", (500.0, 510.0), 0x_1F), Mux::rc_new( "mux_write_addr", - (560.0, 500.0), + (970.0, 520.0), Input::new("control_unit_1", cntr_field::REG_DEST_OUT), vec![ Input::new("instruction_split", INSTRUCTION_SPLITTER_RT_ID), diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index dce6a04..30bcbfd 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -1,231 +1,154 @@ { "store": [ { - "type": "PhysicalMem", - "id": "phys_mem", + "type": "Register", + "id": "control_MEM_reg", "pos": [ - 0.0, - 0.0 - ] + 1470.0, + -40.0 + ], + "r_in": { + "id": "control_EX_pass", + "field": "pass_through_out" + } }, { "type": "Register", - "id": "pc", + "id": "operand_b_reg", "pos": [ - 170.0, - 410.0 + 1100.0, + 325.0 ], "r_in": { - "id": "mux_jump_merge", + "id": "alu_forward_B_mux", "field": "mux_out" } }, { - "type": "Constant", - "id": "+4", + "type": "Register", + "id": "InMem_reg", "pos": [ - 80.0, - 380.0 + 240.0, + 475.0 ], - "value": { - "data": { - "Data": 4 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } + "r_in": { + "id": "instr_mem", + "field": "instruction" } }, { - "type": "Add", - "id": "pc+4", + "type": "Register", + "id": "operand_a_reg", "pos": [ - 130.0, - 380.0 + 1100.0, + 215.0 ], - "a_in": { - "id": "pc", - "field": "register_out" - }, - "b_in": { - "id": "+4", - "field": "constant_out" - }, - "scale": 1.0 + "r_in": { + "id": "alu_forward_A_mux", + "field": "mux_out" + } }, { - "type": "InstrMem", - "id": "instr_mem", + "type": "Register", + "id": "control_WB_reg", "pos": [ - 100.0, - 585.0 + 1920.0, + -40.0 ], - "pc": { - "id": "pc", - "field": "register_out" - }, - "phys_mem_id": "phys_mem", - "regfile_id": "reg_file", - "mem_view": { - "visible": false, - "title": "instruction memory view", - "id": "instr_mem", - "row_offset": 0, - "max_rows": 1024, - "big_endian": true, - "format": "HexAndMips", - "show_settings": { - "symbols": true, - "sections": false, - "program_counter": false, - "registers": [ - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - true - ] - }, - "register_values": null, - "dynamic_symbols": { - "PC_IM": [ - 0, - true - ] - }, - "break_points": [] + "r_in": { + "id": "control_MEM_pass", + "field": "pass_through_out" } }, { - "type": "Mux", - "id": "mux_jump_merge", + "type": "Register", + "id": "alu_reg", "pos": [ - -54.0, - 390.0 + 1470.0, + 250.0 ], - "select": { - "id": "branch", - "field": "branch_out" - }, - "m_in": [ - { - "id": "pc_add_branch", - "field": "add_out" - }, - { - "id": "alu_forward_A_mux", - "field": "mux_out" - }, - { - "id": "merge_reg", - "field": "register_out" - }, - { - "id": "pc+4", - "field": "add_out" - } + "r_in": { + "id": "alu", + "field": "alu_out" + } + }, + { + "type": "Register", + "id": "reg_addr_MEM_reg", + "pos": [ + 1470.0, + 520.0 ], - "scale": 1.0 + "r_in": { + "id": "reg_addr_EX_pass", + "field": "pass_through_out" + } }, { - "type": "JumpMerge", - "id": "jump_merge", + "type": "Register", + "id": "zero_extend_reg", "pos": [ - -62.0, - 500.0 + 1100.0, + 110.0 ], - "instr_addr_in": { - "id": "pc", - "field": "register_out" - }, - "jump_addr_in": { - "id": "instr_mem", - "field": "instruction" + "r_in": { + "id": "instruction_split", + "field": "shamt_out" } }, { "type": "Register", - "id": "pc+4_reg", + "id": "control_EX_reg", "pos": [ - 200.0, - 370.0 + 1100.0, + -40.0 ], "r_in": { - "id": "pc+4", - "field": "add_out" + "id": "InMem_pass", + "field": "pass_through_out" } }, { - "type": "PassThrough", - "id": "pc+4_pass", + "type": "Register", + "id": "reg_addr_EX_reg", "pos": [ - 240.0, - 370.0 + 1100.0, + 520.0 ], - "input": { - "id": "pc+4_reg", - "field": "register_out" + "r_in": { + "id": "mux_write_addr", + "field": "mux_out" } }, { "type": "Register", - "id": "InMem_reg", + "id": "result_reg_EX", "pos": [ - 210.0, - 475.0 + 1920.0, + 270.0 ], "r_in": { - "id": "instr_mem", - "field": "instruction" + "id": "write_back_mux", + "field": "mux_out" } }, { - "type": "PassThrough", - "id": "InMem_pass", + "type": "Register", + "id": "data_MEM_reg", "pos": [ - 250.0, - 475.0 + 1470.0, + 585.0 ], - "input": { - "id": "InMem_reg", - "field": "register_out" + "r_in": { + "id": "operand_b_pass", + "field": "pass_through_out" } }, { "type": "Register", "id": "merge_reg", "pos": [ - 215.0, + 240.0, 580.0 ], "r_in": { @@ -234,307 +157,248 @@ } }, { - "type": "InstrSplit", - "id": "instruction_split", + "type": "Register", + "id": "mux_b3_reg", "pos": [ - 270.0, - 150.0 + 1100.0, + 475.0 ], - "instruction_in": { - "id": "InMem_reg", - "field": "register_out" + "r_in": { + "id": "signzero_extend", + "field": "sz_out" } }, { - "type": "ControlUnit", - "id": "control_unit_1", + "type": "Register", + "id": "mux_b2_reg", "pos": [ - 260.0, - 0.0 + 1100.0, + 420.0 ], - "a_in": { - "id": "InMem_reg", - "field": "register_out" + "r_in": { + "id": "pc+4_pass", + "field": "pass_through_out" } }, { - "type": "ControlUnit", - "id": "control_unit_2", + "type": "Register", + "id": "pc+4_reg", "pos": [ - 1200.0, - 0.0 + 240.0, + 380.0 ], - "a_in": { - "id": "control_EX_reg", - "field": "register_out" + "r_in": { + "id": "pc+4", + "field": "add_out" } }, { - "type": "ControlUnit", - "id": "control_unit_3", + "type": "Register", + "id": "reg_addr_reg", "pos": [ - 1670.0, - 0.0 + 1920.0, + 520.0 ], - "a_in": { - "id": "control_MEM_reg", - "field": "register_out" + "r_in": { + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" } }, { - "type": "ControlUnit", - "id": "control_unit_4", + "type": "Register", + "id": "pc", "pos": [ - 2216.0, - 0.0 + 0.0, + 390.0 ], - "a_in": { - "id": "control_WB_reg", - "field": "register_out" + "r_in": { + "id": "mux_jump_merge", + "field": "mux_out" } }, { - "type": "SignZeroExtend", - "id": "signzero_extend", + "type": "Wire", + "id": "from operand_b_reg:register_out to mux_source_b:in0", "pos": [ - 310.0, - 410.0 + [ + 1110.0, + 325.0 + ], + [ + 1230.0, + 305.0 + ] ], - "signzero_signal_in": { - "id": "instruction_split", - "field": "immediate_out" - }, - "signzero_ctrl_in": { - "id": "control_unit_1", - "field": "extend_select" + "input": { + "id": "operand_b_reg", + "field": "register_out" } }, { - "type": "DataForward", - "id": "data_forward_A", + "type": "Wire", + "id": "from InMem_reg:register_out to instruction_split:instruction_in", "pos": [ - 800.0, - 160.0 + [ + 279.0, + 275.0 + ], + [ + 359.0, + 275.0 + ] ], - "a_in": { - "id": "reg_addr_MEM_reg", + "input": { + "id": "InMem_reg", "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "we_in": { - "id": "control_unit_3", - "field": "reg_write_enable" } }, { - "type": "Mux", - "id": "data_forward_A_mux", + "type": "Wire", + "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", "pos": [ - 800.0, - 225.0 - ], - "select": { - "id": "data_forward_A", - "field": "data_forward_out" - }, - "m_in": [ - { - "id": "reg_file", - "field": "rs_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } + [ + 250.0, + 475.0 + ], + [ + 250.0, + 475.0 + ] ], - "scale": 1.0 + "input": { + "id": "InMem_reg", + "field": "register_out" + } }, { - "type": "DataForward", - "id": "data_forward_B", + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", "pos": [ - 800.0, - 425.0 + [ + 1480.0, + 520.0 + ], + [ + 1520.0, + 520.0 + ] ], - "a_in": { + "input": { "id": "reg_addr_MEM_reg", "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "we_in": { - "id": "control_unit_3", - "field": "reg_write_enable" } }, { - "type": "Mux", - "id": "data_forward_B_mux", + "type": "PassThrough", + "id": "InMem_pass", "pos": [ - 800.0, - 325.0 + 250.0, + 475.0 ], - "select": { - "id": "data_forward_B", - "field": "data_forward_out" - }, - "m_in": [ - { - "id": "reg_file", - "field": "rt_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } + "input": { + "id": "InMem_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", + "pos": [ + [ + 250.0, + 475.0 + ], + [ + 280.0, + 475.0 + ], + [ + 280.0, + -40.0 + ], + [ + 1090.0, + -40.0 + ] ], - "scale": 1.0 + "input": { + "id": "InMem_pass", + "field": "pass_through_out" + } }, { - "type": "AluForward", - "id": "alu_forward_A", + "type": "ZeroExtend", + "id": "zero_extend_for_shamt", "pos": [ - 970.0, - 160.0 + 1165.0, + 110.0 ], - "a_in": { - "id": "reg_addr_EX_reg", + "signal_in": { + "id": "zero_extend_reg", "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "we_in": { - "id": "control_unit_2", - "field": "reg_write_enable" - }, - "load_in": { - "id": "control_unit_2", - "field": "mem_mode" } }, { - "type": "Mux", - "id": "alu_forward_A_mux", + "type": "Constant", + "id": "+4", "pos": [ - 970.0, - 225.0 + 80.0, + 400.0 ], - "select": { - "id": "alu_forward_A", - "field": "equals_forward_out" - }, - "m_in": [ - { - "id": "data_forward_A_mux", - "field": "mux_out" + "value": { + "data": { + "Data": 4 }, - { - "id": "alu", - "field": "alu_out" + "fmt": { + "Hex": [ + "_32", + false + ] } - ], - "scale": 1.0 + } }, { - "type": "AluForward", - "id": "equals_operand_B_2", + "type": "PassThrough", + "id": "control_EX_pass", "pos": [ - 970.0, - 425.0 + 1140.0, + -40.0 ], - "a_in": { - "id": "reg_addr_EX_reg", - "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "we_in": { - "id": "control_unit_2", - "field": "reg_write_enable" - }, - "load_in": { - "id": "control_unit_2", - "field": "mem_mode" - } - }, - { - "type": "Mux", - "id": "alu_forward_B_mux", - "pos": [ - 970.0, - 325.0 - ], - "select": { - "id": "equals_operand_B_2", - "field": "equals_forward_out" - }, - "m_in": [ - { - "id": "data_forward_B_mux", - "field": "mux_out" - }, - { - "id": "alu", - "field": "alu_out" - } - ], - "scale": 1.0 - }, - { - "type": "BranchLogic", - "id": "branch", - "pos": [ - 1040.0, - 275.0 - ], - "op_in": { - "id": "instruction_split", - "field": "op_out" - }, - "rt_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "funct_in": { - "id": "instruction_split", - "field": "funct_out" - }, - "rs_value": { - "id": "alu_forward_A_mux", - "field": "mux_out" - }, - "rt_value": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "input": { + "id": "control_EX_reg", + "field": "register_out" } }, { - "type": "Register", - "id": "control_EX_reg", + "type": "Wire", + "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", "pos": [ - 920.0, - -40.0 + [ + 1140.0, + -40.0 + ], + [ + 1460.0, + -40.0 + ] ], - "r_in": { - "id": "InMem_pass", + "input": { + "id": "control_EX_pass", "field": "pass_through_out" } }, { - "type": "PassThrough", - "id": "control_EX_pass", + "type": "Wire", + "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", "pos": [ - 960.0, - -40.0 + [ + 1110.0, + -40.0 + ], + [ + 1140.0, + -40.0 + ] ], "input": { "id": "control_EX_reg", @@ -542,95 +406,35 @@ } }, { - "type": "Register", - "id": "zero_extend_reg", - "pos": [ - 1100.0, - 110.0 - ], - "r_in": { - "id": "instruction_split", - "field": "shamt_out" - } - }, - { - "type": "Register", - "id": "operand_a_reg", - "pos": [ - 1100.0, - 215.0 - ], - "r_in": { - "id": "alu_forward_A_mux", - "field": "mux_out" - } - }, - { - "type": "Register", - "id": "operand_b_reg", - "pos": [ - 1100.0, - 325.0 - ], - "r_in": { - "id": "alu_forward_B_mux", - "field": "mux_out" - } - }, - { - "type": "PassThrough", - "id": "operand_b_pass", + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", "pos": [ - 1140.0, - 325.0 + [ + 1110.0, + 520.0 + ], + [ + 1165.0, + 520.0 + ] ], "input": { - "id": "operand_b_reg", + "id": "reg_addr_EX_reg", "field": "register_out" } }, { - "type": "Register", - "id": "mux_b2_reg", - "pos": [ - 1100.0, - 550.0 - ], - "r_in": { - "id": "pc+4_pass", - "field": "pass_through_out" - } - }, - { - "type": "Register", - "id": "mux_b3_reg", - "pos": [ - 1100.0, - 625.0 - ], - "r_in": { - "id": "signzero_extend", - "field": "sz_out" - } - }, - { - "type": "Register", - "id": "reg_addr_EX_reg", - "pos": [ - 1125.0, - 800.0 - ], - "r_in": { - "id": "mux_write_addr", - "field": "mux_out" - } - }, - { - "type": "PassThrough", - "id": "reg_addr_EX_pass", + "type": "Wire", + "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", "pos": [ - 1165.0, - 800.0 + [ + 1110.0, + 520.0 + ], + [ + 953.0, + 145.0 + ] ], "input": { "id": "reg_addr_EX_reg", @@ -638,1063 +442,1018 @@ } }, { - "type": "ZeroExtend", - "id": "zero_extend_for_shamt", + "type": "Wire", + "id": "from result_reg_EX:register_out to reg_file:write_data_in", "pos": [ - 1165.0, - 110.0 + [ + 1930.0, + 270.0 + ], + [ + 1970.0, + 270.0 + ], + [ + 1970.0, + 655.0 + ], + [ + 620.0, + 655.0 + ], + [ + 620.0, + 406.0 + ] ], - "signal_in": { - "id": "zero_extend_reg", + "input": { + "id": "result_reg_EX", "field": "register_out" } }, { - "type": "Constant", - "id": "0_a_inp", - "pos": [ - 600.0, - 50.0 - ], - "value": { - "data": { - "Data": 4 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } - } - }, - { - "type": "Mux", - "id": "mux_source_a", - "pos": [ - 1250.0, - 210.0 - ], - "select": { - "id": "control_unit_2", - "field": "alu_src_a" - }, - "m_in": [ - { - "id": "zero_extend_for_shamt", - "field": "zero_extend_out" - }, - { - "id": "operand_a_reg", - "field": "register_out" - }, - { - "id": "0_a_inp", - "field": "constant_out" - } - ], - "scale": 1.0 - }, - { - "type": "Mux", - "id": "mux_source_b", - "pos": [ - 1250.0, - 325.0 - ], - "select": { - "id": "control_unit_2", - "field": "alu_src_b" - }, - "m_in": [ - { - "id": "operand_b_reg", - "field": "register_out" - }, - { - "id": "mux_b2_reg", - "field": "register_out" - }, - { - "id": "mux_b3_reg", - "field": "register_out" - } - ], - "scale": 1.0 - }, - { - "type": "ALU", - "id": "alu", - "pos": [ - 1400.0, - 220.0 - ], - "a_in": { - "id": "mux_source_a", - "field": "mux_out" - }, - "b_in": { - "id": "mux_source_b", - "field": "mux_out" - }, - "op_in": { - "id": "control_unit_2", - "field": "alu_op" - } - }, - { - "type": "DataMem", - "id": "data_mem", + "type": "Wire", + "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", "pos": [ - 1660.0, - 560.0 + [ + 1110.0, + -40.0 + ], + [ + 1079.0, + 0.0 + ] ], - "address_input": { - "id": "alu_reg", - "field": "register_out" - }, - "data_input": { - "id": "data_MEM_reg", + "input": { + "id": "control_EX_reg", "field": "register_out" - }, - "op_input": { - "id": "control_unit_3", - "field": "mem_mode" - }, - "write_enable_input": { - "id": "control_unit_3", - "field": "mem_write_enable" - }, - "phys_mem_id": "phys_mem", - "regfile_id": "reg_file", - "mem_view": { - "visible": false, - "title": "Data memory view", - "id": "data_mem", - "row_offset": 0, - "max_rows": 1024, - "big_endian": true, - "format": "ByteAndUtf8", - "show_settings": { - "symbols": true, - "sections": false, - "program_counter": false, - "registers": [ - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false - ] - }, - "register_values": null, - "dynamic_symbols": {}, - "break_points": [] } }, { - "type": "Register", - "id": "control_MEM_reg", - "pos": [ - 1470.0, - -40.0 - ], - "r_in": { - "id": "control_EX_pass", - "field": "pass_through_out" - } - }, - { - "type": "PassThrough", - "id": "control_MEM_pass", + "type": "Wire", + "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", "pos": [ - 1510.0, - -40.0 + [ + 1480.0, + 520.0 + ], + [ + 783.0, + 145.0 + ] ], "input": { - "id": "control_MEM_reg", + "id": "reg_addr_MEM_reg", "field": "register_out" } }, { - "type": "Register", - "id": "alu_reg", - "pos": [ - 1470.0, - 250.0 - ], - "r_in": { - "id": "alu", - "field": "alu_out" - } - }, - { - "type": "Register", - "id": "data_MEM_reg", + "type": "InstrSplit", + "id": "instruction_split", "pos": [ - 1470.0, - 565.0 + 400.0, + 275.0 ], - "r_in": { - "id": "operand_b_pass", - "field": "pass_through_out" + "instruction_in": { + "id": "InMem_reg", + "field": "register_out" } }, { - "type": "Register", - "id": "reg_addr_MEM_reg", + "type": "Wire", + "id": "from instruction_split:rs_out to data_forward_A:b_in", "pos": [ - 1480.0, - 800.0 + [ + 585.0, + 120.0 + ], + [ + 800.0, + 120.0 + ], + [ + 800.0, + 142.0 + ] ], - "r_in": { - "id": "reg_addr_EX_pass", - "field": "pass_through_out" + "input": { + "id": "instruction_split", + "field": "rs_out" } }, { - "type": "PassThrough", - "id": "reg_addr_MEM_pass", + "type": "Wire", + "id": "from instruction_split:rd_out to mux_write_addr:in1", "pos": [ - 1520.0, - 800.0 + [ + 431.0, + 350.0 + ], + [ + 480.0, + 350.0 + ], + [ + 480.0, + 519.2 + ], + [ + 700.0, + 520.0 + ] ], "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" + "id": "instruction_split", + "field": "rd_out" } }, { - "type": "Mux", - "id": "write_back_mux", + "type": "Wire", + "id": "from instruction_split:rt_out to alu_forward_B:b_in", "pos": [ - 1680.0, - 270.0 - ], - "select": { - "id": "control_unit_3", - "field": "reg_write_src" - }, - "m_in": [ - { - "id": "alu_reg", - "field": "register_out" - }, - { - "id": "data_mem", - "field": "data_out" - } + [ + 431.0, + 286.1111 + ], + [ + 953.0, + 405.0 + ] ], - "scale": 1.0 + "input": { + "id": "instruction_split", + "field": "rt_out" + } }, { - "type": "Register", - "id": "control_WB_reg", + "type": "Wire", + "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", "pos": [ - 1920.0, - -40.0 + [ + 400.0, + 381.5 + ], + [ + 400.0, + 391.0 + ], + [ + 320.0, + 391.0 + ], + [ + 320.0, + 475.5 + ], + [ + 341.5, + 475.0 + ] ], - "r_in": { - "id": "control_MEM_pass", - "field": "pass_through_out" + "input": { + "id": "instruction_split", + "field": "immediate_out" } }, { - "type": "Register", - "id": "result_reg_EX", + "type": "Wire", + "id": "from instruction_split:rt_out to reg_file:rt_address_in", "pos": [ - 1920.0, - 270.0 + [ + 431.0, + 286.1111 + ], + [ + 585.0, + 406.0 + ] ], - "r_in": { - "id": "write_back_mux", - "field": "mux_out" + "input": { + "id": "instruction_split", + "field": "rt_out" } }, { - "type": "Register", - "id": "reg_addr_reg", + "type": "Wire", + "id": "from operand_a_reg:register_out to mux_source_a:in1", "pos": [ - 1920.0, - 800.0 + [ + 1110.0, + 215.0 + ], + [ + 1230.0, + 210.0 + ] ], - "r_in": { - "id": "reg_addr_MEM_pass", - "field": "pass_through_out" + "input": { + "id": "operand_a_reg", + "field": "register_out" } }, { - "type": "ShiftConst", - "id": "branch_shift", + "type": "Wire", + "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", "pos": [ - 380.0, - 460.0 + [ + 1480.0, + 585.0 + ], + [ + 1594.0, + 585.0 + ] ], - "signal_in": { - "id": "signzero_extend", - "field": "sz_out" - }, - "shift_by": 2 + "input": { + "id": "data_MEM_reg", + "field": "register_out" + } }, { - "type": "Add", - "id": "pc_add_branch", + "type": "Wire", + "id": "from instruction_split:rs_out to reg_file:rs_address_in", "pos": [ - 420.0, - 440.0 + [ + 431.0, + 196.0 + ], + [ + 440.0, + 196.0 + ], + [ + 440.0, + 120.0 + ], + [ + 585.0, + 120.0 + ], + [ + 585.0, + 144.0 + ] ], - "a_in": { - "id": "pc+4_reg", - "field": "register_out" - }, - "b_in": { - "id": "branch_shift", - "field": "shift_left_const_out" - }, - "scale": 1.0 + "input": { + "id": "instruction_split", + "field": "rs_out" + } }, { - "type": "Constant", - "id": "0x_1F", + "type": "PassThrough", + "id": "operand_b_pass", "pos": [ - 500.0, - 510.0 + 1140.0, + 325.0 ], - "value": { - "data": { - "Data": 31 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } + "input": { + "id": "operand_b_reg", + "field": "register_out" } }, { - "type": "Mux", - "id": "mux_write_addr", + "type": "Wire", + "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", "pos": [ - 560.0, - 500.0 - ], - "select": { - "id": "control_unit_1", - "field": "reg_dest" - }, - "m_in": [ - { - "id": "instruction_split", - "field": "rt_out" - }, - { - "id": "instruction_split", - "field": "rd_out" - }, - { - "id": "0x_1F", - "field": "constant_out" - } + [ + 1140.8003, + 325.0 + ], + [ + 1140.8003, + 585.0 + ], + [ + 1460.8003, + 585.0 + ] ], - "scale": 1.0 + "input": { + "id": "operand_b_pass", + "field": "pass_through_out" + } }, { - "type": "RegFile", - "id": "reg_file", + "type": "Wire", + "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", "pos": [ - 435.0, - 180.0 + [ + 395.0, + 170.0 + ], + [ + 395.0, + 100.0 + ], + [ + 1090.0, + 100.0 + ] ], - "rs_address_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "rt_address_in": { + "input": { "id": "instruction_split", - "field": "rt_out" - }, - "write_address_in": { - "id": "reg_addr_reg", - "field": "register_out" - }, - "write_data_in": { - "id": "result_reg_EX", - "field": "register_out" - }, - "write_enable_in": { - "id": "control_unit_4", - "field": "reg_write_enable" + "field": "shamt_out" } }, { "type": "Wire", - "id": "from mux_jump_merge:mux_out to pc:r_in", + "id": "from merge_reg:register_out to mux_jump_merge:in2", "pos": [ [ - -44.0, - 390.0 + 250.0, + 580.0 + ], + [ + 260.0, + 580.0 + ], + [ + 260.0, + 630.0 + ], + [ + -94.0, + 630.0 + ], + [ + -94.0, + 400.0 ], [ - 160.0, - 410.0 + -74.0, + 400.0 ] ], "input": { - "id": "mux_jump_merge", - "field": "mux_out" + "id": "merge_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "control_MEM_pass", + "pos": [ + 1510.0, + -40.0 + ], + "input": { + "id": "control_MEM_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from pc:register_out to pc+4:a_in", + "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", "pos": [ [ - 180.0, - 410.0 + 1510.0, + -40.0 ], [ - 110.0, - 360.0 + 1910.0, + -40.0 ] ], "input": { - "id": "pc", - "field": "register_out" + "id": "control_MEM_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from +4:constant_out to pc+4:b_in", + "id": "from alu_reg:register_out to write_back_mux:in0", "pos": [ [ - 80.0, - 380.0 + 1480.0, + 250.0 ], [ - 110.0, - 400.0 + 1750.0, + 250.0 + ], + [ + 1750.0, + 260.0 + ], + [ + 1780.0, + 260.0 ] ], "input": { - "id": "+4", - "field": "constant_out" + "id": "alu_reg", + "field": "register_out" } }, { - "type": "Wire", - "id": "from pc:register_out to instr_mem:pc", + "type": "ControlUnit", + "id": "control_unit_2", "pos": [ - [ - 180.0, - 410.0 - ], - [ - 60.0, - 551.5 - ] + 1285.0, + 0.0 ], - "input": { - "id": "pc", + "a_in": { + "id": "control_EX_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from branch:branch_out to mux_jump_merge:select", + "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", "pos": [ [ - 1040.0, - 275.0 + 1318.3334, + 13.5 ], [ - -64.0, - 340.0 + 953.0, + 162.5 ] ], "input": { - "id": "branch", - "field": "branch_out" + "id": "control_unit_2", + "field": "mem_mode" } }, { "type": "Wire", - "id": "from pc_add_branch:add_out to mux_jump_merge:in0", + "id": "from control_unit_2:reg_write_enable to alu_forward_B:we_in", "pos": [ [ - 440.0, - 440.0 + 1451.6666, + 13.5 ], [ - -74.0, - 360.0 + 953.0, + 397.5 ] ], "input": { - "id": "pc_add_branch", - "field": "add_out" + "id": "control_unit_2", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", + "id": "from control_unit_2:alu_src_b to mux_source_b:select", "pos": [ [ - 980.0, - 225.0 + 1251.6666, + 13.5 ], [ - -74.0, - 380.0 + 1240.0, + 285.0 ] ], "input": { - "id": "alu_forward_A_mux", - "field": "mux_out" + "id": "control_unit_2", + "field": "alu_src_b" } }, { "type": "Wire", - "id": "from merge_reg:register_out to mux_jump_merge:in2", + "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", "pos": [ [ - 225.0, - 580.0 + 1451.6666, + 13.5 ], [ - -74.0, - 400.0 + 953.0, + 157.5 ] ], "input": { - "id": "merge_reg", - "field": "register_out" + "id": "control_unit_2", + "field": "reg_write_enable" } }, { - "type": "Wire", - "id": "from pc+4:add_out to mux_jump_merge:in3", + "type": "AluForward", + "id": "alu_forward_A", "pos": [ - [ - 150.0, - 380.0 - ], - [ - -74.0, - 420.0 - ] + 970.0, + 155.0 ], - "input": { - "id": "pc+4", - "field": "add_out" + "a_in": { + "id": "reg_addr_EX_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "we_in": { + "id": "control_unit_2", + "field": "reg_write_enable" + }, + "load_in": { + "id": "control_unit_2", + "field": "mem_mode" } }, { "type": "Wire", - "id": "from pc:register_out to jump_merge:merge_instr_addr_in", + "id": "from alu_reg:register_out to data_mem:data_mem_address_in", "pos": [ [ - 180.0, - 410.0 + 1630.0, + 250.0 ], [ - -62.0, - 500.0 + 1630.0, + 551.5 ] ], "input": { - "id": "pc", + "id": "alu_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", + "id": "from control_unit_2:mem_mode to alu_forward_B:load_in", "pos": [ [ - 140.0, - 551.5 + 1318.3334, + 13.5 ], [ - -62.0, - 500.0 + 953.0, + 402.5 ] ], "input": { - "id": "instr_mem", - "field": "instruction" + "id": "control_unit_2", + "field": "mem_mode" } }, { - "type": "Wire", - "id": "from pc+4:add_out to pc+4_reg:r_in", + "type": "PassThrough", + "id": "reg_addr_MEM_pass", "pos": [ - [ - 150.0, - 380.0 - ], - [ - 190.0, - 370.0 - ] + 1520.0, + 520.0 ], "input": { - "id": "pc+4", - "field": "add_out" + "id": "reg_addr_MEM_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", + "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", "pos": [ [ - 210.0, - 370.0 + 1110.0, + 325.0 ], [ - 240.0, - 370.0 + 1140.0, + 325.0 ] ], "input": { - "id": "pc+4_reg", + "id": "operand_b_reg", "field": "register_out" } }, { - "type": "Wire", - "id": "from instr_mem:instruction to InMem_reg:r_in", + "type": "Constant", + "id": "0x_1F", "pos": [ - [ - 140.0, - 551.5 - ], - [ - 200.0, - 475.0 - ] + 670.0, + 540.0 ], - "input": { - "id": "instr_mem", - "field": "instruction" + "value": { + "data": { + "Data": 31 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { "type": "Wire", - "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", + "id": "from 0x_1F:constant_out to mux_write_addr:in2", "pos": [ [ - 220.0, - 475.0 + 670.0, + 540.0 ], [ - 250.0, - 475.0 + 700.0, + 540.0 ] ], "input": { - "id": "InMem_reg", - "field": "register_out" + "id": "0x_1F", + "field": "constant_out" } }, { "type": "Wire", - "id": "from jump_merge:merge_out to merge_reg:r_in", + "id": "from +4:constant_out to pc+4:b_in", "pos": [ [ - -62.0, - 500.0 + 80.0, + 400.0 ], [ - 205.0, - 580.0 + 110.0, + 400.0 ] ], "input": { - "id": "jump_merge", - "field": "merge_out" + "id": "+4", + "field": "constant_out" } }, { "type": "Wire", - "id": "from InMem_reg:register_out to instruction_split:instruction_in", + "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", "pos": [ [ - 220.0, - 475.0 + 1520.0, + 520.0 ], [ - 239.0, - 150.0 + 1910.0, + 520.0 ] ], "input": { - "id": "InMem_reg", - "field": "register_out" + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", + "id": "from instruction_split:rt_out to mux_write_addr:in0", "pos": [ [ - 220.0, - 475.0 + 430.0, + 332.0 ], [ - 54.0, - 0.0 + 495.19995, + 332.8 + ], + [ + 494.39996, + 500.0 + ], + [ + 700.0, + 500.0 ] ], "input": { - "id": "InMem_reg", - "field": "register_out" + "id": "instruction_split", + "field": "rt_out" } }, { "type": "Wire", - "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", + "id": "from mux_b2_reg:register_out to mux_source_b:in1", "pos": [ [ - 930.0, - -40.0 + 1110.0, + 420.0 ], [ - 994.0, - 0.0 + 1230.0, + 325.0 ] ], "input": { - "id": "control_EX_reg", + "id": "mux_b2_reg", "field": "register_out" } }, + { + "type": "Mux", + "id": "mux_source_b", + "pos": [ + 1250.0, + 325.0 + ], + "select": { + "id": "control_unit_2", + "field": "alu_src_b" + }, + "m_in": [ + { + "id": "operand_b_reg", + "field": "register_out" + }, + { + "id": "mux_b2_reg", + "field": "register_out" + }, + { + "id": "mux_b3_reg", + "field": "register_out" + } + ], + "scale": 1.0 + }, { "type": "Wire", - "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", + "id": "from control_unit_2:alu_op to alu:full_add_op_in", "pos": [ [ - 1480.0, - -40.0 + 1385.0, + 13.5 ], [ - 1464.0, - 0.0 + 1390.0, + 210.0 ] ], "input": { - "id": "control_MEM_reg", - "field": "register_out" + "id": "control_unit_2", + "field": "alu_op" } }, { "type": "Wire", - "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", + "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", "pos": [ [ - 1930.0, - -40.0 + 1206.0, + 110.0 ], [ - 2010.0, - 0.0 + 1230.0, + 190.0 ] ], "input": { - "id": "control_WB_reg", - "field": "register_out" + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" } }, { - "type": "Wire", - "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", + "type": "PassThrough", + "id": "pc+4_pass", "pos": [ - [ - 301.0, - 183.33333 - ], - [ - 251.5, - 410.0 - ] + 260.0, + 370.0 ], "input": { - "id": "instruction_split", - "field": "immediate_out" + "id": "pc+4_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", + "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", "pos": [ [ - 93.33333, - 13.5 + 260.0, + 380.0 + ], + [ + 260.0, + 420.0 ], [ - 310.0, - 389.0 + 1090.0, + 420.0 ] ], "input": { - "id": "control_unit_1", - "field": "extend_select" + "id": "pc+4_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", + "id": "from pc+4_reg:register_out to pc_add_branch:a_in", "pos": [ [ - 1490.0, - 800.0 + 305.0, + 420.0 ], [ - 783.0, - 150.0 + 305.0, + 545.0 + ], + [ + 510.0, + 545.0 ] ], "input": { - "id": "reg_addr_MEM_reg", + "id": "pc+4_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from instruction_split:rs_out to data_forward_A:b_in", + "id": "from instruction_split:rt_out to data_forward_B:b_in", "pos": [ [ - 301.0, - 138.88889 + 431.0, + 286.1111 ], [ 783.0, - 170.0 + 405.0 ] ], "input": { "id": "instruction_split", - "field": "rs_out" + "field": "rt_out" } }, { "type": "Wire", - "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", + "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", "pos": [ [ - 1836.6666, - 13.5 + 1480.0, + 520.0 ], [ 783.0, - 160.0 + 385.0 ] ], "input": { - "id": "control_unit_3", - "field": "reg_write_enable" + "id": "reg_addr_MEM_reg", + "field": "register_out" } }, + { + "type": "PhysicalMem", + "id": "phys_mem", + "pos": [ + 800.0, + 600.0 + ] + }, { "type": "Wire", - "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", + "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", "pos": [ [ - 817.0, - 160.0 + 987.0, + 155.0 ], [ - 790.0, + 960.0, 195.0 ] ], "input": { - "id": "data_forward_A", - "field": "data_forward_out" + "id": "alu_forward_A", + "field": "equals_forward_out" } }, { "type": "Wire", - "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", + "id": "from mux_b3_reg:register_out to mux_source_b:in2", "pos": [ [ - 501.0, - 220.0 + 1110.0, + 465.0 ], [ - 780.0, - 215.0 + 1230.0, + 345.0 ] ], "input": { - "id": "reg_file", - "field": "rs_value_out" + "id": "mux_b3_reg", + "field": "register_out" } }, { - "type": "Wire", - "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", + "type": "PassThrough", + "id": "reg_addr_EX_pass", "pos": [ - [ - 1690.0, - 270.0 - ], - [ - 780.0, - 235.0 - ] + 1165.0, + 520.0 ], "input": { - "id": "write_back_mux", - "field": "mux_out" + "id": "reg_addr_EX_reg", + "field": "register_out" } }, { - "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", + "type": "ControlUnit", + "id": "control_unit_4", "pos": [ - [ - 1490.0, - 800.0 - ], - [ - 783.0, - 415.0 - ] + 2220.0, + 0.0 ], - "input": { - "id": "reg_addr_MEM_reg", + "a_in": { + "id": "control_WB_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from instruction_split:rt_out to data_forward_B:b_in", + "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", "pos": [ [ - 301.0, - 161.11111 + 434.0, + -40.0 ], [ - 783.0, - 435.0 + 434.0, + 0.0 + ], + [ + 464.0, + 0.0 ] ], "input": { - "id": "instruction_split", - "field": "rt_out" + "id": "InMem_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", + "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", "pos": [ [ - 1836.6666, - 13.5 + 2320.0, + 13.0 ], [ - 783.0, - 425.0 - ] - ], - "input": { - "id": "control_unit_3", - "field": "reg_write_enable" - } - }, - { - "type": "Wire", - "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", - "pos": [ + 2320.0, + 670.0 + ], [ - 817.0, - 425.0 + 600.0, + 670.0 ], [ - 790.0, - 295.0 + 600.0, + 406.0 ] ], "input": { - "id": "data_forward_B", - "field": "data_forward_out" + "id": "control_unit_4", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", + "id": "from control_unit_2:alu_src_a to mux_source_a:select", "pos": [ [ - 501.0, - 140.0 + 1218.3334, + 13.5 ], [ - 780.0, - 315.0 + 1240.0, + 170.0 ] ], "input": { - "id": "reg_file", - "field": "rt_value_out" + "id": "control_unit_2", + "field": "alu_src_a" } }, { "type": "Wire", - "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", + "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", "pos": [ [ - 1690.0, - 270.0 + 1110.0, + 110.0 ], [ - 780.0, - 335.0 + 1124.0, + 110.0 ] ], "input": { - "id": "write_back_mux", - "field": "mux_out" + "id": "zero_extend_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", + "id": "from reg_addr_EX_reg:register_out to alu_forward_B:a_in", "pos": [ [ - 1135.0, - 800.0 + 1110.0, + 520.0 ], [ 953.0, - 150.0 + 385.0 ] ], "input": { @@ -1704,218 +1463,234 @@ }, { "type": "Wire", - "id": "from instruction_split:rs_out to alu_forward_A:b_in", + "id": "from reg_addr_reg:register_out to reg_file:write_address_in", "pos": [ [ - 301.0, - 138.88889 + 1930.0, + 520.0 ], [ - 953.0, - 170.0 - ] - ], - "input": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "Wire", - "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", - "pos": [ + 1950.0, + 520.0 + ], [ - 1366.6666, - 13.5 + 1951.6001, + 642.0 ], [ - 953.0, - 162.5 + 641.60004, + 642.0 + ], + [ + 640.0, + 406.0 ] ], "input": { - "id": "control_unit_2", - "field": "reg_write_enable" + "id": "reg_addr_reg", + "field": "register_out" } }, { - "type": "Wire", - "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", + "type": "RegFile", + "id": "reg_file", "pos": [ - [ - 1233.3334, - 13.5 - ], - [ - 953.0, - 167.5 - ] + 585.0, + 275.0 ], - "input": { - "id": "control_unit_2", - "field": "mem_mode" + "rs_address_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "rt_address_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "write_address_in": { + "id": "reg_addr_reg", + "field": "register_out" + }, + "write_data_in": { + "id": "result_reg_EX", + "field": "register_out" + }, + "write_enable_in": { + "id": "control_unit_4", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", + "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", "pos": [ [ - 987.0, - 160.0 + 651.0, + 315.0 ], [ - 960.0, - 195.0 + 780.0, + 315.0 ] ], "input": { - "id": "alu_forward_A", - "field": "equals_forward_out" + "id": "reg_file", + "field": "rt_value_out" } }, { "type": "Wire", - "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", + "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", "pos": [ [ - 810.0, - 225.0 + 651.0, + 215.0 ], [ - 950.0, + 780.0, 215.0 ] ], "input": { - "id": "data_forward_A_mux", - "field": "mux_out" + "id": "reg_file", + "field": "rs_value_out" } }, { "type": "Wire", - "id": "from alu:alu_out to alu_forward_A_mux:in1", + "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", "pos": [ [ - 1420.0, - 220.0 + 1480.0, + -40.0 ], [ - 950.0, - 235.0 + 1489.0, + 0.0 ] ], "input": { - "id": "alu", - "field": "alu_out" + "id": "control_MEM_reg", + "field": "register_out" } }, { - "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to equals_operand_B_2:a_in", + "type": "Constant", + "id": "0_a_inp", "pos": [ - [ - 1135.0, - 800.0 - ], - [ - 953.0, - 415.0 - ] + 1190.0, + 210.0 ], - "input": { - "id": "reg_addr_EX_reg", - "field": "register_out" + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { "type": "Wire", - "id": "from instruction_split:rt_out to equals_operand_B_2:b_in", + "id": "from 0_a_inp:constant_out to mux_source_a:in2", "pos": [ [ - 301.0, - 161.11111 + 1190.0, + 210.0 ], [ - 953.0, - 435.0 + 1230.0, + 230.0 ] ], "input": { - "id": "instruction_split", - "field": "rt_out" + "id": "0_a_inp", + "field": "constant_out" } }, { - "type": "Wire", - "id": "from control_unit_2:reg_write_enable to equals_operand_B_2:we_in", + "type": "Mux", + "id": "mux_source_a", "pos": [ - [ - 1366.6666, - 13.5 - ], - [ - 953.0, - 427.5 - ] + 1250.0, + 210.0 ], - "input": { + "select": { "id": "control_unit_2", - "field": "reg_write_enable" - } + "field": "alu_src_a" + }, + "m_in": [ + { + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" + }, + { + "id": "operand_a_reg", + "field": "register_out" + }, + { + "id": "0_a_inp", + "field": "constant_out" + } + ], + "scale": 1.0 }, { - "type": "Wire", - "id": "from control_unit_2:mem_mode to equals_operand_B_2:load_in", + "type": "ALU", + "id": "alu", "pos": [ - [ - 1233.3334, - 13.5 - ], - [ - 953.0, - 432.5 - ] + 1400.0, + 250.0 ], - "input": { + "a_in": { + "id": "mux_source_a", + "field": "mux_out" + }, + "b_in": { + "id": "mux_source_b", + "field": "mux_out" + }, + "op_in": { "id": "control_unit_2", - "field": "mem_mode" + "field": "alu_op" } }, { "type": "Wire", - "id": "from equals_operand_B_2:equals_forward_out to alu_forward_B_mux:select", + "id": "from alu:alu_out to alu_reg:r_in", "pos": [ [ - 987.0, - 425.0 + 1420.0, + 250.0 ], [ - 960.0, - 295.0 + 1460.0, + 250.0 ] ], "input": { - "id": "equals_operand_B_2", - "field": "equals_forward_out" + "id": "alu", + "field": "alu_out" } }, { "type": "Wire", - "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", + "id": "from alu:alu_out to alu_forward_A_mux:in1", "pos": [ [ - 810.0, - 325.0 + 1420.0, + 250.0 ], [ 950.0, - 315.0 + 235.0 ] ], "input": { - "id": "data_forward_B_mux", - "field": "mux_out" + "id": "alu", + "field": "alu_out" } }, { @@ -1924,7 +1699,7 @@ "pos": [ [ 1420.0, - 220.0 + 250.0 ], [ 950.0, @@ -1938,830 +1713,1254 @@ }, { "type": "Wire", - "id": "from instruction_split:op_out to branch:branch_op_in", + "id": "from mux_source_a:mux_out to alu:full_add_a_in", "pos": [ [ - 301.0, - 94.44444 + 1260.0, + 210.0 ], [ - 1040.0, - 275.0 + 1380.0, + 220.0 ] ], "input": { - "id": "instruction_split", - "field": "op_out" + "id": "mux_source_a", + "field": "mux_out" } }, { "type": "Wire", - "id": "from instruction_split:rt_out to branch:branch_rt_in", + "id": "from pc:register_out to jump_merge:merge_instr_addr_in", "pos": [ [ - 301.0, - 161.11111 + 30.0, + 465.0 ], [ - 1040.0, - 275.0 + 180.0, + 465.0 + ], + [ + 180.0, + 517.0 ] ], "input": { - "id": "instruction_split", - "field": "rt_out" + "id": "pc", + "field": "register_out" } }, { "type": "Wire", - "id": "from instruction_split:funct_out to branch:branch_funct_in", + "id": "from pc:register_out to pc+4:a_in", "pos": [ [ - 301.0, - 116.666664 + 30.0, + 390.0 ], [ - 1040.0, - 275.0 + 30.0, + 360.0 + ], + [ + 110.0, + 360.0 ] ], "input": { - "id": "instruction_split", - "field": "funct_out" + "id": "pc", + "field": "register_out" } }, { - "type": "Wire", - "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", + "type": "InstrMem", + "id": "instr_mem", "pos": [ - [ - 980.0, - 225.0 - ], - [ - 1040.0, - 275.0 - ] + 45.0, + 585.0 ], - "input": { - "id": "alu_forward_A_mux", - "field": "mux_out" + "pc": { + "id": "pc", + "field": "register_out" + }, + "phys_mem_id": "phys_mem", + "regfile_id": "reg_file", + "mem_view": { + "visible": false, + "title": "instruction memory view", + "id": "instr_mem", + "row_offset": 0, + "max_rows": 1024, + "big_endian": true, + "format": "HexAndMips", + "show_settings": { + "symbols": true, + "sections": false, + "program_counter": false, + "registers": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + true + ] + }, + "register_values": [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 + ], + "dynamic_symbols": { + "PC_IM": [ + 0, + true + ] + }, + "break_points": [] } }, { "type": "Wire", - "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", + "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", "pos": [ [ - 980.0, - 325.0 + 85.0, + 530.0 ], [ - 1040.0, - 275.0 + 140.0, + 530.0 ] ], "input": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "id": "instr_mem", + "field": "instruction" } }, { "type": "Wire", - "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", + "id": "from instr_mem:instruction to InMem_reg:r_in", "pos": [ [ - 250.0, + 85.0, + 551.5 + ], + [ + 85.0, 475.0 ], [ - 910.0, - -40.0 + 230.0, + 475.0 ] ], "input": { - "id": "InMem_pass", - "field": "pass_through_out" + "id": "instr_mem", + "field": "instruction" } }, { - "type": "Wire", - "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", + "type": "Add", + "id": "pc+4", "pos": [ - [ - 930.0, - -40.0 - ], - [ - 960.0, - -40.0 - ] + 130.0, + 380.0 ], - "input": { - "id": "control_EX_reg", + "a_in": { + "id": "pc", "field": "register_out" - } + }, + "b_in": { + "id": "+4", + "field": "constant_out" + }, + "scale": 1.0 }, { "type": "Wire", - "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", + "id": "from pc+4:add_out to mux_jump_merge:in3", "pos": [ [ - 301.0, - 72.22222 + 150.0, + 380.0 ], [ - 1090.0, - 110.0 + 170.0, + 380.0 + ], + [ + 170.0, + 455.0 + ], + [ + -80.0, + 455.0 + ], + [ + -80.0, + 420.0 + ], + [ + -74.0, + 420.0 ] ], "input": { - "id": "instruction_split", - "field": "shamt_out" + "id": "pc+4", + "field": "add_out" } }, { "type": "Wire", - "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", + "id": "from pc+4:add_out to pc+4_reg:r_in", "pos": [ [ - 980.0, - 225.0 + 150.0, + 380.0 ], [ - 1090.0, - 215.0 + 230.0, + 380.0 ] ], "input": { - "id": "alu_forward_A_mux", - "field": "mux_out" + "id": "pc+4", + "field": "add_out" } }, { "type": "Wire", - "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", + "id": "from pc:register_out to instr_mem:pc", "pos": [ [ - 980.0, - 325.0 + 10.0, + 390.0 ], [ - 1090.0, - 325.0 + 30.0, + 390.0 + ], + [ + 31.0, + 551.5 ] ], "input": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "id": "pc", + "field": "register_out" } }, { - "type": "Wire", - "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", + "type": "JumpMerge", + "id": "jump_merge", "pos": [ - [ - 1110.0, - 325.0 - ], - [ - 1140.0, - 325.0 - ] + 180.0, + 530.0 ], - "input": { - "id": "operand_b_reg", + "instr_addr_in": { + "id": "pc", "field": "register_out" + }, + "jump_addr_in": { + "id": "instr_mem", + "field": "instruction" } }, { "type": "Wire", - "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", + "id": "from jump_merge:merge_out to merge_reg:r_in", "pos": [ [ - 240.0, - 370.0 + 180.0, + 544.0 ], [ - 1090.0, - 550.0 + 180.0, + 580.0 + ], + [ + 230.0, + 580.0 ] ], "input": { - "id": "pc+4_pass", - "field": "pass_through_out" + "id": "jump_merge", + "field": "merge_out" } }, { "type": "Wire", - "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", + "id": "from mux_source_b:mux_out to alu:full_add_b_in", "pos": [ [ - 368.5, - 410.0 + 1260.0, + 325.0 ], [ - 1090.0, - 625.0 + 1380.0, + 280.0 ] ], "input": { - "id": "signzero_extend", - "field": "sz_out" + "id": "mux_source_b", + "field": "mux_out" } }, { "type": "Wire", - "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", + "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", "pos": [ [ - 570.0, - 500.0 + 1165.0, + 520.0 ], [ - 1115.0, - 800.0 + 1460.0, + 520.0 ] ], "input": { - "id": "mux_write_addr", - "field": "mux_out" + "id": "reg_addr_EX_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", + "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", "pos": [ [ - 1135.0, - 800.0 + 1930.0, + -40.0 ], [ - 1165.0, - 800.0 + 2014.0, + 0.0 ] ], "input": { - "id": "reg_addr_EX_reg", + "id": "control_WB_reg", "field": "register_out" } }, { - "type": "Wire", - "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", + "type": "ControlUnit", + "id": "control_unit_3", "pos": [ - [ - 1110.0, - 110.0 - ], - [ - 1124.0, - 110.0 - ] + 1695.0, + 0.0 ], - "input": { - "id": "zero_extend_reg", + "a_in": { + "id": "control_MEM_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_2:alu_src_a to mux_source_a:select", + "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", "pos": [ [ - 1133.3334, + 1690.0, 13.5 ], [ - 1240.0, - 170.0 + 1690.0, + 551.5 ] ], "input": { - "id": "control_unit_2", - "field": "alu_src_a" + "id": "control_unit_3", + "field": "mem_mode" } }, { "type": "Wire", - "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", + "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", "pos": [ [ - 1206.0, - 110.0 + 820.0, + 155.0 ], [ - 1230.0, - 190.0 + 820.0, + 395.0 + ], + [ + 808.5, + 395.0 ] ], "input": { - "id": "zero_extend_for_shamt", - "field": "zero_extend_out" + "id": "control_unit_3", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from operand_a_reg:register_out to mux_source_a:in1", + "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", "pos": [ [ - 1110.0, - 215.0 + 1660.0, + 13.5 ], [ - 1230.0, - 210.0 + 1660.0, + 551.5 ] ], "input": { - "id": "operand_a_reg", - "field": "register_out" + "id": "control_unit_3", + "field": "mem_write_enable" } }, { "type": "Wire", - "id": "from 0_a_inp:constant_out to mux_source_a:in2", + "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", "pos": [ [ - 600.0, - 50.0 + 1540.0, + 13.5 ], [ - 1230.0, - 230.0 + 1540.0, + 80.0 + ], + [ + 820.0, + 80.0 + ], + [ + 820.0, + 155.0 + ], + [ + 809.0, + 155.0 ] ], "input": { - "id": "0_a_inp", - "field": "constant_out" + "id": "control_unit_3", + "field": "reg_write_enable" } }, { - "type": "Wire", - "id": "from control_unit_2:alu_src_b to mux_source_b:select", + "type": "DataForward", + "id": "data_forward_B", "pos": [ - [ - 1166.6666, - 13.5 - ], - [ - 1240.0, - 285.0 - ] + 800.0, + 395.0 ], - "input": { - "id": "control_unit_2", - "field": "alu_src_b" + "a_in": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "we_in": { + "id": "control_unit_3", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from operand_b_reg:register_out to mux_source_b:in0", + "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", "pos": [ [ - 1110.0, - 325.0 + 817.0, + 395.0 ], [ - 1230.0, - 305.0 + 790.0, + 295.0 ] ], "input": { - "id": "operand_b_reg", - "field": "register_out" + "id": "data_forward_B", + "field": "data_forward_out" } }, { - "type": "Wire", - "id": "from mux_b2_reg:register_out to mux_source_b:in1", + "type": "DataForward", + "id": "data_forward_A", "pos": [ - [ - 1110.0, - 550.0 - ], - [ - 1230.0, - 325.0 - ] + 800.0, + 155.0 ], - "input": { - "id": "mux_b2_reg", + "a_in": { + "id": "reg_addr_MEM_reg", "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "we_in": { + "id": "control_unit_3", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from mux_b3_reg:register_out to mux_source_b:in2", + "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", "pos": [ [ - 1110.0, - 625.0 + 817.0, + 155.0 ], [ - 1230.0, - 345.0 + 790.0, + 195.0 ] ], "input": { - "id": "mux_b3_reg", - "field": "register_out" + "id": "data_forward_A", + "field": "data_forward_out" } }, { - "type": "Wire", - "id": "from mux_source_a:mux_out to alu:full_add_a_in", + "type": "DataMem", + "id": "data_mem", "pos": [ - [ - 1260.0, - 210.0 + 1660.0, + 585.0 + ], + "address_input": { + "id": "alu_reg", + "field": "register_out" + }, + "data_input": { + "id": "data_MEM_reg", + "field": "register_out" + }, + "op_input": { + "id": "control_unit_3", + "field": "mem_mode" + }, + "write_enable_input": { + "id": "control_unit_3", + "field": "mem_write_enable" + }, + "phys_mem_id": "phys_mem", + "regfile_id": "reg_file", + "mem_view": { + "visible": false, + "title": "Data memory view", + "id": "data_mem", + "row_offset": 512, + "max_rows": 1024, + "big_endian": true, + "format": "ByteAndUtf8", + "show_settings": { + "symbols": true, + "sections": false, + "program_counter": false, + "registers": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false + ] + }, + "register_values": [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 ], - [ - 1380.0, - 190.0 + "dynamic_symbols": { + "DM_ADRS": [ + 0, + false + ] + }, + "break_points": [ + 4176 ] - ], - "input": { - "id": "mux_source_a", - "field": "mux_out" } }, { "type": "Wire", - "id": "from mux_source_b:mux_out to alu:full_add_b_in", + "id": "from data_mem:data_out to write_back_mux:in1", "pos": [ [ - 1260.0, - 325.0 + 1726.0, + 585.0 ], [ - 1380.0, - 250.0 + 1750.0, + 585.0 + ], + [ + 1750.0, + 280.0 + ], + [ + 1780.0, + 280.0 ] ], "input": { - "id": "mux_source_b", - "field": "mux_out" + "id": "data_mem", + "field": "data_out" } }, { "type": "Wire", - "id": "from control_unit_2:alu_op to alu:full_add_op_in", + "id": "from control_unit_3:reg_write_src to write_back_mux:select", "pos": [ [ - 1300.0, + 1790.0, 13.5 ], [ - 1390.0, - 180.0 + 1790.0, + 240.0 ] ], "input": { - "id": "control_unit_2", - "field": "alu_op" + "id": "control_unit_3", + "field": "reg_write_src" } }, + { + "type": "Mux", + "id": "write_back_mux", + "pos": [ + 1800.0, + 270.0 + ], + "select": { + "id": "control_unit_3", + "field": "reg_write_src" + }, + "m_in": [ + { + "id": "alu_reg", + "field": "register_out" + }, + { + "id": "data_mem", + "field": "data_out" + } + ], + "scale": 1.0 + }, { "type": "Wire", - "id": "from alu_reg:register_out to data_mem:data_mem_address_in", + "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", "pos": [ [ - 1480.0, - 250.0 + 740.0, + 335.0 ], [ - 1630.0, - 526.5 + 780.0, + 335.0 ] ], "input": { - "id": "alu_reg", - "field": "register_out" + "id": "write_back_mux", + "field": "mux_out" } }, + { + "type": "Mux", + "id": "data_forward_A_mux", + "pos": [ + 800.0, + 225.0 + ], + "select": { + "id": "data_forward_A", + "field": "data_forward_out" + }, + "m_in": [ + { + "id": "reg_file", + "field": "rs_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, { "type": "Wire", - "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", + "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", "pos": [ [ - 1703.3334, - 13.5 + 810.0, + 225.0 ], [ - 1690.0, - 526.5 + 950.0, + 215.0 ] ], "input": { - "id": "control_unit_3", - "field": "mem_mode" + "id": "data_forward_A_mux", + "field": "mux_out" } }, { - "type": "Wire", - "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", + "type": "Mux", + "id": "alu_forward_A_mux", "pos": [ - [ - 1480.0, - 565.0 - ], - [ - 1594.0, - 560.0 - ] + 970.0, + 225.0 + ], + "select": { + "id": "alu_forward_A", + "field": "equals_forward_out" + }, + "m_in": [ + { + "id": "data_forward_A_mux", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" + } ], - "input": { - "id": "data_MEM_reg", - "field": "register_out" - } + "scale": 1.0 }, { "type": "Wire", - "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", + "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", "pos": [ [ - 1670.0, - 13.5 + 980.0, + 225.0 ], [ - 1660.0, - 526.5 + 1090.0, + 215.0 ] ], "input": { - "id": "control_unit_3", - "field": "mem_write_enable" + "id": "alu_forward_A_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", + "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", "pos": [ [ - 960.0, - -40.0 + 980.0, + 225.0 ], [ - 1460.0, - -40.0 + 1040.0, + 275.0 ] ], "input": { - "id": "control_EX_pass", - "field": "pass_through_out" + "id": "alu_forward_A_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", + "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", "pos": [ [ - 1480.0, - -40.0 + 980.0, + 225.0 ], [ - 1510.0, - -40.0 + 1000.0, + 225.0 + ], + [ + 1000.0, + 40.0 + ], + [ + -94.0, + 40.0 + ], + [ + -94.0, + 380.0 + ], + [ + -74.0, + 380.0 ] ], "input": { - "id": "control_MEM_reg", - "field": "register_out" + "id": "alu_forward_A_mux", + "field": "mux_out" } }, { - "type": "Wire", - "id": "from alu:alu_out to alu_reg:r_in", + "type": "Mux", + "id": "data_forward_B_mux", "pos": [ - [ - 1420.0, - 220.0 - ], - [ - 1460.0, - 250.0 - ] + 800.0, + 325.0 ], - "input": { - "id": "alu", - "field": "alu_out" - } + "select": { + "id": "data_forward_B", + "field": "data_forward_out" + }, + "m_in": [ + { + "id": "reg_file", + "field": "rt_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 }, { "type": "Wire", - "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", + "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", "pos": [ [ - 1140.0, + 810.0, 325.0 ], [ - 1460.0, - 565.0 + 950.0, + 315.0 ] ], "input": { - "id": "operand_b_pass", - "field": "pass_through_out" + "id": "data_forward_B_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", + "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", "pos": [ [ - 1165.0, - 800.0 + 1830.0, + 270.0 + ], + [ + 1830.0, + 440.0 + ], + [ + 740.0, + 440.0 ], [ - 1470.0, - 800.0 + 740.0, + 235.0 + ], + [ + 780.0, + 235.0 ] ], "input": { - "id": "reg_addr_EX_pass", - "field": "pass_through_out" + "id": "write_back_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", + "id": "from write_back_mux:mux_out to result_reg_EX:r_in", "pos": [ [ - 1490.0, - 800.0 + 1810.0, + 270.0 ], [ - 1520.0, - 800.0 + 1910.0, + 270.0 ] ], "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" + "id": "write_back_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from control_unit_3:reg_write_src to write_back_mux:select", + "id": "from instruction_split:rs_out to alu_forward_A:b_in", "pos": [ [ - 1803.3334, - 13.5 + 800.0, + 120.0 ], [ - 1670.0, - 240.0 + 970.0, + 120.0 + ], + [ + 970.0, + 142.0 ] ], "input": { - "id": "control_unit_3", - "field": "reg_write_src" + "id": "instruction_split", + "field": "rs_out" } }, { - "type": "Wire", - "id": "from alu_reg:register_out to write_back_mux:in0", + "type": "ControlUnit", + "id": "control_unit_1", "pos": [ - [ - 1480.0, - 250.0 - ], - [ - 1660.0, - 260.0 - ] + 670.0, + 0.0 ], - "input": { - "id": "alu_reg", + "a_in": { + "id": "InMem_reg", "field": "register_out" } }, { - "type": "Wire", - "id": "from data_mem:data_out to write_back_mux:in1", + "type": "SignZeroExtend", + "id": "signzero_extend", "pos": [ - [ - 1726.0, - 560.0 - ], - [ - 1660.0, - 280.0 - ] + 400.0, + 475.0 ], - "input": { - "id": "data_mem", - "field": "data_out" + "signzero_signal_in": { + "id": "instruction_split", + "field": "immediate_out" + }, + "signzero_ctrl_in": { + "id": "control_unit_1", + "field": "extend_select" } }, { "type": "Wire", - "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", + "id": "from signzero_extend:sz_out to branch_shift:shift_in", "pos": [ [ - 1510.0, - -40.0 + 458.5, + 475.0 ], [ - 1910.0, - -40.0 + 468.5, + 475.0 + ], + [ + 468.5, + 560.0 + ], + [ + 356.0, + 560.0 + ], + [ + 356.0, + 585.0 + ], + [ + 366.5, + 585.0 ] ], "input": { - "id": "control_MEM_pass", - "field": "pass_through_out" + "id": "signzero_extend", + "field": "sz_out" } }, { "type": "Wire", - "id": "from write_back_mux:mux_out to result_reg_EX:r_in", + "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", "pos": [ [ - 1690.0, - 270.0 + 469.0, + 475.0 ], [ - 1910.0, - 270.0 + 1090.0, + 475.0 ] ], "input": { - "id": "write_back_mux", - "field": "mux_out" + "id": "signzero_extend", + "field": "sz_out" } }, + { + "type": "ShiftConst", + "id": "branch_shift", + "pos": [ + 400.0, + 585.0 + ], + "signal_in": { + "id": "signzero_extend", + "field": "sz_out" + }, + "shift_by": 2 + }, + { + "type": "Add", + "id": "pc_add_branch", + "pos": [ + 530.0, + 565.0 + ], + "a_in": { + "id": "pc+4_reg", + "field": "register_out" + }, + "b_in": { + "id": "branch_shift", + "field": "shift_left_const_out" + }, + "scale": 1.0 + }, { "type": "Wire", - "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", + "id": "from pc_add_branch:add_out to mux_jump_merge:in0", "pos": [ [ - 1520.0, - 800.0 + 550.0, + 565.0 + ], + [ + 560.0, + 565.0 + ], + [ + 561.0, + 640.0 + ], + [ + -114.0, + 640.0 + ], + [ + -114.0, + 360.0 ], [ - 1910.0, - 800.0 + -74.0, + 360.0 ] ], "input": { - "id": "reg_addr_MEM_pass", - "field": "pass_through_out" + "id": "pc_add_branch", + "field": "add_out" } }, { "type": "Wire", - "id": "from signzero_extend:sz_out to branch_shift:shift_in", + "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", "pos": [ [ - 368.5, - 410.0 + 433.5, + 585.0 ], [ - 346.5, - 460.0 + 510.0, + 585.0 ] ], "input": { - "id": "signzero_extend", - "field": "sz_out" + "id": "branch_shift", + "field": "shift_left_const_out" } }, + { + "type": "Mux", + "id": "mux_write_addr", + "pos": [ + 720.0, + 520.0 + ], + "select": { + "id": "control_unit_1", + "field": "reg_dest" + }, + "m_in": [ + { + "id": "instruction_split", + "field": "rt_out" + }, + { + "id": "instruction_split", + "field": "rd_out" + }, + { + "id": "0x_1F", + "field": "constant_out" + } + ], + "scale": 1.0 + }, { "type": "Wire", - "id": "from pc+4_reg:register_out to pc_add_branch:a_in", + "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", "pos": [ [ - 210.0, - 370.0 + 980.0, + 520.0 ], [ - 400.0, - 420.0 + 1090.0, + 520.0 ] ], "input": { - "id": "pc+4_reg", - "field": "register_out" + "id": "mux_write_addr", + "field": "mux_out" } }, { "type": "Wire", - "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", + "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", "pos": [ [ - 413.5, - 460.0 + 480.0, + 13.5 + ], + [ + 480.0, + 80.0 + ], + [ + 340.0, + 80.0 + ], + [ + 340.0, + 440.0 + ], + [ + 400.0, + 440.0 ], [ 400.0, - 460.0 + 454.0 ] ], "input": { - "id": "branch_shift", - "field": "shift_left_const_out" + "id": "control_unit_1", + "field": "extend_select" } }, { @@ -2769,12 +2968,12 @@ "id": "from control_unit_1:reg_dest to mux_write_addr:select", "pos": [ [ - 160.0, - 13.5 + 710.0, + 14.0 ], [ - 550.0, - 460.0 + 710.0, + 480.0 ] ], "input": { @@ -2784,146 +2983,242 @@ }, { "type": "Wire", - "id": "from instruction_split:rt_out to mux_write_addr:in0", + "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", "pos": [ [ - 301.0, - 161.11111 + 1480.0, + -40.0 ], [ - 540.0, - 480.0 + 1510.0, + -40.0 ] ], "input": { + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "AluForward", + "id": "alu_forward_B", + "pos": [ + 970.0, + 395.0 + ], + "a_in": { + "id": "reg_addr_EX_reg", + "field": "register_out" + }, + "b_in": { "id": "instruction_split", "field": "rt_out" + }, + "we_in": { + "id": "control_unit_2", + "field": "reg_write_enable" + }, + "load_in": { + "id": "control_unit_2", + "field": "mem_mode" } }, + { + "type": "Mux", + "id": "alu_forward_B_mux", + "pos": [ + 970.0, + 325.0 + ], + "select": { + "id": "alu_forward_B", + "field": "equals_forward_out" + }, + "m_in": [ + { + "id": "data_forward_B_mux", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" + } + ], + "scale": 1.0 + }, { "type": "Wire", - "id": "from instruction_split:rd_out to mux_write_addr:in1", + "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", "pos": [ [ - 301.0, - 205.55556 + 980.0, + 325.0 ], [ - 540.0, - 500.0 + 1040.0, + 275.0 ] ], "input": { - "id": "instruction_split", - "field": "rd_out" + "id": "alu_forward_B_mux", + "field": "mux_out" } }, { - "type": "Wire", - "id": "from 0x_1F:constant_out to mux_write_addr:in2", + "type": "BranchLogic", + "id": "branch", "pos": [ - [ - 500.0, - 510.0 - ], - [ - 540.0, - 520.0 - ] + 1040.0, + 275.0 ], - "input": { - "id": "0x_1F", - "field": "constant_out" + "op_in": { + "id": "instruction_split", + "field": "op_out" + }, + "rt_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "funct_in": { + "id": "instruction_split", + "field": "funct_out" + }, + "rs_value": { + "id": "alu_forward_A_mux", + "field": "mux_out" + }, + "rt_value": { + "id": "alu_forward_B_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from instruction_split:rs_out to reg_file:rs_address_in", + "id": "from branch:branch_out to mux_jump_merge:select", "pos": [ [ - 301.0, - 138.88889 + 1040.0, + 262.0 + ], + [ + 1040.0, + 60.0 + ], + [ + -64.0, + 60.0 ], [ - 435.0, - 49.0 + -64.0, + 340.0 ] ], "input": { - "id": "instruction_split", - "field": "rs_out" + "id": "branch", + "field": "branch_out" } }, + { + "type": "Mux", + "id": "mux_jump_merge", + "pos": [ + -54.0, + 390.0 + ], + "select": { + "id": "branch", + "field": "branch_out" + }, + "m_in": [ + { + "id": "pc_add_branch", + "field": "add_out" + }, + { + "id": "alu_forward_A_mux", + "field": "mux_out" + }, + { + "id": "merge_reg", + "field": "register_out" + }, + { + "id": "pc+4", + "field": "add_out" + } + ], + "scale": 1.0 + }, { "type": "Wire", - "id": "from instruction_split:rt_out to reg_file:rt_address_in", + "id": "from mux_jump_merge:mux_out to pc:r_in", "pos": [ [ - 301.0, - 161.11111 + -44.0, + 390.0 ], [ - 435.0, - 311.0 + -10.0, + 390.0 ] ], "input": { - "id": "instruction_split", - "field": "rt_out" + "id": "mux_jump_merge", + "field": "mux_out" } }, { "type": "Wire", - "id": "from reg_addr_reg:register_out to reg_file:write_address_in", + "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", "pos": [ [ - 1930.0, - 800.0 + 980.0, + 325.0 ], [ - 369.0, - 270.0 + 1090.0, + 325.0 ] ], "input": { - "id": "reg_addr_reg", - "field": "register_out" + "id": "alu_forward_B_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from result_reg_EX:register_out to reg_file:write_data_in", + "id": "from alu_forward_B:equals_forward_out to alu_forward_B_mux:select", "pos": [ [ - 1930.0, - 270.0 + 987.0, + 395.0 ], [ - 369.0, - 290.0 + 960.0, + 295.0 ] ], "input": { - "id": "result_reg_EX", - "field": "register_out" + "id": "alu_forward_B", + "field": "equals_forward_out" } }, { "type": "Wire", - "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", + "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", "pos": [ [ - 2382.6667, - 13.5 + 250.0, + 380.0 ], [ - 369.0, - 250.0 + 260.0, + 380.0 ] ], "input": { - "id": "control_unit_4", - "field": "reg_write_enable" + "id": "pc+4_reg", + "field": "register_out" } } ] From de5bcdd51b8b1065c4808d35e9cdcf3d3e608ba3 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Fri, 11 Oct 2024 17:30:12 +0200 Subject: [PATCH 13/18] wires are nice --- mips-lib/mips_pipe.json | 3666 +++++++++++++++++++++------------------ 1 file changed, 1964 insertions(+), 1702 deletions(-) diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index 30bcbfd..cb025a0 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -2,110 +2,110 @@ "store": [ { "type": "Register", - "id": "control_MEM_reg", + "id": "pc+4_reg", "pos": [ - 1470.0, - -40.0 + 240.0, + 380.0 ], "r_in": { - "id": "control_EX_pass", - "field": "pass_through_out" + "id": "pc+4", + "field": "add_out" } }, { "type": "Register", - "id": "operand_b_reg", + "id": "mux_b2_reg", "pos": [ 1100.0, - 325.0 + 420.0 ], "r_in": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "id": "pc+4_pass", + "field": "pass_through_out" } }, { "type": "Register", - "id": "InMem_reg", + "id": "pc", "pos": [ - 240.0, - 475.0 + 0.0, + 390.0 ], "r_in": { - "id": "instr_mem", - "field": "instruction" + "id": "mux_jump_merge", + "field": "mux_out" } }, { "type": "Register", - "id": "operand_a_reg", + "id": "zero_extend_reg", "pos": [ 1100.0, - 215.0 + 110.0 ], "r_in": { - "id": "alu_forward_A_mux", - "field": "mux_out" + "id": "instruction_split", + "field": "shamt_out" } }, { "type": "Register", - "id": "control_WB_reg", + "id": "reg_addr_reg", "pos": [ 1920.0, - -40.0 + 520.0 ], "r_in": { - "id": "control_MEM_pass", + "id": "reg_addr_MEM_pass", "field": "pass_through_out" } }, { "type": "Register", - "id": "alu_reg", + "id": "operand_a_reg", "pos": [ - 1470.0, - 250.0 + 1100.0, + 215.0 ], "r_in": { - "id": "alu", - "field": "alu_out" + "id": "alu_forward_A_mux", + "field": "mux_out" } }, { "type": "Register", - "id": "reg_addr_MEM_reg", + "id": "control_MEM_reg", "pos": [ 1470.0, - 520.0 + -40.0 ], "r_in": { - "id": "reg_addr_EX_pass", + "id": "control_EX_pass", "field": "pass_through_out" } }, { "type": "Register", - "id": "zero_extend_reg", + "id": "mux_b3_reg", "pos": [ 1100.0, - 110.0 + 475.0 ], "r_in": { - "id": "instruction_split", - "field": "shamt_out" + "id": "signzero_extend", + "field": "sz_out" } }, { "type": "Register", - "id": "control_EX_reg", + "id": "result_reg_EX", "pos": [ - 1100.0, - -40.0 + 1920.0, + 270.0 ], "r_in": { - "id": "InMem_pass", - "field": "pass_through_out" + "id": "write_back_mux", + "field": "mux_out" } }, { @@ -122,1678 +122,1913 @@ }, { "type": "Register", - "id": "result_reg_EX", + "id": "operand_b_reg", "pos": [ - 1920.0, - 270.0 + 1100.0, + 325.0 ], "r_in": { - "id": "write_back_mux", + "id": "alu_forward_B_mux", "field": "mux_out" } }, { "type": "Register", - "id": "data_MEM_reg", + "id": "control_EX_reg", "pos": [ - 1470.0, - 585.0 + 1100.0, + -40.0 ], "r_in": { - "id": "operand_b_pass", + "id": "InMem_pass", "field": "pass_through_out" } }, { "type": "Register", - "id": "merge_reg", + "id": "reg_addr_MEM_reg", "pos": [ - 240.0, - 580.0 + 1470.0, + 520.0 ], "r_in": { - "id": "jump_merge", - "field": "merge_out" + "id": "reg_addr_EX_pass", + "field": "pass_through_out" } }, { "type": "Register", - "id": "mux_b3_reg", + "id": "InMem_reg", "pos": [ - 1100.0, + 240.0, 475.0 ], "r_in": { - "id": "signzero_extend", - "field": "sz_out" + "id": "instr_mem", + "field": "instruction" } }, { "type": "Register", - "id": "mux_b2_reg", + "id": "alu_reg", "pos": [ - 1100.0, - 420.0 + 1470.0, + 250.0 ], "r_in": { - "id": "pc+4_pass", - "field": "pass_through_out" + "id": "alu", + "field": "alu_out" } }, { "type": "Register", - "id": "pc+4_reg", + "id": "merge_reg", "pos": [ 240.0, - 380.0 + 580.0 ], "r_in": { - "id": "pc+4", - "field": "add_out" + "id": "jump_merge", + "field": "merge_out" } }, { "type": "Register", - "id": "reg_addr_reg", + "id": "data_MEM_reg", "pos": [ - 1920.0, - 520.0 + 1470.0, + 585.0 ], "r_in": { - "id": "reg_addr_MEM_pass", + "id": "operand_b_pass", "field": "pass_through_out" } }, { "type": "Register", - "id": "pc", + "id": "control_WB_reg", "pos": [ - 0.0, - 390.0 + 1920.0, + -40.0 ], "r_in": { - "id": "mux_jump_merge", - "field": "mux_out" + "id": "control_MEM_pass", + "field": "pass_through_out" + } + }, + { + "type": "Constant", + "id": "+4", + "pos": [ + 80.0, + 400.0 + ], + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { "type": "Wire", - "id": "from operand_b_reg:register_out to mux_source_b:in0", + "id": "from pc:register_out to instr_mem:pc", "pos": [ [ - 1110.0, - 325.0 + 10.0, + 390.0 ], [ - 1230.0, - 305.0 + 30.0, + 390.0 + ], + [ + 31.0, + 551.5 ] ], "input": { - "id": "operand_b_reg", + "id": "pc", "field": "register_out" } }, { "type": "Wire", - "id": "from InMem_reg:register_out to instruction_split:instruction_in", + "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", "pos": [ [ - 279.0, - 275.0 + 1110.0, + 110.0 ], [ - 359.0, - 275.0 + 1124.0, + 110.0 ] ], "input": { - "id": "InMem_reg", + "id": "zero_extend_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", + "id": "from mux_b2_reg:register_out to mux_source_b:in1", "pos": [ [ - 250.0, - 475.0 + 1110.0, + 420.0 ], [ - 250.0, - 475.0 + 1160.0, + 420.0 + ], + [ + 1160.0, + 325.0 + ], + [ + 1230.0, + 325.0 ] ], "input": { - "id": "InMem_reg", + "id": "mux_b2_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", + "id": "from reg_addr_reg:register_out to reg_file:write_address_in", "pos": [ [ - 1480.0, + 1930.0, 520.0 ], [ - 1520.0, + 1950.0, 520.0 + ], + [ + 1951.6001, + 642.0 + ], + [ + 641.60004, + 642.0 + ], + [ + 640.0, + 406.0 ] ], "input": { - "id": "reg_addr_MEM_reg", + "id": "reg_addr_reg", "field": "register_out" } }, { - "type": "PassThrough", - "id": "InMem_pass", + "type": "ZeroExtend", + "id": "zero_extend_for_shamt", "pos": [ - 250.0, - 475.0 + 1165.0, + 110.0 ], - "input": { - "id": "InMem_reg", + "signal_in": { + "id": "zero_extend_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", + "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", "pos": [ [ - 250.0, - 475.0 + 1206.0, + 110.0 ], [ - 280.0, - 475.0 + 1220.0, + 110.0 ], [ - 280.0, - -40.0 + 1220.0, + 190.0 ], [ - 1090.0, - -40.0 + 1230.0, + 190.0 ] ], "input": { - "id": "InMem_pass", - "field": "pass_through_out" - } - }, - { - "type": "ZeroExtend", - "id": "zero_extend_for_shamt", - "pos": [ - 1165.0, - 110.0 - ], - "signal_in": { - "id": "zero_extend_reg", - "field": "register_out" - } - }, - { - "type": "Constant", - "id": "+4", - "pos": [ - 80.0, - 400.0 - ], - "value": { - "data": { - "Data": 4 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" } }, { - "type": "PassThrough", - "id": "control_EX_pass", + "type": "ControlUnit", + "id": "control_unit_3", "pos": [ - 1140.0, - -40.0 + 1695.0, + 0.0 ], - "input": { - "id": "control_EX_reg", + "a_in": { + "id": "control_MEM_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", + "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", "pos": [ [ - 1140.0, - -40.0 + 1690.0, + 13.5 ], [ - 1460.0, - -40.0 + 1690.0, + 551.5 ] ], "input": { - "id": "control_EX_pass", - "field": "pass_through_out" - } + "id": "control_unit_3", + "field": "mem_mode" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", + "id": "from control_unit_3:reg_write_src to write_back_mux:select", "pos": [ [ - 1110.0, - -40.0 + 1790.0, + 13.5 ], [ - 1140.0, - -40.0 + 1790.0, + 240.0 ] ], "input": { - "id": "control_EX_reg", - "field": "register_out" - } + "id": "control_unit_3", + "field": "reg_write_src" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { - "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", + "type": "PassThrough", + "id": "control_MEM_pass", "pos": [ - [ - 1110.0, - 520.0 - ], - [ - 1165.0, - 520.0 - ] + 1510.0, + -40.0 ], "input": { - "id": "reg_addr_EX_reg", + "id": "control_MEM_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", + "id": "from operand_a_reg:register_out to mux_source_a:in1", "pos": [ [ 1110.0, - 520.0 + 215.0 + ], + [ + 1140.0, + 215.0 + ], + [ + 1140.0, + 210.0 ], [ - 953.0, - 145.0 + 1230.0, + 210.0 ] ], "input": { - "id": "reg_addr_EX_reg", + "id": "operand_a_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from result_reg_EX:register_out to reg_file:write_data_in", + "id": "from reg_addr_EX_reg:register_out to alu_forward_B:a_in", "pos": [ [ - 1930.0, - 270.0 + 1130.0, + 520.0 ], [ - 1970.0, - 270.0 + 1130.0, + 497.0 ], [ - 1970.0, - 655.0 + 930.0, + 497.0 ], [ - 620.0, - 655.0 + 930.0, + 395.0 ], [ - 620.0, - 406.0 + 960.0, + 395.0 ] ], "input": { - "id": "result_reg_EX", + "id": "reg_addr_EX_reg", "field": "register_out" } }, { - "type": "Wire", - "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", + "type": "PassThrough", + "id": "reg_addr_EX_pass", "pos": [ - [ - 1110.0, - -40.0 - ], - [ - 1079.0, - 0.0 - ] + 1165.0, + 520.0 ], "input": { - "id": "control_EX_reg", + "id": "reg_addr_EX_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", + "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", "pos": [ [ - 1480.0, + 1110.0, 520.0 ], [ - 783.0, - 145.0 + 1165.0, + 520.0 ] ], "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" - } - }, - { - "type": "InstrSplit", - "id": "instruction_split", - "pos": [ - 400.0, - 275.0 - ], - "instruction_in": { - "id": "InMem_reg", + "id": "reg_addr_EX_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from instruction_split:rs_out to data_forward_A:b_in", - "pos": [ - [ - 585.0, - 120.0 - ], - [ - 800.0, - 120.0 - ], - [ - 800.0, - 142.0 - ] - ], - "input": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:rd_out to mux_write_addr:in1", + "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", "pos": [ [ - 431.0, - 350.0 - ], - [ - 480.0, - 350.0 + 820.0, + 155.0 ], [ - 480.0, - 519.2 + 820.0, + 395.0 ], [ - 700.0, - 520.0 + 808.5, + 395.0 ] ], "input": { - "id": "instruction_split", - "field": "rd_out" - } + "id": "control_unit_3", + "field": "reg_write_enable" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { - "type": "Wire", - "id": "from instruction_split:rt_out to alu_forward_B:b_in", + "type": "InstrMem", + "id": "instr_mem", "pos": [ - [ - 431.0, - 286.1111 - ], - [ - 953.0, - 405.0 - ] + 45.0, + 585.0 ], - "input": { - "id": "instruction_split", - "field": "rt_out" - } - }, - { - "type": "Wire", - "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", - "pos": [ - [ - 400.0, - 381.5 - ], - [ - 400.0, - 391.0 - ], - [ - 320.0, - 391.0 - ], - [ - 320.0, - 475.5 - ], - [ - 341.5, - 475.0 - ] + "pc": { + "id": "pc", + "field": "register_out" + }, + "phys_mem_id": "phys_mem", + "regfile_id": "reg_file", + "mem_view": { + "visible": false, + "title": "instruction memory view", + "id": "instr_mem", + "row_offset": 0, + "max_rows": 1024, + "big_endian": true, + "format": "HexAndMips", + "show_settings": { + "symbols": true, + "sections": false, + "program_counter": false, + "registers": [ + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + false, + true + ] + }, + "register_values": [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2147483648, + 0, + 0 + ], + "dynamic_symbols": { + "PC_IM": [ + 0, + true + ] + }, + "break_points": [] + } + }, + { + "type": "JumpMerge", + "id": "jump_merge", + "pos": [ + 180.0, + 530.0 ], - "input": { - "id": "instruction_split", - "field": "immediate_out" + "instr_addr_in": { + "id": "pc", + "field": "register_out" + }, + "jump_addr_in": { + "id": "instr_mem", + "field": "instruction" } }, { "type": "Wire", - "id": "from instruction_split:rt_out to reg_file:rt_address_in", + "id": "from jump_merge:merge_out to merge_reg:r_in", "pos": [ [ - 431.0, - 286.1111 + 180.0, + 544.0 ], [ - 585.0, - 406.0 + 180.0, + 580.0 + ], + [ + 230.0, + 580.0 ] ], "input": { - "id": "instruction_split", - "field": "rt_out" + "id": "jump_merge", + "field": "merge_out" } }, { "type": "Wire", - "id": "from operand_a_reg:register_out to mux_source_a:in1", + "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", "pos": [ [ - 1110.0, - 215.0 + 85.0, + 530.0 ], [ - 1230.0, - 210.0 + 140.0, + 530.0 ] ], "input": { - "id": "operand_a_reg", - "field": "register_out" + "id": "instr_mem", + "field": "instruction" } }, { "type": "Wire", - "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", + "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", "pos": [ [ - 1480.0, - 585.0 + 1110.0, + 325.0 ], [ - 1594.0, - 585.0 + 1140.0, + 325.0 ] ], "input": { - "id": "data_MEM_reg", + "id": "operand_b_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from instruction_split:rs_out to reg_file:rs_address_in", + "id": "from instr_mem:instruction to InMem_reg:r_in", "pos": [ [ - 431.0, - 196.0 - ], - [ - 440.0, - 196.0 - ], - [ - 440.0, - 120.0 + 85.0, + 551.5 ], [ - 585.0, - 120.0 + 85.0, + 475.0 ], [ - 585.0, - 144.0 + 230.0, + 475.0 ] ], "input": { - "id": "instruction_split", - "field": "rs_out" + "id": "instr_mem", + "field": "instruction" } }, { - "type": "PassThrough", - "id": "operand_b_pass", + "type": "Constant", + "id": "0_a_inp", "pos": [ - 1140.0, - 325.0 + 1190.0, + 230.0 ], - "input": { - "id": "operand_b_reg", - "field": "register_out" + "value": { + "data": { + "Data": 4 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { "type": "Wire", - "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", + "id": "from pc:register_out to jump_merge:merge_instr_addr_in", "pos": [ [ - 1140.8003, - 325.0 + 30.0, + 465.0 ], [ - 1140.8003, - 585.0 + 180.0, + 465.0 ], [ - 1460.8003, - 585.0 + 180.0, + 517.0 ] ], "input": { - "id": "operand_b_pass", - "field": "pass_through_out" + "id": "pc", + "field": "register_out" } }, { "type": "Wire", - "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", + "id": "from mux_b3_reg:register_out to mux_source_b:in2", "pos": [ [ - 395.0, - 170.0 + 1110.0, + 475.0 ], [ - 395.0, - 100.0 + 1180.0, + 475.0 ], [ - 1090.0, - 100.0 + 1180.0, + 345.0 + ], + [ + 1230.0, + 345.0 ] ], "input": { - "id": "instruction_split", - "field": "shamt_out" + "id": "mux_b3_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from merge_reg:register_out to mux_jump_merge:in2", + "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", "pos": [ [ - 250.0, - 580.0 - ], - [ - 260.0, - 580.0 - ], - [ - 260.0, - 630.0 - ], - [ - -94.0, - 630.0 + 1110.0, + -40.0 ], [ - -94.0, - 400.0 + 1140.0, + -40.0 + ] + ], + "input": { + "id": "control_EX_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", + "pos": [ + [ + 1110.0, + -40.0 ], [ - -74.0, - 400.0 + 1079.0, + 0.0 ] ], "input": { - "id": "merge_reg", + "id": "control_EX_reg", "field": "register_out" } }, { "type": "PassThrough", - "id": "control_MEM_pass", + "id": "control_EX_pass", "pos": [ - 1510.0, + 1140.0, -40.0 ], "input": { - "id": "control_MEM_reg", + "id": "control_EX_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", + "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", "pos": [ [ - 1510.0, + 1140.0, -40.0 ], [ - 1910.0, + 1460.0, -40.0 ] ], "input": { - "id": "control_MEM_pass", + "id": "control_EX_pass", "field": "pass_through_out" } }, { - "type": "Wire", - "id": "from alu_reg:register_out to write_back_mux:in0", + "type": "PassThrough", + "id": "pc+4_pass", "pos": [ - [ - 1480.0, - 250.0 - ], - [ - 1750.0, - 250.0 - ], - [ - 1750.0, - 260.0 - ], - [ - 1780.0, - 260.0 - ] + 260.0, + 370.0 ], "input": { - "id": "alu_reg", - "field": "register_out" - } - }, - { - "type": "ControlUnit", - "id": "control_unit_2", - "pos": [ - 1285.0, - 0.0 - ], - "a_in": { - "id": "control_EX_reg", + "id": "pc+4_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", + "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", "pos": [ [ - 1318.3334, - 13.5 + 260.0, + 380.0 + ], + [ + 260.0, + 420.0 ], [ - 953.0, - 162.5 + 1090.0, + 420.0 ] ], "input": { - "id": "control_unit_2", - "field": "mem_mode" + "id": "pc+4_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from control_unit_2:reg_write_enable to alu_forward_B:we_in", + "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", "pos": [ [ - 1451.6666, - 13.5 + 1480.0, + 520.0 ], [ - 953.0, - 397.5 + 1520.0, + 520.0 ] ], "input": { - "id": "control_unit_2", - "field": "reg_write_enable" + "id": "reg_addr_MEM_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_2:alu_src_b to mux_source_b:select", + "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", "pos": [ [ - 1251.6666, - 13.5 + 760.0, + 395.0 ], [ - 1240.0, - 285.0 + 790.0, + 395.0 ] ], "input": { - "id": "control_unit_2", - "field": "alu_src_b" + "id": "reg_addr_MEM_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", + "id": "from 0_a_inp:constant_out to mux_source_a:in2", "pos": [ [ - 1451.6666, - 13.5 + 1190.0, + 230.0 ], [ - 953.0, - 157.5 + 1230.0, + 230.0 ] ], "input": { - "id": "control_unit_2", - "field": "reg_write_enable" - } - }, - { - "type": "AluForward", - "id": "alu_forward_A", - "pos": [ - 970.0, - 155.0 - ], - "a_in": { - "id": "reg_addr_EX_reg", - "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "we_in": { - "id": "control_unit_2", - "field": "reg_write_enable" - }, - "load_in": { - "id": "control_unit_2", - "field": "mem_mode" + "id": "0_a_inp", + "field": "constant_out" } }, { "type": "Wire", - "id": "from alu_reg:register_out to data_mem:data_mem_address_in", + "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", "pos": [ [ - 1630.0, - 250.0 + 1540.0, + 13.5 ], [ - 1630.0, - 551.5 + 1540.0, + 80.0 + ], + [ + 820.0, + 80.0 + ], + [ + 820.0, + 155.0 + ], + [ + 809.0, + 155.0 ] ], "input": { - "id": "alu_reg", - "field": "register_out" - } + "id": "control_unit_3", + "field": "reg_write_enable" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from control_unit_2:mem_mode to alu_forward_B:load_in", + "id": "from +4:constant_out to pc+4:b_in", "pos": [ [ - 1318.3334, - 13.5 + 80.0, + 400.0 ], [ - 953.0, - 402.5 + 110.0, + 400.0 ] ], "input": { - "id": "control_unit_2", - "field": "mem_mode" + "id": "+4", + "field": "constant_out" } }, { - "type": "PassThrough", - "id": "reg_addr_MEM_pass", + "type": "ControlUnit", + "id": "control_unit_2", "pos": [ - 1520.0, - 520.0 + 1285.0, + 0.0 ], - "input": { - "id": "reg_addr_MEM_reg", + "a_in": { + "id": "control_EX_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", + "id": "from control_unit_2:alu_src_a to mux_source_a:select", "pos": [ [ - 1110.0, - 325.0 + 1240.0, + 13.5 ], [ - 1140.0, - 325.0 + 1240.0, + 170.0 ] ], "input": { - "id": "operand_b_reg", - "field": "register_out" - } + "id": "control_unit_2", + "field": "alu_src_a" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { - "type": "Constant", - "id": "0x_1F", + "type": "Mux", + "id": "mux_source_a", "pos": [ - 670.0, - 540.0 + 1250.0, + 210.0 ], - "value": { - "data": { - "Data": 31 + "select": { + "id": "control_unit_2", + "field": "alu_src_a" + }, + "m_in": [ + { + "id": "zero_extend_for_shamt", + "field": "zero_extend_out" }, - "fmt": { - "Hex": [ - "_32", - false - ] + { + "id": "operand_a_reg", + "field": "register_out" + }, + { + "id": "0_a_inp", + "field": "constant_out" } - } + ], + "scale": 1.0 }, { "type": "Wire", - "id": "from 0x_1F:constant_out to mux_write_addr:in2", + "id": "from mux_source_a:mux_out to alu:full_add_a_in", "pos": [ [ - 670.0, - 540.0 + 1260.0, + 210.0 ], [ - 700.0, - 540.0 + 1320.0, + 210.0 + ], + [ + 1320.0, + 220.0 + ], + [ + 1380.0, + 220.0 ] ], "input": { - "id": "0x_1F", - "field": "constant_out" + "id": "mux_source_a", + "field": "mux_out" } }, { "type": "Wire", - "id": "from +4:constant_out to pc+4:b_in", + "id": "from control_unit_2:alu_src_b to mux_source_b:select", "pos": [ [ - 80.0, - 400.0 + 1280.0, + 13.5 ], [ - 110.0, - 400.0 + 1280.0, + 270.0 + ], + [ + 1240.0, + 270.0 + ], + [ + 1240.0, + 285.0 ] ], "input": { - "id": "+4", - "field": "constant_out" - } + "id": "control_unit_2", + "field": "alu_src_b" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", + "id": "from control_unit_2:alu_op to alu:full_add_op_in", "pos": [ [ - 1520.0, - 520.0 + 1390.0, + 13.5 ], [ - 1910.0, - 520.0 + 1390.0, + 210.0 ] ], "input": { - "id": "reg_addr_MEM_pass", - "field": "pass_through_out" - } + "id": "control_unit_2", + "field": "alu_op" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from instruction_split:rt_out to mux_write_addr:in0", + "id": "from control_unit_2:mem_mode to alu_forward_B:load_in", "pos": [ [ - 430.0, - 332.0 - ], - [ - 495.19995, - 332.8 + 1000.0, + 160.0 ], [ - 494.39996, - 500.0 + 1000.0, + 402.5 ], [ - 700.0, - 500.0 + 980.0, + 402.5 ] ], "input": { - "id": "instruction_split", - "field": "rt_out" - } + "id": "control_unit_2", + "field": "mem_mode" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from mux_b2_reg:register_out to mux_source_b:in1", + "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", "pos": [ [ - 1110.0, - 420.0 + 1140.0, + 13.5 ], [ - 1230.0, - 325.0 + 1140.0, + 70.0 + ], + [ + 990.0, + 70.0 + ], + [ + 990.0, + 150.0 + ], + [ + 980.0, + 150.0 ] ], "input": { - "id": "mux_b2_reg", - "field": "register_out" - } - }, - { - "type": "Mux", - "id": "mux_source_b", - "pos": [ - 1250.0, - 325.0 - ], - "select": { "id": "control_unit_2", - "field": "alu_src_b" + "field": "reg_write_enable" }, - "m_in": [ - { - "id": "operand_b_reg", - "field": "register_out" - }, - { - "id": "mux_b2_reg", - "field": "register_out" - }, - { - "id": "mux_b3_reg", - "field": "register_out" - } - ], - "scale": 1.0 + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from control_unit_2:alu_op to alu:full_add_op_in", + "id": "from control_unit_2:reg_write_enable to alu_forward_B:we_in", "pos": [ [ - 1385.0, - 13.5 + 990.0, + 150.0 ], [ - 1390.0, - 210.0 + 990.0, + 390.0 + ], + [ + 980.0, + 390.0 ] ], "input": { "id": "control_unit_2", - "field": "alu_op" - } + "field": "reg_write_enable" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", + "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", "pos": [ [ - 1206.0, - 110.0 + 1110.0, + 13.5 ], [ - 1230.0, - 190.0 + 1110.0, + 50.0 + ], + [ + 1000.0, + 50.0 + ], + [ + 1000.0, + 160.0 + ], + [ + 980.0, + 160.0 ] ], "input": { - "id": "zero_extend_for_shamt", - "field": "zero_extend_out" - } + "id": "control_unit_2", + "field": "mem_mode" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { - "type": "PassThrough", - "id": "pc+4_pass", + "type": "ControlUnit", + "id": "control_unit_1", "pos": [ - 260.0, - 370.0 + 670.0, + 0.0 ], - "input": { - "id": "pc+4_reg", + "a_in": { + "id": "InMem_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", + "id": "from control_unit_1:reg_dest to mux_write_addr:select", "pos": [ [ - 260.0, - 380.0 - ], - [ - 260.0, - 420.0 + 710.0, + 14.0 ], [ - 1090.0, - 420.0 + 710.0, + 480.0 ] ], "input": { - "id": "pc+4_pass", - "field": "pass_through_out" - } + "id": "control_unit_1", + "field": "reg_dest" + }, + "color_rgba": [ + 0, + 0, + 0, + 30 + ] }, { "type": "Wire", - "id": "from pc+4_reg:register_out to pc_add_branch:a_in", + "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", "pos": [ [ - 305.0, - 420.0 + 434.0, + -40.0 ], [ - 305.0, - 545.0 + 434.0, + 0.0 ], [ - 510.0, - 545.0 + 464.0, + 0.0 ] ], "input": { - "id": "pc+4_reg", + "id": "InMem_reg", "field": "register_out" } }, { - "type": "Wire", - "id": "from instruction_split:rt_out to data_forward_B:b_in", + "type": "InstrSplit", + "id": "instruction_split", "pos": [ - [ - 431.0, - 286.1111 - ], - [ - 783.0, - 405.0 - ] + 400.0, + 275.0 ], - "input": { - "id": "instruction_split", - "field": "rt_out" + "instruction_in": { + "id": "InMem_reg", + "field": "register_out" } }, { - "type": "Wire", - "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", + "type": "SignZeroExtend", + "id": "signzero_extend", "pos": [ - [ - 1480.0, - 520.0 - ], - [ - 783.0, - 385.0 - ] + 400.0, + 475.0 ], - "input": { - "id": "reg_addr_MEM_reg", - "field": "register_out" + "signzero_signal_in": { + "id": "instruction_split", + "field": "immediate_out" + }, + "signzero_ctrl_in": { + "id": "control_unit_1", + "field": "extend_select" } }, { - "type": "PhysicalMem", - "id": "phys_mem", - "pos": [ - 800.0, - 600.0 - ] - }, - { - "type": "Wire", - "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", + "type": "Wire", + "id": "from signzero_extend:sz_out to branch_shift:shift_in", "pos": [ [ - 987.0, - 155.0 + 458.5, + 475.0 ], [ - 960.0, - 195.0 + 468.5, + 475.0 + ], + [ + 468.5, + 560.0 + ], + [ + 356.0, + 560.0 + ], + [ + 356.0, + 585.0 + ], + [ + 366.5, + 585.0 ] ], "input": { - "id": "alu_forward_A", - "field": "equals_forward_out" + "id": "signzero_extend", + "field": "sz_out" } }, { "type": "Wire", - "id": "from mux_b3_reg:register_out to mux_source_b:in2", + "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", "pos": [ [ - 1110.0, - 465.0 + 469.0, + 475.0 ], [ - 1230.0, - 345.0 + 1090.0, + 475.0 ] ], "input": { - "id": "mux_b3_reg", - "field": "register_out" + "id": "signzero_extend", + "field": "sz_out" } }, { - "type": "PassThrough", - "id": "reg_addr_EX_pass", + "type": "ShiftConst", + "id": "branch_shift", "pos": [ - 1165.0, - 520.0 + 400.0, + 585.0 ], - "input": { - "id": "reg_addr_EX_reg", - "field": "register_out" - } + "signal_in": { + "id": "signzero_extend", + "field": "sz_out" + }, + "shift_by": 2 }, { - "type": "ControlUnit", - "id": "control_unit_4", + "type": "Add", + "id": "pc_add_branch", "pos": [ - 2220.0, - 0.0 + 530.0, + 565.0 ], "a_in": { - "id": "control_WB_reg", + "id": "pc+4_reg", "field": "register_out" - } + }, + "b_in": { + "id": "branch_shift", + "field": "shift_left_const_out" + }, + "scale": 1.0 }, { "type": "Wire", - "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", + "id": "from pc_add_branch:add_out to mux_jump_merge:in0", "pos": [ [ - 434.0, - -40.0 + 550.0, + 565.0 ], [ - 434.0, - 0.0 + 560.0, + 565.0 ], [ - 464.0, - 0.0 + 561.0, + 640.0 + ], + [ + -114.0, + 640.0 + ], + [ + -114.0, + 360.0 + ], + [ + -74.0, + 360.0 ] ], "input": { - "id": "InMem_reg", - "field": "register_out" + "id": "pc_add_branch", + "field": "add_out" } }, { "type": "Wire", - "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", + "id": "from instruction_split:rt_out to data_forward_B:b_in", "pos": [ [ - 2320.0, - 13.0 - ], - [ - 2320.0, - 670.0 + 585.0, + 465.0 ], [ - 600.0, - 670.0 + 800.0, + 465.0 ], [ - 600.0, - 406.0 + 800.0, + 408.0 ] ], "input": { - "id": "control_unit_4", + "id": "instruction_split", + "field": "rt_out" + } + }, + { + "type": "AluForward", + "id": "alu_forward_B", + "pos": [ + 970.0, + 395.0 + ], + "a_in": { + "id": "reg_addr_EX_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "we_in": { + "id": "control_unit_2", "field": "reg_write_enable" + }, + "load_in": { + "id": "control_unit_2", + "field": "mem_mode" } }, { "type": "Wire", - "id": "from control_unit_2:alu_src_a to mux_source_a:select", + "id": "from alu_forward_B:equals_forward_out to alu_forward_B_mux:select", "pos": [ [ - 1218.3334, - 13.5 + 970.0, + 381.0 ], [ - 1240.0, - 170.0 + 960.0, + 355.0 ] ], "input": { + "id": "alu_forward_B", + "field": "equals_forward_out" + } + }, + { + "type": "AluForward", + "id": "alu_forward_A", + "pos": [ + 970.0, + 155.0 + ], + "a_in": { + "id": "reg_addr_EX_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "we_in": { "id": "control_unit_2", - "field": "alu_src_a" + "field": "reg_write_enable" + }, + "load_in": { + "id": "control_unit_2", + "field": "mem_mode" } }, { "type": "Wire", - "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", + "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", "pos": [ [ - 1110.0, - 110.0 + 970.0, + 167.0 ], [ - 1124.0, - 110.0 + 960.0, + 195.0 ] ], "input": { - "id": "zero_extend_reg", - "field": "register_out" + "id": "alu_forward_A", + "field": "equals_forward_out" } }, { "type": "Wire", - "id": "from reg_addr_EX_reg:register_out to alu_forward_B:a_in", + "id": "from instruction_split:rt_out to alu_forward_B:b_in", "pos": [ [ - 1110.0, - 520.0 + 800.0, + 465.0 + ], + [ + 970.0, + 465.0 ], [ - 953.0, - 385.0 + 970.0, + 408.0 ] ], "input": { - "id": "reg_addr_EX_reg", - "field": "register_out" + "id": "instruction_split", + "field": "rt_out" } }, { "type": "Wire", - "id": "from reg_addr_reg:register_out to reg_file:write_address_in", + "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", "pos": [ [ - 1930.0, - 520.0 + 400.0, + 381.5 ], [ - 1950.0, - 520.0 + 400.0, + 391.0 ], [ - 1951.6001, - 642.0 + 320.0, + 391.0 ], [ - 641.60004, - 642.0 + 320.0, + 475.5 ], [ - 640.0, - 406.0 + 341.5, + 475.0 ] ], "input": { - "id": "reg_addr_reg", - "field": "register_out" + "id": "instruction_split", + "field": "immediate_out" } }, { - "type": "RegFile", - "id": "reg_file", - "pos": [ - 585.0, - 275.0 - ], - "rs_address_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "rt_address_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "write_address_in": { - "id": "reg_addr_reg", - "field": "register_out" - }, - "write_data_in": { - "id": "result_reg_EX", - "field": "register_out" - }, - "write_enable_in": { - "id": "control_unit_4", - "field": "reg_write_enable" - } - }, - { - "type": "Wire", - "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", + "type": "Wire", + "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", "pos": [ [ - 651.0, - 315.0 + 395.0, + 170.0 ], [ - 780.0, - 315.0 + 395.0, + 100.0 + ], + [ + 1090.0, + 100.0 ] ], "input": { - "id": "reg_file", - "field": "rt_value_out" + "id": "instruction_split", + "field": "shamt_out" } }, { "type": "Wire", - "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", + "id": "from instruction_split:rt_out to mux_write_addr:in0", "pos": [ [ - 651.0, - 215.0 + 430.0, + 332.0 ], [ - 780.0, - 215.0 + 495.19995, + 332.8 + ], + [ + 494.39996, + 500.0 + ], + [ + 700.0, + 500.0 ] ], "input": { - "id": "reg_file", - "field": "rs_value_out" + "id": "instruction_split", + "field": "rt_out" } }, { "type": "Wire", - "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", + "id": "from instruction_split:rs_out to data_forward_A:b_in", "pos": [ [ - 1480.0, - -40.0 + 585.0, + 120.0 ], [ - 1489.0, - 0.0 + 800.0, + 120.0 + ], + [ + 800.0, + 142.0 ] ], "input": { - "id": "control_MEM_reg", - "field": "register_out" + "id": "instruction_split", + "field": "rs_out" } }, { - "type": "Constant", - "id": "0_a_inp", + "type": "DataForward", + "id": "data_forward_A", "pos": [ - 1190.0, - 210.0 + 800.0, + 155.0 ], - "value": { - "data": { - "Data": 4 - }, - "fmt": { - "Hex": [ - "_32", - false - ] - } + "a_in": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "we_in": { + "id": "control_unit_3", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from 0_a_inp:constant_out to mux_source_a:in2", + "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", "pos": [ [ - 1190.0, - 210.0 + 800.0, + 168.0 ], [ - 1230.0, - 230.0 + 790.0, + 195.0 ] ], "input": { - "id": "0_a_inp", - "field": "constant_out" + "id": "data_forward_A", + "field": "data_forward_out" } }, { - "type": "Mux", - "id": "mux_source_a", - "pos": [ - 1250.0, - 210.0 - ], - "select": { - "id": "control_unit_2", - "field": "alu_src_a" - }, - "m_in": [ - { - "id": "zero_extend_for_shamt", - "field": "zero_extend_out" - }, - { - "id": "operand_a_reg", - "field": "register_out" - }, - { - "id": "0_a_inp", - "field": "constant_out" - } - ], - "scale": 1.0 - }, - { - "type": "ALU", - "id": "alu", + "type": "Wire", + "id": "from instruction_split:rs_out to alu_forward_A:b_in", "pos": [ - 1400.0, - 250.0 + [ + 800.0, + 120.0 + ], + [ + 970.0, + 120.0 + ], + [ + 970.0, + 142.0 + ] ], - "a_in": { - "id": "mux_source_a", - "field": "mux_out" - }, - "b_in": { - "id": "mux_source_b", - "field": "mux_out" - }, - "op_in": { - "id": "control_unit_2", - "field": "alu_op" + "input": { + "id": "instruction_split", + "field": "rs_out" } }, { "type": "Wire", - "id": "from alu:alu_out to alu_reg:r_in", + "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", "pos": [ [ - 1420.0, - 250.0 + 250.0, + 475.0 ], [ - 1460.0, - 250.0 + 250.0, + 475.0 ] ], "input": { - "id": "alu", - "field": "alu_out" + "id": "InMem_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from alu:alu_out to alu_forward_A_mux:in1", + "id": "from alu_reg:register_out to write_back_mux:in0", "pos": [ [ - 1420.0, + 1480.0, 250.0 ], [ - 950.0, - 235.0 + 1750.0, + 250.0 + ], + [ + 1750.0, + 260.0 + ], + [ + 1780.0, + 260.0 ] ], "input": { - "id": "alu", - "field": "alu_out" + "id": "alu_reg", + "field": "register_out" + } + }, + { + "type": "DataForward", + "id": "data_forward_B", + "pos": [ + 800.0, + 395.0 + ], + "a_in": { + "id": "reg_addr_MEM_reg", + "field": "register_out" + }, + "b_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "we_in": { + "id": "control_unit_3", + "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from alu:alu_out to alu_forward_B_mux:in1", + "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", "pos": [ [ - 1420.0, - 250.0 + 800.0, + 382.0 ], [ - 950.0, - 335.0 + 790.0, + 355.0 ] ], "input": { - "id": "alu", - "field": "alu_out" + "id": "data_forward_B", + "field": "data_forward_out" } }, { "type": "Wire", - "id": "from mux_source_a:mux_out to alu:full_add_a_in", + "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", "pos": [ [ - 1260.0, - 210.0 + 1510.0, + -40.0 ], [ - 1380.0, - 220.0 + 1910.0, + -40.0 ] ], "input": { - "id": "mux_source_a", - "field": "mux_out" + "id": "control_MEM_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from pc:register_out to jump_merge:merge_instr_addr_in", + "id": "from merge_reg:register_out to mux_jump_merge:in2", "pos": [ [ - 30.0, - 465.0 + 250.0, + 580.0 ], [ - 180.0, - 465.0 + 260.0, + 580.0 ], [ - 180.0, - 517.0 + 260.0, + 630.0 + ], + [ + -94.0, + 630.0 + ], + [ + -94.0, + 400.0 + ], + [ + -74.0, + 400.0 ] ], "input": { - "id": "pc", + "id": "merge_reg", "field": "register_out" } }, { "type": "Wire", - "id": "from pc:register_out to pc+4:a_in", + "id": "from result_reg_EX:register_out to reg_file:write_data_in", "pos": [ [ - 30.0, - 390.0 + 1930.0, + 270.0 ], [ - 30.0, - 360.0 + 1970.0, + 270.0 ], [ - 110.0, - 360.0 + 1970.0, + 655.0 + ], + [ + 620.0, + 655.0 + ], + [ + 620.0, + 406.0 ] ], "input": { - "id": "pc", + "id": "result_reg_EX", "field": "register_out" } }, { - "type": "InstrMem", - "id": "instr_mem", + "type": "Wire", + "id": "from pc+4_reg:register_out to pc_add_branch:a_in", "pos": [ - 45.0, + [ + 305.0, + 420.0 + ], + [ + 305.0, + 545.0 + ], + [ + 510.0, + 545.0 + ] + ], + "input": { + "id": "pc+4_reg", + "field": "register_out" + } + }, + { + "type": "Wire", + "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", + "pos": [ + [ + 1480.0, + 585.0 + ], + [ + 1594.0, + 585.0 + ] + ], + "input": { + "id": "data_MEM_reg", + "field": "register_out" + } + }, + { + "type": "DataMem", + "id": "data_mem", + "pos": [ + 1660.0, 585.0 ], - "pc": { - "id": "pc", + "address_input": { + "id": "alu_reg", + "field": "register_out" + }, + "data_input": { + "id": "data_MEM_reg", "field": "register_out" }, + "op_input": { + "id": "control_unit_3", + "field": "mem_mode" + }, + "write_enable_input": { + "id": "control_unit_3", + "field": "mem_write_enable" + }, "phys_mem_id": "phys_mem", "regfile_id": "reg_file", "mem_view": { "visible": false, - "title": "instruction memory view", - "id": "instr_mem", - "row_offset": 0, + "title": "Data memory view", + "id": "data_mem", + "row_offset": 512, "max_rows": 1024, "big_endian": true, - "format": "HexAndMips", + "format": "ByteAndUtf8", "show_settings": { "symbols": true, "sections": false, @@ -1830,7 +2065,7 @@ false, false, false, - true + false ] }, "register_values": [ @@ -1868,182 +2103,157 @@ 0 ], "dynamic_symbols": { - "PC_IM": [ + "DM_ADRS": [ 0, - true + false ] }, - "break_points": [] + "break_points": [ + 4176 + ] } }, { - "type": "Wire", - "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", + "type": "Mux", + "id": "write_back_mux", "pos": [ - [ - 85.0, - 530.0 - ], - [ - 140.0, - 530.0 - ] + 1800.0, + 270.0 ], - "input": { - "id": "instr_mem", - "field": "instruction" - } + "select": { + "id": "control_unit_3", + "field": "reg_write_src" + }, + "m_in": [ + { + "id": "alu_reg", + "field": "register_out" + }, + { + "id": "data_mem", + "field": "data_out" + } + ], + "scale": 1.0 }, { "type": "Wire", - "id": "from instr_mem:instruction to InMem_reg:r_in", + "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", "pos": [ [ - 85.0, - 551.5 - ], - [ - 85.0, - 475.0 + 740.0, + 335.0 ], [ - 230.0, - 475.0 + 780.0, + 335.0 ] ], "input": { - "id": "instr_mem", - "field": "instruction" + "id": "write_back_mux", + "field": "mux_out" } }, - { - "type": "Add", - "id": "pc+4", - "pos": [ - 130.0, - 380.0 - ], - "a_in": { - "id": "pc", - "field": "register_out" - }, - "b_in": { - "id": "+4", - "field": "constant_out" - }, - "scale": 1.0 - }, { "type": "Wire", - "id": "from pc+4:add_out to mux_jump_merge:in3", + "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", "pos": [ [ - 150.0, - 380.0 - ], - [ - 170.0, - 380.0 + 1830.0, + 270.0 ], [ - 170.0, - 455.0 + 1830.0, + 440.0 ], [ - -80.0, - 455.0 + 740.0, + 440.0 ], [ - -80.0, - 420.0 + 740.0, + 235.0 ], [ - -74.0, - 420.0 + 780.0, + 235.0 ] ], "input": { - "id": "pc+4", - "field": "add_out" + "id": "write_back_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from pc+4:add_out to pc+4_reg:r_in", + "id": "from write_back_mux:mux_out to result_reg_EX:r_in", "pos": [ [ - 150.0, - 380.0 + 1810.0, + 270.0 ], [ - 230.0, - 380.0 + 1910.0, + 270.0 ] ], "input": { - "id": "pc+4", - "field": "add_out" + "id": "write_back_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from pc:register_out to instr_mem:pc", + "id": "from data_mem:data_out to write_back_mux:in1", "pos": [ [ - 10.0, - 390.0 + 1726.0, + 585.0 ], [ - 30.0, - 390.0 + 1750.0, + 585.0 ], [ - 31.0, - 551.5 - ] - ], + 1750.0, + 280.0 + ], + [ + 1780.0, + 280.0 + ] + ], "input": { - "id": "pc", - "field": "register_out" + "id": "data_mem", + "field": "data_out" } }, { - "type": "JumpMerge", - "id": "jump_merge", + "type": "Mux", + "id": "mux_source_b", "pos": [ - 180.0, - 530.0 + 1250.0, + 325.0 ], - "instr_addr_in": { - "id": "pc", - "field": "register_out" + "select": { + "id": "control_unit_2", + "field": "alu_src_b" }, - "jump_addr_in": { - "id": "instr_mem", - "field": "instruction" - } - }, - { - "type": "Wire", - "id": "from jump_merge:merge_out to merge_reg:r_in", - "pos": [ - [ - 180.0, - 544.0 - ], - [ - 180.0, - 580.0 - ], - [ - 230.0, - 580.0 - ] + "m_in": [ + { + "id": "operand_b_reg", + "field": "register_out" + }, + { + "id": "mux_b2_reg", + "field": "register_out" + }, + { + "id": "mux_b3_reg", + "field": "register_out" + } ], - "input": { - "id": "jump_merge", - "field": "merge_out" - } + "scale": 1.0 }, { "type": "Wire", @@ -2053,6 +2263,14 @@ 1260.0, 325.0 ], + [ + 1320.0, + 325.0 + ], + [ + 1320.0, + 280.0 + ], [ 1380.0, 280.0 @@ -2064,1162 +2282,1206 @@ } }, { - "type": "Wire", - "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", + "type": "ALU", + "id": "alu", "pos": [ - [ - 1165.0, - 520.0 - ], - [ - 1460.0, - 520.0 - ] + 1400.0, + 250.0 ], - "input": { - "id": "reg_addr_EX_pass", - "field": "pass_through_out" + "a_in": { + "id": "mux_source_a", + "field": "mux_out" + }, + "b_in": { + "id": "mux_source_b", + "field": "mux_out" + }, + "op_in": { + "id": "control_unit_2", + "field": "alu_op" } }, { "type": "Wire", - "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", + "id": "from alu:alu_out to alu_reg:r_in", "pos": [ [ - 1930.0, - -40.0 + 1420.0, + 250.0 ], [ - 2014.0, - 0.0 + 1460.0, + 250.0 ] ], "input": { - "id": "control_WB_reg", - "field": "register_out" - } - }, - { - "type": "ControlUnit", - "id": "control_unit_3", - "pos": [ - 1695.0, - 0.0 - ], - "a_in": { - "id": "control_MEM_reg", - "field": "register_out" + "id": "alu", + "field": "alu_out" } }, { "type": "Wire", - "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", + "id": "from alu:alu_out to alu_forward_A_mux:in1", "pos": [ [ - 1690.0, - 13.5 + 910.0, + 335.0 ], [ - 1690.0, - 551.5 + 910.0, + 235.0 + ], + [ + 950.0, + 235.0 ] ], "input": { - "id": "control_unit_3", - "field": "mem_mode" + "id": "alu", + "field": "alu_out" } }, { "type": "Wire", - "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", + "id": "from alu:alu_out to alu_forward_B_mux:in1", "pos": [ [ - 820.0, - 155.0 + 1440.0, + 250.0 ], [ - 820.0, - 395.0 + 1440.0, + 570.0 ], [ - 808.5, - 395.0 + 910.0, + 570.0 + ], + [ + 910.0, + 335.0 + ], + [ + 950.0, + 335.0 ] ], "input": { - "id": "control_unit_3", - "field": "reg_write_enable" + "id": "alu", + "field": "alu_out" } }, { "type": "Wire", - "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", + "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", "pos": [ [ - 1660.0, - 13.5 + 250.0, + 380.0 ], [ - 1660.0, - 551.5 + 260.0, + 380.0 ] ], "input": { - "id": "control_unit_3", - "field": "mem_write_enable" + "id": "pc+4_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", + "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", "pos": [ [ - 1540.0, - 13.5 - ], - [ - 1540.0, - 80.0 - ], - [ - 820.0, - 80.0 + 930.0, + 395.0 ], [ - 820.0, + 930.0, 155.0 ], [ - 809.0, + 960.0, 155.0 ] ], "input": { - "id": "control_unit_3", - "field": "reg_write_enable" - } - }, - { - "type": "DataForward", - "id": "data_forward_B", - "pos": [ - 800.0, - 395.0 - ], - "a_in": { - "id": "reg_addr_MEM_reg", + "id": "reg_addr_EX_reg", "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "we_in": { - "id": "control_unit_3", - "field": "reg_write_enable" } }, { "type": "Wire", - "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", + "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", "pos": [ [ - 817.0, - 395.0 + 1930.0, + -40.0 ], [ - 790.0, - 295.0 + 2014.0, + 0.0 ] ], "input": { - "id": "data_forward_B", - "field": "data_forward_out" + "id": "control_WB_reg", + "field": "register_out" } }, { - "type": "DataForward", - "id": "data_forward_A", + "type": "ControlUnit", + "id": "control_unit_4", "pos": [ - 800.0, - 155.0 + 2220.0, + 0.0 ], "a_in": { - "id": "reg_addr_MEM_reg", + "id": "control_WB_reg", "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rs_out" - }, - "we_in": { - "id": "control_unit_3", - "field": "reg_write_enable" } }, { - "type": "Wire", - "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", + "type": "RegFile", + "id": "reg_file", "pos": [ - [ - 817.0, - 155.0 - ], - [ - 790.0, - 195.0 - ] + 585.0, + 275.0 ], - "input": { - "id": "data_forward_A", - "field": "data_forward_out" + "rs_address_in": { + "id": "instruction_split", + "field": "rs_out" + }, + "rt_address_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "write_address_in": { + "id": "reg_addr_reg", + "field": "register_out" + }, + "write_data_in": { + "id": "result_reg_EX", + "field": "register_out" + }, + "write_enable_in": { + "id": "control_unit_4", + "field": "reg_write_enable" } }, { - "type": "DataMem", - "id": "data_mem", + "type": "Mux", + "id": "data_forward_A_mux", "pos": [ - 1660.0, - 585.0 + 800.0, + 225.0 ], - "address_input": { - "id": "alu_reg", - "field": "register_out" - }, - "data_input": { - "id": "data_MEM_reg", - "field": "register_out" - }, - "op_input": { - "id": "control_unit_3", - "field": "mem_mode" + "select": { + "id": "data_forward_A", + "field": "data_forward_out" }, - "write_enable_input": { - "id": "control_unit_3", - "field": "mem_write_enable" + "m_in": [ + { + "id": "reg_file", + "field": "rs_value_out" + }, + { + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, + { + "type": "Mux", + "id": "alu_forward_A_mux", + "pos": [ + 970.0, + 225.0 + ], + "select": { + "id": "alu_forward_A", + "field": "equals_forward_out" }, - "phys_mem_id": "phys_mem", - "regfile_id": "reg_file", - "mem_view": { - "visible": false, - "title": "Data memory view", - "id": "data_mem", - "row_offset": 512, - "max_rows": 1024, - "big_endian": true, - "format": "ByteAndUtf8", - "show_settings": { - "symbols": true, - "sections": false, - "program_counter": false, - "registers": [ - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false, - false - ] + "m_in": [ + { + "id": "data_forward_A_mux", + "field": "mux_out" }, - "register_values": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 2147483648, - 0, - 0 + { + "id": "alu", + "field": "alu_out" + } + ], + "scale": 1.0 + }, + { + "type": "Wire", + "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", + "pos": [ + [ + 1010.0, + 225.0 ], - "dynamic_symbols": { - "DM_ADRS": [ - 0, - false - ] - }, - "break_points": [ - 4176 + [ + 1010.0, + 262.0 ] + ], + "input": { + "id": "alu_forward_A_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from data_mem:data_out to write_back_mux:in1", + "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", "pos": [ [ - 1726.0, - 585.0 + 1020.0, + 215.5 ], [ - 1750.0, - 585.0 + 1090.0, + 215.0 + ] + ], + "input": { + "id": "alu_forward_A_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", + "pos": [ + [ + 980.0, + 225.0 ], [ - 1750.0, - 280.0 + 1020.0, + 225.0 ], [ - 1780.0, - 280.0 + 1020.0, + 40.0 + ], + [ + -94.0, + 40.0 + ], + [ + -94.0, + 380.0 + ], + [ + -74.0, + 380.0 ] ], "input": { - "id": "data_mem", - "field": "data_out" + "id": "alu_forward_A_mux", + "field": "mux_out" } }, { "type": "Wire", - "id": "from control_unit_3:reg_write_src to write_back_mux:select", + "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", "pos": [ [ - 1790.0, - 13.5 + 651.0, + 315.0 ], [ - 1790.0, - 240.0 + 780.0, + 315.0 ] ], "input": { - "id": "control_unit_3", - "field": "reg_write_src" + "id": "reg_file", + "field": "rt_value_out" } }, { "type": "Mux", - "id": "write_back_mux", + "id": "data_forward_B_mux", "pos": [ - 1800.0, - 270.0 + 800.0, + 325.0 ], "select": { - "id": "control_unit_3", - "field": "reg_write_src" + "id": "data_forward_B", + "field": "data_forward_out" }, "m_in": [ { - "id": "alu_reg", - "field": "register_out" + "id": "reg_file", + "field": "rt_value_out" }, { - "id": "data_mem", - "field": "data_out" + "id": "write_back_mux", + "field": "mux_out" + } + ], + "scale": 1.0 + }, + { + "type": "Mux", + "id": "alu_forward_B_mux", + "pos": [ + 970.0, + 325.0 + ], + "select": { + "id": "alu_forward_B", + "field": "equals_forward_out" + }, + "m_in": [ + { + "id": "data_forward_B_mux", + "field": "mux_out" + }, + { + "id": "alu", + "field": "alu_out" } ], "scale": 1.0 }, { "type": "Wire", - "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", + "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", "pos": [ [ - 740.0, - 335.0 + 980.0, + 325.0 ], [ - 780.0, - 335.0 + 1090.0, + 325.0 ] ], "input": { - "id": "write_back_mux", + "id": "alu_forward_B_mux", "field": "mux_out" } }, { - "type": "Mux", - "id": "data_forward_A_mux", + "type": "BranchLogic", + "id": "branch", "pos": [ - 800.0, - 225.0 + 1040.0, + 275.0 ], - "select": { - "id": "data_forward_A", - "field": "data_forward_out" + "op_in": { + "id": "instruction_split", + "field": "op_out" }, - "m_in": [ - { - "id": "reg_file", - "field": "rs_value_out" - }, - { - "id": "write_back_mux", - "field": "mux_out" - } + "rt_in": { + "id": "instruction_split", + "field": "rt_out" + }, + "funct_in": { + "id": "instruction_split", + "field": "funct_out" + }, + "rs_value": { + "id": "alu_forward_A_mux", + "field": "mux_out" + }, + "rt_value": { + "id": "alu_forward_B_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from branch:branch_out to mux_jump_merge:select", + "pos": [ + [ + 1040.0, + 262.0 + ], + [ + 1040.0, + 60.0 + ], + [ + -64.0, + 60.0 + ], + [ + -64.0, + 340.0 + ] ], - "scale": 1.0 + "input": { + "id": "branch", + "field": "branch_out" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] }, { "type": "Wire", - "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", + "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", + "pos": [ + [ + 1010.0, + 325.0 + ], + [ + 1010.0, + 288.0 + ] + ], + "input": { + "id": "alu_forward_B_mux", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", + "pos": [ + [ + 2030.0, + 13.0 + ], + [ + 2030.0, + 670.0 + ], + [ + 600.0, + 670.0 + ], + [ + 600.0, + 406.0 + ] + ], + "input": { + "id": "control_unit_4", + "field": "reg_write_enable" + } + }, + { + "type": "Wire", + "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", "pos": [ [ - 810.0, - 225.0 + 433.5, + 585.0 ], [ - 950.0, - 215.0 + 510.0, + 585.0 ] ], "input": { - "id": "data_forward_A_mux", - "field": "mux_out" + "id": "branch_shift", + "field": "shift_left_const_out" } }, - { - "type": "Mux", - "id": "alu_forward_A_mux", - "pos": [ - 970.0, - 225.0 - ], - "select": { - "id": "alu_forward_A", - "field": "equals_forward_out" - }, - "m_in": [ - { - "id": "data_forward_A_mux", - "field": "mux_out" - }, - { - "id": "alu", - "field": "alu_out" - } - ], - "scale": 1.0 - }, { "type": "Wire", - "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", + "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", "pos": [ [ - 980.0, - 225.0 + 480.0, + 13.5 ], [ - 1090.0, - 215.0 + 480.0, + 80.0 + ], + [ + 340.0, + 80.0 + ], + [ + 340.0, + 440.0 + ], + [ + 400.0, + 440.0 + ], + [ + 400.0, + 454.0 ] ], "input": { - "id": "alu_forward_A_mux", - "field": "mux_out" - } + "id": "control_unit_1", + "field": "extend_select" + }, + "color_rgba": [ + 0, + 0, + 0, + 30 + ] }, { "type": "Wire", - "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", + "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", "pos": [ [ - 980.0, + 810.0, 225.0 ], [ - 1040.0, - 275.0 + 860.0, + 225.0 + ], + [ + 860.0, + 215.0 + ], + [ + 950.0, + 215.0 ] ], "input": { - "id": "alu_forward_A_mux", + "id": "data_forward_A_mux", "field": "mux_out" } }, { "type": "Wire", - "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", + "id": "from instruction_split:rd_out to mux_write_addr:in1", "pos": [ [ - 980.0, - 225.0 - ], - [ - 1000.0, - 225.0 - ], - [ - 1000.0, - 40.0 + 431.0, + 350.0 ], [ - -94.0, - 40.0 + 480.0, + 350.0 ], [ - -94.0, - 380.0 + 480.0, + 519.2 ], [ - -74.0, - 380.0 + 700.0, + 520.0 ] ], "input": { - "id": "alu_forward_A_mux", - "field": "mux_out" + "id": "instruction_split", + "field": "rd_out" + } + }, + { + "type": "Constant", + "id": "0x_1F", + "pos": [ + 670.0, + 540.0 + ], + "value": { + "data": { + "Data": 31 + }, + "fmt": { + "Hex": [ + "_32", + false + ] + } } }, { "type": "Mux", - "id": "data_forward_B_mux", + "id": "mux_write_addr", "pos": [ - 800.0, - 325.0 + 720.0, + 520.0 ], "select": { - "id": "data_forward_B", - "field": "data_forward_out" + "id": "control_unit_1", + "field": "reg_dest" }, "m_in": [ { - "id": "reg_file", - "field": "rt_value_out" + "id": "instruction_split", + "field": "rt_out" }, { - "id": "write_back_mux", - "field": "mux_out" + "id": "instruction_split", + "field": "rd_out" + }, + { + "id": "0x_1F", + "field": "constant_out" } ], "scale": 1.0 }, { "type": "Wire", - "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", + "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", "pos": [ [ - 810.0, - 325.0 + 730.0, + 520.0 ], [ - 950.0, - 315.0 + 1090.0, + 520.0 ] ], "input": { - "id": "data_forward_B_mux", + "id": "mux_write_addr", "field": "mux_out" } }, { "type": "Wire", - "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", + "id": "from 0x_1F:constant_out to mux_write_addr:in2", "pos": [ [ - 1830.0, - 270.0 - ], - [ - 1830.0, - 440.0 - ], - [ - 740.0, - 440.0 - ], - [ - 740.0, - 235.0 + 670.0, + 540.0 ], [ - 780.0, - 235.0 + 700.0, + 540.0 ] ], "input": { - "id": "write_back_mux", - "field": "mux_out" + "id": "0x_1F", + "field": "constant_out" } }, { "type": "Wire", - "id": "from write_back_mux:mux_out to result_reg_EX:r_in", + "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", "pos": [ [ - 1810.0, - 270.0 + 810.0, + 325.0 ], [ - 1910.0, - 270.0 + 860.0, + 325.0 + ], + [ + 860.0, + 315.0 + ], + [ + 950.0, + 315.0 ] ], "input": { - "id": "write_back_mux", + "id": "data_forward_B_mux", "field": "mux_out" } }, { "type": "Wire", - "id": "from instruction_split:rs_out to alu_forward_A:b_in", + "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", "pos": [ [ - 800.0, - 120.0 + 1500.0, + 520.0 ], [ - 970.0, - 120.0 + 1500.0, + 450.0 ], [ - 970.0, - 142.0 + 760.0, + 450.0 + ], + [ + 760.0, + 155.0 + ], + [ + 790.0, + 155.0 ] ], "input": { - "id": "instruction_split", - "field": "rs_out" - } - }, - { - "type": "ControlUnit", - "id": "control_unit_1", - "pos": [ - 670.0, - 0.0 - ], - "a_in": { - "id": "InMem_reg", + "id": "reg_addr_MEM_reg", "field": "register_out" } }, { - "type": "SignZeroExtend", - "id": "signzero_extend", + "type": "PassThrough", + "id": "InMem_pass", "pos": [ - 400.0, + 250.0, 475.0 ], - "signzero_signal_in": { - "id": "instruction_split", - "field": "immediate_out" - }, - "signzero_ctrl_in": { - "id": "control_unit_1", - "field": "extend_select" + "input": { + "id": "InMem_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from signzero_extend:sz_out to branch_shift:shift_in", + "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", "pos": [ [ - 458.5, + 250.0, 475.0 ], [ - 468.5, + 280.0, 475.0 ], [ - 468.5, - 560.0 - ], - [ - 356.0, - 560.0 - ], - [ - 356.0, - 585.0 + 280.0, + -40.0 ], [ - 366.5, - 585.0 + 1090.0, + -40.0 ] ], "input": { - "id": "signzero_extend", - "field": "sz_out" + "id": "InMem_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", + "id": "from InMem_reg:register_out to instruction_split:instruction_in", "pos": [ [ - 469.0, - 475.0 + 279.0, + 275.0 ], [ - 1090.0, - 475.0 + 359.0, + 275.0 ] ], "input": { - "id": "signzero_extend", - "field": "sz_out" + "id": "InMem_reg", + "field": "register_out" } }, { - "type": "ShiftConst", - "id": "branch_shift", + "type": "PhysicalMem", + "id": "phys_mem", "pos": [ - 400.0, - 585.0 - ], - "signal_in": { - "id": "signzero_extend", - "field": "sz_out" - }, - "shift_by": 2 + 800.0, + 600.0 + ] }, { "type": "Add", - "id": "pc_add_branch", + "id": "pc+4", "pos": [ - 530.0, - 565.0 + 130.0, + 380.0 ], "a_in": { - "id": "pc+4_reg", + "id": "pc", "field": "register_out" }, "b_in": { - "id": "branch_shift", - "field": "shift_left_const_out" + "id": "+4", + "field": "constant_out" + }, + "scale": 1.0 + }, + { + "type": "Mux", + "id": "mux_jump_merge", + "pos": [ + -54.0, + 390.0 + ], + "select": { + "id": "branch", + "field": "branch_out" }, + "m_in": [ + { + "id": "pc_add_branch", + "field": "add_out" + }, + { + "id": "alu_forward_A_mux", + "field": "mux_out" + }, + { + "id": "merge_reg", + "field": "register_out" + }, + { + "id": "pc+4", + "field": "add_out" + } + ], "scale": 1.0 }, { "type": "Wire", - "id": "from pc_add_branch:add_out to mux_jump_merge:in0", + "id": "from mux_jump_merge:mux_out to pc:r_in", "pos": [ [ - 550.0, - 565.0 + -44.0, + 390.0 ], [ - 560.0, - 565.0 + -10.0, + 390.0 + ] + ], + "input": { + "id": "mux_jump_merge", + "field": "mux_out" + } + }, + { + "type": "Wire", + "id": "from pc+4:add_out to mux_jump_merge:in3", + "pos": [ + [ + 150.0, + 380.0 ], [ - 561.0, - 640.0 + 170.0, + 380.0 ], [ - -114.0, - 640.0 + 170.0, + 455.0 ], [ - -114.0, - 360.0 + -80.0, + 455.0 + ], + [ + -80.0, + 420.0 ], [ -74.0, - 360.0 + 420.0 ] ], "input": { - "id": "pc_add_branch", + "id": "pc+4", "field": "add_out" } }, { "type": "Wire", - "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", + "id": "from pc+4:add_out to pc+4_reg:r_in", "pos": [ [ - 433.5, - 585.0 + 150.0, + 380.0 ], [ - 510.0, - 585.0 + 230.0, + 380.0 ] ], "input": { - "id": "branch_shift", - "field": "shift_left_const_out" + "id": "pc+4", + "field": "add_out" } }, { - "type": "Mux", - "id": "mux_write_addr", + "type": "Wire", + "id": "from instruction_split:rt_out to reg_file:rt_address_in", "pos": [ - 720.0, - 520.0 - ], - "select": { - "id": "control_unit_1", - "field": "reg_dest" - }, - "m_in": [ - { - "id": "instruction_split", - "field": "rt_out" - }, - { - "id": "instruction_split", - "field": "rd_out" - }, - { - "id": "0x_1F", - "field": "constant_out" - } + [ + 431.0, + 310.0 + ], + [ + 505.0, + 310.0 + ], + [ + 505.0, + 465.0 + ], + [ + 585.0, + 465.0 + ], + [ + 585.0, + 406.0 + ] ], - "scale": 1.0 + "input": { + "id": "instruction_split", + "field": "rt_out" + } }, { "type": "Wire", - "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", + "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", "pos": [ [ - 980.0, - 520.0 + 1480.0, + -40.0 ], [ - 1090.0, - 520.0 + 1489.0, + 0.0 ] ], "input": { - "id": "mux_write_addr", - "field": "mux_out" + "id": "control_MEM_reg", + "field": "register_out" + } + }, + { + "type": "PassThrough", + "id": "operand_b_pass", + "pos": [ + 1140.0, + 325.0 + ], + "input": { + "id": "operand_b_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", + "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", "pos": [ [ - 480.0, - 13.5 - ], - [ - 480.0, - 80.0 - ], - [ - 340.0, - 80.0 - ], - [ - 340.0, - 440.0 + 1140.0, + 325.0 ], [ - 400.0, - 440.0 + 1140.0, + 585.0 ], [ - 400.0, - 454.0 + 1460.0, + 585.0 ] ], - "input": { - "id": "control_unit_1", - "field": "extend_select" + "input": { + "id": "operand_b_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from control_unit_1:reg_dest to mux_write_addr:select", + "id": "from instruction_split:rs_out to reg_file:rs_address_in", "pos": [ [ - 710.0, - 14.0 + 431.0, + 196.0 ], [ - 710.0, - 480.0 + 440.0, + 196.0 + ], + [ + 440.0, + 120.0 + ], + [ + 585.0, + 120.0 + ], + [ + 585.0, + 144.0 ] ], "input": { - "id": "control_unit_1", - "field": "reg_dest" + "id": "instruction_split", + "field": "rs_out" } }, { "type": "Wire", - "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", + "id": "from operand_b_reg:register_out to mux_source_b:in0", "pos": [ [ - 1480.0, - -40.0 + 1140.0, + 325.0 ], [ - 1510.0, - -40.0 + 1140.0, + 305.0 + ], + [ + 1230.0, + 305.0 ] ], "input": { - "id": "control_MEM_reg", + "id": "operand_b_reg", "field": "register_out" } }, { - "type": "AluForward", - "id": "alu_forward_B", + "type": "PassThrough", + "id": "reg_addr_MEM_pass", "pos": [ - 970.0, - 395.0 + 1520.0, + 520.0 ], - "a_in": { - "id": "reg_addr_EX_reg", + "input": { + "id": "reg_addr_MEM_reg", "field": "register_out" - }, - "b_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "we_in": { - "id": "control_unit_2", - "field": "reg_write_enable" - }, - "load_in": { - "id": "control_unit_2", - "field": "mem_mode" } }, - { - "type": "Mux", - "id": "alu_forward_B_mux", - "pos": [ - 970.0, - 325.0 - ], - "select": { - "id": "alu_forward_B", - "field": "equals_forward_out" - }, - "m_in": [ - { - "id": "data_forward_B_mux", - "field": "mux_out" - }, - { - "id": "alu", - "field": "alu_out" - } - ], - "scale": 1.0 - }, { "type": "Wire", - "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", + "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", "pos": [ [ - 980.0, - 325.0 + 1520.0, + 520.0 ], [ - 1040.0, - 275.0 + 1910.0, + 520.0 ] ], "input": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "id": "reg_addr_MEM_pass", + "field": "pass_through_out" } }, { - "type": "BranchLogic", - "id": "branch", + "type": "Wire", + "id": "from alu_reg:register_out to data_mem:data_mem_address_in", "pos": [ - 1040.0, - 275.0 + [ + 1630.0, + 250.0 + ], + [ + 1630.0, + 551.5 + ] ], - "op_in": { - "id": "instruction_split", - "field": "op_out" - }, - "rt_in": { - "id": "instruction_split", - "field": "rt_out" - }, - "funct_in": { - "id": "instruction_split", - "field": "funct_out" - }, - "rs_value": { - "id": "alu_forward_A_mux", - "field": "mux_out" - }, - "rt_value": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "input": { + "id": "alu_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from branch:branch_out to mux_jump_merge:select", + "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", "pos": [ [ - 1040.0, - 262.0 - ], - [ - 1040.0, - 60.0 - ], - [ - -64.0, - 60.0 + 651.0, + 215.0 ], [ - -64.0, - 340.0 + 780.0, + 215.0 ] ], "input": { - "id": "branch", - "field": "branch_out" + "id": "reg_file", + "field": "rs_value_out" } }, - { - "type": "Mux", - "id": "mux_jump_merge", - "pos": [ - -54.0, - 390.0 - ], - "select": { - "id": "branch", - "field": "branch_out" - }, - "m_in": [ - { - "id": "pc_add_branch", - "field": "add_out" - }, - { - "id": "alu_forward_A_mux", - "field": "mux_out" - }, - { - "id": "merge_reg", - "field": "register_out" - }, - { - "id": "pc+4", - "field": "add_out" - } - ], - "scale": 1.0 - }, { "type": "Wire", - "id": "from mux_jump_merge:mux_out to pc:r_in", + "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", "pos": [ [ - -44.0, - 390.0 + 1165.0, + 520.0 ], [ - -10.0, - 390.0 + 1460.0, + 520.0 ] ], "input": { - "id": "mux_jump_merge", - "field": "mux_out" + "id": "reg_addr_EX_pass", + "field": "pass_through_out" } }, { "type": "Wire", - "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", + "id": "from pc:register_out to pc+4:a_in", "pos": [ [ - 980.0, - 325.0 + 30.0, + 390.0 ], [ - 1090.0, - 325.0 + 30.0, + 360.0 + ], + [ + 110.0, + 360.0 ] ], "input": { - "id": "alu_forward_B_mux", - "field": "mux_out" + "id": "pc", + "field": "register_out" } }, { "type": "Wire", - "id": "from alu_forward_B:equals_forward_out to alu_forward_B_mux:select", + "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", "pos": [ [ - 987.0, - 395.0 + 1480.0, + -40.0 ], [ - 960.0, - 295.0 + 1510.0, + -40.0 ] ], "input": { - "id": "alu_forward_B", - "field": "equals_forward_out" + "id": "control_MEM_reg", + "field": "register_out" } }, { "type": "Wire", - "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", + "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", "pos": [ [ - 250.0, - 380.0 + 1660.0, + 13.5 ], [ - 260.0, - 380.0 + 1660.0, + 551.5 ] ], "input": { - "id": "pc+4_reg", - "field": "register_out" - } + "id": "control_unit_3", + "field": "mem_write_enable" + }, + "color_rgba": [ + 0, + 0, + 0, + 40 + ] } ] -} +} \ No newline at end of file From dcc3a32ecf85ea8c2ccc5af3e964e9caad5d0144 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Fri, 11 Oct 2024 17:51:38 +0200 Subject: [PATCH 14/18] made passthrough only visible in editor --- src/gui_egui/components/pass_through.rs | 80 +++++-------------------- 1 file changed, 15 insertions(+), 65 deletions(-) diff --git a/src/gui_egui/components/pass_through.rs b/src/gui_egui/components/pass_through.rs index 9b1fb0a..289ed7e 100644 --- a/src/gui_egui/components/pass_through.rs +++ b/src/gui_egui/components/pass_through.rs @@ -2,90 +2,40 @@ use crate::common::{Component, EguiComponent, Ports, Simulator}; use crate::components::PassThrough; use crate::gui_egui::editor::{EditorMode, EditorRenderReturn, GridOptions}; use crate::gui_egui::gui::EguiExtra; -use egui::{ - Align2, Area, Context, InnerResponse, Order, Pos2, Rect, Response, TextWrapMode, Ui, Vec2, -}; +use crate::gui_egui::helper::basic_component_gui; +use egui::{Pos2, Rect, Response, Ui, Vec2}; #[typetag::serde] impl EguiComponent for PassThrough { /// TODO this need to be rewritten when newer helper functions becomes available fn render( &self, - ui: &mut Ui, + _ui: &mut Ui, _context: &mut EguiExtra, _simulator: Option<&mut Simulator>, - offset: Vec2, - scale: f32, - clip_rect: Rect, + _offset: Vec2, + _scale: f32, + _clip_rect: Rect, _editor_mode: EditorMode, ) -> Option> { - fn component_area( - id: String, - ctx: &Context, - pos: impl Into, - content: impl FnOnce(&mut Ui) -> R, - ) -> InnerResponse { - Area::new(egui::Id::from(id)) - .order(Order::Middle) - .current_pos(pos) - .movable(false) - .enabled(true) - .interactable(false) - .pivot(Align2::CENTER_CENTER) - .constrain(false) - .show(ctx, content) - } - - let offset: Vec2 = offset.into(); - - let r = component_area( - self.get_id_ports().0, - ui.ctx(), - Pos2::from(self.get_pos()) * scale + offset, - |ui| { - ui.set_clip_rect(clip_rect); - - ui.style_mut().wrap_mode = Some(TextWrapMode::Extend); - - for (_text_style, font) in ui.style_mut().text_styles.iter_mut() { - font.size *= scale; - } - ui.spacing_mut().button_padding *= scale; - ui.spacing_mut().item_spacing *= scale; - ui.spacing_mut().combo_height *= scale; - ui.spacing_mut().combo_width *= scale; - ui.spacing_mut().icon_width *= scale; - ui.spacing_mut().icon_width_inner *= scale; - ui.spacing_mut().icon_spacing *= scale; - ui.spacing_mut().interact_size *= scale; - - let mut group = egui::containers::Frame::group(ui.style()); - group.inner_margin *= scale; - group.rounding *= scale; - // group.fill = Color32::LIGHT_RED; // Use this ween component background is implemented, probably when we implement dark mode - group - .show(ui, |ui| { - ui.label("➡️"); - }) - .response - }, - ) - .inner; - Some(vec![r]) + Some(vec![]) } fn render_editor( &mut self, - _ui: &mut Ui, + ui: &mut Ui, _context: &mut EguiExtra, - _simulator: Option<&mut Simulator>, - _offset: Vec2, - _scale: f32, - _clip_rect: Rect, + simulator: Option<&mut Simulator>, + offset: Vec2, + scale: f32, + clip_rect: Rect, _id_ports: &[(crate::common::Id, Ports)], _grid: &GridOptions, _editor_mode: EditorMode, ) -> EditorRenderReturn { + basic_component_gui(self, &simulator, ui.ctx(), offset, scale, clip_rect, |ui| { + ui.label("\u{27A1}"); + }); EditorRenderReturn { delete: false, resp: Some(vec![]), From fbce8ab83fbaf22ca147a043f9d3375977df6f99 Mon Sep 17 00:00:00 2001 From: Olle Ronstad Date: Fri, 11 Oct 2024 18:09:23 +0200 Subject: [PATCH 15/18] fixed clippy stuff note some clippy stuff was not cause by this branch and therefore not fixed --- mips-lib/src/components/mips_alu_forward.rs | 15 ++++++--------- mips-lib/src/components/mips_data_forward.rs | 8 +------- src/gui_egui/components/pass_through.rs | 2 +- 3 files changed, 8 insertions(+), 17 deletions(-) diff --git a/mips-lib/src/components/mips_alu_forward.rs b/mips-lib/src/components/mips_alu_forward.rs index 2c2a354..28ec66d 100644 --- a/mips-lib/src/components/mips_alu_forward.rs +++ b/mips-lib/src/components/mips_alu_forward.rs @@ -67,16 +67,13 @@ impl Component for AluForward { let we_in: u32 = simulator.get_input_value(&self.we_in).try_into().unwrap(); let load_in: u32 = simulator.get_input_value(&self.load_in).try_into().unwrap(); - let equal: u32 = (a_in == b_in) as u32; - let result: u32; - - // if the instruction is write forward - // dont forward if its some from adrs calc for lw or sw - if we_in == 1 && load_in == NO_OP { - result = equal; + // if the instruction writes to regfile, forward + // don't forward if its some from adrs calc for lw or sw + let result: u32 = if we_in == 1 && load_in == NO_OP { + (a_in == b_in) as u32 } else { - result = 0; - } + 0 + }; simulator.set_out_value(&self.id, ALU_FORWARD_OUT_ID, SignalValue::Data(result)); Ok(()) diff --git a/mips-lib/src/components/mips_data_forward.rs b/mips-lib/src/components/mips_data_forward.rs index eb02061..70bc0fc 100644 --- a/mips-lib/src/components/mips_data_forward.rs +++ b/mips-lib/src/components/mips_data_forward.rs @@ -58,13 +58,7 @@ impl Component for DataForward { let b_in: u32 = simulator.get_input_value(&self.b_in).try_into().unwrap(); let we_in: u32 = simulator.get_input_value(&self.we_in).try_into().unwrap(); - let equal: u32 = (a_in == b_in) as u32; - let result: u32; - if we_in == 1 { - result = equal; - } else { - result = 0; - } + let result: u32 = if we_in == 1 { (a_in == b_in) as u32 } else { 0 }; simulator.set_out_value(&self.id, DATA_FORWARD_OUT_ID, SignalValue::Data(result)); Ok(()) diff --git a/src/gui_egui/components/pass_through.rs b/src/gui_egui/components/pass_through.rs index 289ed7e..771620f 100644 --- a/src/gui_egui/components/pass_through.rs +++ b/src/gui_egui/components/pass_through.rs @@ -1,4 +1,4 @@ -use crate::common::{Component, EguiComponent, Ports, Simulator}; +use crate::common::{EguiComponent, Ports, Simulator}; use crate::components::PassThrough; use crate::gui_egui::editor::{EditorMode, EditorRenderReturn, GridOptions}; use crate::gui_egui::gui::EguiExtra; From ec4a20bd023f289652c5f94fd736a300eef48741 Mon Sep 17 00:00:00 2001 From: pawdzi-7 Date: Fri, 11 Oct 2024 20:22:57 +0200 Subject: [PATCH 16/18] change default to pipelined version, allow unused importsfor dynamic components --- mips-lib/src/main.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/mips-lib/src/main.rs b/mips-lib/src/main.rs index 5a9e989..9d0b4bb 100644 --- a/mips-lib/src/main.rs +++ b/mips-lib/src/main.rs @@ -3,12 +3,15 @@ use std::path::PathBuf; #[cfg(feature = "gui-egui")] use syncrim::gui_egui::editor::Library; use syncrim::{common::ComponentStore, fern::fern_setup}; +// this is actually loaded dynamically, so it is used. +#[allow(unused_imports)] +use mips_lib::components::*; /// Simple program to greet a person #[derive(Parser, Debug)] #[command(author, version, about, long_about = None)] struct Args { /// Path to the model to load on startup - #[arg(short, long, default_value = "mips_singel_cycle.json")] + #[arg(short, long, default_value = "mips_pipe.json")] model: String, } From 39591c38545c127a9d609b544d0284f2b056011d Mon Sep 17 00:00:00 2001 From: pawdzi-7 Date: Sat, 12 Oct 2024 22:42:09 +0200 Subject: [PATCH 17/18] move default memview row to show addr 0x1000, remove default breakpoint --- mips-lib/mips_pipe.json | 2066 ++++++++------------------------------- 1 file changed, 399 insertions(+), 1667 deletions(-) diff --git a/mips-lib/mips_pipe.json b/mips-lib/mips_pipe.json index cb025a0..75ea515 100644 --- a/mips-lib/mips_pipe.json +++ b/mips-lib/mips_pipe.json @@ -3,10 +3,7 @@ { "type": "Register", "id": "pc+4_reg", - "pos": [ - 240.0, - 380.0 - ], + "pos": [240.0, 380.0], "r_in": { "id": "pc+4", "field": "add_out" @@ -15,10 +12,7 @@ { "type": "Register", "id": "mux_b2_reg", - "pos": [ - 1100.0, - 420.0 - ], + "pos": [1100.0, 420.0], "r_in": { "id": "pc+4_pass", "field": "pass_through_out" @@ -27,10 +21,7 @@ { "type": "Register", "id": "pc", - "pos": [ - 0.0, - 390.0 - ], + "pos": [0.0, 390.0], "r_in": { "id": "mux_jump_merge", "field": "mux_out" @@ -39,10 +30,7 @@ { "type": "Register", "id": "zero_extend_reg", - "pos": [ - 1100.0, - 110.0 - ], + "pos": [1100.0, 110.0], "r_in": { "id": "instruction_split", "field": "shamt_out" @@ -51,10 +39,7 @@ { "type": "Register", "id": "reg_addr_reg", - "pos": [ - 1920.0, - 520.0 - ], + "pos": [1920.0, 520.0], "r_in": { "id": "reg_addr_MEM_pass", "field": "pass_through_out" @@ -63,10 +48,7 @@ { "type": "Register", "id": "operand_a_reg", - "pos": [ - 1100.0, - 215.0 - ], + "pos": [1100.0, 215.0], "r_in": { "id": "alu_forward_A_mux", "field": "mux_out" @@ -75,10 +57,7 @@ { "type": "Register", "id": "control_MEM_reg", - "pos": [ - 1470.0, - -40.0 - ], + "pos": [1470.0, -40.0], "r_in": { "id": "control_EX_pass", "field": "pass_through_out" @@ -87,10 +66,7 @@ { "type": "Register", "id": "mux_b3_reg", - "pos": [ - 1100.0, - 475.0 - ], + "pos": [1100.0, 475.0], "r_in": { "id": "signzero_extend", "field": "sz_out" @@ -99,10 +75,7 @@ { "type": "Register", "id": "result_reg_EX", - "pos": [ - 1920.0, - 270.0 - ], + "pos": [1920.0, 270.0], "r_in": { "id": "write_back_mux", "field": "mux_out" @@ -111,10 +84,7 @@ { "type": "Register", "id": "reg_addr_EX_reg", - "pos": [ - 1100.0, - 520.0 - ], + "pos": [1100.0, 520.0], "r_in": { "id": "mux_write_addr", "field": "mux_out" @@ -123,10 +93,7 @@ { "type": "Register", "id": "operand_b_reg", - "pos": [ - 1100.0, - 325.0 - ], + "pos": [1100.0, 325.0], "r_in": { "id": "alu_forward_B_mux", "field": "mux_out" @@ -135,10 +102,7 @@ { "type": "Register", "id": "control_EX_reg", - "pos": [ - 1100.0, - -40.0 - ], + "pos": [1100.0, -40.0], "r_in": { "id": "InMem_pass", "field": "pass_through_out" @@ -147,10 +111,7 @@ { "type": "Register", "id": "reg_addr_MEM_reg", - "pos": [ - 1470.0, - 520.0 - ], + "pos": [1470.0, 520.0], "r_in": { "id": "reg_addr_EX_pass", "field": "pass_through_out" @@ -159,10 +120,7 @@ { "type": "Register", "id": "InMem_reg", - "pos": [ - 240.0, - 475.0 - ], + "pos": [240.0, 475.0], "r_in": { "id": "instr_mem", "field": "instruction" @@ -171,10 +129,7 @@ { "type": "Register", "id": "alu_reg", - "pos": [ - 1470.0, - 250.0 - ], + "pos": [1470.0, 250.0], "r_in": { "id": "alu", "field": "alu_out" @@ -183,10 +138,7 @@ { "type": "Register", "id": "merge_reg", - "pos": [ - 240.0, - 580.0 - ], + "pos": [240.0, 580.0], "r_in": { "id": "jump_merge", "field": "merge_out" @@ -195,10 +147,7 @@ { "type": "Register", "id": "data_MEM_reg", - "pos": [ - 1470.0, - 585.0 - ], + "pos": [1470.0, 585.0], "r_in": { "id": "operand_b_pass", "field": "pass_through_out" @@ -207,10 +156,7 @@ { "type": "Register", "id": "control_WB_reg", - "pos": [ - 1920.0, - -40.0 - ], + "pos": [1920.0, -40.0], "r_in": { "id": "control_MEM_pass", "field": "pass_through_out" @@ -219,19 +165,13 @@ { "type": "Constant", "id": "+4", - "pos": [ - 80.0, - 400.0 - ], + "pos": [80.0, 400.0], "value": { "data": { "Data": 4 }, "fmt": { - "Hex": [ - "_32", - false - ] + "Hex": ["_32", false] } } }, @@ -239,18 +179,9 @@ "type": "Wire", "id": "from pc:register_out to instr_mem:pc", "pos": [ - [ - 10.0, - 390.0 - ], - [ - 30.0, - 390.0 - ], - [ - 31.0, - 551.5 - ] + [10.0, 390.0], + [30.0, 390.0], + [31.0, 551.5] ], "input": { "id": "pc", @@ -261,14 +192,8 @@ "type": "Wire", "id": "from zero_extend_reg:register_out to zero_extend_for_shamt:signal_in", "pos": [ - [ - 1110.0, - 110.0 - ], - [ - 1124.0, - 110.0 - ] + [1110.0, 110.0], + [1124.0, 110.0] ], "input": { "id": "zero_extend_reg", @@ -279,22 +204,10 @@ "type": "Wire", "id": "from mux_b2_reg:register_out to mux_source_b:in1", "pos": [ - [ - 1110.0, - 420.0 - ], - [ - 1160.0, - 420.0 - ], - [ - 1160.0, - 325.0 - ], - [ - 1230.0, - 325.0 - ] + [1110.0, 420.0], + [1160.0, 420.0], + [1160.0, 325.0], + [1230.0, 325.0] ], "input": { "id": "mux_b2_reg", @@ -305,26 +218,11 @@ "type": "Wire", "id": "from reg_addr_reg:register_out to reg_file:write_address_in", "pos": [ - [ - 1930.0, - 520.0 - ], - [ - 1950.0, - 520.0 - ], - [ - 1951.6001, - 642.0 - ], - [ - 641.60004, - 642.0 - ], - [ - 640.0, - 406.0 - ] + [1930.0, 520.0], + [1950.0, 520.0], + [1951.6001, 642.0], + [641.60004, 642.0], + [640.0, 406.0] ], "input": { "id": "reg_addr_reg", @@ -334,10 +232,7 @@ { "type": "ZeroExtend", "id": "zero_extend_for_shamt", - "pos": [ - 1165.0, - 110.0 - ], + "pos": [1165.0, 110.0], "signal_in": { "id": "zero_extend_reg", "field": "register_out" @@ -347,22 +242,10 @@ "type": "Wire", "id": "from zero_extend_for_shamt:zero_extend_out to mux_source_a:in0", "pos": [ - [ - 1206.0, - 110.0 - ], - [ - 1220.0, - 110.0 - ], - [ - 1220.0, - 190.0 - ], - [ - 1230.0, - 190.0 - ] + [1206.0, 110.0], + [1220.0, 110.0], + [1220.0, 190.0], + [1230.0, 190.0] ], "input": { "id": "zero_extend_for_shamt", @@ -372,10 +255,7 @@ { "type": "ControlUnit", "id": "control_unit_3", - "pos": [ - 1695.0, - 0.0 - ], + "pos": [1695.0, 0.0], "a_in": { "id": "control_MEM_reg", "field": "register_out" @@ -385,57 +265,32 @@ "type": "Wire", "id": "from control_unit_3:mem_mode to data_mem:data_mem_op_in", "pos": [ - [ - 1690.0, - 13.5 - ], - [ - 1690.0, - 551.5 - ] + [1690.0, 13.5], + [1690.0, 551.5] ], "input": { "id": "control_unit_3", "field": "mem_mode" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from control_unit_3:reg_write_src to write_back_mux:select", "pos": [ - [ - 1790.0, - 13.5 - ], - [ - 1790.0, - 240.0 - ] + [1790.0, 13.5], + [1790.0, 240.0] ], "input": { "id": "control_unit_3", "field": "reg_write_src" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "PassThrough", "id": "control_MEM_pass", - "pos": [ - 1510.0, - -40.0 - ], + "pos": [1510.0, -40.0], "input": { "id": "control_MEM_reg", "field": "register_out" @@ -445,22 +300,10 @@ "type": "Wire", "id": "from operand_a_reg:register_out to mux_source_a:in1", "pos": [ - [ - 1110.0, - 215.0 - ], - [ - 1140.0, - 215.0 - ], - [ - 1140.0, - 210.0 - ], - [ - 1230.0, - 210.0 - ] + [1110.0, 215.0], + [1140.0, 215.0], + [1140.0, 210.0], + [1230.0, 210.0] ], "input": { "id": "operand_a_reg", @@ -471,26 +314,11 @@ "type": "Wire", "id": "from reg_addr_EX_reg:register_out to alu_forward_B:a_in", "pos": [ - [ - 1130.0, - 520.0 - ], - [ - 1130.0, - 497.0 - ], - [ - 930.0, - 497.0 - ], - [ - 930.0, - 395.0 - ], - [ - 960.0, - 395.0 - ] + [1130.0, 520.0], + [1130.0, 497.0], + [930.0, 497.0], + [930.0, 395.0], + [960.0, 395.0] ], "input": { "id": "reg_addr_EX_reg", @@ -500,10 +328,7 @@ { "type": "PassThrough", "id": "reg_addr_EX_pass", - "pos": [ - 1165.0, - 520.0 - ], + "pos": [1165.0, 520.0], "input": { "id": "reg_addr_EX_reg", "field": "register_out" @@ -513,14 +338,8 @@ "type": "Wire", "id": "from reg_addr_EX_reg:register_out to reg_addr_EX_pass:pass_through_in", "pos": [ - [ - 1110.0, - 520.0 - ], - [ - 1165.0, - 520.0 - ] + [1110.0, 520.0], + [1165.0, 520.0] ], "input": { "id": "reg_addr_EX_reg", @@ -531,37 +350,20 @@ "type": "Wire", "id": "from control_unit_3:reg_write_enable to data_forward_B:we_in", "pos": [ - [ - 820.0, - 155.0 - ], - [ - 820.0, - 395.0 - ], - [ - 808.5, - 395.0 - ] + [820.0, 155.0], + [820.0, 395.0], + [808.5, 395.0] ], "input": { "id": "control_unit_3", "field": "reg_write_enable" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "InstrMem", "id": "instr_mem", - "pos": [ - 45.0, - 585.0 - ], + "pos": [45.0, 585.0], "pc": { "id": "pc", "field": "register_out" @@ -616,44 +418,11 @@ ] }, "register_values": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 2147483648, - 0, - 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 2147483648, 0, 0 ], "dynamic_symbols": { - "PC_IM": [ - 0, - true - ] + "PC_IM": [0, true] }, "break_points": [] } @@ -661,10 +430,7 @@ { "type": "JumpMerge", "id": "jump_merge", - "pos": [ - 180.0, - 530.0 - ], + "pos": [180.0, 530.0], "instr_addr_in": { "id": "pc", "field": "register_out" @@ -678,18 +444,9 @@ "type": "Wire", "id": "from jump_merge:merge_out to merge_reg:r_in", "pos": [ - [ - 180.0, - 544.0 - ], - [ - 180.0, - 580.0 - ], - [ - 230.0, - 580.0 - ] + [180.0, 544.0], + [180.0, 580.0], + [230.0, 580.0] ], "input": { "id": "jump_merge", @@ -700,14 +457,8 @@ "type": "Wire", "id": "from instr_mem:instruction to jump_merge:merge_jump_addr_in", "pos": [ - [ - 85.0, - 530.0 - ], - [ - 140.0, - 530.0 - ] + [85.0, 530.0], + [140.0, 530.0] ], "input": { "id": "instr_mem", @@ -718,14 +469,8 @@ "type": "Wire", "id": "from operand_b_reg:register_out to operand_b_pass:pass_through_in", "pos": [ - [ - 1110.0, - 325.0 - ], - [ - 1140.0, - 325.0 - ] + [1110.0, 325.0], + [1140.0, 325.0] ], "input": { "id": "operand_b_reg", @@ -736,18 +481,9 @@ "type": "Wire", "id": "from instr_mem:instruction to InMem_reg:r_in", "pos": [ - [ - 85.0, - 551.5 - ], - [ - 85.0, - 475.0 - ], - [ - 230.0, - 475.0 - ] + [85.0, 551.5], + [85.0, 475.0], + [230.0, 475.0] ], "input": { "id": "instr_mem", @@ -757,19 +493,13 @@ { "type": "Constant", "id": "0_a_inp", - "pos": [ - 1190.0, - 230.0 - ], + "pos": [1190.0, 230.0], "value": { "data": { "Data": 4 }, "fmt": { - "Hex": [ - "_32", - false - ] + "Hex": ["_32", false] } } }, @@ -777,18 +507,9 @@ "type": "Wire", "id": "from pc:register_out to jump_merge:merge_instr_addr_in", "pos": [ - [ - 30.0, - 465.0 - ], - [ - 180.0, - 465.0 - ], - [ - 180.0, - 517.0 - ] + [30.0, 465.0], + [180.0, 465.0], + [180.0, 517.0] ], "input": { "id": "pc", @@ -799,22 +520,10 @@ "type": "Wire", "id": "from mux_b3_reg:register_out to mux_source_b:in2", "pos": [ - [ - 1110.0, - 475.0 - ], - [ - 1180.0, - 475.0 - ], - [ - 1180.0, - 345.0 - ], - [ - 1230.0, - 345.0 - ] + [1110.0, 475.0], + [1180.0, 475.0], + [1180.0, 345.0], + [1230.0, 345.0] ], "input": { "id": "mux_b3_reg", @@ -825,14 +534,8 @@ "type": "Wire", "id": "from control_EX_reg:register_out to control_EX_pass:pass_through_in", "pos": [ - [ - 1110.0, - -40.0 - ], - [ - 1140.0, - -40.0 - ] + [1110.0, -40.0], + [1140.0, -40.0] ], "input": { "id": "control_EX_reg", @@ -843,14 +546,8 @@ "type": "Wire", "id": "from control_EX_reg:register_out to control_unit_2:control_unit_instr_in", "pos": [ - [ - 1110.0, - -40.0 - ], - [ - 1079.0, - 0.0 - ] + [1110.0, -40.0], + [1079.0, 0.0] ], "input": { "id": "control_EX_reg", @@ -860,10 +557,7 @@ { "type": "PassThrough", "id": "control_EX_pass", - "pos": [ - 1140.0, - -40.0 - ], + "pos": [1140.0, -40.0], "input": { "id": "control_EX_reg", "field": "register_out" @@ -873,14 +567,8 @@ "type": "Wire", "id": "from control_EX_pass:pass_through_out to control_MEM_reg:r_in", "pos": [ - [ - 1140.0, - -40.0 - ], - [ - 1460.0, - -40.0 - ] + [1140.0, -40.0], + [1460.0, -40.0] ], "input": { "id": "control_EX_pass", @@ -890,10 +578,7 @@ { "type": "PassThrough", "id": "pc+4_pass", - "pos": [ - 260.0, - 370.0 - ], + "pos": [260.0, 370.0], "input": { "id": "pc+4_reg", "field": "register_out" @@ -903,18 +588,9 @@ "type": "Wire", "id": "from pc+4_pass:pass_through_out to mux_b2_reg:r_in", "pos": [ - [ - 260.0, - 380.0 - ], - [ - 260.0, - 420.0 - ], - [ - 1090.0, - 420.0 - ] + [260.0, 380.0], + [260.0, 420.0], + [1090.0, 420.0] ], "input": { "id": "pc+4_pass", @@ -925,14 +601,8 @@ "type": "Wire", "id": "from reg_addr_MEM_reg:register_out to reg_addr_MEM_pass:pass_through_in", "pos": [ - [ - 1480.0, - 520.0 - ], - [ - 1520.0, - 520.0 - ] + [1480.0, 520.0], + [1520.0, 520.0] ], "input": { "id": "reg_addr_MEM_reg", @@ -943,14 +613,8 @@ "type": "Wire", "id": "from reg_addr_MEM_reg:register_out to data_forward_B:a_in", "pos": [ - [ - 760.0, - 395.0 - ], - [ - 790.0, - 395.0 - ] + [760.0, 395.0], + [790.0, 395.0] ], "input": { "id": "reg_addr_MEM_reg", @@ -961,14 +625,8 @@ "type": "Wire", "id": "from 0_a_inp:constant_out to mux_source_a:in2", "pos": [ - [ - 1190.0, - 230.0 - ], - [ - 1230.0, - 230.0 - ] + [1190.0, 230.0], + [1230.0, 230.0] ], "input": { "id": "0_a_inp", @@ -979,50 +637,24 @@ "type": "Wire", "id": "from control_unit_3:reg_write_enable to data_forward_A:we_in", "pos": [ - [ - 1540.0, - 13.5 - ], - [ - 1540.0, - 80.0 - ], - [ - 820.0, - 80.0 - ], - [ - 820.0, - 155.0 - ], - [ - 809.0, - 155.0 - ] + [1540.0, 13.5], + [1540.0, 80.0], + [820.0, 80.0], + [820.0, 155.0], + [809.0, 155.0] ], "input": { "id": "control_unit_3", "field": "reg_write_enable" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from +4:constant_out to pc+4:b_in", "pos": [ - [ - 80.0, - 400.0 - ], - [ - 110.0, - 400.0 - ] + [80.0, 400.0], + [110.0, 400.0] ], "input": { "id": "+4", @@ -1032,10 +664,7 @@ { "type": "ControlUnit", "id": "control_unit_2", - "pos": [ - 1285.0, - 0.0 - ], + "pos": [1285.0, 0.0], "a_in": { "id": "control_EX_reg", "field": "register_out" @@ -1045,33 +674,19 @@ "type": "Wire", "id": "from control_unit_2:alu_src_a to mux_source_a:select", "pos": [ - [ - 1240.0, - 13.5 - ], - [ - 1240.0, - 170.0 - ] + [1240.0, 13.5], + [1240.0, 170.0] ], "input": { "id": "control_unit_2", "field": "alu_src_a" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Mux", "id": "mux_source_a", - "pos": [ - 1250.0, - 210.0 - ], + "pos": [1250.0, 210.0], "select": { "id": "control_unit_2", "field": "alu_src_a" @@ -1096,22 +711,10 @@ "type": "Wire", "id": "from mux_source_a:mux_out to alu:full_add_a_in", "pos": [ - [ - 1260.0, - 210.0 - ], - [ - 1320.0, - 210.0 - ], - [ - 1320.0, - 220.0 - ], - [ - 1380.0, - 220.0 - ] + [1260.0, 210.0], + [1320.0, 210.0], + [1320.0, 220.0], + [1380.0, 220.0] ], "input": { "id": "mux_source_a", @@ -1122,193 +725,94 @@ "type": "Wire", "id": "from control_unit_2:alu_src_b to mux_source_b:select", "pos": [ - [ - 1280.0, - 13.5 - ], - [ - 1280.0, - 270.0 - ], - [ - 1240.0, - 270.0 - ], - [ - 1240.0, - 285.0 - ] + [1280.0, 13.5], + [1280.0, 270.0], + [1240.0, 270.0], + [1240.0, 285.0] ], "input": { "id": "control_unit_2", "field": "alu_src_b" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from control_unit_2:alu_op to alu:full_add_op_in", "pos": [ - [ - 1390.0, - 13.5 - ], - [ - 1390.0, - 210.0 - ] + [1390.0, 13.5], + [1390.0, 210.0] ], "input": { "id": "control_unit_2", "field": "alu_op" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from control_unit_2:mem_mode to alu_forward_B:load_in", "pos": [ - [ - 1000.0, - 160.0 - ], - [ - 1000.0, - 402.5 - ], - [ - 980.0, - 402.5 - ] + [1000.0, 160.0], + [1000.0, 402.5], + [980.0, 402.5] ], "input": { "id": "control_unit_2", "field": "mem_mode" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from control_unit_2:reg_write_enable to alu_forward_A:we_in", "pos": [ - [ - 1140.0, - 13.5 - ], - [ - 1140.0, - 70.0 - ], - [ - 990.0, - 70.0 - ], - [ - 990.0, - 150.0 - ], - [ - 980.0, - 150.0 - ] + [1140.0, 13.5], + [1140.0, 70.0], + [990.0, 70.0], + [990.0, 150.0], + [980.0, 150.0] ], "input": { "id": "control_unit_2", "field": "reg_write_enable" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from control_unit_2:reg_write_enable to alu_forward_B:we_in", "pos": [ - [ - 990.0, - 150.0 - ], - [ - 990.0, - 390.0 - ], - [ - 980.0, - 390.0 - ] + [990.0, 150.0], + [990.0, 390.0], + [980.0, 390.0] ], "input": { "id": "control_unit_2", "field": "reg_write_enable" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from control_unit_2:mem_mode to alu_forward_A:load_in", "pos": [ - [ - 1110.0, - 13.5 - ], - [ - 1110.0, - 50.0 - ], - [ - 1000.0, - 50.0 - ], - [ - 1000.0, - 160.0 - ], - [ - 980.0, - 160.0 - ] + [1110.0, 13.5], + [1110.0, 50.0], + [1000.0, 50.0], + [1000.0, 160.0], + [980.0, 160.0] ], "input": { "id": "control_unit_2", "field": "mem_mode" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "ControlUnit", "id": "control_unit_1", - "pos": [ - 670.0, - 0.0 - ], + "pos": [670.0, 0.0], "a_in": { "id": "InMem_reg", "field": "register_out" @@ -1318,42 +822,22 @@ "type": "Wire", "id": "from control_unit_1:reg_dest to mux_write_addr:select", "pos": [ - [ - 710.0, - 14.0 - ], - [ - 710.0, - 480.0 - ] + [710.0, 14.0], + [710.0, 480.0] ], "input": { "id": "control_unit_1", "field": "reg_dest" }, - "color_rgba": [ - 0, - 0, - 0, - 30 - ] + "color_rgba": [0, 0, 0, 30] }, { "type": "Wire", "id": "from InMem_reg:register_out to control_unit_1:control_unit_instr_in", "pos": [ - [ - 434.0, - -40.0 - ], - [ - 434.0, - 0.0 - ], - [ - 464.0, - 0.0 - ] + [434.0, -40.0], + [434.0, 0.0], + [464.0, 0.0] ], "input": { "id": "InMem_reg", @@ -1363,10 +847,7 @@ { "type": "InstrSplit", "id": "instruction_split", - "pos": [ - 400.0, - 275.0 - ], + "pos": [400.0, 275.0], "instruction_in": { "id": "InMem_reg", "field": "register_out" @@ -1375,10 +856,7 @@ { "type": "SignZeroExtend", "id": "signzero_extend", - "pos": [ - 400.0, - 475.0 - ], + "pos": [400.0, 475.0], "signzero_signal_in": { "id": "instruction_split", "field": "immediate_out" @@ -1392,30 +870,12 @@ "type": "Wire", "id": "from signzero_extend:sz_out to branch_shift:shift_in", "pos": [ - [ - 458.5, - 475.0 - ], - [ - 468.5, - 475.0 - ], - [ - 468.5, - 560.0 - ], - [ - 356.0, - 560.0 - ], - [ - 356.0, - 585.0 - ], - [ - 366.5, - 585.0 - ] + [458.5, 475.0], + [468.5, 475.0], + [468.5, 560.0], + [356.0, 560.0], + [356.0, 585.0], + [366.5, 585.0] ], "input": { "id": "signzero_extend", @@ -1426,14 +886,8 @@ "type": "Wire", "id": "from signzero_extend:sz_out to mux_b3_reg:r_in", "pos": [ - [ - 469.0, - 475.0 - ], - [ - 1090.0, - 475.0 - ] + [469.0, 475.0], + [1090.0, 475.0] ], "input": { "id": "signzero_extend", @@ -1443,10 +897,7 @@ { "type": "ShiftConst", "id": "branch_shift", - "pos": [ - 400.0, - 585.0 - ], + "pos": [400.0, 585.0], "signal_in": { "id": "signzero_extend", "field": "sz_out" @@ -1456,10 +907,7 @@ { "type": "Add", "id": "pc_add_branch", - "pos": [ - 530.0, - 565.0 - ], + "pos": [530.0, 565.0], "a_in": { "id": "pc+4_reg", "field": "register_out" @@ -1474,30 +922,12 @@ "type": "Wire", "id": "from pc_add_branch:add_out to mux_jump_merge:in0", "pos": [ - [ - 550.0, - 565.0 - ], - [ - 560.0, - 565.0 - ], - [ - 561.0, - 640.0 - ], - [ - -114.0, - 640.0 - ], - [ - -114.0, - 360.0 - ], - [ - -74.0, - 360.0 - ] + [550.0, 565.0], + [560.0, 565.0], + [561.0, 640.0], + [-114.0, 640.0], + [-114.0, 360.0], + [-74.0, 360.0] ], "input": { "id": "pc_add_branch", @@ -1508,18 +938,9 @@ "type": "Wire", "id": "from instruction_split:rt_out to data_forward_B:b_in", "pos": [ - [ - 585.0, - 465.0 - ], - [ - 800.0, - 465.0 - ], - [ - 800.0, - 408.0 - ] + [585.0, 465.0], + [800.0, 465.0], + [800.0, 408.0] ], "input": { "id": "instruction_split", @@ -1529,10 +950,7 @@ { "type": "AluForward", "id": "alu_forward_B", - "pos": [ - 970.0, - 395.0 - ], + "pos": [970.0, 395.0], "a_in": { "id": "reg_addr_EX_reg", "field": "register_out" @@ -1554,14 +972,8 @@ "type": "Wire", "id": "from alu_forward_B:equals_forward_out to alu_forward_B_mux:select", "pos": [ - [ - 970.0, - 381.0 - ], - [ - 960.0, - 355.0 - ] + [970.0, 381.0], + [960.0, 355.0] ], "input": { "id": "alu_forward_B", @@ -1571,10 +983,7 @@ { "type": "AluForward", "id": "alu_forward_A", - "pos": [ - 970.0, - 155.0 - ], + "pos": [970.0, 155.0], "a_in": { "id": "reg_addr_EX_reg", "field": "register_out" @@ -1596,14 +1005,8 @@ "type": "Wire", "id": "from alu_forward_A:equals_forward_out to alu_forward_A_mux:select", "pos": [ - [ - 970.0, - 167.0 - ], - [ - 960.0, - 195.0 - ] + [970.0, 167.0], + [960.0, 195.0] ], "input": { "id": "alu_forward_A", @@ -1614,18 +1017,9 @@ "type": "Wire", "id": "from instruction_split:rt_out to alu_forward_B:b_in", "pos": [ - [ - 800.0, - 465.0 - ], - [ - 970.0, - 465.0 - ], - [ - 970.0, - 408.0 - ] + [800.0, 465.0], + [970.0, 465.0], + [970.0, 408.0] ], "input": { "id": "instruction_split", @@ -1636,26 +1030,11 @@ "type": "Wire", "id": "from instruction_split:immediate_out to signzero_extend:signzero_signal_in", "pos": [ - [ - 400.0, - 381.5 - ], - [ - 400.0, - 391.0 - ], - [ - 320.0, - 391.0 - ], - [ - 320.0, - 475.5 - ], - [ - 341.5, - 475.0 - ] + [400.0, 381.5], + [400.0, 391.0], + [320.0, 391.0], + [320.0, 475.5], + [341.5, 475.0] ], "input": { "id": "instruction_split", @@ -1666,18 +1045,9 @@ "type": "Wire", "id": "from instruction_split:shamt_out to zero_extend_reg:r_in", "pos": [ - [ - 395.0, - 170.0 - ], - [ - 395.0, - 100.0 - ], - [ - 1090.0, - 100.0 - ] + [395.0, 170.0], + [395.0, 100.0], + [1090.0, 100.0] ], "input": { "id": "instruction_split", @@ -1688,22 +1058,10 @@ "type": "Wire", "id": "from instruction_split:rt_out to mux_write_addr:in0", "pos": [ - [ - 430.0, - 332.0 - ], - [ - 495.19995, - 332.8 - ], - [ - 494.39996, - 500.0 - ], - [ - 700.0, - 500.0 - ] + [430.0, 332.0], + [495.19995, 332.8], + [494.39996, 500.0], + [700.0, 500.0] ], "input": { "id": "instruction_split", @@ -1714,18 +1072,9 @@ "type": "Wire", "id": "from instruction_split:rs_out to data_forward_A:b_in", "pos": [ - [ - 585.0, - 120.0 - ], - [ - 800.0, - 120.0 - ], - [ - 800.0, - 142.0 - ] + [585.0, 120.0], + [800.0, 120.0], + [800.0, 142.0] ], "input": { "id": "instruction_split", @@ -1735,10 +1084,7 @@ { "type": "DataForward", "id": "data_forward_A", - "pos": [ - 800.0, - 155.0 - ], + "pos": [800.0, 155.0], "a_in": { "id": "reg_addr_MEM_reg", "field": "register_out" @@ -1756,14 +1102,8 @@ "type": "Wire", "id": "from data_forward_A:data_forward_out to data_forward_A_mux:select", "pos": [ - [ - 800.0, - 168.0 - ], - [ - 790.0, - 195.0 - ] + [800.0, 168.0], + [790.0, 195.0] ], "input": { "id": "data_forward_A", @@ -1774,18 +1114,9 @@ "type": "Wire", "id": "from instruction_split:rs_out to alu_forward_A:b_in", "pos": [ - [ - 800.0, - 120.0 - ], - [ - 970.0, - 120.0 - ], - [ - 970.0, - 142.0 - ] + [800.0, 120.0], + [970.0, 120.0], + [970.0, 142.0] ], "input": { "id": "instruction_split", @@ -1796,14 +1127,8 @@ "type": "Wire", "id": "from InMem_reg:register_out to InMem_pass:pass_through_in", "pos": [ - [ - 250.0, - 475.0 - ], - [ - 250.0, - 475.0 - ] + [250.0, 475.0], + [250.0, 475.0] ], "input": { "id": "InMem_reg", @@ -1814,22 +1139,10 @@ "type": "Wire", "id": "from alu_reg:register_out to write_back_mux:in0", "pos": [ - [ - 1480.0, - 250.0 - ], - [ - 1750.0, - 250.0 - ], - [ - 1750.0, - 260.0 - ], - [ - 1780.0, - 260.0 - ] + [1480.0, 250.0], + [1750.0, 250.0], + [1750.0, 260.0], + [1780.0, 260.0] ], "input": { "id": "alu_reg", @@ -1839,10 +1152,7 @@ { "type": "DataForward", "id": "data_forward_B", - "pos": [ - 800.0, - 395.0 - ], + "pos": [800.0, 395.0], "a_in": { "id": "reg_addr_MEM_reg", "field": "register_out" @@ -1860,14 +1170,8 @@ "type": "Wire", "id": "from data_forward_B:data_forward_out to data_forward_B_mux:select", "pos": [ - [ - 800.0, - 382.0 - ], - [ - 790.0, - 355.0 - ] + [800.0, 382.0], + [790.0, 355.0] ], "input": { "id": "data_forward_B", @@ -1878,14 +1182,8 @@ "type": "Wire", "id": "from control_MEM_pass:pass_through_out to control_WB_reg:r_in", "pos": [ - [ - 1510.0, - -40.0 - ], - [ - 1910.0, - -40.0 - ] + [1510.0, -40.0], + [1910.0, -40.0] ], "input": { "id": "control_MEM_pass", @@ -1896,30 +1194,12 @@ "type": "Wire", "id": "from merge_reg:register_out to mux_jump_merge:in2", "pos": [ - [ - 250.0, - 580.0 - ], - [ - 260.0, - 580.0 - ], - [ - 260.0, - 630.0 - ], - [ - -94.0, - 630.0 - ], - [ - -94.0, - 400.0 - ], - [ - -74.0, - 400.0 - ] + [250.0, 580.0], + [260.0, 580.0], + [260.0, 630.0], + [-94.0, 630.0], + [-94.0, 400.0], + [-74.0, 400.0] ], "input": { "id": "merge_reg", @@ -1930,26 +1210,11 @@ "type": "Wire", "id": "from result_reg_EX:register_out to reg_file:write_data_in", "pos": [ - [ - 1930.0, - 270.0 - ], - [ - 1970.0, - 270.0 - ], - [ - 1970.0, - 655.0 - ], - [ - 620.0, - 655.0 - ], - [ - 620.0, - 406.0 - ] + [1930.0, 270.0], + [1970.0, 270.0], + [1970.0, 655.0], + [620.0, 655.0], + [620.0, 406.0] ], "input": { "id": "result_reg_EX", @@ -1960,18 +1225,9 @@ "type": "Wire", "id": "from pc+4_reg:register_out to pc_add_branch:a_in", "pos": [ - [ - 305.0, - 420.0 - ], - [ - 305.0, - 545.0 - ], - [ - 510.0, - 545.0 - ] + [305.0, 420.0], + [305.0, 545.0], + [510.0, 545.0] ], "input": { "id": "pc+4_reg", @@ -1982,14 +1238,8 @@ "type": "Wire", "id": "from data_MEM_reg:register_out to data_mem:data_mem_write_data_in", "pos": [ - [ - 1480.0, - 585.0 - ], - [ - 1594.0, - 585.0 - ] + [1480.0, 585.0], + [1594.0, 585.0] ], "input": { "id": "data_MEM_reg", @@ -1999,10 +1249,7 @@ { "type": "DataMem", "id": "data_mem", - "pos": [ - 1660.0, - 585.0 - ], + "pos": [1660.0, 585.0], "address_input": { "id": "alu_reg", "field": "register_out" @@ -2025,7 +1272,7 @@ "visible": false, "title": "Data memory view", "id": "data_mem", - "row_offset": 512, + "row_offset": 1024, "max_rows": 1024, "big_endian": true, "format": "ByteAndUtf8", @@ -2069,57 +1316,19 @@ ] }, "register_values": [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 2147483648, - 0, - 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 2147483648, 0, 0 ], "dynamic_symbols": { - "DM_ADRS": [ - 0, - false - ] + "DM_ADRS": [0, false] }, - "break_points": [ - 4176 - ] + "break_points": [] } }, { "type": "Mux", "id": "write_back_mux", - "pos": [ - 1800.0, - 270.0 - ], + "pos": [1800.0, 270.0], "select": { "id": "control_unit_3", "field": "reg_write_src" @@ -2140,14 +1349,8 @@ "type": "Wire", "id": "from write_back_mux:mux_out to data_forward_B_mux:in1", "pos": [ - [ - 740.0, - 335.0 - ], - [ - 780.0, - 335.0 - ] + [740.0, 335.0], + [780.0, 335.0] ], "input": { "id": "write_back_mux", @@ -2158,26 +1361,11 @@ "type": "Wire", "id": "from write_back_mux:mux_out to data_forward_A_mux:in1", "pos": [ - [ - 1830.0, - 270.0 - ], - [ - 1830.0, - 440.0 - ], - [ - 740.0, - 440.0 - ], - [ - 740.0, - 235.0 - ], - [ - 780.0, - 235.0 - ] + [1830.0, 270.0], + [1830.0, 440.0], + [740.0, 440.0], + [740.0, 235.0], + [780.0, 235.0] ], "input": { "id": "write_back_mux", @@ -2188,14 +1376,8 @@ "type": "Wire", "id": "from write_back_mux:mux_out to result_reg_EX:r_in", "pos": [ - [ - 1810.0, - 270.0 - ], - [ - 1910.0, - 270.0 - ] + [1810.0, 270.0], + [1910.0, 270.0] ], "input": { "id": "write_back_mux", @@ -2206,22 +1388,10 @@ "type": "Wire", "id": "from data_mem:data_out to write_back_mux:in1", "pos": [ - [ - 1726.0, - 585.0 - ], - [ - 1750.0, - 585.0 - ], - [ - 1750.0, - 280.0 - ], - [ - 1780.0, - 280.0 - ] + [1726.0, 585.0], + [1750.0, 585.0], + [1750.0, 280.0], + [1780.0, 280.0] ], "input": { "id": "data_mem", @@ -2231,10 +1401,7 @@ { "type": "Mux", "id": "mux_source_b", - "pos": [ - 1250.0, - 325.0 - ], + "pos": [1250.0, 325.0], "select": { "id": "control_unit_2", "field": "alu_src_b" @@ -2259,22 +1426,10 @@ "type": "Wire", "id": "from mux_source_b:mux_out to alu:full_add_b_in", "pos": [ - [ - 1260.0, - 325.0 - ], - [ - 1320.0, - 325.0 - ], - [ - 1320.0, - 280.0 - ], - [ - 1380.0, - 280.0 - ] + [1260.0, 325.0], + [1320.0, 325.0], + [1320.0, 280.0], + [1380.0, 280.0] ], "input": { "id": "mux_source_b", @@ -2284,10 +1439,7 @@ { "type": "ALU", "id": "alu", - "pos": [ - 1400.0, - 250.0 - ], + "pos": [1400.0, 250.0], "a_in": { "id": "mux_source_a", "field": "mux_out" @@ -2305,14 +1457,8 @@ "type": "Wire", "id": "from alu:alu_out to alu_reg:r_in", "pos": [ - [ - 1420.0, - 250.0 - ], - [ - 1460.0, - 250.0 - ] + [1420.0, 250.0], + [1460.0, 250.0] ], "input": { "id": "alu", @@ -2323,18 +1469,9 @@ "type": "Wire", "id": "from alu:alu_out to alu_forward_A_mux:in1", "pos": [ - [ - 910.0, - 335.0 - ], - [ - 910.0, - 235.0 - ], - [ - 950.0, - 235.0 - ] + [910.0, 335.0], + [910.0, 235.0], + [950.0, 235.0] ], "input": { "id": "alu", @@ -2345,26 +1482,11 @@ "type": "Wire", "id": "from alu:alu_out to alu_forward_B_mux:in1", "pos": [ - [ - 1440.0, - 250.0 - ], - [ - 1440.0, - 570.0 - ], - [ - 910.0, - 570.0 - ], - [ - 910.0, - 335.0 - ], - [ - 950.0, - 335.0 - ] + [1440.0, 250.0], + [1440.0, 570.0], + [910.0, 570.0], + [910.0, 335.0], + [950.0, 335.0] ], "input": { "id": "alu", @@ -2375,14 +1497,8 @@ "type": "Wire", "id": "from pc+4_reg:register_out to pc+4_pass:pass_through_in", "pos": [ - [ - 250.0, - 380.0 - ], - [ - 260.0, - 380.0 - ] + [250.0, 380.0], + [260.0, 380.0] ], "input": { "id": "pc+4_reg", @@ -2393,18 +1509,9 @@ "type": "Wire", "id": "from reg_addr_EX_reg:register_out to alu_forward_A:a_in", "pos": [ - [ - 930.0, - 395.0 - ], - [ - 930.0, - 155.0 - ], - [ - 960.0, - 155.0 - ] + [930.0, 395.0], + [930.0, 155.0], + [960.0, 155.0] ], "input": { "id": "reg_addr_EX_reg", @@ -2415,14 +1522,8 @@ "type": "Wire", "id": "from control_WB_reg:register_out to control_unit_4:control_unit_instr_in", "pos": [ - [ - 1930.0, - -40.0 - ], - [ - 2014.0, - 0.0 - ] + [1930.0, -40.0], + [2014.0, 0.0] ], "input": { "id": "control_WB_reg", @@ -2432,10 +1533,7 @@ { "type": "ControlUnit", "id": "control_unit_4", - "pos": [ - 2220.0, - 0.0 - ], + "pos": [2220.0, 0.0], "a_in": { "id": "control_WB_reg", "field": "register_out" @@ -2444,10 +1542,7 @@ { "type": "RegFile", "id": "reg_file", - "pos": [ - 585.0, - 275.0 - ], + "pos": [585.0, 275.0], "rs_address_in": { "id": "instruction_split", "field": "rs_out" @@ -2472,10 +1567,7 @@ { "type": "Mux", "id": "data_forward_A_mux", - "pos": [ - 800.0, - 225.0 - ], + "pos": [800.0, 225.0], "select": { "id": "data_forward_A", "field": "data_forward_out" @@ -2495,10 +1587,7 @@ { "type": "Mux", "id": "alu_forward_A_mux", - "pos": [ - 970.0, - 225.0 - ], + "pos": [970.0, 225.0], "select": { "id": "alu_forward_A", "field": "equals_forward_out" @@ -2519,14 +1608,8 @@ "type": "Wire", "id": "from alu_forward_A_mux:mux_out to branch:branch_rs_value_id", "pos": [ - [ - 1010.0, - 225.0 - ], - [ - 1010.0, - 262.0 - ] + [1010.0, 225.0], + [1010.0, 262.0] ], "input": { "id": "alu_forward_A_mux", @@ -2537,14 +1620,8 @@ "type": "Wire", "id": "from alu_forward_A_mux:mux_out to operand_a_reg:r_in", "pos": [ - [ - 1020.0, - 215.5 - ], - [ - 1090.0, - 215.0 - ] + [1020.0, 215.5], + [1090.0, 215.0] ], "input": { "id": "alu_forward_A_mux", @@ -2555,30 +1632,12 @@ "type": "Wire", "id": "from alu_forward_A_mux:mux_out to mux_jump_merge:in1", "pos": [ - [ - 980.0, - 225.0 - ], - [ - 1020.0, - 225.0 - ], - [ - 1020.0, - 40.0 - ], - [ - -94.0, - 40.0 - ], - [ - -94.0, - 380.0 - ], - [ - -74.0, - 380.0 - ] + [980.0, 225.0], + [1020.0, 225.0], + [1020.0, 40.0], + [-94.0, 40.0], + [-94.0, 380.0], + [-74.0, 380.0] ], "input": { "id": "alu_forward_A_mux", @@ -2589,14 +1648,8 @@ "type": "Wire", "id": "from reg_file:rt_value_out to data_forward_B_mux:in0", "pos": [ - [ - 651.0, - 315.0 - ], - [ - 780.0, - 315.0 - ] + [651.0, 315.0], + [780.0, 315.0] ], "input": { "id": "reg_file", @@ -2606,10 +1659,7 @@ { "type": "Mux", "id": "data_forward_B_mux", - "pos": [ - 800.0, - 325.0 - ], + "pos": [800.0, 325.0], "select": { "id": "data_forward_B", "field": "data_forward_out" @@ -2629,10 +1679,7 @@ { "type": "Mux", "id": "alu_forward_B_mux", - "pos": [ - 970.0, - 325.0 - ], + "pos": [970.0, 325.0], "select": { "id": "alu_forward_B", "field": "equals_forward_out" @@ -2653,14 +1700,8 @@ "type": "Wire", "id": "from alu_forward_B_mux:mux_out to operand_b_reg:r_in", "pos": [ - [ - 980.0, - 325.0 - ], - [ - 1090.0, - 325.0 - ] + [980.0, 325.0], + [1090.0, 325.0] ], "input": { "id": "alu_forward_B_mux", @@ -2670,10 +1711,7 @@ { "type": "BranchLogic", "id": "branch", - "pos": [ - 1040.0, - 275.0 - ], + "pos": [1040.0, 275.0], "op_in": { "id": "instruction_split", "field": "op_out" @@ -2699,46 +1737,23 @@ "type": "Wire", "id": "from branch:branch_out to mux_jump_merge:select", "pos": [ - [ - 1040.0, - 262.0 - ], - [ - 1040.0, - 60.0 - ], - [ - -64.0, - 60.0 - ], - [ - -64.0, - 340.0 - ] + [1040.0, 262.0], + [1040.0, 60.0], + [-64.0, 60.0], + [-64.0, 340.0] ], "input": { "id": "branch", "field": "branch_out" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] }, { "type": "Wire", "id": "from alu_forward_B_mux:mux_out to branch:branch_rt_value_id", "pos": [ - [ - 1010.0, - 325.0 - ], - [ - 1010.0, - 288.0 - ] + [1010.0, 325.0], + [1010.0, 288.0] ], "input": { "id": "alu_forward_B_mux", @@ -2749,22 +1764,10 @@ "type": "Wire", "id": "from control_unit_4:reg_write_enable to reg_file:write_enable_in", "pos": [ - [ - 2030.0, - 13.0 - ], - [ - 2030.0, - 670.0 - ], - [ - 600.0, - 670.0 - ], - [ - 600.0, - 406.0 - ] + [2030.0, 13.0], + [2030.0, 670.0], + [600.0, 670.0], + [600.0, 406.0] ], "input": { "id": "control_unit_4", @@ -2775,14 +1778,8 @@ "type": "Wire", "id": "from branch_shift:shift_left_const_out to pc_add_branch:b_in", "pos": [ - [ - 433.5, - 585.0 - ], - [ - 510.0, - 585.0 - ] + [433.5, 585.0], + [510.0, 585.0] ], "input": { "id": "branch_shift", @@ -2793,62 +1790,27 @@ "type": "Wire", "id": "from control_unit_1:extend_select to signzero_extend:signzero_ctrl_in", "pos": [ - [ - 480.0, - 13.5 - ], - [ - 480.0, - 80.0 - ], - [ - 340.0, - 80.0 - ], - [ - 340.0, - 440.0 - ], - [ - 400.0, - 440.0 - ], - [ - 400.0, - 454.0 - ] + [480.0, 13.5], + [480.0, 80.0], + [340.0, 80.0], + [340.0, 440.0], + [400.0, 440.0], + [400.0, 454.0] ], "input": { "id": "control_unit_1", "field": "extend_select" }, - "color_rgba": [ - 0, - 0, - 0, - 30 - ] + "color_rgba": [0, 0, 0, 30] }, { "type": "Wire", "id": "from data_forward_A_mux:mux_out to alu_forward_A_mux:in0", "pos": [ - [ - 810.0, - 225.0 - ], - [ - 860.0, - 225.0 - ], - [ - 860.0, - 215.0 - ], - [ - 950.0, - 215.0 - ] + [810.0, 225.0], + [860.0, 225.0], + [860.0, 215.0], + [950.0, 215.0] ], "input": { "id": "data_forward_A_mux", @@ -2859,22 +1821,10 @@ "type": "Wire", "id": "from instruction_split:rd_out to mux_write_addr:in1", "pos": [ - [ - 431.0, - 350.0 - ], - [ - 480.0, - 350.0 - ], - [ - 480.0, - 519.2 - ], - [ - 700.0, - 520.0 - ] + [431.0, 350.0], + [480.0, 350.0], + [480.0, 519.2], + [700.0, 520.0] ], "input": { "id": "instruction_split", @@ -2884,29 +1834,20 @@ { "type": "Constant", "id": "0x_1F", - "pos": [ - 670.0, - 540.0 - ], + "pos": [670.0, 540.0], "value": { "data": { "Data": 31 }, "fmt": { - "Hex": [ - "_32", - false - ] + "Hex": ["_32", false] } } }, { "type": "Mux", "id": "mux_write_addr", - "pos": [ - 720.0, - 520.0 - ], + "pos": [720.0, 520.0], "select": { "id": "control_unit_1", "field": "reg_dest" @@ -2931,14 +1872,8 @@ "type": "Wire", "id": "from mux_write_addr:mux_out to reg_addr_EX_reg:r_in", "pos": [ - [ - 730.0, - 520.0 - ], - [ - 1090.0, - 520.0 - ] + [730.0, 520.0], + [1090.0, 520.0] ], "input": { "id": "mux_write_addr", @@ -2949,14 +1884,8 @@ "type": "Wire", "id": "from 0x_1F:constant_out to mux_write_addr:in2", "pos": [ - [ - 670.0, - 540.0 - ], - [ - 700.0, - 540.0 - ] + [670.0, 540.0], + [700.0, 540.0] ], "input": { "id": "0x_1F", @@ -2967,22 +1896,10 @@ "type": "Wire", "id": "from data_forward_B_mux:mux_out to alu_forward_B_mux:in0", "pos": [ - [ - 810.0, - 325.0 - ], - [ - 860.0, - 325.0 - ], - [ - 860.0, - 315.0 - ], - [ - 950.0, - 315.0 - ] + [810.0, 325.0], + [860.0, 325.0], + [860.0, 315.0], + [950.0, 315.0] ], "input": { "id": "data_forward_B_mux", @@ -2993,26 +1910,11 @@ "type": "Wire", "id": "from reg_addr_MEM_reg:register_out to data_forward_A:a_in", "pos": [ - [ - 1500.0, - 520.0 - ], - [ - 1500.0, - 450.0 - ], - [ - 760.0, - 450.0 - ], - [ - 760.0, - 155.0 - ], - [ - 790.0, - 155.0 - ] + [1500.0, 520.0], + [1500.0, 450.0], + [760.0, 450.0], + [760.0, 155.0], + [790.0, 155.0] ], "input": { "id": "reg_addr_MEM_reg", @@ -3022,10 +1924,7 @@ { "type": "PassThrough", "id": "InMem_pass", - "pos": [ - 250.0, - 475.0 - ], + "pos": [250.0, 475.0], "input": { "id": "InMem_reg", "field": "register_out" @@ -3035,22 +1934,10 @@ "type": "Wire", "id": "from InMem_pass:pass_through_out to control_EX_reg:r_in", "pos": [ - [ - 250.0, - 475.0 - ], - [ - 280.0, - 475.0 - ], - [ - 280.0, - -40.0 - ], - [ - 1090.0, - -40.0 - ] + [250.0, 475.0], + [280.0, 475.0], + [280.0, -40.0], + [1090.0, -40.0] ], "input": { "id": "InMem_pass", @@ -3061,14 +1948,8 @@ "type": "Wire", "id": "from InMem_reg:register_out to instruction_split:instruction_in", "pos": [ - [ - 279.0, - 275.0 - ], - [ - 359.0, - 275.0 - ] + [279.0, 275.0], + [359.0, 275.0] ], "input": { "id": "InMem_reg", @@ -3078,18 +1959,12 @@ { "type": "PhysicalMem", "id": "phys_mem", - "pos": [ - 800.0, - 600.0 - ] + "pos": [800.0, 600.0] }, { "type": "Add", "id": "pc+4", - "pos": [ - 130.0, - 380.0 - ], + "pos": [130.0, 380.0], "a_in": { "id": "pc", "field": "register_out" @@ -3103,10 +1978,7 @@ { "type": "Mux", "id": "mux_jump_merge", - "pos": [ - -54.0, - 390.0 - ], + "pos": [-54.0, 390.0], "select": { "id": "branch", "field": "branch_out" @@ -3135,14 +2007,8 @@ "type": "Wire", "id": "from mux_jump_merge:mux_out to pc:r_in", "pos": [ - [ - -44.0, - 390.0 - ], - [ - -10.0, - 390.0 - ] + [-44.0, 390.0], + [-10.0, 390.0] ], "input": { "id": "mux_jump_merge", @@ -3153,30 +2019,12 @@ "type": "Wire", "id": "from pc+4:add_out to mux_jump_merge:in3", "pos": [ - [ - 150.0, - 380.0 - ], - [ - 170.0, - 380.0 - ], - [ - 170.0, - 455.0 - ], - [ - -80.0, - 455.0 - ], - [ - -80.0, - 420.0 - ], - [ - -74.0, - 420.0 - ] + [150.0, 380.0], + [170.0, 380.0], + [170.0, 455.0], + [-80.0, 455.0], + [-80.0, 420.0], + [-74.0, 420.0] ], "input": { "id": "pc+4", @@ -3187,14 +2035,8 @@ "type": "Wire", "id": "from pc+4:add_out to pc+4_reg:r_in", "pos": [ - [ - 150.0, - 380.0 - ], - [ - 230.0, - 380.0 - ] + [150.0, 380.0], + [230.0, 380.0] ], "input": { "id": "pc+4", @@ -3205,26 +2047,11 @@ "type": "Wire", "id": "from instruction_split:rt_out to reg_file:rt_address_in", "pos": [ - [ - 431.0, - 310.0 - ], - [ - 505.0, - 310.0 - ], - [ - 505.0, - 465.0 - ], - [ - 585.0, - 465.0 - ], - [ - 585.0, - 406.0 - ] + [431.0, 310.0], + [505.0, 310.0], + [505.0, 465.0], + [585.0, 465.0], + [585.0, 406.0] ], "input": { "id": "instruction_split", @@ -3235,14 +2062,8 @@ "type": "Wire", "id": "from control_MEM_reg:register_out to control_unit_3:control_unit_instr_in", "pos": [ - [ - 1480.0, - -40.0 - ], - [ - 1489.0, - 0.0 - ] + [1480.0, -40.0], + [1489.0, 0.0] ], "input": { "id": "control_MEM_reg", @@ -3252,10 +2073,7 @@ { "type": "PassThrough", "id": "operand_b_pass", - "pos": [ - 1140.0, - 325.0 - ], + "pos": [1140.0, 325.0], "input": { "id": "operand_b_reg", "field": "register_out" @@ -3265,18 +2083,9 @@ "type": "Wire", "id": "from operand_b_pass:pass_through_out to data_MEM_reg:r_in", "pos": [ - [ - 1140.0, - 325.0 - ], - [ - 1140.0, - 585.0 - ], - [ - 1460.0, - 585.0 - ] + [1140.0, 325.0], + [1140.0, 585.0], + [1460.0, 585.0] ], "input": { "id": "operand_b_pass", @@ -3287,26 +2096,11 @@ "type": "Wire", "id": "from instruction_split:rs_out to reg_file:rs_address_in", "pos": [ - [ - 431.0, - 196.0 - ], - [ - 440.0, - 196.0 - ], - [ - 440.0, - 120.0 - ], - [ - 585.0, - 120.0 - ], - [ - 585.0, - 144.0 - ] + [431.0, 196.0], + [440.0, 196.0], + [440.0, 120.0], + [585.0, 120.0], + [585.0, 144.0] ], "input": { "id": "instruction_split", @@ -3317,18 +2111,9 @@ "type": "Wire", "id": "from operand_b_reg:register_out to mux_source_b:in0", "pos": [ - [ - 1140.0, - 325.0 - ], - [ - 1140.0, - 305.0 - ], - [ - 1230.0, - 305.0 - ] + [1140.0, 325.0], + [1140.0, 305.0], + [1230.0, 305.0] ], "input": { "id": "operand_b_reg", @@ -3338,10 +2123,7 @@ { "type": "PassThrough", "id": "reg_addr_MEM_pass", - "pos": [ - 1520.0, - 520.0 - ], + "pos": [1520.0, 520.0], "input": { "id": "reg_addr_MEM_reg", "field": "register_out" @@ -3351,14 +2133,8 @@ "type": "Wire", "id": "from reg_addr_MEM_pass:pass_through_out to reg_addr_reg:r_in", "pos": [ - [ - 1520.0, - 520.0 - ], - [ - 1910.0, - 520.0 - ] + [1520.0, 520.0], + [1910.0, 520.0] ], "input": { "id": "reg_addr_MEM_pass", @@ -3369,14 +2145,8 @@ "type": "Wire", "id": "from alu_reg:register_out to data_mem:data_mem_address_in", "pos": [ - [ - 1630.0, - 250.0 - ], - [ - 1630.0, - 551.5 - ] + [1630.0, 250.0], + [1630.0, 551.5] ], "input": { "id": "alu_reg", @@ -3387,14 +2157,8 @@ "type": "Wire", "id": "from reg_file:rs_value_out to data_forward_A_mux:in0", "pos": [ - [ - 651.0, - 215.0 - ], - [ - 780.0, - 215.0 - ] + [651.0, 215.0], + [780.0, 215.0] ], "input": { "id": "reg_file", @@ -3405,14 +2169,8 @@ "type": "Wire", "id": "from reg_addr_EX_pass:pass_through_out to reg_addr_MEM_reg:r_in", "pos": [ - [ - 1165.0, - 520.0 - ], - [ - 1460.0, - 520.0 - ] + [1165.0, 520.0], + [1460.0, 520.0] ], "input": { "id": "reg_addr_EX_pass", @@ -3423,18 +2181,9 @@ "type": "Wire", "id": "from pc:register_out to pc+4:a_in", "pos": [ - [ - 30.0, - 390.0 - ], - [ - 30.0, - 360.0 - ], - [ - 110.0, - 360.0 - ] + [30.0, 390.0], + [30.0, 360.0], + [110.0, 360.0] ], "input": { "id": "pc", @@ -3445,14 +2194,8 @@ "type": "Wire", "id": "from control_MEM_reg:register_out to control_MEM_pass:pass_through_in", "pos": [ - [ - 1480.0, - -40.0 - ], - [ - 1510.0, - -40.0 - ] + [1480.0, -40.0], + [1510.0, -40.0] ], "input": { "id": "control_MEM_reg", @@ -3463,25 +2206,14 @@ "type": "Wire", "id": "from control_unit_3:mem_write_enable to data_mem:data_mem_write_enable", "pos": [ - [ - 1660.0, - 13.5 - ], - [ - 1660.0, - 551.5 - ] + [1660.0, 13.5], + [1660.0, 551.5] ], "input": { "id": "control_unit_3", "field": "mem_write_enable" }, - "color_rgba": [ - 0, - 0, - 0, - 40 - ] + "color_rgba": [0, 0, 0, 40] } ] -} \ No newline at end of file +} From eca26b1b081ab94ead9174bf3482d8f454d27890 Mon Sep 17 00:00:00 2001 From: pawdzi-7 Date: Sat, 12 Oct 2024 22:58:56 +0200 Subject: [PATCH 18/18] correct README --- README.md | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index e617736..50c6eeb 100644 --- a/README.md +++ b/README.md @@ -30,18 +30,11 @@ To load and run the created model (`.json`). cargo run -- -model .json ``` -Alternatively, you can run the `mips` example from the `mips` folder. +Alternatively, you can run a pipelined mips model from the mips-lib folder. ```shell -cd mips -cargo run --example mips -``` - -And consequently run the created model (`mips.json`). - -```shell -cd mips # if not already done -cargo run +cd mips-lib +cargo run --release ``` You can also run the examples correspondingly in `vscode`.